diff -pruN 2025.01-3/debian/changelog 2025.01-3ubuntu1/debian/changelog --- 2025.01-3/debian/changelog 2025-04-08 23:07:41.000000000 +0000 +++ 2025.01-3ubuntu1/debian/changelog 2025-05-09 09:52:48.000000000 +0000 @@ -1,3 +1,75 @@ +u-boot (2025.01-3ubuntu1) questing; urgency=medium + + * Merge from Debian unstable (LP: #2109512). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Fix nitrogen6q2g patch to build properly on armhf + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Enable commands for displaying and configuring the UEFI environment + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Add package for PolarFire SoC Icicle Kit + - Enable CONFIG_CMD_SBI by default to display SBI information on RISC-V + - d/p/riscv64/usb-reset.patch - Add a trivial quirk to fix USB MSD access + from U-boot + - d/u-boot-starfive.README.Debian - Add instructions for varying boot + sources on the VisionFive 2 + - Consider dpkg-buildflags when building host tools + - Enable FIT images + - d/rules: Unexport ELF_PACKAGE_METADATA to fix FTBFS on oracular + - Enable 'env erase' sub-command to enable reset of the boot environment + on RISC-V boards + - Set $fdtfile on MicroChip PolarFire + - d/p/riscv64/mpfs-icicle-kit_fdtfile.patch + - Update lintian-override syntax to include [brackets] + - d/*.lintian-overrides: Update syntax to include [brackets] + - d/p/riscv64/starfive: Add StarFive JH7110 compatibility patches + - d/p/use-cryptographically-safe-RNG.patch: Fix use of unsafe RNG in FIT + images + - Fix USB on Pine64 Star64 + - Add d/p/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in- + cdns3_drd_update_mode.patch + - Add d/p/riscv64/star64/0002-phy-starfive-Add-Starfive- + JH7110-USB-2.0-PHY-driver.patch + - Add d/p/riscv64/star64/0003-phy-starfive-Add-Starfive- + JH7110-PCIe-2.0-PHY-driver.patch + - Add d/p/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from- + wrapper-device-dt.patch + - Add d/p/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB- + driver.patch + - Add d/p/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB- + overcurrent-pin.patch + - Add d/p/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence- + USB-configu.patch + * Removed patches obsoleted/merged by upstream: + - d/targets.mk: + - Remove omap3_beagle target, removed from upstream + - Remove omap4_panda target, removed from upstream + - d/p/riscv64/efi_loader-create-common-function-to-free-struct-efi.patch: + remove unused patch + + -- Dave Jones Fri, 09 May 2025 10:52:48 +0100 + u-boot (2025.01-3) unstable; urgency=medium [ Marek Vasut ] @@ -46,6 +118,89 @@ u-boot (2025.01-1) unstable; urgency=med -- Vagrant Cascadian Fri, 07 Mar 2025 14:28:45 -0800 +u-boot (2025.01-1~0ubuntu2) plucky; urgency=medium + + * Fix USB on Pine64 Star64 (LP: #2100766) + - Add d/p/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch + - Add d/p/riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch + - Add d/p/riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch + - Add d/p/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch + - Add d/p/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch + - Add d/p/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch + - Add d/p/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch + + -- Heinrich Schuchardt Thu, 27 Feb 2025 18:08:21 +0100 + +u-boot (2025.01-1~0ubuntu1) plucky; urgency=medium + + * Merge from Debian unstable (LP: #2097726). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Fix nitrogen6q2g patch to build properly on armhf + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Enable commands for displaying and configuring the UEFI environment + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Add package for PolarFire SoC Icicle Kit + - Enable CONFIG_CMD_SBI by default to display SBI information on RISC-V + - d/p/riscv64/usb-reset.patch - Add a trivial quirk to fix USB MSD access + from U-boot + - d/u-boot-starfive.README.Debian - Add instructions for varying boot + sources on the VisionFive 2 + - Consider dpkg-buildflags when building host tools + - Enable FIT images + - d/rules: Unexport ELF_PACKAGE_METADATA to fix FTBFS on oracular + - Enable 'env erase' sub-command to enable reset of the boot environment + on RISC-V boards + - Set $fdtfile on MicroChip PolarFire + - d/p/riscv64/mpfs-icicle-kit_fdtfile.patch + * Removed patches obsoleted/merged by upstream: + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add support for the Milk-V Mars board to the u-boot-starfive package. + - Enable UEFI boot manager + - d/copyright Added missing license: + - GPL-2.0 WITH Linux-syscall-note exception + - d/p/use-cpp-flags.patch: Fixed cross-building issues by calling CPP with + cpp_flags instead of CFLAGS + - Fix card detection on the JH7110 SoC + - d/p/riscv64/synopsys-designware-cd-gpios.patch + - d/p/riscv64/starfive-mmc-card-detect.patch + - d/rules: Unexport ELF_PACKAGE_METADATA to fix FTBFS on oracular + - d/p/scripts-dtc-pylibfdt-libfdt.i_shipped-Use-SWIG_Appen.patch + * d/targets.mk: + - Remove omap3_beagle target, removed from upstream + - Remove omap4_panda target, removed from upstream + * d/*.lintian-overrides: Update syntax to include [brackets] + * d/copyright: Remove redundant patterns + * d/p/riscv64/starfive: Add StarFive JH7110 compatibility patches + * d/p/use-cryptographically-safe-RNG.patch: Fix use of unsafe RNG in FIT + images (LP: #2086515) + * d/p/riscv64/efi_loader-create-common-function-to-free-struct-efi.patch: + remove unused patch + + -- Dave Jones Mon, 10 Feb 2025 01:31:27 +0000 + u-boot (2024.01+dfsg-6) unstable; urgency=medium * Use system dtc from device-tree-compiler (Closes: #1091125) @@ -57,6 +212,81 @@ u-boot (2024.01+dfsg-6) unstable; urgenc -- Vagrant Cascadian Thu, 02 Jan 2025 13:47:07 -0800 +u-boot (2024.01+dfsg-5ubuntu3) plucky; urgency=medium + + * Set $fdtfile on MicroChip PolarFire (LP: #2095400) + - d/p/riscv64/mpfs-icicle-kit_fdtfile.patch + - d/p/scripts-dtc-pylibfdt-libfdt.i_shipped-Use-SWIG_Appen.patch + + -- Heinrich Schuchardt Tue, 21 Jan 2025 13:01:42 +0100 + +u-boot (2024.01+dfsg-5ubuntu2) oracular; urgency=medium + + * Enable FIT images (LP: #2054092) + * Fix card detection on the JH7110 SoC (LP: #2069410) + - d/p/riscv64/synopsys-designware-cd-gpios.patch + - d/p/riscv64/starfive-mmc-card-detect.patch + * d/rules: Unexport ELF_PACKAGE_METADATA to fix FTBFS on oracular + * Enable 'env erase' sub-command to enable reset of the boot environment on + RISC-V boards (LP: #2080386) + + -- Dave Jones Tue, 06 Aug 2024 09:41:28 +0100 + +u-boot (2024.01+dfsg-5ubuntu1) oracular; urgency=medium + + * Merge from Debian unstable (LP: #2075352). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Fix nitrogen6q2g patch to build properly on armhf + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Enable commands for displaying and configuring the UEFI environment + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Add package for PolarFire SoC Icicle Kit + - Enable CONFIG_CMD_SBI by default to display SBI information on RISC-V + - d/p/riscv64/usb-reset.patch - Add a trivial quirk to fix USB MSD access + from U-boot + - d/u-boot-starfive.README.Debian - Add instructions for varying boot + sources on the VisionFive 2 + - Consider dpkg-buildflags when building host tools + * Removed patches obsoleted/merged by upstream: + - Remove the MIPS targets as the mips cross-compiler is currently + uninstallable in Ubuntu + - d/p/riscv64/000[12]-efi-loader*.patch - Fix a boot-time crash on the + VisionFive2 when a USB stick is present + - Fix device-tree corruption on RISC-V boards + - d/p/dbcn_serial_use_data_section.patch + - Added -mno-omit-leaf-frame-pointer to list of flags excluded from build + to fix FTBFS of u-boot-qemu + * Refreshed patches to remove fuzz: + - d/p/riscv64/0003-board-starfive-support-Milk-V-Mars-board.patch + * d/copyright Added missing license: + - GPL-2.0 WITH Linux-syscall-note exception + * d/p/use-cpp-flags.patch: Fixed cross-building issues by calling CPP with + cpp_flags instead of CFLAGS + + -- Dave Jones Thu, 01 Aug 2024 10:30:29 +0100 + u-boot (2024.01+dfsg-5) unstable; urgency=medium * Upload to unstable. @@ -111,6 +341,97 @@ u-boot (2024.01+dfsg-2) unstable; urgenc -- Vagrant Cascadian Tue, 19 Mar 2024 16:27:45 -0700 +u-boot (2024.01+dfsg-1ubuntu6) oracular; urgency=medium + + * Consider dpkg-buildflags when building host tools (LP: #2071846) + + -- Heinrich Schuchardt Mon, 01 Jul 2024 17:26:46 +0200 + +u-boot (2024.01+dfsg-1ubuntu5) noble; urgency=medium + + * Enable UEFI boot manager (LP: #2060212) + * Update 0003-board-starfive-support-Milk-V-Mars-board.patch + + -- Heinrich Schuchardt Thu, 04 Apr 2024 18:22:45 +0200 + +u-boot (2024.01+dfsg-1ubuntu4) noble; urgency=medium + + * No-change rebuild for CVE-2024-3094 + + -- William Grant Mon, 01 Apr 2024 19:26:24 +1100 + +u-boot (2024.01+dfsg-1ubuntu3) noble; urgency=medium + + Add support for the Milk-V Mars board to the u-boot-starfive package. + (LP: #2055939) + + -- Heinrich Schuchardt Mon, 04 Mar 2024 16:58:44 +0100 + +u-boot (2024.01+dfsg-1ubuntu2) noble; urgency=medium + + * Fix device-tree corruption on RISC-V boards (LP: #2054091) + + d/p/dbcn_serial_use_data_section.patch + + -- Heinrich Schuchardt Wed, 21 Feb 2024 01:58:55 +0100 + +u-boot (2024.01+dfsg-1ubuntu1) noble; urgency=medium + + [ Dave Jones ] + * Merge from Debian unstable (LP: #2051940). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Fix nitrogen6q2g patch to build properly on armhf + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Enable commands for displaying and configuring the UEFI environment + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Remove the MIPS targets as the mips cross-compiler is currently + uninstallable in Ubuntu + - Add package for PolarFire SoC Icicle Kit + - Enable CONFIG_CMD_SBI by default to display SBI information on RISC-V + * Removed patches obsoleted/merged by upstream: + - d/p/riscv64/sync-polarfire-dts-with-linux-[123].patch: assign MAC + address on PolarFire + - d/p/riscv64/multi-usb-msd-[12].patch: fix non-unique device paths on + machines with multiple USB mass-storage devices attached + * Refreshed patches to apply cleanly without fuzz: + - d/p/rpi-config-tweaks.patch + - d/p/rpi-maxargs.patch + * Added -mno-omit-leaf-frame-pointer to list of flags excluded from build + to fix FTBFS of u-boot-qemu + + [ Heinrich Schuchardt ] + * d/p/riscv64/000[12]-efi-loader*.patch - Fix a boot-time crash on the + VisionFive2 when a USB stick is present + * d/p/riscv64/usb-reset.patch - Add a trivial quirk to fix USB MSD access + from U-boot + * d/u-boot-starfive.README.Debian - Add instructions for varying boot + sources on the VisionFive 2 + + -- Dave Jones Thu, 01 Feb 2024 13:52:26 +0000 + u-boot (2024.01+dfsg-1) unstable; urgency=medium * New upstream version. @@ -167,6 +488,77 @@ u-boot (2024.01~rc6+dfsg-1) experimental -- Vagrant Cascadian Fri, 05 Jan 2024 14:17:59 -0800 +u-boot (2023.07+dfsg-1ubuntu2) mantic; urgency=medium + + * Fix FTBFS by excluding -fcf-protection from CFLAGS; this flag isn't valid + when cross-building (LP: #2034536) + + -- Dave Jones Thu, 21 Sep 2023 12:00:38 +0100 + +u-boot (2023.07+dfsg-1ubuntu1) mantic; urgency=medium + + [ Dave Jones] + * Merge from Debian unstable (LP: #2027789). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Fix nitrogen6q2g patch to build properly on armhf + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Enable commands for displaying and configuring the UEFI environment + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Remove the MIPS targets as the mips cross-compiler is currently + uninstallable in Ubuntu + - Add package for PolarFire SoC Icicle Kit + * Removed patches obsoleted/merged by upstream: + - SECURITY UPDATE: unchecked length field in DFU implementation + - debian/patches/CVE-2022-2347.patch: fix the unchecked length field in + drivers/usb/gadget/f_dfu.c. + - CVE-2022-2347 + - Fix probing of virtio devices + d/p/virtio-pci-fix-bug-of-virtio_pci_map_capability.patch + - Enable reset via SBI on PolarFire Icicle Kit + d/p/riscv64/enable-reset-via-SBI-on-PolarFire-Icicle-Kit.patch + - Adjust u-boot-microchip on PolarFire Icicle Kit for the changed memory + layout of the HSS 2022.10 firmware + * Refreshed patches: + - d/p/rpi-config-tweaks.patch + - d/p/ubuntu-nitrogen6q2g-config-tweaks.patch + - d/p/rpi-cm4-sdhci.patch + - d/p/rpi-8gb-pci.patch + - d/p/riscv64/mpfs-icicle-reserve-the-top-of-memory-for-the-.patch + + [ Heinrich Schuchardt ] + * d/p/riscv64/enable-sbi.patch: Enable CONFIG_CMD_SBI by default to display + SBI information on RISC-V + * d/p/riscv64/sync-polarfire-dts-with-linux-[123].patch: assign MAC address + on PolarFire + * d/p/riscv64/multi-usb-msd-[12].patch: fix non-unique device paths on + machines with multiple USB mass-storage devices attached + + -- Dave Jones Fri, 14 Jul 2023 15:52:36 +0100 + u-boot (2023.07+dfsg-1) unstable; urgency=medium * New upstream release. @@ -311,6 +703,62 @@ u-boot (2022.10+dfsg-2) unstable; urgenc -- Vagrant Cascadian Fri, 23 Dec 2022 15:18:44 -0800 +u-boot (2022.10+dfsg-1ubuntu1) lunar; urgency=medium + + * Merge from Debian unstable (LP: #1999039). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Re-added target for nitrogen6q2 u-boot binary (missed in prior merge) + - Enable commands for displaying and configuring the UEFI environment + - Fix nitrogen6q2g patch to build properly on armhf + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + - Remove the MIPS targets as the mips cross-compiler is currently + uninstallable in Ubuntu + - Add package for PolarFire SoC Icicle Kit + - Adjust u-boot-microchip on PolarFire Icicle Kit for the changed memory + layout of the HSS 2022.10 firmware + - Enable reset via SBI on PolarFire Icicle Kit d/p/riscv64/enable-reset- + via-SBI-on-PolarFire-Icicle-Kit.patch + - Fix probing of virtio devices d/p/virtio-pci-fix-bug-of- + virtio_pci_map_capability.patch + - SECURITY UPDATE: unchecked length field in DFU implementation + - debian/patches/CVE-2022-2347.patch: fix the unchecked length field in + drivers/usb/gadget/f_dfu.c. + - CVE-2022-2347 + * Removed patches obsoleted/merged by upstream: + - System reset via the SRST extension in the SBI should be the default. + * Refreshed patches: + - d/p/rpi-config-tweaks.patch + - d/p/rpi-cm4-sdhci.patch + - d/p/rpi-8gb-pci.patch + - d/p/rpi-maxargs.patch + * d/p/ubuntu-nitrogen6q2g-config-tweaks.patch: enable SCSI which is now + required for ENV_IS_IN_FAT + + -- Dave Jones Wed, 07 Dec 2022 12:37:17 +0000 + u-boot (2022.10+dfsg-1) unstable; urgency=medium * New upstream release. (Closes: #1019004) @@ -336,6 +784,97 @@ u-boot (2022.10~rc2+dfsg-1) experimental -- Vagrant Cascadian Fri, 12 Aug 2022 07:18:56 -0700 +u-boot (2022.07+dfsg-1ubuntu7) lunar; urgency=medium + + * SECURITY UPDATE: unchecked length field in DFU implementation + - debian/patches/CVE-2022-2347.patch: fix the unchecked length field in + drivers/usb/gadget/f_dfu.c. + - CVE-2022-2347 + + -- Marc Deslauriers Tue, 06 Dec 2022 09:21:18 -0500 + +u-boot (2022.07+dfsg-1ubuntu6) lunar; urgency=medium + + * Fix probing of virtio devices (LP: #1996285) + d/p/virtio-pci-fix-bug-of-virtio_pci_map_capability.patch + + -- Heinrich Schuchardt Fri, 11 Nov 2022 16:14:13 +0100 + +u-boot (2022.07+dfsg-1ubuntu5) lunar; urgency=medium + + * Rebuild against updated OpenSBI + Fixes emulation of fence.tso on Allwinner D1 (LP: #1995860) + * Enable reset via SBI on PolarFire Icicle Kit (LP: #1995932) + d/p/riscv64/enable-reset-via-SBI-on-PolarFire-Icicle-Kit.patch + + -- Heinrich Schuchardt Mon, 07 Nov 2022 13:25:23 +0100 + +u-boot (2022.07+dfsg-1ubuntu4) kinetic; urgency=medium + + * Adjust u-boot-microchip on PolarFire Icicle Kit for the changed memory + layout of the HSS 2022.10 firmware (LP: #1992776) + + -- Heinrich Schuchardt Thu, 13 Oct 2022 12:12:03 +0200 + +u-boot (2022.07+dfsg-1ubuntu3) kinetic; urgency=medium + + * Add package for PolarFire SoC Icicle Kit (LP: #1987505) + * System reset via the SRST extension in the SBI should be the default. + + -- Heinrich Schuchardt Wed, 24 Aug 2022 10:12:10 +0200 + +u-boot (2022.07+dfsg-1ubuntu2) kinetic; urgency=medium + + * Remove the MIPS targets as the mips cross-compiler is currently + uninstallable in Ubuntu + + -- Dave Jones Thu, 01 Sep 2022 16:51:48 +0100 + +u-boot (2022.07+dfsg-1ubuntu1) kinetic; urgency=medium + + * Merge from Debian unstable (LP: #1980017). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Re-added target for nitrogen6q2 u-boot binary (missed in prior merge) + - Enable commands for displaying and configuring the UEFI environment + - Fix nitrogen6q2g patch to build properly on armhf + - In u-boot-sifive.postinst support partition names Loader1, Loader2 as + the installer image uses these. + * Removed patches obsoleted/merged by upstream: + - Enabling booting via SCSI and USB on SiFive Unmatched + - d/patches: Add SiFive Unmatched PCIe fix + - In u-boot-sifive.postinst support partition names Loader1, Loader2 + as the installer image uses these. + - d/p/efi-loader-copy-guid.patch: Copy GUID in InstallProtocolInterface to + avoid crash with systemd-boot + - d/p/efi-part-list.patch: Permit listing of non-contiguous partitions in + GPT tables + - Fix Unleashed name typo that resulted in an unbootable image due to + missing OpenSBI. + + -- Dave Jones Tue, 23 Aug 2022 11:57:13 +0100 + u-boot (2022.07+dfsg-1) unstable; urgency=medium [ Dave Jones ] @@ -424,6 +963,86 @@ u-boot (2022.04~rc2+dfsg-1) experimental -- Vagrant Cascadian Wed, 23 Feb 2022 17:10:03 -0800 +u-boot (2022.01+dfsg-2ubuntu3) kinetic; urgency=medium + + * Enabling booting via SCSI and USB on SiFive Unmatched + (LP: #1968174) + * In u-boot-sifive.postinst support partition names Loader1, Loader2 + as the installer image uses these. + + -- Heinrich Schuchardt Sun, 15 May 2022 08:13:41 +0200 + +u-boot (2022.01+dfsg-2ubuntu2) jammy; urgency=medium + + * d/patches: Add SiFive Unmatched PCIe fix (LP: #1965321) + + -- Alexandre Ghiti Fri, 25 Mar 2022 11:15:18 +0100 + +u-boot (2022.01+dfsg-2ubuntu1) jammy; urgency=medium + + [ Dave Jones ] + * Merge from Debian unstable (LP: #1964365). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Removed d/u-boot-rpi.postinst. The task of copying the u-boot binaries + to the boot partition is now performed by flash-kernel + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. Maybe this should move to flash- + kernel, and update SPI too. + - Provide compat symlinks for old unleashed & unmatched platform names + - sifive boards: re-enable back USE_PREBOOT< it used to be there in + 2021.01 releases, and I suspect it affects unleashed bootability. + - In postinst support Unmatched model name without A00 suffix, as used by + meta-sifive kernels and may be contributed upstream in the future. + - Fix Unleashed name typo that resulted in an unbootable image due to + missing OpenSBI. + * Removed obsolete patches/changes: + - fix cmd_sysconfig in qemu + - set default fdtfile names for sifive boards + - Drop unleashed hunk from + riscv64/qemu-riscv64_smode-sifive-fu540-fix-extlinux-define-.patch, as + the same preboot is specified in unleashed board include. + - Cherrypick patch from Heinrich Schuchardt (xypron) to fix failure to + boot on Unmatched. + - Drop 75efe7dc996ddb9835590b1a8970f19b5c4b1ade.patch included upstream. + - Remove unreferenced fe01f41d57b79d9ca94604503a25e55175744d42.patch, + included as riscv64/0013-riscv-sifive-Set-default-fdtfile-names.patch. + - Build against opensbi with reboot support on Unmatched + - Add missing trailing \n to arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig. + Fixes a rare (but reliable) FTBFS from check-config.sh. In the original + case on LP armhf, mach-imx/Kconfig sorted immediately after + cmd_stm32prog/Kconfig, causing lines to run together and the sed to not + match the "config HAS_CAAM" line, causing the dh_imx6 defconfig to + appear invalid. + - Import meta-sifive patch series. + - Refreshed rk3399 patches for new release + * Refreshed patches for new release + * Re-added target for nitrogen6q2 u-boot binary (missed in prior merge) + * Fixed nitrogen6q2g patch to build properly on armhf + + [ Heinrich Schuchardt ] + * d/p/efivars-commands.patch: Enable commands for displaying and configuring + the UEFI environment + * d/p/efi-part-list.patch: Permit listing of non-contiguous partitions in + GPT tables + * d/p/efi-loader-copy-guid.patch: Copy GUID in InstallProtocolInterface to + avoid crash with systemd-boot + + -- Dave Jones Thu, 10 Mar 2022 16:54:01 +0000 + u-boot (2022.01+dfsg-2) unstable; urgency=medium * debian/patches: Fix building qemu-ppce500 target with binutils @@ -512,6 +1131,109 @@ u-boot (2021.07+dfsg-1) experimental; ur -- Vagrant Cascadian Sat, 24 Jul 2021 18:35:37 -0700 +u-boot (2021.07+dfsg-0ubuntu10) jammy; urgency=medium + + * No-change rebuild against openssl3 + + -- Simon Chopin Fri, 03 Dec 2021 14:16:56 +0000 + +u-boot (2021.07+dfsg-0ubuntu9) jammy; urgency=medium + + * No change rebuild with new opensbi snapshot. + + -- Dimitri John Ledkov Tue, 02 Nov 2021 12:41:21 +0000 + +u-boot (2021.07+dfsg-0ubuntu8) impish; urgency=medium + + * Add missing trailing \n to arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig. + Fixes a rare (but reliable) FTBFS from check-config.sh. In the original + case on LP armhf, mach-imx/Kconfig sorted immediately after + cmd_stm32prog/Kconfig, causing lines to run together and the sed to not + match the "config HAS_CAAM" line, causing the dh_imx6 defconfig to appear + invalid. + + -- William Grant Wed, 13 Oct 2021 20:05:23 +1100 + +u-boot (2021.07+dfsg-0ubuntu7) impish; urgency=medium + + * Fix Unleashed name typo that resulted in an unbootable image due to + missing OpenSBI (LP: #1946913). + + -- William Grant Wed, 13 Oct 2021 14:59:55 +1100 + +u-boot (2021.07+dfsg-0ubuntu6) impish; urgency=medium + + * Build against opensbi with reboot support on Unmatched + * In postinst support Unmatched model name without A00 suffix, as used + by meta-sifive kernels and may be contributed upstream in the future. + + -- Dimitri John Ledkov Wed, 25 Aug 2021 17:22:24 +0100 + +u-boot (2021.07+dfsg-0ubuntu4) impish; urgency=medium + + * sifive boards: re-enable back USE_PREBOOT< it used to be there in + 2021.01 releases, and I suspect it affects unleashed bootability. + * control: add crust-firmware build-dep, it is now available in the + archive. + * Remove unreferenced fe01f41d57b79d9ca94604503a25e55175744d42.patch, + included as riscv64/0013-riscv-sifive-Set-default-fdtfile-names.patch. + * Skip removed/incorrect 0ubuntu3 upload. + + -- Dimitri John Ledkov Wed, 04 Aug 2021 11:18:25 +0100 + +u-boot (2021.07+dfsg-0ubuntu2) impish; urgency=medium + + * Import meta-sifive patch series. + + -- Dimitri John Ledkov Fri, 23 Jul 2021 17:14:09 +0100 + +u-boot (2021.07+dfsg-0ubuntu1) impish; urgency=medium + + * New upstream release. + - Drop 75efe7dc996ddb9835590b1a8970f19b5c4b1ade.patch included upstream. + + -- Dimitri John Ledkov Fri, 23 Jul 2021 12:45:26 +0100 + +u-boot (2021.07~rc4+dfsg-1ubuntu2) impish; urgency=medium + + * Cherrypick patch from Heinrich Schuchardt (xypron) to fix failure to + boot on Unmatched. LP: #1937246 + + -- Dimitri John Ledkov Thu, 22 Jul 2021 12:33:49 +0100 + +u-boot (2021.07~rc4+dfsg-1ubuntu1) impish; urgency=medium + + * Merge from Debian Experimental, remaining changes: + - Implement u-boot-sifive.postinst to upgrade u-boot in + loader1/loader2 partitions upon package upgrades. LP: #1936370 Maybe + this should move to flash-kernel, and update SPI too. + - Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + * Cherrypick upstream patches to: + - fix cmd_sysconfig in qemu + - set default fdtfile names for sifive boards + * Provide compat symlinks for old unleashed & unmatched platform names + * Drop unleashed hunk from + riscv64/qemu-riscv64_smode-sifive-fu540-fix-extlinux-define-.patch, as + the same preboot is specified in unleashed board include. + * Drop crust-firmware build-dep, until it is available in Ubuntu, + currently in impish NEW queue. + + -- Dimitri John Ledkov Tue, 20 Jul 2021 12:30:01 +0100 + u-boot (2021.07~rc4+dfsg-1) experimental; urgency=medium [ Nicolas Boulenguez ] @@ -603,6 +1325,55 @@ u-boot (2021.01+dfsg-5) unstable; urgenc -- Vagrant Cascadian Sat, 22 May 2021 21:32:45 -0700 +u-boot (2021.01+dfsg-4ubuntu3) impish; urgency=medium + + * Implement u-boot-sifive.postinst to upgrade u-boot in loader1/loader2 + partitions upon package upgrades. LP: #1936370 + + -- Dimitri John Ledkov Thu, 15 Jul 2021 13:01:50 +0100 + +u-boot (2021.01+dfsg-4ubuntu2) impish; urgency=medium + + * Revert '* debian/rules: Ensure debugging symbols are enabled.' as it + breaks riscv64 booting. + + -- Dimitri John Ledkov Wed, 02 Jun 2021 16:52:03 +0100 + +u-boot (2021.01+dfsg-4ubuntu1) impish; urgency=medium + + * Merge from Debian unstable (LP: #1928777). Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + - Import meta-sifive u-boot patches. + - Enable sifive_hifive_unmatched_fu740 target. + - Build-depend on opensbi with fu740 errata fix. + - Set default FDT files for the sifive boards. + - Set USE_PREBOOT on unmatched board too (just like unleashed & qemu), + otherwise u-boot's fdtfile from itb is not used (i.e. when extlinux.conf + does not specify fdtdir). LP: #1923162 + - Unapply unmatched patches, whilst building unleashed platform. Fixes + failure to boot from sd-card on Unleashed. LP: #1924761 + - Skip processing fdtdir on qemu-riscv64_smode target, as it crashes the + riscv qemu VM. LP: #1925267 LP: #1923162 + - sifive-unleashed-default-fdt-files.patch: split into unleashed & + unmatched separate patches, for ease of upstreaming to meta-sifive and + u-boot upstreams. Also this ensures that unleashed target is built with + fdtfile= set, as unleashed target unapplies lots of patches. + + -- Dave Jones Tue, 18 May 2021 11:07:17 +0100 + u-boot (2021.01+dfsg-4) unstable; urgency=medium [ Arnaud Ferraris ] @@ -618,6 +1389,83 @@ u-boot (2021.01+dfsg-4) unstable; urgenc -- Vagrant Cascadian Fri, 12 Mar 2021 15:00:43 -0800 +u-boot (2021.01+dfsg-3ubuntu9) hirsute; urgency=medium + + * sifive-unleashed-default-fdt-files.patch: split into unleashed & + unmatched separate patches, for ease of upstreaming to meta-sifive and + u-boot upstreams. Also this ensures that unleashed target is built + with fdtfile= set, as unleashed target unapplies lots of patches. + + -- Dimitri John Ledkov Wed, 21 Apr 2021 18:05:00 +0100 + +u-boot (2021.01+dfsg-3ubuntu8) hirsute; urgency=medium + + * Skip processing fdtdir on qemu-riscv64_smode target, as it crashes the + riscv qemu VM. LP: #1925267 LP: #1923162 + + -- Dimitri John Ledkov Wed, 21 Apr 2021 01:25:13 +0100 + +u-boot (2021.01+dfsg-3ubuntu7) hirsute; urgency=medium + + * Unapply unmatched patches, whilst building unleashed platform. Fixes + failure to boot from sd-card on Unleashed. LP: #1924761 + + -- Dimitri John Ledkov Fri, 16 Apr 2021 14:07:49 +0100 + +u-boot (2021.01+dfsg-3ubuntu6) hirsute; urgency=medium + + * Set USE_PREBOOT on unmatched board too (just like unleashed & qemu), + otherwise u-boot's fdtfile from itb is not used (i.e. when + extlinux.conf does not specify fdtdir). LP: #1923162 + + -- Dimitri John Ledkov Tue, 13 Apr 2021 14:52:32 +0100 + +u-boot (2021.01+dfsg-3ubuntu5) hirsute; urgency=medium + + * Set default FDT files for the sifive boards. + + -- Dimitri John Ledkov Tue, 16 Mar 2021 18:03:09 +0000 + +u-boot (2021.01+dfsg-3ubuntu4) hirsute; urgency=medium + + * Update patch for unmatched. + + -- Dimitri John Ledkov Mon, 15 Mar 2021 21:26:35 +0000 + +u-boot (2021.01+dfsg-3ubuntu3) hirsute; urgency=medium + + * Update patches for unmatched. + + -- Dimitri John Ledkov Mon, 15 Mar 2021 16:29:23 +0000 + +u-boot (2021.01+dfsg-3ubuntu2) hirsute; urgency=medium + + * Import meta-sifive u-boot patches. + * Enable sifive_hifive_unmatched_fu740 target. + * Build-depend on opensbi with fu740 errata fix. + + -- Dimitri John Ledkov Wed, 10 Mar 2021 12:27:57 +0000 + +u-boot (2021.01+dfsg-3ubuntu1) hirsute; urgency=medium + + * Merge from Debian unstable. Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + + -- Dave Jones Wed, 10 Mar 2021 12:02:04 +0000 + u-boot (2021.01+dfsg-3) unstable; urgency=medium [ Domenico Andreoli ] @@ -650,6 +1498,33 @@ u-boot (2021.01+dfsg-3) unstable; urgenc -- Vagrant Cascadian Mon, 01 Mar 2021 00:00:18 -0800 +u-boot (2021.01+dfsg-2ubuntu1) hirsute; urgency=medium + + * Merge from Debian unstable. Remaining changes: + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - Enable FIT signing support + - Limit key names to keys within the keydir. + - Enable Ubuntu support for the Nitrogen6x board + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + - Enable u-boot spl for unleashed. + - Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + - Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support + - Add d/p/rpi-maxargs.patch for new Core 18 boot-env + * Dropped changes, included in Debian: + - Enable FIT signing support + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + * Dropped changes, no longer needed: + - Added d/u-boot-rpi.postinst to install u-boot binaries + (previously unnoted) + + -- Dave Jones Thu, 18 Feb 2021 18:15:04 +0000 + u-boot (2021.01+dfsg-2) unstable; urgency=medium * debian/patches: Disable USE_PREBOOT on rockpro64 and pinebook-pro to @@ -765,6 +1640,63 @@ u-boot (2020.10+dfsg-2) unstable; urgenc -- Vagrant Cascadian Mon, 04 Jan 2021 19:59:11 -0800 +u-boot (2020.10+dfsg-1ubuntu6) hirsute; urgency=medium + + * Add d/p/rpi-8gb-pci.patch for Pi400 and Pi4-8Gb support (LP: #1906552) + * Add d/p/rpi-cm4-sdhci.patch for CM4 eMMC support + * Add d/p/rpi-maxargs.patch for new Core 18 boot-env (LP: #1910094) + * Remove redundant d/targets entries + + -- Dave Jones Thu, 10 Dec 2020 23:44:09 +0000 + +u-boot (2020.10+dfsg-1ubuntu5) hirsute; urgency=medium + + * Use flat binary rather than ELF OpenSBI; U-Boot SPL doesn't support ELF. + * Switch back to generic OpenSBI, as modern versions detect the platform. + + -- William Grant Mon, 21 Dec 2020 10:32:59 +1100 + +u-boot (2020.10+dfsg-1ubuntu4) hirsute; urgency=medium + + * Use the right opensbi fw_dynamic for fu540. + + -- Dimitri John Ledkov Tue, 08 Dec 2020 09:04:00 +0000 + +u-boot (2020.10+dfsg-1ubuntu3) hirsute; urgency=medium + + * Enable u-boot spl for unleashed. LP: #1905274 + + -- Dimitri John Ledkov Mon, 23 Nov 2020 12:51:03 +0000 + +u-boot (2020.10+dfsg-1ubuntu2) hirsute; urgency=medium + + * No-change rebuild to build with python3.9 as default. + + -- Matthias Klose Thu, 19 Nov 2020 18:38:58 +0100 + +u-boot (2020.10+dfsg-1ubuntu1) hirsute; urgency=low + + * Merge from Debian unstable. Remaining changes: + - Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + + * Removed obsolete patches/changes: + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + + -- Dave Jones Tue, 06 Oct 2020 03:18:18 +0000 + u-boot (2020.10+dfsg-1) unstable; urgency=medium * New upstream release. @@ -850,6 +1782,53 @@ u-boot (2020.07~rc2+dfsg-1) experimental -- Vagrant Cascadian Mon, 18 May 2020 17:16:07 -0700 +u-boot (2020.04+dfsg-2ubuntu1) groovy; urgency=medium + + * Merge with 2020.04+dfsg-2 from Debian unstable. Remaining changes: + - Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + - Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + - d/p/rpi-config-tweaks.patch: Configuration adjustments to the RPi + configs + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + - d/p/rpi-board-dt.patch: use the board's device-tree instead of an + embedded one + + * Removed obsolete patches/changes: + - Handle differing root partition labels during migration + - Add script to migrate old boot configurations to split, selective style + - Don't attempt config migration when /boot/firmware is a chroot + - Use vc4-fkms-v3d overlay on all models of Raspberry Pi + - Do not include the vc4-fkms-v3d overlay; this breaks book on the 3A+ + - Ensure boot.scr is from recent flash-kernel + - d/p/rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + - Remove redundant d/p/rpi-import-mkknlimg.patch + - d/p/ubuntu-nitrogen6q2g-temporary-config-fixup.patch: + Fix bad CRC issue. The env size and redundant environment config + variables have not yet been migrated to Kconfig, so setting them in + _defconfig has no effect. Set those manually. + + * Removed patches obsoleted/merged by upstream: + - Use python2 for the build. + - Added d/p/python2.patch to fix-up remaining scripts still using bare + "python" + - d/p/am57xx/omap5_distro_bootcmd + - Correct odroid README paths + - Add d/p/rpi4.patch to support Raspberry Pi 4 boot + - Avoid device-tree memory fixup on Raspberry Pi 4; this allows access to + the all the RAM on models with more than 1Gb + - Add missing build dependency on arm/arm64 + + -- Dave Jones Sat, 16 May 2020 01:02:53 +0000 + u-boot (2020.04+dfsg-2) unstable; urgency=medium * debian/patches: @@ -995,6 +1974,68 @@ u-boot (2019.10~rc4+dfsg-1) experimental -- Vagrant Cascadian Tue, 24 Sep 2019 01:03:23 -0700 +u-boot (2019.07+dfsg-1ubuntu6) focal; urgency=medium + + [ Ethan Hsieh ] + * d/p/ubuntu-nitrogen6q2g-temporary-config-fixup.patch: + Fix bad CRC issue. The env size and redundant environment config variables + have not yet been migrated to Kconfig, so setting them in _defconfig has + no effect. Set those manually. + + -- Łukasz 'sil2100' Zemczak Tue, 11 Feb 2020 11:43:57 +0100 + +u-boot (2019.07+dfsg-1ubuntu5) focal; urgency=medium + + [ Matthias Klose ] + * Use python2 for the build. + + [ Dave Jones ] + * Added d/p/python2.patch to fix-up remaining scripts still using bare + "python" + + -- Dave Jones Fri, 24 Jan 2020 11:29:15 +0000 + +u-boot (2019.07+dfsg-1ubuntu4) focal; urgency=medium + + * Do not include the vc4-fkms-v3d overlay; this breaks book on the 3A+ + (LP: #1848247) + * Handle differing root partition labels during migration + * Ensure boot.scr is from recent flash-kernel + + -- Dave Jones Fri, 17 Jan 2020 13:31:35 +0000 + +u-boot (2019.07+dfsg-1ubuntu3) eoan; urgency=medium + + * Avoid device-tree memory fixup on Raspberry Pi 4; this allows access to + the all the RAM on models with more than 1Gb (LP: #1847500) + + -- Dave Jones Sat, 12 Oct 2019 01:02:29 +0100 + +u-boot (2019.07+dfsg-1ubuntu2) eoan; urgency=medium + + * Don't attempt config migration when /boot/firmware is a chroot + * Use vc4-fkms-v3d overlay on all models of Raspberry Pi + + -- Dave Jones Wed, 09 Oct 2019 12:35:06 +0100 + +u-boot (2019.07+dfsg-1ubuntu1) eoan; urgency=medium + + * New upstream release to support Pi 4 boot (LP: #1846329) + * Removed patches applied upstream: + - d/p/dreamplug/Commit-ARM-CPU-arm926ejs-Consolidate-cache-routines-.patch + - d/p/mkimage/0001-fdt-Fix-mkimage-list-to-try-every-header-type.patch + - d/p/sunxi/teres-i.patch + * Updated patch: + - d/p/am57xx/omap5_distro_bootcmd + * Add missing build dependency on arm/arm64 + * Correct odroid README paths + * Add d/p/rpi4.patch to support Raspberry Pi 4 boot + * Remove redundant d/p/rpi-import-mkknlimg.patch + * Add script to migrate old boot configurations to split, selective style + * Use the board's device-tree instead of an embedded one + + -- Dave Jones Tue, 23 Jul 2019 10:02:04 +0000 + u-boot (2019.07+dfsg-1) experimental; urgency=medium * New upstream release. @@ -1101,6 +2142,48 @@ u-boot (2019.07~rc1+dfsg-1) experimental -- Vagrant Cascadian Fri, 03 May 2019 16:58:13 -0700 +u-boot (2019.04+dfsg-2ubuntu3) eoan; urgency=medium + + [ Shrirang Bagul ] + * Enable Ubuntu support for the Nitrogen6x board (LP: #1838064) + - Add d/p/ubuntu-nitrogen6q2g-config-tweaks.patch to tweak the + nitrogen6q2g configs to better fit our Ubuntu usage. + - Start building the nitrogen6x2g target for u-boot. + + -- Łukasz 'sil2100' Zemczak Tue, 03 Sep 2019 11:39:53 +0200 + +u-boot (2019.04+dfsg-2ubuntu2) eoan; urgency=low + + * Enable FIT signing support (LP: #1831942) + - Enable CONFIG_FIT_SIGNATURE so we can sign FIT images. + - Add libssl-dev to Build-Depends: to enable crypto functionality. + - Limit key names to keys within the keydir. + + -- Andy Whitcroft Mon, 10 Jun 2019 15:44:35 +0100 + +u-boot (2019.04+dfsg-2ubuntu1) eoan; urgency=medium + + * Merge with 2019.04+dfsg-2 from Debian experimental. Remaining changes: + - d/p/rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + - d/p/rpi2-rpi3-config-tweaks.patch: basing on the earlier + rpi2-config-tweaks.patch, make configuration adjustments to the rpi2 and + rpi3 configs. + - d/u-boot-rpi.postinst: support the fact that we now ship multiple uboot + binaries for multiple Pi platforms in one package. Try to determine + which device we're running on and use the right binary during + upgrade/installation. * debian/patches: + - d/p/lzo-to-lzno.patch: use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and in + the next releases ideally we should follow what Debian does. + - debian/control: Add missing dependency on binutils (for strings) + (LP: #1814930) + - debian/patches: Refreshed patches. + * Obsoleted; applied upstream: + - Removed d/p/odroid-xu3/bootdelay + + -- Dave Jones Mon, 03 Jun 2019 14:41:23 +0000 + u-boot (2019.04+dfsg-2) experimental; urgency=medium [ Vagrant Cascadian ] @@ -1301,6 +2384,29 @@ u-boot (2018.07+dfsg-1) experimental; ur -- Vagrant Cascadian Mon, 09 Jul 2018 13:34:06 -0700 +u-boot (2018.07~rc3+dfsg1-0ubuntu2) disco; urgency=medium + + * d/control: Add missing dependency on binutils (for strings) (LP: #1814930) + + -- Dave Jones Wed, 06 Feb 2019 16:40:22 +0000 + +u-boot (2018.07~rc3+dfsg1-0ubuntu1) disco; urgency=medium + + * New interim upstream release. + - We pull in an rc version because that's the u-boot version we use in + our current core18 images and we want to provide 'feature parity'. + * debian/control: + - Added missing build-deps bison and flex. + * debian/patches: + - Refresh am57xx/omap5_distro_bootcmd. + - Refreshed patches. + - Removed odroid-xu3/bootdelay which was applied upstream. + - Add lzo-to-lzno.patch to use gzip instead of lzo compression for FIT + images as lzop in Ubuntu is in universe. This should be temporary and + in the next releases ideally we should follow what Debian does. + + -- Dave Jones Fri, 11 Jan 2019 16:43:27 +0000 + u-boot (2018.07~rc2+dfsg-1) experimental; urgency=medium * New upstream release candidate: @@ -1362,6 +2468,26 @@ u-boot (2018.05~rc2+dfsg-1) experimental -- Vagrant Cascadian Tue, 17 Apr 2018 16:05:55 -0700 +u-boot (2018.03+dfsg1-2ubuntu2) disco; urgency=medium + + * debian/u-boot-rpi.postinst: + - Support the fact that we now ship multiple uboot binaries for multiple + Pi platforms in one package. Try to determine which device we're running + on and use the right binary during upgrade/installation. + + -- Łukasz 'sil2100' Zemczak Thu, 29 Nov 2018 01:16:07 +0100 + +u-boot (2018.03+dfsg1-2ubuntu1) cosmic; urgency=low + + * Merge from Debian unstable. Remaining changes: + - rpi-import-mkknlimg.patch import tools/mkknlimg from Xenial/raspi2 - + scripts/mkknlimg @ 83a3ebb + * debian/patches/rpi2-rpi3-config-tweaks.patch: basing on the earlier + rpi2-config-tweaks.patch, make configuration adjustments to the rpi2 and + rpi3 configs. + + -- Łukasz 'sil2100' Zemczak Fri, 27 Apr 2018 12:38:24 +0100 + u-boot (2018.03+dfsg1-2) unstable; urgency=medium [ Riku Voipio ] @@ -1838,6 +2964,26 @@ u-boot (2016.05~rc3+dfsg1-1) experimenta -- Vagrant Cascadian Sat, 30 Apr 2016 18:53:04 -0700 +u-boot (2016.03+dfsg1-6ubuntu2) zesty; urgency=medium + + * From upstream u-boot: (LP: #1636838) + - debian/patches/rpi-import-mkknlimg.patch: import tools/mkknlimg from + Xenial/raspi2 - scripts/mkknlimg @ 83a3ebb + - debian/u-boot-rpi.postinst: pass u-boot.bin through mkknlimg before + installing it as /boot/firmware/uboot.bin + - debian/patches/serial-pl01x-Add-support-for-devices-with-the-rate-p.patch: + Skip serial clock initialization when it's done by the firmware. + + -- Paolo Pisati Wed, 09 Nov 2016 17:09:29 +0200 + +u-boot (2016.03+dfsg1-6ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Wed, 06 Jul 2016 17:30:44 -0700 + u-boot (2016.03+dfsg1-6) unstable; urgency=medium [ Vagrant Cascadian ] @@ -1859,6 +3005,14 @@ u-boot (2016.03+dfsg1-6) unstable; urgen -- Vagrant Cascadian Tue, 28 Jun 2016 09:38:27 +0200 +u-boot (2016.03+dfsg1-5ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Fri, 10 Jun 2016 21:46:33 -0700 + u-boot (2016.03+dfsg1-5) unstable; urgency=medium [ Vagrant Cascadian ] @@ -1884,6 +3038,14 @@ u-boot (2016.03+dfsg1-5) unstable; urgen -- Vagrant Cascadian Sun, 29 May 2016 14:29:59 -0700 +u-boot (2016.03+dfsg1-4ubuntu1) yakkety; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Tue, 26 Apr 2016 21:06:04 -0700 + u-boot (2016.03+dfsg1-4) unstable; urgency=medium * Add patch to fix detected ram size on Firefly boards by reverting @@ -1942,6 +3104,14 @@ u-boot (2016.03~rc2+dfsg1-1) experimenta -- Vagrant Cascadian Tue, 16 Feb 2016 15:01:48 -0800 +u-boot (2016.01+dfsg1-2ubuntu1) xenial; urgency=low + + * Merge from Debian unstable. Remaining changes: + - debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Thu, 11 Feb 2016 21:55:38 -0800 + u-boot (2016.01+dfsg1-2) unstable; urgency=medium * u-boot-omap: @@ -1955,6 +3125,13 @@ u-boot (2016.01+dfsg1-2) unstable; urgen -- Vagrant Cascadian Mon, 08 Feb 2016 20:14:04 -0800 +u-boot (2016.01+dfsg1-1ubuntu1) xenial; urgency=medium + + * debian/patches/rpi2-config-tweaks.patch: configuration adjustments + to the RPi2 config. + + -- Steve Langasek Tue, 02 Feb 2016 11:43:50 -0800 + u-boot (2016.01+dfsg1-1) unstable; urgency=medium * u-boot-sunxi: Enable orangepi_plus target. @@ -3017,3 +4194,4 @@ u-boot (2010.03-1) unstable; urgency=low * Initial packaging. closes: #583605. -- Clint Adams Fri, 28 May 2010 16:20:39 -0400 + diff -pruN 2025.01-3/debian/control 2025.01-3ubuntu1/debian/control --- 2025.01-3/debian/control 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/control 2025-05-09 09:52:48.000000000 +0000 @@ -1,7 +1,8 @@ Source: u-boot Section: admin Priority: optional -Maintainer: Vagrant Cascadian +Maintainer: Ubuntu Developers +XSBC-Original-Maintainer: Vagrant Cascadian Uploaders: Loïc Minier , Clint Adams Build-Depends: bc, @@ -21,6 +22,7 @@ Build-Depends-Arch: arm-trusted-firmware (>= 2.9~) [arm64], crust-firmware (>= 0.3-2~) [arm64], gcc-arm-linux-gnueabihf [arm64], + hart-payload-generator [riscv64], libfdt-dev:native [arm64], libgnutls28-dev:native [arm64 armel armhf], libncurses-dev, @@ -248,6 +250,23 @@ Description: A boot loader for exynos sy Included platforms: ${u-boot-exynos-binaries:platforms} +Package: u-boot-microchip +Architecture: riscv64 +Multi-Arch: same +Depends: ${misc:Depends} +Built-Using: ${u-boot-microchip:Built-Using} +Description: A boot loader for Microchip systems + Das U-Boot is a cross-platform bootloader for embedded systems, + used as the default boot loader by several board vendors. It is + intended to be easy to port and to debug, and runs on many + supported architectures, including PPC, ARM, MIPS, x86, m68k, + NIOS, and Microblaze. + . + This package includes boot loaders for various Microchip platforms. + . + Included platforms: + ${u-boot-microchip:platforms} + Package: u-boot-mvebu Architecture: arm64 Multi-Arch: same @@ -287,6 +306,7 @@ Package: u-boot-rpi Architecture: armel armhf arm64 Multi-Arch: same Depends: ${misc:Depends} +Breaks: flash-kernel (<< 3.104) Description: A boot loader for Raspberry PI systems Das U-Boot is a cross-platform bootloader for embedded systems, used as the default boot loader by several board vendors. It is diff -pruN 2025.01-3/debian/copyright 2025.01-3ubuntu1/debian/copyright --- 2025.01-3/debian/copyright 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/copyright 2025-05-09 09:50:55.000000000 +0000 @@ -18839,6 +18839,38 @@ License: bzip2-1.0.6 OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +License: GPL-2.0 WITH Linux-syscall-note exception + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + version 2 as published by the Free Software Foundation. + . + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + . + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + 02110-1301 USA + . + On Debian systems, the full text of the GNU General Public + License version 2 can be found in the file + `/usr/share/common-licenses/GPL-2'. + . + NOTE! This copyright does *not* cover user programs that use kernel + services by normal system calls - this is merely considered normal use + of the kernel, and does *not* fall under the heading of "derived work". + Also note that the GPL below is copyrighted by the Free Software + Foundation, but the instance of code that it refers to (the Linux + kernel) is copyrighted by me and others who actually wrote it. + . + Also note that the only valid version of the GPL as far as the kernel + is concerned is _this_ particular version of the license (ie v2, not + v2.2 or v3.x or whatever), unless explicitly otherwise stated. + . + Linus Torvalds + License: bzlib-BSD-4 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions diff -pruN 2025.01-3/debian/microchip_mpfs_icicle.yaml 2025.01-3ubuntu1/debian/microchip_mpfs_icicle.yaml --- 2025.01-3/debian/microchip_mpfs_icicle.yaml 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/microchip_mpfs_icicle.yaml 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,4 @@ +set-name: 'PolarFire-SoC-HSS::U-Boot' +hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'} +payloads: + debian/build/microchip_mpfs_icicle/u-boot.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_s} diff -pruN 2025.01-3/debian/patches/efivars-commands.patch 2025.01-3ubuntu1/debian/patches/efivars-commands.patch --- 2025.01-3/debian/patches/efivars-commands.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/efivars-commands.patch 2025-05-09 09:50:53.000000000 +0000 @@ -0,0 +1,31 @@ +Enable commands for display and manipulation of UEFI boot options by +default. + +Signed-off-by: Heinrich Schuchardt +--- + cmd/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 02c298fdbe..cfc4563f59 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -502,6 +502,7 @@ config CMD_ENV_FLAGS + config CMD_NVEDIT_EFI + bool "env [set|print] -e - set/print UEFI variables" + depends on EFI_LOADER ++ default y + imply HEXDUMP + help + UEFI variables are encoded as some form of U-Boot variables. +@@ -1757,6 +1758,7 @@ config CMD_CLS + config CMD_EFIDEBUG + bool "efidebug - display/configure UEFI environment" + depends on EFI_LOADER ++ default y + select EFI_DEVICE_PATH_TO_TEXT + help + Enable the 'efidebug' command which provides a subset of UEFI +-- +2.33.1 + diff -pruN 2025.01-3/debian/patches/riscv64/enable-sbi.patch 2025.01-3ubuntu1/debian/patches/riscv64/enable-sbi.patch --- 2025.01-3/debian/patches/riscv64/enable-sbi.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/enable-sbi.patch 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,14 @@ +Author: Dave Jones +Forwarded: no +Description: Display SBI information on RISC-V boot + +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -206,6 +206,7 @@ config SPL_CMD_TLV_EEPROM + + config CMD_SBI + bool "sbi" ++ default y + depends on RISCV_SMODE && SBI_V02 + help + Display information about the SBI implementation. diff -pruN 2025.01-3/debian/patches/riscv64/erase-env.patch 2025.01-3ubuntu1/debian/patches/riscv64/erase-env.patch --- 2025.01-3/debian/patches/riscv64/erase-env.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/erase-env.patch 2025-05-09 09:50:55.000000000 +0000 @@ -0,0 +1,17 @@ +Author: Heinrich Schuchardt +Forwarded: not-needed +Description: Enable the env erase sub-command on RISC-V arch + This should not be forwarded as it's Ubuntu's configuration decision to enable + the env erase sub-command by default on the RISC-V architecture. Upstream + wishes to keep the default configuration minimal + +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -612,6 +612,7 @@ config CMD_SAVEENV + config CMD_ERASEENV + bool "eraseenv" + depends on CMD_SAVEENV ++ default y if RISCV + help + Erase environment variables from the compiled-in persistent + storage. diff -pruN 2025.01-3/debian/patches/riscv64/mpfs-icicle-kit_fdtfile.patch 2025.01-3ubuntu1/debian/patches/riscv64/mpfs-icicle-kit_fdtfile.patch --- 2025.01-3/debian/patches/riscv64/mpfs-icicle-kit_fdtfile.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/mpfs-icicle-kit_fdtfile.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,20 @@ +--- a/configs/microchip_mpfs_icicle_defconfig ++++ b/configs/microchip_mpfs_icicle_defconfig +@@ -12,6 +12,7 @@ CONFIG_ARCH_RV64I=y + CONFIG_RISCV_SMODE=y + CONFIG_FIT=y + CONFIG_DISTRO_DEFAULTS=y ++CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" + CONFIG_SYS_CBSIZE=256 + CONFIG_SYS_PBSIZE=282 + CONFIG_DISPLAY_CPUINFO=y +--- a/include/configs/microchip_mpfs_icicle.h ++++ b/include/configs/microchip_mpfs_icicle.h +@@ -26,6 +26,7 @@ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + + #endif /* __CONFIG_H */ diff -pruN 2025.01-3/debian/patches/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch --- 2025.01-3/debian/patches/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,60 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:05 +0800 +Subject: [PATCH 1/7] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode() + +USB PHY maybe need to set PHY mode in different USB +dr mode. So translate USB PHY mode to generic PHY mode +and call generic_phy_set_mode(). + +Signed-off-by: Minda Chen +Reviewed-by: Marek Vasut +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-2-minda.chen@starfivetech.com/ +--- + drivers/usb/cdns3/drd.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c +index 47874fec29e..cbb13342343 100644 +--- a/drivers/usb/cdns3/drd.c ++++ b/drivers/usb/cdns3/drd.c +@@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns) + int cdns3_drd_update_mode(struct cdns3 *cdns) + { + int ret = 0; ++ int mode; + + switch (cdns->dr_mode) { + case USB_DR_MODE_PERIPHERAL: ++ mode = PHY_MODE_USB_DEVICE; + ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL); + break; + case USB_DR_MODE_HOST: ++ mode = PHY_MODE_USB_HOST; + ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST); + break; + case USB_DR_MODE_OTG: ++ mode = PHY_MODE_USB_OTG; + ret = cdns3_init_otg_mode(cdns); + break; + default: +@@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns) + return -EINVAL; + } + ++ ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0); ++ if (ret) { ++ dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret); ++ return ret; ++ } ++ ++ ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0); ++ if (ret) ++ dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret); ++ + return ret; + } + +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch --- 2025.01-3/debian/patches/riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,262 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:06 +0800 +Subject: [PATCH 2/7] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver + +Add Starfive JH7110 USB 2.0 PHY driver, which is generic +PHY driver. + +Signed-off-by: Minda Chen +Reviewed-by: Roger Quadros +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-3-minda.chen@starfivetech.com/ +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/starfive/Kconfig | 14 ++ + drivers/phy/starfive/Makefile | 6 + + drivers/phy/starfive/phy-jh7110-usb-syscon.h | 9 ++ + drivers/phy/starfive/phy-jh7110-usb2.c | 162 +++++++++++++++++++ + 6 files changed, 193 insertions(+) + create mode 100644 drivers/phy/starfive/Kconfig + create mode 100644 drivers/phy/starfive/Makefile + create mode 100644 drivers/phy/starfive/phy-jh7110-usb-syscon.h + create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index e12347e8a03..f940648fe58 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -309,5 +309,6 @@ source "drivers/phy/cadence/Kconfig" + source "drivers/phy/ti/Kconfig" + source "drivers/phy/qcom/Kconfig" + source "drivers/phy/renesas/Kconfig" ++source "drivers/phy/starfive/Kconfig" + + endmenu +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index c35f9294dd9..ce4ea28b299 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -44,3 +44,4 @@ obj-y += cadence/ + obj-y += ti/ + obj-y += qcom/ + obj-y += renesas/ ++obj-y += starfive/ +diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig +new file mode 100644 +index 00000000000..a7cf0a55dff +--- /dev/null ++++ b/drivers/phy/starfive/Kconfig +@@ -0,0 +1,14 @@ ++# ++# PHY drivers for Starfive platforms ++# ++ ++menu "Starfive PHY driver" ++ ++config PHY_STARFIVE_JH7110_USB2 ++ bool "Starfive JH7110 USB 2.0 PHY driver" ++ depends on PHY ++ help ++ Enable this to support the Starfive JH7110 USB 2.0 PHY. ++ Generic PHY driver JH7110 USB 2.0. ++ ++endmenu +diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile +new file mode 100644 +index 00000000000..a405a75e34c +--- /dev/null ++++ b/drivers/phy/starfive/Makefile +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2023 Starfive ++# ++ ++obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o +diff --git a/drivers/phy/starfive/phy-jh7110-usb-syscon.h b/drivers/phy/starfive/phy-jh7110-usb-syscon.h +new file mode 100644 +index 00000000000..0eb66f0d859 +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-usb-syscon.h +@@ -0,0 +1,9 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef PHY_JH7110_USB_SYSCON_H_ ++#define PHY_JH7110_USB_SYSCON_H_ ++ ++#define SYSCON_USB_PDRSTN_REG_OFFSET 0x18 ++#define USB_PDRSTN_SPLIT_BIT 17 ++ ++#endif +diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c +new file mode 100644 +index 00000000000..1a28381e0df +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-usb2.c +@@ -0,0 +1,162 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 USB 2.0 PHY driver ++ * ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "phy-jh7110-usb-syscon.h" ++ ++#define USB_LS_KEEPALIVE_OFF 0x4 ++#define USB_LS_KEEPALIVE_ENABLE BIT(4) ++#define USB_PHY_CLK_RATE 125000000 ++ ++struct jh7110_usb2_phy { ++ struct phy *phy; ++ struct regmap *sys_syscon; ++ void __iomem *regs; ++ struct clk *usb_125m_clk; ++ struct clk *app_125m; ++ struct regmap_field *usb_split; ++ enum phy_mode mode; ++}; ++ ++static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) ++{ ++ /* Host mode enable the LS speed keep-alive signal */ ++ clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF, ++ USB_LS_KEEPALIVE_ENABLE, ++ set ? USB_LS_KEEPALIVE_ENABLE : 0); ++} ++ ++static int usb2_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct udevice *dev = phy->dev; ++ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); ++ ++ if (mode == usb2_phy->mode) ++ return 0; ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ dev_dbg(dev, "Changing PHY to %d\n", mode); ++ usb2_phy->mode = mode; ++ usb2_set_ls_keepalive(usb2_phy, (mode != PHY_MODE_USB_DEVICE)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* set default split usb 2.0 only mode */ ++ regmap_field_write(usb2_phy->usb_split, true); ++ ++ return 0; ++} ++ ++static int jh7110_usb2_phy_init(struct phy *phy) ++{ ++ struct udevice *dev = phy->dev; ++ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); ++ int ret; ++ ++ ret = clk_set_rate(usb2_phy->usb_125m_clk, USB_PHY_CLK_RATE); ++ if (ret < 0) { ++ dev_err(dev, "Failed to set 125m clock\n"); ++ return ret; ++ } ++ ++ return clk_prepare_enable(usb2_phy->app_125m); ++} ++ ++static int jh7110_usb2_phy_exit(struct phy *phy) ++{ ++ struct udevice *dev = phy->dev; ++ struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev); ++ ++ clk_disable_unprepare(usb2_phy->app_125m); ++ ++ return 0; ++} ++ ++struct phy_ops jh7110_usb2_phy_ops = { ++ .init = jh7110_usb2_phy_init, ++ .exit = jh7110_usb2_phy_exit, ++ .set_mode = usb2_phy_set_mode, ++}; ++ ++int jh7110_usb2_phy_probe(struct udevice *dev) ++{ ++ struct jh7110_usb2_phy *phy = dev_get_priv(dev); ++ ofnode node; ++ struct reg_field usb_split; ++ int ret; ++ ++ phy->regs = dev_read_addr_ptr(dev); ++ if (!phy->regs) ++ return -EINVAL; ++ ++ node = ofnode_by_compatible(ofnode_null(), "starfive,jh7110-sys-syscon"); ++ if (!ofnode_valid(node)) { ++ dev_err(dev, "Can't get syscon dev node\n"); ++ return -ENODEV; ++ } ++ ++ phy->sys_syscon = syscon_node_to_regmap(node); ++ if (IS_ERR(phy->sys_syscon)) { ++ dev_err(dev, "Can't get syscon regmap: %d\n", ret); ++ return PTR_ERR(phy->sys_syscon); ++ } ++ ++ usb_split.reg = SYSCON_USB_PDRSTN_REG_OFFSET; ++ usb_split.lsb = USB_PDRSTN_SPLIT_BIT; ++ usb_split.msb = USB_PDRSTN_SPLIT_BIT; ++ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split); ++ if (IS_ERR(phy->usb_split)) { ++ dev_err(dev, "USB split field init failed\n"); ++ return PTR_ERR(phy->usb_split); ++ } ++ ++ phy->usb_125m_clk = devm_clk_get(dev, "125m"); ++ if (IS_ERR(phy->usb_125m_clk)) { ++ dev_err(dev, "Failed to get 125m clock\n"); ++ return PTR_ERR(phy->usb_125m_clk); ++ } ++ ++ phy->app_125m = devm_clk_get(dev, "app_125m"); ++ if (IS_ERR(phy->app_125m)) { ++ dev_err(dev, "Failed to get app 125m clock\n"); ++ return PTR_ERR(phy->app_125m); ++ } ++ ++ return 0; ++} ++ ++static const struct udevice_id jh7110_usb2_phy[] = { ++ { .compatible = "starfive,jh7110-usb-phy"}, ++ {}, ++}; ++ ++U_BOOT_DRIVER(jh7110_usb2_phy) = { ++ .name = "jh7110_usb2_phy", ++ .id = UCLASS_PHY, ++ .of_match = jh7110_usb2_phy, ++ .probe = jh7110_usb2_phy_probe, ++ .ops = &jh7110_usb2_phy_ops, ++ .priv_auto = sizeof(struct jh7110_usb2_phy), ++}; +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch --- 2025.01-3/debian/patches/riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,293 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:07 +0800 +Subject: [PATCH 3/7] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver + +Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic +PHY driver and can be used as USB 3.0 driver. + +Signed-off-by: Minda Chen +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-4-minda.chen@starfivetech.com/ +--- + drivers/phy/starfive/Kconfig | 7 + + drivers/phy/starfive/Makefile | 1 + + drivers/phy/starfive/phy-jh7110-pcie.c | 239 +++++++++++++++++++++++++ + 3 files changed, 247 insertions(+) + create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c + +diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig +index a7cf0a55dff..d11338ed484 100644 +--- a/drivers/phy/starfive/Kconfig ++++ b/drivers/phy/starfive/Kconfig +@@ -4,6 +4,13 @@ + + menu "Starfive PHY driver" + ++config PHY_STARFIVE_JH7110_PCIE ++ bool "Starfive JH7110 PCIe 2.0 PHY driver" ++ depends on PHY ++ help ++ Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY. ++ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0. ++ + config PHY_STARFIVE_JH7110_USB2 + bool "Starfive JH7110 USB 2.0 PHY driver" + depends on PHY +diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile +index a405a75e34c..82f25aa21b7 100644 +--- a/drivers/phy/starfive/Makefile ++++ b/drivers/phy/starfive/Makefile +@@ -3,4 +3,5 @@ + # Copyright (C) 2023 Starfive + # + ++obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o + obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o +diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c +new file mode 100644 +index 00000000000..ecb04bdedfa +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-pcie.c +@@ -0,0 +1,239 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 PCIe 2.0 PHY driver ++ * ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "phy-jh7110-usb-syscon.h" ++ ++#define PCIE_KVCO_LEVEL_OFF 0x28 ++#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c ++#define PCIE_USB3_PHY_SS_MODE BIT(4) ++#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 ++#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 ++#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc ++ ++#define PCIE_USB3_PHY_MODE 0x1 ++#define PCIE_BUS_WIDTH 0x2 ++#define PCIE_USB3_PHY_ENABLE 0x1 ++#define PCIE_USB3_PHY_SPLIT 0x1 ++ ++struct jh7110_pcie_phy { ++ struct phy *phy; ++ struct regmap *stg_syscon; ++ struct regmap *sys_syscon; ++ void __iomem *regs; ++ struct regmap_field *phy_mode; ++ struct regmap_field *bus_width; ++ struct regmap_field *usb3_phy_en; ++ struct regmap_field *usb_split; ++ enum phy_mode mode; ++}; ++ ++static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode) ++{ ++ unsigned int phy_mode, width, usb3_phy, ss_mode, split; ++ ++ /* default is PCIe mode */ ++ if (!data->stg_syscon || !data->sys_syscon) { ++ if (usb_mode) { ++ dev_err(data->phy->dev, "doesn't support USB3 mode\n"); ++ return -EINVAL; ++ } ++ return 0; ++ } ++ ++ if (usb_mode) { ++ phy_mode = PCIE_USB3_PHY_MODE; ++ width = 0; ++ usb3_phy = PCIE_USB3_PHY_ENABLE; ++ ss_mode = PCIE_USB3_PHY_SS_MODE; ++ split = 0; ++ } else { ++ phy_mode = 0; ++ width = PCIE_BUS_WIDTH; ++ usb3_phy = 0; ++ ss_mode = 0; ++ split = PCIE_USB3_PHY_SPLIT; ++ } ++ ++ regmap_field_write(data->phy_mode, phy_mode); ++ regmap_field_write(data->bus_width, width); ++ regmap_field_write(data->usb3_phy_en, usb3_phy); ++ clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF, ++ PCIE_USB3_PHY_SS_MODE, ss_mode); ++ regmap_field_write(data->usb_split, split); ++ ++ return 0; ++} ++ ++static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) ++{ ++ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ ++ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); ++ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); ++} ++ ++static int jh7110_pcie_phy_set_mode(struct phy *phy, ++ enum phy_mode mode, int submode) ++{ ++ struct udevice *dev = phy->dev; ++ struct jh7110_pcie_phy *pcie_phy = dev_get_priv(dev); ++ int ret; ++ ++ if (mode == pcie_phy->mode) ++ return 0; ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ ret = phy_pcie_mode_set(pcie_phy, 1); ++ if (ret) ++ return ret; ++ break; ++ case PHY_MODE_PCIE: ++ phy_pcie_mode_set(pcie_phy, 0); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ dev_dbg(phy->dev, "Changing PHY mode to %d\n", mode); ++ pcie_phy->mode = mode; ++ ++ return 0; ++} ++ ++static const struct phy_ops jh7110_pcie_phy_ops = { ++ .set_mode = jh7110_pcie_phy_set_mode, ++}; ++ ++static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3) ++{ ++ struct jh7110_pcie_phy *phy = dev_get_priv(dev); ++ struct reg_field phy_mode = REG_FIELD(mode, 20, 21); ++ struct reg_field bus_width = REG_FIELD(usb3, 2, 3); ++ struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4); ++ ++ phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode); ++ if (IS_ERR(phy->phy_mode)) { ++ dev_err(dev, "PHY mode reg field init failed\n"); ++ return PTR_ERR(phy->phy_mode); ++ } ++ ++ phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width); ++ if (IS_ERR(phy->bus_width)) { ++ dev_err(dev, "PHY bus width reg field init failed\n"); ++ return PTR_ERR(phy->bus_width); ++ } ++ ++ phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en); ++ if (IS_ERR(phy->usb3_phy_en)) { ++ dev_err(dev, "USB3 PHY enable field init failed\n"); ++ return PTR_ERR(phy->bus_width); ++ } ++ ++ return 0; ++} ++ ++static int phy_sys_regfield_init(struct udevice *dev, int split) ++{ ++ struct jh7110_pcie_phy *phy = dev_get_priv(dev); ++ struct reg_field usb_split = REG_FIELD(split, USB_PDRSTN_SPLIT_BIT, USB_PDRSTN_SPLIT_BIT); ++ ++ phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split); ++ if (IS_ERR(phy->usb_split)) { ++ dev_err(dev, "USB split field init failed\n"); ++ return PTR_ERR(phy->usb_split); ++ } ++ ++ return 0; ++} ++ ++static int starfive_pcie_phy_get_syscon(struct udevice *dev) ++{ ++ struct jh7110_pcie_phy *phy = dev_get_priv(dev); ++ struct ofnode_phandle_args sys_phandle, stg_phandle; ++ int ret; ++ ++ /* get corresponding syscon phandle */ ++ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 0, 0, ++ &sys_phandle); ++ ++ if (ret < 0) { ++ dev_err(dev, "Can't get sys cfg phandle: %d\n", ret); ++ return ret; ++ } ++ ++ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0, ++ &stg_phandle); ++ ++ if (ret < 0) { ++ dev_err(dev, "Can't get stg cfg phandle: %d\n", ret); ++ return ret; ++ } ++ ++ phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node); ++ /* get syscon register offset */ ++ if (!IS_ERR(phy->sys_syscon)) { ++ ret = phy_sys_regfield_init(dev, SYSCON_USB_PDRSTN_REG_OFFSET); ++ if (ret) ++ return ret; ++ } else { ++ phy->sys_syscon = NULL; ++ } ++ ++ phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node); ++ if (!IS_ERR(phy->stg_syscon)) ++ return phy_stg_regfield_init(dev, stg_phandle.args[0], ++ stg_phandle.args[1]); ++ else ++ phy->stg_syscon = NULL; ++ ++ return 0; ++} ++ ++int jh7110_pcie_phy_probe(struct udevice *dev) ++{ ++ struct jh7110_pcie_phy *phy = dev_get_priv(dev); ++ int rc; ++ ++ phy->regs = dev_read_addr_ptr(dev); ++ if (!phy->regs) ++ return -EINVAL; ++ ++ rc = starfive_pcie_phy_get_syscon(dev); ++ if (rc) ++ return rc; ++ ++ phy_kvco_gain_set(phy); ++ ++ return 0; ++} ++ ++static const struct udevice_id jh7110_pcie_phy[] = { ++ { .compatible = "starfive,jh7110-pcie-phy"}, ++ {}, ++}; ++ ++U_BOOT_DRIVER(jh7110_pcie_phy) = { ++ .name = "jh7110_pcie_phy", ++ .id = UCLASS_PHY, ++ .of_match = jh7110_pcie_phy, ++ .probe = jh7110_pcie_phy_probe, ++ .ops = &jh7110_pcie_phy_ops, ++ .priv_auto = sizeof(struct jh7110_pcie_phy), ++}; +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch --- 2025.01-3/debian/patches/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,48 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:08 +0800 +Subject: [PATCH 4/7] usb: cdns: starfive: Get dr mode from wrapper device dts + node + +Cdns core driver also get dr mode from wrapper devcie dts node +to make it is same with Starfive cdns USB Linux kernel driver, +Starfive 7110 OF_UPSTREAM is enabled + +Signed-off-by: Minda Chen +Reviewed-by: Marek Vasut +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-5-minda.chen@starfivetech.com/ +--- + drivers/phy/starfive/phy-jh7110-pcie.c | 2 +- + drivers/usb/cdns3/core.c | 3 +++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c +index ecb04bdedfa..a30582821d9 100644 +--- a/drivers/phy/starfive/phy-jh7110-pcie.c ++++ b/drivers/phy/starfive/phy-jh7110-pcie.c +@@ -170,7 +170,7 @@ static int starfive_pcie_phy_get_syscon(struct udevice *dev) + int ret; + + /* get corresponding syscon phandle */ +- ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 0, 0, ++ ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0, + &sys_phandle); + + if (ret < 0) { +diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c +index 4cfd38ec245..4434dc15bec 100644 +--- a/drivers/usb/cdns3/core.c ++++ b/drivers/usb/cdns3/core.c +@@ -410,6 +410,9 @@ int cdns3_bind(struct udevice *parent) + name = ofnode_get_name(node); + dr_mode = usb_get_dr_mode(node); + ++ if (dr_mode == USB_DR_MODE_UNKNOWN) ++ dr_mode = usb_get_dr_mode(dev_ofnode(parent)); ++ + switch (dr_mode) { + #if defined(CONFIG_SPL_USB_HOST) || \ + (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch --- 2025.01-3/debian/patches/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,236 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:09 +0800 +Subject: [PATCH 5/7] usb: cdns: starfive: Add cdns USB driver + +Add Starfive cdns USB3 wrapper driver. + +Signed-off-by: Minda Chen +Reviewed-by: Marek Vasut +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-6-minda.chen@starfivetech.com/ +--- + drivers/usb/cdns3/Kconfig | 7 ++ + drivers/usb/cdns3/Makefile | 1 + + drivers/usb/cdns3/cdns3-starfive.c | 182 +++++++++++++++++++++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 drivers/usb/cdns3/cdns3-starfive.c + +diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig +index 35b61497d9c..1d5e4afac6c 100644 +--- a/drivers/usb/cdns3/Kconfig ++++ b/drivers/usb/cdns3/Kconfig +@@ -49,6 +49,13 @@ config SPL_USB_CDNS3_HOST + Host controller is compliant with XHCI so it will use + standard XHCI driver. + ++config USB_CDNS3_STARFIVE ++ tristate "Cadence USB3 support on Starfive platforms" ++ default y if STARFIVE_JH7110 ++ help ++ Say 'Y' here if you are building for Starfive platforms ++ that contain Cadence USB3 controller core. E.g.: JH7110. ++ + config USB_CDNS3_TI + tristate "Cadence USB3 support on TI platforms" + default USB_CDNS3 +diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile +index d6047856091..1f00f23f704 100644 +--- a/drivers/usb/cdns3/Makefile ++++ b/drivers/usb/cdns3/Makefile +@@ -8,4 +8,5 @@ cdns3-$(CONFIG_$(XPL_)USB_CDNS3_GADGET) += gadget.o ep0.o + + cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST) += host.o + ++obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o + obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o +diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c +new file mode 100644 +index 00000000000..f5f3e462559 +--- /dev/null ++++ b/drivers/usb/cdns3/cdns3-starfive.c +@@ -0,0 +1,182 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller ++ * ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ * ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "core.h" ++ ++#define USB_STRAP_HOST BIT(17) ++#define USB_STRAP_DEVICE BIT(18) ++#define USB_STRAP_MASK GENMASK(18, 16) ++ ++#define USB_SUSPENDM_HOST BIT(19) ++#define USB_SUSPENDM_MASK BIT(19) ++ ++#define USB_MISC_CFG_MASK GENMASK(23, 20) ++#define USB_SUSPENDM_BYPS BIT(20) ++#define USB_PLL_EN BIT(22) ++#define USB_REFCLK_MODE BIT(23) ++ ++struct cdns_starfive { ++ struct udevice *dev; ++ struct regmap *stg_syscon; ++ struct reset_ctl_bulk resets; ++ struct clk_bulk clks; ++ u32 stg_usb_mode; ++ enum usb_dr_mode mode; ++}; ++ ++static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode) ++{ ++ unsigned int strap, suspendm; ++ ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_MISC_CFG_MASK, ++ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE); ++ ++ switch (mode) { ++ case USB_DR_MODE_HOST: ++ strap = USB_STRAP_HOST; ++ suspendm = USB_SUSPENDM_HOST; ++ break; ++ case USB_DR_MODE_PERIPHERAL: ++ strap = USB_STRAP_DEVICE; ++ suspendm = 0; ++ break; ++ default: ++ return; ++ } ++ ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_SUSPENDM_MASK | USB_STRAP_MASK, ++ strap | suspendm); ++} ++ ++static void cdns_clk_rst_deinit(struct cdns_starfive *data) ++{ ++ reset_assert_bulk(&data->resets); ++ clk_disable_bulk(&data->clks); ++} ++ ++static int cdns_clk_rst_init(struct cdns_starfive *data) ++{ ++ int ret; ++ ++ ret = clk_get_bulk(data->dev, &data->clks); ++ if (ret) ++ return ret; ++ ++ ret = reset_get_bulk(data->dev, &data->resets); ++ if (ret) ++ goto err_clk; ++ ++ ret = clk_enable_bulk(&data->clks); ++ if (ret) { ++ dev_err(data->dev, "clk enable failed: %d\n", ret); ++ goto err_en_clk; ++ } ++ ++ ret = reset_deassert_bulk(&data->resets); ++ if (ret) { ++ dev_err(data->dev, "reset deassert failed: %d\n", ret); ++ goto err_reset; ++ } ++ ++ return 0; ++ ++err_reset: ++ clk_disable_bulk(&data->clks); ++err_en_clk: ++ reset_release_bulk(&data->resets); ++err_clk: ++ clk_release_bulk(&data->clks); ++ ++ return ret; ++} ++ ++static int cdns_starfive_get_syscon(struct cdns_starfive *data) ++{ ++ struct ofnode_phandle_args phandle; ++ int ret; ++ ++ ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0, ++ &phandle); ++ if (ret < 0) { ++ dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret); ++ return ret; ++ } ++ ++ data->stg_syscon = syscon_node_to_regmap(phandle.node); ++ if (IS_ERR(data->stg_syscon)) { ++ dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon)); ++ return PTR_ERR(data->stg_syscon); ++ } ++ ++ data->stg_usb_mode = phandle.args[0]; ++ ++ return 0; ++} ++ ++static int cdns_starfive_probe(struct udevice *dev) ++{ ++ struct cdns_starfive *data = dev_get_plat(dev); ++ enum usb_dr_mode dr_mode; ++ int ret; ++ ++ data->dev = dev; ++ ++ ret = cdns_starfive_get_syscon(data); ++ if (ret) ++ return ret; ++ ++ dr_mode = usb_get_dr_mode(dev_ofnode(dev)); ++ ++ data->mode = dr_mode; ++ ret = cdns_clk_rst_init(data); ++ if (ret) { ++ dev_err(data->dev, "clk reset failed: %d\n", ret); ++ return ret; ++ } ++ cdns_mode_init(data, dr_mode); ++ ++ return 0; ++} ++ ++static int cdns_starfive_remove(struct udevice *dev) ++{ ++ struct cdns_starfive *data = dev_get_plat(dev); ++ ++ cdns_clk_rst_deinit(data); ++ return 0; ++} ++ ++static const struct udevice_id cdns_starfive_of_match[] = { ++ { .compatible = "starfive,jh7110-usb", }, ++ {}, ++}; ++ ++U_BOOT_DRIVER(cdns_starfive) = { ++ .name = "cdns-starfive", ++ .id = UCLASS_NOP, ++ .of_match = cdns_starfive_of_match, ++ .bind = cdns3_bind, ++ .probe = cdns_starfive_probe, ++ .remove = cdns_starfive_remove, ++ .plat_auto = sizeof(struct cdns_starfive), ++ .flags = DM_FLAG_OS_PREPARE, ++}; +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch --- 2025.01-3/debian/patches/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,50 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:10 +0800 +Subject: [PATCH 6/7] spl: starfive: visionfive2: Disable USB overcurrent pin + by default. + +For some JH7110 boards, USB host overcurent pin is not reserved, +To make USB host work, overcurrent pin must be disabled. So set the +pin default disabled in spl stage. + +Signed-off-by: Minda Chen +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-7-minda.chen@starfivetech.com/ +--- + arch/riscv/include/asm/arch-jh7110/gpio.h | 5 +++++ + board/starfive/visionfive2/spl.c | 3 +++ + 2 files changed, 8 insertions(+) + +diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h +index 90aa2f8a9ed..be2a1e0d1c8 100644 +--- a/arch/riscv/include/asm/arch-jh7110/gpio.h ++++ b/arch/riscv/include/asm/arch-jh7110/gpio.h +@@ -63,6 +63,11 @@ enum gpio_state { + GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ + ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) + ++#define SYS_IOMUX_DIN_DISABLED(gpi)\ ++ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \ ++ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ ++ ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) ++ + #define SYS_IOMUX_SET_DS(gpio, ds) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ + GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT) +diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c +index 22afd76c6b9..1538d6aec73 100644 +--- a/board/starfive/visionfive2/spl.c ++++ b/board/starfive/visionfive2/spl.c +@@ -103,6 +103,9 @@ void board_init_f(ulong dummy) + JH7110_CLK_CPU_ROOT_MASK, + BIT(JH7110_CLK_CPU_ROOT_SHIFT)); + ++ /* Set USB overcurrent overflow pin disable */ ++ SYS_IOMUX_DIN_DISABLED(2); ++ + ret = spl_board_init_f(); + if (ret) { + debug("spl_board_init_f init failed: %d\n", ret); +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch 2025.01-3ubuntu1/debian/patches/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch --- 2025.01-3/debian/patches/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch 2025-05-09 09:51:05.000000000 +0000 @@ -0,0 +1,59 @@ +From: Minda Chen +Date: Thu, 23 Jan 2025 09:01:11 +0800 +Subject: [PATCH 7/7] configs: starfive: Add visionfive2 cadence USB + configuration + +Add cadence USB confiuration. + +Signed-off-by: Minda Chen +Tested-by: E Shattow +Origin: https://lore.kernel.org/u-boot/20250123010112.78924-8-minda.chen@starfivetech.com/ +--- + configs/starfive_visionfive2_defconfig | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig +index 1e0a99ed17b..390d78ce4cb 100644 +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -71,6 +71,7 @@ CONFIG_SYS_EEPROM_SIZE=512 + CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4 + CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 + CONFIG_CMD_MEMINFO=y ++# CONFIG_CMD_BIND is not set + CONFIG_CMD_I2C=y + CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y +@@ -117,6 +118,9 @@ CONFIG_NVME_PCI=y + CONFIG_DM_PCI_COMPAT=y + CONFIG_PCI_REGION_MULTI_ENTRY=y + CONFIG_PCIE_STARFIVE_JH7110=y ++CONFIG_PHY=y ++CONFIG_PHY_STARFIVE_JH7110_PCIE=y ++CONFIG_PHY_STARFIVE_JH7110_USB2=y + CONFIG_PINCTRL=y + CONFIG_PINCONF=y + CONFIG_SPL_PINCTRL=y +@@ -132,13 +136,19 @@ CONFIG_CADENCE_QSPI=y + CONFIG_SYSRESET=y + CONFIG_TIMER_EARLY=y + CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_PCI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_PCI=y + CONFIG_USB_OHCI_HCD=y + CONFIG_USB_OHCI_PCI=y ++CONFIG_USB_CDNS3=y ++CONFIG_USB_CDNS3_GADGET=y ++CONFIG_USB_CDNS3_HOST=y ++# CONFIG_USB_CDNS3_TI is not set + CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y + # CONFIG_WATCHDOG is not set + # CONFIG_WATCHDOG_AUTOSTART is not set + CONFIG_WDT=y +-- +2.47.1 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0001-efi-Correct-ECPT-table-GUID.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0001-efi-Correct-ECPT-table-GUID.patch --- 2025.01-3/debian/patches/riscv64/starfive/0001-efi-Correct-ECPT-table-GUID.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0001-efi-Correct-ECPT-table-GUID.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,33 @@ +From 0bfbb283202371ba79e6c15687456a6b983efb84 Mon Sep 17 00:00:00 2001 +From: Yang Gang +Date: Fri, 3 Jan 2025 16:18:42 +0800 +Subject: [PATCH 01/27] efi: Correct ECPT table GUID + +Refer to UEFI specification 2.10: + #define EFI_CONFORMANCE_PROFILES_TABLE_GUID \ + { 0x36122546, 0xf7e7, 0x4c8f, \ + { 0xbd, 0x9b, 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b }} + +Signed-off-by: Yang Gang +Fixes: 6b92c1735205 ("efi: Create ECPT table") +Reviewed-by: Heinrich Schuchardt +--- + include/efi_api.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/efi_api.h b/include/efi_api.h +index f07d074f93b..d3cf012693f 100644 +--- a/include/efi_api.h ++++ b/include/efi_api.h +@@ -227,7 +227,7 @@ enum efi_reset_type { + 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) + + #define EFI_CONFORMANCE_PROFILES_TABLE_GUID \ +- EFI_GUID(0x36122546, 0xf7ef, 0x4c8f, 0xbd, 0x9b, \ ++ EFI_GUID(0x36122546, 0xf7e7, 0x4c8f, 0xbd, 0x9b, \ + 0xeb, 0x85, 0x25, 0xb5, 0x0c, 0x0b) + + #define EFI_CONFORMANCE_PROFILES_TABLE_VERSION 1 +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0002-pinctrl-imx-Fix-NULL-dereference-in-imx_pinctrl_prob.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0002-pinctrl-imx-Fix-NULL-dereference-in-imx_pinctrl_prob.patch --- 2025.01-3/debian/patches/riscv64/starfive/0002-pinctrl-imx-Fix-NULL-dereference-in-imx_pinctrl_prob.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0002-pinctrl-imx-Fix-NULL-dereference-in-imx_pinctrl_prob.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,41 @@ +From 079da94f154712145a8777a800df222a1672c5be Mon Sep 17 00:00:00 2001 +From: Jesse Taube +Date: Thu, 16 Jan 2025 22:00:48 -0500 +Subject: [PATCH 02/27] pinctrl: imx: Fix NULL dereference in + imx_pinctrl_probe() + +When converting to ofnode `ofnode_read_u32` was accedentally used to +replace `fdtdec_get_int` instead of `ofnode_read_u32_default`. +Use `ofnode_read_u32_default` to fix this. + +Fixes: 59382d2 ("pinctrl: imx: Convert to use livetree API for fdt access") +Signed-off-by: Jesse Taube +--- + drivers/pinctrl/nxp/pinctrl-imx.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c +index b1960c56b51..54cec37327c 100644 +--- a/drivers/pinctrl/nxp/pinctrl-imx.c ++++ b/drivers/pinctrl/nxp/pinctrl-imx.c +@@ -219,7 +219,7 @@ int imx_pinctrl_probe(struct udevice *dev, + if (info->flags & IMX8_USE_SCU) + return 0; + +- addr = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &size); ++ addr = ofnode_get_addr_size_index(node, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + +@@ -228,7 +228,7 @@ int imx_pinctrl_probe(struct udevice *dev, + return -ENOMEM; + priv->info = info; + +- info->mux_mask = ofnode_read_u32(node, "fsl,mux_mask", 0); ++ info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0); + /* + * Refer to linux documentation for details: + * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0003-power-pmic-sunxi-guard-DCDC5-separately.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0003-power-pmic-sunxi-guard-DCDC5-separately.patch --- 2025.01-3/debian/patches/riscv64/starfive/0003-power-pmic-sunxi-guard-DCDC5-separately.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0003-power-pmic-sunxi-guard-DCDC5-separately.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,54 @@ +From 3703a8ab5c6aebc762ede358cd49b084ec66757a Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Sun, 15 Dec 2024 00:22:48 +0000 +Subject: [PATCH 03/27] power: pmic: sunxi: guard DCDC5 separately + +So far all sunxi boards programming the DCDC1 power rail on the AXP PMIC +also set the DCDC5 rail, so we could handle both with the same DCDC1 +guard. +Some boards using the AXP313 will need to set DCDC1 now as well, and +since the AXP313 only has three buck converters, there will be no DCDC5, +so this trick is not going to work anymore. + +Don't try to be too clever, and just protect programming the two DCDC +rails with two separate guards. + +This has the interesting side effect of fixing operation on A80 boards, +using the AXP809 PMIC. Apparently programming DCDC5 right after DCDC1, +but before the other three rails caused some glitch, which made the board +hang during Linux boot, during the PSCI handler in U-Boot. Just keeping +the old setup order (DCDC1,2,3,4,5) will make those boards boot to the +Linux prompt again. + +Fixes: ffb02942fab024d4a9b6a ("sunxi: board: simplify early PMIC setup conditions") +Signed-off-by: Andre Przywara +Reviewed-by: Chen-Yu Tsai +--- + board/sunxi/board.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 824c322a0dc..9c340908a96 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -577,7 +577,6 @@ void sunxi_board_init(void) + + #ifdef CONFIG_AXP_DCDC1_VOLT + power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); +- power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); + #endif + #ifdef CONFIG_AXP_DCDC2_VOLT + power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); +@@ -586,6 +585,9 @@ void sunxi_board_init(void) + #ifdef CONFIG_AXP_DCDC4_VOLT + power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); + #endif ++#ifdef CONFIG_AXP_DCDC5_VOLT ++ power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); ++#endif + + #ifdef CONFIG_AXP_ALDO1_VOLT + power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0004-configs-use-syntax-CONFIG_FOO-n-in-tools-only_defcon.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0004-configs-use-syntax-CONFIG_FOO-n-in-tools-only_defcon.patch --- 2025.01-3/debian/patches/riscv64/starfive/0004-configs-use-syntax-CONFIG_FOO-n-in-tools-only_defcon.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0004-configs-use-syntax-CONFIG_FOO-n-in-tools-only_defcon.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,77 @@ +From 0cbaf853e1f7ea34c111ffe5fca7cf780809efa0 Mon Sep 17 00:00:00 2001 +From: Tom Rini +Date: Wed, 29 Jan 2025 08:08:52 -0600 +Subject: [PATCH 04/27] configs: use syntax CONFIG_FOO=n in + tools-only_defconfig again + +As explained in commit c2cd7bd3ecfe ("configs: use syntax CONFIG_FOO=n +in tools-only_defconfig") we need to not use the "# CONFIG_FOO is not +set" syntax here in order to work correctly on OSes where cpp comes +ffrom LLVM. + +Fixes: 867e16ae05e2 ("configs: Resync with savedefconfig") +Signed-off-by: Tom Rini +--- + configs/tools-only_defconfig | 32 ++++++++++++++++---------------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig +index 5e3a46baa41..cecd26175d1 100644 +--- a/configs/tools-only_defconfig ++++ b/configs/tools-only_defconfig +@@ -4,27 +4,27 @@ CONFIG_ENV_SIZE=0x2000 + CONFIG_DEFAULT_DEVICE_TREE="sandbox" + CONFIG_SYS_LOAD_ADDR=0x0 + CONFIG_PCI=y +-# CONFIG_SANDBOX_SDL is not set +-# CONFIG_EFI_LOADER is not set ++CONFIG_SANDBOX_SDL=n ++CONFIG_EFI_LOADER=n + CONFIG_ANDROID_BOOT_IMAGE=y + CONFIG_TIMESTAMP=y + CONFIG_FIT=y + CONFIG_FIT_SIGNATURE=y +-# CONFIG_BOOTSTD_FULL is not set +-# CONFIG_BOOTMETH_CROS is not set +-# CONFIG_BOOTMETH_VBE is not set ++CONFIG_BOOTSTD_FULL=n ++CONFIG_BOOTMETH_CROS=n ++CONFIG_BOOTMETH_VBE=n + CONFIG_USE_BOOTCOMMAND=y + CONFIG_BOOTCOMMAND="run distro_bootcmd" +-# CONFIG_CMD_BOOTD is not set +-# CONFIG_CMD_BOOTM is not set +-# CONFIG_CMD_BOOTI is not set +-# CONFIG_CMD_ELF is not set +-# CONFIG_CMD_EXTENSION is not set +-# CONFIG_CMD_DATE is not set ++CONFIG_CMD_BOOTD=n ++CONFIG_CMD_BOOTM=n ++CONFIG_CMD_BOOTI=n ++CONFIG_CMD_ELF=n ++CONFIG_CMD_EXTENSION=n ++CONFIG_CMD_DATE=n + CONFIG_OF_CONTROL=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_NO_NET=y +-# CONFIG_ACPIGEN is not set ++CONFIG_ACPIGEN=n + CONFIG_AXI=y + CONFIG_AXI_SANDBOX=y + CONFIG_SANDBOX_GPIO=y +@@ -33,8 +33,8 @@ CONFIG_DM_RTC=y + CONFIG_SOUND=y + CONFIG_SYSRESET=y + CONFIG_TIMER=y +-# CONFIG_VIRTIO_MMIO is not set +-# CONFIG_VIRTIO_PCI is not set +-# CONFIG_VIRTIO_SANDBOX is not set +-# CONFIG_GENERATE_ACPI_TABLE is not set ++CONFIG_VIRTIO_MMIO=n ++CONFIG_VIRTIO_PCI=n ++CONFIG_VIRTIO_SANDBOX=n ++CONFIG_GENERATE_ACPI_TABLE=n + CONFIG_TOOLS_MKEFICAPSULE=y +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0005-pinctrl-starfive-Correct-driver-declaration-for-star.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0005-pinctrl-starfive-Correct-driver-declaration-for-star.patch --- 2025.01-3/debian/patches/riscv64/starfive/0005-pinctrl-starfive-Correct-driver-declaration-for-star.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0005-pinctrl-starfive-Correct-driver-declaration-for-star.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,42 @@ +From d880024b92e97ec326d41838d96fa2935b5464fd Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Thu, 16 Jan 2025 11:45:34 +0800 +Subject: [PATCH 05/27] pinctrl: starfive: Correct driver declaration for + starfive_gpio + +Use the driver macros so that the driver appears in the +linker list. + +Reported-by: Simon Glass +Fixes: 732f01aabf53 ("pinctrl: starfive: Add StarFive JH7110 driver") +Signed-off-by: Hal Feng +Reviewed-by: Anand Moon +--- + drivers/pinctrl/starfive/pinctrl-starfive.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/starfive/pinctrl-starfive.c b/drivers/pinctrl/starfive/pinctrl-starfive.c +index 95b1a752de2..1b942e6f045 100644 +--- a/drivers/pinctrl/starfive/pinctrl-starfive.c ++++ b/drivers/pinctrl/starfive/pinctrl-starfive.c +@@ -348,7 +348,7 @@ static const struct dm_gpio_ops starfive_gpio_ops = { + .set_value = starfive_gpio_set_value, + }; + +-static struct driver starfive_gpio_driver = { ++U_BOOT_DRIVER(starfive_gpio) = { + .name = "starfive_gpio", + .id = UCLASS_GPIO, + .probe = starfive_gpio_probe, +@@ -367,7 +367,7 @@ static int starfive_gpiochip_register(struct udevice *parent) + return -ENOENT; + + node = dev_ofnode(parent); +- ret = device_bind_with_driver_data(parent, &starfive_gpio_driver, ++ ret = device_bind_with_driver_data(parent, DM_DRIVER_REF(starfive_gpio), + "starfive_gpio", 0, node, &dev); + + return (ret == 0) ? 0 : ret; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0006-net-eth_bootdev_hunt-should-not-run-DHCP.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0006-net-eth_bootdev_hunt-should-not-run-DHCP.patch --- 2025.01-3/debian/patches/riscv64/starfive/0006-net-eth_bootdev_hunt-should-not-run-DHCP.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0006-net-eth_bootdev_hunt-should-not-run-DHCP.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,83 @@ +From a3169eaf39f737ce6b929a5f2696706797740d44 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Wed, 27 Nov 2024 08:06:29 +0100 +Subject: [PATCH 06/27] net: eth_bootdev_hunt() should not run DHCP + +Currently when booting dhcp_run() may be executed multiple times: +once in eth_bootdev_hunt() and once in the network booting bootmeth. + +We need to call eth_bootdev_hunt() when setting up the EFI sub-system to +supply the simple network protocol. We don't need an IP address set up. + +We can reduce the bootime by not executing dhcp_run() in +eth_bootdev_hunt(). + +Furthermore eth_bootdev_hunt() with autostart=yes leads on the legacy +network stack leads to downloading a file via TFTP and to booting the +downloaded file. + +Instead of running dchp_run() just check that there is a network device +in eth_bootdev_hunt(). + +Reviewed-by: Ilias Apalodimas +Signed-off-by: Heinrich Schuchardt +Reviewed-by: Simon Glass +--- + net/eth_bootdev.c | 30 ++++++++++++++++++------------ + 1 file changed, 18 insertions(+), 12 deletions(-) + +diff --git a/net/eth_bootdev.c b/net/eth_bootdev.c +index 6ee54e3c790..b0fca6e8313 100644 +--- a/net/eth_bootdev.c ++++ b/net/eth_bootdev.c +@@ -64,9 +64,23 @@ static int eth_bootdev_bind(struct udevice *dev) + return 0; + } + ++/** ++ * eth_bootdev_hunt() - probe all network devices ++ * ++ * Network devices can also come from USB, but that is a higher ++ * priority (BOOTDEVP_5_SCAN_SLOW) than network, so it should have been ++ * enumerated already. If something like 'bootflow scan dhcp' is used, ++ * then the user will need to run 'usb start' first. ++ * ++ * @info: info structure describing this hunter ++ * @show: true to show information from the hunter ++ * ++ * Return: 0 if device found, -EINVAL otherwise ++ */ + static int eth_bootdev_hunt(struct bootdev_hunter *info, bool show) + { + int ret; ++ struct udevice *dev = NULL; + + if (!test_eth_enabled()) + return 0; +@@ -78,19 +92,11 @@ static int eth_bootdev_hunt(struct bootdev_hunter *info, bool show) + log_warning("Failed to init PCI (%dE)\n", ret); + } + +- /* +- * Ethernet devices can also come from USB, but that is a higher +- * priority (BOOTDEVP_5_SCAN_SLOW) than ethernet, so it should have been +- * enumerated already. If something like 'bootflow scan dhcp' is used +- * then the user will need to run 'usb start' first. +- */ +- if (IS_ENABLED(CONFIG_CMD_DHCP)) { +- ret = dhcp_run(0, NULL, false); +- if (ret) +- return -EINVAL; +- } ++ ret = -EINVAL; ++ uclass_foreach_dev_probe(UCLASS_ETH, dev) ++ ret = 0; + +- return 0; ++ return ret; + } + + struct bootdev_ops eth_bootdev_ops = { +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0007-configs-SiFive-Unmatched-add-nvme-scan-to-preboot.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0007-configs-SiFive-Unmatched-add-nvme-scan-to-preboot.patch --- 2025.01-3/debian/patches/riscv64/starfive/0007-configs-SiFive-Unmatched-add-nvme-scan-to-preboot.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0007-configs-SiFive-Unmatched-add-nvme-scan-to-preboot.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,53 @@ +From cee5a030ffaf86394fbe90aa3eb89a886aa49a92 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 12 Nov 2024 11:26:44 +0100 +Subject: [PATCH 07/27] configs: SiFive Unmatched: add 'nvme scan' to preboot + +Without 'nvme scan' the ESP on the NVMe drive is not found early. +EFI variables cannot be persisted. + + Hit any key to stop autoboot: 0 + Cannot persist EFI variables without system partition + ** Booting bootflow '' with efi_mgr + Loading Boot0000 'mmc 0' failed + EFI boot manager: Cannot load any image + Boot failed (err=-14) + scanning bus for devices... + ** Booting bootflow 'nvme#1.blk#1.bootdev.part_1' with efi + Booting /\EFI\BOOT\BOOTRISCV64.EFI + error: no suitable video mode found. + GNU GRUB version 2.12 + +With 'nmve scan' booting works as expected. + + Hit any key to stop autoboot: 0 + ** Booting bootflow '' with efi_mgr + Loading Boot0000 'mmc 0' failed + Loading Boot0001 'nvme 0' failed + Booting: nvme 1 + error: no suitable video mode found. + GNU GRUB version 2.12 + +Reported by Yuri Zaporozhets + +Signed-off-by: Heinrich Schuchardt +--- + configs/sifive_unmatched_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig +index 4fed7eda948..a400538dcbe 100644 +--- a/configs/sifive_unmatched_defconfig ++++ b/configs/sifive_unmatched_defconfig +@@ -27,7 +27,7 @@ CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" ++CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};nvme scan" + CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" + CONFIG_SYS_CBSIZE=256 + CONFIG_SYS_PBSIZE=276 +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0008-efi_loader-fix-pe-reloc-pointer-overrun.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0008-efi_loader-fix-pe-reloc-pointer-overrun.patch --- 2025.01-3/debian/patches/riscv64/starfive/0008-efi_loader-fix-pe-reloc-pointer-overrun.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0008-efi_loader-fix-pe-reloc-pointer-overrun.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,53 @@ +From b1e6da80b0a4ee0f03eac2cd4af25e7d1c0c5077 Mon Sep 17 00:00:00 2001 +From: Aleksandar Gerasimovski +Date: Fri, 29 Nov 2024 21:09:44 +0000 +Subject: [PATCH 08/27] efi_loader: fix pe reloc pointer overrun + +The fix provided by 997fc12ec91 is actually introducing +a buffer overrun, and the overrun is effective if the +memory after the reloc section is not zeroed. +Probably that's why this bug is not always noticeable. + +The problem is that 8-bytes 'rel' pointer can be 4-bytes aligned +according to the PE Format, so the actual relocate function can +take values after the reloc section. + +One example is the following dump from the reloc section: + + bce26000: 3000 0000 000c 0000 0000 0000 0000 0000 + bce26010: 7c00 9340 67e0 f900 1c00 0ea1 a400 0f20 + +This section has two relocations at offset bce26008 and bce2600a, +however the given size (rel_size) for this relocation is 16-bytes +and this is coming form the efi image Misc.VirtualSize, so in this +case the 'reloc' pointer ends at affset bce2600c and is taken as +valid and this is where the overflow is. + +In our system we see this problem when we are starting the +Boot Guard efi image. + +This patch is fixing the overrun while preserving the fix done +by 997fc12ec91. + +Signed-off-by: Aleksandar Gerasimovski +Reviewed-by: Heinrich Schuchardt +--- + lib/efi_loader/efi_image_loader.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c +index 0ddf69a0918..04075d83cb7 100644 +--- a/lib/efi_loader/efi_image_loader.c ++++ b/lib/efi_loader/efi_image_loader.c +@@ -121,7 +121,7 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, + return EFI_SUCCESS; + + end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size); +- while (rel < end && rel->SizeOfBlock) { ++ while (rel + 1 < end && rel->SizeOfBlock) { + const uint16_t *relocs = (const uint16_t *)(rel + 1); + i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t); + while (i--) { +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0009-riscv-dts-starfive-add-DeepComputing-FML13V01-board-.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0009-riscv-dts-starfive-add-DeepComputing-FML13V01-board-.patch --- 2025.01-3/debian/patches/riscv64/starfive/0009-riscv-dts-starfive-add-DeepComputing-FML13V01-board-.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0009-riscv-dts-starfive-add-DeepComputing-FML13V01-board-.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,42 @@ +From 2da75a560cfcd24728ff31e051e808d1f88cb60e Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 08:30:17 +0100 +Subject: [PATCH 09/27] riscv: dts: starfive: add DeepComputing FML13V01 board + device tree + +The FML13V01 board from DeepComputing incorporates a StarFive JH7110 SoC. +It is a mainboard designed for the Framework Laptop 13 Chassis, which has +(Framework) SKU FRANHQ0001. + +Signed-off-by: Heinrich Schuchardt +--- + .../starfive/jh7110-deepcomputing-fml13v01.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + create mode 100644 dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts + +diff --git a/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts +new file mode 100644 +index 00000000000..30b0715196b +--- /dev/null ++++ b/dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2024 DeepComputing (HK) Limited ++ */ ++ ++/dts-v1/; ++#include "jh7110-common.dtsi" ++ ++/ { ++ model = "DeepComputing FML13V01"; ++ compatible = "deepcomputing,fml13v01", "starfive,jh7110"; ++}; ++ ++&usb0 { ++ dr_mode = "host"; ++ status = "okay"; ++}; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0010-dts-starfive-Switch-to-using-upstream-DT.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0010-dts-starfive-Switch-to-using-upstream-DT.patch --- 2025.01-3/debian/patches/riscv64/starfive/0010-dts-starfive-Switch-to-using-upstream-DT.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0010-dts-starfive-Switch-to-using-upstream-DT.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,1833 @@ +From 4f1a3d1e9b90edefc07245a7ffba2791f2e9caae Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:31 +0800 +Subject: [PATCH 10/27] dts: starfive: Switch to using upstream DT + +Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to +the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi +to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b +device tree as the default device tree. + +Drop redundant DT files from arch/riscv/dts/ and redundant clock and +reset definitions from include/dt-bindings/. + +Since the old clock definitions is a little different from those in +upstream Linux, update the clock definitions in clock drivers +accordingly. + +Tested-by: Anand Moon +Tested-by: E Shattow +Acked-by: Sumit Garg +Signed-off-by: Hal Feng +--- + arch/riscv/cpu/jh7110/Kconfig | 1 + + arch/riscv/dts/Makefile | 1 - + ...0-starfive-visionfive-2-v1.3b-u-boot.dtsi} | 0 + .../dts/jh7110-starfive-visionfive-2.dts | 11 - + .../dts/jh7110-starfive-visionfive-2.dtsi | 380 --------- + arch/riscv/dts/jh7110-u-boot.dtsi | 2 +- + arch/riscv/dts/jh7110.dtsi | 761 ------------------ + configs/starfive_visionfive2_defconfig | 2 +- + drivers/clk/starfive/clk-jh7110-pll.c | 6 +- + drivers/clk/starfive/clk-jh7110.c | 44 +- + .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------ + .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- + 12 files changed, 28 insertions(+), 1621 deletions(-) + rename arch/riscv/dts/{jh7110-starfive-visionfive-2-u-boot.dtsi => jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi} (100%) + delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts + delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi + delete mode 100644 arch/riscv/dts/jh7110.dtsi + delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h + delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h + +diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig +index e5549a01b83..9904a60dddb 100644 +--- a/arch/riscv/cpu/jh7110/Kconfig ++++ b/arch/riscv/cpu/jh7110/Kconfig +@@ -19,6 +19,7 @@ config STARFIVE_JH7110 + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI ++ imply OF_UPSTREAM + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CACHE + imply SIFIVE_CCACHE +diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile +index de356584bf1..07ebe530bda 100644 +--- a/arch/riscv/dts/Makefile ++++ b/arch/riscv/dts/Makefile +@@ -7,7 +7,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb + dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb + dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb + dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb +-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb + dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb + dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb + dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +similarity index 100% +rename from arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi +rename to arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts +deleted file mode 100644 +index 288ea394939..00000000000 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts ++++ /dev/null +@@ -1,11 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright (C) 2023 StarFive Technology Co., Ltd. +- */ +- +-/dts-v1/; +-#include "jh7110-starfive-visionfive-2.dtsi" +- +-/ { +- compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; +-}; +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +deleted file mode 100644 +index e11babc1cde..00000000000 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi ++++ /dev/null +@@ -1,380 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright (C) 2022 StarFive Technology Co., Ltd. +- */ +- +-/dts-v1/; +- +-#include "jh7110.dtsi" +-#include +-#include +-/ { +- aliases { +- serial0 = &uart0; +- spi0 = &qspi; +- mmc0 = &mmc0; +- mmc1 = &mmc1; +- i2c0 = &i2c0; +- i2c2 = &i2c2; +- i2c5 = &i2c5; +- i2c6 = &i2c6; +- ethernet0 = &gmac0; +- ethernet1 = &gmac1; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- cpus { +- timebase-frequency = <4000000>; +- }; +- +- memory@40000000 { +- device_type = "memory"; +- reg = <0x0 0x40000000 0x2 0x0>; +- }; +- +- gpio-restart { +- compatible = "gpio-restart"; +- gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; +- }; +-}; +- +-&osc { +- clock-frequency = <24000000>; +-}; +- +-&rtc_osc { +- clock-frequency = <32768>; +-}; +- +-&gmac0_rmii_refin { +- clock-frequency = <50000000>; +-}; +- +-&gmac0_rgmii_rxin { +- clock-frequency = <125000000>; +-}; +- +-&gmac1_rmii_refin { +- clock-frequency = <50000000>; +-}; +- +-&gmac1_rgmii_rxin { +- clock-frequency = <125000000>; +-}; +- +-&i2stx_bclk_ext { +- clock-frequency = <12288000>; +-}; +- +-&i2stx_lrck_ext { +- clock-frequency = <192000>; +-}; +- +-&i2srx_bclk_ext { +- clock-frequency = <12288000>; +-}; +- +-&i2srx_lrck_ext { +- clock-frequency = <192000>; +-}; +- +-&tdm_ext { +- clock-frequency = <49152000>; +-}; +- +-&mclk_ext { +- clock-frequency = <12288000>; +-}; +- +-&uart0 { +- reg-offset = <0>; +- current-speed = <115200>; +- clock-frequency = <24000000>; +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins>; +- status = "okay"; +-}; +- +-&i2c0 { +- clock-frequency = <100000>; +- i2c-sda-hold-time-ns = <300>; +- i2c-sda-falling-time-ns = <510>; +- i2c-scl-falling-time-ns = <510>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c0_pins>; +- status = "okay"; +-}; +- +-&i2c2 { +- clock-frequency = <100000>; +- i2c-sda-hold-time-ns = <300>; +- i2c-sda-falling-time-ns = <510>; +- i2c-scl-falling-time-ns = <510>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c2_pins>; +- status = "okay"; +-}; +- +-&i2c5 { +- clock-frequency = <100000>; +- i2c-sda-hold-time-ns = <300>; +- i2c-sda-falling-time-ns = <510>; +- i2c-scl-falling-time-ns = <510>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c5_pins>; +- status = "okay"; +- +- pmic@36 { +- compatible = "x-powers,axp15060"; +- reg = <0x36>; +- }; +- +- eeprom@50 { +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&i2c6 { +- clock-frequency = <100000>; +- i2c-sda-hold-time-ns = <300>; +- i2c-sda-falling-time-ns = <510>; +- i2c-scl-falling-time-ns = <510>; +- pinctrl-names = "default"; +- pinctrl-0 = <&i2c6_pins>; +- status = "okay"; +-}; +- +-&sysgpio { +- status = "okay"; +- uart0_pins: uart0-0 { +- tx-pins { +- pinmux = ; +- bias-disable; +- drive-strength = <12>; +- input-disable; +- input-schmitt-disable; +- slew-rate = <0>; +- }; +- +- rx-pins { +- pinmux = ; +- bias-disable; /* external pull-up */ +- drive-strength = <2>; +- input-enable; +- input-schmitt-enable; +- slew-rate = <0>; +- }; +- }; +- +- i2c0_pins: i2c0-0 { +- i2c-pins { +- pinmux = , +- ; +- bias-disable; /* external pull-up */ +- input-enable; +- input-schmitt-enable; +- }; +- }; +- +- i2c2_pins: i2c2-0 { +- i2c-pins { +- pinmux = , +- ; +- bias-disable; /* external pull-up */ +- input-enable; +- input-schmitt-enable; +- }; +- }; +- +- i2c5_pins: i2c5-0 { +- i2c-pins { +- pinmux = , +- ; +- bias-disable; /* external pull-up */ +- input-enable; +- input-schmitt-enable; +- }; +- }; +- +- i2c6_pins: i2c6-0 { +- i2c-pins { +- pinmux = , +- ; +- bias-disable; /* external pull-up */ +- input-enable; +- input-schmitt-enable; +- }; +- }; +- +- mmc0_pins: mmc0-pins { +- mmc0-pins-rest { +- pinmux = ; +- bias-pull-up; +- drive-strength = <12>; +- input-disable; +- input-schmitt-disable; +- slew-rate = <0>; +- }; +- }; +- +- mmc1_pins: mmc1-pins { +- mmc1-pins0 { +- pinmux = ; +- bias-pull-up; +- drive-strength = <12>; +- input-disable; +- input-schmitt-disable; +- slew-rate = <0>; +- }; +- +- mmc1-pins1 { +- pinmux = , +- , +- , +- , +- ; +- bias-pull-up; +- drive-strength = <12>; +- input-enable; +- input-schmitt-enable; +- slew-rate = <0>; +- }; +- }; +-}; +- +-&mmc0 { +- compatible = "snps,dw-mshc"; +- max-frequency = <100000000>; +- bus-width = <8>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins>; +- cap-mmc-highspeed; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- non-removable; +- cap-mmc-hw-reset; +- post-power-on-delay-ms = <200>; +- status = "okay"; +- +-}; +- +-&mmc1 { +- compatible = "snps,dw-mshc"; +- max-frequency = <100000000>; +- bus-width = <4>; +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc1_pins>; +- no-sdio; +- no-mmc; +- cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; +- cap-sd-highspeed; +- post-power-on-delay-ms = <200>; +- status = "okay"; +-}; +- +-&qspi { +- spi-max-frequency = <250000000>; +- status = "okay"; +- +- nor-flash@0 { +- compatible = "jedec,spi-nor"; +- reg=<0>; +- spi-max-frequency = <100000000>; +- cdns,tshsl-ns = <1>; +- cdns,tsd2d-ns = <1>; +- cdns,tchsh-ns = <1>; +- cdns,tslch-ns = <1>; +- }; +-}; +- +-&pcie0 { +- reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&pcie1 { +- reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; +- status = "okay"; +-}; +- +-&syscrg { +- assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, +- <&syscrg JH7110_SYSCLK_BUS_ROOT>, +- <&syscrg JH7110_SYSCLK_PERH_ROOT>, +- <&syscrg JH7110_SYSCLK_QSPI_REF>; +- assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, +- <&pllclk JH7110_SYSCLK_PLL2_OUT>, +- <&pllclk JH7110_SYSCLK_PLL2_OUT>, +- <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; +- assigned-clock-rates = <0>, <0>, <0>, <0>; +-}; +- +-&aoncrg { +- assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; +- assigned-clock-parents = <&osc>; +- assigned-clock-rates = <0>; +-}; +- +-&gmac0 { +- phy-handle = <&phy0>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- +- phy0: ethernet-phy@0 { +- reg = <0>; +- }; +- }; +-}; +- +-&gmac1 { +- phy-handle = <&phy1>; +- phy-mode = "rgmii-id"; +- status = "okay"; +- +- mdio { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "snps,dwmac-mdio"; +- +- phy1: ethernet-phy@1 { +- reg = <0>; +- }; +- }; +-}; +diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi +index 2f560e7296f..52c1d60859a 100644 +--- a/arch/riscv/dts/jh7110-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-u-boot.dtsi +@@ -62,7 +62,7 @@ + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; +- clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; ++ clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll1_out"; + clock-frequency = <2133>; + }; +diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi +deleted file mode 100644 +index 2cdc683d49b..00000000000 +--- a/arch/riscv/dts/jh7110.dtsi ++++ /dev/null +@@ -1,761 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * Copyright (C) 2022 StarFive Technology Co., Ltd. +- */ +- +-/dts-v1/; +-#include +-#include +- +-/ { +- compatible = "starfive,jh7110"; +- #address-cells = <2>; +- #size-cells = <2>; +- +- cpus { +- #address-cells = <1>; +- #size-cells = <0>; +- +- S7_0: cpu@0 { +- compatible = "sifive,s7", "riscv"; +- reg = <0>; +- device_type = "cpu"; +- i-cache-block-size = <64>; +- i-cache-sets = <64>; +- i-cache-size = <16384>; +- next-level-cache = <&ccache>; +- riscv,isa = "rv64imac_zba_zbb"; +- status = "disabled"; +- +- cpu0_intc: interrupt-controller { +- compatible = "riscv,cpu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- U74_1: cpu@1 { +- compatible = "sifive,u74-mc", "riscv"; +- reg = <1>; +- d-cache-block-size = <64>; +- d-cache-sets = <64>; +- d-cache-size = <32768>; +- d-tlb-sets = <1>; +- d-tlb-size = <40>; +- device_type = "cpu"; +- i-cache-block-size = <64>; +- i-cache-sets = <64>; +- i-cache-size = <32768>; +- i-tlb-sets = <1>; +- i-tlb-size = <40>; +- mmu-type = "riscv,sv39"; +- next-level-cache = <&ccache>; +- riscv,isa = "rv64imafdc_zba_zbb"; +- tlb-split; +- +- cpu1_intc: interrupt-controller { +- compatible = "riscv,cpu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- U74_2: cpu@2 { +- compatible = "sifive,u74-mc", "riscv"; +- reg = <2>; +- d-cache-block-size = <64>; +- d-cache-sets = <64>; +- d-cache-size = <32768>; +- d-tlb-sets = <1>; +- d-tlb-size = <40>; +- device_type = "cpu"; +- i-cache-block-size = <64>; +- i-cache-sets = <64>; +- i-cache-size = <32768>; +- i-tlb-sets = <1>; +- i-tlb-size = <40>; +- mmu-type = "riscv,sv39"; +- next-level-cache = <&ccache>; +- riscv,isa = "rv64imafdc_zba_zbb"; +- tlb-split; +- +- cpu2_intc: interrupt-controller { +- compatible = "riscv,cpu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- U74_3: cpu@3 { +- compatible = "sifive,u74-mc", "riscv"; +- reg = <3>; +- d-cache-block-size = <64>; +- d-cache-sets = <64>; +- d-cache-size = <32768>; +- d-tlb-sets = <1>; +- d-tlb-size = <40>; +- device_type = "cpu"; +- i-cache-block-size = <64>; +- i-cache-sets = <64>; +- i-cache-size = <32768>; +- i-tlb-sets = <1>; +- i-tlb-size = <40>; +- mmu-type = "riscv,sv39"; +- next-level-cache = <&ccache>; +- riscv,isa = "rv64imafdc_zba_zbb"; +- tlb-split; +- +- cpu3_intc: interrupt-controller { +- compatible = "riscv,cpu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- U74_4: cpu@4 { +- compatible = "sifive,u74-mc", "riscv"; +- reg = <4>; +- d-cache-block-size = <64>; +- d-cache-sets = <64>; +- d-cache-size = <32768>; +- d-tlb-sets = <1>; +- d-tlb-size = <40>; +- device_type = "cpu"; +- i-cache-block-size = <64>; +- i-cache-sets = <64>; +- i-cache-size = <32768>; +- i-tlb-sets = <1>; +- i-tlb-size = <40>; +- mmu-type = "riscv,sv39"; +- next-level-cache = <&ccache>; +- riscv,isa = "rv64imafdc_zba_zbb"; +- tlb-split; +- +- cpu4_intc: interrupt-controller { +- compatible = "riscv,cpu-intc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- }; +- }; +- +- cpu-map { +- cluster0 { +- core0 { +- cpu = <&S7_0>; +- }; +- +- core1 { +- cpu = <&U74_1>; +- }; +- +- core2 { +- cpu = <&U74_2>; +- }; +- +- core3 { +- cpu = <&U74_3>; +- }; +- +- core4 { +- cpu = <&U74_4>; +- }; +- }; +- }; +- }; +- +- timer { +- compatible = "riscv,timer"; +- interrupts-extended = <&cpu0_intc 5>, +- <&cpu1_intc 5>, +- <&cpu2_intc 5>, +- <&cpu3_intc 5>, +- <&cpu4_intc 5>; +- }; +- +- osc: oscillator { +- compatible = "fixed-clock"; +- clock-output-names = "osc"; +- #clock-cells = <0>; +- }; +- +- rtc_osc: rtc-oscillator { +- compatible = "fixed-clock"; +- clock-output-names = "rtc_osc"; +- #clock-cells = <0>; +- }; +- +- gmac0_rmii_refin: gmac0-rmii-refin-clock { +- compatible = "fixed-clock"; +- clock-output-names = "gmac0_rmii_refin"; +- #clock-cells = <0>; +- }; +- +- gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { +- compatible = "fixed-clock"; +- clock-output-names = "gmac0_rgmii_rxin"; +- #clock-cells = <0>; +- }; +- +- gmac1_rmii_refin: gmac1-rmii-refin-clock { +- compatible = "fixed-clock"; +- clock-output-names = "gmac1_rmii_refin"; +- #clock-cells = <0>; +- }; +- +- gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { +- compatible = "fixed-clock"; +- clock-output-names = "gmac1_rgmii_rxin"; +- #clock-cells = <0>; +- }; +- +- i2stx_bclk_ext: i2stx-bclk-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "i2stx_bclk_ext"; +- #clock-cells = <0>; +- }; +- +- i2stx_lrck_ext: i2stx-lrck-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "i2stx_lrck_ext"; +- #clock-cells = <0>; +- }; +- +- i2srx_bclk_ext: i2srx-bclk-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "i2srx_bclk_ext"; +- #clock-cells = <0>; +- }; +- +- i2srx_lrck_ext: i2srx-lrck-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "i2srx_lrck_ext"; +- #clock-cells = <0>; +- }; +- +- tdm_ext: tdm-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "tdm_ext"; +- #clock-cells = <0>; +- }; +- +- mclk_ext: mclk-ext-clock { +- compatible = "fixed-clock"; +- clock-output-names = "mclk_ext"; +- #clock-cells = <0>; +- }; +- +- stmmac_axi_setup: stmmac-axi-config { +- snps,lpi_en; +- snps,wr_osr_lmt = <4>; +- snps,rd_osr_lmt = <4>; +- snps,blen = <256 128 64 32 0 0 0>; +- }; +- +- soc { +- compatible = "simple-bus"; +- interrupt-parent = <&plic>; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; +- +- clint: timer@2000000 { +- compatible = "starfive,jh7110-clint", "sifive,clint0"; +- reg = <0x0 0x2000000 0x0 0x10000>; +- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, +- <&cpu1_intc 3>, <&cpu1_intc 7>, +- <&cpu2_intc 3>, <&cpu2_intc 7>, +- <&cpu3_intc 3>, <&cpu3_intc 7>, +- <&cpu4_intc 3>, <&cpu4_intc 7>; +- }; +- +- plic: interrupt-controller@c000000 { +- compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; +- reg = <0x0 0xc000000 0x0 0x4000000>; +- interrupts-extended = <&cpu0_intc 11>, +- <&cpu1_intc 11>, <&cpu1_intc 9>, +- <&cpu2_intc 11>, <&cpu2_intc 9>, +- <&cpu3_intc 11>, <&cpu3_intc 9>, +- <&cpu4_intc 11>, <&cpu4_intc 9>; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <0>; +- riscv,ndev = <136>; +- }; +- +- ccache: cache-controller@2010000 { +- compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; +- reg = <0x0 0x2010000 0x0 0x4000>; +- interrupts = <1>, <3>, <4>, <2>; +- cache-block-size = <64>; +- cache-level = <2>; +- cache-sets = <2048>; +- cache-size = <2097152>; +- cache-unified; +- }; +- +- uart0: serial@10000000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x10000000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, +- <&syscrg JH7110_SYSCLK_UART0_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART0_APB>, +- <&syscrg JH7110_SYSRST_UART0_CORE>; +- interrupts = <32>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart1: serial@10010000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x10010000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, +- <&syscrg JH7110_SYSCLK_UART1_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART1_APB>, +- <&syscrg JH7110_SYSRST_UART1_CORE>; +- interrupts = <33>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart2: serial@10020000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x10020000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, +- <&syscrg JH7110_SYSCLK_UART2_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART2_APB>, +- <&syscrg JH7110_SYSRST_UART2_CORE>; +- interrupts = <34>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- i2c0: i2c@10030000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10030000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C0_APB>; +- interrupts = <35>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c1: i2c@10040000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10040000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C1_APB>; +- interrupts = <36>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c2: i2c@10050000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x10050000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C2_APB>; +- interrupts = <37>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- stgcrg: clock-controller@10230000 { +- compatible = "starfive,jh7110-stgcrg"; +- reg = <0x0 0x10230000 0x0 0x10000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- stg_syscon: stg_syscon@10240000 { +- compatible = "starfive,jh7110-stg-syscon","syscon"; +- reg = <0x0 0x10240000 0x0 0x1000>; +- }; +- +- uart3: serial@12000000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x12000000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, +- <&syscrg JH7110_SYSCLK_UART3_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART3_APB>, +- <&syscrg JH7110_SYSRST_UART3_CORE>; +- interrupts = <45>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart4: serial@12010000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x12010000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, +- <&syscrg JH7110_SYSCLK_UART4_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART4_APB>, +- <&syscrg JH7110_SYSRST_UART4_CORE>; +- interrupts = <46>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- uart5: serial@12020000 { +- compatible = "snps,dw-apb-uart"; +- reg = <0x0 0x12020000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, +- <&syscrg JH7110_SYSCLK_UART5_APB>; +- clock-names = "baudclk", "apb_pclk"; +- resets = <&syscrg JH7110_SYSRST_UART5_APB>, +- <&syscrg JH7110_SYSRST_UART5_CORE>; +- interrupts = <47>; +- reg-io-width = <4>; +- reg-shift = <2>; +- status = "disabled"; +- }; +- +- i2c3: i2c@12030000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x12030000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C3_APB>; +- interrupts = <48>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c4: i2c@12040000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x12040000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C4_APB>; +- interrupts = <49>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c5: i2c@12050000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x12050000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C5_APB>; +- interrupts = <50>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- i2c6: i2c@12060000 { +- compatible = "snps,designware-i2c"; +- reg = <0x0 0x12060000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; +- clock-names = "ref"; +- resets = <&syscrg JH7110_SYSRST_I2C6_APB>; +- interrupts = <51>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; +- +- power-controller@17030000 { +- compatible = "starfive,jh7110-pmu"; +- reg = <0x0 0x17030000 0x0 0x10000>; +- interrupts = <111>; +- }; +- +- qspi: spi@13010000 { +- compatible = "cdns,qspi-nor"; +- reg = <0x0 0x13010000 0x0 0x10000 +- 0x0 0x21000000 0x0 0x400000>; +- clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; +- clock-names = "clk_ref"; +- resets = <&syscrg JH7110_SYSRST_QSPI_APB>, +- <&syscrg JH7110_SYSRST_QSPI_AHB>, +- <&syscrg JH7110_SYSRST_QSPI_REF>; +- reset-names = "rst_apb", "rst_ahb", "rst_ref"; +- cdns,fifo-depth = <256>; +- cdns,fifo-width = <4>; +- #address-cells = <1>; +- #size-cells = <0>; +- }; +- +- syscrg: clock-controller@13020000 { +- compatible = "starfive,jh7110-syscrg"; +- reg = <0x0 0x13020000 0x0 0x10000>; +- clocks = <&osc>, <&gmac1_rmii_refin>, +- <&gmac1_rgmii_rxin>, +- <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, +- <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, +- <&tdm_ext>, <&mclk_ext>, +- <&pllclk JH7110_SYSCLK_PLL0_OUT>, +- <&pllclk JH7110_SYSCLK_PLL1_OUT>, +- <&pllclk JH7110_SYSCLK_PLL2_OUT>; +- clock-names = "osc", "gmac1_rmii_refin", +- "gmac1_rgmii_rxin", +- "i2stx_bclk_ext", "i2stx_lrck_ext", +- "i2srx_bclk_ext", "i2srx_lrck_ext", +- "tdm_ext", "mclk_ext", +- "pll0_out", "pll1_out", "pll2_out"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- sys_syscon: sys_syscon@13030000 { +- compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; +- reg = <0x0 0x13030000 0x0 0x1000>; +- +- pllclk: clock-controller { +- compatible = "starfive,jh7110-pll"; +- clocks = <&osc>; +- #clock-cells = <1>; +- }; +- }; +- +- sysgpio: pinctrl@13040000 { +- compatible = "starfive,jh7110-sys-pinctrl"; +- reg = <0x0 0x13040000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; +- resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; +- interrupts = <86>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- watchdog@13070000 { +- compatible = "starfive,jh7110-wdt"; +- reg = <0x0 0x13070000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, +- <&syscrg JH7110_SYSCLK_WDT_CORE>; +- clock-names = "apb", "core"; +- resets = <&syscrg JH7110_SYSRST_WDT_APB>, +- <&syscrg JH7110_SYSRST_WDT_CORE>; +- }; +- +- mmc0: mmc@16010000 { +- compatible = "starfive,jh7110-mmc"; +- reg = <0x0 0x16010000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, +- <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; +- clock-names = "biu", "ciu"; +- resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; +- reset-names = "reset"; +- interrupts = <74>; +- fifo-depth = <32>; +- fifo-watermark-aligned; +- data-addr = <0>; +- starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; +- status = "disabled"; +- }; +- +- mmc1: mmc@16020000 { +- compatible = "starfive,jh7110-mmc"; +- reg = <0x0 0x16020000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, +- <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; +- clock-names = "biu", "ciu"; +- resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; +- reset-names = "reset"; +- interrupts = <75>; +- fifo-depth = <32>; +- fifo-watermark-aligned; +- data-addr = <0>; +- starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; +- status = "disabled"; +- }; +- +- gmac0: ethernet@16030000 { +- compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; +- reg = <0x0 0x16030000 0x0 0x10000>; +- clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, +- <&aoncrg JH7110_AONCLK_GMAC0_AHB>, +- <&syscrg JH7110_SYSCLK_GMAC0_PTP>, +- <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, +- <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; +- clock-names = "stmmaceth", "pclk", "ptp_ref", +- "tx", "gtx"; +- resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, +- <&aoncrg JH7110_AONRST_GMAC0_AHB>; +- reset-names = "stmmaceth", "ahb"; +- interrupts = <7>, <6>, <5>; +- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; +- snps,multicast-filter-bins = <64>; +- snps,perfect-filter-entries = <8>; +- rx-fifo-depth = <2048>; +- tx-fifo-depth = <2048>; +- snps,fixed-burst; +- snps,no-pbl-x8; +- snps,force_thresh_dma_mode; +- snps,axi-config = <&stmmac_axi_setup>; +- snps,tso; +- snps,en-tx-lpi-clockgating; +- snps,txpbl = <16>; +- snps,rxpbl = <16>; +- starfive,syscon = <&aon_syscon 0xc 0x12>; +- status = "disabled"; +- }; +- +- gmac1: ethernet@16040000 { +- compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; +- reg = <0x0 0x16040000 0x0 0x10000>; +- clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, +- <&syscrg JH7110_SYSCLK_GMAC1_AHB>, +- <&syscrg JH7110_SYSCLK_GMAC1_PTP>, +- <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, +- <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; +- clock-names = "stmmaceth", "pclk", "ptp_ref", +- "tx", "gtx"; +- resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, +- <&syscrg JH7110_SYSRST_GMAC1_AHB>; +- reset-names = "stmmaceth", "ahb"; +- interrupts = <78>, <77>, <76>; +- interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; +- snps,multicast-filter-bins = <64>; +- snps,perfect-filter-entries = <8>; +- rx-fifo-depth = <2048>; +- tx-fifo-depth = <2048>; +- snps,fixed-burst; +- snps,no-pbl-x8; +- snps,force_thresh_dma_mode; +- snps,axi-config = <&stmmac_axi_setup>; +- snps,tso; +- snps,en-tx-lpi-clockgating; +- snps,txpbl = <16>; +- snps,rxpbl = <16>; +- starfive,syscon = <&sys_syscon 0x90 0x2>; +- status = "disabled"; +- }; +- +- rng: rng@1600c000 { +- compatible = "starfive,jh7110-trng"; +- reg = <0x0 0x1600C000 0x0 0x4000>; +- clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, +- <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; +- clock-names = "hclk", "ahb"; +- resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; +- interrupts = <30>; +- }; +- +- aoncrg: clock-controller@17000000 { +- compatible = "starfive,jh7110-aoncrg"; +- reg = <0x0 0x17000000 0x0 0x10000>; +- clocks = <&osc>, <&rtc_osc>, +- <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, +- <&syscrg JH7110_SYSCLK_STG_AXIAHB>, +- <&syscrg JH7110_SYSCLK_APB_BUS>, +- <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; +- clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", +- "gmac0_rgmii_rxin", "stg_axiahb", +- "apb_bus", "gmac0_gtxclk"; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- aon_syscon: aon_syscon@17010000 { +- compatible = "starfive,jh7110-aon-syscon","syscon"; +- reg = <0x0 0x17010000 0x0 0x1000>; +- }; +- +- aongpio: pinctrl@17020000 { +- compatible = "starfive,jh7110-aon-pinctrl"; +- reg = <0x0 0x17020000 0x0 0x10000>; +- resets = <&aoncrg JH7110_AONRST_IOMUX>; +- interrupts = <85>; +- interrupt-controller; +- #interrupt-cells = <2>; +- gpio-controller; +- #gpio-cells = <2>; +- }; +- +- pcie0: pcie@2b000000 { +- compatible = "starfive,jh7110-pcie"; +- reg = <0x0 0x2b000000 0x0 0x1000000 +- 0x9 0x40000000 0x0 0x10000000>; +- reg-names = "reg", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, +- <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; +- interrupts = <56>; +- interrupt-parent = <&plic>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, +- <0x0 0x0 0x0 0x2 &plic 0x2>, +- <0x0 0x0 0x0 0x3 &plic 0x3>, +- <0x0 0x0 0x0 0x4 &plic 0x4>; +- msi-parent = <&plic>; +- device_type = "pci"; +- starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; +- bus-range = <0x0 0xff>; +- clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, +- <&stgcrg JH7110_STGCLK_PCIE0_TL>, +- <&stgcrg JH7110_STGCLK_PCIE0_AXI>, +- <&stgcrg JH7110_STGCLK_PCIE0_APB>; +- clock-names = "noc", "tl", "axi", "apb"; +- resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, +- <&stgcrg JH7110_STGRST_PCIE0_SLV0>, +- <&stgcrg JH7110_STGRST_PCIE0_SLV>, +- <&stgcrg JH7110_STGRST_PCIE0_BRG>, +- <&stgcrg JH7110_STGRST_PCIE0_CORE>, +- <&stgcrg JH7110_STGRST_PCIE0_APB>; +- reset-names = "mst0", "slv0", "slv", "brg", +- "core", "apb"; +- status = "disabled"; +- }; +- +- pcie1: pcie@2c000000 { +- compatible = "starfive,jh7110-pcie"; +- reg = <0x0 0x2c000000 0x0 0x1000000 +- 0x9 0xc0000000 0x0 0x10000000>; +- reg-names = "reg", "config"; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, +- <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; +- interrupts = <57>; +- interrupt-parent = <&plic>; +- interrupt-map-mask = <0x0 0x0 0x0 0x7>; +- interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, +- <0x0 0x0 0x0 0x2 &plic 0x2>, +- <0x0 0x0 0x0 0x3 &plic 0x3>, +- <0x0 0x0 0x0 0x4 &plic 0x4>; +- msi-parent = <&plic>; +- device_type = "pci"; +- starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; +- bus-range = <0x0 0xff>; +- clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, +- <&stgcrg JH7110_STGCLK_PCIE1_TL>, +- <&stgcrg JH7110_STGCLK_PCIE1_AXI>, +- <&stgcrg JH7110_STGCLK_PCIE1_APB>; +- clock-names = "noc", "tl", "axi", "apb"; +- resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, +- <&stgcrg JH7110_STGRST_PCIE1_SLV0>, +- <&stgcrg JH7110_STGRST_PCIE1_SLV>, +- <&stgcrg JH7110_STGRST_PCIE1_BRG>, +- <&stgcrg JH7110_STGRST_PCIE1_CORE>, +- <&stgcrg JH7110_STGRST_PCIE1_APB>; +- reset-names = "mst0", "slv0", "slv", "brg", +- "core", "apb"; +- status = "disabled"; +- }; +- }; +-}; +diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig +index 1c70d1d4b70..389adb5e55b 100644 +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=100000000 + CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0xf0000 + CONFIG_SPL_DM_SPI=y +-CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" ++CONFIG_DEFAULT_DEVICE_TREE="starfive/jh7110-starfive-visionfive-2-v1.3b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_DM_RESET=y + CONFIG_SPL_MMC=y +diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c +index 6d2bfb3ecb7..f8af17227c5 100644 +--- a/drivers/clk/starfive/clk-jh7110-pll.c ++++ b/drivers/clk/starfive/clk-jh7110-pll.c +@@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev) + if (sysreg == FDT_ADDR_T_NONE) + return -EINVAL; + +- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), ++ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT), + starfive_jh7110_pll("pll0_out", "oscillator", reg, + (void __iomem *)sysreg, &starfive_jh7110_pll0)); +- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), ++ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT), + starfive_jh7110_pll("pll1_out", "oscillator", reg, + (void __iomem *)sysreg, &starfive_jh7110_pll1)); +- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), ++ clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT), + starfive_jh7110_pll("pll2_out", "oscillator", reg, + (void __iomem *)sysreg, &starfive_jh7110_pll2)); + +diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c +index 191da75d7ba..6387e949d50 100644 +--- a/drivers/clk/starfive/clk-jh7110.c ++++ b/drivers/clk/starfive/clk-jh7110.c +@@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev) + { + struct jh7110_clk_priv *priv = dev_get_priv(dev); + +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB), + starfive_clk_gate(priv->reg, + "usb_apb", "apb_bus", +- OFFSET(JH7110_STGCLK_USB_APB))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB), ++ OFFSET(JH7110_STGCLK_USB0_APB))); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB), + starfive_clk_gate(priv->reg, + "usb_utmi_apb", "apb_bus", +- OFFSET(JH7110_STGCLK_USB_UTMI_APB))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI), ++ OFFSET(JH7110_STGCLK_USB0_UTMI_APB))); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI), + starfive_clk_gate(priv->reg, + "usb_axi", "stg_axiahb", +- OFFSET(JH7110_STGCLK_USB_AXI))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM), ++ OFFSET(JH7110_STGCLK_USB0_AXI))); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM), + starfive_clk_gate_divider(priv->reg, + "usb_lpm", "oscillator", +- OFFSET(JH7110_STGCLK_USB_LPM), 2)); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB), ++ OFFSET(JH7110_STGCLK_USB0_LPM), 2)); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB), + starfive_clk_gate_divider(priv->reg, + "usb_stb", "oscillator", +- OFFSET(JH7110_STGCLK_USB_STB), 3)); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125), ++ OFFSET(JH7110_STGCLK_USB0_STB), 3)); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125), + starfive_clk_gate(priv->reg, + "usb_app_125", "usb_125m", +- OFFSET(JH7110_STGCLK_USB_APP_125))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK), ++ OFFSET(JH7110_STGCLK_USB0_APP_125))); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK), + starfive_clk_divider(priv->reg, "usb_refclk", "oscillator", +- OFFSET(JH7110_STGCLK_USB_REFCLK), 2)); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI), ++ OFFSET(JH7110_STGCLK_USB0_REFCLK), 2)); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0), + starfive_clk_gate(priv->reg, + "pcie0_axi", "stg_axiahb", +- OFFSET(JH7110_STGCLK_PCIE0_AXI))); ++ OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB), + starfive_clk_gate(priv->reg, + "pcie0_apb", "apb_bus", +@@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev) + starfive_clk_gate(priv->reg, + "pcie0_tl", "stg_axiahb", + OFFSET(JH7110_STGCLK_PCIE0_TL))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI), ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0), + starfive_clk_gate(priv->reg, + "pcie1_axi", "stg_axiahb", +- OFFSET(JH7110_STGCLK_PCIE1_AXI))); ++ OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB), + starfive_clk_gate(priv->reg, + "pcie1_apb", "apb_bus", +@@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev) + OFFSET(JH7110_STGCLK_PCIE1_TL))); + + /* Security clocks */ +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB), + starfive_clk_gate(priv->reg, + "sec_ahb", "stg_axiahb", +- OFFSET(JH7110_STGCLK_SEC_HCLK))); +- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), ++ OFFSET(JH7110_STGCLK_SEC_AHB))); ++ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB), + starfive_clk_gate(priv->reg, + "sec_misc_ahb", "stg_axiahb", +- OFFSET(JH7110_STGCLK_SEC_MISCAHB))); ++ OFFSET(JH7110_STGCLK_SEC_MISC_AHB))); + + return 0; + } +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +deleted file mode 100644 +index b51e3829ff4..00000000000 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ /dev/null +@@ -1,258 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2022 StarFive Technology Co., Ltd. +- * +- * Author: Yanhong Wang +- */ +- +-#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ +-#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ +- +-#define JH7110_SYSCLK_PLL0_OUT 0 +-#define JH7110_SYSCLK_PLL1_OUT 1 +-#define JH7110_SYSCLK_PLL2_OUT 2 +-#define JH7110_PLLCLK_END 3 +- +-#define JH7110_SYSCLK_CPU_ROOT 0 +-#define JH7110_SYSCLK_CPU_CORE 1 +-#define JH7110_SYSCLK_CPU_BUS 2 +-#define JH7110_SYSCLK_GPU_ROOT 3 +-#define JH7110_SYSCLK_PERH_ROOT 4 +-#define JH7110_SYSCLK_BUS_ROOT 5 +-#define JH7110_SYSCLK_NOCSTG_BUS 6 +-#define JH7110_SYSCLK_AXI_CFG0 7 +-#define JH7110_SYSCLK_STG_AXIAHB 8 +-#define JH7110_SYSCLK_AHB0 9 +-#define JH7110_SYSCLK_AHB1 10 +-#define JH7110_SYSCLK_APB_BUS 11 +-#define JH7110_SYSCLK_APB0 12 +-#define JH7110_SYSCLK_PLL0_DIV2 13 +-#define JH7110_SYSCLK_PLL1_DIV2 14 +-#define JH7110_SYSCLK_PLL2_DIV2 15 +-#define JH7110_SYSCLK_AUDIO_ROOT 16 +-#define JH7110_SYSCLK_MCLK_INNER 17 +-#define JH7110_SYSCLK_MCLK 18 +-#define JH7110_SYSCLK_MCLK_OUT 19 +-#define JH7110_SYSCLK_ISP_2X 20 +-#define JH7110_SYSCLK_ISP_AXI 21 +-#define JH7110_SYSCLK_GCLK0 22 +-#define JH7110_SYSCLK_GCLK1 23 +-#define JH7110_SYSCLK_GCLK2 24 +-#define JH7110_SYSCLK_CORE 25 +-#define JH7110_SYSCLK_CORE1 26 +-#define JH7110_SYSCLK_CORE2 27 +-#define JH7110_SYSCLK_CORE3 28 +-#define JH7110_SYSCLK_CORE4 29 +-#define JH7110_SYSCLK_DEBUG 30 +-#define JH7110_SYSCLK_RTC_TOGGLE 31 +-#define JH7110_SYSCLK_TRACE0 32 +-#define JH7110_SYSCLK_TRACE1 33 +-#define JH7110_SYSCLK_TRACE2 34 +-#define JH7110_SYSCLK_TRACE3 35 +-#define JH7110_SYSCLK_TRACE4 36 +-#define JH7110_SYSCLK_TRACE_COM 37 +-#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +-#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +-#define JH7110_SYSCLK_OSC_DIV2 40 +-#define JH7110_SYSCLK_PLL1_DIV4 41 +-#define JH7110_SYSCLK_PLL1_DIV8 42 +-#define JH7110_SYSCLK_DDR_BUS 43 +-#define JH7110_SYSCLK_DDR_AXI 44 +-#define JH7110_SYSCLK_GPU_CORE 45 +-#define JH7110_SYSCLK_GPU_CORE_CLK 46 +-#define JH7110_SYSCLK_GPU_SYS_CLK 47 +-#define JH7110_SYSCLK_GPU_APB 48 +-#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +-#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +-#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 +-#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 +-#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +-#define JH7110_SYSCLK_HIFI4_CORE 54 +-#define JH7110_SYSCLK_HIFI4_AXI 55 +-#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 +-#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 +-#define JH7110_SYSCLK_VOUT_SRC 58 +-#define JH7110_SYSCLK_VOUT_AXI 59 +-#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 +-#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 +-#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 +-#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 +-#define JH7110_SYSCLK_JPEGC_AXI 65 +-#define JH7110_SYSCLK_CODAJ12_AXI 66 +-#define JH7110_SYSCLK_CODAJ12_CORE 67 +-#define JH7110_SYSCLK_CODAJ12_APB 68 +-#define JH7110_SYSCLK_VDEC_AXI 69 +-#define JH7110_SYSCLK_WAVE511_AXI 70 +-#define JH7110_SYSCLK_WAVE511_BPU 71 +-#define JH7110_SYSCLK_WAVE511_VCE 72 +-#define JH7110_SYSCLK_WAVE511_APB 73 +-#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 +-#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 +-#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +-#define JH7110_SYSCLK_VENC_AXI 77 +-#define JH7110_SYSCLK_WAVE420L_AXI 78 +-#define JH7110_SYSCLK_WAVE420L_BPU 79 +-#define JH7110_SYSCLK_WAVE420L_VCE 80 +-#define JH7110_SYSCLK_WAVE420L_APB 81 +-#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 +-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 +-#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 +-#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 +-#define JH7110_SYSCLK_AXIMEM2_AXI 86 +-#define JH7110_SYSCLK_QSPI_AHB 87 +-#define JH7110_SYSCLK_QSPI_APB 88 +-#define JH7110_SYSCLK_QSPI_REF_SRC 89 +-#define JH7110_SYSCLK_QSPI_REF 90 +-#define JH7110_SYSCLK_SDIO0_AHB 91 +-#define JH7110_SYSCLK_SDIO1_AHB 92 +-#define JH7110_SYSCLK_SDIO0_SDCARD 93 +-#define JH7110_SYSCLK_SDIO1_SDCARD 94 +-#define JH7110_SYSCLK_USB_125M 95 +-#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 +-#define JH7110_SYSCLK_GMAC1_AHB 97 +-#define JH7110_SYSCLK_GMAC1_AXI 98 +-#define JH7110_SYSCLK_GMAC_SRC 99 +-#define JH7110_SYSCLK_GMAC1_GTXCLK 100 +-#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 +-#define JH7110_SYSCLK_GMAC1_PTP 102 +-#define JH7110_SYSCLK_GMAC1_RX 103 +-#define JH7110_SYSCLK_GMAC1_RX_INV 104 +-#define JH7110_SYSCLK_GMAC1_TX 105 +-#define JH7110_SYSCLK_GMAC1_TX_INV 106 +-#define JH7110_SYSCLK_GMAC1_GTXC 107 +-#define JH7110_SYSCLK_GMAC0_GTXCLK 108 +-#define JH7110_SYSCLK_GMAC0_PTP 109 +-#define JH7110_SYSCLK_GMAC_PHY 110 +-#define JH7110_SYSCLK_GMAC0_GTXC 111 +-#define JH7110_SYSCLK_IOMUX_APB 112 +-#define JH7110_SYSCLK_MAILBOX 113 +-#define JH7110_SYSCLK_INT_CTRL_APB 114 +-#define JH7110_SYSCLK_CAN0_APB 115 +-#define JH7110_SYSCLK_CAN0_TIMER 116 +-#define JH7110_SYSCLK_CAN0_CAN 117 +-#define JH7110_SYSCLK_CAN1_APB 118 +-#define JH7110_SYSCLK_CAN1_TIMER 119 +-#define JH7110_SYSCLK_CAN1_CAN 120 +-#define JH7110_SYSCLK_PWM_APB 121 +-#define JH7110_SYSCLK_WDT_APB 122 +-#define JH7110_SYSCLK_WDT_CORE 123 +-#define JH7110_SYSCLK_TIMER_APB 124 +-#define JH7110_SYSCLK_TIMER0 125 +-#define JH7110_SYSCLK_TIMER1 126 +-#define JH7110_SYSCLK_TIMER2 127 +-#define JH7110_SYSCLK_TIMER3 128 +-#define JH7110_SYSCLK_TEMP_APB 129 +-#define JH7110_SYSCLK_TEMP_CORE 130 +-#define JH7110_SYSCLK_SPI0_APB 131 +-#define JH7110_SYSCLK_SPI1_APB 132 +-#define JH7110_SYSCLK_SPI2_APB 133 +-#define JH7110_SYSCLK_SPI3_APB 134 +-#define JH7110_SYSCLK_SPI4_APB 135 +-#define JH7110_SYSCLK_SPI5_APB 136 +-#define JH7110_SYSCLK_SPI6_APB 137 +-#define JH7110_SYSCLK_I2C0_APB 138 +-#define JH7110_SYSCLK_I2C1_APB 139 +-#define JH7110_SYSCLK_I2C2_APB 140 +-#define JH7110_SYSCLK_I2C3_APB 141 +-#define JH7110_SYSCLK_I2C4_APB 142 +-#define JH7110_SYSCLK_I2C5_APB 143 +-#define JH7110_SYSCLK_I2C6_APB 144 +-#define JH7110_SYSCLK_UART0_APB 145 +-#define JH7110_SYSCLK_UART0_CORE 146 +-#define JH7110_SYSCLK_UART1_APB 147 +-#define JH7110_SYSCLK_UART1_CORE 148 +-#define JH7110_SYSCLK_UART2_APB 149 +-#define JH7110_SYSCLK_UART2_CORE 150 +-#define JH7110_SYSCLK_UART3_APB 151 +-#define JH7110_SYSCLK_UART3_CORE 152 +-#define JH7110_SYSCLK_UART4_APB 153 +-#define JH7110_SYSCLK_UART4_CORE 154 +-#define JH7110_SYSCLK_UART5_APB 155 +-#define JH7110_SYSCLK_UART5_CORE 156 +-#define JH7110_SYSCLK_PWMDAC_APB 157 +-#define JH7110_SYSCLK_PWMDAC_CORE 158 +-#define JH7110_SYSCLK_SPDIF_APB 159 +-#define JH7110_SYSCLK_SPDIF_CORE 160 +-#define JH7110_SYSCLK_I2STX0_APB 161 +-#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 +-#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 +-#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 +-#define JH7110_SYSCLK_I2STX0_BCLK 165 +-#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 +-#define JH7110_SYSCLK_I2STX0_LRCK 167 +-#define JH7110_SYSCLK_I2STX1_APB 168 +-#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 +-#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 +-#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 +-#define JH7110_SYSCLK_I2STX1_BCLK 172 +-#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 +-#define JH7110_SYSCLK_I2STX1_LRCK 174 +-#define JH7110_SYSCLK_I2SRX_APB 175 +-#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 +-#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 +-#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 +-#define JH7110_SYSCLK_I2SRX_BCLK 179 +-#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 +-#define JH7110_SYSCLK_I2SRX_LRCK 181 +-#define JH7110_SYSCLK_PDM_DMIC 182 +-#define JH7110_SYSCLK_PDM_APB 183 +-#define JH7110_SYSCLK_TDM_AHB 184 +-#define JH7110_SYSCLK_TDM_APB 185 +-#define JH7110_SYSCLK_TDM_INTERNAL 186 +-#define JH7110_SYSCLK_TDM_CLK_TDM 187 +-#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 +-#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 +- +-#define JH7110_SYSCLK_END 190 +- +-#define JH7110_AONCLK_OSC_DIV4 0 +-#define JH7110_AONCLK_APB_FUNC 1 +-#define JH7110_AONCLK_GMAC0_AHB 2 +-#define JH7110_AONCLK_GMAC0_AXI 3 +-#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +-#define JH7110_AONCLK_GMAC0_TX 5 +-#define JH7110_AONCLK_GMAC0_TX_INV 6 +-#define JH7110_AONCLK_GMAC0_RX 7 +-#define JH7110_AONCLK_GMAC0_RX_INV 8 +-#define JH7110_AONCLK_OTPC_APB 9 +-#define JH7110_AONCLK_RTC_APB 10 +-#define JH7110_AONCLK_RTC_INTERNAL 11 +-#define JH7110_AONCLK_RTC_32K 12 +-#define JH7110_AONCLK_RTC_CAL 13 +- +-#define JH7110_AONCLK_END 14 +- +-#define JH7110_STGCLK_HIFI4_CORE 0 +-#define JH7110_STGCLK_USB_APB 1 +-#define JH7110_STGCLK_USB_UTMI_APB 2 +-#define JH7110_STGCLK_USB_AXI 3 +-#define JH7110_STGCLK_USB_LPM 4 +-#define JH7110_STGCLK_USB_STB 5 +-#define JH7110_STGCLK_USB_APP_125 6 +-#define JH7110_STGCLK_USB_REFCLK 7 +-#define JH7110_STGCLK_PCIE0_AXI 8 +-#define JH7110_STGCLK_PCIE0_APB 9 +-#define JH7110_STGCLK_PCIE0_TL 10 +-#define JH7110_STGCLK_PCIE1_AXI 11 +-#define JH7110_STGCLK_PCIE1_APB 12 +-#define JH7110_STGCLK_PCIE1_TL 13 +-#define JH7110_STGCLK_PCIE01_MAIN 14 +-#define JH7110_STGCLK_SEC_HCLK 15 +-#define JH7110_STGCLK_SEC_MISCAHB 16 +-#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 +-#define JH7110_STGCLK_MTRX_GRP0_BUS 18 +-#define JH7110_STGCLK_MTRX_GRP0_STG 19 +-#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 +-#define JH7110_STGCLK_MTRX_GRP1_BUS 21 +-#define JH7110_STGCLK_MTRX_GRP1_STG 22 +-#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 +-#define JH7110_STGCLK_E2_RTC 24 +-#define JH7110_STGCLK_E2_CORE 25 +-#define JH7110_STGCLK_E2_DBG 26 +-#define JH7110_STGCLK_DMA1P_AXI 27 +-#define JH7110_STGCLK_DMA1P_AHB 28 +- +-#define JH7110_STGCLK_END 29 +- +-#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +deleted file mode 100644 +index 1d596581da7..00000000000 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* +- * Copyright (C) 2022 StarFive Technology Co., Ltd. +- * +- * Author: Yanhong Wang +- */ +- +-#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +-#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ +- +-/* SYSCRG resets */ +-#define JH7110_SYSRST_JTAG2APB 0 +-#define JH7110_SYSRST_SYSCON 1 +-#define JH7110_SYSRST_IOMUX_APB 2 +-#define JH7110_SYSRST_BUS 3 +-#define JH7110_SYSRST_DEBUG 4 +-#define JH7110_SYSRST_CORE0 5 +-#define JH7110_SYSRST_CORE1 6 +-#define JH7110_SYSRST_CORE2 7 +-#define JH7110_SYSRST_CORE3 8 +-#define JH7110_SYSRST_CORE4 9 +-#define JH7110_SYSRST_CORE0_ST 10 +-#define JH7110_SYSRST_CORE1_ST 11 +-#define JH7110_SYSRST_CORE2_ST 12 +-#define JH7110_SYSRST_CORE3_ST 13 +-#define JH7110_SYSRST_CORE4_ST 14 +-#define JH7110_SYSRST_TRACE0 15 +-#define JH7110_SYSRST_TRACE1 16 +-#define JH7110_SYSRST_TRACE2 17 +-#define JH7110_SYSRST_TRACE3 18 +-#define JH7110_SYSRST_TRACE4 19 +-#define JH7110_SYSRST_TRACE_COM 20 +-#define JH7110_SYSRST_GPU_APB 21 +-#define JH7110_SYSRST_GPU_DOMA 22 +-#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 +-#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +-#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +-#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +-#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +-#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +-#define JH7110_SYSRST_NOC_BUS_DDRC 29 +-#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +-#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 +- +-#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +-#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 +-#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 +-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 +-#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 +-#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 +-#define JH7110_SYSRST_DDR_AXI 38 +-#define JH7110_SYSRST_DDR_OSC 39 +-#define JH7110_SYSRST_DDR_APB 40 +-#define JH7110_SYSRST_DOM_ISP_TOP_N 41 +-#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 +-#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 +-#define JH7110_SYSRST_CODAJ12_AXI 44 +-#define JH7110_SYSRST_CODAJ12_CORE 45 +-#define JH7110_SYSRST_CODAJ12_APB 46 +-#define JH7110_SYSRST_WAVE511_AXI 47 +-#define JH7110_SYSRST_WAVE511_BPU 48 +-#define JH7110_SYSRST_WAVE511_VCE 49 +-#define JH7110_SYSRST_WAVE511_APB 50 +-#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 +-#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 +-#define JH7110_SYSRST_AXIMEM0_AXI 53 +-#define JH7110_SYSRST_WAVE420L_AXI 54 +-#define JH7110_SYSRST_WAVE420L_BPU 55 +-#define JH7110_SYSRST_WAVE420L_VCE 56 +-#define JH7110_SYSRST_WAVE420L_APB 57 +-#define JH7110_SYSRST_AXIMEM1_AXI 58 +-#define JH7110_SYSRST_AXIMEM2_AXI 59 +-#define JH7110_SYSRST_INTMEM 60 +-#define JH7110_SYSRST_QSPI_AHB 61 +-#define JH7110_SYSRST_QSPI_APB 62 +-#define JH7110_SYSRST_QSPI_REF 63 +- +-#define JH7110_SYSRST_SDIO0_AHB 64 +-#define JH7110_SYSRST_SDIO1_AHB 65 +-#define JH7110_SYSRST_GMAC1_AXI 66 +-#define JH7110_SYSRST_GMAC1_AHB 67 +-#define JH7110_SYSRST_MAILBOX 68 +-#define JH7110_SYSRST_SPI0_APB 69 +-#define JH7110_SYSRST_SPI1_APB 70 +-#define JH7110_SYSRST_SPI2_APB 71 +-#define JH7110_SYSRST_SPI3_APB 72 +-#define JH7110_SYSRST_SPI4_APB 73 +-#define JH7110_SYSRST_SPI5_APB 74 +-#define JH7110_SYSRST_SPI6_APB 75 +-#define JH7110_SYSRST_I2C0_APB 76 +-#define JH7110_SYSRST_I2C1_APB 77 +-#define JH7110_SYSRST_I2C2_APB 78 +-#define JH7110_SYSRST_I2C3_APB 79 +-#define JH7110_SYSRST_I2C4_APB 80 +-#define JH7110_SYSRST_I2C5_APB 81 +-#define JH7110_SYSRST_I2C6_APB 82 +-#define JH7110_SYSRST_UART0_APB 83 +-#define JH7110_SYSRST_UART0_CORE 84 +-#define JH7110_SYSRST_UART1_APB 85 +-#define JH7110_SYSRST_UART1_CORE 86 +-#define JH7110_SYSRST_UART2_APB 87 +-#define JH7110_SYSRST_UART2_CORE 88 +-#define JH7110_SYSRST_UART3_APB 89 +-#define JH7110_SYSRST_UART3_CORE 90 +-#define JH7110_SYSRST_UART4_APB 91 +-#define JH7110_SYSRST_UART4_CORE 92 +-#define JH7110_SYSRST_UART5_APB 93 +-#define JH7110_SYSRST_UART5_CORE 94 +-#define JH7110_SYSRST_SPDIF_APB 95 +- +-#define JH7110_SYSRST_PWMDAC_APB 96 +-#define JH7110_SYSRST_PDM_DMIC 97 +-#define JH7110_SYSRST_PDM_APB 98 +-#define JH7110_SYSRST_I2SRX_APB 99 +-#define JH7110_SYSRST_I2SRX_BCLK 100 +-#define JH7110_SYSRST_I2STX0_APB 101 +-#define JH7110_SYSRST_I2STX0_BCLK 102 +-#define JH7110_SYSRST_I2STX1_APB 103 +-#define JH7110_SYSRST_I2STX1_BCLK 104 +-#define JH7110_SYSRST_TDM_AHB 105 +-#define JH7110_SYSRST_TDM_CORE 106 +-#define JH7110_SYSRST_TDM_APB 107 +-#define JH7110_SYSRST_PWM_APB 108 +-#define JH7110_SYSRST_WDT_APB 109 +-#define JH7110_SYSRST_WDT_CORE 110 +-#define JH7110_SYSRST_CAN0_APB 111 +-#define JH7110_SYSRST_CAN0_CORE 112 +-#define JH7110_SYSRST_CAN0_TIMER 113 +-#define JH7110_SYSRST_CAN1_APB 114 +-#define JH7110_SYSRST_CAN1_CORE 115 +-#define JH7110_SYSRST_CAN1_TIMER 116 +-#define JH7110_SYSRST_TIMER_APB 117 +-#define JH7110_SYSRST_TIMER0 118 +-#define JH7110_SYSRST_TIMER1 119 +-#define JH7110_SYSRST_TIMER2 120 +-#define JH7110_SYSRST_TIMER3 121 +-#define JH7110_SYSRST_INT_CTRL_APB 122 +-#define JH7110_SYSRST_TEMP_APB 123 +-#define JH7110_SYSRST_TEMP_CORE 124 +-#define JH7110_SYSRST_JTAG_CERTIFICATION 125 +- +-#define JH7110_SYSRST_END 126 +- +-/* AONCRG resets */ +-#define JH7110_AONRST_GMAC0_AXI 0 +-#define JH7110_AONRST_GMAC0_AHB 1 +-#define JH7110_AONRST_IOMUX 2 +-#define JH7110_AONRST_PMU_APB 3 +-#define JH7110_AONRST_PMU_WKUP 4 +-#define JH7110_AONRST_RTC_APB 5 +-#define JH7110_AONRST_RTC_CAL 6 +-#define JH7110_AONRST_RTC_32K 7 +- +-#define JH7110_AONRST_END 8 +- +-/* STGCRG resets */ +-#define JH7110_STGRST_SYSCON_PRESETN 0 +-#define JH7110_STGRST_HIFI4_CORE 1 +-#define JH7110_STGRST_HIFI4_AXI 2 +-#define JH7110_STGRST_SEC_TOP_HRESETN 3 +-#define JH7110_STGRST_E24_CORE 4 +-#define JH7110_STGRST_DMA1P_AXI 5 +-#define JH7110_STGRST_DMA1P_AHB 6 +-#define JH7110_STGRST_USB_AXI 7 +-#define JH7110_STGRST_USB_APB 8 +-#define JH7110_STGRST_USB_UTMI_APB 9 +-#define JH7110_STGRST_USB_PWRUP 10 +-#define JH7110_STGRST_PCIE0_MST0 11 +-#define JH7110_STGRST_PCIE0_SLV0 12 +-#define JH7110_STGRST_PCIE0_SLV 13 +-#define JH7110_STGRST_PCIE0_BRG 14 +-#define JH7110_STGRST_PCIE0_CORE 15 +-#define JH7110_STGRST_PCIE0_APB 16 +-#define JH7110_STGRST_PCIE1_MST0 17 +-#define JH7110_STGRST_PCIE1_SLV0 18 +-#define JH7110_STGRST_PCIE1_SLV 19 +-#define JH7110_STGRST_PCIE1_BRG 20 +-#define JH7110_STGRST_PCIE1_CORE 21 +-#define JH7110_STGRST_PCIE1_APB 22 +- +-#define JH7110_STGRST_END 23 +- +-#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */ +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0011-riscv-dts-jh7110-Make-u-boot-device-trees-adapting-t.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0011-riscv-dts-jh7110-Make-u-boot-device-trees-adapting-t.patch --- 2025.01-3/debian/patches/riscv64/starfive/0011-riscv-dts-jh7110-Make-u-boot-device-trees-adapting-t.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0011-riscv-dts-jh7110-Make-u-boot-device-trees-adapting-t.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,155 @@ +From 337af57e2dc2d3e2766f53c31fd6f4f4d31fecaa Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:32 +0800 +Subject: [PATCH 11/27] riscv: dts: jh7110: Make u-boot device trees adapting + to upstream DT + +Add u-boot features to the U-Boot device tree. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: E Shattow +Acked-by: Sumit Garg +Signed-off-by: Hal Feng +--- + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 32 ++++++++++++++++--- + arch/riscv/dts/jh7110-u-boot.dtsi | 25 ++++++++++++--- + 2 files changed, 49 insertions(+), 8 deletions(-) + +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +index 3012466b305..45fada34d2f 100644 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +@@ -6,6 +6,10 @@ + #include "binman.dtsi" + #include "jh7110-u-boot.dtsi" + / { ++ aliases { ++ spi0 = &qspi; ++ }; ++ + chosen { + bootph-pre-ram; + }; +@@ -27,6 +31,9 @@ + + &uart0 { + bootph-pre-ram; ++ reg-offset = <0>; ++ current-speed = <115200>; ++ clock-frequency = <24000000>; + }; + + &mmc0 { +@@ -40,29 +47,43 @@ + &qspi { + bootph-pre-ram; + +- nor-flash@0 { ++ flash@0 { + bootph-pre-ram; ++ cdns,read-delay = <2>; ++ spi-max-frequency = <100000000>; + }; + }; + ++&syscrg { ++ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, ++ <&syscrg JH7110_SYSCLK_BUS_ROOT>, ++ <&syscrg JH7110_SYSCLK_PERH_ROOT>, ++ <&syscrg JH7110_SYSCLK_QSPI_REF>; ++ assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, ++ <&pllclk JH7110_PLLCLK_PLL2_OUT>, ++ <&pllclk JH7110_PLLCLK_PLL2_OUT>, ++ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; ++ assigned-clock-rates = <0>, <0>, <0>, <0>; ++}; ++ + &sysgpio { + bootph-pre-ram; + }; + + &mmc0_pins { + bootph-pre-ram; +- mmc0-pins-rest { ++ rst-pins { + bootph-pre-ram; + }; + }; + + &mmc1_pins { + bootph-pre-ram; +- mmc1-pins0 { ++ clk-pins { + bootph-pre-ram; + }; + +- mmc1-pins1 { ++ mmc-pins { + bootph-pre-ram; + }; + }; +@@ -78,6 +99,9 @@ + bootph-pre-ram; + eeprom@50 { + bootph-pre-ram; ++ compatible = "atmel,24c04"; ++ reg = <0x50>; ++ pagesize = <16>; + }; + }; + +diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi +index 52c1d60859a..ce7d9e16961 100644 +--- a/arch/riscv/dts/jh7110-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-u-boot.dtsi +@@ -46,6 +46,15 @@ + }; + }; + ++ timer { ++ compatible = "riscv,timer"; ++ interrupts-extended = <&cpu0_intc 5>, ++ <&cpu1_intc 5>, ++ <&cpu2_intc 5>, ++ <&cpu3_intc 5>, ++ <&cpu4_intc 5>; ++ }; ++ + soc { + bootph-pre-ram; + +@@ -73,10 +82,22 @@ + bootph-pre-ram; + }; + ++&gmac0_rgmii_rxin { ++ bootph-pre-ram; ++}; ++ + &gmac0_rmii_refin { + bootph-pre-ram; + }; + ++&gmac1_rgmii_rxin { ++ bootph-pre-ram; ++}; ++ ++&gmac1_rmii_refin { ++ bootph-pre-ram; ++}; ++ + &aoncrg { + bootph-pre-ram; + }; +@@ -92,7 +113,3 @@ + &sys_syscon { + bootph-pre-ram; + }; +- +-&S7_0 { +- status = "okay"; +-}; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0012-mmc-dw_mmc-Add-starfive-jh7110-mmc-compatible-to-mat.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0012-mmc-dw_mmc-Add-starfive-jh7110-mmc-compatible-to-mat.patch --- 2025.01-3/debian/patches/riscv64/starfive/0012-mmc-dw_mmc-Add-starfive-jh7110-mmc-compatible-to-mat.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0012-mmc-dw_mmc-Add-starfive-jh7110-mmc-compatible-to-mat.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,29 @@ +From 324d3a5f5f9bac9585ece5886c53ab99a2bf9880 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:33 +0800 +Subject: [PATCH 12/27] mmc: dw_mmc: Add "starfive, jh7110-mmc" compatible to + match upstream DT + +Make the U-Boot JH7110 MMC driver compatible with upstream DT. + +Reviewed-by: Jaehoon Chung +Signed-off-by: Hal Feng +--- + drivers/mmc/snps_dw_mmc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c +index 47ab5654bd6..92880e0ed87 100644 +--- a/drivers/mmc/snps_dw_mmc.c ++++ b/drivers/mmc/snps_dw_mmc.c +@@ -186,6 +186,7 @@ static int snps_dwmmc_bind(struct udevice *dev) + + static const struct udevice_id snps_dwmmc_ids[] = { + { .compatible = "snps,dw-mshc" }, ++ { .compatible = "starfive,jh7110-mmc" }, + { } + }; + +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0013-pcie-starfive-Make-the-driver-compatible-with-upstre.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0013-pcie-starfive-Make-the-driver-compatible-with-upstre.patch --- 2025.01-3/debian/patches/riscv64/starfive/0013-pcie-starfive-Make-the-driver-compatible-with-upstre.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0013-pcie-starfive-Make-the-driver-compatible-with-upstre.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,175 @@ +From 86f9779bda7b971b752d2c5a4aa9f2cbc2fd72f9 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:34 +0800 +Subject: [PATCH 13/27] pcie: starfive: Make the driver compatible with + upstream DT + +There are difference between upstream DT and the old DT +in terms of reg base, reset gpio and syscon. Make the driver +compatible with upstream DT. + +Tested-by: Anand Moon +Tested-by: E Shattow +Signed-off-by: Hal Feng +--- + drivers/pci/pcie_starfive_jh7110.c | 59 +++++++++++++++--------------- + 1 file changed, 30 insertions(+), 29 deletions(-) + +diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c +index 569fbfd35c8..51aca7359ff 100644 +--- a/drivers/pci/pcie_starfive_jh7110.c ++++ b/drivers/pci/pcie_starfive_jh7110.c +@@ -25,13 +25,19 @@ + #include "pcie_plda_common.h" + + /* system control */ +-#define STG_SYSCON_K_RP_NEP_MASK BIT(8) ++#define STG_SYSCON_PCIE0_BASE 0x48 ++#define STG_SYSCON_PCIE1_BASE 0x1f8 ++ ++#define STG_SYSCON_AR_OFFSET 0x78 + #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) + #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 ++#define STG_SYSCON_AW_OFFSET 0x7c + #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) + #define STG_SYSCON_CLKREQ_MASK BIT(22) + #define STG_SYSCON_CKREF_SRC_SHIFT 18 + #define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) ++#define STG_SYSCON_RP_NEP_OFFSET 0xe8 ++#define STG_SYSCON_K_RP_NEP_MASK BIT(8) + + DECLARE_GLOBAL_DATA_PTR; + +@@ -41,9 +47,7 @@ struct starfive_pcie { + struct reset_ctl_bulk rsts; + struct gpio_desc reset_gpio; + struct regmap *regmap; +- u32 stg_arfun; +- u32 stg_awfun; +- u32 stg_rp_nep; ++ unsigned int stg_pcie_base; + }; + + static int starfive_pcie_atr_init(struct starfive_pcie *priv) +@@ -92,7 +96,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) + struct starfive_pcie *priv = dev_get_priv(dev); + struct udevice *syscon; + struct ofnode_phandle_args syscfg_phandle; +- u32 cells[4]; + int ret; + + /* get corresponding syscon phandle */ +@@ -117,20 +120,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) + return -ENODEV; + } + +- /* get syscon register offset */ +- ret = dev_read_u32_array(dev, "starfive,stg-syscon", +- cells, ARRAY_SIZE(cells)); +- if (ret) { +- dev_err(dev, "Get syscon register err %d\n", ret); +- return -EINVAL; +- } +- +- dev_dbg(dev, "Get syscon values: %x, %x, %x\n", +- cells[1], cells[2], cells[3]); +- priv->stg_arfun = cells[1]; +- priv->stg_awfun = cells[2]; +- priv->stg_rp_nep = cells[3]; +- + return 0; + } + +@@ -138,8 +127,9 @@ static int starfive_pcie_parse_dt(struct udevice *dev) + { + struct starfive_pcie *priv = dev_get_priv(dev); + int ret; ++ u32 domain_nr; + +- priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg"); ++ priv->plda.reg_base = (void *)dev_read_addr_name(dev, "apb"); + if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) { + dev_err(dev, "Missing required reg address range\n"); + return -EINVAL; +@@ -147,7 +137,7 @@ static int starfive_pcie_parse_dt(struct udevice *dev) + + priv->plda.cfg_base = + (void *)dev_read_addr_size_name(dev, +- "config", ++ "cfg", + &priv->plda.cfg_size); + if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) { + dev_err(dev, "Missing required config address range"); +@@ -172,7 +162,18 @@ static int starfive_pcie_parse_dt(struct udevice *dev) + return ret; + } + +- ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, ++ ret = dev_read_u32(dev, "linux,pci-domain", &domain_nr); ++ if (ret) { ++ dev_err(dev, "Can't get pci domain: %d\n", ret); ++ return ret; ++ } ++ ++ if (domain_nr == 0) ++ priv->stg_pcie_base = STG_SYSCON_PCIE0_BASE; ++ else ++ priv->stg_pcie_base = STG_SYSCON_PCIE1_BASE; ++ ++ ret = gpio_request_by_name(dev, "perst-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Can't get reset-gpio: %d\n", ret); +@@ -208,12 +209,12 @@ static int starfive_pcie_init_port(struct udevice *dev) + /* Disable physical functions except #0 */ + for (i = 1; i < PLDA_FUNC_NUM; i++) { + regmap_update_bits(priv->regmap, +- priv->stg_arfun, ++ priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, + STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, + (i << PLDA_PHY_FUNC_SHIFT) << + STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); + regmap_update_bits(priv->regmap, +- priv->stg_awfun, ++ priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, + i << PLDA_PHY_FUNC_SHIFT); + +@@ -222,11 +223,11 @@ static int starfive_pcie_init_port(struct udevice *dev) + + /* Disable physical functions */ + regmap_update_bits(priv->regmap, +- priv->stg_arfun, ++ priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, + STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, + 0); + regmap_update_bits(priv->regmap, +- priv->stg_awfun, ++ priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, + 0); + +@@ -273,17 +274,17 @@ static int starfive_pcie_probe(struct udevice *dev) + return ret; + + regmap_update_bits(priv->regmap, +- priv->stg_rp_nep, ++ priv->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, + STG_SYSCON_K_RP_NEP_MASK, + STG_SYSCON_K_RP_NEP_MASK); + + regmap_update_bits(priv->regmap, +- priv->stg_awfun, ++ priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_CKREF_SRC_MASK, + 2 << STG_SYSCON_CKREF_SRC_SHIFT); + + regmap_update_bits(priv->regmap, +- priv->stg_awfun, ++ priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, + STG_SYSCON_CLKREQ_MASK, + STG_SYSCON_CLKREQ_MASK); + +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0014-riscv-dts-jh7110-Move-common-code-to-the-new-jh7110-.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0014-riscv-dts-jh7110-Move-common-code-to-the-new-jh7110-.patch --- 2025.01-3/debian/patches/riscv64/starfive/0014-riscv-dts-jh7110-Move-common-code-to-the-new-jh7110-.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0014-riscv-dts-jh7110-Move-common-code-to-the-new-jh7110-.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,314 @@ +From 8585d0a2ddd3cc7c20d6fd6186868f7a442bdbad Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:35 +0800 +Subject: [PATCH 14/27] riscv: dts: jh7110: Move common code to the new + jh7110-common-u-boot.dtsi + +To support JH7110 based boards besides v1.3B, +add a common dtsi and add common code to it. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: E Shattow +Signed-off-by: Hal Feng +--- + arch/riscv/dts/jh7110-common-u-boot.dtsi | 141 ++++++++++++++++++ + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 137 +---------------- + 2 files changed, 142 insertions(+), 136 deletions(-) + create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi + +diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi +new file mode 100644 +index 00000000000..45fada34d2f +--- /dev/null ++++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi +@@ -0,0 +1,141 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include "binman.dtsi" ++#include "jh7110-u-boot.dtsi" ++/ { ++ aliases { ++ spi0 = &qspi; ++ }; ++ ++ chosen { ++ bootph-pre-ram; ++ }; ++ ++ firmware { ++ spi0 = &qspi; ++ bootph-pre-ram; ++ }; ++ ++ config { ++ bootph-pre-ram; ++ u-boot,spl-payload-offset = <0x100000>; ++ }; ++ ++ memory@40000000 { ++ bootph-pre-ram; ++ }; ++}; ++ ++&uart0 { ++ bootph-pre-ram; ++ reg-offset = <0>; ++ current-speed = <115200>; ++ clock-frequency = <24000000>; ++}; ++ ++&mmc0 { ++ bootph-pre-ram; ++}; ++ ++&mmc1 { ++ bootph-pre-ram; ++}; ++ ++&qspi { ++ bootph-pre-ram; ++ ++ flash@0 { ++ bootph-pre-ram; ++ cdns,read-delay = <2>; ++ spi-max-frequency = <100000000>; ++ }; ++}; ++ ++&syscrg { ++ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, ++ <&syscrg JH7110_SYSCLK_BUS_ROOT>, ++ <&syscrg JH7110_SYSCLK_PERH_ROOT>, ++ <&syscrg JH7110_SYSCLK_QSPI_REF>; ++ assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, ++ <&pllclk JH7110_PLLCLK_PLL2_OUT>, ++ <&pllclk JH7110_PLLCLK_PLL2_OUT>, ++ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; ++ assigned-clock-rates = <0>, <0>, <0>, <0>; ++}; ++ ++&sysgpio { ++ bootph-pre-ram; ++}; ++ ++&mmc0_pins { ++ bootph-pre-ram; ++ rst-pins { ++ bootph-pre-ram; ++ }; ++}; ++ ++&mmc1_pins { ++ bootph-pre-ram; ++ clk-pins { ++ bootph-pre-ram; ++ }; ++ ++ mmc-pins { ++ bootph-pre-ram; ++ }; ++}; ++ ++&i2c5_pins { ++ bootph-pre-ram; ++ i2c-pins { ++ bootph-pre-ram; ++ }; ++}; ++ ++&i2c5 { ++ bootph-pre-ram; ++ eeprom@50 { ++ bootph-pre-ram; ++ compatible = "atmel,24c04"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++}; ++ ++&binman { ++ itb { ++ fit { ++ images { ++ fdt-1 { ++ description = "NAME"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ uboot_fdt_blob: blob-ext { ++ filename = "u-boot.dtb"; ++ }; ++ }; ++ }; ++ ++ configurations { ++ conf-1 { ++ fdt = "fdt-1"; ++ }; ++ }; ++ }; ++ }; ++ ++ spl-img { ++ filename = "spl/u-boot-spl.bin.normal.out"; ++ ++ mkimage { ++ args = "-T sfspl"; ++ ++ u-boot-spl { ++ }; ++ }; ++ }; ++}; +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +index 45fada34d2f..e6bc6630dcd 100644 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +@@ -3,139 +3,4 @@ + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +-#include "binman.dtsi" +-#include "jh7110-u-boot.dtsi" +-/ { +- aliases { +- spi0 = &qspi; +- }; +- +- chosen { +- bootph-pre-ram; +- }; +- +- firmware { +- spi0 = &qspi; +- bootph-pre-ram; +- }; +- +- config { +- bootph-pre-ram; +- u-boot,spl-payload-offset = <0x100000>; +- }; +- +- memory@40000000 { +- bootph-pre-ram; +- }; +-}; +- +-&uart0 { +- bootph-pre-ram; +- reg-offset = <0>; +- current-speed = <115200>; +- clock-frequency = <24000000>; +-}; +- +-&mmc0 { +- bootph-pre-ram; +-}; +- +-&mmc1 { +- bootph-pre-ram; +-}; +- +-&qspi { +- bootph-pre-ram; +- +- flash@0 { +- bootph-pre-ram; +- cdns,read-delay = <2>; +- spi-max-frequency = <100000000>; +- }; +-}; +- +-&syscrg { +- assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, +- <&syscrg JH7110_SYSCLK_BUS_ROOT>, +- <&syscrg JH7110_SYSCLK_PERH_ROOT>, +- <&syscrg JH7110_SYSCLK_QSPI_REF>; +- assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, +- <&pllclk JH7110_PLLCLK_PLL2_OUT>, +- <&pllclk JH7110_PLLCLK_PLL2_OUT>, +- <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; +- assigned-clock-rates = <0>, <0>, <0>, <0>; +-}; +- +-&sysgpio { +- bootph-pre-ram; +-}; +- +-&mmc0_pins { +- bootph-pre-ram; +- rst-pins { +- bootph-pre-ram; +- }; +-}; +- +-&mmc1_pins { +- bootph-pre-ram; +- clk-pins { +- bootph-pre-ram; +- }; +- +- mmc-pins { +- bootph-pre-ram; +- }; +-}; +- +-&i2c5_pins { +- bootph-pre-ram; +- i2c-pins { +- bootph-pre-ram; +- }; +-}; +- +-&i2c5 { +- bootph-pre-ram; +- eeprom@50 { +- bootph-pre-ram; +- compatible = "atmel,24c04"; +- reg = <0x50>; +- pagesize = <16>; +- }; +-}; +- +-&binman { +- itb { +- fit { +- images { +- fdt-1 { +- description = "NAME"; +- load = <0x40400000>; +- compression = "none"; +- +- uboot_fdt_blob: blob-ext { +- filename = "u-boot.dtb"; +- }; +- }; +- }; +- +- configurations { +- conf-1 { +- fdt = "fdt-1"; +- }; +- }; +- }; +- }; +- +- spl-img { +- filename = "spl/u-boot-spl.bin.normal.out"; +- +- mkimage { +- args = "-T sfspl"; +- +- u-boot-spl { +- }; +- }; +- }; +-}; ++#include "jh7110-common-u-boot.dtsi" +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0015-riscv-dts-jh7110-Add-u-boot-device-tree-for-JH7110-b.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0015-riscv-dts-jh7110-Add-u-boot-device-tree-for-JH7110-b.patch --- 2025.01-3/debian/patches/riscv64/starfive/0015-riscv-dts-jh7110-Add-u-boot-device-tree-for-JH7110-b.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0015-riscv-dts-jh7110-Add-u-boot-device-tree-for-JH7110-b.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,63 @@ +From f3ff73439c0ebbb93ebddc611ca223279b07b898 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:36 +0800 +Subject: [PATCH 15/27] riscv: dts: jh7110: Add u-boot device tree for JH7110 + based boards + +To support the other JH7110 based boards, add u-boot +device tree for them. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: E Shattow +Cc: Heinrich Schuchardt +Cc: H Bell +Signed-off-by: Hal Feng +--- + arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 6 ++++++ + arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 6 ++++++ + .../dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 6 ++++++ + 3 files changed, 18 insertions(+) + create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi + create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi + create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi + +diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +new file mode 100644 +index 00000000000..9df1e5db553 +--- /dev/null ++++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ */ ++ ++#include "jh7110-common-u-boot.dtsi" +diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +new file mode 100644 +index 00000000000..9df1e5db553 +--- /dev/null ++++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ */ ++ ++#include "jh7110-common-u-boot.dtsi" +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +new file mode 100644 +index 00000000000..9df1e5db553 +--- /dev/null ++++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +@@ -0,0 +1,6 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ */ ++ ++#include "jh7110-common-u-boot.dtsi" +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0016-board-starfive-spl-Drop-the-unneeded-DT-modification.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0016-board-starfive-spl-Drop-the-unneeded-DT-modification.patch --- 2025.01-3/debian/patches/riscv64/starfive/0016-board-starfive-spl-Drop-the-unneeded-DT-modification.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0016-board-starfive-spl-Drop-the-unneeded-DT-modification.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,387 @@ +From 3631a110c6c11f97a2ebce620fa1a3c21a1c9d21 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:37 +0800 +Subject: [PATCH 16/27] board: starfive: spl: Drop the unneeded DT modification + code + +As OF_UPSTREAM is implemented, these code are redundant. + +Tested-by: Anand Moon +Tested-by: E Shattow +Signed-off-by: Hal Feng +--- + board/starfive/visionfive2/spl.c | 356 ------------------------------- + 1 file changed, 356 deletions(-) + +diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c +index 3fd535e7cfc..38132ecccd3 100644 +--- a/board/starfive/visionfive2/spl.c ++++ b/board/starfive/visionfive2/spl.c +@@ -20,364 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; + #define JH7110_CLK_CPU_ROOT_SHIFT 24 + #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24) + +-struct starfive_vf2_pro { +- const char *path; +- const char *name; +- const char *value; +-}; +- +-static const struct starfive_vf2_pro milk_v_mars[] = { +- {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, +- {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, +- +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-adj-enabled", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-100-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-1000-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-clk-drv-microamp", "3970"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-data-drv-microamp", "2910"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "rx-internal-delay-ps", "1500"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "tx-internal-delay-ps", "1500"}, +-}; +- +-static const struct starfive_vf2_pro starfive_vera[] = { +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", +- "1900"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", +- "1350"} +-}; +- +-static const struct starfive_vf2_pro starfive_verb[] = { +- {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, +- {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, +- +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-adj-enabled", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-100-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-1000-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-clk-drv-microamp", "3970"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-data-drv-microamp", "2910"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "rx-internal-delay-ps", "1500"}, +- +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,tx-clk-adj-enabled", NULL}, +- { "/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,tx-clk-100-inverted", NULL}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,rx-clk-drv-microamp", "3970"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,rx-data-drv-microamp", "2910"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "rx-internal-delay-ps", "0"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "tx-internal-delay-ps", "0"}, +-}; +- +-static const struct starfive_vf2_pro star64_pine64[] = { +- {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, +- {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, +- +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-adj-enabled", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-10-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-100-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,tx-clk-1000-inverted", NULL}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-clk-drv-microamp", "2910"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "motorcomm,rx-data-drv-microamp", "2910"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "rx-internal-delay-ps", "1900"}, +- {"/soc/ethernet@16030000/mdio/ethernet-phy@0", +- "tx-internal-delay-ps", "1500"}, +- +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,tx-clk-adj-enabled", NULL}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,tx-clk-10-inverted", NULL}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,tx-clk-100-inverted", NULL}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,rx-clk-drv-microamp", "2910"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "motorcomm,rx-data-drv-microamp", "2910"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "rx-internal-delay-ps", "0"}, +- {"/soc/ethernet@16040000/mdio/ethernet-phy@1", +- "tx-internal-delay-ps", "300"}, +-}; +- +-void spl_fdt_fixup_mars(void *fdt) +-{ +- static const char compat[] = "milkv,mars\0starfive,jh7110"; +- u32 phandle; +- u8 i; +- int offset; +- int ret; +- +- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", +- "Milk-V Mars"); +- +- /* gmac0 */ +- offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_AONCLK_GMAC0_RMII_RTX); +- +- /* gmac1 */ +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), +- "status", "disabled"); +- +- for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) { +- offset = fdt_path_offset(fdt, milk_v_mars[i].path); +- +- if (milk_v_mars[i].value) +- ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name, +- dectoul(milk_v_mars[i].value, NULL)); +- else +- ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name); +- +- if (ret) { +- pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name); +- break; +- } +- } +-} +- +-void spl_fdt_fixup_mars_cm(void *fdt) +-{ +- const char *compat; +- const char *model; +- int compat_size; +- +- spl_fdt_fixup_mars(fdt); +- +- if (!get_mmc_size_from_eeprom()) { +- int offset; +- static const char +- compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110"; +- +- model = "Milk-V Mars CM Lite"; +- compat = compat_cm_lite; +- compat_size = sizeof(compat_cm_lite); +- +- offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); +- /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ +- fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); +- } else { +- static const char +- compat_cm[] = "milkv,mars-cm\0starfive,jh7110"; +- +- model = "Milk-V Mars CM"; +- compat = compat_cm; +- compat_size = sizeof(compat_cm); +- } +- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), +- "compatible", compat, compat_size); +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); +-} +- +-void spl_fdt_fixup_version_a(void *fdt) +-{ +- static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110"; +- u32 phandle; +- u8 i; +- int offset; +- int ret; +- +- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", +- "StarFive VisionFive 2 v1.2A"); +- +- offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX); +- +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_SYSCLK_GMAC1_RMII_RTX); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_SYSCLK_GMAC1_RMII_RTX); +- +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), +- "phy-mode", "rmii"); +- +- for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) { +- offset = fdt_path_offset(fdt, starfive_vera[i].path); +- +- if (starfive_vera[i].value) +- ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name, +- dectoul(starfive_vera[i].value, NULL)); +- else +- ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name); +- +- if (ret) { +- pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name); +- break; +- } +- } +-} +- +-void spl_fdt_fixup_version_b(void *fdt) +-{ +- static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110"; +- u32 phandle; +- u8 i; +- int offset; +- int ret; +- +- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", +- "StarFive VisionFive 2 v1.3B"); +- +- /* gmac0 */ +- offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_AONCLK_GMAC0_RMII_RTX); +- +- /* gmac1 */ +- offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_SYSCLK_GMAC1_RMII_RTX); +- +- for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { +- offset = fdt_path_offset(fdt, starfive_verb[i].path); +- +- if (starfive_verb[i].value) +- ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, +- dectoul(starfive_verb[i].value, NULL)); +- else +- ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); +- +- if (ret) { +- pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); +- break; +- } +- } +-} +- +-void spl_fdt_fixup_star64(void *fdt) +-{ +- static const char compat[] = "pine64,star64\0starfive,jh7110"; +- u32 phandle; +- u8 i; +- int offset; +- int ret; +- +- fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); +- fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", +- "Pine64 Star64"); +- +- /* gmac0 */ +- offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_AONCLK_GMAC0_RMII_RTX); +- +- /* gmac1 */ +- offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); +- phandle = fdt_get_phandle(fdt, offset); +- offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); +- +- fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); +- fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); +- fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", +- JH7110_SYSCLK_GMAC1_RMII_RTX); +- +- for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { +- offset = fdt_path_offset(fdt, star64_pine64[i].path); +- +- if (star64_pine64[i].value) +- ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, +- dectoul(star64_pine64[i].value, NULL)); +- else +- ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); +- +- if (ret) { +- pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); +- break; +- } +- } +-} +- + void spl_perform_fixups(struct spl_image_info *spl_image) + { +- u8 version; +- const char *product_id; +- +- product_id = get_product_id_from_eeprom(); +- if (!product_id) { +- pr_err("Can't read EEPROM\n"); +- return; +- } +- if (!strncmp(product_id, "MARC", 4)) { +- spl_fdt_fixup_mars_cm(spl_image->fdt_addr); +- } else if (!strncmp(product_id, "MARS", 4)) { +- spl_fdt_fixup_mars(spl_image->fdt_addr); +- } else if (!strncmp(product_id, "VF7110", 6)) { +- version = get_pcb_revision_from_eeprom(); +- switch (version) { +- case 'a': +- case 'A': +- spl_fdt_fixup_version_a(spl_image->fdt_addr); +- break; +- +- case 'b': +- case 'B': +- default: +- spl_fdt_fixup_version_b(spl_image->fdt_addr); +- break; +- }; +- } else if (!strncmp(product_id, "STAR64", 6)) { +- spl_fdt_fixup_star64(spl_image->fdt_addr); +- } else { +- pr_err("Unknown product %s\n", product_id); +- }; +- + /* Update the memory size which read from eeprom or DT */ + fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); + } +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0017-configs-visionfive2-Enable-MULTI_DTB_FIT-for-JH7110-.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0017-configs-visionfive2-Enable-MULTI_DTB_FIT-for-JH7110-.patch --- 2025.01-3/debian/patches/riscv64/starfive/0017-configs-visionfive2-Enable-MULTI_DTB_FIT-for-JH7110-.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0017-configs-visionfive2-Enable-MULTI_DTB_FIT-for-JH7110-.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,32 @@ +From bd8645f720f908fd6e70893aea88921d9323cbf0 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:38 +0800 +Subject: [PATCH 17/27] configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 + based board DT + +So JH7110 based boards can select their own DT at runtime. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: E Shattow +Signed-off-by: Hal Feng +--- + configs/starfive_visionfive2_defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig +index 389adb5e55b..c3f2142ae1b 100644 +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -78,6 +78,8 @@ CONFIG_CMD_WDT=y + CONFIG_CMD_TFTPPUT=y + CONFIG_CMD_BOOTSTAGE=y + CONFIG_OF_BOARD=y ++CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" ++CONFIG_MULTI_DTB_FIT=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_ENV_SECT_SIZE_AUTO=y +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0018-riscv-dts-jh7110-Support-multiple-DTBs-in-a-Fit-imag.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0018-riscv-dts-jh7110-Support-multiple-DTBs-in-a-Fit-imag.patch --- 2025.01-3/debian/patches/riscv64/starfive/0018-riscv-dts-jh7110-Support-multiple-DTBs-in-a-Fit-imag.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0018-riscv-dts-jh7110-Support-multiple-DTBs-in-a-Fit-imag.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,105 @@ +From 02df66dc8e70cb010e3abcf22303a4ad792ca9cb Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:39 +0800 +Subject: [PATCH 18/27] riscv: dts: jh7110: Support multiple DTBs in a Fit + image + +Support multiple DTBs for JH7110 based boards, so they can +select the correct DT at runtime. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: E Shattow +Signed-off-by: Hal Feng +--- + arch/riscv/dts/jh7110-common-u-boot.dtsi | 66 +++++++++++++++++++++--- + 1 file changed, 60 insertions(+), 6 deletions(-) + +diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi +index 45fada34d2f..7871294e90d 100644 +--- a/arch/riscv/dts/jh7110-common-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi +@@ -109,20 +109,74 @@ + itb { + fit { + images { +- fdt-1 { +- description = "NAME"; ++ fdt-jh7110-milkv-mars { ++ description = "jh7110-milkv-mars"; + load = <0x40400000>; + compression = "none"; + +- uboot_fdt_blob: blob-ext { +- filename = "u-boot.dtb"; ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-pine64-star64 { ++ description = "jh7110-pine64-star64"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-starfive-visionfive-2-v1.2a { ++ description = "jh7110-starfive-visionfive-2-v1.2a"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-starfive-visionfive-2-v1.3b { ++ description = "jh7110-starfive-visionfive-2-v1.3b"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; + }; + }; + }; + + configurations { +- conf-1 { +- fdt = "fdt-1"; ++ conf-jh7110-milkv-mars { ++ description = "jh7110-milkv-mars"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-milkv-mars"; ++ }; ++ ++ conf-jh7110-pine64-star64 { ++ description = "jh7110-pine64-star64"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-pine64-star64"; ++ }; ++ ++ conf-jh7110-starfive-visionfive-2-v1.2a { ++ description = "jh7110-starfive-visionfive-2-v1.2a"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a"; ++ }; ++ ++ conf-jh7110-starfive-visionfive-2-v1.3b { ++ description = "jh7110-starfive-visionfive-2-v1.3b"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b"; + }; + }; + }; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0019-board-starfive-spl-Fix-the-wrong-use-of-CONFIG_IS_EN.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0019-board-starfive-spl-Fix-the-wrong-use-of-CONFIG_IS_EN.patch --- 2025.01-3/debian/patches/riscv64/starfive/0019-board-starfive-spl-Fix-the-wrong-use-of-CONFIG_IS_EN.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0019-board-starfive-spl-Fix-the-wrong-use-of-CONFIG_IS_EN.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,33 @@ +From b05be1e43fb90776ca58ff80fd5b2ad7a07fe039 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:40 +0800 +Subject: [PATCH 19/27] board: starfive: spl: Fix the wrong use of + CONFIG_IS_ENABLED() + +The prefix "SPL_" is not needed when using CONFIG_IS_ENABLED(). + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: Heinrich Schuchardt +Fixes: 5ecf9b0b8a75 ("board: starfive: add StarFive VisionFive v2 board support") +Signed-off-by: Hal Feng +--- + board/starfive/visionfive2/spl.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c +index 38132ecccd3..cf7f39d5c55 100644 +--- a/board/starfive/visionfive2/spl.c ++++ b/board/starfive/visionfive2/spl.c +@@ -110,7 +110,7 @@ void board_init_f(ulong dummy) + } + } + +-#if CONFIG_IS_ENABLED(SPL_LOAD_FIT) ++#if CONFIG_IS_ENABLED(LOAD_FIT) + int board_fit_config_name_match(const char *name) + { + /* boot using first FIT config */ +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0020-board-starfive-spl-Support-multiple-DTBs-for-JH7110-.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0020-board-starfive-spl-Support-multiple-DTBs-for-JH7110-.patch --- 2025.01-3/debian/patches/riscv64/starfive/0020-board-starfive-spl-Support-multiple-DTBs-for-JH7110-.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0020-board-starfive-spl-Support-multiple-DTBs-for-JH7110-.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,63 @@ +From 8a9f2c8df1b76102c9080249952fa6df56be4055 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:41 +0800 +Subject: [PATCH 20/27] board: starfive: spl: Support multiple DTBs for JH7110 + based boards + +Get product ID and the other information from EEPROM, use them to select +the correct DTB. + +Tested-by: Anand Moon +Tested-by: E Shattow +Reviewed-by: Heinrich Schuchardt +Signed-off-by: Hal Feng +--- + board/starfive/visionfive2/spl.c | 33 ++++++++++++++++++++++++++++++-- + 1 file changed, 31 insertions(+), 2 deletions(-) + +diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c +index cf7f39d5c55..22afd76c6b9 100644 +--- a/board/starfive/visionfive2/spl.c ++++ b/board/starfive/visionfive2/spl.c +@@ -113,7 +113,36 @@ void board_init_f(ulong dummy) + #if CONFIG_IS_ENABLED(LOAD_FIT) + int board_fit_config_name_match(const char *name) + { +- /* boot using first FIT config */ +- return 0; ++ const char *product_id; ++ u8 version; ++ ++ product_id = get_product_id_from_eeprom(); ++ ++ if (!strncmp(product_id, "VF7110", 6)) { ++ version = get_pcb_revision_from_eeprom(); ++ if ((version == 'b' || version == 'B') && ++ !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b")) ++ return 0; ++ ++ if ((version == 'a' || version == 'A') && ++ !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a")) ++ return 0; ++ } else if (!strncmp(product_id, "MARS", 4) && ++ !strcmp(name, "jh7110-milkv-mars")) { ++ return 0; ++ } else if (!strncmp(product_id, "MARC", 4)) { ++ if (!get_mmc_size_from_eeprom()) { ++ if (!strcmp(name, "jh7110-milkv-mars-cm-lite")) ++ return 0; ++ } else { ++ if (!strcmp(name, "jh7110-milkv-mars-cm")) ++ return 0; ++ } ++ } else if (!strncmp(product_id, "STAR64", 6) && ++ !strcmp(name, "jh7110-pine64-star64")) { ++ return 0; ++ } ++ ++ return -EINVAL; + } + #endif +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0021-riscv-cpu-jh7110-Sort-the-list-of-imply-statements.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0021-riscv-cpu-jh7110-Sort-the-list-of-imply-statements.patch --- 2025.01-3/debian/patches/riscv64/starfive/0021-riscv-cpu-jh7110-Sort-the-list-of-imply-statements.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0021-riscv-cpu-jh7110-Sort-the-list-of-imply-statements.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,51 @@ +From 4ac51f2dd3e77cd60fb5cc2d9a7488d85ee4aa74 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sun, 8 Dec 2024 17:19:42 +0800 +Subject: [PATCH 21/27] riscv: cpu: jh7110: Sort the list of imply statements + +The imply statements should be sorted in the sequence +of appearance in .config. + +Tested-by: Anand Moon +Tested-by: E Shattow +Suggested-by: Heinrich Schuchardt +Signed-off-by: Hal Feng +--- + arch/riscv/cpu/jh7110/Kconfig | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig +index 9904a60dddb..fa47e55226e 100644 +--- a/arch/riscv/cpu/jh7110/Kconfig ++++ b/arch/riscv/cpu/jh7110/Kconfig +@@ -16,17 +16,17 @@ config STARFIVE_JH7110 + select SYS_CACHE_SHIFT_6 + select SPL_ZERO_MEM_BEFORE_USE + select PINCTRL_STARFIVE_JH7110 ++ imply SMP ++ imply SPL_RISCV_ACLINT ++ imply SIFIVE_CACHE ++ imply SPL_SYS_MALLOC_CLEAR_ON_INIT ++ imply SPL_LOAD_FIT ++ imply SPL_CPU ++ imply SPL_OPENSBI ++ imply OF_UPSTREAM ++ imply SIFIVE_CCACHE + imply MMC + imply MMC_BROKEN_CD + imply MMC_SPI +- imply OF_UPSTREAM +- imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) +- imply SIFIVE_CACHE +- imply SIFIVE_CCACHE +- imply SMP + imply SPI +- imply SPL_CPU +- imply SPL_LOAD_FIT +- imply SPL_OPENSBI +- imply SPL_RISCV_ACLINT +- imply SPL_SYS_MALLOC_CLEAR_ON_INIT ++ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0022-riscv-dts-starfive-split-out-visionfive2-target-spec.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0022-riscv-dts-starfive-split-out-visionfive2-target-spec.patch --- 2025.01-3/debian/patches/riscv64/starfive/0022-riscv-dts-starfive-split-out-visionfive2-target-spec.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0022-riscv-dts-starfive-split-out-visionfive2-target-spec.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,286 @@ +From 06f0b9677416bdb57cacbd203bbe07900bbb8633 Mon Sep 17 00:00:00 2001 +From: E Shattow +Date: Tue, 31 Dec 2024 22:35:57 -0800 +Subject: [PATCH 22/27] riscv: dts: starfive: split out visionfive2 target + specific configuration + +Split out StarFive VisionFive2 multi-board target specific configuration +into starfive-visionfive2-binman.dtsi in preparation for removal of +jh7110-u-boot and jh7110-common-u-boot in part or whole as sent upstream. + +Signed-off-by: E Shattow +Reviewed-by: Leo Yu-Chi Liang +--- + arch/riscv/dts/jh7110-common-u-boot.dtsi | 95 ---------------- + arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 1 + + .../dts/jh7110-pine64-star64-u-boot.dtsi | 1 + + ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 1 + + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 1 + + .../dts/starfive-visionfive2-binman.dtsi | 102 ++++++++++++++++++ + 6 files changed, 106 insertions(+), 95 deletions(-) + create mode 100644 arch/riscv/dts/starfive-visionfive2-binman.dtsi + +diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi +index 7871294e90d..6d85b2d91a7 100644 +--- a/arch/riscv/dts/jh7110-common-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi +@@ -3,7 +3,6 @@ + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +-#include "binman.dtsi" + #include "jh7110-u-boot.dtsi" + / { + aliases { +@@ -19,11 +18,6 @@ + bootph-pre-ram; + }; + +- config { +- bootph-pre-ram; +- u-boot,spl-payload-offset = <0x100000>; +- }; +- + memory@40000000 { + bootph-pre-ram; + }; +@@ -104,92 +98,3 @@ + pagesize = <16>; + }; + }; +- +-&binman { +- itb { +- fit { +- images { +- fdt-jh7110-milkv-mars { +- description = "jh7110-milkv-mars"; +- load = <0x40400000>; +- compression = "none"; +- +- blob-ext { +- filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb"; +- }; +- }; +- +- fdt-jh7110-pine64-star64 { +- description = "jh7110-pine64-star64"; +- load = <0x40400000>; +- compression = "none"; +- +- blob-ext { +- filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb"; +- }; +- }; +- +- fdt-jh7110-starfive-visionfive-2-v1.2a { +- description = "jh7110-starfive-visionfive-2-v1.2a"; +- load = <0x40400000>; +- compression = "none"; +- +- blob-ext { +- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; +- }; +- }; +- +- fdt-jh7110-starfive-visionfive-2-v1.3b { +- description = "jh7110-starfive-visionfive-2-v1.3b"; +- load = <0x40400000>; +- compression = "none"; +- +- blob-ext { +- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; +- }; +- }; +- }; +- +- configurations { +- conf-jh7110-milkv-mars { +- description = "jh7110-milkv-mars"; +- firmware = "opensbi"; +- loadables = "uboot"; +- fdt = "fdt-jh7110-milkv-mars"; +- }; +- +- conf-jh7110-pine64-star64 { +- description = "jh7110-pine64-star64"; +- firmware = "opensbi"; +- loadables = "uboot"; +- fdt = "fdt-jh7110-pine64-star64"; +- }; +- +- conf-jh7110-starfive-visionfive-2-v1.2a { +- description = "jh7110-starfive-visionfive-2-v1.2a"; +- firmware = "opensbi"; +- loadables = "uboot"; +- fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a"; +- }; +- +- conf-jh7110-starfive-visionfive-2-v1.3b { +- description = "jh7110-starfive-visionfive-2-v1.3b"; +- firmware = "opensbi"; +- loadables = "uboot"; +- fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b"; +- }; +- }; +- }; +- }; +- +- spl-img { +- filename = "spl/u-boot-spl.bin.normal.out"; +- +- mkimage { +- args = "-T sfspl"; +- +- u-boot-spl { +- }; +- }; +- }; +-}; +diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +index 9df1e5db553..ab882d07f6f 100644 +--- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +@@ -4,3 +4,4 @@ + */ + + #include "jh7110-common-u-boot.dtsi" ++#include "starfive-visionfive2-binman.dtsi" +diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +index 9df1e5db553..ab882d07f6f 100644 +--- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +@@ -4,3 +4,4 @@ + */ + + #include "jh7110-common-u-boot.dtsi" ++#include "starfive-visionfive2-binman.dtsi" +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +index 9df1e5db553..ab882d07f6f 100644 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +@@ -4,3 +4,4 @@ + */ + + #include "jh7110-common-u-boot.dtsi" ++#include "starfive-visionfive2-binman.dtsi" +diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +index e6bc6630dcd..874074174ff 100644 +--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi ++++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +@@ -4,3 +4,4 @@ + */ + + #include "jh7110-common-u-boot.dtsi" ++#include "starfive-visionfive2-binman.dtsi" +diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi +new file mode 100644 +index 00000000000..4cce001e80d +--- /dev/null ++++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi +@@ -0,0 +1,102 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include "binman.dtsi" ++ ++/ { ++ config { ++ bootph-pre-ram; ++ u-boot,spl-payload-offset = <0x100000>; ++ }; ++}; ++ ++&binman { ++ itb { ++ fit { ++ images { ++ fdt-jh7110-milkv-mars { ++ description = "jh7110-milkv-mars"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-pine64-star64 { ++ description = "jh7110-pine64-star64"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-starfive-visionfive-2-v1.2a { ++ description = "jh7110-starfive-visionfive-2-v1.2a"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; ++ }; ++ }; ++ ++ fdt-jh7110-starfive-visionfive-2-v1.3b { ++ description = "jh7110-starfive-visionfive-2-v1.3b"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; ++ }; ++ }; ++ }; ++ ++ configurations { ++ conf-jh7110-milkv-mars { ++ description = "jh7110-milkv-mars"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-milkv-mars"; ++ }; ++ ++ conf-jh7110-pine64-star64 { ++ description = "jh7110-pine64-star64"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-pine64-star64"; ++ }; ++ ++ conf-jh7110-starfive-visionfive-2-v1.2a { ++ description = "jh7110-starfive-visionfive-2-v1.2a"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a"; ++ }; ++ ++ conf-jh7110-starfive-visionfive-2-v1.3b { ++ description = "jh7110-starfive-visionfive-2-v1.3b"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b"; ++ }; ++ }; ++ }; ++ }; ++ ++ spl-img { ++ filename = "spl/u-boot-spl.bin.normal.out"; ++ ++ mkimage { ++ args = "-T sfspl"; ++ ++ u-boot-spl { ++ }; ++ }; ++ }; ++}; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0023-configs-add-jh7110-deepcomputing-fml13v01-to-VF2-def.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0023-configs-add-jh7110-deepcomputing-fml13v01-to-VF2-def.patch --- 2025.01-3/debian/patches/riscv64/starfive/0023-configs-add-jh7110-deepcomputing-fml13v01-to-VF2-def.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0023-configs-add-jh7110-deepcomputing-fml13v01-to-VF2-def.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,31 @@ +From 893630997019672a84b5221f079bf25ccb8f08a6 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 00:03:38 +0100 +Subject: [PATCH 23/27] configs: add jh7110-deepcomputing-fml13v01 to VF2 + defconfig + +The DeepComputing Framework motherboard is a JH7110 device support by the +upstream kernel. Add its device-tree to the list of device-trees to be +included into the starfive_visionfive_defconfig. + +Signed-off-by: Heinrich Schuchardt +--- + configs/starfive_visionfive2_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig +index c3f2142ae1b..821aea9c236 100644 +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -78,7 +78,7 @@ CONFIG_CMD_WDT=y + CONFIG_CMD_TFTPPUT=y + CONFIG_CMD_BOOTSTAGE=y + CONFIG_OF_BOARD=y +-CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" ++CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" + CONFIG_MULTI_DTB_FIT=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_SPI_FLASH=y +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0024-riscv-dts-starfive-DeepComputing-FML13V01-binman-con.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0024-riscv-dts-starfive-DeepComputing-FML13V01-binman-con.patch --- 2025.01-3/debian/patches/riscv64/starfive/0024-riscv-dts-starfive-DeepComputing-FML13V01-binman-con.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0024-riscv-dts-starfive-DeepComputing-FML13V01-binman-con.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,52 @@ +From f3331e2f34f019a9a39f3b1ed8a0cf3e1a649740 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 00:34:30 +0100 +Subject: [PATCH 24/27] riscv: dts: starfive: DeepComputing FML13V01 binman + config + +Add the DeepComputing Framework motherboard (FML13V01) to the binman +include for the starfive_visionfive2_defconfig. + +Signed-off-by: Heinrich Schuchardt +--- + arch/riscv/dts/starfive-visionfive2-binman.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi +index 4cce001e80d..63289405fbb 100644 +--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi ++++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi +@@ -16,6 +16,16 @@ + itb { + fit { + images { ++ fdt-jh7110-deepcomputing-fml13v01 { ++ description = "jh7110-deepcomputing-fml13v01"; ++ load = <0x40400000>; ++ compression = "none"; ++ ++ blob-ext { ++ filename = "dts/upstream/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dtb"; ++ }; ++ }; ++ + fdt-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; + load = <0x40400000>; +@@ -58,6 +68,13 @@ + }; + + configurations { ++ conf-jh7110-deepcomputing-fml13v01 { ++ description = "jh7110-deepcomputing-fml13v01"; ++ firmware = "opensbi"; ++ loadables = "uboot"; ++ fdt = "fdt-jh7110-deepcomputing-fml13v01"; ++ }; ++ + conf-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; + firmware = "opensbi"; +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0025-riscv-dts-jh7110-add-DeepComputing-FML13V01-device-t.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0025-riscv-dts-jh7110-add-DeepComputing-FML13V01-device-t.patch --- 2025.01-3/debian/patches/riscv64/starfive/0025-riscv-dts-jh7110-add-DeepComputing-FML13V01-device-t.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0025-riscv-dts-jh7110-add-DeepComputing-FML13V01-device-t.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,31 @@ +From c47865a8fd74a644884cd36b4b19cde645f718b9 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 16:59:58 +0100 +Subject: [PATCH 25/27] riscv: dts: jh7110: add DeepComputing FML13V01 + device-tree + +Add the u-boot device-tree include needed to support the +DeepComputing Framework motherboard (FML13V01). + +Signed-off-by: Heinrich Schuchardt +--- + arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + create mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi + +diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +new file mode 100644 +index 00000000000..ab882d07f6f +--- /dev/null ++++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2024 StarFive Technology Co., Ltd. ++ */ ++ ++#include "jh7110-common-u-boot.dtsi" ++#include "starfive-visionfive2-binman.dtsi" +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0026-board-starfive-DeepComputing-FML13V01-fdt-selection.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0026-board-starfive-DeepComputing-FML13V01-fdt-selection.patch --- 2025.01-3/debian/patches/riscv64/starfive/0026-board-starfive-DeepComputing-FML13V01-fdt-selection.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0026-board-starfive-DeepComputing-FML13V01-fdt-selection.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,43 @@ +From 5791aca1aa7dff5c54153db12f87707c31871f74 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 00:11:31 +0100 +Subject: [PATCH 26/27] board: starfive: DeepComputing FML13V01 fdt selection + +We support all JH7110 boards with starfive_visionfive2_defconfig. +The relevant device-tree is selected at runtime based on EEPROM data. + +Support setting $fdtfile to the file name of the DeepComputing Framework +motherboard (FML13V01) device-tree. + +Signed-off-by: Heinrich Schuchardt +--- + board/starfive/visionfive2/starfive_visionfive2.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c +index f6114602f88..48ca1531928 100644 +--- a/board/starfive/visionfive2/starfive_visionfive2.c ++++ b/board/starfive/visionfive2/starfive_visionfive2.c +@@ -17,6 +17,8 @@ + DECLARE_GLOBAL_DATA_PTR; + #define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000 + #define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000 ++#define FDTFILE_FML13V01 \ ++ "starfive/jh7110-deepcomputing-fml13v01.dtb" + #define FDTFILE_MILK_V_MARS \ + "starfive/jh7110-milkv-mars.dtb" + #define FDTFILE_MILK_V_MARS_CM \ +@@ -67,7 +69,9 @@ static void set_fdtfile(void) + log_err("Can't read EEPROM\n"); + return; + } +- if (!strncmp(product_id, "MARC", 4)) { ++ if (!strncmp(product_id, "FML13V01", 8)) { ++ fdtfile = FDTFILE_FML13V01; ++ } else if (!strncmp(product_id, "MARC", 4)) { + if (get_mmc_size_from_eeprom()) + fdtfile = FDTFILE_MILK_V_MARS_CM; + else +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/starfive/0027-board-starfive-spl-support-DeepComputing-FML13V01.patch 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0027-board-starfive-spl-support-DeepComputing-FML13V01.patch --- 2025.01-3/debian/patches/riscv64/starfive/0027-board-starfive-spl-support-DeepComputing-FML13V01.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/starfive/0027-board-starfive-spl-support-DeepComputing-FML13V01.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,32 @@ +From 447f10ed3db437bcf2da5366e64392a18fbfb6cb Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 7 Feb 2025 15:59:53 +0100 +Subject: [PATCH 27/27] board: starfive: spl: support DeepComputing FML13V01 + +On the DeepComputing Framework motherboard (FML13V01) choose the matching +FIT configuration. + +Signed-off-by: Heinrich Schuchardt +--- + board/starfive/visionfive2/spl.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c +index 22afd76c6b9..e97ea90cf4b 100644 +--- a/board/starfive/visionfive2/spl.c ++++ b/board/starfive/visionfive2/spl.c +@@ -118,7 +118,10 @@ int board_fit_config_name_match(const char *name) + + product_id = get_product_id_from_eeprom(); + +- if (!strncmp(product_id, "VF7110", 6)) { ++ if (!strncmp(product_id, "FML13V01", 8) && ++ !strcmp(name, "jh7110-deepcomputing-fml13v01")) { ++ return 0; ++ } else if (!strncmp(product_id, "VF7110", 6)) { + version = get_pcb_revision_from_eeprom(); + if ((version == 'b' || version == 'B') && + !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b")) +-- +2.43.0 + diff -pruN 2025.01-3/debian/patches/riscv64/usb-reset.patch 2025.01-3ubuntu1/debian/patches/riscv64/usb-reset.patch --- 2025.01-3/debian/patches/riscv64/usb-reset.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/riscv64/usb-reset.patch 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,26 @@ +From: Heinrich Schuchardt +Subject: [PATCH 1/1] configs: visionfive2: add 'usb reset' in PREBOOT +Date: Fri, 2 Feb 2024 22:41:57 +0100 + +When starting up USB some devices are detected twice and USB block +devices are not usable. Issuing a 'usb reset' resolves the situation. + +This needs a proper upstream fix. But at least with this quirk USB +block devices become usable. + +Signed-off-by: Heinrich Schuchardt +--- + configs/starfive_visionfive2_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -41,7 +41,7 @@ CONFIG_OF_BOARD_SETUP=y + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" ++CONFIG_PREBOOT="nvme scan; usb start; usb reset; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" + CONFIG_SYS_CBSIZE=256 + CONFIG_SYS_PBSIZE=276 + CONFIG_DISPLAY_CPUINFO=y diff -pruN 2025.01-3/debian/patches/rpi-8gb-pci.patch 2025.01-3ubuntu1/debian/patches/rpi-8gb-pci.patch --- 2025.01-3/debian/patches/rpi-8gb-pci.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/rpi-8gb-pci.patch 2025-05-09 09:50:52.000000000 +0000 @@ -0,0 +1,30 @@ +Author: Dave Jones +Forwarded: yes +Description: Disable Broadcom PCI driver + The Broadcom PCI driver seems to break u-boot when booting on a Pi 4B with + 8Gb of RAM, when no monitor is attached. This is a brute-force and ignorance + patch and further (upstream) investigation is warranted to discover why this + is the case. Commit 3113c84ba25ec3ceae072cc5ad450c4238425939 (a merge, + annoyingly) is the first bad commit in the u-boot repository when bisecting + this issue. + +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -39,7 +39,6 @@ CONFIG_BCM2835_GPIO=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_BCMGENET=y +-CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_DM_RNG=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -39,7 +39,6 @@ CONFIG_BCM2835_GPIO=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_BCMGENET=y +-CONFIG_PCI_BRCMSTB=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + CONFIG_DM_RNG=y diff -pruN 2025.01-3/debian/patches/rpi-cm4-sdhci.patch 2025.01-3ubuntu1/debian/patches/rpi-cm4-sdhci.patch --- 2025.01-3/debian/patches/rpi-cm4-sdhci.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/rpi-cm4-sdhci.patch 2025-05-09 09:50:52.000000000 +0000 @@ -0,0 +1,26 @@ +Author: Dave Jones +Forwarded: yes +Description: Revert commit c6b9fbf7566f84a807a5c116288648085fa529df + This commit adds SDHCI DMA support which works happily with the SD card + interface on the Pi 4, but breaks eMMC support on the CM4 + +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -37,7 +37,6 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 + CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 + CONFIG_BCM2835_GPIO=y + CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_BCMGENET=y + CONFIG_PCI_BRCMSTB=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -37,7 +37,6 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 + CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 + CONFIG_BCM2835_GPIO=y + CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_BCM2835=y + CONFIG_BCMGENET=y + CONFIG_PCI_BRCMSTB=y diff -pruN 2025.01-3/debian/patches/rpi-config-tweaks.patch 2025.01-3ubuntu1/debian/patches/rpi-config-tweaks.patch --- 2025.01-3/debian/patches/rpi-config-tweaks.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/rpi-config-tweaks.patch 2025-05-09 09:50:51.000000000 +0000 @@ -0,0 +1,104 @@ +Author: Dave Jones +Description: Configuration adjustments to the RPi2 and RPi3 configs + Based off rpi2-config-tweaks.patch created by Steve Langasek, and + subsequently rpi2-rpi3-config-tweaks.patch created by Łukasz Zemczak, this + ensures that all pi-related configurations are consistent. + Specifically that enable the "redundant" environment setting + (entirely pointlessly but this changes the env header and, again, + several related code-bases now assume this). + +--- a/configs/rpi_2_defconfig ++++ b/configs/rpi_2_defconfig +@@ -8,7 +8,7 @@ CONFIG_TARGET_RPI_2=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_SYS_LOAD_ADDR=0x1000000 +@@ -25,6 +25,7 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_3_32b_defconfig ++++ b/configs/rpi_3_32b_defconfig +@@ -7,7 +7,7 @@ CONFIG_TARGET_RPI_3_32B=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff00 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_SYS_LOAD_ADDR=0x1000000 +@@ -24,6 +24,7 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_3_defconfig ++++ b/configs/rpi_3_defconfig +@@ -6,7 +6,7 @@ CONFIG_TARGET_RPI_3=y + CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe40 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_SYS_LOAD_ADDR=0x1000000 +@@ -27,6 +27,7 @@ CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y + CONFIG_CMD_EFIDEBUG=y + CONFIG_CMD_FS_UUID=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -4,7 +4,7 @@ CONFIG_TEXT_BASE=0x00008000 + CONFIG_TARGET_RPI_4_32B=y + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffee0 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_DM_RESET=y +@@ -26,6 +26,7 @@ CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_FS_UUID=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -4,7 +4,7 @@ CONFIG_TEXT_BASE=0x00080000 + CONFIG_TARGET_RPI_4=y + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7fffe30 +-CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="bcm2711-rpi-4-b" + CONFIG_OF_LIBFDT_OVERLAY=y + CONFIG_DM_RESET=y +@@ -30,6 +30,7 @@ CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y + CONFIG_CMD_EFIDEBUG=y + CONFIG_CMD_FS_UUID=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff -pruN 2025.01-3/debian/patches/rpi-fit-images.patch 2025.01-3ubuntu1/debian/patches/rpi-fit-images.patch --- 2025.01-3/debian/patches/rpi-fit-images.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/rpi-fit-images.patch 2025-05-09 09:50:55.000000000 +0000 @@ -0,0 +1,79 @@ +Author: Dave Jones +Forwarded: not-needed +Description: Enable FIT images in the Raspberry Pi configuration + +--- a/configs/rpi_3_32b_defconfig ++++ b/configs/rpi_3_32b_defconfig +@@ -52,3 +52,12 @@ CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_SYS_MAXARGS=64 ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_PRINT=y ++CONFIG_TOOLS_FIT=y ++CONFIG_TOOLS_FIT_SIGNATURE=y ++CONFIG_TOOLS_FIT_VERBOSE=y ++CONFIG_TOOLS_FIT_PRINT=y ++CONFIG_ZSTD=y +--- a/configs/rpi_3_defconfig ++++ b/configs/rpi_3_defconfig +@@ -59,3 +59,12 @@ CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + # CONFIG_HEXDUMP is not set + CONFIG_SYS_MAXARGS=64 ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_PRINT=y ++CONFIG_TOOLS_FIT=y ++CONFIG_TOOLS_FIT_SIGNATURE=y ++CONFIG_TOOLS_FIT_VERBOSE=y ++CONFIG_TOOLS_FIT_PRINT=y ++CONFIG_ZSTD=y +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -67,3 +67,12 @@ CONFIG_PHYS_TO_BUS=y + CONFIG_ADDR_MAP=y + CONFIG_SYS_NUM_ADDR_MAP=2 + CONFIG_SYS_MAXARGS=64 ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_PRINT=y ++CONFIG_TOOLS_FIT=y ++CONFIG_TOOLS_FIT_SIGNATURE=y ++CONFIG_TOOLS_FIT_VERBOSE=y ++CONFIG_TOOLS_FIT_PRINT=y ++CONFIG_ZSTD=y +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -70,3 +70,12 @@ CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + # CONFIG_HEXDUMP is not set + CONFIG_SYS_MAXARGS=64 ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_PRINT=y ++CONFIG_TOOLS_FIT=y ++CONFIG_TOOLS_FIT_SIGNATURE=y ++CONFIG_TOOLS_FIT_VERBOSE=y ++CONFIG_TOOLS_FIT_PRINT=y ++CONFIG_ZSTD=y +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -64,3 +64,12 @@ CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + # CONFIG_HEXDUMP is not set ++CONFIG_FIT=y ++CONFIG_FIT_SIGNATURE=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_PRINT=y ++CONFIG_TOOLS_FIT=y ++CONFIG_TOOLS_FIT_SIGNATURE=y ++CONFIG_TOOLS_FIT_VERBOSE=y ++CONFIG_TOOLS_FIT_PRINT=y ++CONFIG_ZSTD=y diff -pruN 2025.01-3/debian/patches/rpi-maxargs.patch 2025.01-3ubuntu1/debian/patches/rpi-maxargs.patch --- 2025.01-3/debian/patches/rpi-maxargs.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/rpi-maxargs.patch 2025-05-09 09:50:52.000000000 +0000 @@ -0,0 +1,42 @@ +Author: Dave Jones +Forwarded: no +Description: Allow more than 16 args for a command for LP: #1910094 + The default u-boot command line configuration only permits a maximum of + 16 arguments per command. Unfortunately, the fix for LP: #1900879 demands + considerably more than this. + +--- a/configs/rpi_2_defconfig ++++ b/configs/rpi_2_defconfig +@@ -50,3 +50,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y + CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y ++CONFIG_SYS_MAXARGS=64 +--- a/configs/rpi_3_32b_defconfig ++++ b/configs/rpi_3_32b_defconfig +@@ -51,3 +51,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y + CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y ++CONFIG_SYS_MAXARGS=64 +--- a/configs/rpi_3_defconfig ++++ b/configs/rpi_3_defconfig +@@ -58,3 +58,4 @@ CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + # CONFIG_HEXDUMP is not set ++CONFIG_SYS_MAXARGS=64 +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -66,3 +66,4 @@ CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + CONFIG_ADDR_MAP=y + CONFIG_SYS_NUM_ADDR_MAP=2 ++CONFIG_SYS_MAXARGS=64 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -69,3 +69,4 @@ CONFIG_VIDEO_BCM2835=y + CONFIG_CONSOLE_SCROLL_LINES=10 + CONFIG_PHYS_TO_BUS=y + # CONFIG_HEXDUMP is not set ++CONFIG_SYS_MAXARGS=64 diff -pruN 2025.01-3/debian/patches/series 2025.01-3ubuntu1/debian/patches/series --- 2025.01-3/debian/patches/series 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/series 2025-05-09 09:51:05.000000000 +0000 @@ -11,3 +11,57 @@ qemu/efi-secure-boot.patch Makefile-Use-relative-paths-for-debugging-symbols.patch sitara/Don-t-attempt-to-build-final-firmware-images.patch + +rpi-config-tweaks.patch +ubuntu-hardening-limit-keynames-to-keydir.patch +ubuntu-nitrogen6q2g-config-tweaks.patch +rpi-cm4-sdhci.patch +rpi-8gb-pci.patch +rpi-maxargs.patch + +efivars-commands.patch + +riscv64/enable-sbi.patch +riscv64/usb-reset.patch + +rpi-fit-images.patch +riscv64/erase-env.patch +riscv64/mpfs-icicle-kit_fdtfile.patch + +riscv64/starfive/0001-efi-Correct-ECPT-table-GUID.patch +riscv64/starfive/0002-pinctrl-imx-Fix-NULL-dereference-in-imx_pinctrl_prob.patch +riscv64/starfive/0003-power-pmic-sunxi-guard-DCDC5-separately.patch +riscv64/starfive/0004-configs-use-syntax-CONFIG_FOO-n-in-tools-only_defcon.patch +riscv64/starfive/0005-pinctrl-starfive-Correct-driver-declaration-for-star.patch +riscv64/starfive/0006-net-eth_bootdev_hunt-should-not-run-DHCP.patch +riscv64/starfive/0007-configs-SiFive-Unmatched-add-nvme-scan-to-preboot.patch +riscv64/starfive/0008-efi_loader-fix-pe-reloc-pointer-overrun.patch +riscv64/starfive/0009-riscv-dts-starfive-add-DeepComputing-FML13V01-board-.patch +riscv64/starfive/0010-dts-starfive-Switch-to-using-upstream-DT.patch +riscv64/starfive/0011-riscv-dts-jh7110-Make-u-boot-device-trees-adapting-t.patch +riscv64/starfive/0012-mmc-dw_mmc-Add-starfive-jh7110-mmc-compatible-to-mat.patch +riscv64/starfive/0013-pcie-starfive-Make-the-driver-compatible-with-upstre.patch +riscv64/starfive/0014-riscv-dts-jh7110-Move-common-code-to-the-new-jh7110-.patch +riscv64/starfive/0015-riscv-dts-jh7110-Add-u-boot-device-tree-for-JH7110-b.patch +riscv64/starfive/0016-board-starfive-spl-Drop-the-unneeded-DT-modification.patch +riscv64/starfive/0017-configs-visionfive2-Enable-MULTI_DTB_FIT-for-JH7110-.patch +riscv64/starfive/0018-riscv-dts-jh7110-Support-multiple-DTBs-in-a-Fit-imag.patch +riscv64/starfive/0019-board-starfive-spl-Fix-the-wrong-use-of-CONFIG_IS_EN.patch +riscv64/starfive/0020-board-starfive-spl-Support-multiple-DTBs-for-JH7110-.patch +riscv64/starfive/0021-riscv-cpu-jh7110-Sort-the-list-of-imply-statements.patch +riscv64/starfive/0022-riscv-dts-starfive-split-out-visionfive2-target-spec.patch +riscv64/starfive/0023-configs-add-jh7110-deepcomputing-fml13v01-to-VF2-def.patch +riscv64/starfive/0024-riscv-dts-starfive-DeepComputing-FML13V01-binman-con.patch +riscv64/starfive/0025-riscv-dts-jh7110-add-DeepComputing-FML13V01-device-t.patch +riscv64/starfive/0026-board-starfive-DeepComputing-FML13V01-fdt-selection.patch +riscv64/starfive/0027-board-starfive-spl-support-DeepComputing-FML13V01.patch + +riscv64/star64/0001-usb-cdns3-Set-USB-PHY-mode-in-cdns3_drd_update_mode.patch +riscv64/star64/0002-phy-starfive-Add-Starfive-JH7110-USB-2.0-PHY-driver.patch +riscv64/star64/0003-phy-starfive-Add-Starfive-JH7110-PCIe-2.0-PHY-driver.patch +riscv64/star64/0004-usb-cdns-starfive-Get-dr-mode-from-wrapper-device-dt.patch +riscv64/star64/0005-usb-cdns-starfive-Add-cdns-USB-driver.patch +riscv64/star64/0006-spl-starfive-visionfive2-Disable-USB-overcurrent-pin.patch +riscv64/star64/0007-configs-starfive-Add-visionfive2-cadence-USB-configu.patch + +use-cryptographically-safe-RNG.patch diff -pruN 2025.01-3/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch 2025.01-3ubuntu1/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch --- 2025.01-3/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/ubuntu-hardening-limit-keynames-to-keydir.patch 2025-05-09 09:50:51.000000000 +0000 @@ -0,0 +1,55 @@ +Description: limit keyname to prevent escape from keydir + Limit key names to keys within the keydir by refusing keynames containing + a slash. +Author: Andy Whitcroft +Forwarded: no +Last-Update: 2019-05-31 + +--- + +Index: u-boot-2021.07~rc4+dfsg/lib/rsa/rsa-sign.c +=================================================================== +--- u-boot-2021.07~rc4+dfsg.orig/lib/rsa/rsa-sign.c ++++ u-boot-2021.07~rc4+dfsg/lib/rsa/rsa-sign.c +@@ -67,7 +67,12 @@ static int rsa_pem_get_pub_key(const cha + if (!evpp) + return -EINVAL; + +- *evpp = NULL; ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ ++ *evpp = NULL; + snprintf(path, sizeof(path), "%s/%s.crt", keydir, name); + f = fopen(path, "r"); + if (!f) { +@@ -199,6 +204,11 @@ static int rsa_pem_get_priv_key(const ch + if (!evpp) + return -EINVAL; + ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ + *evpp = NULL; + if (keydir && name) + snprintf(path, sizeof(path), "%s/%s.key", keydir, name); +Index: u-boot-2021.07~rc4+dfsg/tools/kwbimage.c +=================================================================== +--- u-boot-2021.07~rc4+dfsg.orig/tools/kwbimage.c ++++ u-boot-2021.07~rc4+dfsg/tools/kwbimage.c +@@ -395,6 +395,11 @@ static int kwb_load_rsa_key(const char * + if (!keydir) + keydir = "."; + ++ if (strchr(name, '/')) { ++ fprintf(stderr, "Invalid key name '%s': contains '/' \n", name); ++ return -EACCES; ++ } ++ + snprintf(path, sizeof(path), "%s/%s.key", keydir, name); + f = fopen(path, "r"); + if (!f) { diff -pruN 2025.01-3/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch 2025.01-3ubuntu1/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch --- 2025.01-3/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/ubuntu-nitrogen6q2g-config-tweaks.patch 2025-05-09 09:50:52.000000000 +0000 @@ -0,0 +1,51 @@ +--- a/configs/nitrogen6q2g_defconfig ++++ b/configs/nitrogen6q2g_defconfig +@@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0xa00000 + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_SF_DEFAULT_SPEED=25000000 +-CONFIG_ENV_SIZE=0x2000 ++CONFIG_ENV_SIZE=0x20000 + CONFIG_ENV_OFFSET=0xC0000 + CONFIG_ENV_SECT_SIZE=0x2000 + CONFIG_IMX_CONFIG="board/boundary/nitrogen6x/nitrogen6q2g.cfg" +@@ -15,6 +15,9 @@ CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="imx6q-nitrogen6x" + CONFIG_CMD_HDMIDETECT=y + CONFIG_AHCI=y ++CONFIG_SCSI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI_AHCI_PLAT=y + CONFIG_SYS_MEMTEST_START=0x10000000 + CONFIG_SYS_MEMTEST_END=0x10010000 + CONFIG_SUPPORT_RAW_INITRD=y +@@ -32,8 +35,10 @@ CONFIG_CMD_BOOTZ=y + CONFIG_CMD_MEMTEST=y + CONFIG_SYS_ALT_MEMTEST=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y + CONFIG_CMD_SATA=y + CONFIG_CMD_USB=y + CONFIG_CMD_USB_MASS_STORAGE=y +@@ -51,7 +56,12 @@ CONFIG_CMD_FS_GENERIC=y + CONFIG_OF_CONTROL=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_ENV_IS_IN_FAT=y ++CONFIG_ENV_FAT_INTERFACE="mmc" ++CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto" ++CONFIG_ENV_FAT_FILE="uboot.env" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y + CONFIG_USE_ETHPRIME=y + CONFIG_ETHPRIME="FEC" + CONFIG_NETCONSOLE=y +@@ -102,3 +112,5 @@ CONFIG_VIDEO_BMP_GZIP=y + CONFIG_VIDEO_LOGO_MAX_SIZE=0x600000 + CONFIG_VIDEO_BMP_RLE8=y + CONFIG_BMP_16BPP=y ++CONFIG_FAT_WRITE=y ++CONFIG_FS_FAT=y diff -pruN 2025.01-3/debian/patches/use-cryptographically-safe-RNG.patch 2025.01-3ubuntu1/debian/patches/use-cryptographically-safe-RNG.patch --- 2025.01-3/debian/patches/use-cryptographically-safe-RNG.patch 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/patches/use-cryptographically-safe-RNG.patch 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,89 @@ +From 19725b319dcc2cabd2ad578a024524acb82daf10 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Tue, 11 Feb 2025 14:24:52 +0100 +Subject: [PATCH] tools: use cryptographically safe RNG + +The PRNG implementing the random() function only has 2^31 states and +therefore is unsafe to use for cryptography. Use arc4random() instead. + +Fixes: cc34f04efd63 ("tools: image-host.c: use random instead of rand") +Addresses-Coverity-ID: 312953 Calling risky function +Signed-off-by: Heinrich Schuchardt +--- + tools/image-host.c | 54 ++++++++++++++++++++++++++++------------------ + 1 file changed, 33 insertions(+), 21 deletions(-) + +diff --git a/tools/image-host.c b/tools/image-host.c +index 84095d760c1..cad3269f5ee 100644 +--- a/tools/image-host.c ++++ b/tools/image-host.c +@@ -364,33 +364,45 @@ static int fit_image_read_key_iv_data(const char *keydir, const char *key_iv_nam + return ret; + } + +-static int get_random_data(void *data, int size) +-{ +- unsigned char *tmp = data; +- struct timespec date; +- int i, ret; +- +- if (!tmp) { +- fprintf(stderr, "%s: pointer data is NULL\n", __func__); +- ret = -1; +- goto out; +- } ++/** ++ * get_random_data() - fill buffer with random data ++ * ++ * There is no common cryptographically safe function in Linux and BSD. ++ * Hence directly access the /dev/urandom PRNG. ++ * ++ * @data: buffer to fill ++ * @size: buffer size ++ */ ++static int get_random_data(void *data, size_t size) { ++ int fd; ++ int ret; + +- ret = clock_gettime(CLOCK_MONOTONIC, &date); +- if (ret) { +- fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__, +- strerror(errno)); +- goto out; ++ fd = open("/dev/urandom", O_RDONLY); ++ if (fd < 0) { ++ perror("Failed to open /dev/urandom"); ++ return -1; + } + +- srandom(date.tv_nsec); ++ while (size) { ++ ssize_t count; + +- for (i = 0; i < size; i++) { +- *tmp = random() & 0xff; +- tmp++; ++ count = read(fd, data, size); ++ if (count < 0) { ++ if (errno == EINTR) { ++ continue; ++ } else { ++ perror("Failed to read from /dev/urandom"); ++ ret = -1; ++ goto out; ++ } ++ } ++ data += count; ++ size -= count; + } ++ ret = 0; ++out: ++ close(fd); + +- out: + return ret; + } + +-- +2.43.0 + diff -pruN 2025.01-3/debian/rules 2025.01-3ubuntu1/debian/rules --- 2025.01-3/debian/rules 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/rules 2025-05-09 09:50:55.000000000 +0000 @@ -26,6 +26,8 @@ else VERBOSE=1 endif common_make_args += V=$(VERBOSE) +common_make_args += BINMAN_DEBUG=1 +common_make_args += BINMAN_VERBOSE=3 # the upstream build passes LDFLAGS directly to ld instead of calling gcc for # linking; so instead of passing -Wl,foo in LDFLAGS as in automake builds, one @@ -33,6 +35,9 @@ common_make_args += V=$(VERBOSE) comma := , LDFLAGS := $(patsubst -Wl$(comma)%,%,$(LDFLAGS)) +HOSTCFLAGS := $(CFLAGS) +export HOSTCFLAGS + notools := $(filter pkg.uboot.notools,$(DEB_BUILD_PROFILES)) subarchs := $(shell dh_listpackages --arch --no-package=u-boot-tools) @@ -58,9 +63,13 @@ ifneq (,$(only_platforms)) $(pkg)_platforms := $(filter $(only_platforms),$($(pkg)_platforms)))) endif +## Disable, as it breaks riscv64 booting # Enable debugging symbols and remove build paths -HOSTCFLAGS = -g -ffile-prefix-map=$(CURDIR)=. -common_make_args += HOSTCFLAGS='$(HOSTCFLAGS)' +#HOSTCFLAGS = -g -ffile-prefix-map=$(CURDIR)=. +#common_make_args += HOSTCFLAGS='$(HOSTCFLAGS)' + +# Exclude package notes to avoid FTBFS on oracular +unexport ELF_PACKAGE_METADATA %: dh $@ @@ -103,6 +112,10 @@ define build_template ifneq (,$(filter uboot.elf,$($(platform)_targets))) cp -u debian/build/$(platform)/u-boot debian/build/$(platform)/uboot.elf endif + ifeq ($(package),u-boot-microchip) + hss-payload-generator -c debian/microchip_mpfs_icicle.yaml \ + debian/build/microchip_mpfs_icicle/u-boot.payload + endif ifeq ($(package),u-boot-qemu) # TODO: --strip-unneeded as policy recommends? If not, why? $($(platform)_CROSS_COMPILE)strip --remove-section=.comment --remove-section=.note \ diff -pruN 2025.01-3/debian/targets.mk 2025.01-3ubuntu1/debian/targets.mk --- 2025.01-3/debian/targets.mk 2025-03-27 18:52:43.000000000 +0000 +++ 2025.01-3ubuntu1/debian/targets.mk 2025-05-09 09:50:54.000000000 +0000 @@ -373,6 +373,10 @@ else ifeq (${DEB_HOST_ARCH},armhf) u-boot-imx_platforms += nitrogen6q nitrogen6q_targets := u-boot-dtb.imx uboot.elf + # Shrirang Bagul + u-boot-imx_platforms += nitrogen6q2g + nitrogen6q2g_targets := u-boot-dtb.imx uboot.elf + # Vagrant Cascadian u-boot-imx_platforms += novena novena_targets := SPL u-boot.img uboot.elf @@ -658,6 +662,11 @@ else ifeq (${DEB_HOST_ARCH},armhf) else ifeq (${DEB_HOST_ARCH},riscv64) +# u-boot-microchip + + u-boot-microchip_platforms += microchip_mpfs_icicle + microchip_mpfs_icicle_targets := u-boot.bin + # u-boot-sifive dpkg-gencontrol_args += "-Vu-boot-sifive:Built-Using=$(shell dpkg-query -Wf \ diff -pruN 2025.01-3/debian/u-boot-amlogic-binaries.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-amlogic-binaries.lintian-overrides --- 2025.01-3/debian/u-boot-amlogic-binaries.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-amlogic-binaries.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-amlogic-binaries binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-amlogic-binaries binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-amlogic-binaries binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-amlogic-binaries binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-amlogic-binaries binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-amlogic-binaries binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-amlogic-binaries: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-exynos-binaries.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-exynos-binaries.lintian-overrides --- 2025.01-3/debian/u-boot-exynos-binaries.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-exynos-binaries.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-exynos-binaries binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos-binaries binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-exynos-binaries binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos-binaries binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-exynos-binaries binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos-binaries binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-exynos-binaries: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-exynos.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-exynos.lintian-overrides --- 2025.01-3/debian/u-boot-exynos.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-exynos.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-exynos binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-exynos binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-exynos binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-exynos binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-exynos: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-imx.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-imx.lintian-overrides --- 2025.01-3/debian/u-boot-imx.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-imx.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-imx binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-imx binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-imx binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-imx binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-imx binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-imx binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-imx: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-microchip.README.Debian 2025.01-3ubuntu1/debian/u-boot-microchip.README.Debian --- 2025.01-3/debian/u-boot-microchip.README.Debian 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.README.Debian 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,13 @@ +== Installation == + +The u-boot-microchip package installs U-Boot in its post installations script +to the partition named 'loader'. If that partition does not exist, you will +have to copy U-Boot manually. + +For the Microchip Icicle Kit, something like the following should work: + + dd conv=fsync,notrunc if=/usr/lib/u-boot/microchip_icicle/u-boot.payload \ + of=/dev/DEVICE + +Replace DEVICE by the partition with partition type EF02 +(GUID type 21686148-6449-6E6F-744E-656564454649) of the SD-card. diff -pruN 2025.01-3/debian/u-boot-microchip.docs 2025.01-3ubuntu1/debian/u-boot-microchip.docs --- 2025.01-3/debian/u-boot-microchip.docs 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.docs 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1 @@ +doc/board/microchip/mpfs_icicle.rst diff -pruN 2025.01-3/debian/u-boot-microchip.install 2025.01-3ubuntu1/debian/u-boot-microchip.install --- 2025.01-3/debian/u-boot-microchip.install 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.install 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1 @@ +debian/build/microchip_mpfs_icicle/u-boot.payload /usr/lib/u-boot/microchip_icicle diff -pruN 2025.01-3/debian/u-boot-microchip.links 2025.01-3ubuntu1/debian/u-boot-microchip.links --- 2025.01-3/debian/u-boot-microchip.links 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.links 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1 @@ +usr/lib/u-boot/microchip_icicle usr/lib/u-boot/doc/board/microchip/mpfs_icicle.rst diff -pruN 2025.01-3/debian/u-boot-microchip.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-microchip.lintian-overrides --- 2025.01-3/debian/u-boot-microchip.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -0,0 +1,15 @@ + +# There are no file conflicts across architectures for u-boot, as each +# target is only installed on a single architecture. In theory, some +# targets could be built on multiple architectures, but could instead install +# the package for the architecture needed. +u-boot-microchip binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] + +# These bootloaders need to be statically linked. +u-boot-microchip binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] + +# These are bootloader binaries, and have no external dependency information +u-boot-microchip binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] + +u-boot-microchip: description-synopsis-starts-with-article + diff -pruN 2025.01-3/debian/u-boot-microchip.postinst 2025.01-3ubuntu1/debian/u-boot-microchip.postinst --- 2025.01-3/debian/u-boot-microchip.postinst 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-microchip.postinst 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,19 @@ +#!/bin/sh + +##DEBHELPER## + +set -e + +case "$1" in + configure) + target="" + if grep -q '^Microchip PolarFire-SoC Icicle Kit$' /sys/firmware/devicetree/base/model; then + target="microchip_icicle" + fi + if [ -n "$target" ] && [ -e /dev/disk/by-partlabel/loader ]; then + dd if=/usr/lib/u-boot/$target/u-boot.payload of=/dev/disk/by-partlabel/loader + fi + ;; +esac + +exit 0 diff -pruN 2025.01-3/debian/u-boot-mvebu.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-mvebu.lintian-overrides --- 2025.01-3/debian/u-boot-mvebu.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-mvebu.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-mvebu binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-mvebu binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-mvebu binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-mvebu binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-mvebu binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-mvebu binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-mvebu: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-omap.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-omap.lintian-overrides --- 2025.01-3/debian/u-boot-omap.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-omap.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-omap binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-omap binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-omap binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-omap binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-omap binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-omap binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-omap: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-qcom.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-qcom.lintian-overrides --- 2025.01-3/debian/u-boot-qcom.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-qcom.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,16 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-qcom binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-qcom binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] +u-boot-qcom binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/u-boot.elf*] # These bootloaders need to be statically linked. -u-boot-qcom binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-qcom binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] +u-boot-qcom binary: statically-linked-binary [*usr/lib/u-boot/*/u-boot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-qcom binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-qcom binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] +u-boot-qcom binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/u-boot.elf*] u-boot-qcom: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-qemu.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-qemu.lintian-overrides --- 2025.01-3/debian/u-boot-qemu.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-qemu.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -1,11 +1,11 @@ # These bootloaders need to be statically linked. -u-boot-qemu binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-qemu binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-qemu binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-qemu binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-qemu: description-synopsis-starts-with-article # These are binary firmware blobs -u-boot-qemu binary: arch-independent-package-contains-binary-or-object *usr/lib/u-boot/*/uboot.elf* +u-boot-qemu binary: arch-independent-package-contains-binary-or-object [*usr/lib/u-boot/*/uboot.elf*] diff -pruN 2025.01-3/debian/u-boot-rockchip.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-rockchip.lintian-overrides --- 2025.01-3/debian/u-boot-rockchip.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-rockchip.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-rockchip binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-rockchip binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-rockchip binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-rockchip binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-rockchip binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-rockchip binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-rockchip: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-rpi.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-rpi.lintian-overrides --- 2025.01-3/debian/u-boot-rpi.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-rpi.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-rpi binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-rpi binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-rpi binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-rpi binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-rpi binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-rpi binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-rpi: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-rpi.triggers 2025.01-3ubuntu1/debian/u-boot-rpi.triggers --- 2025.01-3/debian/u-boot-rpi.triggers 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-rpi.triggers 2025-05-09 09:50:52.000000000 +0000 @@ -0,0 +1 @@ +activate-noawait flash-kernel diff -pruN 2025.01-3/debian/u-boot-sifive.links 2025.01-3ubuntu1/debian/u-boot-sifive.links --- 2025.01-3/debian/u-boot-sifive.links 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-sifive.links 2025-05-09 09:50:53.000000000 +0000 @@ -0,0 +1,2 @@ +usr/lib/u-boot/sifive_unleashed usr/lib/u-boot/sifive_fu540 +usr/lib/u-boot/sifive_unmatched usr/lib/u-boot/sifive_hifive_unmatched_fu740 diff -pruN 2025.01-3/debian/u-boot-sifive.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-sifive.lintian-overrides --- 2025.01-3/debian/u-boot-sifive.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-sifive.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-sifive binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-sifive binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-sifive binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-sifive binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-sifive binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-sifive binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-sifive: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-sifive.postinst 2025.01-3ubuntu1/debian/u-boot-sifive.postinst --- 2025.01-3/debian/u-boot-sifive.postinst 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-sifive.postinst 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,29 @@ +#!/bin/sh + +##DEBHELPER## + +set -e + +case "$1" in + configure) + target="" + if grep -q '^SiFive HiFive Unleashed A00$' /sys/firmware/devicetree/base/model; then + target="sifive_unleashed" + fi + if grep -q '^SiFive HiFive Unmatched A00$' /sys/firmware/devicetree/base/model; then + target="sifive_unmatched" + fi + if grep -q '^SiFive HiFive Unmatched$' /sys/firmware/devicetree/base/model; then + target="sifive_unmatched" + fi + if [ -n "$target" ] && [ -e /dev/disk/by-partlabel/loader1 ] && [ -e /dev/disk/by-partlabel/loader2 ]; then + dd if=/usr/lib/u-boot/$target/u-boot-spl.bin of=/dev/disk/by-partlabel/loader1 + dd if=/usr/lib/u-boot/$target/u-boot.itb of=/dev/disk/by-partlabel/loader2 + elif [ -n "$target" ] && [ -e /dev/disk/by-partlabel/Loader1 ] && [ -e /dev/disk/by-partlabel/Loader2 ]; then + dd if=/usr/lib/u-boot/$target/u-boot-spl.bin of=/dev/disk/by-partlabel/Loader1 + dd if=/usr/lib/u-boot/$target/u-boot.itb of=/dev/disk/by-partlabel/Loader2 + fi + ;; +esac + +exit 0 diff -pruN 2025.01-3/debian/u-boot-starfive.README.Debian 2025.01-3ubuntu1/debian/u-boot-starfive.README.Debian --- 2025.01-3/debian/u-boot-starfive.README.Debian 1970-01-01 00:00:00.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-starfive.README.Debian 2025-05-09 09:50:54.000000000 +0000 @@ -0,0 +1,15 @@ +StarFive VisionFive 2 +===================== + +Directory /usr/lib/u-boot/starfive_visionfive2/ contains the U-Boot binaries. + +The VisionFive 2 supports different boot sources (SPI flash, SD-card, eMMC, +UART) selected by DIP switches. + +/usr/share/doc/u-boot-starfive/visionfive2.rst.gz describes writing U-Boot to +boot from an SD card. + +Updating U-Boot on the SPI flash is described in +https://doc-en.rvspace.org/VisionFive2/PDF/VisionFive2_QSG.pdf, +chapter "3.8.1. Updating SPL and U-Boot of Flash". Replace the file name +visionfive2_fw_payload.img by u-boot.itb. diff -pruN 2025.01-3/debian/u-boot-stm32.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-stm32.lintian-overrides --- 2025.01-3/debian/u-boot-stm32.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-stm32.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,12 +3,12 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-stm32 binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-stm32 binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-stm32 binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-stm32 binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-stm32 binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-stm32 binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-stm32: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-sunxi.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-sunxi.lintian-overrides --- 2025.01-3/debian/u-boot-sunxi.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-sunxi.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-sunxi binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-sunxi binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-sunxi binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-sunxi binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-sunxi binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-sunxi binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-sunxi: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot-tegra.lintian-overrides 2025.01-3ubuntu1/debian/u-boot-tegra.lintian-overrides --- 2025.01-3/debian/u-boot-tegra.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot-tegra.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot-tegra binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot-tegra binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot-tegra binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot-tegra binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot-tegra binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot-tegra binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot-tegra: description-synopsis-starts-with-article diff -pruN 2025.01-3/debian/u-boot.lintian-overrides 2025.01-3ubuntu1/debian/u-boot.lintian-overrides --- 2025.01-3/debian/u-boot.lintian-overrides 2025-03-18 07:16:11.000000000 +0000 +++ 2025.01-3ubuntu1/debian/u-boot.lintian-overrides 2025-05-09 09:50:56.000000000 +0000 @@ -3,13 +3,13 @@ # target is only installed on a single architecture. In theory, some # targets could be built on multiple architectures, but could instead install # the package for the architecture needed. -u-boot binary: arch-dependent-file-not-in-arch-specific-directory *usr/lib/u-boot/*/uboot.elf* +u-boot binary: arch-dependent-file-not-in-arch-specific-directory [*usr/lib/u-boot/*/uboot.elf*] # These bootloaders need to be statically linked. -u-boot binary: statically-linked-binary *usr/lib/u-boot/*/uboot.elf* +u-boot binary: statically-linked-binary [*usr/lib/u-boot/*/uboot.elf*] # These are bootloader binaries, and have no external dependency information -u-boot binary: shared-library-lacks-prerequisites *usr/lib/u-boot/*/uboot.elf* +u-boot binary: shared-library-lacks-prerequisites [*usr/lib/u-boot/*/uboot.elf*] u-boot: description-synopsis-starts-with-article