diff -pruN 5882+dfsg-2/.clang-format 6641+dfsg-2/.clang-format --- 5882+dfsg-2/.clang-format 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.clang-format 2025-09-30 07:36:33.000000000 +0000 @@ -22,8 +22,15 @@ AllowShortIfStatementsOnASingleLine: Nev AllowShortLambdasOnASingleLine: Inline AllowShortLoopsOnASingleLine: false AlwaysBreakBeforeMultilineStrings: true +# Treat CUDA keywords/attributes as "attribute macros" and avoid breaking lines inside them +AttributeMacros: + - __host__ + - __device__ + - __global__ + - __forceinline__ + - __launch_bounds__ BinPackArguments: true -BinPackParameters: true # OnePerLine +BinPackParameters: false # OnePerLine BitFieldColonSpacing: Both BreakBeforeBraces: Custom # Attach BraceWrapping: @@ -70,15 +77,18 @@ ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true IncludeBlocks: Regroup IncludeCategories: - - Regex: '^<.*\.h>' + - Regex: '".*"' Priority: 1 SortPriority: 0 - - Regex: '^<.*' + - Regex: '^<.*\.h>' Priority: 2 SortPriority: 0 - - Regex: '.*' + - Regex: '^<.*' Priority: 3 SortPriority: 0 + - Regex: '.*' + Priority: 4 + SortPriority: 0 IncludeIsMainRegex: '([-_](test|unittest))?$' IncludeIsMainSourceRegex: '' IndentAccessModifiers: false diff -pruN 5882+dfsg-2/.clang-tidy 6641+dfsg-2/.clang-tidy --- 5882+dfsg-2/.clang-tidy 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.clang-tidy 2025-09-30 07:36:33.000000000 +0000 @@ -17,6 +17,7 @@ Checks: > clang-analyzer-*, -clang-analyzer-security.insecureAPI.DeprecatedOrUnsafeBufferHandling, performance-*, + -performance-enum-size, portability-*, -portability-simd-intrinsics, misc-*, diff -pruN 5882+dfsg-2/.devops/cann.Dockerfile 6641+dfsg-2/.devops/cann.Dockerfile --- 5882+dfsg-2/.devops/cann.Dockerfile 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.devops/cann.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,130 @@ +# ============================================================================== +# ARGUMENTS +# ============================================================================== + +# Define the CANN base image for easier version updates later +ARG CANN_BASE_IMAGE=quay.io/ascend/cann:8.1.rc1-910b-openeuler22.03-py3.10 + +# ============================================================================== +# BUILD STAGE +# Compile all binary files and libraries +# ============================================================================== +FROM ${CANN_BASE_IMAGE} AS build + +# Define the Ascend chip model for compilation. Default is Ascend910B3 +ARG ASCEND_SOC_TYPE=Ascend910B3 + +# -- Install build dependencies -- +RUN yum install -y gcc g++ cmake make git libcurl-devel python3 python3-pip && \ + yum clean all && \ + rm -rf /var/cache/yum + +# -- Set the working directory -- +WORKDIR /app + +# -- Copy project files -- +COPY . . + +# -- Set CANN environment variables (required for compilation) -- +# Using ENV instead of `source` allows environment variables to persist across the entire image layer +ENV ASCEND_TOOLKIT_HOME=/usr/local/Ascend/ascend-toolkit/latest +ENV LD_LIBRARY_PATH=${ASCEND_TOOLKIT_HOME}/lib64:${LD_LIBRARY_PATH} +ENV PATH=${ASCEND_TOOLKIT_HOME}/bin:${PATH} +ENV ASCEND_OPP_PATH=${ASCEND_TOOLKIT_HOME}/opp +ENV LD_LIBRARY_PATH=${ASCEND_TOOLKIT_HOME}/runtime/lib64/stub:$LD_LIBRARY_PATH +# ... You can add other environment variables from the original file as needed ... +# For brevity, only core variables are listed here. You can paste the original ENV list here. + +# -- Build llama.cpp -- +# Use the passed ASCEND_SOC_TYPE argument and add general build options +RUN source /usr/local/Ascend/ascend-toolkit/set_env.sh --force \ + && \ + cmake -B build \ + -DGGML_CANN=ON \ + -DCMAKE_BUILD_TYPE=Release \ + -DSOC_TYPE=${ASCEND_SOC_TYPE} \ + . && \ + cmake --build build --config Release -j$(nproc) + +# -- Organize build artifacts for copying in later stages -- +# Create a lib directory to store all .so files +RUN mkdir -p /app/lib && \ + find build -name "*.so" -exec cp {} /app/lib \; + +# Create a full directory to store all executables and Python scripts +RUN mkdir -p /app/full && \ + cp build/bin/* /app/full/ && \ + cp *.py /app/full/ && \ + cp -r gguf-py /app/full/ && \ + cp -r requirements /app/full/ && \ + cp requirements.txt /app/full/ + # If you have a tools.sh script, make sure it is copied here + # cp .devops/tools.sh /app/full/tools.sh + +# ============================================================================== +# BASE STAGE +# Create a minimal base image with CANN runtime and common libraries +# ============================================================================== +FROM ${CANN_BASE_IMAGE} AS base + +# -- Install runtime dependencies -- +RUN yum install -y libgomp curl && \ + yum clean all && \ + rm -rf /var/cache/yum + +# -- Set CANN environment variables (required for runtime) -- +ENV ASCEND_TOOLKIT_HOME=/usr/local/Ascend/ascend-toolkit/latest +ENV LD_LIBRARY_PATH=/app:${ASCEND_TOOLKIT_HOME}/lib64:${LD_LIBRARY_PATH} +ENV PATH=${ASCEND_TOOLKIT_HOME}/bin:${PATH} +ENV ASCEND_OPP_PATH=${ASCEND_TOOLKIT_HOME}/opp +# ... You can add other environment variables from the original file as needed ... + +WORKDIR /app + +# Copy compiled .so files from the build stage +COPY --from=build /app/lib/ /app + +# ============================================================================== +# FINAL STAGES (TARGETS) +# ============================================================================== + +### Target: full +# Complete image with all tools, Python bindings, and dependencies +# ============================================================================== +FROM base AS full + +COPY --from=build /app/full /app + +# Install Python dependencies +RUN yum install -y git python3 python3-pip && \ + pip3 install --no-cache-dir --upgrade pip setuptools wheel && \ + pip3 install --no-cache-dir -r requirements.txt && \ + yum clean all && \ + rm -rf /var/cache/yum + +# You need to provide a tools.sh script as the entrypoint +ENTRYPOINT ["/app/tools.sh"] +# If there is no tools.sh, you can set the default to start the server +# ENTRYPOINT ["/app/llama-server"] + +### Target: light +# Lightweight image containing only llama-cli +# ============================================================================== +FROM base AS light + +COPY --from=build /app/full/llama-cli /app + +ENTRYPOINT [ "/app/llama-cli" ] + +### Target: server +# Dedicated server image containing only llama-server +# ============================================================================== +FROM base AS server + +ENV LLAMA_ARG_HOST=0.0.0.0 + +COPY --from=build /app/full/llama-server /app + +HEALTHCHECK --interval=5m CMD [ "curl", "-f", "http://localhost:8080/health" ] + +ENTRYPOINT [ "/app/llama-server" ] diff -pruN 5882+dfsg-2/.devops/cloud-v-pipeline 6641+dfsg-2/.devops/cloud-v-pipeline --- 5882+dfsg-2/.devops/cloud-v-pipeline 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/cloud-v-pipeline 1970-01-01 00:00:00.000000000 +0000 @@ -1,22 +0,0 @@ -node('x86_runner1'){ // Running on x86 runner containing latest vector qemu, latest vector gcc and all the necessary libraries - stage('Cleanup'){ - cleanWs() // Cleaning previous CI build in workspace - } - stage('checkout repo'){ - retry(5){ // Retry if the cloning fails due to some reason - checkout scm // Clone the repo on Runner - } - } - stage('Compiling llama.cpp'){ - sh'''#!/bin/bash - make RISCV=1 RISCV_CROSS_COMPILE=1 # Compiling llama for RISC-V - ''' - } - stage('Running llama.cpp'){ - sh'''#!/bin/bash - module load gnu-bin2/0.1 # loading latest versions of vector qemu and vector gcc - qemu-riscv64 -L /softwares/gnu-bin2/sysroot -cpu rv64,v=true,vlen=256,elen=64,vext_spec=v1.0 ./llama-cli -m /home/alitariq/codellama-7b.Q4_K_M.gguf -p "Anything" -n 9 > llama_log.txt # Running llama.cpp on vector qemu-riscv64 - cat llama_log.txt # Printing results - ''' - } -} diff -pruN 5882+dfsg-2/.devops/cpu.Dockerfile 6641+dfsg-2/.devops/cpu.Dockerfile --- 5882+dfsg-2/.devops/cpu.Dockerfile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/cpu.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -4,8 +4,6 @@ FROM ubuntu:$UBUNTU_VERSION AS build ARG TARGETARCH -ARG GGML_CPU_ARM_ARCH=armv8-a - RUN apt-get update && \ apt-get install -y build-essential git cmake libcurl4-openssl-dev @@ -13,10 +11,8 @@ WORKDIR /app COPY . . -RUN if [ "$TARGETARCH" = "amd64" ]; then \ +RUN if [ "$TARGETARCH" = "amd64" ] || [ "$TARGETARCH" = "arm64" ]; then \ cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DGGML_NATIVE=OFF -DLLAMA_BUILD_TESTS=OFF -DGGML_BACKEND_DL=ON -DGGML_CPU_ALL_VARIANTS=ON; \ - elif [ "$TARGETARCH" = "arm64" ]; then \ - cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DGGML_NATIVE=OFF -DLLAMA_BUILD_TESTS=OFF -DGGML_CPU_ARM_ARCH=${GGML_CPU_ARM_ARCH}; \ else \ echo "Unsupported architecture"; \ exit 1; \ diff -pruN 5882+dfsg-2/.devops/cuda.Dockerfile 6641+dfsg-2/.devops/cuda.Dockerfile --- 5882+dfsg-2/.devops/cuda.Dockerfile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/cuda.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -61,7 +61,7 @@ RUN apt-get update \ python3 \ python3-pip \ && pip install --upgrade pip setuptools wheel \ - && pip install -r requirements.txt \ + && pip install --break-system-packages -r requirements.txt \ && apt autoremove -y \ && apt clean -y \ && rm -rf /tmp/* /var/tmp/* \ diff -pruN 5882+dfsg-2/.devops/musa.Dockerfile 6641+dfsg-2/.devops/musa.Dockerfile --- 5882+dfsg-2/.devops/musa.Dockerfile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/musa.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -1,10 +1,10 @@ ARG UBUNTU_VERSION=22.04 # This needs to generally match the container host's environment. -ARG MUSA_VERSION=rc4.0.1 +ARG MUSA_VERSION=rc4.3.0 # Target the MUSA build image -ARG BASE_MUSA_DEV_CONTAINER=mthreads/musa:${MUSA_VERSION}-mudnn-devel-ubuntu${UBUNTU_VERSION} +ARG BASE_MUSA_DEV_CONTAINER=mthreads/musa:${MUSA_VERSION}-devel-ubuntu${UBUNTU_VERSION}-amd64 -ARG BASE_MUSA_RUN_CONTAINER=mthreads/musa:${MUSA_VERSION}-mudnn-runtime-ubuntu${UBUNTU_VERSION} +ARG BASE_MUSA_RUN_CONTAINER=mthreads/musa:${MUSA_VERSION}-runtime-ubuntu${UBUNTU_VERSION}-amd64 FROM ${BASE_MUSA_DEV_CONTAINER} AS build diff -pruN 5882+dfsg-2/.devops/nix/package.nix 6641+dfsg-2/.devops/nix/package.nix --- 5882+dfsg-2/.devops/nix/package.nix 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/nix/package.nix 2025-09-30 07:36:33.000000000 +0000 @@ -47,6 +47,7 @@ let inherit (lib) cmakeBool cmakeFeature + optionalAttrs optionals strings ; @@ -197,7 +198,7 @@ effectiveStdenv.mkDerivation (finalAttrs ]; # Environment variables needed for ROCm - env = optionals useRocm { + env = optionalAttrs useRocm { ROCM_PATH = "${rocmPackages.clr}"; HIP_DEVICE_LIB_PATH = "${rocmPackages.rocm-device-libs}/amdgcn/bitcode"; }; diff -pruN 5882+dfsg-2/.devops/rocm.Dockerfile 6641+dfsg-2/.devops/rocm.Dockerfile --- 5882+dfsg-2/.devops/rocm.Dockerfile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/rocm.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -1,10 +1,10 @@ ARG UBUNTU_VERSION=24.04 # This needs to generally match the container host's environment. -ARG ROCM_VERSION=6.3 -ARG AMDGPU_VERSION=6.3 +ARG ROCM_VERSION=6.4 +ARG AMDGPU_VERSION=6.4 -# Target the CUDA build image +# Target the ROCm build image ARG BASE_ROCM_DEV_CONTAINER=rocm/dev-ubuntu-${UBUNTU_VERSION}:${ROCM_VERSION}-complete ### Build image @@ -15,16 +15,13 @@ FROM ${BASE_ROCM_DEV_CONTAINER} AS build # This is mostly tied to rocBLAS supported archs. # gfx803, gfx900, gfx1032, gfx1101, gfx1102,not officialy supported # gfx906 is deprecated -#check https://rocm.docs.amd.com/projects/install-on-linux/en/docs-6.2.4/reference/system-requirements.html +#check https://rocm.docs.amd.com/projects/install-on-linux/en/docs-6.4.1/reference/system-requirements.html -ARG ROCM_DOCKER_ARCH='gfx803,gfx900,gfx906,gfx908,gfx90a,gfx942,gfx1010,gfx1030,gfx1032,gfx1100,gfx1101,gfx1102' -#ARG ROCM_DOCKER_ARCH=gfx1100 +ARG ROCM_DOCKER_ARCH='gfx803;gfx900;gfx906;gfx908;gfx90a;gfx942;gfx1010;gfx1030;gfx1032;gfx1100;gfx1101;gfx1102;gfx1200;gfx1201;gfx1151' +#ARG ROCM_DOCKER_ARCH='gfx1151' -# Set nvcc architectured +# Set ROCm architectures ENV AMDGPU_TARGETS=${ROCM_DOCKER_ARCH} -# Enable ROCm -# ENV CC=/opt/rocm/llvm/bin/clang -# ENV CXX=/opt/rocm/llvm/bin/clang++ RUN apt-get update \ && apt-get install -y \ @@ -39,8 +36,16 @@ WORKDIR /app COPY . . +RUN git clone https://github.com/rocm/rocwmma --branch develop --depth 1 + RUN HIPCXX="$(hipconfig -l)/clang" HIP_PATH="$(hipconfig -R)" \ - cmake -S . -B build -DGGML_HIP=ON -DAMDGPU_TARGETS=$ROCM_DOCKER_ARCH -DGGML_BACKEND_DL=ON -DGGML_CPU_ALL_VARIANTS=ON -DCMAKE_BUILD_TYPE=Release -DLLAMA_BUILD_TESTS=OFF \ + cmake -S . -B build \ + -DGGML_HIP=ON \ + -DGGML_HIP_ROCWMMA_FATTN=ON \ + -DCMAKE_HIP_FLAGS="-I$(pwd)/rocwmma/library/include/" \ + -DAMDGPU_TARGETS="$ROCM_DOCKER_ARCH" \ + -DGGML_BACKEND_DL=ON -DGGML_CPU_ALL_VARIANTS=ON \ + -DCMAKE_BUILD_TYPE=Release -DLLAMA_BUILD_TESTS=OFF \ && cmake --build build --config Release -j$(nproc) RUN mkdir -p /app/lib \ diff -pruN 5882+dfsg-2/.devops/s390x.Dockerfile 6641+dfsg-2/.devops/s390x.Dockerfile --- 5882+dfsg-2/.devops/s390x.Dockerfile 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.devops/s390x.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,123 @@ +ARG GCC_VERSION=15.2.0 +ARG UBUNTU_VERSION=24.04 + +### Build Llama.cpp stage +FROM gcc:${GCC_VERSION} AS build + +RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ + --mount=type=cache,target=/var/lib/apt/lists,sharing=locked \ + apt update -y && \ + apt upgrade -y && \ + apt install -y --no-install-recommends \ + git cmake ccache ninja-build \ + # WARNING: Do not use libopenblas-openmp-dev. libopenblas-dev is faster. + libopenblas-dev libcurl4-openssl-dev && \ + rm -rf /var/lib/apt/lists/* + +WORKDIR /app +COPY . . + +RUN --mount=type=cache,target=/root/.ccache \ + --mount=type=cache,target=/app/build \ + cmake -S . -B build -G Ninja \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_C_COMPILER_LAUNCHER=ccache \ + -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \ + -DLLAMA_BUILD_TESTS=OFF \ + -DGGML_BACKEND_DL=OFF \ + -DGGML_NATIVE=OFF \ + -DGGML_BLAS=ON \ + -DGGML_BLAS_VENDOR=OpenBLAS && \ + cmake --build build --config Release -j $(nproc) && \ + cmake --install build --prefix /opt/llama.cpp + +COPY *.py /opt/llama.cpp/bin +COPY .devops/tools.sh /opt/llama.cpp/bin + +COPY gguf-py /opt/llama.cpp/gguf-py +COPY requirements.txt /opt/llama.cpp/gguf-py +COPY requirements /opt/llama.cpp/gguf-py/requirements + + +### Collect all llama.cpp binaries, libraries and distro libraries +FROM scratch AS collector + +# Copy llama.cpp binaries and libraries +COPY --from=build /opt/llama.cpp/bin /llama.cpp/bin +COPY --from=build /opt/llama.cpp/lib /llama.cpp/lib +COPY --from=build /opt/llama.cpp/gguf-py /llama.cpp/gguf-py + + +### Base image +FROM ubuntu:${UBUNTU_VERSION} AS base + +RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ + --mount=type=cache,target=/var/lib/apt/lists,sharing=locked \ + apt update -y && \ + apt install -y --no-install-recommends \ + # WARNING: Do not use libopenblas-openmp-dev. libopenblas-dev is faster. + # See: https://github.com/ggml-org/llama.cpp/pull/15915#issuecomment-3317166506 + curl libgomp1 libopenblas-dev && \ + apt autoremove -y && \ + apt clean -y && \ + rm -rf /tmp/* /var/tmp/* && \ + find /var/cache/apt/archives /var/lib/apt/lists -not -name lock -type f -delete && \ + find /var/cache -type f -delete + +# Copy llama.cpp libraries +COPY --from=collector /llama.cpp/lib /usr/lib/s390x-linux-gnu + + +### Full +FROM base AS full + +ENV PATH="/root/.cargo/bin:${PATH}" +WORKDIR /app + +RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ + --mount=type=cache,target=/var/lib/apt/lists,sharing=locked \ + apt update -y && \ + apt install -y \ + git cmake libjpeg-dev \ + python3 python3-pip python3-dev && \ + apt autoremove -y && \ + apt clean -y && \ + rm -rf /tmp/* /var/tmp/* && \ + find /var/cache/apt/archives /var/lib/apt/lists -not -name lock -type f -delete && \ + find /var/cache -type f -delete + +RUN curl https://sh.rustup.rs -sSf | bash -s -- -y + +COPY --from=collector /llama.cpp/bin /app +COPY --from=collector /llama.cpp/gguf-py /app/gguf-py + +RUN pip install --no-cache-dir --break-system-packages \ + -r /app/gguf-py/requirements.txt + +ENTRYPOINT [ "/app/tools.sh" ] + + +### CLI Only +FROM base AS light + +WORKDIR /llama.cpp/bin + +# Copy llama.cpp binaries and libraries +COPY --from=collector /llama.cpp/bin/llama-cli /llama.cpp/bin + +ENTRYPOINT [ "/llama.cpp/bin/llama-cli" ] + + +### Server +FROM base AS server + +ENV LLAMA_ARG_HOST=0.0.0.0 + +WORKDIR /llama.cpp/bin + +# Copy llama.cpp binaries and libraries +COPY --from=collector /llama.cpp/bin/llama-server /llama.cpp/bin + +EXPOSE 8080 + +ENTRYPOINT [ "/llama.cpp/bin/llama-server" ] diff -pruN 5882+dfsg-2/.devops/vulkan.Dockerfile 6641+dfsg-2/.devops/vulkan.Dockerfile --- 5882+dfsg-2/.devops/vulkan.Dockerfile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.devops/vulkan.Dockerfile 2025-09-30 07:36:33.000000000 +0000 @@ -2,14 +2,30 @@ ARG UBUNTU_VERSION=24.04 FROM ubuntu:$UBUNTU_VERSION AS build +# Ref: https://vulkan.lunarg.com/doc/sdk/latest/linux/getting_started.html + # Install build tools -RUN apt update && apt install -y git build-essential cmake wget +RUN apt update && apt install -y git build-essential cmake wget xz-utils + +# Install Vulkan SDK +ARG VULKAN_VERSION=1.4.321.1 +RUN ARCH=$(uname -m) && \ + wget -qO /tmp/vulkan-sdk.tar.xz https://sdk.lunarg.com/sdk/download/${VULKAN_VERSION}/linux/vulkan-sdk-linux-${ARCH}-${VULKAN_VERSION}.tar.xz && \ + mkdir -p /opt/vulkan && \ + tar -xf /tmp/vulkan-sdk.tar.xz -C /tmp --strip-components=1 && \ + mv /tmp/${ARCH}/* /opt/vulkan/ && \ + rm -rf /tmp/* + +# Install cURL and Vulkan SDK dependencies +RUN apt install -y libcurl4-openssl-dev curl \ + libxcb-xinput0 libxcb-xinerama0 libxcb-cursor-dev -# Install Vulkan SDK and cURL -RUN wget -qO - https://packages.lunarg.com/lunarg-signing-key-pub.asc | apt-key add - && \ - wget -qO /etc/apt/sources.list.d/lunarg-vulkan-noble.list https://packages.lunarg.com/vulkan/lunarg-vulkan-noble.list && \ - apt update -y && \ - apt-get install -y vulkan-sdk libcurl4-openssl-dev curl +# Set environment variables +ENV VULKAN_SDK=/opt/vulkan +ENV PATH=$VULKAN_SDK/bin:$PATH +ENV LD_LIBRARY_PATH=$VULKAN_SDK/lib:$LD_LIBRARY_PATH +ENV CMAKE_PREFIX_PATH=$VULKAN_SDK:$CMAKE_PREFIX_PATH +ENV PKG_CONFIG_PATH=$VULKAN_SDK/lib/pkgconfig:$PKG_CONFIG_PATH # Build it WORKDIR /app diff -pruN 5882+dfsg-2/.editorconfig 6641+dfsg-2/.editorconfig --- 5882+dfsg-2/.editorconfig 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.editorconfig 2025-09-30 07:36:33.000000000 +0000 @@ -52,3 +52,11 @@ insert_final_newline = unset [vendor/miniaudio/miniaudio.h] trim_trailing_whitespace = unset insert_final_newline = unset + +[tools/server/webui/**] +indent_style = unset +indent_size = unset +end_of_line = unset +charset = unset +trim_trailing_whitespace = unset +insert_final_newline = unset diff -pruN 5882+dfsg-2/.github/ISSUE_TEMPLATE/010-bug-compilation.yml 6641+dfsg-2/.github/ISSUE_TEMPLATE/010-bug-compilation.yml --- 5882+dfsg-2/.github/ISSUE_TEMPLATE/010-bug-compilation.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/ISSUE_TEMPLATE/010-bug-compilation.yml 2025-09-30 07:36:33.000000000 +0000 @@ -40,7 +40,7 @@ body: attributes: label: GGML backends description: Which GGML backends do you know to be affected? - options: [AMX, BLAS, CPU, CUDA, HIP, Metal, Musa, RPC, SYCL, Vulkan, OpenCL] + options: [AMX, BLAS, CPU, CUDA, HIP, Metal, Musa, RPC, SYCL, Vulkan, OpenCL, zDNN] multiple: true validations: required: true diff -pruN 5882+dfsg-2/.github/ISSUE_TEMPLATE/011-bug-results.yml 6641+dfsg-2/.github/ISSUE_TEMPLATE/011-bug-results.yml --- 5882+dfsg-2/.github/ISSUE_TEMPLATE/011-bug-results.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/ISSUE_TEMPLATE/011-bug-results.yml 2025-09-30 07:36:33.000000000 +0000 @@ -42,7 +42,7 @@ body: attributes: label: GGML backends description: Which GGML backends do you know to be affected? - options: [AMX, BLAS, CPU, CUDA, HIP, Metal, Musa, RPC, SYCL, Vulkan, OpenCL] + options: [AMX, BLAS, CPU, CUDA, HIP, Metal, Musa, RPC, SYCL, Vulkan, OpenCL, zDNN] multiple: true validations: required: true diff -pruN 5882+dfsg-2/.github/copilot-instructions.md 6641+dfsg-2/.github/copilot-instructions.md --- 5882+dfsg-2/.github/copilot-instructions.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.github/copilot-instructions.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,262 @@ +# Copilot Instructions for llama.cpp + +## Repository Overview + +llama.cpp is a large-scale C/C++ project for efficient LLM (Large Language Model) inference with minimal setup and dependencies. The project enables running language models on diverse hardware with state-of-the-art performance. + +**Key Facts:** +- **Primary language**: C/C++ with Python utility scripts +- **Size**: ~200k+ lines of code across 1000+ files +- **Architecture**: Modular design with main library (`libllama`) and 40+ executable tools/examples +- **Core dependency**: ggml tensor library (vendored in `ggml/` directory) +- **Backends supported**: CPU (AVX/NEON optimized), CUDA, Metal, Vulkan, SYCL, ROCm, MUSA +- **License**: MIT + +## Build Instructions + +### Prerequisites +- CMake 3.14+ (primary build system) +- C++17 compatible compiler (GCC 13.3+, Clang, MSVC) +- Optional: ccache for faster compilation + +### Basic Build (CPU-only) +**ALWAYS run these commands in sequence:** +```bash +cmake -B build +cmake --build build --config Release -j $(nproc) +``` + +**Build time**: ~10 minutes on 4-core system with ccache enabled, ~25 minutes without ccache. + +**Important Notes:** +- The Makefile is deprecated - always use CMake +- ccache is automatically detected and used if available +- Built binaries are placed in `build/bin/` +- Parallel builds (`-j`) significantly reduce build time + +### Backend-Specific Builds +For CUDA support: +```bash +cmake -B build -DGGML_CUDA=ON +cmake --build build --config Release -j $(nproc) +``` + +For Metal (macOS): +```bash +cmake -B build -DGGML_METAL=ON +cmake --build build --config Release -j $(nproc) +``` + +**Important Note**: While all backends can be built as long as the correct requirements for that backend are installed, you will not be able to run them without the correct hardware. The only backend that can be run for testing and validation is the CPU backend. + +### Debug Builds +Single-config generators: +```bash +cmake -B build -DCMAKE_BUILD_TYPE=Debug +cmake --build build +``` + +Multi-config generators: +```bash +cmake -B build -G "Xcode" +cmake --build build --config Debug +``` + +### Common Build Issues +- **Issue**: Network tests fail in isolated environments + **Solution**: Expected behavior - core functionality tests will still pass + +## Testing + +### Running Tests +```bash +ctest --test-dir build --output-on-failure -j $(nproc) +``` + +**Test suite**: 38 tests covering tokenizers, grammar parsing, sampling, backends, and integration +**Expected failures**: 2-3 tests may fail if network access is unavailable (they download models) +**Test time**: ~30 seconds for passing tests + +### Server Unit Tests +Run server-specific unit tests after building the server: +```bash +# Build the server first +cmake --build build --target llama-server + +# Navigate to server tests and run +cd tools/server/tests +source ../../../.venv/bin/activate +./tests.sh +``` +**Server test dependencies**: The `.venv` environment includes the required dependencies for server unit tests (pytest, aiohttp, etc.). Tests can be run individually or with various options as documented in `tools/server/tests/README.md`. + +### Test Categories +- Tokenizer tests: Various model tokenizers (BERT, GPT-2, LLaMA, etc.) +- Grammar tests: GBNF parsing and validation +- Backend tests: Core ggml operations across different backends +- Integration tests: End-to-end workflows + +### Manual Testing Commands +```bash +# Test basic inference +./build/bin/llama-cli --version + +# Test model loading (requires model file) +./build/bin/llama-cli -m path/to/model.gguf -p "Hello" -n 10 +``` + +## Code Quality and Linting + +### C++ Code Formatting +**ALWAYS format C++ code before committing:** +```bash +git clang-format +``` + +Configuration is in `.clang-format` with these key rules: +- 4-space indentation +- 120 column limit +- Braces on same line for functions +- Pointer alignment: `void * ptr` (middle) +- Reference alignment: `int & ref` (middle) + +### Python Code +**ALWAYS activate the Python environment in `.venv` and use tools from that environment:** +```bash +# Activate virtual environment +source .venv/bin/activate +``` + +Configuration files: +- `.flake8`: flake8 settings (max-line-length=125, excludes examples/tools) +- `pyrightconfig.json`: pyright type checking configuration + +### Pre-commit Hooks +Run before committing: +```bash +pre-commit run --all-files +``` + +## Continuous Integration + +### GitHub Actions Workflows +Key workflows that run on every PR: +- `.github/workflows/build.yml`: Multi-platform builds +- `.github/workflows/server.yml`: Server functionality tests +- `.github/workflows/python-lint.yml`: Python code quality +- `.github/workflows/python-type-check.yml`: Python type checking + +### Local CI Validation +**Run full CI locally before submitting PRs:** +```bash +mkdir tmp + +# CPU-only build +bash ./ci/run.sh ./tmp/results ./tmp/mnt +``` + +**CI Runtime**: 30-60 minutes depending on backend configuration + +### Triggering CI +Add `ggml-ci` to commit message to trigger heavy CI workloads on the custom CI infrastructure. + +## Project Layout and Architecture + +### Core Directories +- **`src/`**: Main llama library implementation (`llama.cpp`, `llama-*.cpp`) +- **`include/`**: Public API headers, primarily `include/llama.h` +- **`ggml/`**: Core tensor library (submodule with custom GGML framework) +- **`examples/`**: 30+ example applications and tools +- **`tools/`**: Additional development and utility tools (server benchmarks, tests) +- **`tests/`**: Comprehensive test suite with CTest integration +- **`docs/`**: Detailed documentation (build guides, API docs, etc.) +- **`scripts/`**: Utility scripts for CI, data processing, and automation +- **`common/`**: Shared utility code used across examples + +### Key Files +- **`CMakeLists.txt`**: Primary build configuration +- **`include/llama.h`**: Main C API header (~2000 lines) +- **`src/llama.cpp`**: Core library implementation (~8000 lines) +- **`CONTRIBUTING.md`**: Coding guidelines and PR requirements +- **`.clang-format`**: C++ formatting rules +- **`.pre-commit-config.yaml`**: Git hook configuration + +### Built Executables (in `build/bin/`) +Primary tools: +- **`llama-cli`**: Main inference tool +- **`llama-server`**: OpenAI-compatible HTTP server +- **`llama-quantize`**: Model quantization utility +- **`llama-perplexity`**: Model evaluation tool +- **`llama-bench`**: Performance benchmarking +- **`llama-convert-llama2c-to-ggml`**: Model conversion utilities + +### Configuration Files +- **CMake**: `CMakeLists.txt`, `cmake/` directory +- **Linting**: `.clang-format`, `.clang-tidy`, `.flake8` +- **CI**: `.github/workflows/`, `ci/run.sh` +- **Git**: `.gitignore` (includes build artifacts, models, cache) + +### Dependencies +- **System**: OpenMP, libcurl (for model downloading) +- **Optional**: CUDA SDK, Metal framework, Vulkan SDK, Intel oneAPI +- **Bundled**: httplib, json (header-only libraries in vendored form) + +## Common Validation Steps + +### After Making Changes +1. **Format code**: `git clang-format` +2. **Build**: `cmake --build build --config Release` +3. **Test**: `ctest --test-dir build --output-on-failure` +4. **Server tests** (if modifying server): `cd tools/server/tests && source ../../../.venv/bin/activate && ./tests.sh` +5. **Manual validation**: Test relevant tools in `build/bin/` + +### Performance Validation +```bash +# Benchmark inference performance +./build/bin/llama-bench -m model.gguf + +# Evaluate model perplexity +./build/bin/llama-perplexity -m model.gguf -f dataset.txt +``` + +### Backend Validation +```bash +# Test backend operations +./build/bin/test-backend-ops +``` + +## Environment Setup + +### Required Tools +- CMake 3.14+ (install via system package manager) +- Modern C++ compiler with C++17 support +- Git (for submodule management) +- Python 3.9+ with virtual environment (`.venv` is provided) + +### Optional but Recommended +- ccache: `apt install ccache` or `brew install ccache` +- clang-format 15+: Usually included with LLVM/Clang installation +- pre-commit: `pip install pre-commit` + +### Backend-Specific Requirements +- **CUDA**: NVIDIA CUDA Toolkit 11.2+ +- **Metal**: Xcode command line tools (macOS only) +- **Vulkan**: Vulkan SDK +- **SYCL**: Intel oneAPI toolkit + +## Important Guidelines + +### Code Changes +- **Minimal dependencies**: Avoid adding new external dependencies +- **Cross-platform compatibility**: Test on Linux, macOS, Windows when possible +- **Performance focus**: This is a performance-critical inference library +- **API stability**: Changes to `include/llama.h` require careful consideration + +### Git Workflow +- Always create feature branches from `master` +- **Never** commit build artifacts (`build/`, `.ccache/`, `*.o`, `*.gguf`) +- Use descriptive commit messages following project conventions + +### Trust These Instructions +Only search for additional information if these instructions are incomplete or found to be incorrect. This document contains validated build and test procedures that work reliably across different environments. + diff -pruN 5882+dfsg-2/.github/labeler.yml 6641+dfsg-2/.github/labeler.yml --- 5882+dfsg-2/.github/labeler.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/labeler.yml 2025-09-30 07:36:33.000000000 +0000 @@ -22,6 +22,11 @@ Vulkan: - any-glob-to-any-file: - ggml/include/ggml-vulkan.h - ggml/src/ggml-vulkan/** +IBM zDNN: + - changed-files: + - any-glob-to-any-file: + - ggml/include/ggml-zdnn.h + - ggml/src/ggml-zdnn/** documentation: - changed-files: - any-glob-to-any-file: diff -pruN 5882+dfsg-2/.github/workflows/build-amd.yml 6641+dfsg-2/.github/workflows/build-amd.yml --- 5882+dfsg-2/.github/workflows/build-amd.yml 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/build-amd.yml 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,52 @@ +name: CI (AMD) + +on: + workflow_dispatch: # allows manual triggering + push: + branches: + - master + paths: [ + '.github/workflows/build-amd.yml', + '**/CMakeLists.txt', + '**/.cmake', + '**/*.h', + '**/*.hpp', + '**/*.c', + '**/*.cpp', + '**/*.cu', + '**/*.cuh', + '**/*.comp' + ] + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref && github.ref || github.run_id }} + cancel-in-progress: true + +jobs: + ggml-ci-x64-amd-vulkan: + runs-on: [self-hosted, Linux, X64, AMD] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + vulkaninfo --summary + GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp + + ggml-ci-x64-amd-rocm: + runs-on: [self-hosted, Linux, X64, AMD] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + amd-smi static + GG_BUILD_ROCM=1 GG_BUILD_AMDGPU_TARGETS="gfx1101" bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp diff -pruN 5882+dfsg-2/.github/workflows/build-linux-cross.yml 6641+dfsg-2/.github/workflows/build-linux-cross.yml --- 5882+dfsg-2/.github/workflows/build-linux-cross.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/build-linux-cross.yml 2025-09-30 07:36:33.000000000 +0000 @@ -48,189 +48,98 @@ jobs: cmake --build build --config Release -j $(nproc) - ubuntu-24-riscv64-vulkan-cross: - runs-on: ubuntu-24.04 - - steps: - - uses: actions/checkout@v4 - - name: Setup Riscv - run: | - sudo dpkg --add-architecture riscv64 - - # Add arch-specific repositories for non-amd64 architectures - cat << EOF | sudo tee /etc/apt/sources.list.d/riscv64-ports.list - deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble main universe - deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe - deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe - deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe - EOF - - sudo apt-get update || true ;# Prevent failure due to missing URLs. - - sudo apt-get install -y --no-install-recommends \ - build-essential \ - glslc \ - gcc-14-riscv64-linux-gnu \ - g++-14-riscv64-linux-gnu \ - libvulkan-dev:riscv64 - - - name: Build - run: | - cmake -B build -DLLAMA_CURL=OFF \ - -DCMAKE_BUILD_TYPE=Release \ - -DGGML_VULKAN=ON \ - -DGGML_OPENMP=OFF \ - -DLLAMA_BUILD_EXAMPLES=ON \ - -DLLAMA_BUILD_TOOLS=ON \ - -DLLAMA_BUILD_TESTS=OFF \ - -DCMAKE_SYSTEM_NAME=Linux \ - -DCMAKE_SYSTEM_PROCESSOR=riscv64 \ - -DCMAKE_C_COMPILER=riscv64-linux-gnu-gcc-14 \ - -DCMAKE_CXX_COMPILER=riscv64-linux-gnu-g++-14 \ - -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ - -DCMAKE_FIND_ROOT_PATH=/usr/lib/riscv64-linux-gnu \ - -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ - -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ - -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH - - cmake --build build --config Release -j $(nproc) - - ubuntu-24-arm64-vulkan-cross: - runs-on: ubuntu-24.04 - - steps: - - uses: actions/checkout@v4 - - name: Setup Arm64 - run: | - sudo dpkg --add-architecture arm64 - - # Add arch-specific repositories for non-amd64 architectures - cat << EOF | sudo tee /etc/apt/sources.list.d/arm64-ports.list - deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble main universe - deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe - deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe - deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe - EOF - - sudo apt-get update || true ;# Prevent failure due to missing URLs. - - sudo apt-get install -y --no-install-recommends \ - build-essential \ - glslc \ - crossbuild-essential-arm64 \ - libvulkan-dev:arm64 - - - name: Build - run: | - cmake -B build -DLLAMA_CURL=OFF \ - -DCMAKE_BUILD_TYPE=Release \ - -DGGML_VULKAN=ON \ - -DGGML_OPENMP=OFF \ - -DLLAMA_BUILD_EXAMPLES=ON \ - -DLLAMA_BUILD_TOOLS=ON \ - -DLLAMA_BUILD_TESTS=OFF \ - -DCMAKE_SYSTEM_NAME=Linux \ - -DCMAKE_SYSTEM_PROCESSOR=aarch64 \ - -DCMAKE_C_COMPILER=aarch64-linux-gnu-gcc \ - -DCMAKE_CXX_COMPILER=aarch64-linux-gnu-g++ \ - -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ - -DCMAKE_FIND_ROOT_PATH=/usr/lib/aarch64-linux-gnu \ - -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ - -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ - -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH + # ubuntu-24-riscv64-vulkan-cross: + # runs-on: ubuntu-24.04 - cmake --build build --config Release -j $(nproc) + # steps: + # - uses: actions/checkout@v4 + # - name: Setup Riscv + # run: | + # sudo dpkg --add-architecture riscv64 + + # # Add arch-specific repositories for non-amd64 architectures + # cat << EOF | sudo tee /etc/apt/sources.list.d/riscv64-ports.list + # deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble main universe + # deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe + # deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe + # deb [arch=riscv64] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe + # EOF + + # sudo apt-get update || true ;# Prevent failure due to missing URLs. + + # sudo apt-get install -y --no-install-recommends \ + # build-essential \ + # glslc \ + # gcc-14-riscv64-linux-gnu \ + # g++-14-riscv64-linux-gnu \ + # libvulkan-dev:riscv64 + + # - name: Build + # run: | + # cmake -B build -DLLAMA_CURL=OFF \ + # -DCMAKE_BUILD_TYPE=Release \ + # -DGGML_VULKAN=ON \ + # -DGGML_OPENMP=OFF \ + # -DLLAMA_BUILD_EXAMPLES=ON \ + # -DLLAMA_BUILD_TOOLS=ON \ + # -DLLAMA_BUILD_TESTS=OFF \ + # -DCMAKE_SYSTEM_NAME=Linux \ + # -DCMAKE_SYSTEM_PROCESSOR=riscv64 \ + # -DCMAKE_C_COMPILER=riscv64-linux-gnu-gcc-14 \ + # -DCMAKE_CXX_COMPILER=riscv64-linux-gnu-g++-14 \ + # -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + # -DCMAKE_FIND_ROOT_PATH=/usr/lib/riscv64-linux-gnu \ + # -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ + # -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ + # -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH + + # cmake --build build --config Release -j $(nproc) + + # ubuntu-24-arm64-vulkan-cross: + # runs-on: ubuntu-24.04 + + # steps: + # - uses: actions/checkout@v4 + # - name: Setup Arm64 + # run: | + # sudo dpkg --add-architecture arm64 + + # # Add arch-specific repositories for non-amd64 architectures + # cat << EOF | sudo tee /etc/apt/sources.list.d/arm64-ports.list + # deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble main universe + # deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe + # deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe + # deb [arch=arm64] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe + # EOF + + # sudo apt-get update || true ;# Prevent failure due to missing URLs. + + # sudo apt-get install -y --no-install-recommends \ + # build-essential \ + # glslc \ + # crossbuild-essential-arm64 \ + # libvulkan-dev:arm64 + + # - name: Build + # run: | + # cmake -B build -DLLAMA_CURL=OFF \ + # -DCMAKE_BUILD_TYPE=Release \ + # -DGGML_VULKAN=ON \ + # -DGGML_OPENMP=OFF \ + # -DLLAMA_BUILD_EXAMPLES=ON \ + # -DLLAMA_BUILD_TOOLS=ON \ + # -DLLAMA_BUILD_TESTS=OFF \ + # -DCMAKE_SYSTEM_NAME=Linux \ + # -DCMAKE_SYSTEM_PROCESSOR=aarch64 \ + # -DCMAKE_C_COMPILER=aarch64-linux-gnu-gcc \ + # -DCMAKE_CXX_COMPILER=aarch64-linux-gnu-g++ \ + # -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + # -DCMAKE_FIND_ROOT_PATH=/usr/lib/aarch64-linux-gnu \ + # -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ + # -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ + # -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH - ubuntu-24-ppc64el-cpu-cross: - runs-on: ubuntu-24.04 - - steps: - - uses: actions/checkout@v4 - - name: Setup PowerPC64le - run: | - sudo dpkg --add-architecture ppc64el - - # Add arch-specific repositories for non-amd64 architectures - cat << EOF | sudo tee /etc/apt/sources.list.d/ppc64el-ports.list - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe - EOF - - sudo apt-get update || true ;# Prevent failure due to missing URLs. - - sudo apt-get install -y --no-install-recommends \ - build-essential \ - gcc-14-powerpc64le-linux-gnu \ - g++-14-powerpc64le-linux-gnu - - - name: Build - run: | - cmake -B build -DLLAMA_CURL=OFF \ - -DCMAKE_BUILD_TYPE=Release \ - -DGGML_OPENMP=OFF \ - -DLLAMA_BUILD_EXAMPLES=ON \ - -DLLAMA_BUILD_TOOLS=ON \ - -DLLAMA_BUILD_TESTS=OFF \ - -DCMAKE_SYSTEM_NAME=Linux \ - -DCMAKE_SYSTEM_PROCESSOR=ppc64 \ - -DCMAKE_C_COMPILER=powerpc64le-linux-gnu-gcc-14 \ - -DCMAKE_CXX_COMPILER=powerpc64le-linux-gnu-g++-14 \ - -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ - -DCMAKE_FIND_ROOT_PATH=/usr/lib/powerpc64le-linux-gnu \ - -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ - -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ - -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH - - cmake --build build --config Release -j $(nproc) - - ubuntu-24-ppc64el-vulkan-cross: - runs-on: ubuntu-24.04 - - steps: - - uses: actions/checkout@v4 - - name: Setup PowerPC64le - run: | - sudo dpkg --add-architecture ppc64el - - # Add arch-specific repositories for non-amd64 architectures - cat << EOF | sudo tee /etc/apt/sources.list.d/ppc64el-ports.list - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-updates main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-security main universe - deb [arch=ppc64el] http://ports.ubuntu.com/ubuntu-ports/ noble-backports main universe - EOF - - sudo apt-get update || true ;# Prevent failure due to missing URLs. - - sudo apt-get install -y --no-install-recommends \ - build-essential \ - glslc \ - gcc-14-powerpc64le-linux-gnu \ - g++-14-powerpc64le-linux-gnu \ - libvulkan-dev:ppc64el - - - name: Build - run: | - cmake -B build -DLLAMA_CURL=OFF \ - -DCMAKE_BUILD_TYPE=Release \ - -DGGML_VULKAN=ON \ - -DGGML_OPENMP=OFF \ - -DLLAMA_BUILD_EXAMPLES=ON \ - -DLLAMA_BUILD_TOOLS=ON \ - -DLLAMA_BUILD_TESTS=OFF \ - -DCMAKE_SYSTEM_NAME=Linux \ - -DCMAKE_SYSTEM_PROCESSOR=ppc64 \ - -DCMAKE_C_COMPILER=powerpc64le-linux-gnu-gcc-14 \ - -DCMAKE_CXX_COMPILER=powerpc64le-linux-gnu-g++-14 \ - -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ - -DCMAKE_FIND_ROOT_PATH=/usr/lib/powerpc64le-linux-gnu \ - -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ - -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ - -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH - - cmake --build build --config Release -j $(nproc) + # cmake --build build --config Release -j $(nproc) debian-13-loongarch64-cpu-cross: runs-on: ubuntu-24.04 @@ -344,3 +253,47 @@ jobs: -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH cmake --build build --config Release -j $(nproc) + + ubuntu-24-riscv64-cpu-spacemit-ime-cross: + runs-on: ubuntu-24.04 + + env: + SPACEMIT_IME_TOOLCHAIN_VERSION: "1.1.2" + SPACEMIT_IME_TOOLCHAIN_PATH: "spacemit-toolchain-linux-glibc-x86_64" + + steps: + - uses: actions/checkout@v4 + + - name: Cache Toolchain + uses: actions/cache@v4 + id: cache-spacemit-ime-cross-toolchain + with: + path: ./${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }} + key: ${{ runner.os }}-spacemit-ime-toolchain-v${{ env.SPACEMIT_IME_TOOLCHAIN_VERSION }} + + - name: Setup Toolchain + if: steps.cache-spacemit-ime-cross-toolchain.outputs.cache-hit != 'true' + run: | + wget --quiet --no-check-certificate https://archive.spacemit.com/toolchain/spacemit-toolchain-linux-glibc-x86_64-v${{ env.SPACEMIT_IME_TOOLCHAIN_VERSION }}.tar.xz -O ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }}.tar.xz + rm -rf ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }} + mkdir -p ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }} + tar xf ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }}.tar.xz -C ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }} --strip-components=1 + rm -rf ${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }}.tar.xz + + - name: Build + run: | + export RISCV_ROOT_PATH=${PWD}/${{ env.SPACEMIT_IME_TOOLCHAIN_PATH }} + cmake -B build -DLLAMA_CURL=OFF \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_OPENMP=OFF \ + -DLLAMA_BUILD_EXAMPLES=ON \ + -DLLAMA_BUILD_TOOLS=ON \ + -DLLAMA_BUILD_TESTS=OFF \ + -DGGML_CPU_RISCV64_SPACEMIT=ON \ + -DGGML_RVV=ON \ + -DGGML_RV_ZFH=ON \ + -DGGML_RV_ZICBOP=ON \ + -DRISCV64_SPACEMIT_IME_SPEC=RISCV64_SPACEMIT_IME1 \ + -DCMAKE_TOOLCHAIN_FILE=${PWD}/cmake/riscv64-spacemit-linux-gnu-gcc.cmake + + cmake --build build --config Release -j $(nproc) diff -pruN 5882+dfsg-2/.github/workflows/build-riscv-native.yml 6641+dfsg-2/.github/workflows/build-riscv-native.yml --- 5882+dfsg-2/.github/workflows/build-riscv-native.yml 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/build-riscv-native.yml 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,120 @@ +name: Build on RISCV Linux Machine by Cloud-V +on: + pull_request: + workflow_dispatch: + workflow_call: + +jobs: + debian-13-riscv64-native: # Bianbu 2.2 + runs-on: [self-hosted, RISCV64] + + steps: + - name: Install prerequisites + run: | + sudo apt-get update || true + sudo apt-get install -y libatomic1 + - uses: actions/checkout@v4 + - name: Setup Riscv + run: | + sudo apt-get update || true + sudo apt-get install -y --no-install-recommends \ + build-essential \ + gcc-14-riscv64-linux-gnu \ + g++-14-riscv64-linux-gnu \ + ccache \ + cmake + + - name: Setup ccache + run: | + mkdir -p $HOME/.ccache + ccache -M 5G -d $HOME/.ccache + export CCACHE_LOGFILE=/home/runneruser/ccache_debug/ccache.log + export CCACHE_DEBUGDIR="/home/runneruser/ccache_debug" + echo "$GITHUB_WORKSPACE" + echo "CCACHE_LOGFILE=$CCACHE_LOGFILE" >> $GITHUB_ENV + echo "CCACHE_DEBUGDIR=$CCACHE_DEBUGDIR" >> $GITHUB_ENV + echo "CCACHE_BASEDIR=$GITHUB_WORKSPACE" >> $GITHUB_ENV + echo "CCACHE_DIR=$HOME/.ccache" >> $GITHUB_ENV + + - name: Build + run: | + cmake -B build \ + -DLLAMA_CURL=OFF \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_OPENMP=OFF \ + -DLLAMA_BUILD_EXAMPLES=ON \ + -DLLAMA_BUILD_TOOLS=ON \ + -DLLAMA_BUILD_TESTS=OFF \ + -DCMAKE_SYSTEM_NAME=Linux \ + -DCMAKE_SYSTEM_PROCESSOR=riscv64 \ + -DCMAKE_C_COMPILER=riscv64-linux-gnu-gcc-14 \ + -DCMAKE_CXX_COMPILER=riscv64-linux-gnu-g++-14 \ + -DCMAKE_C_COMPILER_LAUNCHER=ccache \ + -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \ + -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + -DCMAKE_FIND_ROOT_PATH=/usr/lib/riscv64-linux-gnu \ + -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ + -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ + -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH + + cmake --build build --config Release -j $(nproc) + + # debian-13-riscv64-spacemit-ime-native: # Bianbu 2.2 + # runs-on: [self-hosted, RISCV64] + + # steps: + # - name: Install prerequisites + # run: | + # sudo apt-get update || true + # sudo apt-get install -y libatomic1 + # - uses: actions/checkout@v4 + # - name: Setup Riscv + # run: | + # sudo apt-get update || true + # sudo apt-get install -y --no-install-recommends \ + # build-essential \ + # gcc-14-riscv64-linux-gnu \ + # g++-14-riscv64-linux-gnu \ + # ccache \ + # cmake + # sudo apt-get upgrade binutils -y + + # - name: Setup ccache + # run: | + # mkdir -p $HOME/.ccache + # ccache -M 5G -d $HOME/.ccache + # export CCACHE_LOGFILE=/home/runneruser/ccache_debug/ccache.log + # export CCACHE_DEBUGDIR="/home/runneruser/ccache_debug" + # echo "$GITHUB_WORKSPACE" + # echo "CCACHE_LOGFILE=$CCACHE_LOGFILE" >> $GITHUB_ENV + # echo "CCACHE_DEBUGDIR=$CCACHE_DEBUGDIR" >> $GITHUB_ENV + # echo "CCACHE_BASEDIR=$GITHUB_WORKSPACE" >> $GITHUB_ENV + # echo "CCACHE_DIR=$HOME/.ccache" >> $GITHUB_ENV + + # - name: Build + # run: | + # cmake -B build \ + # -DLLAMA_CURL=OFF \ + # -DCMAKE_BUILD_TYPE=Release \ + # -DGGML_OPENMP=OFF \ + # -DLLAMA_BUILD_EXAMPLES=ON \ + # -DLLAMA_BUILD_TOOLS=ON \ + # -DLLAMA_BUILD_TESTS=OFF \ + # -DCMAKE_SYSTEM_NAME=Linux \ + # -DCMAKE_SYSTEM_PROCESSOR=riscv64 \ + # -DCMAKE_C_COMPILER=riscv64-linux-gnu-gcc-14 \ + # -DCMAKE_CXX_COMPILER=riscv64-linux-gnu-g++-14 \ + # -DCMAKE_C_COMPILER_LAUNCHER=ccache \ + # -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \ + # -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + # -DCMAKE_FIND_ROOT_PATH=/usr/lib/riscv64-linux-gnu \ + # -DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \ + # -DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \ + # -DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=BOTH \ + # -DGGML_RVV=ON \ + # -DGGML_RV_ZFH=ON \ + # -DGGML_RV_ZICBOP=ON \ + # -DGGML_CPU_RISCV64_SPACEMIT=ON \ + # -DRISCV64_SPACEMIT_IME_SPEC=RISCV64_SPACEMIT_IME1 + + # cmake --build build --config Release -j $(nproc) diff -pruN 5882+dfsg-2/.github/workflows/build.yml 6641+dfsg-2/.github/workflows/build.yml --- 5882+dfsg-2/.github/workflows/build.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/build.yml 2025-09-30 07:36:33.000000000 +0000 @@ -56,7 +56,7 @@ env: jobs: macOS-latest-cmake-arm64: - runs-on: macos-14 + runs-on: macos-latest steps: - name: Clone @@ -64,7 +64,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-arm64 evict-old-files: 1d @@ -88,6 +88,7 @@ jobs: -DGGML_METAL_SHADER_DEBUG=ON \ -DGGML_RPC=ON cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) + leaks -atExit -- ./build/bin/test-thread-safety -hf ggml-org/gemma-3-270m-qat-GGUF -ngl 99 -p "$(printf 'hello %.0s' {1..128})" -n 16 -c 512 -ub 32 -np 2 -t 2 -lv 1 - name: Test id: cmake_test @@ -104,7 +105,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-x64 evict-old-files: 1d @@ -126,7 +127,55 @@ jobs: -DCMAKE_BUILD_RPATH="@loader_path" \ -DLLAMA_FATAL_WARNINGS=ON \ -DGGML_METAL=OFF \ - -DGGML_RPC=ON + -DGGML_RPC=ON \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=13.3 + cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) + + - name: Test + id: cmake_test + run: | + cd build + ctest -L main --verbose --timeout 900 + + macOS-latest-cmake-arm64-webgpu: + runs-on: macos-latest + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: macOS-latest-cmake-arm64-webgpu + evict-old-files: 1d + + - name: Dependencies + id: depends + continue-on-error: true + run: | + brew update + brew install curl + + - name: Dawn Dependency + id: dawn-depends + run: | + DAWN_VERSION="v1.0.0" + DAWN_OWNER="reeselevine" + DAWN_REPO="dawn" + DAWN_ASSET_NAME="Dawn-a1a6b45cced25a3b7f4fb491e0ae70796cc7f22b-macos-latest-Release.tar.gz" + echo "Fetching release asset from https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + curl -L -o artifact.tar.gz \ + "https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + mkdir dawn + tar -xvf artifact.tar.gz -C dawn --strip-components=1 + + - name: Build + id: cmake_build + run: | + export CMAKE_PREFIX_PATH=dawn + cmake -B build -DGGML_WEBGPU=ON -DGGML_METAL=OFF -DGGML_BLAS=OFF cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) - name: Test @@ -143,6 +192,10 @@ jobs: os: ubuntu-22.04 - build: 'arm64' os: ubuntu-22.04-arm + - build: 's390x' + os: ubuntu-24.04-s390x + - build: 'ppc64le' + os: ubuntu-24.04-ppc64le runs-on: ${{ matrix.os }} @@ -152,16 +205,33 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-cpu-cmake evict-old-files: 1d - - name: Dependencies - id: depends + - name: Build Dependencies + id: build_depends run: | sudo apt-get update - sudo apt-get install build-essential libcurl4-openssl-dev + sudo apt-get install -y --no-install-recommends \ + python3 python3-pip python3-dev \ + libjpeg-dev build-essential libcurl4-openssl-dev \ + git-lfs + + - name: Python Dependencies + id: python_depends + run: | + python3 -m pip install --upgrade pip + pip3 install ./gguf-py + + - name: Swap Endianness + id: endianness + if: ${{ matrix.build == 's390x' }} + run: | + for f in models/*.gguf; do + echo YES | python3 gguf-py/gguf/scripts/gguf_convert_endian.py $f big + done - name: Build id: cmake_build @@ -179,6 +249,7 @@ jobs: - name: Test llama2c conversion id: llama2c_test + if: ${{ matrix.build != 's390x' }} run: | cd build echo "Fetch tokenizer" @@ -188,6 +259,15 @@ jobs: ./bin/llama-convert-llama2c-to-ggml --copy-vocab-from-model ./tok512.bin --llama2c-model stories260K.bin --llama2c-output-model stories260K.gguf ./bin/llama-cli -m stories260K.gguf -p "One day, Lily met a Shoggoth" -n 500 -c 256 + - name: Test llama2c (s390x) + id: llama2c_test_s390x + if: ${{ matrix.build == 's390x' }} + run: | + cd build + echo "Fetch llama2c big-endian model" + wget https://huggingface.co/ggml-org/models/resolve/main/tinyllamas/stories260K-be.gguf + ./bin/llama-cli -m stories260K-be.gguf -p "One day, Lily met a Shoggoth" -n 500 -c 256 + ubuntu-latest-cmake-sanitizer: runs-on: ubuntu-latest @@ -204,7 +284,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-latest-cmake-sanitizer-${{ matrix.sanitizer }} evict-old-files: 1d @@ -283,7 +363,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-latest-cmake-rpc evict-old-files: 1d @@ -316,7 +396,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-vulkan evict-old-files: 1d @@ -344,9 +424,59 @@ jobs: # This is using llvmpipe and runs slower than other backends ctest -L main --verbose --timeout 4200 + ubuntu-22-cmake-webgpu: + runs-on: ubuntu-22.04 + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ubuntu-22-cmake-webgpu + evict-old-files: 1d + + - name: Vulkan SDK Dependencies + id: vulkan-depends + run: | + wget -qO - https://packages.lunarg.com/lunarg-signing-key-pub.asc | sudo apt-key add - + sudo wget -qO /etc/apt/sources.list.d/lunarg-vulkan-jammy.list https://packages.lunarg.com/vulkan/lunarg-vulkan-jammy.list + sudo apt-get update -y + sudo apt-get install -y build-essential mesa-vulkan-drivers vulkan-sdk libcurl4-openssl-dev + + - name: Dawn Dependency + id: dawn-depends + run: | + sudo apt-get install -y libxrandr-dev libxinerama-dev libxcursor-dev mesa-common-dev libx11-xcb-dev libxi-dev + DAWN_VERSION="v1.0.0" + DAWN_OWNER="reeselevine" + DAWN_REPO="dawn" + DAWN_ASSET_NAME="Dawn-a1a6b45cced25a3b7f4fb491e0ae70796cc7f22b-ubuntu-latest-Release.tar.gz" + echo "Fetching release asset from https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + curl -L -o artifact.tar.gz \ + "https://github.com/${DAWN_OWNER}/${DAWN_REPO}/releases/download/${DAWN_VERSION}/${DAWN_ASSET_NAME}" + mkdir dawn + tar -xvf artifact.tar.gz -C dawn --strip-components=1 + + - name: Build + id: cmake_build + run: | + export Dawn_DIR=dawn/lib64/cmake/Dawn + cmake -B build -DGGML_WEBGPU=ON + cmake --build build --config Release -j $(nproc) + + - name: Test + id: cmake_test + run: | + cd build + # This is using llvmpipe and runs slower than other backends + ctest -L main --verbose --timeout 3600 + ubuntu-22-cmake-hip: runs-on: ubuntu-22.04 - container: rocm/dev-ubuntu-22.04:6.0.2 + container: rocm/dev-ubuntu-22.04:6.1.2 steps: - name: Clone @@ -360,7 +490,7 @@ jobs: sudo apt-get install -y build-essential git cmake rocblas-dev hipblas-dev libcurl4-openssl-dev - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-hip evict-old-files: 1d @@ -374,19 +504,9 @@ jobs: -DGGML_HIP=ON cmake --build build --config Release -j $(nproc) - - name: Build with legacy HIP support - id: cmake_build_legacy_hip - run: | - cmake -B build2 -S . \ - -DCMAKE_C_COMPILER=hipcc \ - -DCMAKE_CXX_COMPILER=hipcc \ - -DGGML_HIP_ROCWMMA_FATTN=ON \ - -DGGML_HIP=ON - cmake --build build2 --config Release -j $(nproc) - ubuntu-22-cmake-musa: runs-on: ubuntu-22.04 - container: mthreads/musa:rc4.0.1-mudnn-devel-ubuntu22.04 + container: mthreads/musa:rc4.3.0-devel-ubuntu22.04-amd64 steps: - name: Clone @@ -400,7 +520,7 @@ jobs: apt-get install -y build-essential git cmake libcurl4-openssl-dev - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-musa evict-old-files: 1d @@ -445,7 +565,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-sycl evict-old-files: 1d @@ -493,7 +613,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-sycl-fp16 evict-old-files: 1d @@ -524,7 +644,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-ios evict-old-files: 1d @@ -561,7 +681,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-tvos evict-old-files: 1d @@ -622,6 +742,7 @@ jobs: macOS-latest-swift: runs-on: macos-latest + needs: ios-xcode-build strategy: matrix: @@ -633,11 +754,17 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-swift evict-old-files: 1d + - name: Download xcframework artifact + uses: actions/download-artifact@v4 + with: + name: llama-xcframework + path: build-apple/llama.xcframework/ + - name: Dependencies id: depends continue-on-error: true @@ -659,11 +786,6 @@ jobs: -DCMAKE_OSX_ARCHITECTURES="arm64;x86_64" cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) - - name: xcodebuild for swift package - id: xcodebuild - run: | - ./build-xcframework.sh - windows-msys2: runs-on: windows-2025 @@ -679,7 +801,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-msys2 variant: ccache @@ -747,7 +869,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-latest-cmake-${{ matrix.build }} variant: ccache @@ -861,7 +983,7 @@ jobs: apt install -y cmake build-essential ninja-build libgomp1 git libcurl4-openssl-dev - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-latest-cmake-cuda evict-old-files: 1d @@ -890,7 +1012,7 @@ jobs: uses: actions/checkout@v4 - name: Install ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-cuda-${{ matrix.cuda }} variant: ccache @@ -946,7 +1068,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-latest-cmake-sycl variant: ccache @@ -963,9 +1085,13 @@ jobs: run: examples/sycl/win-build-sycl.bat windows-latest-cmake-hip: - if: ${{ github.event.inputs.create_release != 'true' }} runs-on: windows-2022 + env: + # The ROCm version must correspond to the version used in the HIP SDK. + ROCM_VERSION: "6.4.2" + HIPSDK_INSTALLER_VERSION: "25.Q3" + steps: - name: Clone id: checkout @@ -974,25 +1100,49 @@ jobs: - name: Clone rocWMMA repository id: clone_rocwmma run: | - git clone https://github.com/rocm/rocwmma --branch rocm-6.2.4 --depth 1 + git clone https://github.com/rocm/rocwmma --branch rocm-${{ env.ROCM_VERSION }} --depth 1 - - name: Install + - name: Cache ROCm Installation + id: cache-rocm + uses: actions/cache@v4 + with: + path: C:\Program Files\AMD\ROCm + key: rocm-${{ env.HIPSDK_INSTALLER_VERSION }}-${{ runner.os }} + + - name: Install ROCm + if: steps.cache-rocm.outputs.cache-hit != 'true' id: depends run: | $ErrorActionPreference = "Stop" write-host "Downloading AMD HIP SDK Installer" - Invoke-WebRequest -Uri "https://download.amd.com/developer/eula/rocm-hub/AMD-Software-PRO-Edition-24.Q3-WinSvr2022-For-HIP.exe" -OutFile "${env:RUNNER_TEMP}\rocm-install.exe" + Invoke-WebRequest -Uri "https://download.amd.com/developer/eula/rocm-hub/AMD-Software-PRO-Edition-${{ env.HIPSDK_INSTALLER_VERSION }}-WinSvr2022-For-HIP.exe" -OutFile "${env:RUNNER_TEMP}\rocm-install.exe" write-host "Installing AMD HIP SDK" - Start-Process "${env:RUNNER_TEMP}\rocm-install.exe" -ArgumentList '-install' -NoNewWindow -Wait + $proc = Start-Process "${env:RUNNER_TEMP}\rocm-install.exe" -ArgumentList '-install' -NoNewWindow -PassThru + $completed = $proc.WaitForExit(600000) + if (-not $completed) { + Write-Error "ROCm installation timed out after 10 minutes. Killing the process" + $proc.Kill() + exit 1 + } + if ($proc.ExitCode -ne 0) { + Write-Error "ROCm installation failed with exit code $($proc.ExitCode)" + exit 1 + } write-host "Completed AMD HIP SDK installation" - name: Verify ROCm id: verify run: | - & 'C:\Program Files\AMD\ROCm\*\bin\clang.exe' --version + # Find and test ROCm installation + $clangPath = Get-ChildItem 'C:\Program Files\AMD\ROCm\*\bin\clang.exe' | Select-Object -First 1 + if (-not $clangPath) { + Write-Error "ROCm installation not found" + exit 1 + } + & $clangPath.FullName --version - name: Install ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ${{ github.job }} evict-old-files: 1d @@ -1026,6 +1176,11 @@ jobs: - name: Checkout code uses: actions/checkout@v4 + - name: Setup Xcode + uses: maxim-lobanov/setup-xcode@v1 + with: + xcode-version: latest-stable + - name: Build id: cmake_build run: | @@ -1048,8 +1203,17 @@ jobs: run: | ./build-xcframework.sh + - name: Upload xcframework artifact + uses: actions/upload-artifact@v4 + with: + name: llama-xcframework + path: build-apple/llama.xcframework/ + retention-days: 1 + - name: Build Xcode project - run: xcodebuild -project examples/llama.swiftui/llama.swiftui.xcodeproj -scheme llama.swiftui -sdk iphoneos CODE_SIGNING_REQUIRED=NO CODE_SIGN_IDENTITY= -destination 'generic/platform=iOS' FRAMEWORK_FOLDER_PATH=./build-ios build + run: | + xcodebuild -downloadPlatform iOS + xcodebuild -project examples/llama.swiftui/llama.swiftui.xcodeproj -scheme llama.swiftui -sdk iphoneos CODE_SIGNING_REQUIRED=NO CODE_SIGN_IDENTITY= -destination 'generic/platform=iOS' FRAMEWORK_FOLDER_PATH=./build-ios build android-build: runs-on: ubuntu-latest @@ -1059,7 +1223,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: android-build evict-old-files: 1d @@ -1114,3 +1278,212 @@ jobs: -DGGML_CANN=on \ -DSOC_TYPE=${{ matrix.device }} cmake --build build -j $(nproc) + +# TODO: simplify the following workflows using a matrix +# TODO: run lighter CI on PRs and the full CI only on master (if needed) + ggml-ci-x64-cpu-low-perf: + runs-on: ubuntu-22.04 + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ggml-ci-x64-cpu-low-perf + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Test + id: ggml-ci + run: | + LLAMA_ARG_THREADS=$(nproc) GG_BUILD_LOW_PERF=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt + + ggml-ci-arm64-cpu-low-perf: + runs-on: ubuntu-22.04-arm + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ggml-ci-arm64-cpu-low-perf + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Test + id: ggml-ci + run: | + LLAMA_ARG_THREADS=$(nproc) GG_BUILD_LOW_PERF=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt + + ggml-ci-x64-cpu-high-perf: + runs-on: ubuntu-22.04 + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ggml-ci-x64-cpu-high-perf + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Test + id: ggml-ci + run: | + LLAMA_ARG_THREADS=$(nproc) bash ./ci/run.sh ./tmp/results ./tmp/mnt + + ggml-ci-arm64-cpu-high-perf: + runs-on: ubuntu-22.04-arm + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ggml-ci-arm64-cpu-high-perf + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Test + id: ggml-ci + run: | + LLAMA_ARG_THREADS=$(nproc) GG_BUILD_NO_SVE=1 GG_BUILD_NO_BF16=1 GG_BUILD_EXTRA_TESTS_0=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt + + ggml-ci-arm64-cpu-high-perf-sve: + runs-on: ubuntu-22.04-arm + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: ggml-ci-arm64-cpu-high-perf-sve + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + + - name: Test + id: ggml-ci + run: | + LLAMA_ARG_THREADS=$(nproc) GG_BUILD_NO_BF16=1 GG_BUILD_EXTRA_TESTS_0=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt + + ggml-ci-x64-nvidia-cuda: + runs-on: [self-hosted, Linux, X64, NVIDIA] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + nvidia-smi + GG_BUILD_CUDA=1 bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp + + ggml-ci-x64-nvidia-vulkan-cm: + runs-on: [self-hosted, Linux, X64, NVIDIA] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + vulkaninfo --summary + GG_BUILD_VULKAN=1 GGML_VK_DISABLE_COOPMAT2=1 bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp + + ggml-ci-x64-nvidia-vulkan-cm2: + runs-on: [self-hosted, Linux, X64, NVIDIA, COOPMAT2] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + vulkaninfo --summary + GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp + + ggml-ci-x64-cpu-amx: + runs-on: [self-hosted, Linux, X64, CPU, AMX] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + bash ./ci/run.sh ~/results/llama.cpp /mnt/llama.cpp + + ggml-ci-mac-metal: + runs-on: [self-hosted, macOS, ARM64] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + GG_BUILD_METAL=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp + + ggml-ci-mac-vulkan: + runs-on: [self-hosted, macOS, ARM64] + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + + - name: Test + id: ggml-ci + run: | + vulkaninfo --summary + GG_BUILD_VULKAN=1 bash ./ci/run.sh ~/results/llama.cpp ~/mnt/llama.cpp diff -pruN 5882+dfsg-2/.github/workflows/close-issue.yml 6641+dfsg-2/.github/workflows/close-issue.yml --- 5882+dfsg-2/.github/workflows/close-issue.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/close-issue.yml 2025-09-30 07:36:33.000000000 +0000 @@ -17,7 +17,7 @@ jobs: steps: - uses: actions/stale@v5 with: - exempt-issue-labels: "refactor,help wanted,good first issue,research,bug,roadmap" + exempt-issue-labels: "refactoring,help wanted,good first issue,research 🔬,bug,roadmap" days-before-issue-stale: 30 days-before-issue-close: 14 stale-issue-label: "stale" diff -pruN 5882+dfsg-2/.github/workflows/copilot-setup-steps.yml 6641+dfsg-2/.github/workflows/copilot-setup-steps.yml --- 5882+dfsg-2/.github/workflows/copilot-setup-steps.yml 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/copilot-setup-steps.yml 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,57 @@ +name: "Copilot Setup Steps" + +# Automatically run the setup steps when they are changed to allow for easy validation, and +# allow manual testing through the repository's "Actions" tab +on: + workflow_dispatch: + push: + paths: + - .github/workflows/copilot-setup-steps.yml + pull_request: + paths: + - .github/workflows/copilot-setup-steps.yml + +jobs: + # The job MUST be called `copilot-setup-steps` or it will not be picked up by Copilot. + copilot-setup-steps: + runs-on: ubuntu-latest + + # Set the permissions to the lowest permissions possible needed for your steps. + # Copilot will be given its own token for its operations. + permissions: + # If you want to clone the repository as part of your setup steps, for example to install dependencies, you'll need the `contents: read` permission. If you don't clone the repository in your setup steps, Copilot will do this for you automatically after the steps complete. + contents: read + + # You can define any steps you want, and they will run before the agent starts. + # If you do not check out your code, Copilot will do this for you. + steps: + - name: Checkout code + uses: actions/checkout@v4 + + - name: ccache + uses: ggml-org/ccache-action@v1.2.16 + with: + key: copilot-setup-steps + evict-old-files: 1d + + - name: Dependencies + id: depends + run: | + sudo apt-get update + sudo apt-get install build-essential libcurl4-openssl-dev + # Install git-clang-format script for formatting only changed code + wget -O /tmp/git-clang-format https://raw.githubusercontent.com/llvm/llvm-project/release/18.x/clang/tools/clang-format/git-clang-format + sudo cp /tmp/git-clang-format /usr/local/bin/git-clang-format + sudo chmod +x /usr/local/bin/git-clang-format + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Install Python dependencies + run: | + python3 -m venv .venv + .venv/bin/activate + pip install -r requirements/requirements-all.txt -r tools/server/tests/requirements.txt + pip install flake8 pyright pre-commit diff -pruN 5882+dfsg-2/.github/workflows/docker.yml 6641+dfsg-2/.github/workflows/docker.yml --- 5882+dfsg-2/.github/workflows/docker.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/docker.yml 2025-09-30 07:36:33.000000000 +0000 @@ -28,7 +28,7 @@ jobs: push_to_registry: name: Push Docker image to Docker Hub - runs-on: ubuntu-22.04 + runs-on: ${{ matrix.config.runs_on }} env: COMMIT_SHA: ${{ github.sha }} strategy: @@ -39,11 +39,12 @@ jobs: # Note: the arm64 images are failing, which prevents the amd64 images from being built # https://github.com/ggml-org/llama.cpp/issues/11888 #- { tag: "cpu", dockerfile: ".devops/cpu.Dockerfile", platforms: "linux/amd64,linux/arm64", full: true, light: true, server: true, free_disk_space: false } - - { tag: "cpu", dockerfile: ".devops/cpu.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false } - - { tag: "cuda", dockerfile: ".devops/cuda.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false } - - { tag: "musa", dockerfile: ".devops/musa.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: true } - - { tag: "intel", dockerfile: ".devops/intel.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: true } - - { tag: "vulkan", dockerfile: ".devops/vulkan.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false } + - { tag: "cpu", dockerfile: ".devops/cpu.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false, runs_on: "ubuntu-22.04" } + - { tag: "cuda", dockerfile: ".devops/cuda.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false, runs_on: "ubuntu-22.04" } + - { tag: "musa", dockerfile: ".devops/musa.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: true, runs_on: "ubuntu-22.04" } + - { tag: "intel", dockerfile: ".devops/intel.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: true, runs_on: "ubuntu-22.04" } + - { tag: "vulkan", dockerfile: ".devops/vulkan.Dockerfile", platforms: "linux/amd64", full: true, light: true, server: true, free_disk_space: false, runs_on: "ubuntu-22.04" } + - { tag: "s390x", dockerfile: ".devops/s390x.Dockerfile", platforms: "linux/s390x", full: true, light: true, server: true, free_disk_space: false, runs_on: "ubuntu-22.04-s390x" } # Note: the rocm images are failing due to a compiler error and are disabled until this is fixed to allow the workflow to complete #- {tag: "rocm", dockerfile: ".devops/rocm.Dockerfile", platforms: "linux/amd64,linux/arm64", full: true, light: true, server: true, free_disk_space: true } steps: @@ -53,6 +54,7 @@ jobs: fetch-depth: 0 # preserve git history, so we can determine the build number - name: Set up QEMU + if: ${{ matrix.config.tag != 's390x' }} uses: docker/setup-qemu-action@v3 with: image: tonistiigi/binfmt:qemu-v7.0.0-28 @@ -67,22 +69,19 @@ jobs: username: ${{ github.repository_owner }} password: ${{ secrets.GITHUB_TOKEN }} - - name: Determine tag name + - name: Determine source tag name + id: srctag + uses: ./.github/actions/get-tag-name + env: + BRANCH_NAME: ${{ github.head_ref || github.ref_name }} + + - name: Determine image tag name id: tag shell: bash run: | - BUILD_NUMBER="$(git rev-list --count HEAD)" - SHORT_HASH="$(git rev-parse --short=7 HEAD)" REPO_OWNER="${GITHUB_REPOSITORY_OWNER@L}" # to lower case REPO_NAME="${{ github.event.repository.name }}" - # determine tag name postfix (build number, commit hash) - if [[ "${{ env.GITHUB_BRANCH_NAME }}" == "master" ]]; then - TAG_POSTFIX="-b${BUILD_NUMBER}" - else - SAFE_NAME=$(echo "${{ env.GITHUB_BRANCH_NAME }}" | tr '/' '-') - TAG_POSTFIX="-${SAFE_NAME}-${SHORT_HASH}" - fi # list all tags possible if [[ "${{ matrix.config.tag }}" == "cpu" ]]; then TYPE="" @@ -90,9 +89,9 @@ jobs: TYPE="-${{ matrix.config.tag }}" fi PREFIX="ghcr.io/${REPO_OWNER}/${REPO_NAME}:" - FULLTAGS="${PREFIX}full${TYPE},${PREFIX}full${TYPE}${TAG_POSTFIX}" - LIGHTTAGS="${PREFIX}light${TYPE},${PREFIX}light${TYPE}${TAG_POSTFIX}" - SERVERTAGS="${PREFIX}server${TYPE},${PREFIX}server${TYPE}${TAG_POSTFIX}" + FULLTAGS="${PREFIX}full${TYPE},${PREFIX}full${TYPE}-${{ steps.srctag.outputs.name }}" + LIGHTTAGS="${PREFIX}light${TYPE},${PREFIX}light${TYPE}-${{ steps.srctag.outputs.name }}" + SERVERTAGS="${PREFIX}server${TYPE},${PREFIX}server${TYPE}-${{ steps.srctag.outputs.name }}" echo "full_output_tags=$FULLTAGS" >> $GITHUB_OUTPUT echo "light_output_tags=$LIGHTTAGS" >> $GITHUB_OUTPUT echo "server_output_tags=$SERVERTAGS" >> $GITHUB_OUTPUT @@ -100,7 +99,6 @@ jobs: echo "light_output_tags=$LIGHTTAGS" # print out for debugging echo "server_output_tags=$SERVERTAGS" # print out for debugging env: - GITHUB_BRANCH_NAME: ${{ github.head_ref || github.ref_name }} GITHUB_REPOSITORY_OWNER: '${{ github.repository_owner }}' - name: Free Disk Space (Ubuntu) @@ -176,3 +174,29 @@ jobs: # return to this if the experimental github cache is having issues #cache-to: type=local,dest=/tmp/.buildx-cache #cache-from: type=local,src=/tmp/.buildx-cache + + create_tag: + name: Create and push git tag + runs-on: ubuntu-22.04 + permissions: + contents: write + + steps: + - name: Clone + id: checkout + uses: actions/checkout@v4 + with: + fetch-depth: 0 + + - name: Determine source tag name + id: srctag + uses: ./.github/actions/get-tag-name + env: + BRANCH_NAME: ${{ github.head_ref || github.ref_name }} + + - name: Create and push git tag + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + run: | + git tag ${{ steps.srctag.outputs.name }} || exit 0 + git push origin ${{ steps.srctag.outputs.name }} || exit 0 diff -pruN 5882+dfsg-2/.github/workflows/pre-tokenizer-hashes.yml 6641+dfsg-2/.github/workflows/pre-tokenizer-hashes.yml --- 5882+dfsg-2/.github/workflows/pre-tokenizer-hashes.yml 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/pre-tokenizer-hashes.yml 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,45 @@ +name: Check Pre-Tokenizer Hashes + +on: + push: + paths: + - 'convert_hf_to_gguf.py' + - 'convert_hf_to_gguf_update.py' + pull_request: + paths: + - 'convert_hf_to_gguf.py' + - 'convert_hf_to_gguf_update.py' + +jobs: + pre-tokenizer-hashes: + runs-on: ubuntu-latest + + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Install Python dependencies + run: | + python3 -m venv .venv + .venv/bin/pip install -r requirements/requirements-convert_hf_to_gguf_update.txt + + - name: Update pre-tokenizer hashes + run: | + cp convert_hf_to_gguf.py /tmp + .venv/bin/python convert_hf_to_gguf_update.py --check-missing + + - name: Check if committed pre-tokenizer hashes matches generated version + run: | + if ! diff -q convert_hf_to_gguf.py /tmp/convert_hf_to_gguf.py; then + echo "Model pre-tokenizer hashes (in convert_hf_to_gguf.py) do not match generated hashes (from convert_hf_to_gguf_update.py)." + echo "To fix: run ./convert_hf_to_gguf_update.py and commit the updated convert_hf_to_gguf.py along with your changes" + echo "Differences found:" + diff convert_hf_to_gguf.py /tmp/convert_hf_to_gguf.py || true + exit 1 + fi + echo "Model pre-tokenizer hashes are up to date." diff -pruN 5882+dfsg-2/.github/workflows/release.yml 6641+dfsg-2/.github/workflows/release.yml --- 5882+dfsg-2/.github/workflows/release.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/release.yml 2025-09-30 07:36:33.000000000 +0000 @@ -32,7 +32,7 @@ jobs: fetch-depth: 0 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-arm64 evict-old-files: 1d @@ -85,7 +85,7 @@ jobs: fetch-depth: 0 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: macOS-latest-cmake-x64 evict-old-files: 1d @@ -108,7 +108,8 @@ jobs: -DCMAKE_BUILD_WITH_INSTALL_RPATH=ON \ -DLLAMA_FATAL_WARNINGS=ON \ -DGGML_METAL=OFF \ - -DGGML_RPC=ON + -DGGML_RPC=ON \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=13.3 cmake --build build --config Release -j $(sysctl -n hw.logicalcpu) - name: Determine tag name @@ -147,7 +148,7 @@ jobs: fetch-depth: 0 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-cpu-cmake evict-old-files: 1d @@ -198,7 +199,7 @@ jobs: fetch-depth: 0 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: ubuntu-22-cmake-vulkan evict-old-files: 1d @@ -256,7 +257,7 @@ jobs: fetch-depth: 0 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-latest-cmake-cpu-${{ matrix.arch }} variant: ccache @@ -328,7 +329,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-latest-cmake-${{ matrix.backend }}-${{ matrix.arch }} variant: ccache @@ -398,7 +399,7 @@ jobs: uses: actions/checkout@v4 - name: Install ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-cuda-${{ matrix.cuda }} variant: ccache @@ -471,7 +472,7 @@ jobs: uses: actions/checkout@v4 - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: key: windows-latest-cmake-sycl variant: ccache @@ -528,11 +529,14 @@ jobs: windows-hip: runs-on: windows-2022 + env: + HIPSDK_INSTALLER_VERSION: "25.Q3" + strategy: matrix: include: - name: "radeon" - gpu_targets: "gfx1100;gfx1101;gfx1102;gfx1030;gfx1031;gfx1032" + gpu_targets: "gfx1151;gfx1200;gfx1201;gfx1100;gfx1101;gfx1102;gfx1030;gfx1031;gfx1032" steps: - name: Clone @@ -542,28 +546,52 @@ jobs: - name: Clone rocWMMA repository id: clone_rocwmma run: | - git clone https://github.com/rocm/rocwmma --branch rocm-6.2.4 --depth 1 + git clone https://github.com/rocm/rocwmma --branch develop --depth 1 + + - name: Cache ROCm Installation + id: cache-rocm + uses: actions/cache@v4 + with: + path: C:\Program Files\AMD\ROCm + key: rocm-${{ env.HIPSDK_INSTALLER_VERSION }}-${{ runner.os }} - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.16 + uses: ggml-org/ccache-action@v1.2.16 with: - key: windows-latest-cmake-hip-${{ matrix.name }}-x64 + key: windows-latest-cmake-hip-${{ env.HIPSDK_INSTALLER_VERSION }}-${{ matrix.name }}-x64 evict-old-files: 1d - - name: Install + - name: Install ROCm + if: steps.cache-rocm.outputs.cache-hit != 'true' id: depends run: | $ErrorActionPreference = "Stop" write-host "Downloading AMD HIP SDK Installer" - Invoke-WebRequest -Uri "https://download.amd.com/developer/eula/rocm-hub/AMD-Software-PRO-Edition-24.Q3-WinSvr2022-For-HIP.exe" -OutFile "${env:RUNNER_TEMP}\rocm-install.exe" + Invoke-WebRequest -Uri "https://download.amd.com/developer/eula/rocm-hub/AMD-Software-PRO-Edition-${{ env.HIPSDK_INSTALLER_VERSION }}-WinSvr2022-For-HIP.exe" -OutFile "${env:RUNNER_TEMP}\rocm-install.exe" write-host "Installing AMD HIP SDK" - Start-Process "${env:RUNNER_TEMP}\rocm-install.exe" -ArgumentList '-install' -NoNewWindow -Wait + $proc = Start-Process "${env:RUNNER_TEMP}\rocm-install.exe" -ArgumentList '-install' -NoNewWindow -PassThru + $completed = $proc.WaitForExit(600000) + if (-not $completed) { + Write-Error "ROCm installation timed out after 10 minutes. Killing the process" + $proc.Kill() + exit 1 + } + if ($proc.ExitCode -ne 0) { + Write-Error "ROCm installation failed with exit code $($proc.ExitCode)" + exit 1 + } write-host "Completed AMD HIP SDK installation" - name: Verify ROCm id: verify run: | - & 'C:\Program Files\AMD\ROCm\*\bin\clang.exe' --version + # Find and test ROCm installation + $clangPath = Get-ChildItem 'C:\Program Files\AMD\ROCm\*\bin\clang.exe' | Select-Object -First 1 + if (-not $clangPath) { + Write-Error "ROCm installation not found" + exit 1 + } + & $clangPath.FullName --version - name: Build id: cmake_build @@ -584,9 +612,12 @@ jobs: -DLLAMA_CURL=OFF cmake --build build --target ggml-hip -j ${env:NUMBER_OF_PROCESSORS} md "build\bin\rocblas\library\" + md "build\bin\hipblaslt\library" cp "${env:HIP_PATH}\bin\hipblas.dll" "build\bin\" + cp "${env:HIP_PATH}\bin\hipblaslt.dll" "build\bin\" cp "${env:HIP_PATH}\bin\rocblas.dll" "build\bin\" cp "${env:HIP_PATH}\bin\rocblas\library\*" "build\bin\rocblas\library\" + cp "${env:HIP_PATH}\bin\hipblaslt\library\*" "build\bin\hipblaslt\library\" - name: Pack artifacts id: pack_artifacts @@ -600,7 +631,7 @@ jobs: name: llama-bin-win-hip-${{ matrix.name }}-x64.zip ios-xcode-build: - runs-on: macos-latest + runs-on: macos-15 steps: - name: Checkout code @@ -608,6 +639,10 @@ jobs: with: fetch-depth: 0 + - name: Setup Xcode + run: | + sudo xcode-select -s /Applications/Xcode_16.4.app + - name: Build id: cmake_build run: | diff -pruN 5882+dfsg-2/.github/workflows/server.yml 6641+dfsg-2/.github/workflows/server.yml --- 5882+dfsg-2/.github/workflows/server.yml 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.github/workflows/server.yml 2025-09-30 07:36:33.000000000 +0000 @@ -76,51 +76,206 @@ jobs: run: | pip install -r tools/server/tests/requirements.txt - # Setup nodejs (to be used for verifying bundled index.html) - - uses: actions/setup-node@v4 + webui-setup: + name: WebUI Setup + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v4 with: - node-version: '22.11.0' + fetch-depth: 0 + ref: ${{ github.event.inputs.sha || github.event.pull_request.head.sha || github.sha || github.head_ref || github.ref_name }} - - name: WebUI - Install dependencies - id: webui_lint - run: | - cd tools/server/webui - npm ci + - name: Setup Node.js + uses: actions/setup-node@v4 + with: + node-version: "22" + cache: "npm" + cache-dependency-path: "tools/server/webui/package-lock.json" + + - name: Cache node_modules + uses: actions/cache@v4 + id: cache-node-modules + with: + path: tools/server/webui/node_modules + key: ${{ runner.os }}-node-modules-${{ hashFiles('tools/server/webui/package-lock.json') }} + restore-keys: | + ${{ runner.os }}-node-modules- + + - name: Install dependencies + if: steps.cache-node-modules.outputs.cache-hit != 'true' + run: npm ci + working-directory: tools/server/webui + + webui-check: + needs: webui-setup + name: WebUI Check + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v4 + with: + fetch-depth: 0 + ref: ${{ github.event.inputs.sha || github.event.pull_request.head.sha || github.sha || github.head_ref || github.ref_name }} + + - name: Setup Node.js + uses: actions/setup-node@v4 + with: + node-version: "22" + + - name: Restore node_modules cache + uses: actions/cache@v4 + with: + path: tools/server/webui/node_modules + key: ${{ runner.os }}-node-modules-${{ hashFiles('tools/server/webui/package-lock.json') }} + restore-keys: | + ${{ runner.os }}-node-modules- + + - name: Run type checking + run: npm run check + working-directory: tools/server/webui + + - name: Run linting + run: npm run lint + working-directory: tools/server/webui + + webui-build: + needs: webui-check + name: WebUI Build + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v4 + with: + fetch-depth: 0 + ref: ${{ github.event.inputs.sha || github.event.pull_request.head.sha || github.sha || github.head_ref || github.ref_name }} + + - name: Setup Node.js + uses: actions/setup-node@v4 + with: + node-version: "22" - - name: WebUI - Check code format - id: webui_format + - name: Restore node_modules cache + uses: actions/cache@v4 + with: + path: tools/server/webui/node_modules + key: ${{ runner.os }}-node-modules-${{ hashFiles('tools/server/webui/package-lock.json') }} + restore-keys: | + ${{ runner.os }}-node-modules- + + - name: Build application + run: npm run build + working-directory: tools/server/webui + + webui-tests: + needs: webui-build + name: Run WebUI tests + permissions: + contents: read + + runs-on: ubuntu-latest + + steps: + - name: Checkout code + uses: actions/checkout@v4 + + - name: Setup Node.js + uses: actions/setup-node@v4 + with: + node-version: "22" + + - name: Restore node_modules cache + uses: actions/cache@v4 + with: + path: tools/server/webui/node_modules + key: ${{ runner.os }}-node-modules-${{ hashFiles('tools/server/webui/package-lock.json') }} + restore-keys: | + ${{ runner.os }}-node-modules- + + - name: Install Playwright browsers + run: npx playwright install --with-deps + working-directory: tools/server/webui + + - name: Build Storybook + run: npm run build-storybook + working-directory: tools/server/webui + + - name: Run Client tests + run: npm run test:client + working-directory: tools/server/webui + + - name: Run Server tests + run: npm run test:server + working-directory: tools/server/webui + + - name: Run UI tests + run: npm run test:ui + working-directory: tools/server/webui + + - name: Run E2E tests + run: npm run test:e2e + working-directory: tools/server/webui + + server-build: + needs: [webui-tests] + runs-on: ubuntu-latest + + strategy: + matrix: + sanitizer: [ADDRESS, UNDEFINED] # THREAD is broken + build_type: [RelWithDebInfo] + include: + - build_type: Release + sanitizer: "" + fail-fast: false # While -DLLAMA_SANITIZE_THREAD=ON is broken + + steps: + - name: Dependencies + id: depends run: | - git config --global --add safe.directory $(realpath .) - cd tools/server/webui - git status - - npm run format - git status - modified_files="$(git status -s)" - echo "Modified files: ${modified_files}" - if [ -n "${modified_files}" ]; then - echo "Files do not follow coding style. To fix: npm run format" - echo "${modified_files}" - exit 1 - fi + sudo apt-get update + sudo apt-get -y install \ + build-essential \ + xxd \ + git \ + cmake \ + curl \ + wget \ + language-pack-en \ + libcurl4-openssl-dev + + - name: Clone + id: checkout + uses: actions/checkout@v4 + with: + fetch-depth: 0 + ref: ${{ github.event.inputs.sha || github.event.pull_request.head.sha || github.sha || github.head_ref || github.ref_name }} - - name: Verify bundled index.html - id: verify_server_index_html + - name: Python setup + id: setup_python + uses: actions/setup-python@v5 + with: + python-version: '3.11' + + - name: Tests dependencies + id: test_dependencies run: | - git config --global --add safe.directory $(realpath .) - cd tools/server/webui - git status - - npm run build - git status - modified_files="$(git status -s)" - echo "Modified files: ${modified_files}" - if [ -n "${modified_files}" ]; then - echo "Repository is dirty or server/webui is not built as expected" - echo "Hint: You may need to follow Web UI build guide in server/README.md" - echo "${modified_files}" - exit 1 - fi + pip install -r tools/server/tests/requirements.txt + + - name: Setup Node.js for WebUI + uses: actions/setup-node@v4 + with: + node-version: "22" + cache: "npm" + cache-dependency-path: "tools/server/webui/package-lock.json" + + - name: Install WebUI dependencies + run: npm ci + working-directory: tools/server/webui + + - name: Build WebUI + run: npm run build + working-directory: tools/server/webui - name: Build (no OpenMP) id: cmake_build_no_openmp diff -pruN 5882+dfsg-2/.gitignore 6641+dfsg-2/.gitignore --- 5882+dfsg-2/.gitignore 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/.gitignore 2025-09-30 07:36:33.000000000 +0000 @@ -82,6 +82,7 @@ models/* models-mnt !models/.editorconfig !models/ggml-vocab-*.gguf* +!models/templates # Zig zig-out/ @@ -146,3 +147,8 @@ poetry.toml # Local scripts /run-vim.sh /run-chat.sh +.ccache/ + +# IDE +*.code-workspace +.windsurf/ diff -pruN 5882+dfsg-2/CMakeLists.txt 6641+dfsg-2/CMakeLists.txt --- 5882+dfsg-2/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -12,6 +12,8 @@ if (NOT XCODE AND NOT MSVC AND NOT CMAKE set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release" "MinSizeRel" "RelWithDebInfo") endif() +message("CMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}") + # Add path to modules list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake/") @@ -56,6 +58,12 @@ if (MSVC) add_compile_options("$<$:/bigobj>") endif() +if (CMAKE_SYSTEM_NAME STREQUAL "iOS") + set(LLAMA_TOOLS_INSTALL_DEFAULT OFF) +else() + set(LLAMA_TOOLS_INSTALL_DEFAULT ${LLAMA_STANDALONE}) +endif() + # # option list # @@ -80,9 +88,11 @@ option(LLAMA_BUILD_TESTS "llama: buil option(LLAMA_BUILD_TOOLS "llama: build tools" ${LLAMA_STANDALONE}) option(LLAMA_BUILD_EXAMPLES "llama: build examples" ${LLAMA_STANDALONE}) option(LLAMA_BUILD_SERVER "llama: build server example" ${LLAMA_STANDALONE}) +option(LLAMA_TOOLS_INSTALL "llama: install tools" ${LLAMA_TOOLS_INSTALL_DEFAULT}) # 3rd party libs option(LLAMA_CURL "llama: use libcurl to download model from an URL" ON) +option(LLAMA_OPENSSL "llama: use openssl to support HTTPS" OFF) option(LLAMA_LLGUIDANCE "llama-common: include LLGuidance library for structured output in common utils" OFF) # Required for relocatable CMake package diff -pruN 5882+dfsg-2/CMakePresets.json 6641+dfsg-2/CMakePresets.json --- 5882+dfsg-2/CMakePresets.json 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/CMakePresets.json 2025-09-30 07:36:33.000000000 +0000 @@ -55,6 +55,17 @@ "CMAKE_TOOLCHAIN_FILE": "${sourceDir}/cmake/arm64-apple-clang.cmake" } }, + { + "name": "x64-linux-gcc", "hidden": true, + "cacheVariables": { + "CMAKE_C_COMPILER": "gcc", + "CMAKE_CXX_COMPILER": "g++" + } + }, + { "name": "x64-linux-gcc-debug", "inherits": [ "base", "x64-linux-gcc", "debug" ] }, + { "name": "x64-linux-gcc-release", "inherits": [ "base", "x64-linux-gcc", "release" ] }, + { "name": "x64-linux-gcc-reldbg", "inherits": [ "base", "x64-linux-gcc", "reldbg" ] }, + { "name": "x64-linux-gcc+static-release", "inherits": [ "base", "x64-linux-gcc", "release", "static" ] }, { "name": "arm64-windows-llvm-debug", "inherits": [ "base", "arm64-windows-llvm", "debug" ] }, { "name": "arm64-windows-llvm-release", "inherits": [ "base", "arm64-windows-llvm", "reldbg" ] }, diff -pruN 5882+dfsg-2/CODEOWNERS 6641+dfsg-2/CODEOWNERS --- 5882+dfsg-2/CODEOWNERS 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/CODEOWNERS 2025-09-30 07:36:33.000000000 +0000 @@ -1,11 +1,111 @@ # collaborators can optionally add themselves here to indicate their availability for reviewing related PRs +# multiplie collaborators per item can be specified -/ci/ @ggerganov -/.devops/*.Dockerfile @ngxson -/tools/server/ @ngxson -/ggml/src/ggml-cuda/fattn* @JohannesGaessler -/ggml/src/ggml-cuda/mmq.* @JohannesGaessler -/ggml/src/ggml-cuda/mmv.* @JohannesGaessler -/ggml/src/ggml-cuda/mmvq.* @JohannesGaessler -/ggml/src/ggml-opt.cpp @JohannesGaessler -/ggml/src/gguf.cpp @JohannesGaessler +/.devops/*.Dockerfile @ngxson +/.github/actions/ @slaren +/.github/workflows/ @CISC +/.github/workflows/release.yml @slaren +/.github/workflows/winget.yml @slaren +/ci/ @ggerganov +/cmake/ @ggerganov +/common/CMakeLists.txt @ggerganov +/common/arg.* @ggerganov @ericcurtin +/common/base64.hpp.* @ggerganov +/common/build-info.* @ggerganov +/common/common.* @ggerganov +/common/console.* @ggerganov +/common/llguidance.* @ggerganov +/common/log.* @ggerganov +/common/sampling.* @ggerganov +/common/speculative.* @ggerganov +/convert_*.py @CISC +/examples/batched.swift/ @ggerganov +/examples/batched/ @ggerganov +/examples/convert-llama2c-to-ggml/ @ggerganov +/examples/deprecation-warning/ @ggerganov +/examples/diffusion/ @am17an +/examples/embedding/ @ggerganov +/examples/eval-callback/ @ggerganov +/examples/export-docs/ @ggerganov +/examples/gen-docs/ @ggerganov +/examples/gguf/ @ggerganov +/examples/llama.android/ @ggerganov +/examples/llama.swiftui/ @ggerganov +/examples/llama.vim @ggerganov +/examples/lookahead/ @ggerganov +/examples/lookup/ @JohannesGaessler +/examples/model-conversion/ @danbev +/examples/parallel/ @ggerganov +/examples/passkey/ @ggerganov +/examples/retrieval/ @ggerganov +/examples/save-load-state/ @ggerganov +/examples/simple-chat/ @slaren +/examples/simple/ @slaren +/examples/speculative-simple/ @ggerganov +/examples/speculative/ @ggerganov +/ggml/cmake/ @ggerganov +/ggml/include/ @ggerganov @slaren +/ggml/src/ggml-alloc.c @slaren +/ggml/src/ggml-backend* @slaren +/ggml/src/ggml-blas/ @slaren +/ggml/src/ggml-common.h @ggerganov @slaren +/ggml/src/ggml-cpu/ @ggerganov @slaren +/ggml/src/ggml-cpu/spacemit/ @alex-spacemit +/ggml/src/ggml-cuda/common.cuh @slaren +/ggml/src/ggml-cuda/fattn* @JohannesGaessler +/ggml/src/ggml-cuda/ggml-cuda.cu @slaren +/ggml/src/ggml-cuda/mmf.* @JohannesGaessler +/ggml/src/ggml-cuda/mmq.* @JohannesGaessler +/ggml/src/ggml-cuda/mmvf.* @JohannesGaessler +/ggml/src/ggml-cuda/mmvq.* @JohannesGaessler +/ggml/src/ggml-impl.h @ggerganov @slaren +/ggml/src/ggml-metal/ @ggerganov +/ggml/src/ggml-opencl/ @lhez @max-krasnyansky +/ggml/src/ggml-opt.cpp @JohannesGaessler +/ggml/src/ggml-quants.* @ggerganov +/ggml/src/ggml-rpc/ @rgerganov +/ggml/src/ggml-threading.* @ggerganov @slaren +/ggml/src/ggml-vulkan/ @0cc4m +/ggml/src/ggml-zdnn/ @taronaeo @Andreas-Krebbel @AlekseiNikiforovIBM +/ggml/src/ggml.c @ggerganov @slaren +/ggml/src/ggml.cpp @ggerganov @slaren +/ggml/src/gguf.cpp @JohannesGaessler @Green-Sky +/gguf-py/ @CISC +/media/ @ggerganov +/scripts/gen* @ggerganov +/scripts/get* @ggerganov +/scripts/sync* @ggerganov +/src/ @ggerganov +/src/llama-adapter.* @CISC +/src/llama-arch.* @CISC +/src/llama-chat.* @ngxson +/src/llama-graph.* @CISC +/src/llama-model-loader.* @slaren +/src/llama-model.* @CISC +/src/llama-vocab.* @CISC +/tests/ @ggerganov +/tests/test-backend-ops.cpp @slaren +/tests/test-thread-safety.cpp @slaren +/tools/batched-bench/ @ggerganov +/tools/llama-bench/ @slaren +/tools/main/ @ggerganov +/tools/mtmd/ @ngxson +/tools/perplexity/ @ggerganov +/tools/quantize/ @ggerganov +/tools/rpc/ @rgerganov +/tools/run/ @ericcurtin +/tools/server/* @ngxson @ggerganov @ericcurtin # no subdir +/tools/server/webui/ @allozaur +/tools/tokenize/ @ggerganov +/tools/tts/ @ggerganov +/vendor/ @ggerganov +/.clang-format @slaren +/.clang-tidy @slaren +/AUTHORS @ggerganov +/CMakeLists.txt @ggerganov +/CONTRIBUTING.md @ggerganov +/LICENSE @ggerganov +/README.md @ggerganov +/SECURITY.md @ggerganov +/build-xcframework.sh @danbev +requirements*.txt @CISC diff -pruN 5882+dfsg-2/CONTRIBUTING.md 6641+dfsg-2/CONTRIBUTING.md --- 5882+dfsg-2/CONTRIBUTING.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/CONTRIBUTING.md 2025-09-30 07:36:33.000000000 +0000 @@ -1,4 +1,12 @@ -# Pull requests (for contributors) +# Contributors + +The project differentiates between 3 levels of contributors: + +- Contributors: people who have contributed before (no special privileges) +- Collaborators (Triage): people with significant contributions, who may be responsible for some parts of the code, and are expected to maintain and review contributions for the code they own +- Maintainers: responsible for reviewing and merging PRs, after approval from the code owners + +# Pull requests (for contributors & collaborators) - llama.cpp uses the ggml tensor library for model evaluation. If you are unfamiliar with ggml, consider taking a look at the [examples in the ggml repository](https://github.com/ggml-org/ggml/tree/master/examples/). [simple](https://github.com/ggml-org/ggml/tree/master/examples/simple) shows the bare minimum for using ggml. [gpt-2](https://github.com/ggml-org/ggml/tree/master/examples/gpt-2) has minimal implementations for language model inference using GPT-2. [mnist](https://github.com/ggml-org/ggml/tree/master/examples/mnist) demonstrates how to train and evaluate a simple image classifier - Test your changes: @@ -9,13 +17,17 @@ - Create separate PRs for each feature or fix. Avoid combining unrelated changes in a single PR - Consider allowing write access to your branch for faster reviews, as reviewers can push commits directly - If your PR becomes stale, don't hesitate to ping the maintainers in the comments +- Maintainers will rely on your insights and approval when making a final decision to approve and merge a PR +- Consider adding yourself to [CODEOWNERS](CODEOWNERS) to indicate your availability for reviewing related PRs -# Pull requests (for collaborators) +# Pull requests (for maintainers) - Squash-merge PRs - Use the following format for the squashed commit title: ` : (#)`. For example: `utils : fix typo in utils.py (#1234)` - Optionally pick a `` from here: https://github.com/ggml-org/llama.cpp/wiki/Modules -- Consider adding yourself to [CODEOWNERS](CODEOWNERS) +- Let other maintainers merge their own PRs +- When merging a PR, make sure you have a good understanding of the changes +- Be mindful of maintenance: most of the work going into a feature happens after the PR is merged. If the PR author is not committed to contribute long-term, someone else needs to take responsibility (you) # Coding guidelines @@ -114,6 +126,21 @@ #endif // FOO ``` +# Code maintenance + +- Existing code should have designated collaborators and/or maintainers specified in the [CODEOWNERS](CODEOWNERS) file reponsible for: + - Reviewing and merging related PRs + - Fixing related bugs + - Providing developer guidance/support + +- When adding or modifying a large piece of code: + - If you are a collaborator, make sure to add yourself to [CODEOWNERS](CODEOWNERS) to indicate your availability for reviewing related PRs + - If you are a contributor, find an existing collaborator who is willing to review and maintain your code long-term + - Provide the necessary CI workflow (and hardware) to test your changes (see [ci/README.md](https://github.com/ggml-org/llama.cpp/tree/master/ci)) + +- New code should follow the guidelines (coding, naming, etc.) outlined in this document. Exceptions are allowed in isolated, backend-specific parts of the code that do not interface directly with the `ggml` interfaces. + _(NOTE: for legacy reasons, existing code is not required to follow this guideline)_ + # Documentation - Documentation is a community effort diff -pruN 5882+dfsg-2/Makefile 6641+dfsg-2/Makefile --- 5882+dfsg-2/Makefile 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/Makefile 2025-09-30 07:36:33.000000000 +0000 @@ -1,1608 +1,9 @@ -ifndef LLAMA_MAKEFILE -$(error The Makefile build is deprecated. Use the CMake build instead. For more details, see https://github.com/ggml-org/llama.cpp/blob/master/docs/build.md) -endif +define newline -# Define the default target now so that it is always the first target -BUILD_TARGETS = \ - libllava.a \ - llama-batched \ - llama-batched-bench \ - llama-bench \ - llama-cli \ - llama-convert-llama2c-to-ggml \ - llama-embedding \ - llama-eval-callback \ - llama-export-lora \ - llama-gbnf-validator \ - llama-gguf \ - llama-gguf-hash \ - llama-gguf-split \ - llama-gritlm \ - llama-imatrix \ - llama-infill \ - llama-llava-cli \ - llama-minicpmv-cli\ - llama-qwen2vl-cli\ - llama-lookahead \ - llama-lookup \ - llama-lookup-create \ - llama-lookup-merge \ - llama-lookup-stats \ - llama-parallel \ - llama-passkey \ - llama-perplexity \ - llama-q8dot \ - llama-quantize \ - llama-quantize-stats \ - llama-retrieval \ - llama-save-load-state \ - llama-server \ - llama-simple \ - llama-simple-chat \ - llama-run \ - llama-speculative \ - llama-tokenize \ - llama-vdot \ - llama-cvector-generator \ - llama-gen-docs \ - tests/test-c.o -# Binaries only useful for tests -TEST_TARGETS = \ - tests/test-arg-parser \ - tests/test-autorelease \ - tests/test-backend-ops \ - tests/test-chat \ - tests/test-chat-template \ - tests/test-double-float \ - tests/test-grammar-integration \ - tests/test-grammar-parser \ - tests/test-json-schema-to-grammar \ - tests/test-llama-grammar \ - tests/test-log \ - tests/test-model-load-cancel \ - tests/test-quantize-fns \ - tests/test-quantize-perf \ - tests/test-rope \ - tests/test-sampling \ - tests/test-tokenizer-0 \ - tests/test-tokenizer-1-bpe \ - tests/test-tokenizer-1-spm -# tests/test-opt \ +endef -# Legacy build targets that were renamed in #7809, but should still be removed when the project is cleaned -LEGACY_TARGETS_CLEAN = main quantize quantize-stats perplexity imatrix embedding vdot q8dot convert-llama2c-to-ggml \ - simple batched batched-bench save-load-state server gguf gguf-split eval-callback llama-bench libllava.a llava-cli baby-llama \ - retrieval speculative infill tokenize parallel export-lora lookahead lookup passkey gritlm - -# Legacy build targets that were renamed in #7809, but we want to build binaries that for them that output a deprecation warning if people try to use them. -# We don't want to clutter things too much, so we only build replacements for the most commonly used binaries. -LEGACY_TARGETS_BUILD = main quantize perplexity embedding server - -# Deprecation aliases -ifdef LLAMA_CUBLAS -$(error LLAMA_CUBLAS is removed. Use GGML_CUDA instead.) -endif - -ifdef LLAMA_CUDA -GGML_CUDA := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_KOMPUTE -GGML_KOMPUTE := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_METAL -GGML_METAL := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_RPC -GGML_RPC := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_SYCL -GGML_SYCL := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_SYCL_F16 -GGML_SYCL_F16 := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_OPENBLAS -GGML_OPENBLAS := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_OPENBLAS64 -GGML_OPENBLAS64 := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_BLIS -GGML_BLIS := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_NO_LLAMAFILE -GGML_NO_LLAMAFILE := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_NO_ACCELERATE -GGML_NO_ACCELERATE := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_NO_OPENMP -GGML_NO_OPENMP := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_NO_METAL -GGML_NO_METAL := 1 -DEPRECATE_WARNING := 1 -endif - -ifdef LLAMA_DISABLE_LOGS -REMOVE_WARNING := 1 -endif - -ifdef LLAMA_SERVER_VERBOSE -REMOVE_WARNING := 1 -endif - -ifndef UNAME_S -UNAME_S := $(shell uname -s) -endif - -ifndef UNAME_P -UNAME_P := $(shell uname -p) -endif - -ifndef UNAME_M -UNAME_M := $(shell uname -m) -endif - -# In GNU make default CXX is g++ instead of c++. Let's fix that so that users -# of non-gcc compilers don't have to provide g++ alias or wrapper. -DEFCC := cc -DEFCXX := c++ -ifeq ($(origin CC),default) -CC := $(DEFCC) -endif -ifeq ($(origin CXX),default) -CXX := $(DEFCXX) -endif - -# Mac OS + Arm can report x86_64 -# ref: https://github.com/ggerganov/whisper.cpp/issues/66#issuecomment-1282546789 -ifeq ($(UNAME_S),Darwin) - ifndef GGML_NO_METAL - GGML_METAL := 1 - endif - - GGML_NO_OPENMP := 1 - - ifneq ($(UNAME_P),arm) - SYSCTL_M := $(shell sysctl -n hw.optional.arm64 2>/dev/null) - ifeq ($(SYSCTL_M),1) - # UNAME_P := arm - # UNAME_M := arm64 - warn := $(warning Your arch is announced as x86_64, but it seems to actually be ARM64. Not fixing that can lead to bad performance. For more info see: https://github.com/ggerganov/whisper.cpp/issues/66\#issuecomment-1282546789) - endif - endif -endif - -ifdef GGML_METAL - GGML_METAL_EMBED_LIBRARY := 1 -endif - -ifdef GGML_RPC - BUILD_TARGETS += rpc-server -endif - -ifdef GGML_VULKAN - BUILD_TARGETS += vulkan-shaders-gen -endif - -default: $(BUILD_TARGETS) $(LEGACY_TARGETS_BUILD) - -test: $(TEST_TARGETS) - @failures=0; \ - for test_target in $(TEST_TARGETS); do \ - if [ "$$test_target" = "tests/test-tokenizer-0" ]; then \ - ./$$test_target $(CURDIR)/models/ggml-vocab-llama-spm.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-llama-bpe.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-phi-3.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-falcon.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-bert-bge.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-starcoder.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-gpt-2.gguf; \ - ./$$test_target $(CURDIR)/models/ggml-vocab-refact.gguf; \ - elif [ "$$test_target" = "tests/test-tokenizer-1-spm" ]; then \ - continue; \ - elif [ "$$test_target" = "tests/test-tokenizer-1-bpe" ]; then \ - continue; \ - else \ - echo "Running test $$test_target..."; \ - ./$$test_target; \ - fi; \ - if [ $$? -ne 0 ]; then \ - printf 'Test %s FAILED!\n\n' $$test_target; \ - failures=$$(( failures + 1 )); \ - else \ - printf 'Test %s passed.\n\n' $$test_target; \ - fi; \ - done; \ - if [ $$failures -gt 0 ]; then \ - printf '\n%s tests failed.\n' $$failures; \ - exit 1; \ - fi - @echo 'All tests passed.' - -all: $(BUILD_TARGETS) $(TEST_TARGETS) $(LEGACY_TARGETS_BUILD) - -ifdef RISCV_CROSS_COMPILE -CC := riscv64-unknown-linux-gnu-gcc -CXX := riscv64-unknown-linux-gnu-g++ -endif - -# -# Compile flags -# - -# keep standard at C11 and C++17 -MK_CPPFLAGS = -Iggml/include -Iggml/src -Iinclude -Isrc -Icommon -DGGML_USE_CPU -MK_CFLAGS = -std=c11 -fPIC -MK_CXXFLAGS = -std=c++17 -fPIC -MK_NVCCFLAGS = -std=c++17 - -ifdef LLAMA_NO_CCACHE -GGML_NO_CCACHE := 1 -DEPRECATE_WARNING := 1 -endif - -ifndef GGML_NO_CCACHE -CCACHE := $(shell which ccache) -ifdef CCACHE -export CCACHE_SLOPPINESS = time_macros -$(info I ccache found, compilation results will be cached. Disable with GGML_NO_CCACHE.) -CC := $(CCACHE) $(CC) -CXX := $(CCACHE) $(CXX) -else -$(info I ccache not found. Consider installing it for faster compilation.) -endif # CCACHE -endif # GGML_NO_CCACHE - -# clock_gettime came in POSIX.1b (1993) -# CLOCK_MONOTONIC came in POSIX.1-2001 / SUSv3 as optional -# posix_memalign came in POSIX.1-2001 / SUSv3 -# M_PI is an XSI extension since POSIX.1-2001 / SUSv3, came in XPG1 (1985) -MK_CPPFLAGS += -D_XOPEN_SOURCE=600 - -# Somehow in OpenBSD whenever POSIX conformance is specified -# some string functions rely on locale_t availability, -# which was introduced in POSIX.1-2008, forcing us to go higher -ifeq ($(UNAME_S),OpenBSD) - MK_CPPFLAGS += -U_XOPEN_SOURCE -D_XOPEN_SOURCE=700 -endif - -# Data types, macros and functions related to controlling CPU affinity and -# some memory allocation are available on Linux through GNU extensions in libc -ifeq ($(UNAME_S),Linux) - MK_CPPFLAGS += -D_GNU_SOURCE - MK_LDFLAGS += -ldl -endif - -# RLIMIT_MEMLOCK came in BSD, is not specified in POSIX.1, -# and on macOS its availability depends on enabling Darwin extensions -# similarly on DragonFly, enabling BSD extensions is necessary -ifeq ($(UNAME_S),Darwin) - MK_CPPFLAGS += -D_DARWIN_C_SOURCE -endif -ifeq ($(UNAME_S),DragonFly) - MK_CPPFLAGS += -D__BSD_VISIBLE -endif - -# alloca is a non-standard interface that is not visible on BSDs when -# POSIX conformance is specified, but not all of them provide a clean way -# to enable it in such cases -ifeq ($(UNAME_S),FreeBSD) - MK_CPPFLAGS += -D__BSD_VISIBLE -endif -ifeq ($(UNAME_S),NetBSD) - MK_CPPFLAGS += -D_NETBSD_SOURCE -endif -ifeq ($(UNAME_S),OpenBSD) - MK_CPPFLAGS += -D_BSD_SOURCE -endif - -ifdef GGML_SCHED_MAX_COPIES - MK_CPPFLAGS += -DGGML_SCHED_MAX_COPIES=$(GGML_SCHED_MAX_COPIES) -endif - -ifdef LLAMA_DEBUG - MK_CFLAGS += -O0 -g - MK_CXXFLAGS += -O0 -g - MK_LDFLAGS += -g - MK_NVCCFLAGS += -O0 -g - - ifeq ($(UNAME_S),Linux) - MK_CPPFLAGS += -D_GLIBCXX_ASSERTIONS - endif -else - MK_CPPFLAGS += -DNDEBUG - MK_CFLAGS += -O3 -g - MK_CXXFLAGS += -O3 -g - MK_NVCCFLAGS += -O3 -g -endif - -ifdef LLAMA_SANITIZE_THREAD - MK_CFLAGS += -fsanitize=thread -g - MK_CXXFLAGS += -fsanitize=thread -g - MK_LDFLAGS += -fsanitize=thread -g -endif - -ifdef LLAMA_SANITIZE_ADDRESS - MK_CFLAGS += -fsanitize=address -fno-omit-frame-pointer -g - MK_CXXFLAGS += -fsanitize=address -fno-omit-frame-pointer -g - MK_LDFLAGS += -fsanitize=address -fno-omit-frame-pointer -g -endif - -ifdef LLAMA_SANITIZE_UNDEFINED - MK_CFLAGS += -fsanitize=undefined -g - MK_CXXFLAGS += -fsanitize=undefined -g - MK_LDFLAGS += -fsanitize=undefined -g -endif - -ifdef LLAMA_SERVER_SSL - MK_CPPFLAGS += -DCPPHTTPLIB_OPENSSL_SUPPORT - MK_LDFLAGS += -lssl -lcrypto -endif - -ifndef GGML_NO_CPU_AARCH64 - MK_CPPFLAGS += -DGGML_USE_CPU_REPACK -endif - -# warnings -WARN_FLAGS = \ - -Wall \ - -Wextra \ - -Wpedantic \ - -Wcast-qual \ - -Wno-unused-function - -MK_CFLAGS += \ - $(WARN_FLAGS) \ - -Wshadow \ - -Wstrict-prototypes \ - -Wpointer-arith \ - -Wmissing-prototypes \ - -Werror=implicit-int \ - -Werror=implicit-function-declaration - -MK_CXXFLAGS += \ - $(WARN_FLAGS) \ - -Wmissing-declarations \ - -Wmissing-noreturn - -ifeq ($(LLAMA_FATAL_WARNINGS),1) - MK_CFLAGS += -Werror - MK_CXXFLAGS += -Werror -endif - -# this version of Apple ld64 is buggy -ifneq '' '$(findstring dyld-1015.7,$(shell $(CC) $(LDFLAGS) -Wl,-v 2>&1))' - MK_CPPFLAGS += -DHAVE_BUGGY_APPLE_LINKER -endif - -# OS specific -# TODO: support Windows -ifneq '' '$(filter $(UNAME_S),Linux Darwin FreeBSD NetBSD OpenBSD Haiku)' - MK_CFLAGS += -pthread - MK_CXXFLAGS += -pthread -endif - -# detect Windows -ifneq ($(findstring _NT,$(UNAME_S)),) - _WIN32 := 1 -endif - -# library name prefix -ifneq ($(_WIN32),1) - LIB_PRE := lib -endif - -# Dynamic Shared Object extension -ifneq ($(_WIN32),1) - DSO_EXT := .so -else - DSO_EXT := .dll -endif - -# Windows Sockets 2 (Winsock) for network-capable apps -ifeq ($(_WIN32),1) - LWINSOCK2 := -lws2_32 -endif - -ifdef LLAMA_GPROF - MK_CFLAGS += -pg - MK_CXXFLAGS += -pg -endif - -# Architecture specific -# TODO: probably these flags need to be tweaked on some architectures -# feel free to update the Makefile for your architecture and send a pull request or issue - -ifndef RISCV_CROSS_COMPILE - -ifeq ($(UNAME_M),$(filter $(UNAME_M),x86_64 i686 amd64)) - # Use all CPU extensions that are available: - MK_CFLAGS += -march=native -mtune=native - HOST_CXXFLAGS += -march=native -mtune=native - - # Usage AMX build test - #MK_CFLAGS += -march=graniterapids -mtune=graniterapids - #HOST_CXXFLAGS += -march=graniterapids -mtune=graniterapids - - # Usage AVX-only - #MK_CFLAGS += -mfma -mf16c -mavx - #MK_CXXFLAGS += -mfma -mf16c -mavx - - # Usage SSSE3-only (Not is SSE3!) - #MK_CFLAGS += -mssse3 - #MK_CXXFLAGS += -mssse3 -endif - -ifneq '' '$(findstring mingw,$(shell $(CC) -dumpmachine))' - # The stack is only 16-byte aligned on Windows, so don't let gcc emit aligned moves. - # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54412 - # https://github.com/ggml-org/llama.cpp/issues/2922 - MK_CFLAGS += -Xassembler -muse-unaligned-vector-move - MK_CXXFLAGS += -Xassembler -muse-unaligned-vector-move - - # Target Windows 8 for PrefetchVirtualMemory - MK_CPPFLAGS += -D_WIN32_WINNT=0x602 -endif - -ifneq ($(filter aarch64%,$(UNAME_M)),) - # Apple M1, M2, etc. - # Raspberry Pi 3, 4, Zero 2 (64-bit) - # Nvidia Jetson - MK_CFLAGS += -mcpu=native - MK_CXXFLAGS += -mcpu=native - JETSON_RELEASE_INFO = $(shell jetson_release) - ifdef JETSON_RELEASE_INFO - ifneq ($(filter TX2%,$(JETSON_RELEASE_INFO)),) - JETSON_EOL_MODULE_DETECT = 1 - CC = aarch64-unknown-linux-gnu-gcc - cxx = aarch64-unknown-linux-gnu-g++ - endif - endif -endif - -ifneq ($(filter armv6%,$(UNAME_M)),) - # Raspberry Pi 1, Zero - MK_CFLAGS += -mfpu=neon-fp-armv8 -mfp16-format=ieee -mno-unaligned-access - MK_CXXFLAGS += -mfpu=neon-fp-armv8 -mfp16-format=ieee -mno-unaligned-access -endif - -ifneq ($(filter armv7%,$(UNAME_M)),) - # Raspberry Pi 2 - MK_CFLAGS += -mfpu=neon-fp-armv8 -mfp16-format=ieee -mno-unaligned-access -funsafe-math-optimizations - MK_CXXFLAGS += -mfpu=neon-fp-armv8 -mfp16-format=ieee -mno-unaligned-access -funsafe-math-optimizations -endif - -ifneq ($(filter armv8%,$(UNAME_M)),) - # Raspberry Pi 3, 4, Zero 2 (32-bit) - MK_CFLAGS += -mfp16-format=ieee -mno-unaligned-access - MK_CXXFLAGS += -mfp16-format=ieee -mno-unaligned-access -endif - -ifneq ($(filter ppc64%,$(UNAME_M)),) - POWER9_M := $(shell grep "POWER9" /proc/cpuinfo) - ifneq (,$(findstring POWER9,$(POWER9_M))) - MK_CFLAGS += -mcpu=power9 - MK_CXXFLAGS += -mcpu=power9 - endif -endif - -ifneq ($(filter ppc64le%,$(UNAME_M)),) - MK_CFLAGS += -mcpu=powerpc64le - MK_CXXFLAGS += -mcpu=powerpc64le - CUDA_POWER_ARCH = 1 -endif - -ifneq ($(filter loongarch64%,$(UNAME_M)),) - MK_CFLAGS += -mlasx - MK_CXXFLAGS += -mlasx -endif - -ifneq ($(filter riscv64%,$(UNAME_M)),) - MK_CFLAGS += -march=rv64gcv -mabi=lp64d - MK_CXXFLAGS += -march=rv64gcv -mabi=lp64d -endif - -else # RISC-V CROSS COMPILATION - MK_CFLAGS += -march=rv64gcv -mabi=lp64d - MK_CXXFLAGS += -march=rv64gcv -mabi=lp64d -endif - -ifndef GGML_NO_ACCELERATE - # Mac OS - include Accelerate framework. - # `-framework Accelerate` works both with Apple Silicon and Mac Intel - ifeq ($(UNAME_S),Darwin) - MK_CPPFLAGS += -DGGML_USE_ACCELERATE -DGGML_USE_BLAS -DGGML_BLAS_USE_ACCELERATE - MK_CPPFLAGS += -DACCELERATE_NEW_LAPACK - MK_CPPFLAGS += -DACCELERATE_LAPACK_ILP64 - MK_LDFLAGS += -framework Accelerate - OBJ_GGML_EXT += ggml/src/ggml-blas/ggml-blas.o - endif -endif # GGML_NO_ACCELERATE - -ifndef GGML_NO_OPENMP - MK_CPPFLAGS += -DGGML_USE_OPENMP - MK_CFLAGS += -fopenmp - MK_CXXFLAGS += -fopenmp -endif # GGML_NO_OPENMP - -ifdef GGML_OPENBLAS - MK_CPPFLAGS += -DGGML_USE_BLAS $(shell pkg-config --cflags-only-I openblas) - MK_CFLAGS += $(shell pkg-config --cflags-only-other openblas) - MK_LDFLAGS += $(shell pkg-config --libs openblas) - OBJ_GGML_EXT += ggml/src/ggml-blas/ggml-blas.o -endif # GGML_OPENBLAS - -ifdef GGML_OPENBLAS64 - MK_CPPFLAGS += -DGGML_USE_BLAS $(shell pkg-config --cflags-only-I openblas64) - MK_CFLAGS += $(shell pkg-config --cflags-only-other openblas64) - MK_LDFLAGS += $(shell pkg-config --libs openblas64) - OBJ_GGML_EXT += ggml/src/ggml-blas/ggml-blas.o -endif # GGML_OPENBLAS64 - -ifdef GGML_BLIS - MK_CPPFLAGS += -DGGML_USE_BLAS -DGGML_BLAS_USE_BLIS -I/usr/local/include/blis -I/usr/include/blis - MK_LDFLAGS += -lblis -L/usr/local/lib - OBJ_GGML_EXT += ggml/src/ggml-blas/ggml-blas.o -endif # GGML_BLIS - -ifdef GGML_NVPL - MK_CPPFLAGS += -DGGML_USE_BLAS -DGGML_BLAS_USE_NVPL -DNVPL_ILP64 -I/usr/local/include/nvpl_blas -I/usr/include/nvpl_blas - MK_LDFLAGS += -L/usr/local/lib -lnvpl_blas_core -lnvpl_blas_ilp64_gomp - OBJ_GGML_EXT += ggml/src/ggml-blas/ggml-blas.o -endif # GGML_NVPL - -ifndef GGML_NO_LLAMAFILE - MK_CPPFLAGS += -DGGML_USE_LLAMAFILE - OBJ_GGML_EXT += ggml/src/ggml-cpu/llamafile/sgemm.o -endif - -ifndef GGML_NO_AMX - MK_CPPFLAGS += -DGGML_USE_AMX - OBJ_GGML_EXT += ggml/src/ggml-cpu/amx/amx.o ggml/src/ggml-cpu/amx/mmq.o -endif - -# only necessary for the CPU backend files -MK_CPPFLAGS += -Iggml/src/ggml-cpu - -ifdef GGML_RPC - MK_CPPFLAGS += -DGGML_USE_RPC - OBJ_GGML_EXT += ggml/src/ggml-rpc.o -endif # GGML_RPC - -OBJ_CUDA_TMPL = $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/fattn-mma*.cu)) -OBJ_CUDA_TMPL += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/mmq*.cu)) - -ifdef GGML_CUDA_FA_ALL_QUANTS - OBJ_CUDA_TMPL += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/fattn-vec*.cu)) -else - OBJ_CUDA_TMPL += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/fattn-vec*q4_0-q4_0.cu)) - OBJ_CUDA_TMPL += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/fattn-vec*q8_0-q8_0.cu)) - OBJ_CUDA_TMPL += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/template-instances/fattn-vec*f16-f16.cu)) -endif # GGML_CUDA_FA_ALL_QUANTS - -ifdef GGML_CUDA - ifneq ('', '$(wildcard /opt/cuda)') - CUDA_PATH ?= /opt/cuda - else - CUDA_PATH ?= /usr/local/cuda - endif - - MK_CPPFLAGS += -DGGML_USE_CUDA -DGGML_CUDA_USE_GRAPHS -I$(CUDA_PATH)/include -I$(CUDA_PATH)/targets/$(UNAME_M)-linux/include - MK_LDFLAGS += -lcuda -lcublas -lculibos -lcudart -lcublasLt -lpthread -ldl -lrt -L$(CUDA_PATH)/lib64 -L/usr/lib64 -L$(CUDA_PATH)/targets/$(UNAME_M)-linux/lib -L$(CUDA_PATH)/lib64/stubs -L/usr/lib/wsl/lib - MK_NVCCFLAGS += -use_fast_math - - OBJ_GGML_EXT += ggml/src/ggml-cuda/ggml-cuda.o - OBJ_GGML_EXT += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/*.cu)) - OBJ_GGML_EXT += $(OBJ_CUDA_TMPL) - -ifdef LLAMA_FATAL_WARNINGS - MK_NVCCFLAGS += -Werror all-warnings -endif # LLAMA_FATAL_WARNINGS - -ifndef JETSON_EOL_MODULE_DETECT - MK_NVCCFLAGS += --forward-unknown-to-host-compiler -endif # JETSON_EOL_MODULE_DETECT - -ifdef LLAMA_DEBUG - MK_NVCCFLAGS += -lineinfo -endif # LLAMA_DEBUG - -ifdef GGML_CUDA_DEBUG - MK_NVCCFLAGS += --device-debug -endif # GGML_CUDA_DEBUG - -ifdef GGML_CUDA_NVCC - NVCC = $(CCACHE) $(GGML_CUDA_NVCC) -else - NVCC = $(CCACHE) nvcc -endif # GGML_CUDA_NVCC - -ifdef CUDA_DOCKER_ARCH - MK_NVCCFLAGS += -Wno-deprecated-gpu-targets -arch=$(CUDA_DOCKER_ARCH) -else ifndef CUDA_POWER_ARCH - MK_NVCCFLAGS += -arch=native -endif # CUDA_DOCKER_ARCH - -ifdef GGML_CUDA_FORCE_MMQ - MK_NVCCFLAGS += -DGGML_CUDA_FORCE_MMQ -endif # GGML_CUDA_FORCE_MMQ - -ifdef GGML_CUDA_FORCE_CUBLAS - MK_NVCCFLAGS += -DGGML_CUDA_FORCE_CUBLAS -endif # GGML_CUDA_FORCE_CUBLAS - -ifdef GGML_CUDA_F16 - MK_NVCCFLAGS += -DGGML_CUDA_F16 -endif # GGML_CUDA_F16 - -ifdef GGML_CUDA_DMMV_F16 - MK_NVCCFLAGS += -DGGML_CUDA_F16 -endif # GGML_CUDA_DMMV_F16 - -ifdef GGML_CUDA_PEER_MAX_BATCH_SIZE - MK_NVCCFLAGS += -DGGML_CUDA_PEER_MAX_BATCH_SIZE=$(GGML_CUDA_PEER_MAX_BATCH_SIZE) -else - MK_NVCCFLAGS += -DGGML_CUDA_PEER_MAX_BATCH_SIZE=128 -endif # GGML_CUDA_PEER_MAX_BATCH_SIZE - -ifdef GGML_CUDA_NO_PEER_COPY - MK_NVCCFLAGS += -DGGML_CUDA_NO_PEER_COPY -endif # GGML_CUDA_NO_PEER_COPY - -ifdef GGML_CUDA_CCBIN - MK_NVCCFLAGS += -ccbin $(GGML_CUDA_CCBIN) -endif # GGML_CUDA_CCBIN - -ifdef GGML_CUDA_NO_FA - MK_NVCCFLAGS += -DGGML_CUDA_NO_FA -endif # GGML_CUDA_NO_FA - -ifdef GGML_CUDA_FA_ALL_QUANTS - MK_NVCCFLAGS += -DGGML_CUDA_FA_ALL_QUANTS -endif # GGML_CUDA_FA_ALL_QUANTS - -ifdef JETSON_EOL_MODULE_DETECT -define NVCC_COMPILE - $(NVCC) -I. -Icommon -D_XOPEN_SOURCE=600 -D_GNU_SOURCE -DNDEBUG -DGGML_USE_CUDA -I/usr/local/cuda/include -I/opt/cuda/include -I/usr/local/cuda/targets/aarch64-linux/include -std=c++11 -O3 $(NVCCFLAGS) $(CPPFLAGS) -Xcompiler "$(CUDA_CXXFLAGS)" -c $< -o $@ -endef # NVCC_COMPILE -else -define NVCC_COMPILE - $(NVCC) $(NVCCFLAGS) $(CPPFLAGS) -Xcompiler "$(CUDA_CXXFLAGS)" -c $< -o $@ -endef # NVCC_COMPILE -endif # JETSON_EOL_MODULE_DETECT - -ggml/src/ggml-cuda/%.o: \ - ggml/src/ggml-cuda/%.cu \ - ggml/include/ggml.h \ - ggml/src/ggml-common.h \ - ggml/src/ggml-cuda/common.cuh - $(NVCC_COMPILE) - -ggml/src/ggml-cuda/ggml-cuda.o: \ - ggml/src/ggml-cuda/ggml-cuda.cu \ - ggml/include/ggml-cuda.h \ - ggml/include/ggml.h \ - ggml/include/ggml-backend.h \ - ggml/src/ggml-backend-impl.h \ - ggml/src/ggml-common.h \ - $(wildcard ggml/src/ggml-cuda/*.cuh) - $(NVCC_COMPILE) -endif # GGML_CUDA - -ifdef GGML_VULKAN - MK_CPPFLAGS += -DGGML_USE_VULKAN - MK_LDFLAGS += $(shell pkg-config --libs vulkan) - OBJ_GGML_EXT += ggml/src/ggml-vulkan.o ggml/src/ggml-vulkan-shaders.o - -ifdef GGML_VULKAN_CHECK_RESULTS - MK_CPPFLAGS += -DGGML_VULKAN_CHECK_RESULTS -endif - -ifdef GGML_VULKAN_DEBUG - MK_CPPFLAGS += -DGGML_VULKAN_DEBUG -endif - -ifdef GGML_VULKAN_MEMORY_DEBUG - MK_CPPFLAGS += -DGGML_VULKAN_MEMORY_DEBUG -endif - -ifdef GGML_VULKAN_PERF - MK_CPPFLAGS += -DGGML_VULKAN_PERF -endif - -ifdef GGML_VULKAN_VALIDATE - MK_CPPFLAGS += -DGGML_VULKAN_VALIDATE -endif - -ifdef GGML_VULKAN_RUN_TESTS - MK_CPPFLAGS += -DGGML_VULKAN_RUN_TESTS -endif - -GLSLC_CMD = glslc -_ggml_vk_genshaders_cmd = $(shell pwd)/vulkan-shaders-gen -_ggml_vk_header = ggml/src/ggml-vulkan-shaders.hpp -_ggml_vk_source = ggml/src/ggml-vulkan-shaders.cpp -_ggml_vk_input_dir = ggml/src/ggml-vulkan/vulkan-shaders -_ggml_vk_shader_deps = $(echo $(_ggml_vk_input_dir)/*.comp) - -ggml/src/ggml-vulkan.o: ggml/src/ggml-vulkan/ggml-vulkan.cpp ggml/include/ggml-vulkan.h $(_ggml_vk_header) $(_ggml_vk_source) - $(CXX) $(CXXFLAGS) $(shell pkg-config --cflags vulkan) -c $< -o $@ - -$(_ggml_vk_header): $(_ggml_vk_source) - -$(_ggml_vk_source): $(_ggml_vk_shader_deps) vulkan-shaders-gen - $(_ggml_vk_genshaders_cmd) \ - --glslc $(GLSLC_CMD) \ - --input-dir $(_ggml_vk_input_dir) \ - --target-hpp $(_ggml_vk_header) \ - --target-cpp $(_ggml_vk_source) - -vulkan-shaders-gen: ggml/src/ggml-vulkan/vulkan-shaders/vulkan-shaders-gen.cpp - $(CXX) $(CXXFLAGS) -o $@ $(LDFLAGS) ggml/src/ggml-vulkan/vulkan-shaders/vulkan-shaders-gen.cpp - -endif # GGML_VULKAN - -ifdef GGML_HIP - ifeq ($(wildcard /opt/rocm),) - ROCM_PATH ?= /usr - AMDGPU_TARGETS ?= $(shell $(shell which amdgpu-arch)) - else - ROCM_PATH ?= /opt/rocm - AMDGPU_TARGETS ?= $(shell $(ROCM_PATH)/llvm/bin/amdgpu-arch) - endif - - MK_CPPFLAGS += -DGGML_USE_HIP -DGGML_USE_CUDA - - MK_LDFLAGS += -L$(ROCM_PATH)/lib -Wl,-rpath=$(ROCM_PATH)/lib - MK_LDFLAGS += -L$(ROCM_PATH)/lib64 -Wl,-rpath=$(ROCM_PATH)/lib64 - MK_LDFLAGS += -lhipblas -lamdhip64 -lrocblas - - HIPCC ?= $(CCACHE) $(ROCM_PATH)/bin/hipcc - - HIPFLAGS += $(addprefix --offload-arch=,$(AMDGPU_TARGETS)) - -ifdef GGML_CUDA_FORCE_MMQ - HIPFLAGS += -DGGML_CUDA_FORCE_MMQ -endif # GGML_CUDA_FORCE_MMQ - -ifdef GGML_CUDA_FORCE_CUBLAS - HIPFLAGS += -DGGML_CUDA_FORCE_CUBLAS -endif # GGML_CUDA_FORCE_CUBLAS - -ifdef GGML_CUDA_NO_PEER_COPY - HIPFLAGS += -DGGML_CUDA_NO_PEER_COPY -endif # GGML_CUDA_NO_PEER_COPY - -ifdef GGML_CUDA_NO_FA - HIPFLAGS += -DGGML_CUDA_NO_FA -endif # GGML_CUDA_NO_FA - - OBJ_GGML_EXT += ggml/src/ggml-cuda/ggml-cuda.o - OBJ_GGML_EXT += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/*.cu)) - OBJ_GGML_EXT += $(OBJ_CUDA_TMPL) - -ggml/src/ggml-cuda/ggml-cuda.o: \ - ggml/src/ggml-cuda/ggml-cuda.cu \ - ggml/include/ggml-cuda.h \ - ggml/include/ggml.h \ - ggml/include/ggml-backend.h \ - ggml/src/ggml-backend-impl.h \ - ggml/src/ggml-common.h \ - $(wildcard ggml/src/ggml-cuda/*.cuh) - $(HIPCC) $(CXXFLAGS) $(HIPFLAGS) -x hip -c -o $@ $< - -ggml/src/ggml-cuda/%.o: \ - ggml/src/ggml-cuda/%.cu \ - ggml/include/ggml.h \ - ggml/src/ggml-common.h \ - ggml/src/ggml-cuda/common.cuh - $(HIPCC) $(CXXFLAGS) $(HIPFLAGS) -x hip -c -o $@ $< -endif # GGML_HIP - -ifdef GGML_MUSA - ifeq ($(wildcard /opt/musa),) - MUSA_PATH ?= /usr/local/musa - else - MUSA_PATH ?= /opt/musa - endif - MUSA_ARCHITECTURES ?= 21;22;31 - - MK_CPPFLAGS += -DGGML_USE_MUSA -DGGML_USE_CUDA - MK_LDFLAGS += -L$(MUSA_PATH)/lib -Wl,-rpath=$(MUSA_PATH)/lib - MK_LDFLAGS += -lmusa -lmusart -lmublas - - ifndef GGML_NO_OPENMP - # For Ubuntu Focal - MK_CPPFLAGS += -I/usr/lib/llvm-10/include/openmp - MK_LDFLAGS += -L/usr/lib/llvm-10/lib - # For Ubuntu Jammy - MK_CPPFLAGS += -I/usr/lib/llvm-14/lib/clang/14.0.0/include - MK_LDFLAGS += -L/usr/lib/llvm-14/lib - endif # GGML_NO_OPENMP - - CC := $(MUSA_PATH)/bin/clang - CXX := $(MUSA_PATH)/bin/clang++ - MCC := $(CCACHE) $(MUSA_PATH)/bin/mcc - - MUSAFLAGS = -fsigned-char -x musa -mtgpu - MUSAFLAGS += $(foreach arch,$(subst ;, ,$(MUSA_ARCHITECTURES)),--cuda-gpu-arch=mp_$(arch)) - -ifdef GGML_CUDA_FORCE_MMQ - MUSAFLAGS += -DGGML_CUDA_FORCE_MMQ -endif # GGML_CUDA_FORCE_MMQ - -ifdef GGML_CUDA_FORCE_CUBLAS - MUSAFLAGS += -DGGML_CUDA_FORCE_CUBLAS -endif # GGML_CUDA_FORCE_CUBLAS - -ifdef GGML_CUDA_F16 - MUSAFLAGS += -DGGML_CUDA_F16 -endif # GGML_CUDA_F16 - -ifdef GGML_CUDA_DMMV_F16 - MUSAFLAGS += -DGGML_CUDA_F16 -endif # GGML_CUDA_DMMV_F16 - -ifdef GGML_CUDA_PEER_MAX_BATCH_SIZE - MUSAFLAGS += -DGGML_CUDA_PEER_MAX_BATCH_SIZE=$(GGML_CUDA_PEER_MAX_BATCH_SIZE) -else - MUSAFLAGS += -DGGML_CUDA_PEER_MAX_BATCH_SIZE=128 -endif # GGML_CUDA_PEER_MAX_BATCH_SIZE - -ifdef GGML_CUDA_NO_PEER_COPY - MUSAFLAGS += -DGGML_CUDA_NO_PEER_COPY -endif # GGML_CUDA_NO_PEER_COPY - -ifdef GGML_CUDA_NO_FA - MUSAFLAGS += -DGGML_CUDA_NO_FA -endif # GGML_CUDA_NO_FA - -ifdef GGML_CUDA_FA_ALL_QUANTS - MUSAFLAGS += -DGGML_CUDA_FA_ALL_QUANTS -endif # GGML_CUDA_FA_ALL_QUANTS - - OBJ_GGML_EXT += ggml/src/ggml-cuda/ggml-cuda.o - OBJ_GGML_EXT += $(patsubst %.cu,%.o,$(wildcard ggml/src/ggml-cuda/*.cu)) - OBJ_GGML_EXT += $(OBJ_CUDA_TMPL) - -ggml/src/ggml-cuda/ggml-cuda.o: \ - ggml/src/ggml-cuda/ggml-cuda.cu \ - ggml/include/ggml-cuda.h \ - ggml/include/ggml.h \ - ggml/include/ggml-backend.h \ - ggml/src/ggml-backend-impl.h \ - ggml/src/ggml-common.h \ - $(wildcard ggml/src/ggml-cuda/*.cuh) - $(MCC) $(CXXFLAGS) $(MUSAFLAGS) -c -o $@ $< - -ggml/src/ggml-cuda/%.o: \ - ggml/src/ggml-cuda/%.cu \ - ggml/include/ggml.h \ - ggml/src/ggml-common.h \ - ggml/src/ggml-cuda/common.cuh - $(MCC) $(CXXFLAGS) $(MUSAFLAGS) -c -o $@ $< -endif # GGML_MUSA - -ifdef GGML_METAL - MK_CPPFLAGS += -DGGML_USE_METAL - MK_LDFLAGS += -framework Foundation -framework Metal -framework MetalKit - OBJ_GGML_EXT += ggml/src/ggml-metal/ggml-metal.o - -ifdef GGML_METAL_USE_BF16 - MK_CPPFLAGS += -DGGML_METAL_USE_BF16 -endif # GGML_METAL_USE_BF16 -ifdef GGML_METAL_NDEBUG - MK_CPPFLAGS += -DGGML_METAL_NDEBUG -endif -ifdef GGML_METAL_EMBED_LIBRARY - MK_CPPFLAGS += -DGGML_METAL_EMBED_LIBRARY - OBJ_GGML_EXT += ggml/src/ggml-metal-embed.o -endif -endif # GGML_METAL - -ifdef GGML_METAL -ggml/src/ggml-metal/ggml-metal.o: \ - ggml/src/ggml-metal/ggml-metal.m \ - ggml/src/ggml-metal/ggml-metal-impl.h \ - ggml/include/ggml-metal.h \ - ggml/include/ggml.h - $(CC) $(CFLAGS) -c $< -o $@ - -ifdef GGML_METAL_EMBED_LIBRARY -ggml/src/ggml-metal-embed.o: \ - ggml/src/ggml-metal/ggml-metal.metal \ - ggml/src/ggml-metal/ggml-metal-impl.h \ - ggml/src/ggml-common.h - @echo "Embedding Metal library" - @sed -e '/__embed_ggml-common.h__/r ggml/src/ggml-common.h' -e '/__embed_ggml-common.h__/d' < ggml/src/ggml-metal/ggml-metal.metal > ggml/src/ggml-metal/ggml-metal-embed.metal.tmp - @sed -e '/#include "ggml-metal-impl.h"/r ggml/src/ggml-metal/ggml-metal-impl.h' -e '/#include "ggml-metal-impl.h"/d' < ggml/src/ggml-metal/ggml-metal-embed.metal.tmp > ggml/src/ggml-metal/ggml-metal-embed.metal - $(eval TEMP_ASSEMBLY=$(shell mktemp -d)) - @echo ".section __DATA, __ggml_metallib" > $(TEMP_ASSEMBLY)/ggml-metal-embed.s - @echo ".globl _ggml_metallib_start" >> $(TEMP_ASSEMBLY)/ggml-metal-embed.s - @echo "_ggml_metallib_start:" >> $(TEMP_ASSEMBLY)/ggml-metal-embed.s - @echo ".incbin \"ggml/src/ggml-metal/ggml-metal-embed.metal\"" >> $(TEMP_ASSEMBLY)/ggml-metal-embed.s - @echo ".globl _ggml_metallib_end" >> $(TEMP_ASSEMBLY)/ggml-metal-embed.s - @echo "_ggml_metallib_end:" >> $(TEMP_ASSEMBLY)/ggml-metal-embed.s - $(CC) $(CFLAGS) -c $(TEMP_ASSEMBLY)/ggml-metal-embed.s -o $@ - @rm -f ${TEMP_ASSEMBLY}/ggml-metal-embed.s - @rmdir ${TEMP_ASSEMBLY} -endif -endif # GGML_METAL - -DIR_GGML = ggml -DIR_LLAMA = src -DIR_COMMON = common - -OBJ_GGML = \ - $(DIR_GGML)/src/ggml.o \ - $(DIR_GGML)/src/ggml-alloc.o \ - $(DIR_GGML)/src/ggml-backend.o \ - $(DIR_GGML)/src/ggml-backend-reg.o \ - $(DIR_GGML)/src/ggml-opt.o \ - $(DIR_GGML)/src/ggml-quants.o \ - $(DIR_GGML)/src/ggml-threading.o \ - $(DIR_GGML)/src/ggml-cpu/ggml-cpu.o \ - $(DIR_GGML)/src/ggml-cpu/ggml-cpu_cpp.o \ - $(DIR_GGML)/src/ggml-cpu/repack.o \ - $(DIR_GGML)/src/ggml-cpu/ggml-cpu-hbm.o \ - $(DIR_GGML)/src/ggml-cpu/ggml-cpu-quants.o \ - $(DIR_GGML)/src/ggml-cpu/ggml-cpu-traits.o \ - $(OBJ_GGML_EXT) - -OBJ_LLAMA = \ - $(DIR_LLAMA)/llama.o \ - $(DIR_LLAMA)/llama-vocab.o \ - $(DIR_LLAMA)/llama-grammar.o \ - $(DIR_LLAMA)/llama-sampling.o \ - $(DIR_LLAMA)/unicode.o \ - $(DIR_LLAMA)/unicode-data.o - -OBJ_COMMON = \ - $(DIR_COMMON)/common.o \ - $(DIR_COMMON)/arg.o \ - $(DIR_COMMON)/log.o \ - $(DIR_COMMON)/console.o \ - $(DIR_COMMON)/ngram-cache.o \ - $(DIR_COMMON)/sampling.o \ - $(DIR_COMMON)/speculative.o \ - $(DIR_COMMON)/chat.o \ - $(DIR_COMMON)/build-info.o \ - $(DIR_COMMON)/json-schema-to-grammar.o - -OBJ_ALL = $(OBJ_GGML) $(OBJ_LLAMA) $(OBJ_COMMON) - -LIB_GGML = $(LIB_PRE)ggml$(DSO_EXT) -LIB_GGML_S = $(LIB_PRE)ggml.a - -LIB_LLAMA = $(LIB_PRE)llama$(DSO_EXT) -LIB_LLAMA_S = $(LIB_PRE)llama.a - -LIB_COMMON = $(LIB_PRE)common$(DSO_EXT) -LIB_COMMON_S = $(LIB_PRE)common.a - -LIB_ALL = $(LIB_GGML) $(LIB_LLAMA) $(LIB_COMMON) -LIB_ALL_S = $(LIB_GGML_S) $(LIB_LLAMA_S) $(LIB_COMMON_S) - -GF_CC := $(CC) -include scripts/get-flags.mk - -# combine build flags with cmdline overrides -override CPPFLAGS := $(MK_CPPFLAGS) $(CPPFLAGS) -override CFLAGS := $(CPPFLAGS) $(MK_CFLAGS) $(GF_CFLAGS) $(CFLAGS) -BASE_CXXFLAGS := $(MK_CXXFLAGS) $(CXXFLAGS) -override CXXFLAGS := $(BASE_CXXFLAGS) $(HOST_CXXFLAGS) $(GF_CXXFLAGS) $(CPPFLAGS) -override NVCCFLAGS := $(MK_NVCCFLAGS) $(NVCCFLAGS) -override LDFLAGS := $(MK_LDFLAGS) $(LDFLAGS) - -# identify CUDA host compiler -ifdef GGML_CUDA -GF_CC := $(NVCC) $(NVCCFLAGS) 2>/dev/null .c -Xcompiler -include scripts/get-flags.mk -CUDA_CXXFLAGS := $(BASE_CXXFLAGS) $(GF_CXXFLAGS) -Wno-pedantic -endif - -ifdef LLAMA_CURL -override CXXFLAGS := $(CXXFLAGS) -DLLAMA_USE_CURL -override LDFLAGS := $(LDFLAGS) -lcurl -endif - -# -# Print build information -# - -$(info I llama.cpp build info: ) -$(info I UNAME_S: $(UNAME_S)) -$(info I UNAME_P: $(UNAME_P)) -$(info I UNAME_M: $(UNAME_M)) -$(info I CFLAGS: $(CFLAGS)) -$(info I CXXFLAGS: $(CXXFLAGS)) -$(info I NVCCFLAGS: $(NVCCFLAGS)) -$(info I LDFLAGS: $(LDFLAGS)) -$(info I CC: $(shell $(CC) --version | head -n 1)) -$(info I CXX: $(shell $(CXX) --version | head -n 1)) -ifdef GGML_CUDA -$(info I NVCC: $(shell $(NVCC) --version | tail -n 1)) -CUDA_VERSION := $(shell $(NVCC) --version | grep -oP 'release (\K[0-9]+\.[0-9])') -ifeq ($(shell awk -v "v=$(CUDA_VERSION)" 'BEGIN { print (v < 11.7) }'),1) - -ifndef CUDA_DOCKER_ARCH -ifndef CUDA_POWER_ARCH -$(error I ERROR: For CUDA versions < 11.7 a target CUDA architecture must be explicitly provided via environment variable CUDA_DOCKER_ARCH, e.g. by running "export CUDA_DOCKER_ARCH=compute_XX" on Unix-like systems, where XX is the minimum compute capability that the code needs to run on. A list with compute capabilities can be found here: https://developer.nvidia.com/cuda-gpus ) -endif # CUDA_POWER_ARCH -endif # CUDA_DOCKER_ARCH - -endif # eq ($(shell echo "$(CUDA_VERSION) < 11.7" | bc),1) -endif # GGML_CUDA -$(info ) - -ifdef DEPRECATE_WARNING -$(info !!! DEPRECATION WARNING !!!) -$(info The following LLAMA_ options are deprecated and will be removed in the future. Use the GGML_ prefix instead) -$(info - LLAMA_CUDA) -$(info - LLAMA_METAL) -$(info - LLAMA_METAL_EMBED_LIBRARY) -$(info - LLAMA_OPENMP) -$(info - LLAMA_RPC) -$(info - LLAMA_SYCL) -$(info - LLAMA_SYCL_F16) -$(info - LLAMA_OPENBLAS) -$(info - LLAMA_OPENBLAS64) -$(info - LLAMA_BLIS) -$(info - LLAMA_NO_LLAMAFILE) -$(info - LLAMA_NO_ACCELERATE) -$(info - LLAMA_NO_OPENMP) -$(info - LLAMA_NO_METAL) -$(info - LLAMA_NO_CCACHE) -$(info ) -endif - -ifdef REMOVE_WARNING -$(info !!! REMOVAL WARNING !!!) -$(info The following LLAMA_ options have been removed and are no longer supported) -$(info - LLAMA_DISABLE_LOGS (https://github.com/ggml-org/llama.cpp/pull/9418)) -$(info - LLAMA_SERVER_VERBOSE (https://github.com/ggml-org/llama.cpp/pull/9418)) -$(info ) -endif - -# -# Build libraries -# - -# Libraries -LIB_GGML = libggml.so -LIB_GGML_S = libggml.a - -LIB_LLAMA = libllama.so -LIB_LLAMA_S = libllama.a - -LIB_COMMON = libcommon.so -LIB_COMMON_S = libcommon.a - -# Targets -BUILD_TARGETS += $(LIB_GGML) $(LIB_GGML_S) $(LIB_LLAMA) $(LIB_LLAMA_S) $(LIB_COMMON) $(LIB_COMMON_S) - -# Dependency files -DEP_FILES = $(OBJ_GGML:.o=.d) $(OBJ_LLAMA:.o=.d) $(OBJ_COMMON:.o=.d) - -# Default target -all: $(BUILD_TARGETS) - -# force c++ build for source file that have same name as c file -# Note: need this exception because `ggml-cpu.c` and `ggml-cpu.cpp` both produce the same obj/dep files -$(DIR_GGML)/%_cpp.o: $(DIR_GGML)/%.cpp - $(CXX) $(CXXFLAGS) -MMD -c $< -o $@ - -# Rules for building object files -$(DIR_GGML)/%.o: $(DIR_GGML)/%.c - $(CC) $(CFLAGS) -MMD -c $< -o $@ - -$(DIR_GGML)/%.o: $(DIR_GGML)/%.cpp - $(CXX) $(CXXFLAGS) -MMD -c $< -o $@ - -$(DIR_LLAMA)/%.o: $(DIR_LLAMA)/%.cpp - $(CXX) $(CXXFLAGS) -MMD -c $< -o $@ - -$(DIR_COMMON)/%.o: $(DIR_COMMON)/%.cpp - $(CXX) $(CXXFLAGS) -MMD -c $< -o $@ - -# Rules for building libraries -$(LIB_GGML): $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -shared -fPIC -o $@ $^ $(LDFLAGS) - -$(LIB_GGML_S): $(OBJ_GGML) - ar rcs $(LIB_GGML_S) $^ - -$(LIB_LLAMA): $(OBJ_LLAMA) $(LIB_GGML) - $(CXX) $(CXXFLAGS) -shared -fPIC -o $@ $^ $(LDFLAGS) - -$(LIB_LLAMA_S): $(OBJ_LLAMA) - ar rcs $(LIB_LLAMA_S) $^ - -$(LIB_COMMON): $(OBJ_COMMON) $(LIB_LLAMA) $(LIB_GGML) - $(CXX) $(CXXFLAGS) -shared -fPIC -o $@ $^ $(LDFLAGS) - -$(LIB_COMMON_S): $(OBJ_COMMON) - ar rcs $(LIB_COMMON_S) $^ - -# Include dependency files --include $(DEP_FILES) - -# Clean generated server assets -clean-server-assets: - find tools/server -type f -name "*.js.hpp" -delete - find tools/server -type f -name "*.mjs.hpp" -delete - find tools/server -type f -name "*.css.hpp" -delete - find tools/server -type f -name "*.html.hpp" -delete - -# Clean rule -clean: clean-server-assets - rm -vrf $(BUILD_TARGETS) $(TEST_TARGETS) - rm -rvf *.a *.dll *.so *.dot - find ggml src common tests examples pocs -type f -name "*.o" -delete - find ggml src common tests examples pocs -type f -name "*.d" -delete - -# -# Examples -# - -# $< is the first prerequisite, i.e. the source file. -# Explicitly compile this to an object file so that it can be cached with ccache. -# The source file is then filtered out from $^ (the list of all prerequisites) and the object file is added instead. - -# Helper function that replaces .c, .cpp, and .cu file endings with .o: -GET_OBJ_FILE = $(patsubst %.c,%.o,$(patsubst %.cpp,%.o,$(patsubst %.cu,%.o,$(1)))) - -llama-cli: tools/main/main.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - @echo - @echo '==== Run ./llama-cli -h for help. ====' - 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$(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-speculative: examples/speculative/speculative.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-parallel: examples/parallel/parallel.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-lookahead: examples/lookahead/lookahead.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-lookup: examples/lookup/lookup.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-lookup-create: examples/lookup/lookup-create.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-lookup-merge: examples/lookup/lookup-merge.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-lookup-stats: examples/lookup/lookup-stats.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-passkey: examples/passkey/passkey.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-gbnf-validator: examples/gbnf-validator/gbnf-validator.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -ifdef GGML_RPC -rpc-server: tools/rpc/rpc-server.cpp \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) $^ -o $@ $(LDFLAGS) -endif # GGML_RPC - -llama-server: \ - tools/server/server.cpp \ - tools/server/utils.hpp \ - tools/server/httplib.h \ - tools/server/index.html.hpp \ - tools/server/loading.html.hpp \ - common/chat.cpp \ - common/chat.h \ - common/chat-template.hpp \ - common/json.hpp \ - common/minja.hpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h %.hpp $<,$^) -Itools/server $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) $(LWINSOCK2) - -# Portable equivalent of `cd tools/server/public && xxd -i $(notdir $<) ../$(notdir $<).hpp`: -tools/server/%.hpp: tools/server/public/% FORCE Makefile - @( export NAME=$(subst .,_,$(subst -,_,$(notdir $<))) && \ - echo "unsigned char $${NAME}[] = {" && \ - cat $< | od -v -t x1 -An | sed -E 's/([0-9a-fA-F]+)/0x\1, /g' && \ - echo "};" && \ - echo "unsigned int $${NAME}_len = $(shell cat $< | wc -c );" \ - ) > $@ - -llama-gen-docs: examples/gen-docs/gen-docs.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -libllava.a: tools/mtmd/llava.cpp \ - tools/mtmd/llava.h \ - tools/mtmd/clip.cpp \ - tools/mtmd/clip.h \ - common/stb_image.h \ - common/base64.hpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -static -fPIC -c $< -o $@ -Wno-cast-qual - -llama-llava-cli: tools/mtmd/llava-cli.cpp \ - tools/mtmd/llava.cpp \ - tools/mtmd/llava.h \ - tools/mtmd/clip.cpp \ - tools/mtmd/clip.h \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) $< $(filter-out %.h $<,$^) -o $@ $(LDFLAGS) -Wno-cast-qual - -llama-minicpmv-cli: tools/mtmd/minicpmv-cli.cpp \ - tools/mtmd/llava.cpp \ - tools/mtmd/llava.h \ - tools/mtmd/clip.cpp \ - tools/mtmd/clip.h \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) $< $(filter-out %.h $<,$^) -o $@ $(LDFLAGS) -Wno-cast-qual - -llama-qwen2vl-cli: tools/mtmd/qwen2vl-cli.cpp \ - tools/mtmd/llava.cpp \ - tools/mtmd/llava.h \ - tools/mtmd/clip.cpp \ - tools/mtmd/clip.h \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) $< $(filter-out %.h $<,$^) -o $@ $(LDFLAGS) -Wno-cast-qual - -ifeq ($(UNAME_S),Darwin) -swift: examples/batched.swift - (cd examples/batched.swift; make build) -endif - -common/build-info.cpp: $(wildcard .git/index) scripts/build-info.sh - @sh scripts/build-info.sh "$(CC)" > $@.tmp - @if ! cmp -s $@.tmp $@; then \ - mv $@.tmp $@; \ - else \ - rm $@.tmp; \ - fi - -common/build-info.o: common/build-info.cpp - $(CXX) $(CXXFLAGS) -c $(filter-out %.h,$^) -o $@ - -# -# Tests -# - -tests: $(TEST_TARGETS) - -tests/test-arg-parser: tests/test-arg-parser.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-llama-grammar: tests/test-llama-grammar.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-log: tests/test-log.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-grammar-parser: tests/test-grammar-parser.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-grammar-integration: tests/test-grammar-integration.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-double-float: tests/test-double-float.cpp - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-json-schema-to-grammar: tests/test-json-schema-to-grammar.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -Itools/server -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-chat: tests/test-chat.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -Itools/server -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-opt: tests/test-opt.cpp \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-quantize-fns: tests/test-quantize-fns.cpp \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-quantize-perf: tests/test-quantize-perf.cpp \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-sampling: tests/test-sampling.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-tokenizer-0: tests/test-tokenizer-0.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-tokenizer-1-bpe: tests/test-tokenizer-1-bpe.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-tokenizer-1-spm: tests/test-tokenizer-1-spm.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-rope: tests/test-rope.cpp ggml/src/ggml.o \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-c.o: tests/test-c.c include/llama.h - $(CC) $(CFLAGS) -c $(filter-out %.h,$^) -o $@ - -tests/test-backend-ops: tests/test-backend-ops.cpp \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-model-load-cancel: tests/test-model-load-cancel.cpp tests/get-model.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-autorelease: tests/test-autorelease.cpp tests/get-model.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -tests/test-chat-template: tests/test-chat-template.cpp \ - $(OBJ_ALL) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out %.h $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -# -# PoCs -# - -llama-vdot: pocs/vdot/vdot.cpp ggml/src/ggml.o \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -llama-q8dot: pocs/vdot/q8dot.cpp ggml/src/ggml.o \ - $(OBJ_GGML) - $(CXX) $(CXXFLAGS) -c $< -o $(call GET_OBJ_FILE, $<) - $(CXX) $(CXXFLAGS) $(filter-out $<,$^) $(call GET_OBJ_FILE, $<) -o $@ $(LDFLAGS) - -# -# Deprecated binaries that we want to keep around long enough for people to migrate to the new filenames, then these can be removed. -# -# Mark legacy binary targets as .PHONY so that they are always checked. -.PHONY: FORCE main quantize perplexity embedding server - -# Define the object file target -examples/deprecation-warning/deprecation-warning.o: examples/deprecation-warning/deprecation-warning.cpp - $(CXX) $(CXXFLAGS) -c $< -o $@ - -# NOTE: We currently will always build the deprecation-warning `main` and `server` binaries to help users migrate. -# Eventually we will want to remove these target from building all the time. -main: examples/deprecation-warning/deprecation-warning.o - $(CXX) $(CXXFLAGS) $< -o $@ $(LDFLAGS) - @echo "NOTICE: The 'main' binary is deprecated. Please use 'llama-cli' instead." - -server: examples/deprecation-warning/deprecation-warning.o - $(CXX) $(CXXFLAGS) $< -o $@ $(LDFLAGS) - @echo "NOTICE: The 'server' binary is deprecated. Please use 'llama-server' instead." - -quantize: examples/deprecation-warning/deprecation-warning.o -ifneq (,$(wildcard quantize)) - $(CXX) $(CXXFLAGS) $< -o $@ $(LDFLAGS) - @echo "#########" - @echo "WARNING: The 'quantize' binary is deprecated. Please use 'llama-quantize' instead." - @echo " Remove the 'quantize' binary to remove this warning." - @echo "#########" -endif - -perplexity: examples/deprecation-warning/deprecation-warning.o -ifneq (,$(wildcard perplexity)) - $(CXX) $(CXXFLAGS) $< -o $@ $(LDFLAGS) - @echo "#########" - @echo "WARNING: The 'perplexity' binary is deprecated. Please use 'llama-perplexity' instead." - @echo " Remove the 'perplexity' binary to remove this warning." - @echo "#########" -endif - -embedding: examples/deprecation-warning/deprecation-warning.o -ifneq (,$(wildcard embedding)) - $(CXX) $(CXXFLAGS) $< -o $@ $(LDFLAGS) - @echo "#########" - @echo "WARNING: The 'embedding' binary is deprecated. Please use 'llama-embedding' instead." - @echo " Remove the 'embedding' binary to remove this warning." - @echo "#########" -endif +$(error Build system changed:$(newline)\ +The Makefile build has been replaced by CMake.$(newline)$(newline)\ +For build instructions see:$(newline)\ +https://github.com/ggml-org/llama.cpp/blob/master/docs/build.md$(newline)${newline}) diff -pruN 5882+dfsg-2/README.md 6641+dfsg-2/README.md --- 5882+dfsg-2/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -17,6 +17,9 @@ LLM inference in C/C++ ## Hot topics +- **[guide : running gpt-oss with llama.cpp](https://github.com/ggml-org/llama.cpp/discussions/15396)** +- **[[FEEDBACK] Better packaging for llama.cpp to support downstream consumers 🤗](https://github.com/ggml-org/llama.cpp/discussions/15313)** +- Support for the `gpt-oss` model with native MXFP4 format has been added | [PR](https://github.com/ggml-org/llama.cpp/pull/15091) | [Collaboration with NVIDIA](https://blogs.nvidia.com/blog/rtx-ai-garage-openai-oss) | [Comment](https://github.com/ggml-org/llama.cpp/discussions/15095) - Hot PRs: [All](https://github.com/ggml-org/llama.cpp/pulls?q=is%3Apr+label%3Ahot+) | [Open](https://github.com/ggml-org/llama.cpp/pulls?q=is%3Apr+label%3Ahot+is%3Aopen) - Multimodal support arrived in `llama-server`: [#12898](https://github.com/ggml-org/llama.cpp/pull/12898) | [documentation](./docs/multimodal.md) - VS Code extension for FIM completions: https://github.com/ggml-org/llama.vscode @@ -133,6 +136,8 @@ Instructions for adding support for new - [x] [GigaChat-20B-A3B](https://huggingface.co/ai-sage/GigaChat-20B-A3B-instruct) - [X] [Trillion-7B-preview](https://huggingface.co/trillionlabs/Trillion-7B-preview) - [x] [Ling models](https://huggingface.co/collections/inclusionAI/ling-67c51c85b34a7ea0aba94c32) +- [x] [LFM2 models](https://huggingface.co/collections/LiquidAI/lfm2-686d721927015b2ad73eaa38) +- [x] [Hunyuan models](https://huggingface.co/collections/tencent/hunyuan-dense-model-6890632cda26b19119c9c5e7) #### Multimodal @@ -147,6 +152,7 @@ Instructions for adding support for new - [x] [Bunny](https://github.com/BAAI-DCAI/Bunny) - [x] [GLM-EDGE](https://huggingface.co/models?search=glm-edge) - [x] [Qwen2-VL](https://huggingface.co/collections/Qwen/qwen2-vl-66cee7455501d7126940800d) +- [x] [LFM2-VL](https://huggingface.co/collections/LiquidAI/lfm2-vl-68963bbc84a610f7638d5ffa) @@ -172,6 +178,7 @@ Instructions for adding support for new - Clojure: [phronmophobic/llama.clj](https://github.com/phronmophobic/llama.clj) - React Native: [mybigday/llama.rn](https://github.com/mybigday/llama.rn) - Java: [kherud/java-llama.cpp](https://github.com/kherud/java-llama.cpp) +- Java: [QuasarByte/llama-cpp-jna](https://github.com/QuasarByte/llama-cpp-jna) - Zig: [deins/llama.cpp.zig](https://github.com/Deins/llama.cpp.zig) - Flutter/Dart: [netdur/llama_cpp_dart](https://github.com/netdur/llama_cpp_dart) - Flutter: [xuegao-tzx/Fllama](https://github.com/xuegao-tzx/Fllama) @@ -238,7 +245,7 @@ Instructions for adding support for new
Infrastructure -- [Paddler](https://github.com/distantmagic/paddler) - Stateful load balancer custom-tailored for llama.cpp +- [Paddler](https://github.com/intentee/paddler) - Open-source LLMOps platform for hosting and scaling AI in your own infrastructure - [GPUStack](https://github.com/gpustack/gpustack) - Manage GPU clusters for running LLMs - [llama_cpp_canister](https://github.com/onicai/llama_cpp_canister) - llama.cpp as a smart contract on the Internet Computer, using WebAssembly - [llama-swap](https://github.com/mostlygeek/llama-swap) - transparent proxy that adds automatic model switching with llama-server @@ -268,6 +275,8 @@ Instructions for adding support for new | [Vulkan](docs/build.md#vulkan) | GPU | | [CANN](docs/build.md#cann) | Ascend NPU | | [OpenCL](docs/backend/OPENCL.md) | Adreno GPU | +| [IBM zDNN](docs/backend/zDNN.md) | IBM Z & LinuxONE | +| [WebGPU [In Progress]](docs/build.md#webgpu) | All | | [RPC](https://github.com/ggml-org/llama.cpp/tree/master/tools/rpc) | All | ## Obtaining and quantizing models @@ -433,7 +442,7 @@ To learn more about model quantization, ## [`llama-perplexity`](tools/perplexity) -#### A tool for measuring the perplexity [^1][^2] (and other quality metrics) of a model over a given text. +#### A tool for measuring the [perplexity](tools/perplexity/README.md) [^1] (and other quality metrics) of a model over a given text. -
Measure the perplexity over a text file @@ -456,8 +465,7 @@ To learn more about model quantization,
-[^1]: [tools/perplexity/README.md](./tools/perplexity/README.md) -[^2]: [https://huggingface.co/docs/transformers/perplexity](https://huggingface.co/docs/transformers/perplexity) +[^1]: [https://huggingface.co/docs/transformers/perplexity](https://huggingface.co/docs/transformers/perplexity) ## [`llama-bench`](tools/llama-bench) @@ -514,8 +522,8 @@ To learn more about model quantization, ## Contributing - Contributors can open PRs -- Collaborators can push to branches in the `llama.cpp` repo and merge PRs into the `master` branch - Collaborators will be invited based on contributions +- Maintainers can push to branches in the `llama.cpp` repo and merge PRs into the `master` branch - Any help with managing issues, PRs and projects is very appreciated! - See [good first issues](https://github.com/ggml-org/llama.cpp/issues?q=is%3Aissue+is%3Aopen+label%3A%22good+first+issue%22) for tasks suitable for first contributions - Read the [CONTRIBUTING.md](CONTRIBUTING.md) for more information diff -pruN 5882+dfsg-2/build-xcframework.sh 6641+dfsg-2/build-xcframework.sh --- 5882+dfsg-2/build-xcframework.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/build-xcframework.sh 2025-09-30 07:36:33.000000000 +0000 @@ -422,6 +422,7 @@ echo "Building for iOS devices..." cmake -B build-ios-device -G Xcode \ "${COMMON_CMAKE_ARGS[@]}" \ -DCMAKE_OSX_DEPLOYMENT_TARGET=${IOS_MIN_OS_VERSION} \ + -DCMAKE_SYSTEM_NAME=iOS \ -DCMAKE_OSX_SYSROOT=iphoneos \ -DCMAKE_OSX_ARCHITECTURES="arm64" \ -DCMAKE_XCODE_ATTRIBUTE_SUPPORTED_PLATFORMS=iphoneos \ diff -pruN 5882+dfsg-2/ci/README-MUSA.md 6641+dfsg-2/ci/README-MUSA.md --- 5882+dfsg-2/ci/README-MUSA.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ci/README-MUSA.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,35 @@ +## Running MUSA CI in a Docker Container + +Assuming `$PWD` is the root of the `llama.cpp` repository, follow these steps to set up and run MUSA CI in a Docker container: + +### 1. Create a local directory to store cached models, configuration files and venv: + +```bash +mkdir -p $HOME/llama.cpp/ci-cache +``` + +### 2. Create a local directory to store CI run results: + +```bash +mkdir -p $HOME/llama.cpp/ci-results +``` + +### 3. Start a Docker container and run the CI: + +```bash +docker run --privileged -it \ + -v $HOME/llama.cpp/ci-cache:/ci-cache \ + -v $HOME/llama.cpp/ci-results:/ci-results \ + -v $PWD:/ws -w /ws \ + mthreads/musa:rc4.3.0-devel-ubuntu22.04-amd64 +``` + +Inside the container, execute the following commands: + +```bash +apt update -y && apt install -y bc cmake ccache git python3.10-venv time unzip wget +git config --global --add safe.directory /ws +GG_BUILD_MUSA=1 bash ./ci/run.sh /ci-results /ci-cache +``` + +This setup ensures that the CI runs within an isolated Docker environment while maintaining cached files and results across runs. diff -pruN 5882+dfsg-2/ci/README.md 6641+dfsg-2/ci/README.md --- 5882+dfsg-2/ci/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ci/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -1,18 +1,10 @@ # CI -In addition to [Github Actions](https://github.com/ggml-org/llama.cpp/actions) `llama.cpp` uses a custom CI framework: +This CI implements heavy-duty workflows that run on self-hosted runners. Typically the purpose of these workflows is to +cover hardware configurations that are not available from Github-hosted runners and/or require more computational +resource than normally available. -https://github.com/ggml-org/ci - -It monitors the `master` branch for new commits and runs the -[ci/run.sh](https://github.com/ggml-org/llama.cpp/blob/master/ci/run.sh) script on dedicated cloud instances. This allows us -to execute heavier workloads compared to just using Github Actions. Also with time, the cloud instances will be scaled -to cover various hardware architectures, including GPU and Apple Silicon instances. - -Collaborators can optionally trigger the CI run by adding the `ggml-ci` keyword to their commit message. -Only the branches of this repo are monitored for this keyword. - -It is a good practice, before publishing changes to execute the full CI locally on your machine: +It is a good practice, before publishing changes to execute the full CI locally on your machine. For example: ```bash mkdir tmp @@ -29,40 +21,13 @@ GG_BUILD_SYCL=1 bash ./ci/run.sh ./tmp/r # with MUSA support GG_BUILD_MUSA=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt -``` - -## Running MUSA CI in a Docker Container -Assuming `$PWD` is the root of the `llama.cpp` repository, follow these steps to set up and run MUSA CI in a Docker container: - -### 1. Create a local directory to store cached models, configuration files and venv: - -```bash -mkdir -p $HOME/llama.cpp/ci-cache +# etc. ``` -### 2. Create a local directory to store CI run results: - -```bash -mkdir -p $HOME/llama.cpp/ci-results -``` - -### 3. Start a Docker container and run the CI: - -```bash -docker run --privileged -it \ - -v $HOME/llama.cpp/ci-cache:/ci-cache \ - -v $HOME/llama.cpp/ci-results:/ci-results \ - -v $PWD:/ws -w /ws \ - mthreads/musa:rc4.0.1-mudnn-devel-ubuntu22.04 -``` - -Inside the container, execute the following commands: - -```bash -apt update -y && apt install -y bc cmake ccache git python3.10-venv time unzip wget -git config --global --add safe.directory /ws -GG_BUILD_MUSA=1 bash ./ci/run.sh /ci-results /ci-cache -``` +# Adding self-hosted runners -This setup ensures that the CI runs within an isolated Docker environment while maintaining cached files and results across runs. +- Add a self-hosted `ggml-ci` workflow to [[.github/workflows/build.yml]] with an appropriate label +- Request a runner token from `ggml-org` (for example, via a comment in the PR or email) +- Set-up a machine using the received token ([docs](https://docs.github.com/en/actions/how-tos/manage-runners/self-hosted-runners/add-runners)) +- Optionally update [ci/run.sh](https://github.com/ggml-org/llama.cpp/blob/master/ci/run.sh) to build and run on the target platform by gating the implementation with a `GG_BUILD_...` env diff -pruN 5882+dfsg-2/ci/run.sh 6641+dfsg-2/ci/run.sh --- 5882+dfsg-2/ci/run.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ci/run.sh 2025-09-30 07:36:33.000000000 +0000 @@ -16,6 +16,9 @@ # # with VULKAN support # GG_BUILD_VULKAN=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt # +# # with WebGPU support +# GG_BUILD_WEBGPU=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt +# # # with MUSA support # GG_BUILD_MUSA=1 bash ./ci/run.sh ./tmp/results ./tmp/mnt # @@ -42,7 +45,7 @@ SRC=`pwd` CMAKE_EXTRA="-DLLAMA_FATAL_WARNINGS=ON -DLLAMA_CURL=ON" if [ ! -z ${GG_BUILD_METAL} ]; then - CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_METAL=ON -DGGML_METAL_USE_BF16=ON" + CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_METAL=ON" fi if [ ! -z ${GG_BUILD_CUDA} ]; then @@ -62,6 +65,16 @@ if [ ! -z ${GG_BUILD_CUDA} ]; then fi fi +if [ ! -z ${GG_BUILD_ROCM} ]; then + CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_HIP=ON" + if [ -z ${GG_BUILD_AMDGPU_TARGETS} ]; then + echo "Missing GG_BUILD_AMDGPU_TARGETS, please set it to your GPU architecture (e.g. gfx90a, gfx1100, etc.)" + exit 1 + fi + + CMAKE_EXTRA="${CMAKE_EXTRA} -DAMDGPU_TARGETS=${GG_BUILD_AMDGPU_TARGETS}" +fi + if [ ! -z ${GG_BUILD_SYCL} ]; then if [ -z ${ONEAPI_ROOT} ]; then echo "Not detected ONEAPI_ROOT, please install oneAPI base toolkit and enable it by:" @@ -79,6 +92,16 @@ fi if [ ! -z ${GG_BUILD_VULKAN} ]; then CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_VULKAN=1" + + # if on Mac, disable METAL + if [[ "$OSTYPE" == "darwin"* ]]; then + CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_METAL=OFF -DGGML_BLAS=OFF" + fi + +fi + +if [ ! -z ${GG_BUILD_WEBGPU} ]; then + CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_WEBGPU=1" fi if [ ! -z ${GG_BUILD_MUSA} ]; then @@ -86,6 +109,12 @@ if [ ! -z ${GG_BUILD_MUSA} ]; then MUSA_ARCH=${MUSA_ARCH:-21} CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_MUSA=ON -DMUSA_ARCHITECTURES=${MUSA_ARCH}" fi + +if [ ! -z ${GG_BUILD_NO_SVE} ]; then + # arm 9 and newer enables sve by default, adjust these flags depending on the cpu used + CMAKE_EXTRA="${CMAKE_EXTRA} -DGGML_NATIVE=OFF -DGGML_CPU_ARM_ARCH=armv8.5-a+fp16+i8mm" +fi + ## helpers # download a file if it does not exist or if it is outdated @@ -99,7 +128,7 @@ function gg_wget { cd $out # should not re-download if file is the same - wget -nv -N $url + wget -nv -c -N $url cd $cwd } @@ -143,7 +172,7 @@ function gg_run_ctest_debug { (time cmake -DCMAKE_BUILD_TYPE=Debug ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log (time make -j$(nproc) ) 2>&1 | tee -a $OUT/${ci}-make.log - (time ctest --output-on-failure -L main -E test-opt ) 2>&1 | tee -a $OUT/${ci}-ctest.log + (time ctest --output-on-failure -L main -E "test-opt|test-backend-ops" ) 2>&1 | tee -a $OUT/${ci}-ctest.log set +e } @@ -193,33 +222,9 @@ function gg_sum_ctest_release { gg_printf '```\n' } -# test_scripts_debug - -function gg_run_test_scripts_debug { - cd ${SRC} - - set -e - - (cd ./tools/gguf-split && time bash tests.sh "$SRC/build-ci-debug/bin" "$MNT/models") 2>&1 | tee -a $OUT/${ci}-scripts.log - (cd ./tools/quantize && time bash tests.sh "$SRC/build-ci-debug/bin" "$MNT/models") 2>&1 | tee -a $OUT/${ci}-scripts.log - - set +e -} - -function gg_sum_test_scripts_debug { - gg_printf '### %s\n\n' "${ci}" - - gg_printf 'Runs test scripts in debug mode\n' - gg_printf '- status: %s\n' "$(cat $OUT/${ci}.exit)" - gg_printf '```\n' - gg_printf '%s\n' "$(cat $OUT/${ci}-scripts.log)" - gg_printf '```\n' - gg_printf '\n' -} - -# test_scripts_release +# test_scripts -function gg_run_test_scripts_release { +function gg_run_test_scripts { cd ${SRC} set -e @@ -230,10 +235,10 @@ function gg_run_test_scripts_release { set +e } -function gg_sum_test_scripts_release { +function gg_sum_test_scripts { gg_printf '### %s\n\n' "${ci}" - gg_printf 'Runs test scripts in release mode\n' + gg_printf 'Runs test scripts\n' gg_printf '- status: %s\n' "$(cat $OUT/${ci}.exit)" gg_printf '```\n' gg_printf '%s\n' "$(cat $OUT/${ci}-scripts.log)" @@ -242,15 +247,9 @@ function gg_sum_test_scripts_release { } function gg_get_model { - local gguf_0="$MNT/models/pythia/1.4B/ggml-model-f16.gguf" - local gguf_1="$MNT/models/pythia/2.8B/ggml-model-f16.gguf" - local gguf_2="$MNT/models/open-llama/7B-v2/ggml-model-f16.gguf" + local gguf_0="$MNT/models/qwen3/0.6B/ggml-model-f16.gguf" if [[ -s $gguf_0 ]]; then echo -n "$gguf_0" - elif [[ -s $gguf_1 ]]; then - echo -n "$gguf_1" - elif [[ -s $gguf_2 ]]; then - echo -n "$gguf_2" else echo >&2 "No model found. Can't run gg_run_ctest_with_model." exit 1 @@ -263,7 +262,9 @@ function gg_run_ctest_with_model_debug { local model; model=$(gg_get_model) cd build-ci-debug set -e + (LLAMACPP_TEST_MODELFILE="$model" time ctest --output-on-failure -L model) 2>&1 | tee -a $OUT/${ci}-ctest.log + set +e cd .. } @@ -274,7 +275,15 @@ function gg_run_ctest_with_model_release local model; model=$(gg_get_model) cd build-ci-release set -e + (LLAMACPP_TEST_MODELFILE="$model" time ctest --output-on-failure -L model) 2>&1 | tee -a $OUT/${ci}-ctest.log + + # test memory leaks + #if [[ ! -z ${GG_BUILD_METAL} ]]; then + # # TODO: this hangs for some reason ... + # (time leaks -quiet -atExit -- ./bin/test-thread-safety -m $model --parallel 2 -t 2 -p "hello") 2>&1 | tee -a $OUT/${ci}-leaks.log + #fi + set +e cd .. } @@ -299,289 +308,22 @@ function gg_sum_ctest_with_model_release gg_printf '```\n' } -# open_llama_7b_v2 - -function gg_run_open_llama_7b_v2 { - cd ${SRC} - - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/raw/main/config.json - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/resolve/main/tokenizer.model - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/raw/main/tokenizer_config.json - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/raw/main/special_tokens_map.json - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/raw/main/pytorch_model.bin.index.json - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/resolve/main/pytorch_model-00001-of-00002.bin - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/resolve/main/pytorch_model-00002-of-00002.bin - gg_wget models-mnt/open-llama/7B-v2/ https://huggingface.co/openlm-research/open_llama_7b_v2/raw/main/generation_config.json - - gg_wget models-mnt/wikitext/ https://huggingface.co/datasets/ggml-org/ci/resolve/main/wikitext-2-raw-v1.zip - unzip -o models-mnt/wikitext/wikitext-2-raw-v1.zip -d models-mnt/wikitext/ - - path_models="../models-mnt/open-llama/7B-v2" - path_wiki="../models-mnt/wikitext/wikitext-2-raw" - - rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release - - set -e - - (time cmake -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log - (time make -j$(nproc) ) 2>&1 | tee -a $OUT/${ci}-make.log - - python3 ../examples/convert_legacy_llama.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf - - model_f16="${path_models}/ggml-model-f16.gguf" - model_q8_0="${path_models}/ggml-model-q8_0.gguf" - model_q4_0="${path_models}/ggml-model-q4_0.gguf" - model_q4_1="${path_models}/ggml-model-q4_1.gguf" - model_q5_0="${path_models}/ggml-model-q5_0.gguf" - model_q5_1="${path_models}/ggml-model-q5_1.gguf" - model_q2_k="${path_models}/ggml-model-q2_k.gguf" - model_q3_k="${path_models}/ggml-model-q3_k.gguf" - model_q4_k="${path_models}/ggml-model-q4_k.gguf" - model_q5_k="${path_models}/ggml-model-q5_k.gguf" - model_q6_k="${path_models}/ggml-model-q6_k.gguf" - - wiki_test="${path_wiki}/wiki.test.raw" - - ./bin/llama-quantize ${model_f16} ${model_q8_0} q8_0 - ./bin/llama-quantize ${model_f16} ${model_q4_0} q4_0 - ./bin/llama-quantize ${model_f16} ${model_q4_1} q4_1 - ./bin/llama-quantize ${model_f16} ${model_q5_0} q5_0 - ./bin/llama-quantize ${model_f16} ${model_q5_1} q5_1 - ./bin/llama-quantize ${model_f16} ${model_q2_k} q2_k - ./bin/llama-quantize ${model_f16} ${model_q3_k} q3_k - ./bin/llama-quantize ${model_f16} ${model_q4_k} q4_k - ./bin/llama-quantize ${model_f16} ${model_q5_k} q5_k - ./bin/llama-quantize ${model_f16} ${model_q6_k} q6_k - - (time ./bin/llama-cli -no-cnv --model ${model_f16} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-cli -no-cnv --model ${model_q8_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_1} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_1} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q2_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q3_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q6_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-perplexity --model ${model_f16} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-perplexity --model ${model_q8_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-perplexity --model ${model_q4_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-perplexity --model ${model_q4_1} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-perplexity --model ${model_q5_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-perplexity --model ${model_q5_1} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-perplexity --model ${model_q2_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-perplexity --model ${model_q3_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-perplexity --model ${model_q4_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-perplexity --model ${model_q5_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-perplexity --model ${model_q6_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-imatrix --model ${model_f16} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-imatrix.log - - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 0 ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 0 -fa ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 -fa ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - - function check_ppl { - qnt="$1" - ppl=$(echo "$2" | grep -oE "[0-9]+\.[0-9]+" | tail -n 1) - - if [ $(echo "$ppl > 20.0" | bc) -eq 1 ]; then - printf ' - %s @ %s (FAIL: ppl > 20.0)\n' "$qnt" "$ppl" - return 20 - fi - - printf ' - %s @ %s OK\n' "$qnt" "$ppl" - return 0 - } - - check_ppl "f16" "$(cat $OUT/${ci}-tg-f16.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q8_0" "$(cat $OUT/${ci}-tg-q8_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_0" "$(cat $OUT/${ci}-tg-q4_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_1" "$(cat $OUT/${ci}-tg-q4_1.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_0" "$(cat $OUT/${ci}-tg-q5_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_1" "$(cat $OUT/${ci}-tg-q5_1.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q2_k" "$(cat $OUT/${ci}-tg-q2_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q3_k" "$(cat $OUT/${ci}-tg-q3_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_k" "$(cat $OUT/${ci}-tg-q4_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_k" "$(cat $OUT/${ci}-tg-q5_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q6_k" "$(cat $OUT/${ci}-tg-q6_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - - cat $OUT/${ci}-imatrix.log | grep "Final" >> $OUT/${ci}-imatrix-sum.log - - set +e -} - -function gg_sum_open_llama_7b_v2 { - gg_printf '### %s\n\n' "${ci}" - - gg_printf 'OpenLLaMA 7B-v2:\n' - gg_printf '- status: %s\n' "$(cat $OUT/${ci}.exit)" - gg_printf '- perplexity:\n%s\n' "$(cat $OUT/${ci}-ppl.log)" - gg_printf '- imatrix:\n```\n%s\n```\n' "$(cat $OUT/${ci}-imatrix-sum.log)" - gg_printf '- f16: \n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-f16.log)" - gg_printf '- q8_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q8_0.log)" - gg_printf '- q4_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_0.log)" - gg_printf '- q4_1:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_1.log)" - gg_printf '- q5_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_0.log)" - gg_printf '- q5_1:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_1.log)" - gg_printf '- q2_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q2_k.log)" - gg_printf '- q3_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q3_k.log)" - gg_printf '- q4_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_k.log)" - gg_printf '- q5_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_k.log)" - gg_printf '- q6_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q6_k.log)" - gg_printf '- save-load-state: \n```\n%s\n```\n' "$(cat $OUT/${ci}-save-load-state.log)" -} - -# pythia_1.4b +# qwen3_0_6b -function gg_run_pythia_1_4b { +function gg_run_qwen3_0_6b { cd ${SRC} - gg_wget models-mnt/pythia/1.4B/ https://huggingface.co/EleutherAI/pythia-1.4b/raw/main/config.json - gg_wget models-mnt/pythia/1.4B/ https://huggingface.co/EleutherAI/pythia-1.4b/raw/main/tokenizer.json - gg_wget models-mnt/pythia/1.4B/ https://huggingface.co/EleutherAI/pythia-1.4b/raw/main/tokenizer_config.json - gg_wget models-mnt/pythia/1.4B/ https://huggingface.co/EleutherAI/pythia-1.4b/raw/main/special_tokens_map.json - gg_wget models-mnt/pythia/1.4B/ https://huggingface.co/EleutherAI/pythia-1.4b/resolve/main/pytorch_model.bin - - gg_wget models-mnt/wikitext/ https://huggingface.co/datasets/ggml-org/ci/resolve/main/wikitext-2-raw-v1.zip - unzip -o models-mnt/wikitext/wikitext-2-raw-v1.zip -d models-mnt/wikitext/ - head -n 60 models-mnt/wikitext/wikitext-2-raw/wiki.test.raw > models-mnt/wikitext/wikitext-2-raw/wiki.test-60.raw - - path_models="../models-mnt/pythia/1.4B" - path_wiki="../models-mnt/wikitext/wikitext-2-raw" - - rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release - - set -e - - (time cmake -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log - (time make -j$(nproc) ) 2>&1 | tee -a $OUT/${ci}-make.log - - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf - - model_f16="${path_models}/ggml-model-f16.gguf" - model_q8_0="${path_models}/ggml-model-q8_0.gguf" - model_q4_0="${path_models}/ggml-model-q4_0.gguf" - model_q4_1="${path_models}/ggml-model-q4_1.gguf" - model_q5_0="${path_models}/ggml-model-q5_0.gguf" - model_q5_1="${path_models}/ggml-model-q5_1.gguf" - model_q2_k="${path_models}/ggml-model-q2_k.gguf" - model_q3_k="${path_models}/ggml-model-q3_k.gguf" - model_q4_k="${path_models}/ggml-model-q4_k.gguf" - model_q5_k="${path_models}/ggml-model-q5_k.gguf" - model_q6_k="${path_models}/ggml-model-q6_k.gguf" - - wiki_test_60="${path_wiki}/wiki.test-60.raw" - - ./bin/llama-quantize ${model_f16} ${model_q8_0} q8_0 - ./bin/llama-quantize ${model_f16} ${model_q4_0} q4_0 - ./bin/llama-quantize ${model_f16} ${model_q4_1} q4_1 - ./bin/llama-quantize ${model_f16} ${model_q5_0} q5_0 - ./bin/llama-quantize ${model_f16} ${model_q5_1} q5_1 - ./bin/llama-quantize ${model_f16} ${model_q2_k} q2_k - ./bin/llama-quantize ${model_f16} ${model_q3_k} q3_k - ./bin/llama-quantize ${model_f16} ${model_q4_k} q4_k - ./bin/llama-quantize ${model_f16} ${model_q5_k} q5_k - ./bin/llama-quantize ${model_f16} ${model_q6_k} q6_k - - (time ./bin/llama-cli -no-cnv --model ${model_f16} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-cli -no-cnv --model ${model_q8_0} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_0} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_1} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_0} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_1} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q2_k} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q3_k} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_k} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_k} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q6_k} -ngl 99 -c 0 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-perplexity --model ${model_f16} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-perplexity --model ${model_q8_0} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-perplexity --model ${model_q4_0} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-perplexity --model ${model_q4_1} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-perplexity --model ${model_q5_0} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-perplexity --model ${model_q5_1} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-perplexity --model ${model_q2_k} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-perplexity --model ${model_q3_k} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-perplexity --model ${model_q4_k} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-perplexity --model ${model_q5_k} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-perplexity --model ${model_q6_k} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-imatrix --model ${model_f16} -f ${wiki_test_60} -ngl 99 -c 128 -b 128 --chunks 1 ) 2>&1 | tee -a $OUT/${ci}-imatrix.log + gg_wget models-mnt/qwen3/0.6B/ https://huggingface.co/Qwen/Qwen3-0.6B-Base/raw/main/config.json + gg_wget models-mnt/qwen3/0.6B/ https://huggingface.co/Qwen/Qwen3-0.6B-Base/raw/main/tokenizer.json + gg_wget models-mnt/qwen3/0.6B/ https://huggingface.co/Qwen/Qwen3-0.6B-Base/raw/main/tokenizer_config.json + #gg_wget models-mnt/qwen3/0.6B/ https://huggingface.co/Qwen/Qwen3-0.6B-Base/raw/main/special_tokens_map.json + gg_wget models-mnt/qwen3/0.6B/ https://huggingface.co/Qwen/Qwen3-0.6B-Base/resolve/main/model.safetensors - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 -fa ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - - function check_ppl { - qnt="$1" - ppl=$(echo "$2" | grep -oE "[0-9]+\.[0-9]+" | tail -n 1) - - if [ $(echo "$ppl > 20.0" | bc) -eq 1 ]; then - printf ' - %s @ %s (FAIL: ppl > 20.0)\n' "$qnt" "$ppl" - return 20 - fi - - printf ' - %s @ %s OK\n' "$qnt" "$ppl" - return 0 - } - - check_ppl "f16" "$(cat $OUT/${ci}-tg-f16.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q8_0" "$(cat $OUT/${ci}-tg-q8_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_0" "$(cat $OUT/${ci}-tg-q4_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_1" "$(cat $OUT/${ci}-tg-q4_1.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_0" "$(cat $OUT/${ci}-tg-q5_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_1" "$(cat $OUT/${ci}-tg-q5_1.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - #check_ppl "q2_k" "$(cat $OUT/${ci}-tg-q2_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log # note: ppl > 20.0 for this quant and model - check_ppl "q3_k" "$(cat $OUT/${ci}-tg-q3_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q4_k" "$(cat $OUT/${ci}-tg-q4_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q5_k" "$(cat $OUT/${ci}-tg-q5_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - check_ppl "q6_k" "$(cat $OUT/${ci}-tg-q6_k.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log - - cat $OUT/${ci}-imatrix.log | grep "Final" >> $OUT/${ci}-imatrix-sum.log - - set +e -} - -function gg_sum_pythia_1_4b { - gg_printf '### %s\n\n' "${ci}" - - gg_printf 'Pythia 1.4B:\n' - gg_printf '- status: %s\n' "$(cat $OUT/${ci}.exit)" - gg_printf '- perplexity:\n%s\n' "$(cat $OUT/${ci}-ppl.log)" - gg_printf '- imatrix:\n```\n%s\n```\n' "$(cat $OUT/${ci}-imatrix-sum.log)" - gg_printf '- f16: \n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-f16.log)" - gg_printf '- q8_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q8_0.log)" - gg_printf '- q4_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_0.log)" - gg_printf '- q4_1:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_1.log)" - gg_printf '- q5_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_0.log)" - gg_printf '- q5_1:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_1.log)" - gg_printf '- q2_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q2_k.log)" - gg_printf '- q3_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q3_k.log)" - gg_printf '- q4_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_k.log)" - gg_printf '- q5_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q5_k.log)" - gg_printf '- q6_k:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q6_k.log)" - gg_printf '- save-load-state: \n```\n%s\n```\n' "$(cat $OUT/${ci}-save-load-state.log)" -} - -# pythia_2_8b - -function gg_run_pythia_2_8b { - cd ${SRC} - - gg_wget models-mnt/pythia/2.8B/ https://huggingface.co/EleutherAI/pythia-2.8b/raw/main/config.json - gg_wget models-mnt/pythia/2.8B/ https://huggingface.co/EleutherAI/pythia-2.8b/raw/main/tokenizer.json - gg_wget models-mnt/pythia/2.8B/ https://huggingface.co/EleutherAI/pythia-2.8b/raw/main/tokenizer_config.json - gg_wget models-mnt/pythia/2.8B/ https://huggingface.co/EleutherAI/pythia-2.8b/raw/main/special_tokens_map.json - gg_wget models-mnt/pythia/2.8B/ https://huggingface.co/EleutherAI/pythia-2.8b/resolve/main/pytorch_model.bin gg_wget models-mnt/wikitext/ https://huggingface.co/datasets/ggml-org/ci/resolve/main/wikitext-2-raw-v1.zip unzip -o models-mnt/wikitext/wikitext-2-raw-v1.zip -d models-mnt/wikitext/ - path_models="../models-mnt/pythia/2.8B" + path_models="../models-mnt/qwen3/0.6B" path_wiki="../models-mnt/wikitext/wikitext-2-raw" rm -rf build-ci-release && mkdir build-ci-release && cd build-ci-release @@ -591,9 +333,11 @@ function gg_run_pythia_2_8b { (time cmake -DCMAKE_BUILD_TYPE=Release ${CMAKE_EXTRA} .. ) 2>&1 | tee -a $OUT/${ci}-cmake.log (time make -j$(nproc) ) 2>&1 | tee -a $OUT/${ci}-make.log - python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-f16.gguf --outtype f16 + python3 ../convert_hf_to_gguf.py ${path_models} --outfile ${path_models}/ggml-model-bf16.gguf --outtype bf16 model_f16="${path_models}/ggml-model-f16.gguf" + model_bf16="${path_models}/ggml-model-bf16.gguf" model_q8_0="${path_models}/ggml-model-q8_0.gguf" model_q4_0="${path_models}/ggml-model-q4_0.gguf" model_q4_1="${path_models}/ggml-model-q4_1.gguf" @@ -607,47 +351,51 @@ function gg_run_pythia_2_8b { wiki_test="${path_wiki}/wiki.test.raw" - ./bin/llama-quantize ${model_f16} ${model_q8_0} q8_0 - ./bin/llama-quantize ${model_f16} ${model_q4_0} q4_0 - ./bin/llama-quantize ${model_f16} ${model_q4_1} q4_1 - ./bin/llama-quantize ${model_f16} ${model_q5_0} q5_0 - ./bin/llama-quantize ${model_f16} ${model_q5_1} q5_1 - ./bin/llama-quantize ${model_f16} ${model_q2_k} q2_k - ./bin/llama-quantize ${model_f16} ${model_q3_k} q3_k - ./bin/llama-quantize ${model_f16} ${model_q4_k} q4_k - ./bin/llama-quantize ${model_f16} ${model_q5_k} q5_k - ./bin/llama-quantize ${model_f16} ${model_q6_k} q6_k - - (time ./bin/llama-cli -no-cnv --model ${model_f16} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-cli -no-cnv --model ${model_q8_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_1} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_0} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_1} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-cli -no-cnv --model ${model_q2_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q3_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q4_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q5_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-cli -no-cnv --model ${model_q6_k} -t 1 -ngl 99 -c 0 -s 1234 -n 256 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-perplexity --model ${model_f16} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log - (time ./bin/llama-perplexity --model ${model_q8_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log - (time ./bin/llama-perplexity --model ${model_q4_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log - (time ./bin/llama-perplexity --model ${model_q4_1} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log - (time ./bin/llama-perplexity --model ${model_q5_0} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log - (time ./bin/llama-perplexity --model ${model_q5_1} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log - (time ./bin/llama-perplexity --model ${model_q2_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log - (time ./bin/llama-perplexity --model ${model_q3_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log - (time ./bin/llama-perplexity --model ${model_q4_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log - (time ./bin/llama-perplexity --model ${model_q5_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log - (time ./bin/llama-perplexity --model ${model_q6_k} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log - - (time ./bin/llama-imatrix --model ${model_f16} -f ${wiki_test} -t 1 -ngl 99 -c 2048 -b 512 --chunks 4 ) 2>&1 | tee -a $OUT/${ci}-imatrix.log - - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 0 ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 0 -fa ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log - (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 0 -fa ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log + ./bin/llama-quantize ${model_bf16} ${model_q8_0} q8_0 $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q4_0} q4_0 $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q4_1} q4_1 $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q5_0} q5_0 $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q5_1} q5_1 $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q2_k} q2_k $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q3_k} q3_k $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q4_k} q4_k $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q5_k} q5_k $(nproc) + ./bin/llama-quantize ${model_bf16} ${model_q6_k} q6_k $(nproc) + + (time ./bin/llama-cli -no-cnv --model ${model_f16} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log + (time ./bin/llama-cli -no-cnv --model ${model_bf16} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-bf16.log + (time ./bin/llama-cli -no-cnv --model ${model_q8_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log + (time ./bin/llama-cli -no-cnv --model ${model_q4_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log + (time ./bin/llama-cli -no-cnv --model ${model_q4_1} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log + (time ./bin/llama-cli -no-cnv --model ${model_q5_0} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log + (time ./bin/llama-cli -no-cnv --model ${model_q5_1} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log + (time ./bin/llama-cli -no-cnv --model ${model_q2_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log + (time ./bin/llama-cli -no-cnv --model ${model_q3_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log + (time ./bin/llama-cli -no-cnv --model ${model_q4_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log + (time ./bin/llama-cli -no-cnv --model ${model_q5_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log + (time ./bin/llama-cli -no-cnv --model ${model_q6_k} -ngl 99 -c 1024 -s 1234 -n 64 --ignore-eos -p "I believe the meaning of life is" ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log + + (time ./bin/llama-perplexity --model ${model_f16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-f16.log + if [ -z ${GG_BUILD_NO_BF16} ]; then + (time ./bin/llama-perplexity --model ${model_bf16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-bf16.log + fi + (time ./bin/llama-perplexity --model ${model_q8_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q8_0.log + (time ./bin/llama-perplexity --model ${model_q4_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_0.log + (time ./bin/llama-perplexity --model ${model_q4_1} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_1.log + (time ./bin/llama-perplexity --model ${model_q5_0} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_0.log + (time ./bin/llama-perplexity --model ${model_q5_1} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_1.log + (time ./bin/llama-perplexity --model ${model_q2_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q2_k.log + (time ./bin/llama-perplexity --model ${model_q3_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q3_k.log + (time ./bin/llama-perplexity --model ${model_q4_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q4_k.log + (time ./bin/llama-perplexity --model ${model_q5_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q5_k.log + (time ./bin/llama-perplexity --model ${model_q6_k} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-tg-q6_k.log + + (time ./bin/llama-imatrix --model ${model_f16} -f ${wiki_test} -ngl 99 -c 1024 -b 512 --chunks 2 ) 2>&1 | tee -a $OUT/${ci}-imatrix.log + + (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 1024 -fa off ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log + (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 10 -c 1024 -fa on ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log + (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 1024 -fa off ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log + (time ./bin/llama-save-load-state --model ${model_q4_0} -ngl 99 -c 1024 -fa on ) 2>&1 | tee -a $OUT/${ci}-save-load-state.log function check_ppl { qnt="$1" @@ -663,6 +411,9 @@ function gg_run_pythia_2_8b { } check_ppl "f16" "$(cat $OUT/${ci}-tg-f16.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log + if [ -z ${GG_BUILD_NO_BF16} ]; then + check_ppl "bf16" "$(cat $OUT/${ci}-tg-bf16.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log + fi check_ppl "q8_0" "$(cat $OUT/${ci}-tg-q8_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log check_ppl "q4_0" "$(cat $OUT/${ci}-tg-q4_0.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log check_ppl "q4_1" "$(cat $OUT/${ci}-tg-q4_1.log | grep "^\[1\]")" | tee -a $OUT/${ci}-ppl.log @@ -679,14 +430,17 @@ function gg_run_pythia_2_8b { set +e } -function gg_sum_pythia_2_8b { +function gg_sum_qwen3_0_6b { gg_printf '### %s\n\n' "${ci}" - gg_printf 'Pythia 2.8B:\n' + gg_printf 'Qwen3 0.6B:\n' gg_printf '- status: %s\n' "$(cat $OUT/${ci}.exit)" gg_printf '- perplexity:\n%s\n' "$(cat $OUT/${ci}-ppl.log)" gg_printf '- imatrix:\n```\n%s\n```\n' "$(cat $OUT/${ci}-imatrix-sum.log)" - gg_printf '- f16: \n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-f16.log)" + gg_printf '- f16:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-f16.log)" + if [ -z ${GG_BUILD_NO_BF16} ]; then + gg_printf '- bf16:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-bf16.log)" + fi gg_printf '- q8_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q8_0.log)" gg_printf '- q4_0:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_0.log)" gg_printf '- q4_1:\n```\n%s\n```\n' "$(cat $OUT/${ci}-tg-q4_1.log)" @@ -853,10 +607,7 @@ if [ -z ${GG_BUILD_LOW_PERF} ]; then fi ret=0 -if [ -z ${GG_BUILD_SYCL} ]; then - # SYCL build breaks with debug build flags - test $ret -eq 0 && gg_run ctest_debug -fi +test $ret -eq 0 && gg_run ctest_debug test $ret -eq 0 && gg_run ctest_release if [ -z ${GG_BUILD_LOW_PERF} ]; then @@ -864,24 +615,13 @@ if [ -z ${GG_BUILD_LOW_PERF} ]; then test $ret -eq 0 && gg_run rerank_tiny if [ -z ${GG_BUILD_CLOUD} ] || [ ${GG_BUILD_EXTRA_TESTS_0} ]; then - if [ -z ${GG_BUILD_SYCL} ]; then - test $ret -eq 0 && gg_run test_scripts_debug - fi - test $ret -eq 0 && gg_run test_scripts_release + test $ret -eq 0 && gg_run test_scripts fi - if [ -z ${GG_BUILD_VRAM_GB} ] || [ ${GG_BUILD_VRAM_GB} -ge 8 ]; then - if [ -z ${GG_BUILD_CUDA} ] && [ -z ${GG_BUILD_VULKAN} ]; then - test $ret -eq 0 && gg_run pythia_1_4b - else - test $ret -eq 0 && gg_run pythia_2_8b - #test $ret -eq 0 && gg_run open_llama_7b_v2 - fi - if [ -z ${GG_BUILD_SYCL} ]; then - test $ret -eq 0 && gg_run ctest_with_model_debug - fi - test $ret -eq 0 && gg_run ctest_with_model_release - fi + test $ret -eq 0 && gg_run qwen3_0_6b + + test $ret -eq 0 && gg_run ctest_with_model_debug + test $ret -eq 0 && gg_run ctest_with_model_release fi exit $ret diff -pruN 5882+dfsg-2/cmake/riscv64-spacemit-linux-gnu-gcc.cmake 6641+dfsg-2/cmake/riscv64-spacemit-linux-gnu-gcc.cmake --- 5882+dfsg-2/cmake/riscv64-spacemit-linux-gnu-gcc.cmake 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/cmake/riscv64-spacemit-linux-gnu-gcc.cmake 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,29 @@ +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_PROCESSOR riscv64) +set(CMAKE_SYSTEM_VERSION 1) + +if (CMAKE_HOST_SYSTEM_PROCESSOR MATCHES "^(riscv)") + message(STATUS "HOST SYSTEM ${CMAKE_HOST_SYSTEM_PROCESSOR}") +else() + set(GNU_MACHINE riscv64-unknown-linux-gnu CACHE STRING "GNU compiler triple") + if (DEFINED ENV{RISCV_ROOT_PATH}) + file(TO_CMAKE_PATH $ENV{RISCV_ROOT_PATH} RISCV_ROOT_PATH) + else() + message(FATAL_ERROR "RISCV_ROOT_PATH env must be defined") + endif() + + set(RISCV_ROOT_PATH ${RISCV_ROOT_PATH} CACHE STRING "root path to riscv toolchain") + set(CMAKE_C_COMPILER ${RISCV_ROOT_PATH}/bin/riscv64-unknown-linux-gnu-gcc) + set(CMAKE_CXX_COMPILER ${RISCV_ROOT_PATH}/bin/riscv64-unknown-linux-gnu-g++) + set(CMAKE_STRIP ${RISCV_ROOT_PATH}/bin/riscv64-unknown-linux-gnu-strip) + set(CMAKE_FIND_ROOT_PATH "${RISCV_ROOT_PATH}/riscv64-unknown-linux-gnu") + set(CMAKE_SYSROOT "${RISCV_ROOT_PATH}/sysroot") +endif() + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) +set(CMAKE_C_FLAGS "-march=rv64gcv_zfh_zba_zicbop -mabi=lp64d ${CMAKE_C_FLAGS}") +set(CMAKE_CXX_FLAGS "-march=rv64gcv_zfh_zba_zicbop -mabi=lp64d ${CXX_FLAGS}") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -latomic") diff -pruN 5882+dfsg-2/common/CMakeLists.txt 6641+dfsg-2/common/CMakeLists.txt --- 5882+dfsg-2/common/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -87,7 +87,43 @@ if (LLAMA_CURL) target_compile_definitions(${TARGET} PUBLIC LLAMA_USE_CURL) include_directories(${CURL_INCLUDE_DIRS}) set(LLAMA_COMMON_EXTRA_LIBS ${LLAMA_COMMON_EXTRA_LIBS} ${CURL_LIBRARIES}) -endif () +endif() + +if (LLAMA_OPENSSL) + find_package(OpenSSL) + if (OpenSSL_FOUND) + include(CheckCSourceCompiles) + set(SAVED_CMAKE_REQUIRED_INCLUDES ${CMAKE_REQUIRED_INCLUDES}) + set(CMAKE_REQUIRED_INCLUDES ${OPENSSL_INCLUDE_DIR}) + check_c_source_compiles(" + #include + #if defined(OPENSSL_IS_BORINGSSL) || defined(LIBRESSL_VERSION_NUMBER) + # if OPENSSL_VERSION_NUMBER < 0x1010107f + # error bad version + # endif + #else + # if OPENSSL_VERSION_NUMBER < 0x30000000L + # error bad version + # endif + #endif + int main() { return 0; } + " OPENSSL_VERSION_SUPPORTED) + set(CMAKE_REQUIRED_INCLUDES ${SAVED_CMAKE_REQUIRED_INCLUDES}) + if (OPENSSL_VERSION_SUPPORTED) + message(STATUS "OpenSSL found: ${OPENSSL_VERSION}") + target_compile_definitions(${TARGET} PUBLIC CPPHTTPLIB_OPENSSL_SUPPORT) + target_link_libraries(${TARGET} PUBLIC OpenSSL::SSL OpenSSL::Crypto) + if (APPLE AND CMAKE_SYSTEM_NAME STREQUAL "Darwin") + target_compile_definitions(${TARGET} PUBLIC CPPHTTPLIB_USE_CERTS_FROM_MACOSX_KEYCHAIN) + find_library(CORE_FOUNDATION_FRAMEWORK CoreFoundation REQUIRED) + find_library(SECURITY_FRAMEWORK Security REQUIRED) + target_link_libraries(${TARGET} PUBLIC ${CORE_FOUNDATION_FRAMEWORK} ${SECURITY_FRAMEWORK}) + endif() + endif() + else() + message(STATUS "OpenSSL not found, SSL support disabled") + endif() +endif() if (LLAMA_LLGUIDANCE) include(ExternalProject) diff -pruN 5882+dfsg-2/common/arg.cpp 6641+dfsg-2/common/arg.cpp --- 5882+dfsg-2/common/arg.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/arg.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -35,8 +37,22 @@ #if defined(LLAMA_USE_CURL) #include #include -#include +#else +#include +#endif + +#ifdef __linux__ +#include +#elif defined(_WIN32) +# if !defined(PATH_MAX) +# define PATH_MAX MAX_PATH +# endif +#elif defined(_AIX) +#include +#else +#include #endif +#define LLAMA_MAX_URL_LENGTH 2084 // Maximum URL Length in Chrome: 2083 using json = nlohmann::ordered_json; @@ -56,12 +72,32 @@ static std::string read_file(const std:: } static void write_file(const std::string & fname, const std::string & content) { - std::ofstream file(fname); + const std::string fname_tmp = fname + ".tmp"; + std::ofstream file(fname_tmp); if (!file) { throw std::runtime_error(string_format("error: failed to open file '%s'\n", fname.c_str())); } - file << content; - file.close(); + + try { + file << content; + file.close(); + + // Makes write atomic + if (rename(fname_tmp.c_str(), fname.c_str()) != 0) { + LOG_ERR("%s: unable to rename file: %s to %s\n", __func__, fname_tmp.c_str(), fname.c_str()); + // If rename fails, try to delete the temporary file + if (remove(fname_tmp.c_str()) != 0) { + LOG_ERR("%s: unable to delete temporary file: %s\n", __func__, fname_tmp.c_str()); + } + } + } catch (...) { + // If anything fails, try to delete the temporary file + if (remove(fname_tmp.c_str()) != 0) { + LOG_ERR("%s: unable to delete temporary file: %s\n", __func__, fname_tmp.c_str()); + } + + throw std::runtime_error(string_format("error: failed to write file '%s'\n", fname.c_str())); + } } common_arg & common_arg::set_examples(std::initializer_list examples) { @@ -181,25 +217,59 @@ struct common_hf_file_res { std::string mmprojFile; }; +static void write_etag(const std::string & path, const std::string & etag) { + const std::string etag_path = path + ".etag"; + write_file(etag_path, etag); + LOG_DBG("%s: file etag saved: %s\n", __func__, etag_path.c_str()); +} + +static std::string read_etag(const std::string & path) { + std::string none; + const std::string etag_path = path + ".etag"; + + if (std::filesystem::exists(etag_path)) { + std::ifstream etag_in(etag_path); + if (!etag_in) { + LOG_ERR("%s: could not open .etag file for reading: %s\n", __func__, etag_path.c_str()); + return none; + } + std::string etag; + std::getline(etag_in, etag); + return etag; + } + + // no etag file, but maybe there is an old .json + // remove this code later + const std::string metadata_path = path + ".json"; + + if (std::filesystem::exists(metadata_path)) { + std::ifstream metadata_in(metadata_path); + try { + nlohmann::json metadata_json; + metadata_in >> metadata_json; + LOG_DBG("%s: previous metadata file found %s: %s\n", __func__, metadata_path.c_str(), + metadata_json.dump().c_str()); + if (metadata_json.contains("etag") && metadata_json.at("etag").is_string()) { + std::string etag = metadata_json.at("etag"); + write_etag(path, etag); + if (!std::filesystem::remove(metadata_path)) { + LOG_WRN("%s: failed to delete old .json metadata file: %s\n", __func__, metadata_path.c_str()); + } + return etag; + } + } catch (const nlohmann::json::exception & e) { + LOG_ERR("%s: error reading metadata file %s: %s\n", __func__, metadata_path.c_str(), e.what()); + } + } + return none; +} + #ifdef LLAMA_USE_CURL bool common_has_curl() { return true; } -#ifdef __linux__ -#include -#elif defined(_WIN32) -# if !defined(PATH_MAX) -# define PATH_MAX MAX_PATH -# endif -#elif defined(_AIX) -#include -#else -#include -#endif -#define LLAMA_CURL_MAX_URL_LENGTH 2084 // Maximum URL Length in Chrome: 2083 - // // CURL utils // @@ -216,252 +286,626 @@ struct curl_slist_ptr { } }; -#define CURL_MAX_RETRY 3 -#define CURL_RETRY_DELAY_SECONDS 2 +static CURLcode common_curl_perf(CURL * curl) { + CURLcode res = curl_easy_perform(curl); + if (res != CURLE_OK) { + LOG_ERR("%s: curl_easy_perform() failed\n", __func__); + } + + return res; +} -static bool curl_perform_with_retry(const std::string & url, CURL * curl, int max_attempts, int retry_delay_seconds, const char * method_name) { - int remaining_attempts = max_attempts; +// Send a HEAD request to retrieve the etag and last-modified headers +struct common_load_model_from_url_headers { + std::string etag; + std::string last_modified; + std::string accept_ranges; +}; - while (remaining_attempts > 0) { - LOG_INF("%s: %s %s (attempt %d of %d)...\n", __func__ , method_name, url.c_str(), max_attempts - remaining_attempts + 1, max_attempts); +struct FILE_deleter { + void operator()(FILE * f) const { fclose(f); } +}; - CURLcode res = curl_easy_perform(curl); - if (res == CURLE_OK) { - return true; +static size_t common_header_callback(char * buffer, size_t, size_t n_items, void * userdata) { + common_load_model_from_url_headers * headers = (common_load_model_from_url_headers *) userdata; + static std::regex header_regex("([^:]+): (.*)\r\n"); + static std::regex etag_regex("ETag", std::regex_constants::icase); + static std::regex last_modified_regex("Last-Modified", std::regex_constants::icase); + static std::regex accept_ranges_regex("Accept-Ranges", std::regex_constants::icase); + std::string header(buffer, n_items); + std::smatch match; + if (std::regex_match(header, match, header_regex)) { + const std::string & key = match[1]; + const std::string & value = match[2]; + if (std::regex_match(key, match, etag_regex)) { + headers->etag = value; + } else if (std::regex_match(key, match, last_modified_regex)) { + headers->last_modified = value; + } else if (std::regex_match(key, match, accept_ranges_regex)) { + headers->accept_ranges = value; } + } + + return n_items; +} - int exponential_backoff_delay = std::pow(retry_delay_seconds, max_attempts - remaining_attempts) * 1000; - LOG_WRN("%s: curl_easy_perform() failed: %s, retrying after %d milliseconds...\n", __func__, curl_easy_strerror(res), exponential_backoff_delay); +static size_t common_write_callback(void * data, size_t size, size_t nmemb, void * fd) { + return std::fwrite(data, size, nmemb, static_cast(fd)); +} - remaining_attempts--; - if (remaining_attempts == 0) break; - std::this_thread::sleep_for(std::chrono::milliseconds(exponential_backoff_delay)); +// helper function to hide password in URL +static std::string llama_download_hide_password_in_url(const std::string & url) { + // Use regex to match and replace the user[:password]@ pattern in URLs + // Pattern: scheme://[user[:password]@]host[...] + static const std::regex url_regex(R"(^(?:[A-Za-z][A-Za-z0-9+.-]://)(?:[^/@]+@)?.$)"); + std::smatch match; + + if (std::regex_match(url, match, url_regex)) { + // match[1] = scheme (e.g., "https://") + // match[2] = user[:password]@ part + // match[3] = rest of URL (host and path) + return match[1].str() + "********@" + match[3].str(); } - LOG_ERR("%s: curl_easy_perform() failed after %d attempts\n", __func__, max_attempts); + return url; // No credentials found or malformed URL +} - return false; +static void common_curl_easy_setopt_head(CURL * curl, const std::string & url) { + // Set the URL, allow to follow http redirection + curl_easy_setopt(curl, CURLOPT_URL, url.c_str()); + curl_easy_setopt(curl, CURLOPT_FOLLOWLOCATION, 1L); + +# if defined(_WIN32) + // CURLSSLOPT_NATIVE_CA tells libcurl to use standard certificate store of + // operating system. Currently implemented under MS-Windows. + curl_easy_setopt(curl, CURLOPT_SSL_OPTIONS, CURLSSLOPT_NATIVE_CA); +# endif + + curl_easy_setopt(curl, CURLOPT_NOBODY, 1L); // will trigger the HEAD verb + curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 1L); // hide head request progress + curl_easy_setopt(curl, CURLOPT_HEADERFUNCTION, common_header_callback); } -// download one single file from remote URL to local path -static bool common_download_file_single(const std::string & url, const std::string & path, const std::string & bearer_token, bool offline) { - // Check if the file already exists locally - auto file_exists = std::filesystem::exists(path); - - // If the file exists, check its JSON metadata companion file. - std::string metadata_path = path + ".json"; - nlohmann::json metadata; // TODO @ngxson : get rid of this json, use regex instead - std::string etag; - std::string last_modified; +static void common_curl_easy_setopt_get(CURL * curl) { + curl_easy_setopt(curl, CURLOPT_NOBODY, 0L); + curl_easy_setopt(curl, CURLOPT_WRITEFUNCTION, common_write_callback); - if (file_exists) { - if (offline) { - LOG_INF("%s: using cached file (offline mode): %s\n", __func__, path.c_str()); - return true; // skip verification/downloading - } - // Try and read the JSON metadata file (note: stream autoclosed upon exiting this block). - std::ifstream metadata_in(metadata_path); - if (metadata_in.good()) { - try { - metadata_in >> metadata; - LOG_DBG("%s: previous metadata file found %s: %s\n", __func__, metadata_path.c_str(), metadata.dump().c_str()); - if (metadata.contains("etag") && metadata.at("etag").is_string()) { - etag = metadata.at("etag"); - } - if (metadata.contains("lastModified") && metadata.at("lastModified").is_string()) { - last_modified = metadata.at("lastModified"); - } - } catch (const nlohmann::json::exception & e) { - LOG_ERR("%s: error reading metadata file %s: %s\n", __func__, metadata_path.c_str(), e.what()); - } - } - // if we cannot open the metadata file, we assume that the downloaded file is not valid (etag and last-modified are left empty, so we will download it again) - } else { - if (offline) { - LOG_ERR("%s: required file is not available in cache (offline mode): %s\n", __func__, path.c_str()); - return false; - } - LOG_INF("%s: no previous model file found %s\n", __func__, path.c_str()); + // display download progress + curl_easy_setopt(curl, CURLOPT_NOPROGRESS, 0L); +} + +static bool common_pull_file(CURL * curl, const std::string & path_temporary) { + if (std::filesystem::exists(path_temporary)) { + const std::string partial_size = std::to_string(std::filesystem::file_size(path_temporary)); + LOG_INF("%s: server supports range requests, resuming download from byte %s\n", __func__, partial_size.c_str()); + const std::string range_str = partial_size + "-"; + curl_easy_setopt(curl, CURLOPT_RANGE, range_str.c_str()); } - // Send a HEAD request to retrieve the etag and last-modified headers - struct common_load_model_from_url_headers { - std::string etag; - std::string last_modified; - }; + // Always open file in append mode could be resuming + std::unique_ptr outfile(fopen(path_temporary.c_str(), "ab")); + if (!outfile) { + LOG_ERR("%s: error opening local file for writing: %s\n", __func__, path_temporary.c_str()); + return false; + } - common_load_model_from_url_headers headers; - bool head_request_ok = false; - bool should_download = !file_exists; // by default, we should download if the file does not exist + common_curl_easy_setopt_get(curl); + curl_easy_setopt(curl, CURLOPT_WRITEDATA, outfile.get()); - // Initialize libcurl - curl_ptr curl(curl_easy_init(), &curl_easy_cleanup); - curl_slist_ptr http_headers; + return common_curl_perf(curl) == CURLE_OK; +} + +static bool common_download_head(CURL * curl, + curl_slist_ptr & http_headers, + const std::string & url, + const std::string & bearer_token) { if (!curl) { LOG_ERR("%s: error initializing libcurl\n", __func__); return false; } - // Set the URL, allow to follow http redirection - curl_easy_setopt(curl.get(), CURLOPT_URL, url.c_str()); - curl_easy_setopt(curl.get(), CURLOPT_FOLLOWLOCATION, 1L); - http_headers.ptr = curl_slist_append(http_headers.ptr, "User-Agent: llama-cpp"); // Check if hf-token or bearer-token was specified if (!bearer_token.empty()) { std::string auth_header = "Authorization: Bearer " + bearer_token; - http_headers.ptr = curl_slist_append(http_headers.ptr, auth_header.c_str()); + http_headers.ptr = curl_slist_append(http_headers.ptr, auth_header.c_str()); } - curl_easy_setopt(curl.get(), CURLOPT_HTTPHEADER, http_headers.ptr); + curl_easy_setopt(curl, CURLOPT_HTTPHEADER, http_headers.ptr); + common_curl_easy_setopt_head(curl, url); + return common_curl_perf(curl) == CURLE_OK; +} + +// download one single file from remote URL to local path +static bool common_download_file_single_online(const std::string & url, + const std::string & path, + const std::string & bearer_token) { + static const int max_attempts = 3; + static const int retry_delay_seconds = 2; + for (int i = 0; i < max_attempts; ++i) { + std::string etag; + + // Check if the file already exists locally + const auto file_exists = std::filesystem::exists(path); + if (file_exists) { + etag = read_etag(path); + } else { + LOG_INF("%s: no previous model file found %s\n", __func__, path.c_str()); + } + + bool head_request_ok = false; + bool should_download = !file_exists; // by default, we should download if the file does not exist + + // Initialize libcurl + curl_ptr curl(curl_easy_init(), &curl_easy_cleanup); + common_load_model_from_url_headers headers; + curl_easy_setopt(curl.get(), CURLOPT_HEADERDATA, &headers); + curl_slist_ptr http_headers; + const bool was_perform_successful = common_download_head(curl.get(), http_headers, url, bearer_token); + if (!was_perform_successful) { + head_request_ok = false; + } + + long http_code = 0; + curl_easy_getinfo(curl.get(), CURLINFO_RESPONSE_CODE, &http_code); + if (http_code == 200) { + head_request_ok = true; + } else { + LOG_WRN("%s: HEAD invalid http status code received: %ld\n", __func__, http_code); + head_request_ok = false; + } + + // if head_request_ok is false, we don't have the etag or last-modified headers + // we leave should_download as-is, which is true if the file does not exist + bool should_download_from_scratch = false; + if (head_request_ok) { + // check if ETag or Last-Modified headers are different + // if it is, we need to download the file again + if (!etag.empty() && etag != headers.etag) { + LOG_WRN("%s: ETag header is different (%s != %s): triggering a new download\n", __func__, etag.c_str(), + headers.etag.c_str()); + should_download = true; + should_download_from_scratch = true; + } + } + + const bool accept_ranges_supported = !headers.accept_ranges.empty() && headers.accept_ranges != "none"; + if (should_download) { + if (file_exists && + !accept_ranges_supported) { // Resumable downloads not supported, delete and start again. + LOG_WRN("%s: deleting previous downloaded file: %s\n", __func__, path.c_str()); + if (remove(path.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path.c_str()); + return false; + } + } + + const std::string path_temporary = path + ".downloadInProgress"; + if (should_download_from_scratch) { + if (std::filesystem::exists(path_temporary)) { + if (remove(path_temporary.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path_temporary.c_str()); + return false; + } + } + + if (std::filesystem::exists(path)) { + if (remove(path.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path.c_str()); + return false; + } + } + } + if (head_request_ok) { + write_etag(path, headers.etag); + } + + // start the download + LOG_INF("%s: trying to download model from %s to %s (server_etag:%s, server_last_modified:%s)...\n", + __func__, llama_download_hide_password_in_url(url).c_str(), path_temporary.c_str(), + headers.etag.c_str(), headers.last_modified.c_str()); + const bool was_pull_successful = common_pull_file(curl.get(), path_temporary); + if (!was_pull_successful) { + if (i + 1 < max_attempts) { + const int exponential_backoff_delay = std::pow(retry_delay_seconds, i) * 1000; + LOG_WRN("%s: retrying after %d milliseconds...\n", __func__, exponential_backoff_delay); + std::this_thread::sleep_for(std::chrono::milliseconds(exponential_backoff_delay)); + } else { + LOG_ERR("%s: curl_easy_perform() failed after %d attempts\n", __func__, max_attempts); + } + + continue; + } + + long http_code = 0; + curl_easy_getinfo(curl.get(), CURLINFO_RESPONSE_CODE, &http_code); + if (http_code < 200 || http_code >= 400) { + LOG_ERR("%s: invalid http status code received: %ld\n", __func__, http_code); + return false; + } + + if (rename(path_temporary.c_str(), path.c_str()) != 0) { + LOG_ERR("%s: unable to rename file: %s to %s\n", __func__, path_temporary.c_str(), path.c_str()); + return false; + } + } else { + LOG_INF("%s: using cached file: %s\n", __func__, path.c_str()); + } + + break; + } + + return true; +} + +std::pair> common_remote_get_content(const std::string & url, const common_remote_params & params) { + curl_ptr curl(curl_easy_init(), &curl_easy_cleanup); + curl_slist_ptr http_headers; + std::vector res_buffer; + + curl_easy_setopt(curl.get(), CURLOPT_URL, url.c_str()); + curl_easy_setopt(curl.get(), CURLOPT_NOPROGRESS, 1L); + curl_easy_setopt(curl.get(), CURLOPT_FOLLOWLOCATION, 1L); + curl_easy_setopt(curl.get(), CURLOPT_VERBOSE, 1L); + typedef size_t(*CURLOPT_WRITEFUNCTION_PTR)(void * ptr, size_t size, size_t nmemb, void * data); + auto write_callback = [](void * ptr, size_t size, size_t nmemb, void * data) -> size_t { + auto data_vec = static_cast *>(data); + data_vec->insert(data_vec->end(), (char *)ptr, (char *)ptr + size * nmemb); + return size * nmemb; + }; + curl_easy_setopt(curl.get(), CURLOPT_WRITEFUNCTION, static_cast(write_callback)); + curl_easy_setopt(curl.get(), CURLOPT_WRITEDATA, &res_buffer); #if defined(_WIN32) - // CURLSSLOPT_NATIVE_CA tells libcurl to use standard certificate store of - // operating system. Currently implemented under MS-Windows. curl_easy_setopt(curl.get(), CURLOPT_SSL_OPTIONS, CURLSSLOPT_NATIVE_CA); #endif + if (params.timeout > 0) { + curl_easy_setopt(curl.get(), CURLOPT_TIMEOUT, params.timeout); + } + if (params.max_size > 0) { + curl_easy_setopt(curl.get(), CURLOPT_MAXFILESIZE, params.max_size); + } + http_headers.ptr = curl_slist_append(http_headers.ptr, "User-Agent: llama-cpp"); + for (const auto & header : params.headers) { + http_headers.ptr = curl_slist_append(http_headers.ptr, header.c_str()); + } + curl_easy_setopt(curl.get(), CURLOPT_HTTPHEADER, http_headers.ptr); - typedef size_t(*CURLOPT_HEADERFUNCTION_PTR)(char *, size_t, size_t, void *); - auto header_callback = [](char * buffer, size_t /*size*/, size_t n_items, void * userdata) -> size_t { - common_load_model_from_url_headers * headers = (common_load_model_from_url_headers *) userdata; - - static std::regex header_regex("([^:]+): (.*)\r\n"); - static std::regex etag_regex("ETag", std::regex_constants::icase); - static std::regex last_modified_regex("Last-Modified", std::regex_constants::icase); - - std::string header(buffer, n_items); - std::smatch match; - if (std::regex_match(header, match, header_regex)) { - const std::string & key = match[1]; - const std::string & value = match[2]; - if (std::regex_match(key, match, etag_regex)) { - headers->etag = value; - } else if (std::regex_match(key, match, last_modified_regex)) { - headers->last_modified = value; - } + CURLcode res = curl_easy_perform(curl.get()); + + if (res != CURLE_OK) { + std::string error_msg = curl_easy_strerror(res); + throw std::runtime_error("error: cannot make GET request: " + error_msg); + } + + long res_code; + curl_easy_getinfo(curl.get(), CURLINFO_RESPONSE_CODE, &res_code); + + return { res_code, std::move(res_buffer) }; +} + +#else + +bool common_has_curl() { + return false; +} + +struct common_url { + std::string scheme; + std::string user; + std::string password; + std::string host; + std::string path; +}; + +static common_url parse_url(const std::string & url) { + common_url parts; + auto scheme_end = url.find("://"); + + if (scheme_end == std::string::npos) { + throw std::runtime_error("invalid URL: no scheme"); + } + parts.scheme = url.substr(0, scheme_end); + + if (parts.scheme != "http" && parts.scheme != "https") { + throw std::runtime_error("unsupported URL scheme: " + parts.scheme); + } + + auto rest = url.substr(scheme_end + 3); + auto at_pos = rest.find('@'); + + if (at_pos != std::string::npos) { + auto auth = rest.substr(0, at_pos); + auto colon_pos = auth.find(':'); + if (colon_pos != std::string::npos) { + parts.user = auth.substr(0, colon_pos); + parts.password = auth.substr(colon_pos + 1); + } else { + parts.user = auth; } - return n_items; - }; + rest = rest.substr(at_pos + 1); + } + + auto slash_pos = rest.find('/'); - curl_easy_setopt(curl.get(), CURLOPT_NOBODY, 1L); // will trigger the HEAD verb - curl_easy_setopt(curl.get(), CURLOPT_NOPROGRESS, 1L); // hide head request progress - curl_easy_setopt(curl.get(), CURLOPT_HEADERFUNCTION, static_cast(header_callback)); - curl_easy_setopt(curl.get(), CURLOPT_HEADERDATA, &headers); - - // we only allow retrying once for HEAD requests - // this is for the use case of using running offline (no internet), retrying can be annoying - bool was_perform_successful = curl_perform_with_retry(url, curl.get(), 1, 0, "HEAD"); - if (!was_perform_successful) { - head_request_ok = false; - } - - long http_code = 0; - curl_easy_getinfo(curl.get(), CURLINFO_RESPONSE_CODE, &http_code); - if (http_code == 200) { - head_request_ok = true; + if (slash_pos != std::string::npos) { + parts.host = rest.substr(0, slash_pos); + parts.path = rest.substr(slash_pos); } else { - LOG_WRN("%s: HEAD invalid http status code received: %ld\n", __func__, http_code); - head_request_ok = false; + parts.host = rest; + parts.path = "/"; } + return parts; +} - // if head_request_ok is false, we don't have the etag or last-modified headers - // we leave should_download as-is, which is true if the file does not exist - if (head_request_ok) { - // check if ETag or Last-Modified headers are different - // if it is, we need to download the file again - if (!etag.empty() && etag != headers.etag) { - LOG_WRN("%s: ETag header is different (%s != %s): triggering a new download\n", __func__, etag.c_str(), headers.etag.c_str()); - should_download = true; - } else if (!last_modified.empty() && last_modified != headers.last_modified) { - LOG_WRN("%s: Last-Modified header is different (%s != %s): triggering a new download\n", __func__, last_modified.c_str(), headers.last_modified.c_str()); - should_download = true; - } +static std::pair http_client(const std::string & url) { + common_url parts = parse_url(url); + + if (parts.host.empty()) { + throw std::runtime_error("error: invalid URL format"); } - if (should_download) { - std::string path_temporary = path + ".downloadInProgress"; - if (file_exists) { - LOG_WRN("%s: deleting previous downloaded file: %s\n", __func__, path.c_str()); - if (remove(path.c_str()) != 0) { - LOG_ERR("%s: unable to delete file: %s\n", __func__, path.c_str()); + if (!parts.user.empty()) { + throw std::runtime_error("error: user:password@ not supported yet"); // TODO + } + + httplib::Client cli(parts.scheme + "://" + parts.host); + cli.set_follow_location(true); + + // TODO cert + + return { std::move(cli), std::move(parts) }; +} + +static std::string show_masked_url(const common_url & parts) { + return parts.scheme + "://" + (parts.user.empty() ? "" : "****:****@") + parts.host + parts.path; +} + +static void print_progress(size_t current, size_t total) { // TODO isatty + if (!total) { + return; + } + + size_t width = 50; + size_t pct = (100 * current) / total; + size_t pos = (width * current) / total; + + std::cout << "[" + << std::string(pos, '=') + << (pos < width ? ">" : "") + << std::string(width - pos, ' ') + << "] " << std::setw(3) << pct << "% (" + << current / (1024 * 1024) << " MB / " + << total / (1024 * 1024) << " MB)\r"; + std::cout.flush(); +} + +static bool common_pull_file(httplib::Client & cli, + const std::string & resolve_path, + const std::string & path_tmp, + bool supports_ranges, + size_t existing_size, + size_t & total_size) { + std::ofstream ofs(path_tmp, std::ios::binary | std::ios::app); + if (!ofs.is_open()) { + LOG_ERR("%s: error opening local file for writing: %s\n", __func__, path_tmp.c_str()); + return false; + } + + httplib::Headers headers; + if (supports_ranges && existing_size > 0) { + headers.emplace("Range", "bytes=" + std::to_string(existing_size) + "-"); + } + + std::atomic downloaded{existing_size}; + + auto res = cli.Get(resolve_path, headers, + [&](const httplib::Response &response) { + if (existing_size > 0 && response.status != 206) { + LOG_WRN("%s: server did not respond with 206 Partial Content for a resume request. Status: %d\n", __func__, response.status); return false; } - } + if (existing_size == 0 && response.status != 200) { + LOG_WRN("%s: download received non-successful status code: %d\n", __func__, response.status); + return false; + } + if (total_size == 0 && response.has_header("Content-Length")) { + try { + size_t content_length = std::stoull(response.get_header_value("Content-Length")); + total_size = existing_size + content_length; + } catch (const std::exception &e) { + LOG_WRN("%s: invalid Content-Length header: %s\n", __func__, e.what()); + } + } + return true; + }, + [&](const char *data, size_t len) { + ofs.write(data, len); + if (!ofs) { + LOG_ERR("%s: error writing to file: %s\n", __func__, path_tmp.c_str()); + return false; + } + downloaded += len; + print_progress(downloaded, total_size); + return true; + }, + nullptr + ); + + std::cout << "\n"; + + if (!res) { + LOG_ERR("%s: error during download. Status: %d\n", __func__, res ? res->status : -1); + return false; + } + + return true; +} + +// download one single file from remote URL to local path +static bool common_download_file_single_online(const std::string & url, + const std::string & path, + const std::string & bearer_token) { + static const int max_attempts = 3; + static const int retry_delay_seconds = 2; + + auto [cli, parts] = http_client(url); + + httplib::Headers default_headers = {{"User-Agent", "llama-cpp"}}; + if (!bearer_token.empty()) { + default_headers.insert({"Authorization", "Bearer " + bearer_token}); + } + cli.set_default_headers(default_headers); + + const bool file_exists = std::filesystem::exists(path); - // Set the output file + std::string last_etag; + if (file_exists) { + last_etag = read_etag(path); + } else { + LOG_INF("%s: no previous model file found %s\n", __func__, path.c_str()); + } - struct FILE_deleter { - void operator()(FILE * f) const { - fclose(f); + for (int i = 0; i < max_attempts; ++i) { + auto head = cli.Head(parts.path); + bool head_ok = head && head->status >= 200 && head->status < 300; + if (!head_ok) { + LOG_WRN("%s: HEAD invalid http status code received: %d\n", __func__, head ? head->status : -1); + if (file_exists) { + LOG_INF("%s: Using cached file (HEAD failed): %s\n", __func__, path.c_str()); + return true; } - }; + } - std::unique_ptr outfile(fopen(path_temporary.c_str(), "wb")); - if (!outfile) { - LOG_ERR("%s: error opening local file for writing: %s\n", __func__, path.c_str()); - return false; + std::string etag; + if (head_ok && head->has_header("ETag")) { + etag = head->get_header_value("ETag"); } - typedef size_t(*CURLOPT_WRITEFUNCTION_PTR)(void * data, size_t size, size_t nmemb, void * fd); - auto write_callback = [](void * data, size_t size, size_t nmemb, void * fd) -> size_t { - return fwrite(data, size, nmemb, (FILE *)fd); - }; - curl_easy_setopt(curl.get(), CURLOPT_NOBODY, 0L); - curl_easy_setopt(curl.get(), CURLOPT_WRITEFUNCTION, static_cast(write_callback)); - curl_easy_setopt(curl.get(), CURLOPT_WRITEDATA, outfile.get()); + size_t total_size = 0; + if (head_ok && head->has_header("Content-Length")) { + try { + total_size = std::stoull(head->get_header_value("Content-Length")); + } catch (const std::exception& e) { + LOG_WRN("%s: Invalid Content-Length in HEAD response: %s\n", __func__, e.what()); + } + } - // display download progress - curl_easy_setopt(curl.get(), CURLOPT_NOPROGRESS, 0L); + bool supports_ranges = false; + if (head_ok && head->has_header("Accept-Ranges")) { + supports_ranges = head->get_header_value("Accept-Ranges") != "none"; + } - // helper function to hide password in URL - auto llama_download_hide_password_in_url = [](const std::string & url) -> std::string { - std::size_t protocol_pos = url.find("://"); - if (protocol_pos == std::string::npos) { - return url; // Malformed URL - } + bool should_download_from_scratch = false; + if (!last_etag.empty() && !etag.empty() && last_etag != etag) { + LOG_WRN("%s: ETag header is different (%s != %s): triggering a new download\n", __func__, + last_etag.c_str(), etag.c_str()); + should_download_from_scratch = true; + } - std::size_t at_pos = url.find('@', protocol_pos + 3); - if (at_pos == std::string::npos) { - return url; // No password in URL + if (file_exists) { + if (!should_download_from_scratch) { + LOG_INF("%s: using cached file: %s\n", __func__, path.c_str()); + return true; + } + LOG_WRN("%s: deleting previous downloaded file: %s\n", __func__, path.c_str()); + if (remove(path.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path.c_str()); + return false; } + } - return url.substr(0, protocol_pos + 3) + "********" + url.substr(at_pos); - }; + const std::string path_temporary = path + ".downloadInProgress"; + size_t existing_size = 0; + + if (std::filesystem::exists(path_temporary)) { + if (supports_ranges && !should_download_from_scratch) { + existing_size = std::filesystem::file_size(path_temporary); + } else if (remove(path_temporary.c_str()) != 0) { + LOG_ERR("%s: unable to delete file: %s\n", __func__, path_temporary.c_str()); + return false; + } + } // start the download - LOG_INF("%s: trying to download model from %s to %s (server_etag:%s, server_last_modified:%s)...\n", __func__, - llama_download_hide_password_in_url(url).c_str(), path.c_str(), headers.etag.c_str(), headers.last_modified.c_str()); - bool was_perform_successful = curl_perform_with_retry(url, curl.get(), CURL_MAX_RETRY, CURL_RETRY_DELAY_SECONDS, "GET"); - if (!was_perform_successful) { - return false; + LOG_INF("%s: trying to download model from %s to %s (etag:%s)...\n", + __func__, show_masked_url(parts).c_str(), path_temporary.c_str(), etag.c_str()); + const bool was_pull_successful = common_pull_file(cli, parts.path, path_temporary, supports_ranges, existing_size, total_size); + if (!was_pull_successful) { + if (i + 1 < max_attempts) { + const int exponential_backoff_delay = std::pow(retry_delay_seconds, i) * 1000; + LOG_WRN("%s: retrying after %d milliseconds...\n", __func__, exponential_backoff_delay); + std::this_thread::sleep_for(std::chrono::milliseconds(exponential_backoff_delay)); + } else { + LOG_ERR("%s: download failed after %d attempts\n", __func__, max_attempts); + } + continue; } - long http_code = 0; - curl_easy_getinfo (curl.get(), CURLINFO_RESPONSE_CODE, &http_code); - if (http_code < 200 || http_code >= 400) { - LOG_ERR("%s: invalid http status code received: %ld\n", __func__, http_code); + if (std::rename(path_temporary.c_str(), path.c_str()) != 0) { + LOG_ERR("%s: unable to rename file: %s to %s\n", __func__, path_temporary.c_str(), path.c_str()); return false; } + if (!etag.empty()) { + write_etag(path, etag); + } + break; + } - // Causes file to be closed explicitly here before we rename it. - outfile.reset(); + return true; +} - // Write the updated JSON metadata file. - metadata.update({ - {"url", url}, - {"etag", headers.etag}, - {"lastModified", headers.last_modified} - }); - write_file(metadata_path, metadata.dump(4)); - LOG_DBG("%s: file metadata saved: %s\n", __func__, metadata_path.c_str()); +std::pair> common_remote_get_content(const std::string & url, + const common_remote_params & params) { + auto [cli, parts] = http_client(url); - if (rename(path_temporary.c_str(), path.c_str()) != 0) { - LOG_ERR("%s: unable to rename file: %s to %s\n", __func__, path_temporary.c_str(), path.c_str()); - return false; + httplib::Headers headers = {{"User-Agent", "llama-cpp"}}; + for (const auto & header : params.headers) { + size_t pos = header.find(':'); + if (pos != std::string::npos) { + headers.emplace(header.substr(0, pos), header.substr(pos + 1)); + } else { + headers.emplace(header, ""); } - } else { - LOG_INF("%s: using cached file: %s\n", __func__, path.c_str()); } + if (params.timeout > 0) { + cli.set_read_timeout(params.timeout, 0); + cli.set_write_timeout(params.timeout, 0); + } + + std::vector buf; + auto res = cli.Get(parts.path, headers, + [&](const char *data, size_t len) { + buf.insert(buf.end(), data, data + len); + return params.max_size == 0 || + buf.size() <= static_cast(params.max_size); + }, + nullptr + ); + + if (!res) { + throw std::runtime_error("error: cannot make GET request"); + } + + return { res->status, std::move(buf) }; +} + +#endif // LLAMA_USE_CURL + +static bool common_download_file_single(const std::string & url, + const std::string & path, + const std::string & bearer_token, + bool offline) { + if (!offline) { + return common_download_file_single_online(url, path, bearer_token); + } + + if (!std::filesystem::exists(path)) { + LOG_ERR("%s: required file is not available in cache (offline mode): %s\n", __func__, path.c_str()); + return false; + } + + LOG_INF("%s: using cached file (offline mode): %s\n", __func__, path.c_str()); return true; } @@ -523,7 +967,7 @@ static bool common_download_model( if (n_split > 1) { char split_prefix[PATH_MAX] = {0}; - char split_url_prefix[LLAMA_CURL_MAX_URL_LENGTH] = {0}; + char split_url_prefix[LLAMA_MAX_URL_LENGTH] = {0}; // Verify the first split file format // and extract split URL and PATH prefixes @@ -544,7 +988,7 @@ static bool common_download_model( char split_path[PATH_MAX] = {0}; llama_split_path(split_path, sizeof(split_path), split_prefix, idx, n_split); - char split_url[LLAMA_CURL_MAX_URL_LENGTH] = {0}; + char split_url[LLAMA_MAX_URL_LENGTH] = {0}; llama_split_path(split_url, sizeof(split_url), split_url_prefix, idx, n_split); if (std::string(split_path) == model.path) { @@ -561,50 +1005,6 @@ static bool common_download_model( return true; } -std::pair> common_remote_get_content(const std::string & url, const common_remote_params & params) { - curl_ptr curl(curl_easy_init(), &curl_easy_cleanup); - curl_slist_ptr http_headers; - std::vector res_buffer; - - curl_easy_setopt(curl.get(), CURLOPT_URL, url.c_str()); - curl_easy_setopt(curl.get(), CURLOPT_NOPROGRESS, 1L); - curl_easy_setopt(curl.get(), CURLOPT_FOLLOWLOCATION, 1L); - typedef size_t(*CURLOPT_WRITEFUNCTION_PTR)(void * ptr, size_t size, size_t nmemb, void * data); - auto write_callback = [](void * ptr, size_t size, size_t nmemb, void * data) -> size_t { - auto data_vec = static_cast *>(data); - data_vec->insert(data_vec->end(), (char *)ptr, (char *)ptr + size * nmemb); - return size * nmemb; - }; - curl_easy_setopt(curl.get(), CURLOPT_WRITEFUNCTION, static_cast(write_callback)); - curl_easy_setopt(curl.get(), CURLOPT_WRITEDATA, &res_buffer); -#if defined(_WIN32) - curl_easy_setopt(curl.get(), CURLOPT_SSL_OPTIONS, CURLSSLOPT_NATIVE_CA); -#endif - if (params.timeout > 0) { - curl_easy_setopt(curl.get(), CURLOPT_TIMEOUT, params.timeout); - } - if (params.max_size > 0) { - curl_easy_setopt(curl.get(), CURLOPT_MAXFILESIZE, params.max_size); - } - http_headers.ptr = curl_slist_append(http_headers.ptr, "User-Agent: llama-cpp"); - for (const auto & header : params.headers) { - http_headers.ptr = curl_slist_append(http_headers.ptr, header.c_str()); - } - curl_easy_setopt(curl.get(), CURLOPT_HTTPHEADER, http_headers.ptr); - - CURLcode res = curl_easy_perform(curl.get()); - - if (res != CURLE_OK) { - std::string error_msg = curl_easy_strerror(res); - throw std::runtime_error("error: cannot make GET request: " + error_msg); - } - - long res_code; - curl_easy_getinfo(curl.get(), CURLINFO_RESPONSE_CODE, &res_code); - - return { res_code, std::move(res_buffer) }; -} - /** * Allow getting the HF file from the HF repo with tag (like ollama), for example: * - bartowski/Llama-3.2-3B-Instruct-GGUF:q4 @@ -671,21 +1071,17 @@ static struct common_hf_file_res common_ std::string mmprojFile; if (res_code == 200 || res_code == 304) { - // extract ggufFile.rfilename in json, using regex - { - std::regex pattern("\"ggufFile\"[\\s\\S]*?\"rfilename\"\\s*:\\s*\"([^\"]+)\""); - std::smatch match; - if (std::regex_search(res_str, match, pattern)) { - ggufFile = match[1].str(); + try { + auto j = json::parse(res_str); + + if (j.contains("ggufFile") && j["ggufFile"].contains("rfilename")) { + ggufFile = j["ggufFile"]["rfilename"].get(); } - } - // extract mmprojFile.rfilename in json, using regex - { - std::regex pattern("\"mmprojFile\"[\\s\\S]*?\"rfilename\"\\s*:\\s*\"([^\"]+)\""); - std::smatch match; - if (std::regex_search(res_str, match, pattern)) { - mmprojFile = match[1].str(); + if (j.contains("mmprojFile") && j["mmprojFile"].contains("rfilename")) { + mmprojFile = j["mmprojFile"]["rfilename"].get(); } + } catch (const std::exception & e) { + throw std::runtime_error(std::string("error parsing manifest JSON: ") + e.what()); } if (!use_cache) { // if not using cached response, update the cache file @@ -705,49 +1101,161 @@ static struct common_hf_file_res common_ return { hf_repo, ggufFile, mmprojFile }; } -#else +// +// Docker registry functions +// -bool common_has_curl() { - return false; -} +static std::string common_docker_get_token(const std::string & repo) { + std::string url = "https://auth.docker.io/token?service=registry.docker.io&scope=repository:" + repo + ":pull"; -static bool common_download_file_single(const std::string &, const std::string &, const std::string &, bool) { - LOG_ERR("error: built without CURL, cannot download model from internet\n"); - return false; -} + common_remote_params params; + auto res = common_remote_get_content(url, params); -static bool common_download_file_multiple(const std::vector> &, const std::string &, bool) { - LOG_ERR("error: built without CURL, cannot download model from the internet\n"); - return false; -} + if (res.first != 200) { + throw std::runtime_error("Failed to get Docker registry token, HTTP code: " + std::to_string(res.first)); + } -static bool common_download_model( - const common_params_model &, - const std::string &, - bool) { - LOG_ERR("error: built without CURL, cannot download model from the internet\n"); - return false; -} + std::string response_str(res.second.begin(), res.second.end()); + nlohmann::ordered_json response = nlohmann::ordered_json::parse(response_str); + + if (!response.contains("token")) { + throw std::runtime_error("Docker registry token response missing 'token' field"); + } -static struct common_hf_file_res common_get_hf_file(const std::string &, const std::string &, bool) { - LOG_ERR("error: built without CURL, cannot download model from the internet\n"); - return {}; + return response["token"].get(); } -std::pair> common_remote_get_content(const std::string & url, const common_remote_params &) { - if (!url.empty()) { - throw std::runtime_error("error: built without CURL, cannot download model from the internet"); +static std::string common_docker_resolve_model(const std::string & docker) { + // Parse ai/smollm2:135M-Q4_0 + size_t colon_pos = docker.find(':'); + std::string repo, tag; + if (colon_pos != std::string::npos) { + repo = docker.substr(0, colon_pos); + tag = docker.substr(colon_pos + 1); + } else { + repo = docker; + tag = "latest"; + } + + // ai/ is the default + size_t slash_pos = docker.find('/'); + if (slash_pos == std::string::npos) { + repo.insert(0, "ai/"); } - return {}; -} + LOG_INF("%s: Downloading Docker Model: %s:%s\n", __func__, repo.c_str(), tag.c_str()); + try { + // --- helper: digest validation --- + auto validate_oci_digest = [](const std::string & digest) -> std::string { + // Expected: algo:hex ; start with sha256 (64 hex chars) + // You can extend this map if supporting other algorithms in future. + static const std::regex re("^sha256:([a-fA-F0-9]{64})$"); + std::smatch m; + if (!std::regex_match(digest, m, re)) { + throw std::runtime_error("Invalid OCI digest format received in manifest: " + digest); + } + // normalize hex to lowercase + std::string normalized = digest; + std::transform(normalized.begin()+7, normalized.end(), normalized.begin()+7, [](unsigned char c){ + return std::tolower(c); + }); + return normalized; + }; -#endif // LLAMA_USE_CURL + std::string token = common_docker_get_token(repo); // Get authentication token + + // Get manifest + const std::string url_prefix = "https://registry-1.docker.io/v2/" + repo; + std::string manifest_url = url_prefix + "/manifests/" + tag; + common_remote_params manifest_params; + manifest_params.headers.push_back("Authorization: Bearer " + token); + manifest_params.headers.push_back( + "Accept: application/vnd.docker.distribution.manifest.v2+json,application/vnd.oci.image.manifest.v1+json"); + auto manifest_res = common_remote_get_content(manifest_url, manifest_params); + if (manifest_res.first != 200) { + throw std::runtime_error("Failed to get Docker manifest, HTTP code: " + std::to_string(manifest_res.first)); + } + + std::string manifest_str(manifest_res.second.begin(), manifest_res.second.end()); + nlohmann::ordered_json manifest = nlohmann::ordered_json::parse(manifest_str); + std::string gguf_digest; // Find the GGUF layer + if (manifest.contains("layers")) { + for (const auto & layer : manifest["layers"]) { + if (layer.contains("mediaType")) { + std::string media_type = layer["mediaType"].get(); + if (media_type == "application/vnd.docker.ai.gguf.v3" || + media_type.find("gguf") != std::string::npos) { + gguf_digest = layer["digest"].get(); + break; + } + } + } + } + + if (gguf_digest.empty()) { + throw std::runtime_error("No GGUF layer found in Docker manifest"); + } + + // Validate & normalize digest + gguf_digest = validate_oci_digest(gguf_digest); + LOG_DBG("%s: Using validated digest: %s\n", __func__, gguf_digest.c_str()); + + // Prepare local filename + std::string model_filename = repo; + std::replace(model_filename.begin(), model_filename.end(), '/', '_'); + model_filename += "_" + tag + ".gguf"; + std::string local_path = fs_get_cache_file(model_filename); + + const std::string blob_url = url_prefix + "/blobs/" + gguf_digest; + if (!common_download_file_single(blob_url, local_path, token, false)) { + throw std::runtime_error("Failed to download Docker Model"); + } + + LOG_INF("%s: Downloaded Docker Model to: %s\n", __func__, local_path.c_str()); + return local_path; + } catch (const std::exception & e) { + LOG_ERR("%s: Docker Model download failed: %s\n", __func__, e.what()); + throw; + } +} // // utils // +// Helper function to parse tensor buffer override strings +static void parse_tensor_buffer_overrides(const std::string & value, std::vector & overrides) { + std::map buft_list; + for (size_t i = 0; i < ggml_backend_dev_count(); ++i) { + auto * dev = ggml_backend_dev_get(i); + auto * buft = ggml_backend_dev_buffer_type(dev); + if (buft) { + buft_list[ggml_backend_buft_name(buft)] = buft; + } + } + + for (const auto & override : string_split(value, ',')) { + std::string::size_type pos = override.find('='); + if (pos == std::string::npos) { + throw std::invalid_argument("invalid value"); + } + std::string tensor_name = override.substr(0, pos); + std::string buffer_type = override.substr(pos + 1); + + if (buft_list.find(buffer_type) == buft_list.end()) { + printf("Available buffer types:\n"); + for (const auto & it : buft_list) { + printf(" %s\n", ggml_backend_buft_name(it.second)); + } + throw std::invalid_argument("unknown buffer type"); + } + // keep strings alive and avoid leaking memory by storing them in a static vector + static std::list buft_overrides; + buft_overrides.push_back(tensor_name); + overrides.push_back({buft_overrides.back().c_str(), buft_list.at(buffer_type)}); + } +} + struct handle_model_result { bool found_mmproj = false; common_params_model mmproj; @@ -761,7 +1269,9 @@ static handle_model_result common_params handle_model_result result; // handle pre-fill default model path and url based on hf_repo and hf_file { - if (!model.hf_repo.empty()) { + if (!model.docker_repo.empty()) { // Handle Docker URLs by resolving them to local paths + model.path = common_docker_resolve_model(model.docker_repo); + } else if (!model.hf_repo.empty()) { // short-hand to avoid specifying --hf-file -> default it to --model if (model.hf_file.empty()) { if (model.path.empty()) { @@ -850,8 +1360,6 @@ static std::string get_all_kv_cache_type // static bool common_params_parse_ex(int argc, char ** argv, common_params_context & ctx_arg) { - std::string arg; - const std::string arg_prefix = "--"; common_params & params = ctx_arg.params; std::unordered_map arg_to_options; @@ -977,6 +1485,10 @@ static bool common_params_parse_ex(int a for (auto & seq_breaker : params.sampling.dry_sequence_breakers) { string_process_escapes(seq_breaker); } + for (auto & pair : params.speculative.replacements) { + string_process_escapes(pair.first); + string_process_escapes(pair.second); + } } if (!params.kv_overrides.empty()) { @@ -988,6 +1500,10 @@ static bool common_params_parse_ex(int a params.tensor_buft_overrides.push_back({nullptr, nullptr}); } + if (!params.speculative.tensor_buft_overrides.empty()) { + params.speculative.tensor_buft_overrides.push_back({nullptr, nullptr}); + } + if (!params.chat_template.empty() && !common_chat_verify_template(params.chat_template, params.use_jinja)) { throw std::runtime_error(string_format( "error: the supplied chat template is not supported: %s%s\n", @@ -1064,7 +1580,7 @@ static void common_params_print_completi printf("\"\n\n"); printf(" case \"$prev\" in\n"); - printf(" --model)\n"); + printf(" --model|-m)\n"); printf(" COMPREPLY=( $(compgen -f -X '!*.gguf' -- \"$cur\") $(compgen -d -- \"$cur\") )\n"); printf(" return 0\n"); printf(" ;;\n"); @@ -1142,7 +1658,7 @@ static std::vector p } else { for (const auto & device : dev_names) { auto * dev = ggml_backend_dev_by_name(device.c_str()); - if (!dev || ggml_backend_dev_type(dev) != GGML_BACKEND_DEVICE_TYPE_GPU) { + if (!dev || ggml_backend_dev_type(dev) == GGML_BACKEND_DEVICE_TYPE_CPU) { throw std::invalid_argument(string_format("invalid device: %s", device.c_str())); } devices.push_back(dev); @@ -1152,7 +1668,7 @@ static std::vector p return devices; } -static void add_rpc_devices(std::string servers) { +static void add_rpc_devices(const std::string & servers) { auto rpc_servers = string_split(servers, ','); if (rpc_servers.empty()) { throw std::invalid_argument("no RPC servers specified"); @@ -1196,6 +1712,7 @@ bool common_params_parse(int argc, char common_params_print_completion(ctx_arg); exit(0); } + params.lr.init(); } catch (const std::invalid_argument & ex) { fprintf(stderr, "%s\n", ex.what()); ctx_arg.params = params_org; @@ -1220,6 +1737,18 @@ static std::string list_builtin_chat_tem return msg.str(); } +static bool is_truthy(const std::string & value) { + return value == "on" || value == "enabled" || value == "1"; +} + +static bool is_falsey(const std::string & value) { + return value == "off" || value == "disabled" || value == "0"; +} + +static bool is_autoy(const std::string & value) { + return value == "auto" || value == "-1"; +} + common_params_context common_params_parser_init(common_params & params, llama_example ex, void(*print_usage)(int, char **)) { // load dynamic backends ggml_backend_load_all(); @@ -1465,6 +1994,22 @@ common_params_context common_params_pars } ).set_env("LLAMA_ARG_SWA_FULL")); add_opt(common_arg( + {"--swa-checkpoints"}, "N", + string_format("max number of SWA checkpoints per slot to create (default: %d)\n" + "[(more info)](https://github.com/ggml-org/llama.cpp/pull/15293)", params.n_swa_checkpoints), + [](common_params & params, int value) { + params.n_swa_checkpoints = value; + } + ).set_env("LLAMA_ARG_SWA_CHECKPOINTS").set_examples({LLAMA_EXAMPLE_SERVER})); + add_opt(common_arg( + {"--kv-unified", "-kvu"}, + string_format("use single unified KV buffer for the KV cache of all sequences (default: %s)\n" + "[(more info)](https://github.com/ggml-org/llama.cpp/pull/14363)", params.kv_unified ? "true" : "false"), + [](common_params & params) { + params.kv_unified = true; + } + ).set_env("LLAMA_ARG_KV_SPLIT")); + add_opt(common_arg( {"--no-context-shift"}, string_format("disables context shift on infinite text generation (default: %s)", params.ctx_shift ? "disabled" : "enabled"), [](common_params & params) { @@ -1472,19 +2017,34 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_PERPLEXITY}).set_env("LLAMA_ARG_NO_CONTEXT_SHIFT")); add_opt(common_arg( + {"--context-shift"}, + string_format("enables context shift on infinite text generation (default: %s)", params.ctx_shift ? "enabled" : "disabled"), + [](common_params & params) { + params.ctx_shift = true; + } + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_PERPLEXITY}).set_env("LLAMA_ARG_CONTEXT_SHIFT")); + add_opt(common_arg( {"--chunks"}, "N", string_format("max number of chunks to process (default: %d, -1 = all)", params.n_chunks), [](common_params & params, int value) { params.n_chunks = value; } ).set_examples({LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_PERPLEXITY, LLAMA_EXAMPLE_RETRIEVAL})); - add_opt(common_arg( - {"-fa", "--flash-attn"}, - string_format("enable Flash Attention (default: %s)", params.flash_attn ? "enabled" : "disabled"), - [](common_params & params) { - params.flash_attn = true; - } - ).set_env("LLAMA_ARG_FLASH_ATTN")); + add_opt(common_arg({ "-fa", "--flash-attn" }, "[on|off|auto]", + string_format("set Flash Attention use ('on', 'off', or 'auto', default: '%s')", + llama_flash_attn_type_name(params.flash_attn_type)), + [](common_params & params, const std::string & value) { + if (is_truthy(value)) { + params.flash_attn_type = LLAMA_FLASH_ATTN_TYPE_ENABLED; + } else if (is_falsey(value)) { + params.flash_attn_type = LLAMA_FLASH_ATTN_TYPE_DISABLED; + } else if (is_autoy(value)) { + params.flash_attn_type = LLAMA_FLASH_ATTN_TYPE_AUTO; + } else { + throw std::runtime_error( + string_format("error: unkown value for --flash-attn: '%s'\n", value.c_str())); + } + }).set_env("LLAMA_ARG_FLASH_ATTN")); add_opt(common_arg( {"-p", "--prompt"}, "PROMPT", "prompt to start generation with; for system message, use -sys", @@ -1498,7 +2058,7 @@ common_params_context common_params_pars [](common_params & params, const std::string & value) { params.system_prompt = value; } - ).set_examples({LLAMA_EXAMPLE_MAIN})); + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_DIFFUSION})); add_opt(common_arg( {"--no-perf"}, string_format("disable internal libllama performance timings (default: %s)", params.no_perf ? "true" : "false"), @@ -1604,7 +2164,7 @@ common_params_context common_params_pars [](common_params & params, const std::string & value) { params.antiprompt.emplace_back(value); } - ).set_examples({LLAMA_EXAMPLE_MAIN})); + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-sp", "--special"}, string_format("special tokens output enabled (default: %s)", params.special ? "true" : "false"), @@ -1689,7 +2249,7 @@ common_params_context common_params_pars [](common_params & params) { params.warmup = false; } - ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_EMBEDDING, LLAMA_EXAMPLE_RETRIEVAL})); + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_EMBEDDING, LLAMA_EXAMPLE_RETRIEVAL, LLAMA_EXAMPLE_PERPLEXITY})); add_opt(common_arg( {"--spm-infill"}, string_format( @@ -1764,7 +2324,7 @@ common_params_context common_params_pars [](common_params & params, const std::string & value) { params.sampling.top_n_sigma = std::stof(value); } - ).set_examples({LLAMA_EXAMPLE_MAIN}).set_sparam()); + ).set_sparam()); add_opt(common_arg( {"--xtc-probability"}, "N", string_format("xtc probability (default: %.1f, 0.0 = disabled)", (double)params.sampling.xtc_probability), @@ -2084,6 +2644,13 @@ common_params_context common_params_pars } ).set_env("LLAMA_ARG_NO_KV_OFFLOAD")); add_opt(common_arg( + {"-nr", "--no-repack"}, + "disable weight repacking", + [](common_params & params) { + params.no_extra_bufts = true; + } + ).set_env("LLAMA_ARG_NO_REPACK")); + add_opt(common_arg( {"-ctk", "--cache-type-k"}, "TYPE", string_format( "KV cache data type for K\n" @@ -2181,9 +2748,11 @@ common_params_context common_params_pars ).set_examples({LLAMA_EXAMPLE_PERPLEXITY})); add_opt(common_arg( {"-dt", "--defrag-thold"}, "N", - string_format("KV cache defragmentation threshold (default: %.1f, < 0 - disabled)", (double)params.defrag_thold), + string_format("KV cache defragmentation threshold (DEPRECATED)"), [](common_params & params, const std::string & value) { - params.defrag_thold = std::stof(value); + GGML_UNUSED(params); + GGML_UNUSED(value); + LOG_WRN("DEPRECATED: --defrag-thold is deprecated and no longer necessary to specify\n"); } ).set_env("LLAMA_ARG_DEFRAG_THOLD")); add_opt(common_arg( @@ -2301,24 +2870,15 @@ common_params_context common_params_pars {"--list-devices"}, "print list of available devices and exit", [](common_params &) { - std::vector rpc_devices; - std::vector all_devices; + std::vector devices; for (size_t i = 0; i < ggml_backend_dev_count(); ++i) { auto * dev = ggml_backend_dev_get(i); - if (ggml_backend_dev_type(dev) == GGML_BACKEND_DEVICE_TYPE_GPU) { - ggml_backend_reg_t reg = ggml_backend_dev_backend_reg(dev); - if (ggml_backend_reg_name(reg) == std::string("RPC")) { - rpc_devices.push_back(dev); - } else { - all_devices.push_back(dev); - } + if (ggml_backend_dev_type(dev) != GGML_BACKEND_DEVICE_TYPE_CPU) { + devices.push_back(dev); } } - // insert RPC devices in front - all_devices.insert(all_devices.begin(), rpc_devices.begin(), rpc_devices.end()); printf("Available devices:\n"); - for (size_t i = 0; i < all_devices.size(); ++i) { - auto * dev = all_devices[i]; + for (auto * dev : devices) { size_t free, total; ggml_backend_dev_memory(dev, &free, &total); printf(" %s: %s (%zu MiB, %zu MiB free)\n", ggml_backend_dev_name(dev), ggml_backend_dev_description(dev), total / 1024 / 1024, free / 1024 / 1024); @@ -2329,41 +2889,61 @@ common_params_context common_params_pars add_opt(common_arg( {"--override-tensor", "-ot"}, "=,...", "override tensor buffer type", [](common_params & params, const std::string & value) { - /* static */ std::map buft_list; - if (buft_list.empty()) { - // enumerate all the devices and add their buffer types to the list - for (size_t i = 0; i < ggml_backend_dev_count(); ++i) { - auto * dev = ggml_backend_dev_get(i); - auto * buft = ggml_backend_dev_buffer_type(dev); - if (buft) { - buft_list[ggml_backend_buft_name(buft)] = buft; - } - } + parse_tensor_buffer_overrides(value, params.tensor_buft_overrides); + } + )); + add_opt(common_arg( + {"--override-tensor-draft", "-otd"}, "=,...", + "override tensor buffer type for draft model", [](common_params & params, const std::string & value) { + parse_tensor_buffer_overrides(value, params.speculative.tensor_buft_overrides); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); + add_opt(common_arg( + {"--cpu-moe", "-cmoe"}, + "keep all Mixture of Experts (MoE) weights in the CPU", + [](common_params & params) { + params.tensor_buft_overrides.push_back(llm_ffn_exps_cpu_override()); + } + ).set_env("LLAMA_ARG_CPU_MOE")); + add_opt(common_arg( + {"--n-cpu-moe", "-ncmoe"}, "N", + "keep the Mixture of Experts (MoE) weights of the first N layers in the CPU", + [](common_params & params, int value) { + if (value < 0) { + throw std::invalid_argument("invalid value"); } - - for (const auto & override : string_split(value, ',')) { - std::string::size_type pos = override.find('='); - if (pos == std::string::npos) { - throw std::invalid_argument("invalid value"); - } - std::string tensor_name = override.substr(0, pos); - std::string buffer_type = override.substr(pos + 1); - - if (buft_list.find(buffer_type) == buft_list.end()) { - printf("Available buffer types:\n"); - for (const auto & it : buft_list) { - printf(" %s\n", ggml_backend_buft_name(it.second)); - } - throw std::invalid_argument("unknown buffer type"); - } - // FIXME: this leaks memory - params.tensor_buft_overrides.push_back({strdup(tensor_name.c_str()), buft_list.at(buffer_type)}); + for (int i = 0; i < value; ++i) { + // keep strings alive and avoid leaking memory by storing them in a static vector + static std::list buft_overrides; + buft_overrides.push_back(llm_ffn_exps_block_regex(i)); + params.tensor_buft_overrides.push_back({buft_overrides.back().c_str(), ggml_backend_cpu_buffer_type()}); } } - )); + ).set_env("LLAMA_ARG_N_CPU_MOE")); + add_opt(common_arg( + {"--cpu-moe-draft", "-cmoed"}, + "keep all Mixture of Experts (MoE) weights in the CPU for the draft model", + [](common_params & params) { + params.speculative.tensor_buft_overrides.push_back(llm_ffn_exps_cpu_override()); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_CPU_MOE_DRAFT")); + add_opt(common_arg( + {"--n-cpu-moe-draft", "-ncmoed"}, "N", + "keep the Mixture of Experts (MoE) weights of the first N layers in the CPU for the draft model", + [](common_params & params, int value) { + if (value < 0) { + throw std::invalid_argument("invalid value"); + } + for (int i = 0; i < value; ++i) { + static std::list buft_overrides_draft; + buft_overrides_draft.push_back(llm_ffn_exps_block_regex(i)); + params.speculative.tensor_buft_overrides.push_back({buft_overrides_draft.back().c_str(), ggml_backend_cpu_buffer_type()}); + } + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_N_CPU_MOE_DRAFT")); add_opt(common_arg( {"-ngl", "--gpu-layers", "--n-gpu-layers"}, "N", - "number of layers to store in VRAM", + string_format("max. number of layers to store in VRAM (default: %d)", params.n_gpu_layers), [](common_params & params, int value) { params.n_gpu_layers = value; if (!llama_supports_gpu_offload()) { @@ -2460,7 +3040,7 @@ common_params_context common_params_pars {"--lora"}, "FNAME", "path to LoRA adapter (can be repeated to use multiple adapters)", [](common_params & params, const std::string & value) { - params.lora_adapters.push_back({ std::string(value), 1.0, nullptr }); + params.lora_adapters.push_back({ std::string(value), 1.0, "", "", nullptr }); } // we define this arg on both COMMON and EXPORT_LORA, so when showing help message of export-lora, it will be categorized as "example-specific" arg ).set_examples({LLAMA_EXAMPLE_COMMON, LLAMA_EXAMPLE_EXPORT_LORA})); @@ -2468,7 +3048,7 @@ common_params_context common_params_pars {"--lora-scaled"}, "FNAME", "SCALE", "path to LoRA adapter with user defined scaling (can be repeated to use multiple adapters)", [](common_params & params, const std::string & fname, const std::string & scale) { - params.lora_adapters.push_back({ fname, std::stof(scale), nullptr }); + params.lora_adapters.push_back({ fname, std::stof(scale), "", "", nullptr }); } // we define this arg on both COMMON and EXPORT_LORA, so when showing help message of export-lora, it will be categorized as "example-specific" arg ).set_examples({LLAMA_EXAMPLE_COMMON, LLAMA_EXAMPLE_EXPORT_LORA})); @@ -2522,6 +3102,15 @@ common_params_context common_params_pars } ).set_env("LLAMA_ARG_MODEL_URL")); add_opt(common_arg( + { "-dr", "--docker-repo" }, "[/][:quant]", + "Docker Hub model repository. repo is optional, default to ai/. quant is optional, default to :latest.\n" + "example: gemma3\n" + "(default: unused)", + [](common_params & params, const std::string & value) { + params.model.docker_repo = value; + } + ).set_env("LLAMA_ARG_DOCKER_REPO")); + add_opt(common_arg( {"-hf", "-hfr", "--hf-repo"}, "/[:quant]", "Hugging Face model repository; quant is optional, case-insensitive, default to Q4_K_M, or falls back to the first file in the repo if Q4_K_M doesn't exist.\n" "mmproj is also downloaded automatically if available. to disable, add --no-mmproj\n" @@ -2611,7 +3200,7 @@ common_params_context common_params_pars [](common_params & params, const std::string & value) { params.out_file = value; } - ).set_examples({LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_CVECTOR_GENERATOR, LLAMA_EXAMPLE_EXPORT_LORA, LLAMA_EXAMPLE_TTS})); + ).set_examples({LLAMA_EXAMPLE_IMATRIX, LLAMA_EXAMPLE_CVECTOR_GENERATOR, LLAMA_EXAMPLE_EXPORT_LORA, LLAMA_EXAMPLE_TTS, LLAMA_EXAMPLE_FINETUNE})); add_opt(common_arg( {"-ofreq", "--output-frequency"}, "N", string_format("output the imatrix every N iterations (default: %d)", params.n_out_freq), @@ -2620,6 +3209,15 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_IMATRIX})); add_opt(common_arg( + {"--output-format"}, "{gguf,dat}", + string_format("output format for imatrix file (default: %s)", params.imat_dat > 0 ? "dat" : "gguf"), + [](common_params & params, const std::string & value) { + /**/ if (value == "gguf") { params.imat_dat = -1; } + else if (value == "dat") { params.imat_dat = 1; } + else { throw std::invalid_argument("invalid output format"); } + } + ).set_examples({LLAMA_EXAMPLE_IMATRIX})); + add_opt(common_arg( {"--save-frequency"}, "N", string_format("save an imatrix copy every N iterations (default: %d)", params.n_save_freq), [](common_params & params, int value) { @@ -2648,6 +3246,13 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_IMATRIX})); add_opt(common_arg( + {"--show-statistics"}, + string_format("show imatrix statistics and then exit (default: %s)", params.show_statistics ? "true" : "false"), + [](common_params & params) { + params.show_statistics = true; + } + ).set_examples({LLAMA_EXAMPLE_IMATRIX})); + add_opt(common_arg( {"--parse-special"}, string_format("prase special tokens (chat, tool, etc) (default: %s)", params.parse_special ? "true" : "false"), [](common_params & params) { @@ -2844,13 +3449,6 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_ENDPOINT_METRICS")); add_opt(common_arg( - {"--slots"}, - string_format("enable slots monitoring endpoint (default: %s)", params.endpoint_slots ? "enabled" : "disabled"), - [](common_params & params) { - params.endpoint_slots = true; - } - ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_ENDPOINT_SLOTS")); - add_opt(common_arg( {"--props"}, string_format("enable changing global properties via POST /props (default: %s)", params.endpoint_props ? "enabled" : "disabled"), [](common_params & params) { @@ -2858,6 +3456,13 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_ENDPOINT_PROPS")); add_opt(common_arg( + {"--slots"}, + string_format("enable slots monitoring endpoint (default: %s)", params.endpoint_slots ? "enabled" : "disabled"), + [](common_params & params) { + params.endpoint_slots = true; + } + ).set_examples({LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_ENDPOINT_SLOTS")); + add_opt(common_arg( {"--no-slots"}, "disables slots monitoring endpoint", [](common_params & params) { @@ -2887,12 +3492,9 @@ common_params_context common_params_pars "controls whether thought tags are allowed and/or extracted from the response, and in which format they're returned; one of:\n" "- none: leaves thoughts unparsed in `message.content`\n" "- deepseek: puts thoughts in `message.reasoning_content` (except in streaming mode, which behaves as `none`)\n" - "(default: deepseek)", + "(default: auto)", [](common_params & params, const std::string & value) { - /**/ if (value == "deepseek") { params.reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK; } - else if (value == "deepseek-legacy") { params.reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY; } - else if (value == "none") { params.reasoning_format = COMMON_REASONING_FORMAT_NONE; } - else { throw std::invalid_argument("invalid value"); } + params.reasoning_format = common_reasoning_format_from_name(value); } ).set_examples({LLAMA_EXAMPLE_SERVER, LLAMA_EXAMPLE_MAIN}).set_env("LLAMA_ARG_THINK")); add_opt(common_arg( @@ -3018,13 +3620,21 @@ common_params_context common_params_pars common_log_set_file(common_log_main(), value.c_str()); } )); - add_opt(common_arg( - {"--log-colors"}, - "Enable colored logging", - [](common_params &) { - common_log_set_colors(common_log_main(), true); - } - ).set_env("LLAMA_LOG_COLORS")); + add_opt(common_arg({ "--log-colors" }, "[on|off|auto]", + "Set colored logging ('on', 'off', or 'auto', default: 'auto')\n" + "'auto' enables colors when output is to a terminal", + [](common_params &, const std::string & value) { + if (is_truthy(value)) { + common_log_set_colors(common_log_main(), LOG_COLORS_ENABLED); + } else if (is_falsey(value)) { + common_log_set_colors(common_log_main(), LOG_COLORS_DISABLED); + } else if (is_autoy(value)) { + common_log_set_colors(common_log_main(), LOG_COLORS_AUTO); + } else { + throw std::invalid_argument( + string_format("error: unkown value for --log-colors: '%s'\n", value.c_str())); + } + }).set_env("LLAMA_LOG_COLORS")); add_opt(common_arg( {"-v", "--verbose", "--log-verbose"}, "Set verbosity level to infinity (i.e. log all messages, useful for debugging)", @@ -3073,7 +3683,7 @@ common_params_context common_params_pars params.speculative.cpuparams.n_threads = std::thread::hardware_concurrency(); } } - ).set_examples({LLAMA_EXAMPLE_SPECULATIVE})); + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-tbd", "--threads-batch-draft"}, "N", "number of threads to use during batch and prompt processing (default: same as --threads-draft)", @@ -3083,7 +3693,7 @@ common_params_context common_params_pars params.speculative.cpuparams_batch.n_threads = std::thread::hardware_concurrency(); } } - ).set_examples({LLAMA_EXAMPLE_SPECULATIVE})); + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); add_opt(common_arg( {"-Cd", "--cpu-mask-draft"}, "M", "Draft model CPU affinity mask. Complements cpu-range-draft (default: same as --cpu-mask)", @@ -3235,6 +3845,13 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER}).set_env("LLAMA_ARG_MODEL_DRAFT")); add_opt(common_arg( + {"--spec-replace"}, "TARGET", "DRAFT", + "translate the string in TARGET into DRAFT if the draft model and main model are not compatible", + [](common_params & params, const std::string & tgt, const std::string & dft) { + params.speculative.replacements.push_back({ tgt, dft }); + } + ).set_examples({LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_SERVER})); + add_opt(common_arg( {"-ctkd", "--cache-type-k-draft"}, "TYPE", string_format( "KV cache data type for K for the draft model\n" @@ -3344,8 +3961,6 @@ common_params_context common_params_pars params.model.hf_repo = "ggml-org/Qwen2.5-Coder-1.5B-Q8_0-GGUF"; params.model.hf_file = "qwen2.5-coder-1.5b-q8_0.gguf"; params.port = 8012; - params.n_gpu_layers = 99; - params.flash_attn = true; params.n_ubatch = 1024; params.n_batch = 1024; params.n_ctx = 0; @@ -3360,8 +3975,6 @@ common_params_context common_params_pars params.model.hf_repo = "ggml-org/Qwen2.5-Coder-3B-Q8_0-GGUF"; params.model.hf_file = "qwen2.5-coder-3b-q8_0.gguf"; params.port = 8012; - params.n_gpu_layers = 99; - params.flash_attn = true; params.n_ubatch = 1024; params.n_batch = 1024; params.n_ctx = 0; @@ -3376,8 +3989,6 @@ common_params_context common_params_pars params.model.hf_repo = "ggml-org/Qwen2.5-Coder-7B-Q8_0-GGUF"; params.model.hf_file = "qwen2.5-coder-7b-q8_0.gguf"; params.port = 8012; - params.n_gpu_layers = 99; - params.flash_attn = true; params.n_ubatch = 1024; params.n_batch = 1024; params.n_ctx = 0; @@ -3393,10 +4004,7 @@ common_params_context common_params_pars params.model.hf_file = "qwen2.5-coder-7b-q8_0.gguf"; params.speculative.model.hf_repo = "ggml-org/Qwen2.5-Coder-0.5B-Q8_0-GGUF"; params.speculative.model.hf_file = "qwen2.5-coder-0.5b-q8_0.gguf"; - params.speculative.n_gpu_layers = 99; params.port = 8012; - params.n_gpu_layers = 99; - params.flash_attn = true; params.n_ubatch = 1024; params.n_batch = 1024; params.n_ctx = 0; @@ -3412,10 +4020,7 @@ common_params_context common_params_pars params.model.hf_file = "qwen2.5-coder-14b-q8_0.gguf"; params.speculative.model.hf_repo = "ggml-org/Qwen2.5-Coder-0.5B-Q8_0-GGUF"; params.speculative.model.hf_file = "qwen2.5-coder-0.5b-q8_0.gguf"; - params.speculative.n_gpu_layers = 99; params.port = 8012; - params.n_gpu_layers = 99; - params.flash_attn = true; params.n_ubatch = 1024; params.n_batch = 1024; params.n_ctx = 0; @@ -3423,5 +4028,111 @@ common_params_context common_params_pars } ).set_examples({LLAMA_EXAMPLE_SERVER})); + add_opt(common_arg( + {"--fim-qwen-30b-default"}, + string_format("use default Qwen 3 Coder 30B A3B Instruct (note: can download weights from the internet)"), + [](common_params & params) { + params.model.hf_repo = "ggml-org/Qwen3-Coder-30B-A3B-Instruct-Q8_0-GGUF"; + params.model.hf_file = "qwen3-coder-30b-a3b-instruct-q8_0.gguf"; + params.port = 8012; + params.n_ubatch = 1024; + params.n_batch = 1024; + params.n_ctx = 0; + params.n_cache_reuse = 256; + } + ).set_examples({LLAMA_EXAMPLE_SERVER})); + + add_opt(common_arg( + { "--diffusion-steps" }, "N", + string_format("number of diffusion steps (default: %d)", params.diffusion.steps), + [](common_params & params, int value) { params.diffusion.steps = value; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-visual" }, + string_format("enable visual diffusion mode (show progressive generation) (default: %s)", + params.diffusion.visual_mode ? "true" : "false"), + [](common_params & params) { params.diffusion.visual_mode = true; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + + add_opt(common_arg( + { "--diffusion-eps" }, "F", + string_format("epsilon for timesteps (default: %.6f)", (double) params.diffusion.eps), + [](common_params & params, const std::string & value) { params.diffusion.eps = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-algorithm" }, "N", + string_format("diffusion algorithm: 0=ORIGIN, 1=ENTROPY_BASED, 2=MARGIN_BASED, 3=RANDOM, 4=LOW_CONFIDENCE (default: %d)", + params.diffusion.algorithm), + [](common_params & params, int value) { params.diffusion.algorithm = value; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-alg-temp" }, "F", + string_format("dream algorithm temperature (default: %.3f)", (double) params.diffusion.alg_temp), + [](common_params & params, const std::string & value) { params.diffusion.alg_temp = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + + add_opt(common_arg( + { "--diffusion-block-length" }, "N", + string_format("llada block length for generation (default: %d)", params.diffusion.block_length), + [](common_params & params, int value) { params.diffusion.block_length = value; } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-cfg-scale" }, "F", + string_format("llada classifier-free guidance scale (default: %.3f)", (double) params.diffusion.cfg_scale), + [](common_params & params, const std::string & value) { params.diffusion.cfg_scale = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + add_opt(common_arg( + { "--diffusion-add-gumbel-noise" }, "F", + string_format("add gumbel noise to the logits if temp > 0.0 (default: %s)", params.diffusion.add_gumbel_noise ? "true" : "false"), + [](common_params & params, const std::string & value) { params.diffusion.add_gumbel_noise = std::stof(value); } + ).set_examples({ LLAMA_EXAMPLE_DIFFUSION })); + + + add_opt( + common_arg({ "-lr", "--learning-rate" }, "ALPHA", + string_format( + "adamw or sgd optimizer alpha (default: %.2g); note: sgd alpha recommended ~10x (no momentum)", + (double) params.lr.lr0), + [](common_params & params, const std::string & value) { params.lr.lr0 = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt( + common_arg({ "-lr-min", "--learning-rate-min" }, "ALPHA", + string_format( + "(if >0) final learning rate after decay (if -decay-epochs is set, default=%.2g)", + (double) params.lr.lr_min), + [](common_params & params, const std::string & value) { params.lr.lr_min = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt( + common_arg({ "-decay-epochs", "--learning-rate-decay-epochs" }, "ALPHA", + string_format( + "(if >0) decay learning rate to -lr-min after this many epochs (exponential decay, default=%.2g)", + (double) params.lr.decay_epochs), + [](common_params & params, const std::string & value) { params.lr.decay_epochs = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg( + { "-wd", "--weight-decay" }, "WD", + string_format( + "adamw or sgd optimizer weight decay (0 is off; recommend very small e.g. 1e-9) (default: %.2g).", + (double) params.lr.wd), + [](common_params & params, const std::string & value) { params.lr.wd = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-val-split", "--val-split" }, "FRACTION", + string_format("fraction of data to use as validation set for training (default: %.2g).", + (double) params.val_split), + [](common_params & params, const std::string & value) { params.val_split = std::stof(value); }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-epochs", "--epochs" }, "N", + string_format("optimizer max # of epochs (default: %d)", params.lr.epochs), + [](common_params & params, int epochs) { params.lr.epochs = epochs; }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + add_opt(common_arg({ "-opt", "--optimizer" }, "sgd|adamw", "adamw or sgd", + [](common_params & params, const std::string & name) { + params.optimizer = common_opt_get_optimizer(name.c_str()); + if (params.optimizer == GGML_OPT_OPTIMIZER_TYPE_COUNT) { + throw std::invalid_argument("invalid --optimizer, valid options: adamw, sgd"); + } + }) + .set_examples({ LLAMA_EXAMPLE_FINETUNE })); + return ctx_arg; } diff -pruN 5882+dfsg-2/common/chat-parser.cpp 6641+dfsg-2/common/chat-parser.cpp --- 5882+dfsg-2/common/chat-parser.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/chat-parser.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -55,7 +55,15 @@ bool common_chat_msg_parser::add_tool_ca bool common_chat_msg_parser::add_tool_call(const json & tool_call) { std::string name = tool_call.contains("name") ? tool_call.at("name") : ""; std::string id = tool_call.contains("id") ? tool_call.at("id") : ""; - std::string arguments = tool_call.contains("arguments") ? tool_call.at("arguments") : ""; + std::string arguments = ""; + if (tool_call.contains("arguments")) { + if (tool_call.at("arguments").is_object()) { + arguments = tool_call.at("arguments").dump(); + } else { + arguments = tool_call.at("arguments"); + } + } + return add_tool_call(name, id, arguments); } diff -pruN 5882+dfsg-2/common/chat.cpp 6641+dfsg-2/common/chat.cpp --- 5882+dfsg-2/common/chat.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/chat.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -126,6 +126,8 @@ std::vector common typedef minja::chat_template common_chat_template; struct common_chat_templates { + bool add_bos; + bool add_eos; bool has_explicit_template; // Model had builtin template or template overridde was specified. std::unique_ptr template_default; // always set (defaults to chatml) std::unique_ptr template_tool_use; @@ -143,6 +145,9 @@ struct templates_params { bool enable_thinking = true; std::chrono::system_clock::time_point now = std::chrono::system_clock::now(); json extra_context; + bool add_bos; + bool add_eos; + bool is_inference = true; }; common_chat_tool_choice common_chat_tool_choice_parse_oaicompat(const std::string & tool_choice) { @@ -158,6 +163,19 @@ common_chat_tool_choice common_chat_tool throw std::runtime_error("Invalid tool_choice: " + tool_choice); } +bool common_chat_templates_support_enable_thinking(const common_chat_templates * chat_templates) { + common_chat_templates_inputs dummy_inputs; + common_chat_msg msg; + msg.role = "user"; + msg.content = "test"; + dummy_inputs.messages = {msg}; + dummy_inputs.enable_thinking = false; + const auto rendered_no_thinking = common_chat_templates_apply(chat_templates, dummy_inputs); + dummy_inputs.enable_thinking = true; + const auto rendered_with_thinking = common_chat_templates_apply(chat_templates, dummy_inputs); + return rendered_no_thinking.prompt != rendered_with_thinking.prompt; +} + template <> std::vector common_chat_msgs_parse_oaicompat(const json & messages) { std::vector msgs; @@ -292,6 +310,7 @@ json common_chat_msgs_to_json_oaicompat( } if (!msg.reasoning_content.empty()) { jmsg["reasoning_content"] = msg.reasoning_content; + jmsg["thinking"] = msg.reasoning_content; // gpt-oss } if (!msg.tool_name.empty()) { jmsg["name"] = msg.tool_name; @@ -445,6 +464,8 @@ std::string common_chat_format_single( common_chat_templates_inputs inputs; inputs.use_jinja = use_jinja; + inputs.add_bos = tmpls->add_bos; + inputs.add_eos = tmpls->add_eos; std::string fmt_past_msg; if (!past_msg.empty()) { @@ -466,9 +487,12 @@ std::string common_chat_format_single( return ss.str(); } -std::string common_chat_format_example(const struct common_chat_templates * tmpls, bool use_jinja) { +std::string common_chat_format_example(const struct common_chat_templates * tmpls, bool use_jinja, const std::map & chat_template_kwargs) { common_chat_templates_inputs inputs; inputs.use_jinja = use_jinja; + inputs.add_bos = tmpls->add_bos; + inputs.add_eos = tmpls->add_eos; + inputs.chat_template_kwargs = chat_template_kwargs; auto add_simple_msg = [&](auto role, auto content) { common_chat_msg msg; msg.role = role; @@ -544,8 +568,21 @@ common_chat_templates_ptr common_chat_te default_template_src = CHATML_TEMPLATE_SRC; } } + + // TODO @ngxson : this is a temporary hack to prevent chat template from throwing an error + // Ref: https://github.com/ggml-org/llama.cpp/pull/15230#issuecomment-3173959633 + if (default_template_src.find("<|channel|>") != std::string::npos + // search for the error message and patch it + && default_template_src.find("in message.content or") != std::string::npos) { + string_replace_all(default_template_src, + "{%- if \"<|channel|>analysis<|message|>\" in message.content or \"<|channel|>final<|message|>\" in message.content %}", + "{%- if false %}"); + } + std::string token_bos = bos_token_override; std::string token_eos = eos_token_override; + bool add_bos = false; + bool add_eos = false; if (model) { const auto * vocab = llama_model_get_vocab(model); const auto get_token = [&](llama_token token, const char * name, const char * jinja_variable_name) { @@ -560,9 +597,13 @@ common_chat_templates_ptr common_chat_te }; token_bos = get_token(llama_vocab_bos(vocab), "BOS", "bos_token"); token_eos = get_token(llama_vocab_eos(vocab), "EOS", "eos_token"); + add_bos = llama_vocab_get_add_bos(vocab); + add_eos = llama_vocab_get_add_eos(vocab); } common_chat_templates_ptr tmpls(new common_chat_templates()); tmpls->has_explicit_template = has_explicit_template; + tmpls->add_bos = add_bos; + tmpls->add_eos = add_eos; try { tmpls->template_default = std::make_unique(default_template_src, token_bos, token_eos); } catch (const std::exception & e) { @@ -590,8 +631,13 @@ const char * common_chat_format_name(com case COMMON_CHAT_FORMAT_FIREFUNCTION_V2: return "FireFunction v2"; case COMMON_CHAT_FORMAT_FUNCTIONARY_V3_2: return "Functionary v3.2"; case COMMON_CHAT_FORMAT_FUNCTIONARY_V3_1_LLAMA_3_1: return "Functionary v3.1 Llama 3.1"; + case COMMON_CHAT_FORMAT_DEEPSEEK_V3_1: return "DeepSeek V3.1"; case COMMON_CHAT_FORMAT_HERMES_2_PRO: return "Hermes 2 Pro"; case COMMON_CHAT_FORMAT_COMMAND_R7B: return "Command R7B"; + case COMMON_CHAT_FORMAT_GRANITE: return "Granite"; + case COMMON_CHAT_FORMAT_GPT_OSS: return "GPT-OSS"; + case COMMON_CHAT_FORMAT_SEED_OSS: return "Seed-OSS"; + case COMMON_CHAT_FORMAT_NEMOTRON_V2: return "Nemotron V2"; default: throw std::runtime_error("Unknown chat format"); } @@ -600,6 +646,7 @@ const char * common_chat_format_name(com const char * common_reasoning_format_name(common_reasoning_format format) { switch (format) { case COMMON_REASONING_FORMAT_NONE: return "none"; + case COMMON_REASONING_FORMAT_AUTO: return "auto"; case COMMON_REASONING_FORMAT_DEEPSEEK: return "deepseek"; case COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY: return "deepseek-legacy"; default: @@ -607,6 +654,19 @@ const char * common_reasoning_format_nam } } +common_reasoning_format common_reasoning_format_from_name(const std::string & format) { + if (format == "none") { + return COMMON_REASONING_FORMAT_NONE; + } else if (format == "auto") { + return COMMON_REASONING_FORMAT_AUTO; + } else if (format == "deepseek") { + return COMMON_REASONING_FORMAT_DEEPSEEK; + } else if (format == "deepseek-legacy") { + return COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY; + } + throw std::runtime_error("Unknown reasoning format: " + format); +} + static std::string wrap_code_as_arguments(common_chat_msg_parser & builder, const std::string & code) { std::string arguments; if (builder.is_partial()) { @@ -639,11 +699,13 @@ static void parse_json_tool_calls( size_t from = std::string::npos; auto first = true; while (true) { + auto start_pos = builder.pos(); auto res = function_regex_start_only && first ? builder.try_consume_regex(*function_regex_start_only) : function_regex ? builder.try_find_regex(*function_regex, from) : std::nullopt; + if (res) { std::string name; if (get_function_name) { @@ -678,6 +740,8 @@ static void parse_json_tool_calls( return; } throw common_chat_msg_partial_exception("incomplete tool call"); + } else { + builder.move_to(start_pos); } break; } @@ -748,10 +812,10 @@ static std::string apply( // instead of using `chat_template_options.use_bos_token = false`, since these tokens // may be needed inside the template / between messages too. auto result = tmpl.apply(tmpl_inputs, tmpl_opts); - if (string_starts_with(result, tmpl.bos_token())) { + if (inputs.add_bos && string_starts_with(result, tmpl.bos_token())) { result = result.substr(tmpl.bos_token().size()); } - if (string_ends_with(result, tmpl.eos_token())) { + if (inputs.add_eos && string_ends_with(result, tmpl.eos_token())) { result = result.substr(0, result.size() - tmpl.eos_token().size()); } return result; @@ -1139,6 +1203,67 @@ static common_chat_params common_chat_pa }); return data; } + +static common_chat_params common_chat_params_init_nemotron_v2(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + + // Generate the prompt using the apply() function with the template + data.prompt = apply(tmpl, inputs); + data.format = COMMON_CHAT_FORMAT_NEMOTRON_V2; + + // Handle thinking tags appropriately based on inputs.enable_thinking + if (string_ends_with(data.prompt, "\n")) { + if (!inputs.enable_thinking) { + data.prompt += ""; + } else { + data.thinking_forced_open = true; + } + } + + // When tools are present, build grammar for the format, similar to CommandR, but without tool call ID + if (!inputs.tools.is_null() && inputs.tools.is_array() && !inputs.tools.empty()) { + data.grammar_lazy = true; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + auto schemas = json::array(); + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + schemas.push_back({ + { "type", "object" }, + { "properties", + { + { "name", + { + { "type", "string" }, + { "const", function.at("name") }, + } }, + { "arguments", function.at("parameters") }, + } }, + { "required", json::array({ "name", "arguments" }) }, + }); + }); + auto schema = json{ + { "type", "array" }, + { "items", schemas.size() == 1 ? schemas[0] : json{ { "anyOf", schemas } } }, + { "minItems", 1 }, + }; + if (!inputs.parallel_tool_calls) { + schema["maxItems"] = 1; + } + builder.add_rule("root", + std::string(data.thinking_forced_open ? "( \"\" space )? " : "") + + "\"\" " + builder.add_schema("tool_calls", schema) + + " \"\""); + }); + data.grammar_triggers.push_back({ COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN_FULL, + // If thinking_forced_open, then we capture the tag in the grammar, + // (important for required tool choice) and in the trigger's first capture (decides what is sent to the grammar) + std::string(data.thinking_forced_open ? + "[\\s\\S]*?(\\s*)" : + "(?:[\\s\\S]*?\\s*)?") + + "()[\\s\\S]*" }); + } + return data; +} static void common_chat_parse_llama_3_1(common_chat_msg_parser & builder, bool with_builtin_tools = false) { if (!builder.syntax().parse_tool_calls) { builder.add_content(builder.consume_rest()); @@ -1268,6 +1393,71 @@ static common_chat_params common_chat_pa } return data; } + +static common_chat_params common_chat_params_init_deepseek_v3_1(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + + // Pass thinking context for DeepSeek V3.1 template + json additional_context = { + {"thinking", inputs.enable_thinking}, + }; + + auto prompt = apply(tmpl, inputs, + /* messages_override= */ inputs.messages, + /* tools_override= */ std::nullopt, + additional_context); + data.prompt = prompt; + data.format = COMMON_CHAT_FORMAT_DEEPSEEK_V3_1; + if (string_ends_with(data.prompt, "")) { + if (!inputs.enable_thinking) { + data.prompt += ""; + } else { + data.thinking_forced_open = true; + } + } + if (inputs.tools.is_array() && !inputs.tools.empty()) { + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED && inputs.json_schema.is_null(); + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + std::vector tool_rules; + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + tool_rules.push_back(builder.add_rule(name + "-call", + "( \"<｜tool▁call▁begin｜>\" )? \"" + name + "<｜tool▁sep｜>" + "\" " + builder.add_schema(name + "-args", parameters) + " " + "\"<｜tool▁call▁end｜>\"")); + }); + // Distill Qwen 7B & 32B models seem confused re/ syntax of their tool call opening tag, + // so we accept common variants (then it's all constrained) + builder.add_rule("root", + std::string(data.thinking_forced_open ? "( \"\" space )? " : "") + + "( \"<｜tool▁calls▁begin｜>\" | \"<｜tool_calls_begin｜>\" | \"<｜tool calls begin｜>\" | \"<｜tool\\\\_calls\\\\_begin｜>\" | \"<｜tool▁calls｜>\" ) " + "(" + string_join(tool_rules, " | ") + ")" + (inputs.parallel_tool_calls ? "*" : "") + " " + "\"<｜tool▁calls▁end｜>\"" + " space"); + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN_FULL, + // If thinking_forced_open, then we capture the tag in the grammar, + // (important for required tool choice) and in the trigger's first capture (decides what is sent to the grammar) + std::string(data.thinking_forced_open ? "[\\s\\S]*?(\\s*)" : "(?:[\\s\\S]*?\\s*)?") + + "(<｜tool▁calls▁begin｜>|<｜tool_calls_begin｜>|<｜tool calls begin｜>|<｜tool\\\\_calls\\\\_begin｜>|<｜tool▁calls｜>)[\\s\\S]*" + }); + data.preserved_tokens = { + "", + "", + "<｜tool▁calls▁begin｜>", + "<｜tool▁call▁begin｜>", + "<｜tool▁sep｜>", + "<｜tool▁call▁end｜>", + "<｜tool▁calls▁end｜>", + }; + }); + } + return data; +} + static void common_chat_parse_deepseek_r1(common_chat_msg_parser & builder) { builder.try_parse_reasoning("", ""); if (!builder.syntax().parse_tool_calls) { @@ -1289,13 +1479,293 @@ static void common_chat_parse_deepseek_r tool_calls_end); } +static void common_chat_parse_deepseek_v3_1_content(common_chat_msg_parser & builder) { + static const common_regex function_regex("(?:<｜tool▁call▁begin｜>)?([^\\n<]+)(?:<｜tool▁sep｜>)"); + + static const common_regex close_regex("(?:[\\s]*)?<｜tool▁call▁end｜>"); + static const common_regex tool_calls_begin("(?:<｜tool▁calls▁begin｜>|<｜tool_calls_begin｜>|<｜tool calls begin｜>|<｜tool\\\\_calls\\\\_begin｜>|<｜tool▁calls｜>)"); + static const common_regex tool_calls_end("<｜tool▁calls▁end｜>"); + + if (!builder.syntax().parse_tool_calls) { + LOG_DBG("%s: not parse_tool_calls\n", __func__); + builder.add_content(builder.consume_rest()); + return; + } + + LOG_DBG("%s: parse_tool_calls\n", __func__); + + parse_json_tool_calls( + builder, + /* block_open= */ tool_calls_begin, + /* function_regex_start_only= */ std::nullopt, + function_regex, + close_regex, + tool_calls_end); +} + +static void common_chat_parse_deepseek_v3_1(common_chat_msg_parser & builder) { + // DeepSeek V3.1 outputs reasoning content between "" and "" tags, followed by regular content + // First try to parse using the standard reasoning parsing method + LOG_DBG("%s: thinking_forced_open: %s\n", __func__, std::to_string(builder.syntax().thinking_forced_open).c_str()); + + auto start_pos = builder.pos(); + auto found_end_think = builder.try_find_literal(""); + builder.move_to(start_pos); + + if (builder.syntax().thinking_forced_open && !builder.is_partial() && !found_end_think) { + LOG_DBG("%s: no end_think, not partial, adding content\n", __func__); + common_chat_parse_deepseek_v3_1_content(builder); + } else if (builder.try_parse_reasoning("", "")) { + // If reasoning was parsed successfully, the remaining content is regular content + LOG_DBG("%s: parsed reasoning, adding content\n", __func__); + // <｜tool▁calls▁begin｜><｜tool▁call▁begin｜>function<｜tool▁sep｜>NAME\n```json\nJSON\n```<｜tool▁call▁end｜><｜tool▁calls▁end｜> + common_chat_parse_deepseek_v3_1_content(builder); + } else { + if (builder.syntax().reasoning_format == COMMON_REASONING_FORMAT_NONE) { + LOG_DBG("%s: reasoning_format none, adding content\n", __func__); + common_chat_parse_deepseek_v3_1_content(builder); + return; + } + // If no reasoning tags found, check if we should treat everything as reasoning + if (builder.syntax().thinking_forced_open) { + // If thinking is forced open but no tags found, treat everything as reasoning + LOG_DBG("%s: thinking_forced_open, adding reasoning content\n", __func__); + builder.add_reasoning_content(builder.consume_rest()); + } else { + LOG_DBG("%s: no thinking_forced_open, adding content\n", __func__); + // <｜tool▁call▁begin｜>NAME<｜tool▁sep｜>JSON<｜tool▁call▁end｜> + common_chat_parse_deepseek_v3_1_content(builder); + } + } +} + +static common_chat_params common_chat_params_init_gpt_oss(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + auto prompt = apply(tmpl, inputs); + + // Check if we need to replace the return token with end token during + // inference and without generation prompt. For more details see: + // https://github.com/ggml-org/llama.cpp/issues/15417 + if (inputs.is_inference && !inputs.add_generation_prompt) { + static constexpr std::string_view return_token = "<|return|>"; + static constexpr std::string_view end_token = "<|end|>"; + if (size_t pos = prompt.rfind(return_token); pos != std::string::npos) { + prompt.replace(pos, return_token.length(), end_token); + } + } + + data.prompt = prompt; + data.format = COMMON_CHAT_FORMAT_GPT_OSS; + + // These special tokens are required to parse properly, so we include them + // even if parse_tool_calls is false. + data.preserved_tokens = { + "<|channel|>", + "<|constrain|>", + "<|message|>", + "<|start|>", + "<|end|>", + }; + + if (!inputs.json_schema.is_null()) { + data.grammar_lazy = false; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + auto schema = inputs.json_schema; + builder.resolve_refs(schema); + + auto not_end = builder.add_rule("not-end", + "[^<] | \"<\" [^|] | \"<|\" [^e] | \"<|e\" [^n] | \"<|en\" [^d] | \"<|end\" [^|] | \"<|end|\" [^>]"); + auto analysis = builder.add_rule("analysis", + "\"<|channel|>analysis<|message|>\" ( " + not_end + " )* \"<|end|>\""); + auto constraint = builder.add_rule("constraint", "\"<|constrain|>\"? [a-zA-Z0-9_-]+"); + auto final = builder.add_rule("final", + "\"<|channel|>final\" ( \" \" " + constraint + " )? \"<|message|>\" " + + builder.add_schema("response", schema) + ); + + builder.add_rule("root", "( " + analysis + " \"<|start|>assistant\" )? " + final); + }); + } + + if (inputs.tools.is_array() && !inputs.tools.empty()) { + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + // tool calls can appear in commentary or analysis channels + auto channel = builder.add_rule("channel", "\"<|channel|>\" ( \"commentary\" | \"analysis\" )"); + + std::vector tool_rules_recipient_in_role; + std::vector tool_rules_recipient_in_channel; + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + + tool_rules_recipient_in_role.push_back( + builder.add_rule(name + "-call", + "\"" + name + "\"" + channel + " \" <|constrain|>json\"? \"<|message|>\" " + + builder.add_schema(name + "-args", parameters) + ) + ); + + tool_rules_recipient_in_channel.push_back( + builder.add_rule(name + "-call", + "\"" + name + "\"" + " \" <|constrain|>json\"? \"<|message|>\" " + + builder.add_schema(name + "-args", parameters) + ) + ); + }); + + auto recipient_in_channel = builder.add_rule("recipient_in_channel", + channel + " \" to=functions.\" ( " + + string_join(tool_rules_recipient_in_channel, " | ") + " )" + ); + + if (data.grammar_lazy) { + auto recipient_in_role = builder.add_rule("recipient_in_role", + "\"<|start|>assistant\"? \" to=functions.\" ( " + + string_join(tool_rules_recipient_in_role, " | ") + " )" + ); + + builder.add_rule("root", recipient_in_role + " | " + recipient_in_channel); + } else { + auto not_end = builder.add_rule("not-end", + "[^<] | \"<\" [^|] | \"<|\" [^e] | \"<|e\" [^n] | \"<|en\" [^d] | \"<|end\" [^|] | \"<|end|\" [^>]"); + auto analysis = builder.add_rule("analysis", + "\"<|channel|>analysis<|message|>\" ( " + not_end + " )* \"<|end|>\""); + auto commentary = builder.add_rule("commentary", + "\"<|channel|>commentary<|message|>\" ( " + not_end + " )* \"<|end|>\""); + + auto recipient_in_role = builder.add_rule("recipient_in_role", + "\" to=functions.\" ( " + string_join(tool_rules_recipient_in_role, " | ") + " )" + ); + + builder.add_rule("root", + "( " + analysis + " \"<|start|>assistant\" )? " + + "( " + commentary + " \"<|start|>assistant\" )? " + + "( " + recipient_in_role + " | " + recipient_in_channel + " )" + ); + } + + // Trigger on tool calls that appear in the commentary channel + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, + "<\\|channel\\|>(commentary|analysis) to" + }); + + // Trigger tool calls that appear in the role section, either at the + // start or in the middle. + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN_FULL, + "^ to" + }); + + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_PATTERN, + "<\\|start\\|>assistant to" + }); + }); + } + + return data; +} +static void common_chat_parse_gpt_oss(common_chat_msg_parser & builder) { + static const std::string constraint = "(?: (<\\|constrain\\|>)?([a-zA-Z0-9_-]+))"; + static const std::string recipient("(?: to=functions\\.([^<\\s]+))"); + + static const common_regex start_regex("<\\|start\\|>assistant"); + static const common_regex analysis_regex("<\\|channel\\|>analysis"); + static const common_regex final_regex("<\\|channel\\|>final" + constraint + "?"); + static const common_regex preamble_regex("<\\|channel\\|>commentary"); + static const common_regex tool_call1_regex(recipient + "<\\|channel\\|>(analysis|commentary)" + constraint + "?"); + static const common_regex tool_call2_regex("<\\|channel\\|>(analysis|commentary)" + recipient + constraint + "?"); + + auto consume_end = [&](bool include_end = false) { + if (auto res = builder.try_find_literal("<|end|>")) { + return res->prelude + (include_end ? builder.str(res->groups[0]) : ""); + } + return builder.consume_rest(); + }; + + auto handle_tool_call = [&](const std::string & name) { + if (auto args = builder.try_consume_json_with_dumped_args({{}})) { + if (builder.syntax().parse_tool_calls) { + if (!builder.add_tool_call(name, "", args->value) || args->is_partial) { + throw common_chat_msg_partial_exception("incomplete tool call"); + } + } else if (args->is_partial) { + throw common_chat_msg_partial_exception("incomplete tool call"); + } + } + }; + + auto regex_match = [](const common_regex & regex, const std::string & input) -> std::optional { + auto match = regex.search(input, 0, true); + if (match.type == COMMON_REGEX_MATCH_TYPE_FULL) { + return match; + } + return std::nullopt; + }; + + do { + auto header_start_pos = builder.pos(); + auto content_start = builder.try_find_literal("<|message|>"); + if (!content_start) { + throw common_chat_msg_partial_exception("incomplete header"); + } + + auto header = content_start->prelude; + + if (auto match = regex_match(tool_call1_regex, header)) { + auto group = match->groups[1]; + auto name = header.substr(group.begin, group.end - group.begin); + handle_tool_call(name); + continue; + } + + if (auto match = regex_match(tool_call2_regex, header)) { + auto group = match->groups[2]; + auto name = header.substr(group.begin, group.end - group.begin); + handle_tool_call(name); + continue; + } + + if (regex_match(analysis_regex, header)) { + builder.move_to(header_start_pos); + if (builder.syntax().reasoning_format == COMMON_REASONING_FORMAT_NONE || builder.syntax().reasoning_in_content) { + builder.add_content(consume_end(true)); + } else { + builder.try_parse_reasoning("<|channel|>analysis<|message|>", "<|end|>"); + } + continue; + } + + if(regex_match(final_regex, header) || regex_match(preamble_regex, header)) { + builder.add_content(consume_end()); + continue; + } + + // Possibly a malformed message, attempt to recover by rolling + // back to pick up the next <|start|> + LOG_DBG("%s: unknown header from message: %s\n", __func__, header.c_str()); + builder.move_to(header_start_pos); + } while (builder.try_find_regex(start_regex, std::string::npos, false)); + + auto remaining = builder.consume_rest(); + if (!remaining.empty()) { + LOG_DBG("%s: content after last message: %s\n", __func__, remaining.c_str()); + } +} + static common_chat_params common_chat_params_init_firefunction_v2(const common_chat_template & tmpl, const struct templates_params & inputs) { LOG_DBG("%s\n", __func__); common_chat_params data; - data.prompt = apply(tmpl, inputs, /* messages_override =*/ std::nullopt, /* tools_override= */ json(), json { + const std::optional tools_override = json(); + const std::optional additional_context = json { {"datetime", format_time(inputs.now, "%b %d %Y %H:%M:%S GMT")}, {"functions", json(inputs.tools.empty() ? "" : inputs.tools.dump(2))}, - }); + }; + data.prompt = apply(tmpl, inputs, /* messages_override =*/ std::nullopt, tools_override, additional_context); if (inputs.tools.is_array() && !inputs.tools.empty()) { data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; data.grammar = build_grammar([&](const common_grammar_builder & builder) { @@ -1586,7 +2056,7 @@ static common_chat_params common_chat_pa // If thinking_forced_open, then we capture the tag in the grammar, // (important for required tool choice) and in the trigger's first capture (decides what is sent to the grammar) std::string(data.thinking_forced_open ? "[\\s\\S]*?(\\s*)" : "(?:[\\s\\S]*?\\s*)?") + ( - "(\\s*" + "\\s*(" "(?:" "||||)?" @@ -1646,7 +2116,7 @@ static void common_chat_parse_hermes_2_p "|" // match 5 (function name again) ); - if (auto res = builder.try_find_regex(open_regex)) { + while (auto res = builder.try_find_regex(open_regex)) { const auto & block_start = res->groups[1]; std::string block_end = block_start.empty() ? "" : "```"; @@ -1668,7 +2138,6 @@ static void common_chat_parse_hermes_2_p builder.consume_literal(block_end); builder.consume_spaces(); } - builder.add_content(builder.consume_rest()); } else { throw common_chat_msg_partial_exception("failed to parse tool call"); } @@ -1693,13 +2162,255 @@ static void common_chat_parse_hermes_2_p builder.consume_spaces(); } } - builder.add_content(builder.consume_rest()); + } + } + + builder.add_content(builder.consume_rest()); +} + +static common_chat_params common_chat_params_init_granite(const common_chat_template & tmpl, const struct templates_params & inputs) { + common_chat_params data; + + // Pass thinking context for Granite template + json additional_context = { + {"thinking", inputs.enable_thinking}, + }; + + data.prompt = apply(tmpl, inputs, /* messages_override= */ std::nullopt, /* tools_override= */ std::nullopt, additional_context); + data.format = COMMON_CHAT_FORMAT_GRANITE; + + if (string_ends_with(data.prompt, "\n") || string_ends_with(data.prompt, "")) { + if (!inputs.enable_thinking) { + data.prompt += ""; + } else { + data.thinking_forced_open = true; + } + } + + if (!inputs.tools.is_null()) { + // Granite uses <|tool_call|> followed by JSON list + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + std::vector tool_rules; + foreach_function(inputs.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + tool_rules.push_back(builder.add_rule(name + "-call", builder.add_schema(name + +"-args", { + {"type", "object"}, + {"properties", { + {"name", {{"const", name}}}, + {"arguments", parameters}, + }}, + {"required", json::array({"name", "arguments"})}, + }))); + }); + + auto tool_call = builder.add_rule("tool_call", string_join(tool_rules, " | ")); + auto tool_list = builder.add_rule("tool_list", "\"[\" space " + tool_call + " (\",\" space " + tool_call + ")* space \"]\""); + + if (data.thinking_forced_open) { + builder.add_rule("root", "\"\" space \"\" space [^<]* \"\" space \"<|tool_call|>\" space " + tool_list); + } else { + builder.add_rule("root", "\"<|tool_call|>\" space " + tool_list); + } + + data.grammar_triggers.push_back({ + COMMON_GRAMMAR_TRIGGER_TYPE_WORD, + "<|tool_call|>" + }); + + data.preserved_tokens = { + "", + "", + "", + "", + "<|tool_call|>", + }; + }); + } else { + // Handle thinking tags for non-tool responses + if (data.thinking_forced_open && inputs.enable_thinking) { + data.grammar_lazy = false; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + builder.add_rule("root", "\"\" space \"\" space .* \"\" space"); + }); + data.preserved_tokens = { + "", + "", + "", + "", + }; + } + } + + return data; +} + +static void common_chat_parse_granite(common_chat_msg_parser & builder) { + // Parse thinking tags + static const common_regex start_think_regex(regex_escape("")); + static const common_regex end_think_regex(regex_escape("")); + // Granite models output partial tokens such as "<" and "groups[0].begin); + builder.try_find_regex(end_think_regex, std::string::npos, false); + // Restore position for try_parse_reasoning() + builder.move_to(res->groups[0].begin); + } + builder.try_parse_reasoning("", ""); + + // Parse response tags + static const common_regex start_response_regex(regex_escape("")); + static const common_regex end_response_regex(regex_escape("")); + // Granite models output partial tokens such as "<" and "")); + if (auto res = builder.try_find_regex(tool_call_regex)) { + builder.move_to(res->groups[0].end); + + // Expect JSON array of tool calls + if (auto tool_call = builder.try_consume_json_with_dumped_args({{{"arguments"}}})) { + if (!builder.add_tool_calls(tool_call->value) || tool_call->is_partial) { + throw common_chat_msg_partial_exception("incomplete tool call"); + } } } else { builder.add_content(builder.consume_rest()); } } +static void common_chat_parse_nemotron_v2(common_chat_msg_parser & builder) { + // Parse thinking tags + builder.try_parse_reasoning("", ""); + if (!builder.syntax().parse_tool_calls) { + builder.add_content(builder.consume_rest()); + return; + } + + // Look for tool calls + static const common_regex tool_call_regex(regex_escape("")); + if (auto res = builder.try_find_regex(tool_call_regex)) { + builder.move_to(res->groups[0].end); + + // Expect JSON array of tool calls + auto tool_calls_data = builder.consume_json(); + if (tool_calls_data.json.is_array()) { + if (!builder.try_consume_literal("")) { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + builder.add_tool_calls(tool_calls_data.json); + } else { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + } + builder.add_content(builder.consume_rest()); +} + +static void common_chat_parse_seed_oss(common_chat_msg_parser & builder) { + // Parse thinking tags first - this handles the main reasoning content + builder.try_parse_reasoning("", ""); + + if (!builder.syntax().parse_tool_calls) { + builder.add_content(builder.consume_rest()); + return; + } + + // Parse tool calls - Seed-OSS uses format + static const common_regex tool_call_begin_regex(""); + static const common_regex tool_call_end_regex(""); + static const common_regex function_regex("]+)>"); + static const common_regex param_regex("]+)>"); + + while (auto tool_res = builder.try_find_regex(tool_call_begin_regex)) { + builder.consume_spaces(); // Consume whitespace after + + // Look for function call inside tool call, ignore any content before it + if (auto func_res = builder.try_find_regex(function_regex, std::string::npos, false)) { + auto function_name = builder.str(func_res->groups[1]); + + // Parse Seed-OSS parameters value + json args = json::object(); + // Parse all parameters + while (auto param_res = builder.try_find_regex(param_regex, std::string::npos, false)) { + // again, ignore noise around parameters + auto param_name = builder.str(param_res->groups[1]); + builder.move_to(param_res->groups[0].end); + builder.consume_spaces(); // Consume whitespace after parameter + auto savedPos = builder.pos(); + if (auto param_parse = builder.try_find_literal("")) { + auto param = param_parse->prelude; + builder.move_to(savedPos); + try { + if (auto param_res = builder.try_consume_json()) { + args[param_name] = param_res->json; + } else { + args[param_name] = param; + } + } catch (json::exception &) { + args[param_name] = param; + } + } else { + throw common_chat_msg_partial_exception("Incomplete tool parameter"); + } + } + // Look for closing function tag + auto end_func = builder.try_find_literal(""); + if (end_func) { + builder.move_to(end_func->groups[0].end); + builder.consume_spaces(); // Consume whitespace after + + // Add the tool call with parsed arguments, but only if we REALLY got the literal + auto eaten_fragment = builder.input().substr(end_func->groups[0].begin, end_func->groups[0].end); + auto funlen = std::string("").length(); + if (eaten_fragment.length() >= funlen && eaten_fragment.substr(0, funlen) == std::string("")) { + if (!builder.add_tool_call(function_name, "", args.dump())) { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + } else { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + } else { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + // Look for closing tool call tag + if (auto end_tool = builder.try_find_regex(tool_call_end_regex, std::string::npos, false)) { + builder.move_to(end_tool->groups[0].end); + builder.consume_spaces(); // Consume trailing whitespace after tool call + } else { + throw common_chat_msg_partial_exception("Incomplete tool call"); + } + } else { + // No function found - don't consume content here, let it be handled at the end + break; + } + } + + // Consume any remaining whitespace after all tool call processing + builder.consume_spaces(); + auto remaining = builder.consume_rest(); + // If there's any non-whitespace content remaining, add it as content + if (!string_strip(remaining).empty()) { + builder.add_content(remaining); + } +} + static common_chat_params common_chat_params_init_without_tools(const common_chat_template & tmpl, const struct templates_params & inputs) { common_chat_params data; data.prompt = apply(tmpl, inputs); @@ -1716,8 +2427,62 @@ static common_chat_params common_chat_pa return data; } +static common_chat_params common_chat_params_init_seed_oss( + const common_chat_template & tmpl, + templates_params & params, + const common_chat_templates_inputs & inputs) +{ + common_chat_params data; + data.prompt = apply(tmpl, params); + data.format = COMMON_CHAT_FORMAT_SEED_OSS; + if (string_ends_with(data.prompt, "")) { + if (!inputs.enable_thinking) { + data.prompt += ""; + } else { + data.thinking_forced_open = true; + } + } + + if (params.tools.is_array() && !params.tools.empty()) { + data.grammar_lazy = inputs.tool_choice != COMMON_CHAT_TOOL_CHOICE_REQUIRED; + data.grammar = build_grammar([&](const common_grammar_builder & builder) { + std::vector tool_rules; + foreach_function(params.tools, [&](const json & tool) { + const auto & function = tool.at("function"); + std::string name = function.at("name"); + auto parameters = function.at("parameters"); + builder.resolve_refs(parameters); + + // Create rule for Seed-OSS function call format + std::string param_rules; + if (parameters.contains("properties")) { + for (const auto & [key, value] : parameters.at("properties").items()) { + param_rules += "\"\"" + builder.add_schema(name + "-arg-" + key, value) + + "\"\""; + } + } + + tool_rules.push_back(builder.add_rule(name + "-call", + "\"\" space \"\" space " + + param_rules + + " \"\" space \"\"")); + }); + + data.grammar_triggers.push_back({ COMMON_GRAMMAR_TRIGGER_TYPE_WORD, "" }); + + data.preserved_tokens = { + "", "", "", "", + "", "", + }; + + builder.add_rule("root", string_join(tool_rules, " | ")); + }); + } + return data; +} + static common_chat_params common_chat_templates_apply_jinja( - const struct common_chat_templates * tmpls, + const struct common_chat_templates * tmpls, const struct common_chat_templates_inputs & inputs) { templates_params params; @@ -1733,6 +2498,8 @@ static common_chat_params common_chat_te params.enable_thinking = inputs.enable_thinking; params.grammar = inputs.grammar; params.now = inputs.now; + params.add_bos = tmpls->add_bos; + params.add_eos = tmpls->add_eos; params.extra_context = json::object(); for (auto el : inputs.chat_template_kwargs) { @@ -1759,6 +2526,12 @@ static common_chat_params common_chat_te } } + // DeepSeek V3.1: detect based on specific patterns in the template + if (src.find("message['prefix'] is defined and message['prefix'] and thinking") != std::string::npos && + params.json_schema.is_null()) { + return common_chat_params_init_deepseek_v3_1(tmpl, params); + } + // DeepSeek R1: use handler in all cases except json schema (thinking / tools). if (src.find("<｜tool▁calls▁begin｜>") != std::string::npos && params.json_schema.is_null()) { return common_chat_params_init_deepseek_r1(tmpl, params); @@ -1769,11 +2542,31 @@ static common_chat_params common_chat_te return common_chat_params_init_command_r7b(tmpl, params); } + // Granite (IBM) - detects thinking / tools support + if (src.find("elif thinking") != std::string::npos && src.find("<|tool_call|>") != std::string::npos) { + return common_chat_params_init_granite(tmpl, params); + } + // Hermes 2/3 Pro, Qwen 2.5 Instruct (w/ tools) if (src.find("") != std::string::npos && params.json_schema.is_null()) { return common_chat_params_init_hermes_2_pro(tmpl, params); } + // GPT-OSS + if (src.find("<|channel|>") != std::string::npos) { + return common_chat_params_init_gpt_oss(tmpl, params); + } + + // Seed-OSS + if (src.find("") != std::string::npos) { + return common_chat_params_init_seed_oss(tmpl, params, inputs); + } + + // Nemotron v2 + if (src.find("") != std::string::npos) { + return common_chat_params_init_nemotron_v2(tmpl, params); + } + // Use generic handler when mixing tools + JSON schema. // TODO: support that mix in handlers below. if ((params.tools.is_array() && params.json_schema.is_object())) { @@ -1824,6 +2617,7 @@ static common_chat_params common_chat_te int alloc_size = 0; std::vector chat; std::vector contents; + for (const auto & msg : inputs.messages) { auto content = msg.content; for (const auto & part : msg.content_parts) { @@ -1910,6 +2704,9 @@ static void common_chat_parse(common_cha case COMMON_CHAT_FORMAT_DEEPSEEK_R1: common_chat_parse_deepseek_r1(builder); break; + case COMMON_CHAT_FORMAT_DEEPSEEK_V3_1: + common_chat_parse_deepseek_v3_1(builder); + break; case COMMON_CHAT_FORMAT_FUNCTIONARY_V3_2: common_chat_parse_functionary_v3_2(builder); break; @@ -1925,6 +2722,18 @@ static void common_chat_parse(common_cha case COMMON_CHAT_FORMAT_COMMAND_R7B: common_chat_parse_command_r7b(builder); break; + case COMMON_CHAT_FORMAT_GRANITE: + common_chat_parse_granite(builder); + break; + case COMMON_CHAT_FORMAT_GPT_OSS: + common_chat_parse_gpt_oss(builder); + break; + case COMMON_CHAT_FORMAT_SEED_OSS: + common_chat_parse_seed_oss(builder); + break; + case COMMON_CHAT_FORMAT_NEMOTRON_V2: + common_chat_parse_nemotron_v2(builder); + break; default: throw std::runtime_error(std::string("Unsupported format: ") + common_chat_format_name(builder.syntax().format)); } @@ -1944,6 +2753,8 @@ common_chat_msg common_chat_parse(const } } auto msg = builder.result(); - LOG_DBG("Parsed message: %s\n", common_chat_msgs_to_json_oaicompat({msg}).at(0).dump().c_str()); + if (!is_partial) { + LOG_DBG("Parsed message: %s\n", common_chat_msgs_to_json_oaicompat({msg}).at(0).dump().c_str()); + } return msg; } diff -pruN 5882+dfsg-2/common/chat.h 6641+dfsg-2/common/chat.h --- 5882+dfsg-2/common/chat.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/chat.h 2025-09-30 07:36:33.000000000 +0000 @@ -107,8 +107,13 @@ enum common_chat_format { COMMON_CHAT_FORMAT_FIREFUNCTION_V2, COMMON_CHAT_FORMAT_FUNCTIONARY_V3_2, COMMON_CHAT_FORMAT_FUNCTIONARY_V3_1_LLAMA_3_1, + COMMON_CHAT_FORMAT_DEEPSEEK_V3_1, COMMON_CHAT_FORMAT_HERMES_2_PRO, COMMON_CHAT_FORMAT_COMMAND_R7B, + COMMON_CHAT_FORMAT_GRANITE, + COMMON_CHAT_FORMAT_GPT_OSS, + COMMON_CHAT_FORMAT_SEED_OSS, + COMMON_CHAT_FORMAT_NEMOTRON_V2, COMMON_CHAT_FORMAT_COUNT, // Not a format, just the # formats }; @@ -127,6 +132,8 @@ struct common_chat_templates_inputs { bool enable_thinking = true; std::chrono::system_clock::time_point now = std::chrono::system_clock::now(); std::map chat_template_kwargs; + bool add_bos = false; + bool add_eos = false; }; struct common_chat_params { @@ -183,14 +190,18 @@ std::string common_chat_format_single( // Returns an example of formatted chat std::string common_chat_format_example( const struct common_chat_templates * tmpls, - bool use_jinja); + bool use_jinja, + const std::map & chat_template_kwargs); const char* common_chat_format_name(common_chat_format format); const char* common_reasoning_format_name(common_reasoning_format format); +common_reasoning_format common_reasoning_format_from_name(const std::string & format); common_chat_msg common_chat_parse(const std::string & input, bool is_partial, const common_chat_syntax & syntax); common_chat_tool_choice common_chat_tool_choice_parse_oaicompat(const std::string & tool_choice); +bool common_chat_templates_support_enable_thinking(const common_chat_templates * chat_templates); + // Parses a JSON array of messages in OpenAI's chat completion API format. // T can be std::string containing JSON or nlohmann::ordered_json template std::vector common_chat_msgs_parse_oaicompat(const T & messages); diff -pruN 5882+dfsg-2/common/common.cpp 6641+dfsg-2/common/common.cpp --- 5882+dfsg-2/common/common.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/common.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,7 @@ #endif #include #include +#include #include #include #else @@ -49,6 +51,11 @@ #include #endif +#if defined(__linux__) +#include +#include +#endif + #if defined(_MSC_VER) #pragma warning(disable: 4244 4267) // possible loss of data #endif @@ -448,6 +455,15 @@ void string_replace_all(std::string & s, bool string_ends_with(const std::string_view & str, const std::string_view & suffix) { return str.size() >= suffix.size() && str.compare(str.size()-suffix.size(), suffix.size(), suffix) == 0; } + +bool string_remove_suffix(std::string & str, const std::string_view & suffix) { + bool has_suffix = string_ends_with(str, suffix); + if (has_suffix) { + str = str.substr(0, str.size() - suffix.size()); + } + return has_suffix; +} + size_t string_find_partial_stop(const std::string_view & str, const std::string_view & stop) { if (!str.empty() && !stop.empty()) { const char text_last_char = str.back(); @@ -548,13 +564,6 @@ std::string string_from(const struct lla auto detokenized = common_token_to_piece(ctx, token); - detokenized.erase( - std::remove_if( - detokenized.begin(), - detokenized.end(), - [](const unsigned char c) { return !std::isprint(c); }), - detokenized.end()); - buf << "'" << detokenized << "'" << ":" << std::to_string(token); } @@ -579,13 +588,6 @@ std::string string_from(const struct lla auto detokenized = common_token_to_piece(ctx, batch.token[i]); - detokenized.erase( - std::remove_if( - detokenized.begin(), - detokenized.end(), - [](const unsigned char c) { return !std::isprint(c); }), - detokenized.end()); - buf << "\n" << std::to_string(i) << ", token '" << detokenized << "'" << ", pos " << std::to_string(batch.pos[i]) @@ -868,8 +870,20 @@ std::string fs_get_cache_directory() { #if defined(__linux__) || defined(__FreeBSD__) || defined(_AIX) || defined(__OpenBSD__) if (std::getenv("XDG_CACHE_HOME")) { cache_directory = std::getenv("XDG_CACHE_HOME"); - } else { + } else if (std::getenv("HOME")) { cache_directory = std::getenv("HOME") + std::string("/.cache/"); + } else { +#if defined(__linux__) + /* no $HOME is defined, fallback to getpwuid */ + struct passwd *pw = getpwuid(getuid()); + if ((!pw) || (!pw->pw_dir)) { + throw std::runtime_error("Failed to find $HOME directory"); + } + + cache_directory = std::string(pw->pw_dir) + std::string("/.cache/"); +#else /* defined(__linux__) */ + throw std::runtime_error("Failed to find $HOME directory"); +#endif /* defined(__linux__) */ } #elif defined(__APPLE__) cache_directory = std::getenv("HOME") + std::string("/Library/Caches/"); @@ -905,7 +919,8 @@ struct common_init_result common_init_fr llama_model * model = llama_model_load_from_file(params.model.path.c_str(), mparams); if (model == NULL) { - LOG_ERR("%s: failed to load model '%s'\n", __func__, params.model.path.c_str()); + LOG_ERR("%s: failed to load model '%s', try reducing --n-gpu-layers if you're running out of VRAM\n", + __func__, params.model.path.c_str()); return iparams; } @@ -915,7 +930,8 @@ struct common_init_result common_init_fr llama_context * lctx = llama_init_from_model(model, cparams); if (lctx == NULL) { - LOG_ERR("%s: failed to create context with model '%s'\n", __func__, params.model.path.c_str()); + LOG_ERR("%s: failed to create context with model '%s', try reducing --n-gpu-layers if you're running out of VRAM\n", + __func__, params.model.path.c_str()); llama_model_free(model); return iparams; } @@ -962,15 +978,13 @@ struct common_init_result common_init_fr bool has_eos = llama_vocab_eos(vocab) != LLAMA_TOKEN_NULL; bool has_sep = llama_vocab_sep(vocab) != LLAMA_TOKEN_NULL; + bool has_rerank_prompt = llama_model_chat_template(model, "rerank") != NULL; - if (!has_eos && !has_sep) { - LOG_WRN("%s: warning: vocab does not have an EOS token or SEP token, reranking will not work\n", __func__); + if (!has_eos && !has_sep && !has_rerank_prompt) { + LOG_WRN("%s: warning: vocab does not have an EOS token, SEP token, or rerank prompt. Reranking will not work\n", __func__); ok = false; } else if (!has_eos) { LOG_WRN("%s: warning: vocab does not have an EOS token, using SEP token as fallback\n", __func__); - } else if (!has_sep) { - LOG_WRN("%s: warning: vocab does not have a SEP token, reranking will not work\n", __func__); - ok = false; } if (!ok) { @@ -992,7 +1006,12 @@ struct common_init_result common_init_fr return iparams; } + char buf[1024]; la.ptr = lora.get(); + llama_adapter_meta_val_str(la.ptr, "adapter.lora.task_name", buf, sizeof(buf)); + la.task_name = buf; + llama_adapter_meta_val_str(la.ptr, "adapter.lora.prompt_prefix", buf, sizeof(buf)); + la.prompt_prefix = buf; iparams.lora.emplace_back(std::move(lora)); // copy to list of loaded adapters } @@ -1005,15 +1024,21 @@ struct common_init_result common_init_fr params.sampling.ignore_eos = false; } - if (params.sampling.ignore_eos) { - for (llama_token i = 0; i < llama_vocab_n_tokens(vocab); i++) { - if (llama_vocab_is_eog(vocab, i)) { - LOG_INF("%s: added %s logit bias = %f\n", __func__, common_token_to_piece(lctx, i).c_str(), -INFINITY); - params.sampling.logit_bias.push_back({i, -INFINITY}); - } + // initialize once + for (llama_token i = 0; i < llama_vocab_n_tokens(vocab); i++) { + if (llama_vocab_is_eog(vocab, i)) { + LOG_INF("%s: added %s logit bias = %f\n", __func__, common_token_to_piece(lctx, i).c_str(), -INFINITY); + params.sampling.logit_bias_eog.push_back({i, -INFINITY}); } } + if (params.sampling.ignore_eos) { + // add EOG biases to the active set of logit biases + params.sampling.logit_bias.insert( + params.sampling.logit_bias.end(), + params.sampling.logit_bias_eog.begin(), params.sampling.logit_bias_eog.end()); + } + if (params.sampling.penalty_last_n == -1) { LOG_INF("%s: setting penalty_last_n to ctx_size = %d\n", __func__, llama_n_ctx(lctx)); params.sampling.penalty_last_n = llama_n_ctx(lctx); @@ -1107,6 +1132,7 @@ struct llama_model_params common_model_p mparams.use_mmap = params.use_mmap; mparams.use_mlock = params.use_mlock; mparams.check_tensors = params.check_tensors; + mparams.use_extra_bufts = !params.no_extra_bufts; if (params.kv_overrides.empty()) { mparams.kv_overrides = NULL; @@ -1149,14 +1175,14 @@ struct llama_context_params common_conte cparams.yarn_orig_ctx = params.yarn_orig_ctx; cparams.pooling_type = params.pooling_type; cparams.attention_type = params.attention_type; - cparams.defrag_thold = params.defrag_thold; + cparams.flash_attn_type = params.flash_attn_type; cparams.cb_eval = params.cb_eval; cparams.cb_eval_user_data = params.cb_eval_user_data; cparams.offload_kqv = !params.no_kv_offload; - cparams.flash_attn = params.flash_attn; cparams.no_perf = params.no_perf; cparams.op_offload = !params.no_op_offload; cparams.swa_full = params.swa_full; + cparams.kv_unified = params.kv_unified; cparams.type_k = params.cache_type_k; cparams.type_v = params.cache_type_v; @@ -1548,3 +1574,56 @@ ggml_opt_dataset_t common_opt_dataset_in return result; } + +ggml_opt_optimizer_params common_opt_lr_pars(void * userdata) { + ggml_opt_optimizer_params result = ggml_opt_get_default_optimizer_params(nullptr); + const lr_opt & d = *(lr_opt *) userdata; + result.adamw.alpha = result.sgd.alpha = d.get_lr(d.epoch); + result.sgd.wd = result.adamw.wd = d.wd; + return result; +} + +// TODO make all command line args case-insensitive +static inline bool eq_case_insensitive(char const* a, char const* b) { + return ! +#if defined(_MSC_VER) + _stricmp +#else + strcasecmp +#endif // defined(_MSC_VER) + (a, b); +} + +enum ggml_opt_optimizer_type common_opt_get_optimizer(const char * n) { + if (eq_case_insensitive("adamw", n)) { + return GGML_OPT_OPTIMIZER_TYPE_ADAMW; + } + if (eq_case_insensitive("sgd", n)) { + return GGML_OPT_OPTIMIZER_TYPE_SGD; + } + return GGML_OPT_OPTIMIZER_TYPE_COUNT; +} + +// TODO simplify to use just log and exp +static float const k_log_2 = std::log(2.f); + +void lr_opt::init() { + if (lr_min > 0 && lr_min < lr0) { + float nhalf = std::log(lr0 / lr_min) / k_log_2; + float e = epochs; + if (decay_epochs > 0 && decay_epochs < e) { + e = decay_epochs; + } else { + decay_epochs = e; + } + scale_epoch = nhalf / e; + } +} + +float lr_opt::get_lr(float epoch) const { + float r = lr_min <= 0 ? lr0 : + epoch >= decay_epochs ? lr_min : + lr0 * std::pow(0.5f, epoch * scale_epoch); + LOG_INF("epoch %.2g lr=%.2g\n", epoch, r); + return r; +} diff -pruN 5882+dfsg-2/common/common.h 6641+dfsg-2/common/common.h --- 5882+dfsg-2/common/common.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/common.h 2025-09-30 07:36:33.000000000 +0000 @@ -2,14 +2,17 @@ #pragma once -#include "llama-cpp.h" - #include +#include #include #include #include #include #include +#include + +#include "ggml-opt.h" +#include "llama-cpp.h" #ifdef _WIN32 #define DIRECTORY_SEPARATOR '\\' @@ -31,6 +34,9 @@ struct common_adapter_lora_info { std::string path; float scale; + std::string task_name; + std::string prompt_prefix; + struct llama_adapter_lora * ptr; }; @@ -81,6 +87,8 @@ enum llama_example { LLAMA_EXAMPLE_LOOKUP, LLAMA_EXAMPLE_PARALLEL, LLAMA_EXAMPLE_TTS, + LLAMA_EXAMPLE_DIFFUSION, + LLAMA_EXAMPLE_FINETUNE, LLAMA_EXAMPLE_COUNT, }; @@ -177,17 +185,19 @@ struct common_params_sampling { std::vector grammar_triggers; // optional triggers (for lazy grammars) std::set preserved_tokens; - std::vector logit_bias; // logit biases to apply + std::vector logit_bias; // logit biases to apply + std::vector logit_bias_eog; // pre-calculated logit biases for EOG tokens // print the parameters into a string std::string print() const; }; struct common_params_model { - std::string path = ""; // model local path // NOLINT - std::string url = ""; // model url to download // NOLINT - std::string hf_repo = ""; // HF repo // NOLINT - std::string hf_file = ""; // HF file // NOLINT + std::string path = ""; // model local path // NOLINT + std::string url = ""; // model url to download // NOLINT + std::string hf_repo = ""; // HF repo // NOLINT + std::string hf_file = ""; // HF file // NOLINT + std::string docker_repo = ""; // Docker repo // NOLINT }; struct common_params_speculative { @@ -199,6 +209,8 @@ struct common_params_speculative { int32_t n_gpu_layers = -1; // number of layers to store in VRAM for the draft model (-1 - use default) float p_split = 0.1f; // speculative decoding split probability float p_min = 0.75f; // minimum speculative decoding probability (greedy) + std::vector> replacements; // main to speculative model replacements + std::vector tensor_buft_overrides; ggml_type cache_type_k = GGML_TYPE_F16; // KV cache data type for the K ggml_type cache_type_v = GGML_TYPE_F16; // KV cache data type for the V @@ -217,12 +229,50 @@ struct common_params_vocoder { bool use_guide_tokens = false; // enable guide tokens to improve TTS accuracy // NOLINT }; +struct common_params_diffusion { + int32_t steps = 128; + bool visual_mode = false; + + float eps = 0; // epsilon for timesteps + int32_t block_length = 0; // block length for generation + + int32_t algorithm = 4; // default algorithm: low-confidence + float alg_temp = 0.0f; // algorithm temperature + + float cfg_scale = 0; // classifier-free guidance scale + bool add_gumbel_noise = false; // add gumbel noise to the logits if temp > 0.0 +}; + +// reasoning API response format (not to be confused as chat template's reasoning format) enum common_reasoning_format { COMMON_REASONING_FORMAT_NONE, + COMMON_REASONING_FORMAT_AUTO, // Same as deepseek, using `message.reasoning_content` COMMON_REASONING_FORMAT_DEEPSEEK_LEGACY, // Extract thinking tag contents and return as `message.reasoning_content`, or leave inline in tags in stream mode COMMON_REASONING_FORMAT_DEEPSEEK, // Extract thinking tag contents and return as `message.reasoning_content`, including in streaming deltas. + // do not extend this enum unless you absolutely have to + // in most cases, use COMMON_REASONING_FORMAT_AUTO + // see: https://github.com/ggml-org/llama.cpp/pull/15408 }; + +struct lr_opt { + float lr0 = 1e-5; // learning rate at first epoch + float lr_min = -1; + float decay_epochs = -1; // if >0, the learning rate starts at lr0 and decays to lr_min after this many epochs + float scale_epoch = 0; + float wd = 0; + unsigned epochs = 2; + + unsigned epoch; // set by optimizer outer (epochs) loop + // learning rate decay - constant LR per epoch only for now + float get_lr(float e) const; + float get_lr() const { return get_lr(epoch); } + // must call after arg parse, before get_lr + void init(); +}; + +struct ggml_opt_optimizer_params common_opt_lr_pars(void * userdata); + struct common_params { int32_t n_predict = -1; // new tokens to predict int32_t n_ctx = 4096; // context size @@ -238,11 +288,10 @@ struct common_params { float rope_freq_base = 0.0f; // RoPE base frequency float rope_freq_scale = 0.0f; // RoPE frequency scaling factor float yarn_ext_factor = -1.0f; // YaRN extrapolation mix factor - float yarn_attn_factor = 1.0f; // YaRN magnitude scaling factor - float yarn_beta_fast = 32.0f; // YaRN low correction dim - float yarn_beta_slow = 1.0f; // YaRN high correction dim + float yarn_attn_factor = -1.0f; // YaRN magnitude scaling factor + float yarn_beta_fast = -1.0f; // YaRN low correction dim + float yarn_beta_slow = -1.0f; // YaRN high correction dim int32_t yarn_orig_ctx = 0; // YaRN original context length - float defrag_thold = 0.1f; // KV cache defragmentation threshold // offload params std::vector devices; // devices to use for offloading @@ -264,10 +313,12 @@ struct common_params { enum llama_rope_scaling_type rope_scaling_type = LLAMA_ROPE_SCALING_TYPE_UNSPECIFIED; enum llama_pooling_type pooling_type = LLAMA_POOLING_TYPE_UNSPECIFIED; // pooling type for embeddings enum llama_attention_type attention_type = LLAMA_ATTENTION_TYPE_UNSPECIFIED; // attention type for embeddings + enum llama_flash_attn_type flash_attn_type = LLAMA_FLASH_ATTN_TYPE_AUTO; // whether to use Flash Attention struct common_params_sampling sampling; struct common_params_speculative speculative; struct common_params_vocoder vocoder; + struct common_params_diffusion diffusion; struct common_params_model model; @@ -326,10 +377,10 @@ struct common_params { bool multiline_input = false; // reverse the usage of `\` bool simple_io = false; // improves compatibility with subprocesses and limited consoles bool cont_batching = true; // insert new sequences for decoding on-the-fly - bool flash_attn = false; // flash attention bool no_perf = false; // disable performance metrics - bool ctx_shift = true; // context shift on inifinite text generation + bool ctx_shift = false; // context shift on infinite text generation bool swa_full = false; // use full-size SWA cache (https://github.com/ggml-org/llama.cpp/pull/13194#issuecomment-2868343055) + bool kv_unified = false; // enable unified KV cache bool input_prefix_bos = false; // prefix BOS to user inputs, preceding input_prefix bool use_mmap = true; // use mmap for faster loads @@ -340,6 +391,7 @@ struct common_params { bool warmup = true; // warmup run bool check_tensors = false; // validate tensor data bool no_op_offload = false; // globally disable offload host tensor operations to device + bool no_extra_bufts = false; // disable extra buffer types (used for weight repacking) bool single_turn = false; // single turn chat conversation @@ -354,6 +406,11 @@ struct common_params { bool no_mmproj = false; // explicitly disable multimodal model std::vector image; // path to image file(s) + // finetune + struct lr_opt lr; + enum ggml_opt_optimizer_type optimizer = GGML_OPT_OPTIMIZER_TYPE_ADAMW; + float val_split = 0.05f; // fraction of the data used for the validation set + // embedding bool embedding = false; // get only sentence embedding int32_t embd_normalize = 2; // normalisation for embeddings (-1=none, 0=max absolute int16, 1=taxicab, 2=euclidean, >2=p-norm) @@ -362,11 +419,12 @@ struct common_params { std::string cls_sep = "\t"; // separator of classification sequences // server params - int32_t port = 8080; // server listens on this network port - int32_t timeout_read = 600; // http read timeout in seconds - int32_t timeout_write = timeout_read; // http write timeout in seconds - int32_t n_threads_http = -1; // number of threads to process HTTP requests (TODO: support threadpool) - int32_t n_cache_reuse = 0; // min chunk size to reuse from the cache via KV shifting + int32_t port = 8080; // server listens on this network port + int32_t timeout_read = 600; // http read timeout in seconds + int32_t timeout_write = timeout_read; // http write timeout in seconds + int32_t n_threads_http = -1; // number of threads to process HTTP requests (TODO: support threadpool) + int32_t n_cache_reuse = 0; // min chunk size to reuse from the cache via KV shifting + int32_t n_swa_checkpoints = 3; // max number of SWA checkpoints per slot std::string hostname = "127.0.0.1"; std::string public_path = ""; // NOLINT @@ -374,7 +432,7 @@ struct common_params { std::string chat_template = ""; // NOLINT bool use_jinja = false; // NOLINT bool enable_chat_template = true; - common_reasoning_format reasoning_format = COMMON_REASONING_FORMAT_DEEPSEEK; + common_reasoning_format reasoning_format = COMMON_REASONING_FORMAT_AUTO; int reasoning_budget = -1; bool prefill_assistant = true; // if true, any trailing assistant message will be prefilled into the response @@ -387,7 +445,7 @@ struct common_params { // "advanced" endpoints are disabled by default for better security bool webui = true; - bool endpoint_slots = false; + bool endpoint_slots = true; bool endpoint_props = false; // only control POST requests, not GET bool endpoint_metrics = false; @@ -395,7 +453,7 @@ struct common_params { std::string slot_save_path; - float slot_prompt_similarity = 0.5f; + float slot_prompt_similarity = 0.1f; // batched-bench params bool is_pp_shared = false; @@ -419,10 +477,12 @@ struct common_params { int32_t n_out_freq = 10; // output the imatrix every n_out_freq iterations int32_t n_save_freq = 0; // save the imatrix every n_save_freq iterations int32_t i_chunk = 0; // start processing from this chunk + int8_t imat_dat = 0; // whether the legacy imatrix.dat format should be output (gguf <= 0 < dat) - bool process_output = false; // collect data for the output tensor - bool compute_ppl = true; // whether to compute perplexity - bool parse_special = false; // whether to parse special tokens during imatrix tokenization + bool process_output = false; // collect data for the output tensor + bool compute_ppl = true; // whether to compute perplexity + bool show_statistics = false; // show imatrix statistics per tensor + bool parse_special = false; // whether to parse special tokens during imatrix tokenization // cvector-generator params int n_pca_batch = 100; @@ -522,6 +582,7 @@ static bool string_starts_with(const std // While we wait for C++20's std::string::ends_with... bool string_ends_with(const std::string_view & str, const std::string_view & suffix); +bool string_remove_suffix(std::string & str, const std::string_view & suffix); size_t string_find_partial_stop(const std::string_view & str, const std::string_view & stop); bool string_parse_kv_override(const char * data, std::vector & overrides); @@ -674,7 +735,24 @@ const char * const LLM_KV_SPLIT_TENSORS_ } // +// MoE utils +// + +const char * const LLM_FFN_EXPS_REGEX = "\\.ffn_(up|down|gate)_(ch|)exps"; + +static std::string llm_ffn_exps_block_regex(int idx) { + return string_format("blk\\.%d%s", idx, LLM_FFN_EXPS_REGEX); +} + +static llama_model_tensor_buft_override llm_ffn_exps_cpu_override() { + return { LLM_FFN_EXPS_REGEX, ggml_backend_cpu_buffer_type() }; +} + +// // training utils // ggml_opt_dataset_t common_opt_dataset_init(struct llama_context * ctx, const std::vector & tokens, int64_t stride); + +// "adamw" or "sgd" (case insensitive) +enum ggml_opt_optimizer_type common_opt_get_optimizer(const char *); diff -pruN 5882+dfsg-2/common/json-schema-to-grammar.cpp 6641+dfsg-2/common/json-schema-to-grammar.cpp --- 5882+dfsg-2/common/json-schema-to-grammar.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/json-schema-to-grammar.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -257,12 +257,13 @@ std::unordered_map RESERVED_NAMES; - if (RESERVED_NAMES.empty()) { - RESERVED_NAMES.insert("root"); - for (const auto &p : PRIMITIVE_RULES) RESERVED_NAMES.insert(p.first); - for (const auto &p : STRING_FORMAT_RULES) RESERVED_NAMES.insert(p.first); - } + static const std::unordered_set RESERVED_NAMES = [] { + std::unordered_set s; + s.insert("root"); + for (const auto & p : PRIMITIVE_RULES) s.insert(p.first); + for (const auto & p : STRING_FORMAT_RULES) s.insert(p.first); + return s; + }(); return RESERVED_NAMES.find(name) != RESERVED_NAMES.end(); } @@ -843,9 +844,10 @@ public: _build_object_rule( properties, required, name, schema.contains("additionalProperties") ? schema["additionalProperties"] : json())); - } else if ((schema_type.is_null() || schema_type == "object") && schema.contains("allOf")) { + } else if ((schema_type.is_null() || schema_type == "object" || schema_type == "string") && schema.contains("allOf")) { std::unordered_set required; std::vector> properties; + std::map enum_values; std::string hybrid_name = name; std::function add_component = [&](const json & comp_schema, bool is_required) { if (comp_schema.contains("$ref")) { @@ -857,6 +859,14 @@ public: required.insert(prop.key()); } } + } else if (comp_schema.contains("enum")) { + for (const auto & v : comp_schema["enum"]) { + const auto rule = _generate_constant_rule(v); + if (enum_values.find(rule) == enum_values.end()) { + enum_values[rule] = 0; + } + enum_values[rule] += 1; + } } else { // todo warning } @@ -870,6 +880,17 @@ public: add_component(t, true); } } + if (!enum_values.empty()) { + std::vector enum_intersection; + for (const auto & p : enum_values) { + if (p.second == schema["allOf"].size()) { + enum_intersection.push_back(p.first); + } + } + if (!enum_intersection.empty()) { + return _add_rule(rule_name, "(" + string_join(enum_intersection, " | ") + ") space"); + } + } return _add_rule(rule_name, _build_object_rule(properties, required, hybrid_name, json())); } else if ((schema_type.is_null() || schema_type == "array") && (schema.contains("items") || schema.contains("prefixItems"))) { json items = schema.contains("items") ? schema["items"] : schema["prefixItems"]; diff -pruN 5882+dfsg-2/common/log.cpp 6641+dfsg-2/common/log.cpp --- 5882+dfsg-2/common/log.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/log.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -4,17 +4,52 @@ #include #include #include +#include +#include #include #include #include #include +#if defined(_WIN32) +# include +# include +# define isatty _isatty +# define fileno _fileno +#else +# include +#endif // defined(_WIN32) + int common_log_verbosity_thold = LOG_DEFAULT_LLAMA; void common_log_set_verbosity_thold(int verbosity) { common_log_verbosity_thold = verbosity; } +// Auto-detect if colors should be enabled based on terminal and environment +static bool common_log_should_use_colors_auto() { + // Check NO_COLOR environment variable (https://no-color.org/) + if (const char * no_color = std::getenv("NO_COLOR")) { + if (no_color[0] != '\0') { + return false; + } + } + + // Check TERM environment variable + if (const char * term = std::getenv("TERM")) { + if (std::strcmp(term, "dumb") == 0) { + return false; + } + } + + // Check if stdout and stderr are connected to a terminal + // We check both because log messages can go to either + bool stdout_is_tty = isatty(fileno(stdout)); + bool stderr_is_tty = isatty(fileno(stderr)); + + return stdout_is_tty || stderr_is_tty; +} + static int64_t t_us() { return std::chrono::duration_cast(std::chrono::system_clock::now().time_since_epoch()).count(); } @@ -353,6 +388,11 @@ struct common_log * common_log_init() { struct common_log * common_log_main() { static struct common_log log; + static std::once_flag init_flag; + std::call_once(init_flag, [&]() { + // Set default to auto-detect colors + log.set_colors(common_log_should_use_colors_auto()); + }); return &log; } @@ -380,8 +420,19 @@ void common_log_set_file(struct common_l log->set_file(file); } -void common_log_set_colors(struct common_log * log, bool colors) { - log->set_colors(colors); +void common_log_set_colors(struct common_log * log, log_colors colors) { + if (colors == LOG_COLORS_AUTO) { + log->set_colors(common_log_should_use_colors_auto()); + return; + } + + if (colors == LOG_COLORS_DISABLED) { + log->set_colors(false); + return; + } + + GGML_ASSERT(colors == LOG_COLORS_ENABLED); + log->set_colors(true); } void common_log_set_prefix(struct common_log * log, bool prefix) { diff -pruN 5882+dfsg-2/common/log.h 6641+dfsg-2/common/log.h --- 5882+dfsg-2/common/log.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/log.h 2025-09-30 07:36:33.000000000 +0000 @@ -24,6 +24,12 @@ #define LOG_DEFAULT_DEBUG 1 #define LOG_DEFAULT_LLAMA 0 +enum log_colors { + LOG_COLORS_AUTO = -1, + LOG_COLORS_DISABLED = 0, + LOG_COLORS_ENABLED = 1, +}; + // needed by the LOG_TMPL macro to avoid computing log arguments if the verbosity lower // set via common_log_set_verbosity() extern int common_log_verbosity_thold; @@ -65,10 +71,10 @@ void common_log_add(struct common_log * // D - debug (stderr, V = LOG_DEFAULT_DEBUG) // -void common_log_set_file (struct common_log * log, const char * file); // not thread-safe -void common_log_set_colors (struct common_log * log, bool colors); // not thread-safe -void common_log_set_prefix (struct common_log * log, bool prefix); // whether to output prefix to each log -void common_log_set_timestamps(struct common_log * log, bool timestamps); // whether to output timestamps in the prefix +void common_log_set_file (struct common_log * log, const char * file); // not thread-safe +void common_log_set_colors (struct common_log * log, log_colors colors); // not thread-safe +void common_log_set_prefix (struct common_log * log, bool prefix); // whether to output prefix to each log +void common_log_set_timestamps(struct common_log * log, bool timestamps); // whether to output timestamps in the prefix // helper macros for logging // use these to avoid computing log arguments if the verbosity of the log is higher than the threshold diff -pruN 5882+dfsg-2/common/sampling.cpp 6641+dfsg-2/common/sampling.cpp --- 5882+dfsg-2/common/sampling.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/sampling.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -332,6 +332,7 @@ void common_perf_print(const struct llam } if (ctx) { llama_perf_context_print(ctx); + llama_memory_breakdown_print(ctx); } } @@ -426,8 +427,29 @@ uint32_t common_sampler_get_seed(const s // helpers -llama_token_data_array * common_sampler_get_candidates(struct common_sampler * gsmpl) { - return &gsmpl->cur_p; +llama_token_data_array * common_sampler_get_candidates(struct common_sampler * gsmpl, bool do_sort) { + auto * res = &gsmpl->cur_p; + + if (do_sort && !res->sorted) { + // remember the selected token before sorting + const llama_token id = res->data[res->selected].id; + + std::sort(res->data, res->data + res->size, [](const llama_token_data & a, const llama_token_data & b) { + return a.p > b.p; + }); + + // restore the selected token after sorting + for (size_t i = 0; i < res->size; ++i) { + if (res->data[i].id == id) { + res->selected = i; + break; + } + } + + res->sorted = true; + } + + return res; } llama_token common_sampler_last(const struct common_sampler * gsmpl) { diff -pruN 5882+dfsg-2/common/sampling.h 6641+dfsg-2/common/sampling.h --- 5882+dfsg-2/common/sampling.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/sampling.h 2025-09-30 07:36:33.000000000 +0000 @@ -86,7 +86,9 @@ uint32_t common_sampler_get_seed(const s // helpers // access the internal list of current candidate tokens -llama_token_data_array * common_sampler_get_candidates(struct common_sampler * gsmpl); +// if do_sort == true, the candidates are guaranteed to be sorted afterwards (in descending order of probability) +// the .sorted flag of the result indicates whether the returned candidates are sorted +llama_token_data_array * common_sampler_get_candidates(struct common_sampler * gsmpl, bool do_sort); // get the last accepted token llama_token common_sampler_last(const struct common_sampler * gsmpl); diff -pruN 5882+dfsg-2/common/speculative.cpp 6641+dfsg-2/common/speculative.cpp --- 5882+dfsg-2/common/speculative.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/speculative.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -1,30 +1,39 @@ #include "speculative.h" +#include "ggml.h" +#include "llama.h" #include "log.h" #include "common.h" #include "sampling.h" #include #include +#include #define SPEC_VOCAB_MAX_SIZE_DIFFERENCE 128 #define SPEC_VOCAB_CHECK_START_TOKEN_ID 5 struct common_speculative { - struct llama_context * ctx; + struct llama_context * ctx_tgt; // only used for retokenizing from ctx_dft + struct llama_context * ctx_dft; struct common_sampler * smpl; llama_batch batch; - llama_tokens prompt; + llama_tokens prompt_dft; + bool vocab_dft_compatible = true; // whether retokenization is needed + std::map tgt_dft_replacements = {}; }; struct common_speculative * common_speculative_init( + struct llama_context * ctx_tgt, struct llama_context * ctx_dft) { auto * result = new common_speculative { - /* .ctx = */ ctx_dft, - /* .smpl = */ nullptr, - /* .batch = */ llama_batch_init(llama_n_batch(ctx_dft), 0, 1), - /* .prompt = */ {}, + /* .ctx_tgt = */ ctx_tgt, + /* .ctx_dft = */ ctx_dft, + /* .smpl = */ nullptr, + /* .batch = */ llama_batch_init(llama_n_batch(ctx_dft), 0, 1), + /* .prompt_dft = */ {}, + /* .vocab_dft_compatible = */ false, }; // TODO: optimize or pass from outside? @@ -59,6 +68,9 @@ struct common_speculative * common_specu } #endif + result->vocab_dft_compatible = common_speculative_are_compatible(ctx_tgt, ctx_dft); + LOG_DBG("vocab_dft_compatible = %d\n", result->vocab_dft_compatible); + return result; } @@ -75,8 +87,8 @@ void common_speculative_free(struct comm } bool common_speculative_are_compatible( - const struct llama_context * ctx_tgt, - const struct llama_context * ctx_dft) { + const struct llama_context * ctx_tgt, + const struct llama_context * ctx_dft) { const struct llama_model * model_tgt = llama_get_model(ctx_tgt); const struct llama_model * model_dft = llama_get_model(ctx_dft); @@ -90,31 +102,32 @@ bool common_speculative_are_compatible( LOG_DBG("%s: vocab_type dft: %d\n", __func__, vocab_type_dft); if (vocab_type_tgt != vocab_type_dft) { - LOG_ERR("%s: draft model vocab type must match target model to use speculation but " - "vocab_type_dft = %d while vocab_type_tgt = %d\n", __func__, vocab_type_dft, vocab_type_tgt); + LOG_DBG("%s: draft model vocab type must match target model to use speculation but ", __func__); + LOG_DBG("vocab_type_dft = %d while vocab_type_tgt = %d\n", vocab_type_dft, vocab_type_tgt); return false; } - if (llama_vocab_get_add_bos(vocab_tgt) != llama_vocab_get_add_bos(vocab_dft) || + if ( + llama_vocab_get_add_bos(vocab_tgt) != llama_vocab_get_add_bos(vocab_dft) || llama_vocab_get_add_eos(vocab_tgt) != llama_vocab_get_add_eos(vocab_dft) || llama_vocab_bos(vocab_tgt) != llama_vocab_bos(vocab_dft) || - llama_vocab_eos(vocab_tgt) != llama_vocab_eos(vocab_dft)) { - LOG_ERR("%s: draft vocab special tokens must match target vocab to use speculation\n", __func__); - LOG_ERR("%s: tgt: bos = %d (%d), eos = %d (%d)\n", __func__, llama_vocab_bos(vocab_tgt), llama_vocab_get_add_bos(vocab_tgt), llama_vocab_eos(vocab_tgt), llama_vocab_get_add_eos(vocab_tgt)); - LOG_ERR("%s: dft: bos = %d (%d), eos = %d (%d)\n", __func__, llama_vocab_bos(vocab_dft), llama_vocab_get_add_bos(vocab_dft), llama_vocab_eos(vocab_dft), llama_vocab_get_add_eos(vocab_dft)); + llama_vocab_eos(vocab_tgt) != llama_vocab_eos(vocab_dft) + ) { + LOG_DBG("%s: draft model special tokens must match target model to use speculation\n", __func__); return false; } { const int n_vocab_tgt = llama_vocab_n_tokens(vocab_tgt); const int n_vocab_dft = llama_vocab_n_tokens(vocab_dft); - - const int vocab_diff = std::abs(n_vocab_tgt - n_vocab_dft); + const int vocab_diff = n_vocab_tgt > n_vocab_dft + ? n_vocab_tgt - n_vocab_dft + : n_vocab_dft - n_vocab_tgt; if (vocab_diff > SPEC_VOCAB_MAX_SIZE_DIFFERENCE) { - LOG_ERR("%s: draft model vocab must closely match target model to use speculation but " - "target vocab size %d does not match draft vocab size %d - difference %d, max allowed %d\n", - __func__, n_vocab_tgt, llama_vocab_n_tokens(vocab_dft), vocab_diff, SPEC_VOCAB_MAX_SIZE_DIFFERENCE); + LOG_DBG("%s: draft model vocab must closely match target model to use speculation but ", __func__); + LOG_DBG("target vocab size %d does not match draft vocab size %d - difference %d, max allowed %d\n", + n_vocab_tgt, llama_vocab_n_tokens(vocab_dft), vocab_diff, SPEC_VOCAB_MAX_SIZE_DIFFERENCE); return false; } @@ -122,8 +135,8 @@ bool common_speculative_are_compatible( const char * token_text_tgt = llama_vocab_get_text(vocab_tgt, i); const char * token_text_dft = llama_vocab_get_text(vocab_dft, i); if (std::strcmp(token_text_tgt, token_text_dft) != 0) { - LOG_ERR("%s: draft vocab vocab must match target vocab to use speculation but " - "token %d content differs - target '%s', draft '%s'\n", __func__, i, + LOG_DBG("%s: draft model vocab must match target model to use speculation but ", __func__); + LOG_DBG("token %d content differs - target '%s', draft '%s'\n", i, common_token_to_piece(ctx_tgt, i).c_str(), common_token_to_piece(ctx_dft, i).c_str()); return false; @@ -134,32 +147,93 @@ bool common_speculative_are_compatible( return true; } +void common_speculative_add_replacement_tgt_dft( + struct common_speculative * spec, + const char *source, const char *dest) { + spec->tgt_dft_replacements[source] = dest; +} + +static std::string replace_to_dft( + struct common_speculative * spec, + const std::string& input) { + std::string result = input; + for (const auto & pair : spec->tgt_dft_replacements) { + size_t pos = result.find(pair.first); + while (pos != std::string::npos) { + result.replace(pos, pair.first.length(), pair.second); + pos = result.find(pair.first, pos + pair.second.length()); + } + } + return result; +} + +static std::string replace_to_tgt( + struct common_speculative * spec, + const std::string& input) { + std::string result = input; + for (const auto& pair : spec->tgt_dft_replacements) { + size_t pos = result.find(pair.second); + while (pos != std::string::npos) { + result.replace(pos, pair.second.length(), pair.first); + pos = result.find(pair.second, pos + pair.first.length()); + } + } + return result; +} + + llama_tokens common_speculative_gen_draft( struct common_speculative * spec, struct common_speculative_params params, - const llama_tokens & prompt_tgt, + const llama_tokens & prompt_tgt_main_model, // specified in target model vocab llama_token id_last) { auto & batch = spec->batch; - auto & ctx = spec->ctx; + auto & ctx_tgt = spec->ctx_tgt; + auto & ctx_dft = spec->ctx_dft; auto & smpl = spec->smpl; - auto & prompt = spec->prompt; + auto & prompt_dft = spec->prompt_dft; - auto * mem = llama_get_memory(ctx); + auto * mem_dft = llama_get_memory(ctx_dft); int reuse_i = 0; int reuse_n = 0; - const int n_ctx = llama_n_ctx(ctx) - params.n_draft; + const int n_ctx = llama_n_ctx(ctx_dft) - params.n_draft; + + llama_tokens prompt_tgt_draft_model; + if (!spec->vocab_dft_compatible) { + std::string text; + text = common_detokenize(ctx_tgt, prompt_tgt_main_model, true); + text = replace_to_dft(spec, text); + LOG_DBG("%s: main->draft detokenized string: '%s'\n", __func__, text.c_str()); + prompt_tgt_draft_model = common_tokenize(ctx_dft, text, false, true); + + // convert id_last to draft vocab. llama_detokenize is called directly to avoid an allocation + const auto * model_tgt = llama_get_model(ctx_tgt); + const auto * vocab_tgt = llama_model_get_vocab(model_tgt); + + int32_t n_chars = llama_detokenize(vocab_tgt, &id_last, 1, nullptr, 0, false, false); + GGML_ASSERT(n_chars < 0 && "failed to detokenize id_last"); + text.resize(-n_chars); + llama_detokenize(vocab_tgt, &id_last, 1, text.data(), text.size(), false, false); + text = replace_to_dft(spec, text); + + LOG_DBG("main->draft detokenized id_last(%d): '%s'\n", id_last, text.c_str()); + id_last = common_tokenize(ctx_dft, text, false, true)[0]; + } + // prompt_tgt's tokens will always be compatible with ctx_dft + const llama_tokens &prompt_tgt = + spec->vocab_dft_compatible ? prompt_tgt_main_model : prompt_tgt_draft_model; const int i_start = std::max(0, (int) prompt_tgt.size() - n_ctx); // reuse as much as possible from the old draft context // ideally, the draft context should be as big as the target context and we will always reuse the entire prompt - for (int i = 0; i < (int) prompt.size(); ++i) { + for (int i = 0; i < (int) prompt_dft.size(); ++i) { int cur = 0; while (i_start + cur < (int) prompt_tgt.size() && - i + cur < (int) prompt.size() && - prompt_tgt[i_start + cur] == prompt[i + cur]) { + i + cur < (int) prompt_dft.size() && + prompt_tgt[i_start + cur] == prompt_dft[i + cur]) { cur++; } @@ -169,21 +243,20 @@ llama_tokens common_speculative_gen_draf } } - LOG_DBG("%s: reuse_i = %d, reuse_n = %d, prompt = %d\n", __func__, reuse_i, reuse_n, (int) prompt.size()); + LOG_DBG("%s: reuse_i = %d, reuse_n = %d, prompt = %d\n", __func__, reuse_i, reuse_n, (int) prompt_dft.size()); llama_tokens result; result.reserve(params.n_draft); if (reuse_n == 0) { - llama_memory_clear(mem, false); - - prompt.clear(); + llama_memory_clear(mem_dft, false); + prompt_dft.clear(); } else { // this happens when a previous draft has been discarded (for example, due to being too small), but the // target model agreed with it. in this case, we simply pass back the previous results to save compute - if (reuse_i + reuse_n < (int) prompt.size() && prompt[reuse_i + reuse_n] == id_last) { - for (int i = reuse_i + reuse_n + 1; i < (int) prompt.size(); ++i) { - result.push_back(prompt[i]); + if (reuse_i + reuse_n < (int) prompt_dft.size() && prompt_dft[reuse_i + reuse_n] == id_last) { + for (int i = reuse_i + reuse_n + 1; i < (int) prompt_dft.size(); ++i) { + result.push_back(prompt_dft[i]); if (params.n_draft <= (int) result.size()) { break; @@ -194,16 +267,15 @@ llama_tokens common_speculative_gen_draf } if (reuse_i > 0) { - llama_memory_seq_rm (mem, 0, 0, reuse_i); - llama_memory_seq_add(mem, 0, reuse_i, -1, -reuse_i); + llama_memory_seq_rm (mem_dft, 0, 0, reuse_i); + llama_memory_seq_add(mem_dft, 0, reuse_i, -1, -reuse_i); - prompt.erase(prompt.begin(), prompt.begin() + reuse_i); + prompt_dft.erase(prompt_dft.begin(), prompt_dft.begin() + reuse_i); } - if (reuse_n < (int) prompt.size()) { - llama_memory_seq_rm (mem, 0, reuse_n, -1); - - prompt.erase(prompt.begin() + reuse_n, prompt.end()); + if (reuse_n < (int) prompt_dft.size()) { + llama_memory_seq_rm (mem_dft, 0, reuse_n, -1); + prompt_dft.erase(prompt_dft.begin() + reuse_n, prompt_dft.end()); } } @@ -214,28 +286,28 @@ llama_tokens common_speculative_gen_draf //LOG_DBG("i = %d, i_start = %d, reuse_n = %d, i - i_start = %d, id = %6d\n", i, i_start, reuse_n, i - i_start, prompt_tgt[i]); common_batch_add(batch, prompt_tgt[i], i - i_start, { 0 }, false); - prompt.push_back(prompt_tgt[i]); + prompt_dft.push_back(prompt_tgt[i]); } // we should rarely end-up here during normal decoding if (batch.n_tokens > 0) { //LOG_DBG("%s: draft prompt batch: %s\n", __func__, string_from(ctx, batch).c_str()); - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); } - const llama_pos n_past = prompt.size(); + const llama_pos n_past = prompt_dft.size(); LOG_DBG("%s: n_past = %d\n", __func__, n_past); common_batch_clear(batch); common_batch_add (batch, id_last, n_past, { 0 }, true); - prompt.push_back(id_last); + prompt_dft.push_back(id_last); - //LOG_DBG("%s: draft prompt: %s\n", __func__, string_from(ctx, prompt).c_str()); + LOG_DBG("%s: draft prompt: %s\n", __func__, string_from(ctx_dft, prompt_dft).c_str()); - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); common_sampler_reset(smpl); @@ -243,13 +315,13 @@ llama_tokens common_speculative_gen_draf for (int i = 0; i < params.n_draft; ++i) { common_batch_clear(batch); - common_sampler_sample(smpl, ctx, 0, true); + common_sampler_sample(smpl, ctx_dft, 0, true); - const auto * cur_p = common_sampler_get_candidates(smpl); + const auto * cur_p = common_sampler_get_candidates(smpl, true); for (int k = 0; k < std::min(3, (int) cur_p->size); ++k) { LOG_DBG(" - draft candidate %3d, pos %3d: %6d (%8.3f) '%s'\n", - k, i, cur_p->data[k].id, cur_p->data[k].p, common_token_to_piece(ctx, cur_p->data[k].id).c_str()); + k, i, cur_p->data[k].id, cur_p->data[k].p, common_token_to_piece(ctx_dft, cur_p->data[k].id).c_str()); } // add drafted token for each sequence @@ -271,10 +343,19 @@ llama_tokens common_speculative_gen_draf common_batch_add(batch, id, n_past + i + 1, { 0 }, true); // evaluate the drafted tokens on the draft model - llama_decode(ctx, batch); + llama_decode(ctx_dft, batch); - prompt.push_back(id); + prompt_dft.push_back(id); } + if (!spec->vocab_dft_compatible) { + std::string detokenized = common_detokenize(ctx_dft, result, true); + detokenized = replace_to_tgt(spec, detokenized); + LOG_DBG("draft->main detokenized string: '%s'\n", detokenized.c_str()); + result = common_tokenize(ctx_tgt, detokenized, false, true); + if (result.size() > (size_t)params.n_draft) { + result.resize(params.n_draft); + } + } return result; } diff -pruN 5882+dfsg-2/common/speculative.h 6641+dfsg-2/common/speculative.h --- 5882+dfsg-2/common/speculative.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/common/speculative.h 2025-09-30 07:36:33.000000000 +0000 @@ -12,7 +12,10 @@ struct common_speculative_params { float p_min = 0.75f; // min probability required to accept a token in the draft }; -struct common_speculative * common_speculative_init(struct llama_context * ctx_dft); +struct common_speculative * common_speculative_init( + struct llama_context * ctx_tgt, + struct llama_context * ctx_dft +); void common_speculative_free(struct common_speculative * spec); @@ -20,6 +23,10 @@ bool common_speculative_are_compatible( const struct llama_context * ctx_tgt, const struct llama_context * ctx_dft); +void common_speculative_add_replacement_tgt_dft( + struct common_speculative * spec, + const char *source, const char *dest); + // sample up to n_draft tokens and add them to the batch using the draft model llama_tokens common_speculative_gen_draft( struct common_speculative * spec, diff -pruN 5882+dfsg-2/convert_hf_to_gguf.py 6641+dfsg-2/convert_hf_to_gguf.py --- 5882+dfsg-2/convert_hf_to_gguf.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/convert_hf_to_gguf.py 2025-09-30 07:36:33.000000000 +0000 @@ -28,6 +28,14 @@ if TYPE_CHECKING: if 'NO_LOCAL_GGUF' not in os.environ: sys.path.insert(1, str(Path(__file__).parent / 'gguf-py')) import gguf +from gguf.vocab import MistralTokenizerType, MistralVocab +from mistral_common.tokens.tokenizers.base import TokenizerVersion +from mistral_common.tokens.tokenizers.multimodal import DATASET_MEAN, DATASET_STD +from mistral_common.tokens.tokenizers.tekken import Tekkenizer +from mistral_common.tokens.tokenizers.sentencepiece import ( + SentencePieceTokenizer, +) + logger = logging.getLogger("hf-to-gguf") @@ -64,6 +72,7 @@ class ModelBase: endianess: gguf.GGUFEndian use_temp_file: bool lazy: bool + dry_run: bool part_names: list[str] is_safetensors: bool hparams: dict[str, Any] @@ -81,11 +90,16 @@ class ModelBase: block_count: int tensor_map: gguf.TensorNameMap + # Mistral format specifics + is_mistral_format: bool = False + disable_mistral_community_chat_template: bool = False + def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, *, is_big_endian: bool = False, use_temp_file: bool = False, eager: bool = False, metadata_override: Path | None = None, model_name: str | None = None, split_max_tensors: int = 0, split_max_size: int = 0, dry_run: bool = False, - small_first_shard: bool = False, hparams: dict[str, Any] | None = None, remote_hf_model_id: str | None = None): + small_first_shard: bool = False, hparams: dict[str, Any] | None = None, remote_hf_model_id: str | None = None, + disable_mistral_community_chat_template: bool = False): if type(self) is ModelBase or \ type(self) is TextModel or \ type(self) is MmprojModel: @@ -98,6 +112,7 @@ class ModelBase: self.endianess = gguf.GGUFEndian.BIG if is_big_endian else gguf.GGUFEndian.LITTLE self.use_temp_file = use_temp_file self.lazy = not eager or (remote_hf_model_id is not None) + self.dry_run = dry_run self.remote_hf_model_id = remote_hf_model_id if remote_hf_model_id is not None: self.is_safetensors = True @@ -106,16 +121,17 @@ class ModelBase: logger.info(f"Using remote model with HuggingFace id: {remote_hf_model_id}") remote_tensors = gguf.utility.SafetensorRemote.get_list_tensors_hf_model(remote_hf_model_id) self.tensor_names = set(name for name in remote_tensors.keys()) - for name, remote_tensor in gguf.utility.SafetensorRemote.get_list_tensors_hf_model(remote_hf_model_id).items(): + for name, remote_tensor in remote_tensors.items(): yield (name, LazyTorchTensor.from_remote_tensor(remote_tensor)) self.get_tensors = get_remote_tensors else: - self.part_names = ModelBase.get_model_part_names(self.dir_model, "model", ".safetensors") + prefix = "model" if not self.is_mistral_format else "consolidated" + self.part_names = ModelBase.get_model_part_names(self.dir_model, prefix, ".safetensors") self.is_safetensors = len(self.part_names) > 0 if not self.is_safetensors: self.part_names = ModelBase.get_model_part_names(self.dir_model, "pytorch_model", ".bin") - self.hparams = ModelBase.load_hparams(self.dir_model) if hparams is None else hparams + self.hparams = ModelBase.load_hparams(self.dir_model, self.is_mistral_format) if hparams is None else hparams self.tensor_names = None self.metadata_override = metadata_override self.model_name = model_name @@ -136,6 +152,9 @@ class ModelBase: self.gguf_writer = gguf.GGUFWriter(path=None, arch=gguf.MODEL_ARCH_NAMES[self.model_arch], endianess=self.endianess, use_temp_file=self.use_temp_file, split_max_tensors=split_max_tensors, split_max_size=split_max_size, dry_run=dry_run, small_first_shard=small_first_shard) + # Mistral specific + self.disable_mistral_community_chat_template = disable_mistral_community_chat_template + @classmethod def add_prefix_to_filename(cls, path: Path, prefix: str) -> Path: stem, suffix = path.stem, path.suffix @@ -153,19 +172,23 @@ class ModelBase: def get_tensors(self) -> Iterator[tuple[str, Tensor]]: tensor_names_from_parts: set[str] = set() - index_name = "model.safetensors" if self.is_safetensors else "pytorch_model.bin" - index_name += ".index.json" - index_file = self.dir_model / index_name - - if index_file.is_file(): - self.tensor_names = set() - logger.info(f"gguf: loading model weight map from '{index_name}'") - with open(index_file, "r", encoding="utf-8") as f: - index: dict[str, Any] = json.load(f) - weight_map = index.get("weight_map") - if weight_map is None or not isinstance(weight_map, dict): - raise ValueError(f"Can't load 'weight_map' from {index_name!r}") - self.tensor_names.update(weight_map.keys()) + if not self.is_mistral_format: + index_name = "model.safetensors" if self.is_safetensors else "pytorch_model.bin" + index_name += ".index.json" + index_file = self.dir_model / index_name + + if index_file.is_file(): + self.tensor_names = set() + logger.info(f"gguf: loading model weight map from '{index_name}'") + with open(index_file, "r", encoding="utf-8") as f: + index: dict[str, Any] = json.load(f) + weight_map = index.get("weight_map") + if weight_map is None or not isinstance(weight_map, dict): + raise ValueError(f"Can't load 'weight_map' from {index_name!r}") + self.tensor_names.update(weight_map.keys()) + else: + self.tensor_names = tensor_names_from_parts + weight_map = {} else: self.tensor_names = tensor_names_from_parts weight_map = {} @@ -279,10 +302,6 @@ class ModelBase: # data = data_torch.squeeze().numpy() data = data_torch.numpy() - # if data ends up empty, it means data_torch was a scalar tensor -> restore - if len(data.shape) == 0: - data = data_torch.numpy() - n_dims = len(data.shape) data_qtype: gguf.GGMLQuantizationType | bool = self.tensor_force_quant(name, new_name, bid, n_dims) @@ -426,7 +445,12 @@ class ModelBase: return part_names @staticmethod - def load_hparams(dir_model: Path): + def load_hparams(dir_model: Path, is_mistral_format: bool): + if is_mistral_format: + with open(dir_model / "params.json", "r", encoding="utf-8") as f: + config = json.load(f) + return config + try: # for security reason, we don't allow loading remote code by default # if a model need remote code, we will fallback to config.json @@ -476,7 +500,10 @@ class TextModel(ModelBase): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - self.hf_arch = get_model_architecture(self.hparams, self.model_type) + if not self.is_mistral_format: + self.hf_arch = get_model_architecture(self.hparams, self.model_type) + else: + self.hf_arch = "" if "text_config" in self.hparams: # move the text_config to the root level @@ -542,14 +569,14 @@ class TextModel(ModelBase): self.gguf_writer.add_head_count(n_head) logger.info(f"gguf: head count = {n_head}") - if (n_head_kv := self.hparams.get("num_key_value_heads")) is not None: + if (n_head_kv := self.find_hparam(["num_key_value_heads", "n_kv_heads"], optional=True)) is not None: self.gguf_writer.add_head_count_kv(n_head_kv) logger.info(f"gguf: key-value head count = {n_head_kv}") if (rope_theta := self.hparams.get("rope_theta")) is not None: self.gguf_writer.add_rope_freq_base(rope_theta) logger.info(f"gguf: rope theta = {rope_theta}") - if (f_rms_eps := self.hparams.get("rms_norm_eps")) is not None: + if (f_rms_eps := self.find_hparam(["rms_norm_eps", "norm_eps"], optional=True)) is not None: self.gguf_writer.add_layer_norm_rms_eps(f_rms_eps) logger.info(f"gguf: rms norm epsilon = {f_rms_eps}") if (f_norm_eps := self.find_hparam(["layer_norm_eps", "layer_norm_epsilon", "norm_epsilon"], optional=True)) is not None: @@ -669,6 +696,48 @@ class TextModel(ModelBase): # NOTE: if you get an error here, you need to update the convert_hf_to_gguf_update.py script # or pull the latest version of the model from Huggingface # don't edit the hashes manually! + if chkhsh == "b6e8e1518dc4305be2fe39c313ed643381c4da5db34a98f6a04c093f8afbe99b": + # ref: https://huggingface.co/THUDM/glm-4-9b-chat + res = "chatglm-bpe" + if chkhsh == "81d72c7348a9f0ebe86f23298d37debe0a5e71149e29bd283904c02262b27516": + # ref: https://huggingface.co/THUDM/glm-4-9b-chat + res = "chatglm-bpe" + if chkhsh == "a1336059768a55c99a734006ffb02203cd450fed003e9a71886c88acf24fdbc2": + # ref: https://huggingface.co/THUDM/glm-4-9b-hf + res = "glm4" + if chkhsh == "9ca2dd618e8afaf09731a7cf6e2105b373ba6a1821559f258b272fe83e6eb902": + # ref: https://huggingface.co/zai-org/GLM-4.5-Air + res = "glm4" + if chkhsh == "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35": + # ref: https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0 + res = "minerva-7b" + if chkhsh == "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664": + # ref: https://huggingface.co/tencent/Hunyuan-A13B-Instruct + res = "hunyuan" + if chkhsh == "bba3b3366b646dbdded5dbc42d59598b849371afc42f7beafa914afaa5b70aa6": + # ref: https://huggingface.co/tencent/Hunyuan-4B-Instruct + res = "hunyuan-dense" + if chkhsh == "a6b57017d60e6edb4d88ecc2845188e0eb333a70357e45dcc9b53964a73bbae6": + # ref: https://huggingface.co/tiiuae/Falcon-H1-0.5B-Base + res = "falcon-h1" + if chkhsh == "60476e1243776c4fb1b993dbd7a5f15ac22f83c80afdf425fa5ae01c8d44ef86": + # ref: https://huggingface.co/tiiuae/Falcon-H1-1B-Base + res = "falcon-h1" + if chkhsh == "3eda48b4c4dc7de733d1a8b3e3b4a85243dbbf704da2ee9d42c6beced8897896": + # ref: https://huggingface.co/tiiuae/Falcon-H1-7B-Base + res = "falcon-h1" + if chkhsh == "48f8e02c0359c0bbdd82f26909171fac1c18a457bb47573ed1fe3bbb2c1cfd4b": + # ref: https://huggingface.co/tiiuae/Falcon-H1-34B-Base + res = "falcon-h1" + if chkhsh == "81212dc7cdb7e0c1074ca62c5aeab0d43c9f52b8a737be7b12a777c953027890": + # ref: https://huggingface.co/moonshotai/Kimi-K2-Base + res = "kimi-k2" + if chkhsh == "d4540891389ea895b53b399da6ac824becc30f2fba0e9ddbb98f92e55ca0e97c": + # ref: https://huggingface.co/Qwen/Qwen3-Embedding-0.6B + res = "qwen2" + if chkhsh == "66b8d4e19ab16c3bfd89bce5d785fb7e0155e8648708a1f42077cb9fe002c273": + # ref: https://huggingface.co/alvarobartt/grok-2-tokenizer + res = "grok-2" if chkhsh == "0ef9807a4087ebef797fc749390439009c3b9eda9ad1a097abbe738f486c01e5": # ref: https://huggingface.co/meta-llama/Meta-Llama-3-8B res = "llama-bpe" @@ -804,42 +873,24 @@ class TextModel(ModelBase): if chkhsh == "d5f1dd6f980fec569fb218a81a7658ac45fc56b38c5a0adeb1c232fbe04ef5ec": # ref: https://huggingface.co/ByteDance-Seed/Seed-Coder-8B-Base res = "seed-coder" - if chkhsh == "b6e8e1518dc4305be2fe39c313ed643381c4da5db34a98f6a04c093f8afbe99b": - # ref: https://huggingface.co/THUDM/glm-4-9b-chat - res = "chatglm-bpe" - if chkhsh == "81d72c7348a9f0ebe86f23298d37debe0a5e71149e29bd283904c02262b27516": - # ref: https://huggingface.co/THUDM/glm-4-9b-chat - res = "chatglm-bpe" - if chkhsh == "a1336059768a55c99a734006ffb02203cd450fed003e9a71886c88acf24fdbc2": - # ref: https://huggingface.co/THUDM/glm-4-9b-hf - res = "glm4" - if chkhsh == "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35": - # ref: https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0 - res = "minerva-7b" - if chkhsh == "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664": - # ref: https://huggingface.co/tencent/Hunyuan-A13B-Instruct - res = "hunyuan" if chkhsh == "b0a6b1c0bd5998ebd9df08611efde34a4ff03faed45ae09c43e6b31ebd4b94cf": # ref: https://huggingface.co/skt/A.X-4.0 res = "a.x-4.0" - if chkhsh == "a6b57017d60e6edb4d88ecc2845188e0eb333a70357e45dcc9b53964a73bbae6": - # ref: https://huggingface.co/tiiuae/Falcon-H1-0.5B-Base - res = "falcon-h1" - if chkhsh == "60476e1243776c4fb1b993dbd7a5f15ac22f83c80afdf425fa5ae01c8d44ef86": - # ref: https://huggingface.co/tiiuae/Falcon-H1-1B-Base - res = "falcon-h1" - if chkhsh == "3eda48b4c4dc7de733d1a8b3e3b4a85243dbbf704da2ee9d42c6beced8897896": - # ref: https://huggingface.co/tiiuae/Falcon-H1-7B-Base - res = "falcon-h1" - if chkhsh == "48f8e02c0359c0bbdd82f26909171fac1c18a457bb47573ed1fe3bbb2c1cfd4b": - # ref: https://huggingface.co/tiiuae/Falcon-H1-34B-Base - res = "falcon-h1" if chkhsh == "f6791d196f87ce6b56a7d234be618e0d58f8cda3549416635b2bebcd22cd95c4": # ref: https://huggingface.co/K-intelligence/Midm-2.0-Base-Instruct res = "midm-2.0" if chkhsh == "169bf0296a13c4d9b7672313f749eb36501d931022de052aad6e36f2bf34dd51": # ref: https://huggingface.co/LiquidAI/LFM2-Tokenizer res = "lfm2" + if chkhsh == "2085e1638f6c377a0aa4ead21b27bb4cb941bf800df86ed391011769c1758dfb": + # ref: https://huggingface.co/LGAI-EXAONE/EXAONE-4.0-32B + res = "exaone4" + if chkhsh == "a1e163ecab2e718a4c829d1148b6e86824ec36163bb71941c3dca9cd5ac25756": + # ref: https://huggingface.co/JetBrains/Mellum-4b-base + res = "mellum" + if chkhsh == "9b1be57e70d20d9501b2b3186e792d81181ae36ada3903c26f9fea418cf87206": + # ref: https://huggingface.co/inclusionAI/LLaDA-MoE-7B-A1B-Base + res = "llada-moe" if res is None: logger.warning("\n") @@ -1082,7 +1133,14 @@ class TextModel(ModelBase): self.gguf_writer.add_token_list(tokens) self.gguf_writer.add_token_types(toktypes) special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=False) - special_vocab.chat_template = "rwkv-world" + if special_vocab.chat_template is None: + template_path = Path(__file__).parent / "models" / "templates" / "llama-cpp-rwkv-world.jinja" + if template_path.is_file(): + with open(template_path, "r", encoding="utf-8") as f: + template = f.read() + else: + template = "rwkv-world" + special_vocab.chat_template = template # hack: Add '\n\n' as the EOT token to make it chat normally special_vocab._set_special_token("eot", 261) # hack: Override these as they have already been set (incorrectly) @@ -1162,6 +1220,55 @@ class TextModel(ModelBase): raise NotImplementedError("Only MEAN, CLS, and LAST pooling types supported") self.gguf_writer.add_pooling_type(pooling_type) + def _set_vocab_interns1(self): + tokens: list[str] = [] + toktypes: list[int] = [] + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + vocab = getattr(tokenizer, 'vocab', tokenizer.get_vocab()) + vocab_size = self.hparams.get("vocab_size", len(vocab)) + assert max(vocab.values()) < vocab_size + + tokpre = self.get_vocab_base_pre(tokenizer) + + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab.items()} + added_vocab = tokenizer.get_added_vocab() + + added_tokens_decoder = tokenizer.added_tokens_decoder + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + else: + token: str = reverse_vocab[i] + if token in added_vocab: + # The tokenizer in llama.cpp assumes the CONTROL and USER_DEFINED tokens are pre-normalized. + # To avoid unexpected issues - we make sure to normalize non-normalized tokens + if not added_tokens_decoder[i].normalized: + previous_token = token + token = tokenizer.decode(tokenizer.encode(token, add_special_tokens=False)) + if previous_token != token: + logger.info(f"{repr(previous_token)} is encoded and decoded back to {repr(token)} using AutoTokenizer") + + if added_tokens_decoder[i].special or self.does_token_look_special(token): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.USER_DEFINED) + else: + toktypes.append(gguf.TokenType.NORMAL) + tokens.append(token) + + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + special_vocab._set_special_token("bos", 151643) + special_vocab.add_to_gguf(self.gguf_writer) + class MmprojModel(ModelBase): model_type = ModelType.MMPROJ @@ -1185,12 +1292,19 @@ class MmprojModel(ModelBase): raise TypeError("MmprojModel must be subclassed with model_arch = gguf.MODEL_ARCH.MMPROJ") # get n_embd of the text model - if "text_config" not in self.hparams: - self.hparams["text_config"] = {} - if "audio_config" not in self.hparams: - self.hparams["audio_config"] = {} - text_config = {**self.hparams, **self.hparams["text_config"]} - self.n_embd_text = text_config.get("hidden_size", text_config.get("n_embd", 0)) + if not self.is_mistral_format: + if "text_config" not in self.hparams: + self.hparams["text_config"] = {} + if "audio_config" not in self.hparams: + self.hparams["audio_config"] = {} + text_config = {**self.hparams, **self.hparams["text_config"]} + self.n_embd_text = text_config.get("hidden_size", text_config.get("n_embd", 0)) + else: + text_config = { + k: v for k, v in self.hparams.items() if k not in ["vision_encoder", "audio_encoder"] + } + self.n_embd_text = text_config.get("hidden_dim", 0) + assert self.n_embd_text > 0, "n_embd not found in hparams" # move vision config to the top level, while preserving the original hparams in global_config @@ -1211,11 +1325,13 @@ class MmprojModel(ModelBase): self.tensor_map = gguf.get_tensor_name_map(gguf.MODEL_ARCH.MMPROJ, self.block_count) # load preprocessor config - with open(self.dir_model / "preprocessor_config.json", "r", encoding="utf-8") as f: - self.preprocessor_config = json.load(f) + if not self.is_mistral_format: + with open(self.dir_model / "preprocessor_config.json", "r", encoding="utf-8") as f: + self.preprocessor_config = json.load(f) def get_vision_config(self) -> dict[str, Any] | None: - return self.global_config.get("vision_config") + config_name = "vision_config" if not self.is_mistral_format else "vision_encoder" + return self.global_config.get(config_name) def get_audio_config(self) -> dict[str, Any] | None: return self.global_config.get("audio_config") @@ -1239,8 +1355,11 @@ class MmprojModel(ModelBase): self.gguf_writer.add_vision_head_count(self.find_vparam(["num_attention_heads"])) # preprocessor config - self.gguf_writer.add_vision_image_mean(self.preprocessor_config["image_mean"]) - self.gguf_writer.add_vision_image_std(self.preprocessor_config["image_std"]) + image_mean = DATASET_MEAN if self.is_mistral_format else self.preprocessor_config["image_mean"] + image_std = DATASET_STD if self.is_mistral_format else self.preprocessor_config["image_std"] + + self.gguf_writer.add_vision_image_mean(image_mean) + self.gguf_writer.add_vision_image_std(image_std) if self.has_audio_encoder: self.gguf_writer.add_clip_has_audio_encoder(True) @@ -1274,6 +1393,12 @@ class MmprojModel(ModelBase): return None raise KeyError(f"could not find any of: {keys}") + def tensor_force_quant(self, name, new_name, bid, n_dims): + del bid, name, n_dims # unused + if ".patch_embd.weight" in new_name: + return gguf.GGMLQuantizationType.F16 if self.ftype == gguf.LlamaFileType.MOSTLY_F16 else gguf.GGMLQuantizationType.F32 + return False + @ModelBase.register("GPTNeoXForCausalLM") class GPTNeoXModel(TextModel): @@ -1887,6 +2012,7 @@ class StableLMModel(TextModel): "MixtralForCausalLM", "VLlama3ForCausalLM", "LlavaForConditionalGeneration", + "VoxtralForConditionalGeneration", "LlamaModel") class LlamaModel(TextModel): model_arch = gguf.MODEL_ARCH.LLAMA @@ -1898,7 +2024,73 @@ class LlamaModel(TextModel): if self.hf_arch == "VLlama3ForCausalLM": self.hparams["num_attention_heads"] = self.hparams.get("num_attention_heads", 32) + def _set_vocab_mistral(self): + vocab = MistralVocab(self.dir_model) + logger.info( + f"Converting tokenizer {vocab.tokenizer_type} of size {vocab.vocab_size}." + ) + + self.gguf_writer.add_tokenizer_model(vocab.gguf_tokenizer_model) + + tokens = [] + scores = [] + toktypes = [] + + for text, score, toktype in vocab.all_tokens(): + tokens.append(text) + scores.append(score) + toktypes.append(toktype) + + assert len(tokens) == vocab.vocab_size, ( + f"token count ({len(tokens)}) != vocab size ({vocab.vocab_size})" + ) + + if vocab.tokenizer_type == MistralTokenizerType.tekken: + self.gguf_writer.add_tokenizer_pre("tekken") + self.gguf_writer.add_token_merges( + vocab.extract_vocab_merges_from_model() + ) + + logger.info( + f"Setting bos, eos, unk and pad token IDs to {vocab.bos_id}, {vocab.eos_id}, {vocab.unk_id}, {vocab.pad_id}." + ) + + self.gguf_writer.add_bos_token_id(vocab.bos_id) + self.gguf_writer.add_eos_token_id(vocab.eos_id) + self.gguf_writer.add_unk_token_id(vocab.unk_id) + self.gguf_writer.add_pad_token_id(vocab.pad_id) + + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_scores(scores) + self.gguf_writer.add_token_types(toktypes) + self.gguf_writer.add_vocab_size(vocab.vocab_size) + + self.gguf_writer.add_add_bos_token(True) + self.gguf_writer.add_add_eos_token(False) + + template_dir = Path(__file__).parent / "models/templates/" + + if not self.is_mistral_format or not self.disable_mistral_community_chat_template: + # Log only for Mistral format that the official tokenization and detokenization is via `mistral-common`. + if self.is_mistral_format: + logger.info( + "Using a Mistral community chat template. These templates can be subject to errors in early days or weeks after a release. " + "Mistral recommends to use `mistral-common` to perform tokenization and detokenization." + ) + template = MistralModel.get_community_chat_template(vocab, template_dir, self.is_mistral_format) + self.gguf_writer.add_chat_template(template) + else: + logger.info("Not using a Mistral community chat template. Ensure to perform the tokenization and detokenization via `mistral-common`.") + def set_vocab(self): + if self.is_mistral_format: + return self._set_vocab_mistral() + + path_tekken_json = self.dir_model / "tekken.json" + path_tokenizer_json = self.dir_model / "tokenizer.json" + if path_tekken_json.is_file() and not path_tokenizer_json.is_file(): + self._set_vocab_mistral() + try: self._set_vocab_sentencepiece() except FileNotFoundError: @@ -1934,7 +2126,9 @@ class LlamaModel(TextModel): def set_gguf_parameters(self): super().set_gguf_parameters() hparams = self.hparams - self.gguf_writer.add_vocab_size(hparams["vocab_size"]) + + if not self.is_mistral_format: + self.gguf_writer.add_vocab_size(hparams["vocab_size"]) if (rope_dim := hparams.get("head_dim")) is None: rope_dim = hparams["hidden_size"] // hparams["num_attention_heads"] @@ -1956,14 +2150,27 @@ class LlamaModel(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: - n_head = self.hparams["num_attention_heads"] - n_kv_head = self.hparams.get("num_key_value_heads") - is_vision_tensor = "vision_tower" in name \ + n_head = self.find_hparam(["n_heads", "num_attention_heads"]) + n_kv_head = self.find_hparam(["n_kv_heads", "num_key_value_heads"]) + + vision_prefixes = [ + "vision_encoder.", + "vision_language_adapter.", + "patch_merger.", + "pre_mm_projector_norm", + ] + + is_multimodal_tensor = "vision_tower" in name \ or "vision_model" in name \ + or "audio_tower" in name \ or "model.connector" in name \ - or "multi_modal_projector" in name + or "multi_modal_projector" in name \ + or any( + name.startswith(prefix) + for prefix in vision_prefixes + ) - if is_vision_tensor: + if is_multimodal_tensor: return [] # skip vision tensors elif self.hf_arch == "LlamaModel": name = "model." + name @@ -2077,13 +2284,18 @@ class LlavaVisionModel(MmprojModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - if self.hparams["model_type"] == "pixtral": + if self.hparams.get("model_type") == "pixtral": # layer_norm_eps is not in config.json, it is hard-coded in modeling_pixtral.py self.hparams["layer_norm_eps"] = self.hparams.get("layer_norm_eps", 1e-5) self.img_break_tok_id = self.get_token_id("[IMG_BREAK]") - logger.info(f"Image break token id: {self.img_break_tok_id}") + elif self.is_mistral_format: + # hparams is already vision config here so norm_eps is only defined in global_config. + self.hparams["norm_eps"] = self.global_config.get("norm_eps", None) + assert self.hparams["norm_eps"] is not None, "norm_eps not found in params.json" + self.img_break_tok_id = self.find_vparam(["image_break_token_id"]) else: raise ValueError(f"Unsupported model type: {self.hparams['model_type']}") + logger.info(f"Image break token id: {self.img_break_tok_id}") def get_token_id(self, token: str) -> int: tokenizer_config_file = self.dir_model / 'tokenizer_config.json' @@ -2097,7 +2309,7 @@ class LlavaVisionModel(MmprojModel): def set_gguf_parameters(self): super().set_gguf_parameters() hparams = self.hparams - if hparams["model_type"] == "pixtral": + if hparams.get("model_type") == "pixtral": self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.PIXTRAL) self.gguf_writer.add_vision_attention_layernorm_eps(hparams["layer_norm_eps"]) @@ -2115,18 +2327,30 @@ class LlavaVisionModel(MmprojModel): def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused - n_head = self.hparams["num_attention_heads"] + n_head = ( + self.hparams["num_attention_heads"] if not self.is_mistral_format else self.find_vparam(["num_attention_heads"]) + ) n_kv_head = n_head - if name.startswith("multi_modal_projector.") or name.startswith("vision_tower."): + valid_prefixes = ( + "multi_modal_projector.", + "vision_tower.", + "vision_encoder.", + "vision_language_adapter.", + "patch_merger.", + "pre_mm_projector_norm", + ) + + if any(name.startswith(prefix) for prefix in valid_prefixes): # process vision tensors - if name.endswith(("q_proj.weight", "q_proj.bias")): + if name.endswith(("q_proj.weight", "q_proj.bias")) and not self.is_mistral_format: data_torch = LlamaModel.permute(data_torch, n_head, n_head) - if name.endswith(("k_proj.weight", "k_proj.bias")): + if name.endswith(("k_proj.weight", "k_proj.bias")) and not self.is_mistral_format: data_torch = LlamaModel.permute(data_torch, n_head, n_kv_head) return [(self.map_tensor_name(name), data_torch)] - if self.img_break_tok_id > 0 and "embed_tokens.weight" in name: + embed_key = "embed_tokens.weight" if not self.is_mistral_format else "tok_embeddings.weight" + if self.img_break_tok_id > 0 and embed_key in name: logger.info(f"Extracting [IMG_BREAK] token embedding from {name}") # for pixtral model, we need to extract the [IMG_BREAK] token embedding img_break_embd = data_torch[self.img_break_tok_id] @@ -2155,10 +2379,9 @@ class SmolVLMModel(MmprojModel): self.gguf_writer.add_vision_use_gelu(True) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, new_name, n_dims # unused if ".embeddings." in name: return gguf.GGMLQuantizationType.F32 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused @@ -2170,7 +2393,10 @@ class SmolVLMModel(MmprojModel): return [] # skip other tensors -@ModelBase.register("Llama4ForConditionalGeneration") +@ModelBase.register( + "Llama4ForConditionalGeneration", + "Llama4ForCausalLM", +) class Llama4Model(LlamaModel): model_arch = gguf.MODEL_ARCH.LLAMA4 undo_permute = False @@ -2188,6 +2414,10 @@ class Llama4Model(LlamaModel): super().set_gguf_parameters() self.gguf_writer.add_interleave_moe_layer_step(self.hparams["interleave_moe_layer_step"]) self.gguf_writer.add_expert_feed_forward_length(self.hparams["intermediate_size_moe"]) + if "layer_types" in self.hparams: + if all(lt == "full_attention" for lt in self.hparams["layer_types"]): + # all layers are full attention (for MobileLLM), disable swa + self.gguf_writer.add_sliding_window(0) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None): if name.startswith("language_model."): @@ -2465,12 +2695,20 @@ class BitnetModel(TextModel): yield (new_name, data_torch) -@ModelBase.register("GrokForCausalLM") +@ModelBase.register("GrokForCausalLM", "Grok1ForCausalLM") class GrokModel(TextModel): model_arch = gguf.MODEL_ARCH.GROK def set_vocab(self): - self._set_vocab_sentencepiece() + if (self.dir_model / 'tokenizer.model').is_file(): + self._set_vocab_sentencepiece() + return + + if not (self.dir_model / 'tokenizer.json').is_file() or not (self.dir_model / 'chat_template.jinja').is_file(): + logger.error('Error: Missing vocab and chat template, download files from https://huggingface.co/alvarobartt/grok-2-tokenizer') + sys.exit(1) + + self._set_vocab_gpt2() def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) @@ -2478,11 +2716,46 @@ class GrokModel(TextModel): def set_gguf_parameters(self): super().set_gguf_parameters() - _experts: list[dict[str, Tensor]] | None = None + self.gguf_writer.add_attn_logit_softcapping(self.hparams.get("attn_logit_softcapping", 30.0)) + self.gguf_writer.add_router_logit_softcapping(self.hparams.get("router_logit_softcapping", 30.0)) + if (final_logit_softcap := self.hparams.get("final_logit_softcapping")): + self.gguf_writer.add_final_logit_softcapping(final_logit_softcap) + + if (rope_dim := self.hparams.get("head_dim")) is None: + rope_dim = self.hparams["hidden_size"] // self.hparams["num_attention_heads"] + + if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + + # Treat "original" as "yarn", seems to have been a mistake + if self.hparams.get("rope_type") in ("yarn", "original"): + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(self.hparams["scaling_factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(self.hparams["original_max_position_embeddings"]) + self.gguf_writer.add_rope_scaling_yarn_ext_factor(self.hparams["extrapolation_factor"]) + self.gguf_writer.add_rope_scaling_yarn_attn_factor(self.hparams["attn_factor"]) + self.gguf_writer.add_rope_scaling_yarn_beta_fast(self.hparams["beta_fast"]) + self.gguf_writer.add_rope_scaling_yarn_beta_slow(self.hparams["beta_slow"]) + + if temp_len := self.hparams.get("attn_temperature_len"): + self.gguf_writer.add_attn_temperature_length(temp_len) + + self.gguf_writer.add_attn_output_scale(self.hparams.get("attn_output_multiplier", rope_dim**-0.5)) + self.gguf_writer.add_embedding_scale(self.hparams["embedding_multiplier_scale"]) + self.gguf_writer.add_logit_scale(self.hparams["output_multiplier_scale"]) + + _experts: list[dict[str, list[Tensor]]] | None = None + _cur_expert = "" def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + tensors: list[tuple[str, Tensor]] = [] + is_expert = ".moe." in name or ".block_sparse_moe.experts." in name + + if not is_expert: + tensors.append((self.map_tensor_name(name), data_torch)) + # process the experts separately - if name.find(".moe.") != -1: + if is_expert or self._cur_expert: n_experts = self.hparams["num_local_experts"] assert bid is not None @@ -2490,32 +2763,41 @@ class GrokModel(TextModel): if self._experts is None: self._experts = [{} for _ in range(self.block_count)] - self._experts[bid][name] = data_torch - - if len(self._experts[bid]) >= n_experts * 3: - tensors: list[tuple[str, Tensor]] = [] + # concatenate split tensors + if name in self._experts[bid]: + self._cur_expert = name + self._experts[bid][name].append(data_torch) + return [] + elif is_expert: + self._cur_expert = name + self._experts[bid][name] = [data_torch] + return [] + else: + self._cur_expert = "" - # merge the experts into a single 3d tensor - for wid in ["linear", "linear_1", "linear_v"]: - datas: list[Tensor] = [] + for bid in range(self.block_count): + if len(self._experts[bid]) >= n_experts * 3: + # merge the experts into a single 3d tensor + for wid in [("linear", "w1", 0), ("linear_1", "w2", 1), ("linear_v", "w3", 0)]: + datas: list[Tensor] = [] - for xid in range(n_experts): - ename = f"transformer.decoder_layer.{bid}.moe.{xid}.{wid}.weight" - datas.append(self._experts[bid][ename]) - del self._experts[bid][ename] + for xid in range(n_experts): + ename = f"transformer.decoder_layer.{bid}.moe.{xid}.{wid[0]}.weight" + if ename not in self._experts[bid]: + ename = f"model.layers.{bid}.block_sparse_moe.experts.{xid}.{wid[1]}.weight" + tensor_list = self._experts[bid][ename] + datas.append(torch.cat(tensor_list, dim=wid[2]) if len(tensor_list) > 1 else tensor_list[0]) + del self._experts[bid][ename] - data_torch = torch.stack(datas, dim=0) + data_torch = torch.stack(datas, dim=0) - merged_name = f"transformer.decoder_layer.{bid}.moe.{wid}.weight" + merged_name = f"transformer.decoder_layer.{bid}.moe.{wid[0]}.weight" - new_name = self.map_tensor_name(merged_name) + new_name = self.map_tensor_name(merged_name) - tensors.append((new_name, data_torch)) - return tensors - else: - return [] + yield (new_name, data_torch) - return [(self.map_tensor_name(name), data_torch)] + yield from tensors @ModelBase.register("DbrxForCausalLM") @@ -2762,13 +3044,185 @@ class Qwen2Model(TextModel): if "language_model." in name: name = name.replace("language_model.", "") # for InternVL if name.startswith("mlp") or name.startswith("multi_modal_projector") \ - or name.startswith("vision_model") or name.startswith("audio_tower"): + or name.startswith("vision_model") or name.startswith("audio_tower") \ + or name.startswith("model.vision_tower") or name.startswith("model.multi_modal_projector"): # skip vision and audio tensors return [] yield from super().modify_tensors(data_torch, name, bid) -@ModelBase.register("Ernie4_5_ForCausalLM") +@ModelBase.register("DreamModel") +class DreamModel(TextModel): + model_arch = gguf.MODEL_ARCH.DREAM + + def get_vocab_base(self) -> tuple[list[str], list[int], str]: + tokens: list[str] = [] + toktypes: list[int] = [] + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + + vocab_dict = tokenizer.get_vocab() + vocab_size = self.hparams.get("vocab_size", len(vocab_dict)) + assert max(vocab_dict.values()) < vocab_size + + tokpre = self.get_vocab_base_pre(tokenizer) + + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab_dict.items()} + added_vocab = tokenizer.get_added_vocab() + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + elif reverse_vocab[i] in added_vocab: + tokens.append(reverse_vocab[i]) + # Check if it's a special token - treat special tokens as CONTROL tokens + if hasattr(tokenizer, 'added_tokens_decoder') and i in tokenizer.added_tokens_decoder: + if tokenizer.added_tokens_decoder[i].special: + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.USER_DEFINED) + else: + # Fallback: treat all added vocab as control tokens for special tokens like <|im_start|> + toktypes.append(gguf.TokenType.CONTROL) + else: + tokens.append(reverse_vocab[i]) + toktypes.append(gguf.TokenType.NORMAL) + + return tokens, toktypes, tokpre + + def set_vocab(self): + try: + self._set_vocab_sentencepiece() + except FileNotFoundError: + self._set_vocab_gpt2() + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._try_set_pooling_type() + + # Dream models use non-causal attention for diffusion + self.gguf_writer.add_causal_attention(False) + # Handle RoPE scaling similar to Qwen2 + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + + # Add Dream-specific parameters + mask_token_id = self.hparams.get("mask_token_id") + if mask_token_id is not None: + self.gguf_writer.add_mask_token_id(mask_token_id) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # Dream model tensors should be mapped directly since it's the base model + yield from super().modify_tensors(data_torch, name, bid) + + +@ModelBase.register("LLaDAModelLM") +class LLaDAModel(TextModel): + model_arch = gguf.MODEL_ARCH.LLADA + undo_permute = True + + def get_vocab_base(self) -> tuple[list[str], list[int], str]: + tokens: list[str] = [] + toktypes: list[int] = [] + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + + vocab_dict = tokenizer.get_vocab() + vocab_size = self.hparams.get("vocab_size", len(vocab_dict)) + assert max(vocab_dict.values()) < vocab_size + + tokpre = self.get_vocab_base_pre(tokenizer) + + reverse_vocab = {id_: encoded_tok for encoded_tok, id_ in vocab_dict.items()} + added_vocab = tokenizer.get_added_vocab() + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + elif reverse_vocab[i] in added_vocab: + tokens.append(reverse_vocab[i]) + # Check if it's a special token - treat special tokens as CONTROL tokens + if hasattr(tokenizer, 'added_tokens_decoder') and i in tokenizer.added_tokens_decoder: + if tokenizer.added_tokens_decoder[i].special: + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.USER_DEFINED) + else: + # Fallback: treat all added vocab as control tokens for special tokens like <|im_start|> + toktypes.append(gguf.TokenType.CONTROL) + else: + tokens.append(reverse_vocab[i]) + toktypes.append(gguf.TokenType.NORMAL) + + return tokens, toktypes, tokpre + + def set_vocab(self): + self._set_vocab_gpt2() + + # LLaDA specific parameters + self.gguf_writer.add_add_bos_token(True) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self._try_set_pooling_type() + + # Add parameters similar to LlamaModel + hparams = self.hparams + self.gguf_writer.add_vocab_size(hparams["vocab_size"]) + + if (rope_dim := hparams.get("head_dim")) is None: + n_heads = hparams.get("num_attention_heads", hparams.get("n_heads")) + rope_dim = hparams.get("hidden_size", hparams.get("d_model")) // n_heads + self.gguf_writer.add_rope_dimension_count(rope_dim) + + # Set context length for LLaDA + context_length = self.hparams.get("max_sequence_length", 4096) + self.gguf_writer.add_context_length(context_length) + + # Set embedding length (dimension size) + embedding_length = self.hparams.get("d_model", 4096) + self.gguf_writer.add_embedding_length(embedding_length) + + # Set feed forward length (MLP hidden size) + feed_forward_length = self.hparams.get("mlp_hidden_size", 12288) + self.gguf_writer.add_feed_forward_length(feed_forward_length) + + # LLaDA models use non-causal attention for diffusion, similar to Dream + self.gguf_writer.add_causal_attention(False) + + # LLaDA models don't shift their logits + self.gguf_writer.add_diffusion_shift_logits(False) + + @staticmethod + def permute(weights: Tensor, n_head: int, n_head_kv: int | None): + if n_head_kv is not None and n_head != n_head_kv: + n_head = n_head_kv + return (weights.reshape(n_head, 2, weights.shape[0] // n_head // 2, *weights.shape[1:]) + .swapaxes(1, 2) + .reshape(weights.shape)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + n_head = self.hparams.get("num_attention_heads", self.hparams.get("n_heads")) + n_kv_head = self.hparams.get("num_key_value_heads", self.hparams.get("n_kv_heads")) + + if self.undo_permute: + if name.endswith(("q_proj.weight", "q_proj.bias")): + data_torch = LLaDAModel.permute(data_torch, n_head, n_head) + if name.endswith(("k_proj.weight", "k_proj.bias")): + data_torch = LLaDAModel.permute(data_torch, n_head, n_kv_head) + + # LLaDA model tensors should be mapped directly since it's the base model + yield from super().modify_tensors(data_torch, name, bid) + + +@ModelBase.register("Ernie4_5_ForCausalLM", "Ernie4_5ForCausalLM") class Ernie4_5Model(TextModel): model_arch = gguf.MODEL_ARCH.ERNIE4_5 @@ -2781,7 +3235,8 @@ class Ernie4_5Model(TextModel): def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: num_heads = self.hparams["num_attention_heads"] num_kv_heads = self.hparams["num_key_value_heads"] - head_dim = self.hparams["head_dim"] + if (head_dim := self.hparams.get("head_dim")) is None: + head_dim = self.hparams["hidden_size"] // num_heads if "ernie." in name: name = name.replace("ernie.", "model.") @@ -2814,6 +3269,93 @@ class Ernie4_5Model(TextModel): return [(self.map_tensor_name(name), data_torch)] +@ModelBase.register("Ernie4_5_MoeForCausalLM") +class Ernie4_5MoeModel(Ernie4_5Model): + model_arch = gguf.MODEL_ARCH.ERNIE4_5_MOE + _experts: list[dict[str, Tensor]] | None = None + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + self._experts = [{} for _ in range(self.block_count)] + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_expert_count(self.hparams["moe_num_experts"]) + self.gguf_writer.add_expert_used_count(self.hparams["moe_k"]) + self.gguf_writer.add_interleave_moe_layer_step(self.hparams["moe_layer_interval"]) + self.gguf_writer.add_leading_dense_block_count(self.hparams["moe_layer_start_index"]) + if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + if (shared_expert_count := self.hparams.get('moe_num_shared_experts')) is not None: + self.gguf_writer.add_expert_shared_count(shared_expert_count) + if shared_expert_count > 0 and (shared_expert_intermediate_size := self.hparams.get('intermediate_size')) is not None and (num_key_value_heads := self.hparams.get('num_key_value_heads')) is not None: + self.gguf_writer.add_expert_shared_feed_forward_length(shared_expert_intermediate_size // num_key_value_heads) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # Modify correction bias name as in DeepseekV2 + if name.endswith("e_score_correction_bias"): + name = name.replace("e_score_correction_bias", "e_score_correction.bias") + + # skip Multi-Token Prediction (MTP) layers (again, same as DeepseekV2) + match = re.match(r"model.mtp_block.(\d+)", name) + if match: + return [] + + # skip all other MTP tensors for now + match = re.match(r"model.mtp_emb_norm.(\d+)", name) + if match: + return [] + + match = re.match(r"model.mtp_hidden_norm.(\d+)", name) + if match: + return [] + + match = re.match(r"model.mtp_linear_proj.(\d+)", name) + if match: + return [] + + # process the experts separately + if name.find("mlp.experts") != -1: + n_experts = self.hparams["moe_num_experts"] + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["gate_proj", "up_proj", "down_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename_to_retrieve = f"model.layers.{bid}.mlp.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename_to_retrieve]) + del self._experts[bid][ename_to_retrieve] + + data_torch = torch.stack(datas, dim=0) + merged_name = f"model.layers.{bid}.mlp.experts.{w_name}.weight" + new_name = self.map_tensor_name(merged_name) + tensors.append((new_name, data_torch)) + + return tensors + else: + return [] + return [(self.map_tensor_name(name), data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + + @ModelBase.register( "Qwen2VLModel", "Qwen2VLForConditionalGeneration", @@ -2887,12 +3429,9 @@ class Qwen2VLVisionModel(MmprojModel): self.gguf_writer.add_vision_attention_layernorm_eps(self.global_config.get("rms_norm_eps", 1e-6)) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, name, n_dims # unused - if ".patch_embd." in new_name: - return gguf.GGMLQuantizationType.F16 if ".position_embd." in new_name: return gguf.GGMLQuantizationType.F32 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused @@ -2965,10 +3504,9 @@ class Qwen25OmniModel(Qwen2VLVisionModel yield ("audio_tower.embed_positions.weight", pos_embd) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, new_name, n_dims # unused if ".conv" in name and ".weight" in name: return gguf.GGMLQuantizationType.F16 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: if name.startswith("thinker."): @@ -2991,7 +3529,13 @@ class Qwen25OmniModel(Qwen2VLVisionModel @ModelBase.register("InternVisionModel") class InternVisionModel(MmprojModel): def set_gguf_parameters(self): + assert self.hparams_vision is not None + if isinstance(self.hparams_vision['image_size'], list): + self.hparams_vision['image_size'] = self.hparams_vision['image_size'][0] + if isinstance(self.hparams_vision['patch_size'], list): + self.hparams_vision['patch_size'] = self.hparams_vision['patch_size'][0] super().set_gguf_parameters() + hparams = self.hparams self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.INTERNVL) self.gguf_writer.add_vision_attention_layernorm_eps(hparams["layer_norm_eps"]) @@ -3008,21 +3552,34 @@ class InternVisionModel(MmprojModel): self.gguf_writer.add_vision_projector_scale_factor(int(1.0 / downsample_ratio)) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, name, n_dims # unused - if ".patch_embd." in new_name: - return gguf.GGMLQuantizationType.F16 if ".position_embd." in new_name: return gguf.GGMLQuantizationType.F32 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) + + def _mapping_interns1_name(self, name): + names_map = { + "model.multi_modal_projector.layer_norm.bias": "mlp1.0.bias", + "model.multi_modal_projector.layer_norm.weight": "mlp1.0.weight", + "model.multi_modal_projector.linear_1.bias": "mlp1.1.bias", + "model.multi_modal_projector.linear_1.weight": "mlp1.1.weight", + "model.multi_modal_projector.linear_2.bias": "mlp1.3.bias", + "model.multi_modal_projector.linear_2.weight": "mlp1.3.weight", + } + if name in names_map: + name = names_map[name] + return name def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused - if name.startswith("vision_model") or name.startswith("mlp"): + vision_prefix = ['vision_model', 'mlp', 'model.vision_tower', 'model.multi_modal_projector'] + # deal with intern-s1 special case + name = self._mapping_interns1_name(name) + if any([name.startswith(prefix) for prefix in vision_prefix]): # process visual tensors # correct name if name.startswith("vision_model"): name = "vision_tower." + name - if (".ls" in name or "position_embedding" in name) and not name.endswith(".weight"): + if (".ls" in name or ".lambda_" in name or "position_embedding" in name) and not name.endswith(".weight"): name += ".weight" # split QKV tensors if needed if ".qkv." in name: @@ -3108,6 +3665,10 @@ class Qwen2MoeModel(TextModel): def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: # process the experts separately + name = name.replace("language_model.", "") # InternVL + if name.startswith("mlp") or name.startswith("vision_model") or name.startswith("model.vision_tower") or name.startswith("model.multi_modal_projector"): + # skip visual tensors + return [] if name.find("experts") != -1: n_experts = self.hparams["num_experts"] assert bid is not None @@ -3156,11 +3717,102 @@ class Qwen2MoeModel(TextModel): class Qwen3Model(Qwen2Model): model_arch = gguf.MODEL_ARCH.QWEN3 + # extra logic for rerank models + is_rerank: bool = False + is_tied_embeddings: bool = False + token_false_id: int | None = None + token_true_id: int | None = None + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + + # track for intern-s1-mini + hparams = ModelBase.load_hparams(self.dir_model, is_mistral_format=False) + self.origin_hf_arch = hparams.get('architectures', [None])[0] + + # a bit hacky, but currently the only way to detect if this is a rerank model + # ref: https://huggingface.co/Qwen/Qwen3-Reranker-0.6B + readme_path = self.dir_model / "README.md" + readme_text = "" + if readme_path.exists(): + with readme_path.open("r", encoding="utf-8") as f: + readme_text = f.read() + if "# Qwen3-Reranker" in readme_text: + self._find_rerank_config() + + def set_vocab(self): + # deal with intern-s1-mini + if self.origin_hf_arch == 'InternS1ForConditionalGeneration': + self._set_vocab_interns1() + return + + super().set_vocab() + + def _find_rerank_config(self): + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model) + + self.is_rerank = True + self.is_tied_embeddings = self.hparams.get("tie_word_embeddings", False) + self.token_false_id = tokenizer.convert_tokens_to_ids("no") + self.token_true_id = tokenizer.convert_tokens_to_ids("yes") + self.sep_token_id = tokenizer.convert_tokens_to_ids("|") + + assert self.token_false_id is not None and self.token_true_id is not None + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if self.is_rerank: + self.gguf_writer.add_pooling_type(gguf.PoolingType.RANK) + self.gguf_writer.add_classifier_output_labels(["yes", "no"]) + self.gguf_writer.add_chat_template([{ + "name": "rerank", + "template": "<|im_start|>system\nJudge whether the Document meets the requirements based on the Query and the Instruct provided. Note that the answer can only be \"yes\" or \"no\".<|im_end|>\n" + "<|im_start|>user\n: Given a web search query, retrieve relevant passages that answer the query\n: {query}\n: {document}<|im_end|>\n" + "<|im_start|>assistant\n\n\n\n\n" + }]) + + def _get_cls_out_tensor(self, data_torch: Tensor) -> Tensor: + # extract "yes" and "no" tokens from the output lm_head tensor + false_row = data_torch[self.token_false_id] + true_row = data_torch[self.token_true_id] + return torch.stack([true_row, false_row], dim=0) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if self.is_rerank: + is_tied_head = self.is_tied_embeddings and "embed_tokens" in name + is_real_head = not self.is_tied_embeddings and "lm_head" in name + if is_tied_head or is_real_head: + cls_out_head = ( + gguf.TENSOR_NAMES[gguf.MODEL_TENSOR.CLS_OUT] + ".weight", + self._get_cls_out_tensor(data_torch), + ) + if is_tied_head: + embed = (self.map_tensor_name(name), data_torch) + return [cls_out_head, embed] + if is_real_head: + return [cls_out_head] + + return super().modify_tensors(data_torch, name, bid) + @ModelBase.register("Qwen3MoeForCausalLM") class Qwen3MoeModel(Qwen2MoeModel): model_arch = gguf.MODEL_ARCH.QWEN3MOE + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + hparams = ModelBase.load_hparams(self.dir_model, False) + self.origin_hf_arch = hparams.get('architectures', [None])[0] + + def set_vocab(self): + # deal with intern-s1 + if self.origin_hf_arch == 'InternS1ForConditionalGeneration': + self._set_vocab_interns1() + return + + super().set_vocab() + @ModelBase.register("GPT2LMHeadModel") class GPT2Model(TextModel): @@ -3501,6 +4153,175 @@ class PlamoModel(TextModel): return [(new_name, data_torch)] +@ModelBase.register("Plamo2ForCausalLM", "PLaMo2ForCausalLM") +class Plamo2Model(TextModel): + model_arch = gguf.MODEL_ARCH.PLAMO2 + + def set_vocab(self): + # PLaMo 2 uses a custom tokenizer with a .jsonl file + # We need to handle this specially + tokenizer_jsonl_path = self.dir_model / "tokenizer.jsonl" + tokenizer_config_path = self.dir_model / "tokenizer_config.json" + + if not tokenizer_jsonl_path.is_file(): + raise FileNotFoundError(f"PLaMo 2 tokenizer file not found: {tokenizer_jsonl_path}") + + # Load tokenizer config + with open(tokenizer_config_path, 'r', encoding='utf-8') as f: + tokenizer_config = json.load(f) + + # Load tokens from JSONL file (actually a list format) + tokens = [] + scores = [] + toktypes = [] + + with open(tokenizer_jsonl_path, 'r', encoding='utf-8') as f: + for line_num, line in enumerate(f): + if line.strip(): + token_data = json.loads(line) + # Format: [token, score, type, ?, ?, ?, ?] + token = token_data[0].encode("utf-8") + score = float(token_data[1]) + token_type_str = token_data[2] if len(token_data) > 2 else "NORMAL" + + tokens.append(token) + scores.append(score) + + # Map token type strings to GGUF token types + if token_type_str == "UNKNOWN": + toktypes.append(gguf.TokenType.UNKNOWN) + elif token_type_str == "CONTROL": + toktypes.append(gguf.TokenType.CONTROL) + elif token_type_str == "BYTE": + toktypes.append(gguf.TokenType.BYTE) + else: + # Check for PLaMo-2 special tokens + token_str = token_data[0] + if token_str.startswith("<|plamo:") and token_str.endswith("|>"): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.NORMAL) + + vocab_size = self.hparams["vocab_size"] + if vocab_size > len(tokens): + pad_count = vocab_size - len(tokens) + logger.debug(f"Padding vocab with {pad_count} token(s) - [PAD1] through [PAD{pad_count}]") + for i in range(1, pad_count + 1): + tokens.append(bytes(f"[PAD{i}]", encoding="utf-8")) + scores.append(-1000.0) + toktypes.append(gguf.TokenType.UNUSED) + + # Use "plamo2" tokenizer type for PLaMo-2's custom Aho-Corasick tokenizer + self.gguf_writer.add_tokenizer_model("plamo2") + self.gguf_writer.add_tokenizer_pre("default") + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_scores(scores) + self.gguf_writer.add_token_types(toktypes) + + # Add special tokens from config + if "bos_token" in tokenizer_config and tokenizer_config["bos_token"] is not None: + token_id = tokens.index(tokenizer_config["bos_token"].encode("utf-8")) + self.gguf_writer.add_bos_token_id(token_id) + if "eos_token" in tokenizer_config and tokenizer_config["eos_token"] is not None: + token_id = tokens.index(tokenizer_config["eos_token"].encode("utf-8")) + self.gguf_writer.add_eos_token_id(token_id) + if "pad_token" in tokenizer_config and tokenizer_config["pad_token"] is not None: + token_id = tokens.index(tokenizer_config["pad_token"].encode("utf-8")) + self.gguf_writer.add_pad_token_id(token_id) + if "sep_token" in tokenizer_config and tokenizer_config["sep_token"] is not None: + token_id = tokens.index(tokenizer_config["sep_token"].encode("utf-8")) + self.gguf_writer.add_sep_token_id(token_id) + if "unk_token" in tokenizer_config and tokenizer_config["unk_token"] is not None: + token_id = tokens.index(tokenizer_config["unk_token"].encode("utf-8")) + self.gguf_writer.add_unk_token_id(token_id) + + # Add <|plamo:op|> as EOT to ensure appropriate end of generation + self.gguf_writer.add_eot_token_id(4) + + self.gguf_writer.add_add_space_prefix(False) + + def set_gguf_parameters(self): + hparams = self.hparams + block_count = hparams["num_hidden_layers"] + self.gguf_writer.add_vocab_size(self.hparams["vocab_size"]) + + # Which layers are Mamba layers + # PLaMo 2 uses mamba_step to indicate the pattern (e.g., 2 means every other layer) + # This logic matches modeling_plamo.py's is_mamba function + mamba_step = hparams.get("mamba_step", 2) + mamba_enabled = hparams.get("mamba_enabled", True) + mamba_layers = [] + + if mamba_enabled: + for i in range(block_count): + if block_count <= (mamba_step // 2): + # use attention in last layer + is_mamba = (i != block_count - 1) + else: + is_mamba = (i % mamba_step) != (mamba_step // 2) + if is_mamba: + mamba_layers.append(0) + else: + mamba_layers.append(hparams.get("num_key_value_heads", 4)) + + if mamba_layers: + self.gguf_writer.add_head_count_kv(mamba_layers) + + self.gguf_writer.add_context_length(hparams.get("max_position_embeddings", 2048)) + self.gguf_writer.add_embedding_length(hparams.get("hidden_size", 4096)) + self.gguf_writer.add_block_count(block_count) + self.gguf_writer.add_head_count(hparams.get("num_attention_heads", 32)) + self.gguf_writer.add_layer_norm_rms_eps(hparams.get("rms_norm_eps", 1e-06)) + self.gguf_writer.add_rope_freq_base(hparams.get("rope_theta", 10000)) + + # Mamba parameters + self.gguf_writer.add_ssm_state_size(hparams.get("mamba_d_state", 64)) + self.gguf_writer.add_ssm_conv_kernel(hparams.get("mamba_d_conv", 4)) + self.gguf_writer.add_ssm_time_step_rank(hparams.get("mamba_num_heads", 64)) + intermediate_size = hparams.get("mamba_num_heads", 64) * hparams.get("hidden_size_per_head", 128) + self.gguf_writer.add_ssm_inner_size(intermediate_size) + self.gguf_writer.add_ssm_group_count(0) + + # MLP feed forward parameters (for attention layers) + self.gguf_writer.add_feed_forward_length(hparams.get("intermediate_size", 13312)) + self.gguf_writer.add_file_type(self.ftype) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + del bid # unused + + if name.endswith(".A_log"): + data_torch = -torch.exp(data_torch) + elif name.endswith(".dt_bias"): + name = name.rpartition(".dt_bias")[0] + ".dt_proj.bias" + elif name.endswith(".dt_norm_weight"): + name = name.rpartition(".dt_norm_weight")[0] + ".dt_norm.weight" + elif name.endswith(".B_norm_weight"): + name = name.rpartition(".B_norm_weight")[0] + ".B_norm.weight" + elif name.endswith(".C_norm_weight"): + name = name.rpartition(".C_norm_weight")[0] + ".C_norm.weight" + elif name.endswith(".k_weight"): + name = name.rpartition(".k_weight")[0] + ".k.weight" + elif name.endswith(".q_weight"): + name = name.rpartition(".q_weight")[0] + ".q.weight" + elif name.endswith(".conv1d.weight"): + data_torch = torch.squeeze(data_torch) # remove (, 1, ) + assert data_torch.ndim == 2 + elif name.endswith(".pre_mixer_norm.weight"): + data_torch += 1.0 + elif name.endswith(".post_mixer_norm.weight"): + data_torch += 1.0 / 5 + elif name.endswith(".pre_mlp_norm.weight"): + data_torch += 1.0 + elif name.endswith(".post_mlp_norm.weight"): + data_torch += 1.0 / (5**1.5) + elif name.endswith(".norm.weight"): + data_torch += 1.0 + + new_name = self.map_tensor_name(name) + + return [(new_name, data_torch)] + + @ModelBase.register("CodeShellForCausalLM") class CodeShellModel(TextModel): model_arch = gguf.MODEL_ARCH.CODESHELL @@ -4072,7 +4893,7 @@ class NomicBertModel(BertModel): def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, **kwargs: Any): hparams = kwargs.pop("hparams", None) if hparams is None: - hparams = ModelBase.load_hparams(dir_model) + hparams = ModelBase.load_hparams(dir_model, False) self.is_moe = bool(hparams.get("moe_every_n_layers")) self.model_arch = gguf.MODEL_ARCH.NOMIC_BERT_MOE if self.is_moe else gguf.MODEL_ARCH.NOMIC_BERT @@ -4178,11 +4999,35 @@ class NeoBert(BertModel): @ModelBase.register("XLMRobertaModel", "XLMRobertaForSequenceClassification") class XLMRobertaModel(BertModel): model_arch = gguf.MODEL_ARCH.BERT + _lora_files = {} + _lora_names = [] - def __init__(self, *args, **kwargs): - super().__init__(*args, **kwargs) + def __init__(self, dir_model: Path, ftype: gguf.LlamaFileType, fname_out: Path, **kwargs: Any): + hparams = kwargs.pop("hparams", None) + if hparams is None: + hparams = ModelBase.load_hparams(dir_model, False) + + if lora_names := hparams.get("lora_adaptations"): + self._lora_names = lora_names + self.model_arch = gguf.MODEL_ARCH.JINA_BERT_V3 + + super().__init__(dir_model, ftype, fname_out, hparams=hparams, **kwargs) self._xlmroberta_tokenizer_init() + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + if self._lora_names: + for name in self._lora_names: + fname = self.add_prefix_to_filename(self.fname_out, f"lora-{name}-") + self._lora_files[name] = gguf.GGUFWriter(fname, arch=gguf.MODEL_ARCH_NAMES[self.model_arch], endianess=self.endianess, use_temp_file=self.use_temp_file, dry_run=self.dry_run) + + return super().generate_extra_tensors() + + def set_type(self): + for lora_writer in self._lora_files.values(): + lora_writer.add_type(gguf.GGUFType.ADAPTER) + lora_writer.add_string(gguf.Keys.Adapter.TYPE, "lora") + super().set_type() + def set_vocab(self): self._xlmroberta_set_vocab() @@ -4192,13 +5037,62 @@ class XLMRobertaModel(BertModel): if name.startswith("roberta."): name = name[8:] + # jina-embeddings-v3 + if ".parametrizations." in name: + name = name.replace(".parametrizations.", ".") + if name.endswith(".original"): + name = name[:-9] + # position embeddings start at pad_token_id + 1, so just chop down the weight tensor if name == "embeddings.position_embeddings.weight": if self._position_offset is not None: data_torch = data_torch[self._position_offset:,:] + if name.endswith(".0.lora_A") or name.endswith(".0.lora_B"): + if name.startswith("pooler.dense"): + return [] + + num_loras = data_torch.size(0) + assert num_loras == len(self._lora_names) + + # Split out each LoRA in their own GGUF + for i, lora_writer in enumerate(self._lora_files.values()): + new_name = self.map_tensor_name(name[:-9]) + name[-7:].lower() + data = data_torch[i, :, :] + # Transpose/flip token_embd/types into correct shape + if new_name == "token_embd.weight.lora_b": + data = data.T + elif new_name.startswith("token_types.weight."): + new_name = new_name[:-1] + ("a" if new_name[-1:] == "b" else "b") + lora_writer.add_tensor(new_name, data.float().numpy(), raw_dtype=gguf.GGMLQuantizationType.F32) + + return [] + return super().modify_tensors(data_torch, name, bid) + def set_gguf_parameters(self): + super().set_gguf_parameters() + + # jina-embeddings-v3 + if rotary_emb_base := self.hparams.get("rotary_emb_base"): + self.gguf_writer.add_rope_freq_base(rotary_emb_base) + lora_alpha = self.hparams.get("lora_alpha") + if lora_prompt_prefixes := self.hparams.get("task_instructions"): + assert self._lora_files and all(lora_name in lora_prompt_prefixes for lora_name in self._lora_files.keys()) + for lora_name, lora_writer in self._lora_files.items(): + lora_writer.add_float32(gguf.Keys.Adapter.LORA_ALPHA, lora_alpha if lora_alpha is not None else 1.0) + lora_writer.add_string(gguf.Keys.Adapter.LORA_TASK_NAME, lora_name) + if lora_prompt_prefixes: + lora_writer.add_string(gguf.Keys.Adapter.LORA_PROMPT_PREFIX, lora_prompt_prefixes[lora_name]) + + def write(self): + super().write() + for lora_writer in self._lora_files.values(): + lora_writer.write_header_to_file() + lora_writer.write_kv_data_to_file() + lora_writer.write_tensors_to_file(progress=True) + lora_writer.close() + @ModelBase.register("GemmaForCausalLM") class GemmaModel(TextModel): @@ -4358,6 +5252,29 @@ class Gemma3Model(TextModel): return [(self.map_tensor_name(name), data_torch)] +@ModelBase.register("Gemma3TextModel") +class EmbeddingGemma(Gemma3Model): + model_arch = gguf.MODEL_ARCH.GEMMA_EMBEDDING + + def set_gguf_parameters(self): + super().set_gguf_parameters() + + # Override the sliding window size as it gets adjusted by the Gemma3TextConfig + # constructor. We want to use the value from the original model's config.json. + # ref: https://github.com/huggingface/transformers/pull/40700 + with open(self.dir_model / "config.json", "r", encoding="utf-8") as f: + config = json.load(f) + orig_sliding_window = config.get("sliding_window") + if orig_sliding_window is None: + raise ValueError("sliding_window not found in model config - this is required for the model") + + logger.info(f"Using original sliding_window from config: {orig_sliding_window} " + f"instead of {self.hparams['sliding_window']}") + self.gguf_writer.add_sliding_window(orig_sliding_window) + + self._try_set_pooling_type() + + @ModelBase.register("Gemma3ForConditionalGeneration") class Gemma3VisionModel(MmprojModel): def set_gguf_parameters(self): @@ -4379,13 +5296,12 @@ class Gemma3VisionModel(MmprojModel): self.gguf_writer.add_vision_projector_scale_factor(proj_scale_factor) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, new_name, n_dims # unused # related to https://github.com/ggml-org/llama.cpp/issues/13025 if "input_projection" in name: return gguf.GGMLQuantizationType.F16 if ".embeddings." in name: return gguf.GGMLQuantizationType.F32 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused @@ -5159,10 +6075,40 @@ class OlmoModel(TextModel): return [(self.map_tensor_name(name), data_torch)] +@ModelBase.register("SeedOssForCausalLM") +class SeedOssModel(TextModel): + model_arch = gguf.MODEL_ARCH.SEED_OSS + + @ModelBase.register("Olmo2ForCausalLM") +@ModelBase.register("Olmo3ForCausalLM") class Olmo2Model(TextModel): model_arch = gguf.MODEL_ARCH.OLMO2 + def set_gguf_parameters(self): + super().set_gguf_parameters() + + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_attn_factors(rope_scaling["attention_factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + + if "sliding_window" in self.hparams: + self.gguf_writer.add_sliding_window(self.hparams["sliding_window"]) + + sliding_window_pattern = [] + if "layer_types" in self.hparams: + sliding_window_pattern = [t == "sliding_attention" for t in self.hparams["layer_types"]] + else: + # Olmo2 does not use sliding window attention. + # Olmo3 defaults to using sliding window for all layers except every 4th. + for i in range(self.hparams["num_hidden_layers"]): + sliding_window_pattern.append((i + 1) % 4 != 0) + + self.gguf_writer.add_sliding_window_pattern(sliding_window_pattern) + @ModelBase.register("OlmoeForCausalLM") class OlmoeModel(TextModel): @@ -5557,13 +6503,67 @@ class DeepseekModel(TextModel): raise ValueError(f"Unprocessed experts: {experts}") -@ModelBase.register("DeepseekV2ForCausalLM") -@ModelBase.register("DeepseekV3ForCausalLM") +@ModelBase.register( + "DeepseekV2ForCausalLM", + "DeepseekV3ForCausalLM", + "KimiVLForConditionalGeneration", +) class DeepseekV2Model(TextModel): model_arch = gguf.MODEL_ARCH.DEEPSEEK2 def set_vocab(self): - self._set_vocab_gpt2() + try: + self._set_vocab_gpt2() + return + except Exception: + pass + + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + tokpre = self.get_vocab_base_pre(tokenizer) + + if tokpre == "kimi-k2": + # Build merges list using the approach similar to HunYuanMoE + merges = [] + vocab = {} + mergeable_ranks = tokenizer.model._mergeable_ranks + for token, rank in mergeable_ranks.items(): + vocab[QwenModel.token_bytes_to_string(token)] = rank + if len(token) == 1: + continue + merged = QwenModel.bpe(mergeable_ranks, token, max_rank=rank) + if len(merged) == 2: + merges.append(' '.join(map(QwenModel.token_bytes_to_string, merged))) + + # Build token list + vocab_size = self.hparams["vocab_size"] + special_tokens = tokenizer.special_tokens + reverse_vocab = {id_ : encoded_tok for encoded_tok, id_ in {**vocab, **special_tokens}.items()} + tokens: list[str] = [] + toktypes: list[int] = [] + + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + else: + token = reverse_vocab[i] + tokens.append(token) + if i in special_tokens.values(): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.NORMAL) + + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + self.gguf_writer.add_token_merges(merges) + + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=False) + special_vocab.add_to_gguf(self.gguf_writer) + else: + raise NotImplementedError(f"Deepseek pre-tokenizer {tokpre!r} is not supported yet!") def set_gguf_parameters(self): @@ -5610,6 +6610,13 @@ class DeepseekV2Model(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # skip vision tensors and remove "language_model." for Kimi-VL + if "vision_tower" in name or "multi_modal_projector" in name: + return [] + + if name.startswith("language_model."): + name = name.replace("language_model.", "") + # rename e_score_correction_bias tensors if name.endswith("e_score_correction_bias"): name = name.replace("e_score_correction_bias", "e_score_correction.bias") @@ -5849,6 +6856,8 @@ class T5Model(TextModel): self.gguf_writer.add_embedding_length(self.hparams["d_model"]) self.gguf_writer.add_feed_forward_length(self.hparams["d_ff"]) self.gguf_writer.add_block_count(self.hparams["num_layers"]) + if (dec_n_layer := self.hparams.get("num_decoder_layers")) is not None: + self.gguf_writer.add_decoder_block_count(dec_n_layer) self.gguf_writer.add_head_count(self.hparams["num_heads"]) self.gguf_writer.add_key_length(self.hparams["d_kv"]) self.gguf_writer.add_value_length(self.hparams["d_kv"]) @@ -6095,7 +7104,7 @@ class JaisModel(TextModel): self.gguf_writer.add_max_alibi_bias(self.max_alibi_bias) -@ModelBase.register("Glm4ForCausalLM") +@ModelBase.register("Glm4ForCausalLM", "Glm4vForConditionalGeneration") class Glm4Model(TextModel): model_arch = gguf.MODEL_ARCH.GLM4 @@ -6117,7 +7126,8 @@ class Glm4Model(TextModel): def set_gguf_parameters(self): super().set_gguf_parameters() - rope_dim = self.hparams["head_dim"] + if (rope_dim := self.hparams.get("head_dim")) is None: + rope_dim = self.hparams["hidden_size"] // self.hparams["num_attention_heads"] self.gguf_writer.add_rope_dimension_count(int(rope_dim * self.hparams.get("partial_rotary_factor", 0.5))) rope_scaling = self.hparams.get("rope_scaling") or {} if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: @@ -6125,6 +7135,146 @@ class Glm4Model(TextModel): self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.startswith("model.visual."): # ignore visual part of Glm4v + return [] + elif name.startswith("model.language_model."): + name = name.replace("language_model.", "") # for Glm4v + return super().modify_tensors(data_torch, name, bid) + + +@ModelBase.register("Glm4MoeForCausalLM") +class Glm4MoeModel(TextModel): + model_arch = gguf.MODEL_ARCH.GLM4_MOE + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + # GLM4_MOE has num_hidden_layers + 1 actual layers (including NextN layer) + self.block_count = self.hparams["num_hidden_layers"] + self.hparams.get("num_nextn_predict_layers", 0) + self.tensor_map = gguf.get_tensor_name_map(self.model_arch, self.block_count) + + def set_vocab(self): + from transformers import AutoTokenizer + + tokenizer = AutoTokenizer.from_pretrained(self.dir_model) + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + tokens, toktypes, tokpre = self.get_vocab_base() + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + # Special tokens + # Note: Using <|endoftext|> (151329) for eot causes endless generation + special_vocab._set_special_token("bos", tokenizer.get_added_vocab()["[gMASK]"]) # 151331 + special_vocab._set_special_token("eot", tokenizer.get_added_vocab()["<|user|>"]) # 151336 + special_vocab._set_special_token("unk", tokenizer.get_added_vocab()["<|endoftext|>"]) # 151329 + special_vocab._set_special_token("eom", tokenizer.get_added_vocab()["<|observation|>"]) # 151338 + + # Patch broken chat template + if isinstance(special_vocab.chat_template, str) and "visible_text(m.content).endswith" in special_vocab.chat_template: + special_vocab.chat_template = special_vocab.chat_template.replace( + """{{ visible_text(m.content) }}\n{{- '/nothink' if (enable_thinking is defined and not enable_thinking and not visible_text(m.content).endswith("/nothink")) else '' -}}""", + """{% set content = visible_text(m.content) %}{{ content }}\n{{- '/nothink' if (enable_thinking is defined and not enable_thinking and not content.endswith("/nothink")) else '' -}}""") + + special_vocab.add_to_gguf(self.gguf_writer) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (rope_dim := self.hparams.get("head_dim")) is None: + rope_dim = ( + self.hparams["hidden_size"] // self.hparams["num_attention_heads"] + ) + self.gguf_writer.add_rope_dimension_count( + int(rope_dim * self.hparams.get("partial_rotary_factor", 0.5)) + ) + + # MoE parameters - Use only routed expert count (shared experts handled separately) + if (n_routed_experts := self.hparams.get("n_routed_experts")) is not None: + self.gguf_writer.add_expert_count(n_routed_experts) + if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + if (n_shared_experts := self.hparams.get("n_shared_experts")) is not None: + self.gguf_writer.add_expert_shared_count(n_shared_experts) + if (first_k_dense_replace := self.hparams.get("first_k_dense_replace")) is not None: + self.gguf_writer.add_leading_dense_block_count(first_k_dense_replace) + + # Expert gating function (sigmoid for GLM4_MOE) + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + + # Routed scaling factor + if (routed_scaling_factor := self.hparams.get("routed_scaling_factor")) is not None: + self.gguf_writer.add_expert_weights_scale(routed_scaling_factor) + + # Normalise topk probabilities + if (norm_topk_prob := self.hparams.get("norm_topk_prob")) is not None: + self.gguf_writer.add_expert_weights_norm(norm_topk_prob) + + # NextN/MTP prediction layers + if (num_nextn_predict_layers := self.hparams.get("num_nextn_predict_layers")) is not None: + self.gguf_writer.add_nextn_predict_layers(num_nextn_predict_layers) + + _experts: list[dict[str, Tensor]] | None = None + + def modify_tensors( + self, data_torch: Tensor, name: str, bid: int | None + ) -> Iterable[tuple[str, Tensor]]: + if name.startswith("model.visual."): # ignore visual part + return [] + elif name.startswith("model.language_model."): + name = name.replace("language_model.", "") # for multimodal variants + + # Handle main token embedding (but not layer-specific NextN embeddings) + if name == "model.embed_tokens.weight" and ".layers." not in name: + return [(self.map_tensor_name("token_embd.weight"), data_torch)] + + # Handle routed experts + if name.find("mlp.experts") != -1: + n_experts = self.hparams["n_routed_experts"] + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down_proj", "gate_proj", "up_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.mlp.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.mlp.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + if name.endswith("e_score_correction_bias"): + name = name.replace("e_score_correction_bias", "e_score_correction.bias") + + new_name = self.map_tensor_name(name) + + return [(new_name, data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + @ModelBase.register("GlmForCausalLM", "ChatGLMModel", "ChatGLMForConditionalGeneration") class ChatGLMModel(TextModel): @@ -6392,6 +7542,75 @@ class ExaoneModel(TextModel): yield (self.format_tensor_name(gguf.MODEL_TENSOR.ROPE_FREQS), torch.tensor(rope_factors, dtype=torch.float32)) +@ModelBase.register("Exaone4ForCausalLM") +class Exaone4Model(TextModel): + model_arch = gguf.MODEL_ARCH.EXAONE4 + + def set_vocab(self): + tokens, toktypes, tokpre = self.get_vocab_base() + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=True) + special_vocab.add_to_gguf(self.gguf_writer) + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hparams = self.hparams + self.gguf_writer.add_vocab_size(hparams["vocab_size"]) + + if hparams.get("sliding_window") is not None: + self.gguf_writer.add_sliding_window(hparams["sliding_window"]) + if "layer_types" in hparams: + self.gguf_writer.add_sliding_window_pattern([t == "sliding_attention" for t in hparams["layer_types"]]) + elif "sliding_window_pattern" in hparams: + sliding_window_pattern = [] + if isinstance(hparams["sliding_window_pattern"], str): # e.g. LLLG + for i in range(hparams["num_hidden_layers"]): + sliding_window_pattern.append(hparams["sliding_window_pattern"][i % len(hparams["sliding_window_pattern"])] == "L") + if isinstance(hparams["sliding_window_pattern"], int): # e.g. 4 + for i in range(hparams["num_hidden_layers"]): + sliding_window_pattern.append((i + 1) % hparams["sliding_window_pattern"] != 0) + if len(sliding_window_pattern) == hparams["num_hidden_layers"]: + self.gguf_writer.add_sliding_window_pattern(sliding_window_pattern) + + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "linear" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.LINEAR) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + if rope_scaling := self.find_hparam(["rope_scaling"], optional=True): + if rope_scaling.get("rope_type", '').lower() == "llama3": + base = self.hparams.get("rope_theta", 10_000.0) + if (dim := self.hparams.get("head_dim")) is None: + dim = self.hparams["hidden_size"] // self.hparams["num_attention_heads"] + freqs = 1.0 / (base ** (torch.arange(0, dim, 2, dtype=torch.float32) / dim)) + + factor = rope_scaling.get("factor", 16.0) + low_freq_factor = rope_scaling.get("low_freq_factor", 1.0) + high_freq_factor = rope_scaling.get("high_freq_factor", 4.0) + old_context_len = self.hparams.get("original_max_position_embeddings", 8192) + + low_freq_wavelen = old_context_len / low_freq_factor + high_freq_wavelen = old_context_len / high_freq_factor + + rope_factors = [] + for freq in freqs: + wavelen = 2 * math.pi / freq + if wavelen < high_freq_wavelen: + rope_factors.append(1) + elif wavelen > low_freq_wavelen: + rope_factors.append(factor) + else: + smooth = (old_context_len / wavelen - low_freq_factor) / (high_freq_factor - low_freq_factor) + rope_factors.append(1 / ((1 - smooth) / factor + smooth)) + + yield (self.format_tensor_name(gguf.MODEL_TENSOR.ROPE_FREQS), torch.tensor(rope_factors, dtype=torch.float32)) + + @ModelBase.register("GraniteForCausalLM") class GraniteModel(LlamaModel): """Conversion for IBM's GraniteForCausalLM""" @@ -6502,10 +7721,29 @@ class GraniteHybridModel(Mamba2Model, Gr if i not in self._attn_layers ] + # There are some models in this family that are non-hybrid, but keep the + # same parent class by setting all layers to "attention." If this is the + # case, the model architecture needs to be updated to a standard + # "granite" or "granitemoe" model + if not self._ssm_layers: + has_experts = self.find_hparam(["num_experts_per_tok"], optional=True) + new_arch = ( + gguf.MODEL_ARCH.GRANITE_MOE + if has_experts else + gguf.MODEL_ARCH.GRANITE + ) + self.model_arch = new_arch + self.gguf_writer.arch = gguf.MODEL_ARCH_NAMES[new_arch] + self.gguf_writer.add_architecture() + # n_group and d_inner are used during reshape_tensors for mamba2 - self.d_model = self.find_hparam(["hidden_size", "d_model"]) - self.n_group = self.find_hparam(["n_groups"]) - self.d_inner = self.find_hparam(["expand"]) * self.d_model + # NOTE: Explicitly include hparam prefix prefix for d_model to + # disambiguate with top-level head_dim + # NOTE 2: If needed for future models, this can be isolated in a method + # to separate the prefix setting and teh keys used + self.d_model = self.find_hparam([f"{self.hparam_prefixes[0]}_head_dim", "hidden_size", "d_model"]) + self.n_group = self.find_hparam(["n_groups", "num_groups"]) + self.d_inner = self.find_hparam(["expand", "num_heads"]) * self.d_model def get_attn_layers(self): # Explicit list of layer type names @@ -6566,12 +7804,12 @@ class GraniteHybridModel(Mamba2Model, Gr ## Mamba mixer params ## self.gguf_writer.add_ssm_conv_kernel(self.find_hparam(["conv_kernel", "d_conv"])) - self.gguf_writer.add_ssm_state_size(self.find_hparam(["state_size", "d_state"])) + self.gguf_writer.add_ssm_state_size(self.find_hparam(["state_size", "d_state", "state_dim", "ssm_state_size"])) self.gguf_writer.add_ssm_group_count(self.n_group) self.gguf_writer.add_ssm_inner_size(self.d_inner) # NOTE: The mamba_dt_rank is _not_ the right field for how this is used # in llama.cpp - self.gguf_writer.add_ssm_time_step_rank(self.find_hparam(["n_heads"])) + self.gguf_writer.add_ssm_time_step_rank(self.find_hparam(["n_heads", "num_heads"])) ## Attention params ## head_count_kv = self.find_hparam(["num_key_value_heads", "n_head_kv"]) @@ -6582,8 +7820,11 @@ class GraniteHybridModel(Mamba2Model, Gr self.gguf_writer.add_rope_dimension_count(rope_dim) self.gguf_writer.add_head_count_kv(head_count_kv_vec) - ## If Bamba, use rope, otherwise don't - use_rope = "BambaForCausalLM" in self.hparams["architectures"] + ## If Bamba or non-hybrid, use rope, otherwise don't + use_rope = ( + "BambaForCausalLM" in self.hparams["architectures"] + or not self._ssm_layers + ) self.gguf_writer.add_rope_scaling_finetuned(use_rope) if not use_rope: self.gguf_writer.add_context_length(2**20) @@ -6598,6 +7839,55 @@ class GraniteHybridModel(Mamba2Model, Gr Mamba2Model.set_vocab(self) +@ModelBase.register("NemotronHForCausalLM") +class NemotronHModel(GraniteHybridModel): + """Hybrid mamba2/attention model from NVIDIA""" + model_arch = gguf.MODEL_ARCH.NEMOTRON_H + + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + + # Save the top-level head_dim for later + self.head_dim = self.hparams.get("head_dim", self.hparams.get("attention_head_dim")) + assert self.head_dim is not None, "Could not find the attention head dim in config" + + # Don't use expand to calculate d_inner + self.d_inner = self.find_hparam(["num_heads"]) * self.d_model + + # Update the ssm / attn / mlp layers + # M: Mamba2, *: Attention, -: MLP + hybrid_override_pattern = self.hparams["hybrid_override_pattern"] + self._ssm_layers = [i for i, val in enumerate(hybrid_override_pattern) if val == "M"] + self._mlp_layers = [i for i, val in enumerate(hybrid_override_pattern) if val == "-"] + + def get_attn_layers(self): + hybrid_override_pattern = self.hparams["hybrid_override_pattern"] + assert len(hybrid_override_pattern) == self.block_count, "Mismatch between hybrid override and num_hidden_layers!" + return [i for i, val in enumerate(hybrid_override_pattern) if val == "*"] + + def set_gguf_parameters(self): + super().set_gguf_parameters() + + self.gguf_writer.add_key_length(self.head_dim) + self.gguf_writer.add_value_length(self.head_dim) + + # Set feed_forward_length + # NOTE: This will trigger an override warning. This is preferrable to + # duplicating all the parent logic + n_ff = self.find_hparam(["intermediate_size", "n_inner", "hidden_dim"]) + self.gguf_writer.add_feed_forward_length([ + n_ff if i in self._mlp_layers else 0 for i in range(self.block_count) + ]) + + def set_vocab(self): + super().set_vocab() + + # The tokenizer _does_ add a BOS token (via post_processor type + # TemplateProcessing) but does not set add_bos_token to true in the + # config, so we need to explicitly override it here. + self.gguf_writer.add_add_bos_token(True) + + @ModelBase.register("BailingMoeForCausalLM") class BailingMoeModel(TextModel): model_arch = gguf.MODEL_ARCH.BAILINGMOE @@ -6705,6 +7995,121 @@ class BailingMoeModel(TextModel): raise ValueError(f"Unprocessed experts: {experts}") +@ModelBase.register("GroveMoeForCausalLM", "modeling_grove_moe.GroveMoeForCausalLM") +class GroveMoeModel(TextModel): + model_arch = gguf.MODEL_ARCH.GROVEMOE + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (n_experts := self.hparams.get("num_experts")) is not None: + self.gguf_writer.add_expert_count(n_experts) + if (moe_intermediate_size := self.hparams.get("moe_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + logger.info(f"gguf: expert feed forward length = {moe_intermediate_size}") + # FIXME?: Hardcoded https://huggingface.co/inclusionAI/GroveMoE-Inst/blob/c4c69e5970d18907b5e6ddccdfd55176fe292df1/modeling_grove_moe.py#L299 + self.gguf_writer.add_expert_chunk_feed_forward_length(self.hparams.get("head_dim") or 128) + # FIXME?: Hardcoded https://huggingface.co/inclusionAI/GroveMoE-Inst/blob/c4c69e5970d18907b5e6ddccdfd55176fe292df1/modeling_grove_moe.py#L298 + self.gguf_writer.add_experts_per_group(2) + # FIXME?: Hardcoded https://huggingface.co/inclusionAI/GroveMoE-Inst/blob/c4c69e5970d18907b5e6ddccdfd55176fe292df1/modeling_grove_moe.py#L376 + self.gguf_writer.add_expert_group_scale(0.05) + # YaRN is not enabled by default + # To enable it, please refer to this guide: https://huggingface.co/Qwen/Qwen3-30B-A3B#processing-long-texts + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + + _experts: list[dict[str, Tensor]] | None = None + _chunk_experts: list[dict[str, Tensor]] | None = None + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name.endswith(".expert_bias"): + # FIXME?: Unused https://huggingface.co/inclusionAI/GroveMoE-Inst/blob/c4c69e5970d18907b5e6ddccdfd55176fe292df1/modeling_grove_moe.py#L303 + return [] + + # process the experts separately + if name.find("chunk_experts") != -1: + n_experts = self.hparams["num_experts"] // 2 # see add_experts_per_group + assert bid is not None + + if self._chunk_experts is None: + self._chunk_experts = [{} for _ in range(self.block_count)] + + self._chunk_experts[bid][name] = data_torch + + if len(self._chunk_experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down_proj", "gate_proj", "up_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.mlp.chunk_experts.{xid}.{w_name}.weight" + datas.append(self._chunk_experts[bid][ename]) + del self._chunk_experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.mlp.chunk_experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + elif name.find("experts") != -1: + n_experts = self.hparams["num_experts"] + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down_proj", "gate_proj", "up_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.mlp.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.mlp.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + return [(self.map_tensor_name(name), data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + + if self._chunk_experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + chunk_experts = [k for d in self._chunk_experts for k in d.keys()] + if len(chunk_experts) > 0: + raise ValueError(f"Unprocessed adjugate experts: {chunk_experts}") + + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + + @ModelBase.register("ChameleonForConditionalGeneration") @ModelBase.register("ChameleonForCausalLM") # obsolete class ChameleonModel(TextModel): @@ -6763,9 +8168,10 @@ class WhisperEncoderModel(MmprojModel): def __init__(self, *args, **kwargs): super().__init__(*args, **kwargs) - self.hparams["hidden_size"] = self.hparams["d_model"] - self.hparams["intermediate_size"] = self.hparams["encoder_ffn_dim"] - self.hparams["num_attention_heads"] = self.hparams["encoder_attention_heads"] + if "hidden_size" not in self.hparams and "intermediate_size" not in self.hparams: + self.hparams["hidden_size"] = self.hparams["d_model"] + self.hparams["intermediate_size"] = self.hparams["encoder_ffn_dim"] + self.hparams["num_attention_heads"] = self.hparams["encoder_attention_heads"] def set_gguf_parameters(self): super().set_gguf_parameters() @@ -6774,10 +8180,9 @@ class WhisperEncoderModel(MmprojModel): self.gguf_writer.add_audio_attention_layernorm_eps(self.hparams.get("layer_norm_eps", 1e-5)) def tensor_force_quant(self, name, new_name, bid, n_dims): - del bid, new_name, n_dims # unused if ".conv" in name and ".weight" in name: return gguf.GGMLQuantizationType.F16 - return False + return super().tensor_force_quant(name, new_name, bid, n_dims) def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: del bid # unused @@ -6804,9 +8209,21 @@ class UltravoxWhisperEncoderModel(Whispe def set_gguf_parameters(self): super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.ULTRAVOX) self.gguf_writer.add_audio_stack_factor(self.global_config["stack_factor"]) +@ModelBase.register("VoxtralForConditionalGeneration") +class VoxtralWhisperEncoderModel(WhisperEncoderModel): + has_vision_encoder = False # no vision encoder + has_audio_encoder = True + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.VOXTRAL) + self.gguf_writer.add_audio_stack_factor(4) # == intermediate_size // hidden_size + + @ModelBase.register("FalconH1ForCausalLM") class FalconH1Model(Mamba2Model): model_arch = gguf.MODEL_ARCH.FALCON_H1 @@ -6918,11 +8335,6 @@ class FalconH1Model(Mamba2Model): class HunYuanMoEModel(TextModel): model_arch = gguf.MODEL_ARCH.HUNYUAN_MOE - def __init__(self, *args, **kwargs): - super().__init__(*args, **kwargs) - # For handling tied embeddings - self._tok_embd = None - def set_vocab(self): from transformers import AutoTokenizer tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) @@ -7016,9 +8428,6 @@ class HunYuanMoEModel(TextModel): _experts: list[dict[str, Tensor]] | None = None def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: - if name == "model.embed_tokens.weight": - self._tok_embd = data_torch.clone() - if name == "lm_head.weight": if self.hparams.get("tie_word_embeddings", False): logger.info("Skipping tied output layer 'lm_head.weight'") @@ -7063,6 +8472,168 @@ class HunYuanMoEModel(TextModel): raise ValueError(f"Unprocessed experts: {experts}") +@ModelBase.register("LLaDAMoEModel", "LLaDAMoEModelLM") +class LLaDAMoEModel(TextModel): + model_arch = gguf.MODEL_ARCH.LLADA_MOE + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (n_experts := self.hparams.get("num_experts")) is not None: + self.gguf_writer.add_expert_count(n_experts) + + if (expert_intermediate_size := self.hparams.get("expert_intermediate_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(expert_intermediate_size) + + # number of experts used per token (top-k) + if (n_experts_used := self.hparams.get("num_experts_per_tok")) is not None: + self.gguf_writer.add_expert_used_count(n_experts_used) + + self.gguf_writer.add_mask_token_id(156895) + self.gguf_writer.add_causal_attention(False) + self.gguf_writer.add_diffusion_shift_logits(False) + + _experts: list[dict[str, Tensor]] | None = None + + # Copied from: Qwen2MoeModel + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # process the experts separately + if name.find("experts") != -1: + n_experts = self.hparams["num_experts"] + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down_proj", "gate_proj", "up_proj"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.mlp.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.mlp.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + return [(self.map_tensor_name(name), data_torch)] + + # Copied from: Qwen2MoeModel + def prepare_tensors(self): + super().prepare_tensors() + + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + + +@ModelBase.register("HunYuanDenseV1ForCausalLM") +class HunYuanModel(TextModel): + model_arch = gguf.MODEL_ARCH.HUNYUAN_DENSE + + def set_vocab(self): + if (self.dir_model / "tokenizer.json").is_file(): + self._set_vocab_gpt2() + else: + from transformers import AutoTokenizer + tokenizer = AutoTokenizer.from_pretrained(self.dir_model, trust_remote_code=True) + + # 1. Get the pre-tokenizer identifier hash + tokpre = self.get_vocab_base_pre(tokenizer) + + # 2. Reverse-engineer the merges list from mergeable_ranks + merges = [] + vocab = {} + mergeable_ranks = tokenizer.mergeable_ranks + for token, rank in mergeable_ranks.items(): + vocab[QwenModel.token_bytes_to_string(token)] = rank + if len(token) == 1: + continue + merged = QwenModel.bpe(mergeable_ranks, token, max_rank=rank) + if len(merged) == 2: + merges.append(' '.join(map(QwenModel.token_bytes_to_string, merged))) + + # 3. Generate the tokens and toktypes lists + vocab_size = self.hparams["vocab_size"] + assert tokenizer.vocab_size == vocab_size + special_tokens = tokenizer.special_tokens + reverse_vocab = {id_ : encoded_tok for encoded_tok, id_ in {**vocab, **special_tokens}.items()} + tokens: list[str] = [] + toktypes: list[int] = [] + for i in range(vocab_size): + if i not in reverse_vocab: + tokens.append(f"[PAD{i}]") + toktypes.append(gguf.TokenType.UNUSED) + else: + token = reverse_vocab[i] + tokens.append(token) + if i in special_tokens.values(): + toktypes.append(gguf.TokenType.CONTROL) + else: + toktypes.append(gguf.TokenType.NORMAL) + + # 4. Write all vocab-related fields to the GGUF writer + self.gguf_writer.add_tokenizer_model("gpt2") + self.gguf_writer.add_tokenizer_pre(tokpre) + self.gguf_writer.add_token_list(tokens) + self.gguf_writer.add_token_types(toktypes) + self.gguf_writer.add_token_merges(merges) + + # 5. Add special tokens and chat templates + special_vocab = gguf.SpecialVocab(self.dir_model, load_merges=False) + special_vocab.add_to_gguf(self.gguf_writer) + # FIX for BOS token: Overwrite incorrect id read from config.json + if self.hparams['hidden_size'] == 4096: + self.gguf_writer.add_bos_token_id(127958) # only for 7b dense, fix <|bos|> token + + def set_gguf_parameters(self): + super().set_gguf_parameters() + hparams = self.hparams + + # Rope + rope_scaling = hparams.get("rope_scaling", {}) + if rope_scaling.get("type") == "dynamic": + # HunYuan uses NTK Aware Alpha based scaling. Original implementation: https://www.reddit.com/r/LocalLLaMA/comments/14lz7j5/ntkaware_scaled_rope_allows_llama_models_to_have/ + # 1000 corresponds to a usable context length of 256k (https://github.com/Tencent-Hunyuan/Hunyuan-A13B/blob/main/report/Hunyuan_A13B_Technical_Report.pdf) + alpha = rope_scaling.get("alpha", 50) + base = hparams.get("rope_theta", 10000.0) + dim = hparams["head_dim"] + scaled_base = base * (alpha ** (dim / (dim - 2))) + self.gguf_writer.add_rope_freq_base(scaled_base) + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.NONE) + self.gguf_writer.add_rope_scaling_factor(1) + # There is no consistent way to calculate ctx from alpha, and the config is incorrectly set to 32k + self.gguf_writer.add_rope_scaling_orig_ctx_len(256 * 1024) # 256k context length + self.gguf_writer.add_context_length(256 * 1024) # 256k context length + + # if any of our assumptions about the values are wrong, something has changed and this may need to be updated + assert base == 10000.0 and self.hparams["max_position_embeddings"] in [32 * 1024, 256 * 1024] , \ + "HunYuan dynamic RoPE scaling assumptions changed, please update the logic or context length manually" + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + if name == "lm_head.weight": + if self.hparams.get("tie_word_embeddings", False): + logger.info("Skipping tied output layer 'lm_head.weight'") + return [] + + return [(self.map_tensor_name(name), data_torch)] + + @ModelBase.register("SmolLM3ForCausalLM") class SmolLM3Model(LlamaModel): model_arch = gguf.MODEL_ARCH.SMOLLM3 @@ -7078,8 +8649,131 @@ class SmolLM3Model(LlamaModel): self.gguf_writer.add_chat_template(chat_template) -@ModelBase.register("Lfm2ForCausalLM") -@ModelBase.register("LFM2ForCausalLM") +@ModelBase.register("GptOssForCausalLM") +class GptOssModel(TextModel): + model_arch = gguf.MODEL_ARCH.GPT_OSS + + def transform_nibble_layout(self, tensor): + assert tensor.dtype == torch.uint8 + assert tensor.shape[-1] == 16 + # swap nibbles + t_lo = tensor & 0x0F + t_hi = tensor & 0xF0 + t_swapped = (t_lo << 4) | (t_hi >> 4) + tensor = t_swapped + # transform aaaa...bbbb... to abababab... + blk_a, blk_b = tensor.chunk(2, dim=-1) + # get a_ + blk_a0 = (blk_a & 0xF0).view(-1, 1) + blk_a1 = (blk_a << 4).view(-1, 1) + blk_a = torch.stack((blk_a0, blk_a1), dim=2).view(tensor.shape) + # get _b + blk_b0 = (blk_b >> 4).view(-1, 1) + blk_b1 = (blk_b & 0x0F).view(-1, 1) + blk_b = torch.stack((blk_b0, blk_b1), dim=2).view(tensor.shape) + # swap once more + out = blk_a | blk_b + out_h = out & 0xF0 + out_l = out & 0x0F + out = (out_h >> 4) | (out_l << 4) + return out + + def repack_mxfp4(self, new_name: str, blocks: Tensor, scales: Tensor): + assert blocks.dtype == torch.uint8 + assert scales.dtype == torch.uint8 + scales = scales.unsqueeze(-1) + assert len(blocks.shape) == 4 + assert len(scales.shape) == 4 + blocks = self.transform_nibble_layout(blocks) + new_data = torch.concat((scales, blocks), dim=-1) + new_shape = [new_data.shape[0], new_data.shape[1], new_data.shape[2] * 32] + logger.info(f"Repacked {new_name} with shape {new_shape} and quantization MXFP4") + # flatten last dim + new_data = new_data.view(new_data.shape[0], new_data.shape[1], new_data.shape[2] * new_data.shape[3]) + new_data = new_data.numpy() + self.gguf_writer.add_tensor(new_name, new_data, raw_dtype=gguf.GGMLQuantizationType.MXFP4) + + def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: + blocks0: Tensor = torch.zeros(1) + blocks1: Tensor = torch.zeros(1) + # we assume that tensors are loaded in the correct order + for name, data_torch in self.get_tensors(): + if "mlp.experts.down_proj_blocks" in name: + blocks0 = data_torch + elif "mlp.experts.down_proj_scales" in name: + new_name = self.map_tensor_name(name.replace("_scales", ".weight")) + self.repack_mxfp4(new_name, blocks0, data_torch) + elif "mlp.experts.gate_up_proj_blocks" in name: + blocks0, blocks1 = data_torch[:, ::2, :, :], data_torch[:, 1::2, :, :] + elif "mlp.experts.gate_up_proj_scales" in name: + scales0, scales1 = data_torch[:, ::2, :], data_torch[:, 1::2, :] + new_name_gate = self.map_tensor_name(name.replace("gate_up_proj_scales", "gate_proj.weight")) + new_name_up = self.map_tensor_name(name.replace("gate_up_proj_scales", "up_proj.weight")) + self.repack_mxfp4(new_name_gate, blocks0, scales0) + self.repack_mxfp4(new_name_up, blocks1, scales1) + return [] + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + del bid # unused + + if "sinks" in name: + name += ".weight" + + # correct naming for down_proj + if "down_proj" in name: + if name.endswith("_bias"): + name = name.replace("down_proj_bias", "down_proj.bias") + elif "_blocks" not in name and "_scales" not in name: + logger.warning(f"{name} is not in MXFP4, performance may be degraded") + name = name.replace("down_proj", "down_proj.weight") + data_torch = data_torch.transpose(-1, -2) + else: + # otherwise, it should already be repacked to ggml MXFP4 format + return [] + + # split the gate_up into gate and up + if "gate_up_proj" in name: + if name.endswith("_bias"): + name_up = name.replace("gate_up_proj_bias", "up_proj.bias") + name_gate = name.replace("gate_up_proj_bias", "gate_proj.bias") + gate_proj_bias, up_proj_bias = data_torch[..., ::2], data_torch[..., 1::2] + return [ + (self.map_tensor_name(name_gate), gate_proj_bias), + (self.map_tensor_name(name_up), up_proj_bias) + ] + elif "_blocks" not in name and "_scales" not in name: + logger.warning(f"{name} is not in MXFP4, performance may be degraded") + name_up = name.replace("gate_up_proj", "up_proj.weight") + name_gate = name.replace("gate_up_proj", "gate_proj.weight") + data_torch = data_torch.transpose(-1, -2) + gate_proj_weight, up_proj_weight = data_torch[:, ::2, :], data_torch[:, 1::2, :] + return [ + (self.map_tensor_name(name_gate), gate_proj_weight), + (self.map_tensor_name(name_up), up_proj_weight) + ] + else: + # otherwise, it should already be repacked to ggml MXFP4 format + return [] + + return [(self.map_tensor_name(name), data_torch)] + + def set_vocab(self): + self._set_vocab_gpt2() + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_sliding_window(self.hparams["sliding_window"]) + self.gguf_writer.add_expert_feed_forward_length(self.hparams["intermediate_size"]) + + rope_scaling = self.hparams.get("rope_scaling") or {} + rope_type = rope_scaling.get("rope_type", rope_scaling.get("type")) + assert rope_type == "yarn", f"GPT-OSS only supports yarn rope scaling, got {rope_type}" + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling.get("original_max_position_embeddings", 4096)) + + +@ModelBase.register("Lfm2ForCausalLM", "LFM2ForCausalLM") class LFM2Model(TextModel): model_arch = gguf.MODEL_ARCH.LFM2 @@ -7114,6 +8808,13 @@ class LFM2Model(TextModel): self._add_feed_forward_length() def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + is_vision_tensor = "vision_tower" in name or "multi_modal_projector" in name + if is_vision_tensor: + # skip vision tensors + return [] + + name = name.replace("language_model.", "") + # conv op requires 2d tensor if 'conv.conv' in name: data_torch = data_torch.squeeze(1) @@ -7121,6 +8822,237 @@ class LFM2Model(TextModel): return [(self.map_tensor_name(name), data_torch)] +@ModelBase.register("Lfm2VlForConditionalGeneration") +class LFM2VLModel(MmprojModel): + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + assert self.hparams_vision is not None + # TODO(tarek): for dynamic resolution image_size is not specified, setting here for compatibility + self.hparams_vision["image_size"] = 256 + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.LFM2) + self.gguf_writer.add_vision_attention_layernorm_eps(self.find_vparam(["layer_norm_eps"])) + self.gguf_writer.add_vision_projector_scale_factor(self.global_config.get("downsample_factor", 2)) + self.gguf_writer.add_vision_use_gelu(True) + # python notation, e.g. for vision_feature_layer == -1, we pick last layer -> vision_feature_layers_to_drop = 0 + vision_feature_layers_to_drop = -(self.global_config.get("vision_feature_layer", -1) + 1) + self.gguf_writer.add_vision_block_count(self.find_vparam(self.n_block_keys) - vision_feature_layers_to_drop) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + del bid # unused + is_vision_tensor = "vision_tower" in name or "multi_modal_projector" in name + + if is_vision_tensor: + # remove "model." prefix + name = name.replace("model.vision_tower.", "vision_tower.") + name = name.replace("model.multi_modal_projector.", "multi_modal_projector.") + + if "patch_embedding.weight" in name: + data_torch = data_torch.view(data_torch.shape[0], 16, 16, 3).permute(0, 3, 1, 2) + + return [(self.map_tensor_name(name), data_torch)] + + return [] # skip other tensors + + +@ModelBase.register("SmallThinkerForCausalLM") +class SmallThinkerModel(TextModel): + model_arch = gguf.MODEL_ARCH.SMALLTHINKER + + def set_gguf_parameters(self): + super().set_gguf_parameters() + if (n_experts := self.hparams.get("num_experts", self.hparams.get("moe_num_primary_experts"))) is not None: + self.gguf_writer.add_expert_count(n_experts) + if (n_experts_used := self.hparams.get("num_experts_per_tok", self.hparams.get("moe_num_active_primary_experts"))) is not None: + self.gguf_writer.add_expert_used_count(n_experts_used) + if (moe_intermediate_size := self.hparams.get("moe_ffn_hidden_size")) is not None: + self.gguf_writer.add_expert_feed_forward_length(moe_intermediate_size) + self.gguf_writer.add_feed_forward_length(moe_intermediate_size) + logger.info(f"gguf: expert feed forward length = {moe_intermediate_size}") + if (self.hparams.get('moe_primary_router_apply_softmax')): + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SOFTMAX) + else: + self.gguf_writer.add_expert_gating_func(gguf.ExpertGatingFuncType.SIGMOID) + # YaRN is not enabled by default + # To enable it, please refer to this guide: https://huggingface.co/Qwen/Qwen3-30B-A3B#processing-long-texts + rope_scaling = self.hparams.get("rope_scaling") or {} + if rope_scaling.get("rope_type", rope_scaling.get("type")) == "yarn" and "factor" in rope_scaling: + self.gguf_writer.add_rope_scaling_type(gguf.RopeScalingType.YARN) + self.gguf_writer.add_rope_scaling_factor(rope_scaling["factor"]) + self.gguf_writer.add_rope_scaling_orig_ctx_len(rope_scaling["original_max_position_embeddings"]) + + sliding_window_layout = self.hparams.get("sliding_window_layout") + if sliding_window_layout: + for i in sliding_window_layout: + if i != 0: + sliding_window = self.hparams.get("sliding_window_size") + if sliding_window: + self.gguf_writer.add_sliding_window(sliding_window) + break + + _experts: list[dict[str, Tensor]] | None = None + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + # process the experts separately + if name.find("experts") != -1: + n_experts = self.hparams.get("num_experts", self.hparams.get("moe_num_primary_experts")) + assert bid is not None + + if self._experts is None: + self._experts = [{} for _ in range(self.block_count)] + + self._experts[bid][name] = data_torch + + if len(self._experts[bid]) >= n_experts * 3: + tensors: list[tuple[str, Tensor]] = [] + + # merge the experts into a single 3d tensor + for w_name in ["down", "gate", "up"]: + datas: list[Tensor] = [] + + for xid in range(n_experts): + ename = f"model.layers.{bid}.block_sparse_moe.experts.{xid}.{w_name}.weight" + datas.append(self._experts[bid][ename]) + del self._experts[bid][ename] + + data_torch = torch.stack(datas, dim=0) + + merged_name = f"model.layers.{bid}.block_sparse_moe.experts.{w_name}.weight" + + new_name = self.map_tensor_name(merged_name) + + tensors.append((new_name, data_torch)) + return tensors + else: + return [] + + return [(self.map_tensor_name(name), data_torch)] + + def prepare_tensors(self): + super().prepare_tensors() + + if self._experts is not None: + # flatten `list[dict[str, Tensor]]` into `list[str]` + experts = [k for d in self._experts for k in d.keys()] + if len(experts) > 0: + raise ValueError(f"Unprocessed experts: {experts}") + + +class MistralModel(LlamaModel): + model_arch = gguf.MODEL_ARCH.LLAMA + model_name = "Mistral" + hf_arch = "" + is_mistral_format = True + undo_permute = False + + @staticmethod + def get_community_chat_template(vocab: MistralVocab, templates_dir: Path, is_mistral_format: bool): + assert TokenizerVersion is not None, "mistral_common is not installed" + assert isinstance(vocab.tokenizer, (Tekkenizer, SentencePieceTokenizer)), ( + f"Expected Tekkenizer or SentencePieceTokenizer, got {type(vocab.tokenizer)}" + ) + + if vocab.tokenizer.version == TokenizerVersion.v1: + return "mistral-v1" + elif vocab.tokenizer.version == TokenizerVersion.v3 and vocab.tokenizer_type == MistralTokenizerType.spm: + return "mistral-v3" + elif vocab.tokenizer.version == TokenizerVersion.v3 and vocab.tokenizer_type == MistralTokenizerType.tekken: + return "mistral-v3-tekken" + elif vocab.tokenizer.version == TokenizerVersion.v7 and vocab.tokenizer_type == MistralTokenizerType.spm: + return "mistral-v7" + elif vocab.tokenizer.version == TokenizerVersion.v7 and vocab.tokenizer_type == MistralTokenizerType.tekken: + return "mistral-v7-tekken" + elif vocab.tokenizer.version == TokenizerVersion.v11: + template_file = "Mistral-Small-3.2-24B-Instruct-2506.jinja" + elif vocab.tokenizer.version == TokenizerVersion.v13: + template_file = "unsloth-mistral-Devstral-Small-2507.jinja" + else: + err_message = f"Unknown tokenizer type: {vocab.tokenizer_type} and version {vocab.tokenizer.version}" + if is_mistral_format: + err_message += ( + " . Please pass --disable-mistral-community-chat-template argument to the CLI " + "if you want to skip this error and use the Mistral official `mistral-common` pre-processing library." + ) + raise ValueError(err_message) + + template_path = templates_dir / template_file + if not template_path.exists(): + raise FileNotFoundError(f"Template file not found: {template_path}") + + with open(template_path, "r", encoding="utf-8") as f: + template = f.read() + + return template + + +class PixtralModel(LlavaVisionModel): + model_name = "Pixtral" + hf_arch = "" + is_mistral_format = True + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.PIXTRAL) + + self.gguf_writer.add_vision_attention_layernorm_eps( + self.find_hparam(["norm_eps"]) + ) + self.gguf_writer.add_rope_freq_base(self.find_vparam(["rope_theta"])) + + self.gguf_writer.add_vision_use_silu(True) + + # spatial_merge_size + if self.find_vparam(["mm_projector_id"]) == "patch_merge": + self.gguf_writer.add_vision_spatial_merge_size( + self.find_vparam(["spatial_merge_size"]) + ) + + def map_tensor_name(self, name: str, try_suffixes: Sequence[str] = (".weight", ".bias")) -> str: + if name == "vision_language_adapter.w_in.weight": + return "mm.1.weight" + elif name == "vision_language_adapter.w_out.weight": + return "mm.2.weight" + return super().map_tensor_name(name, try_suffixes) + + +@ModelBase.register("KimiVLForConditionalGeneration") +class KimiVLModel(MmprojModel): + def __init__(self, *args, **kwargs): + super().__init__(*args, **kwargs) + assert self.hparams_vision is not None + self.hparams_vision["image_size"] = 64 * 14 # for compatibility + + def set_gguf_parameters(self): + super().set_gguf_parameters() + self.gguf_writer.add_clip_projector_type(gguf.VisionProjectorType.KIMIVL) + self.gguf_writer.add_vision_use_gelu(True) + self.gguf_writer.add_vision_projector_scale_factor(2) + # eps is the same as pytorch's default value + assert self.hparams_vision is not None + self.gguf_writer.add_vision_attention_layernorm_eps(self.hparams_vision.get("layer_norm_eps", 1e-5)) + + def modify_tensors(self, data_torch: Tensor, name: str, bid: int | None) -> Iterable[tuple[str, Tensor]]: + del bid # unused + is_vision_tensor = "vision_tower" in name or "multi_modal_projector" in name + + if is_vision_tensor: + if "pos_emb.weight" in name: + data_torch = data_torch.view(data_torch.shape[0] * data_torch.shape[1], data_torch.shape[2]) + elif "wqkv" in name: + split_dim = 0 if "weight" in name else -1 + wq, wk, wv = data_torch.chunk(3, dim=split_dim) + return [ + (self.map_tensor_name(name.replace("wqkv", "wq")), wq), + (self.map_tensor_name(name.replace("wqkv", "wk")), wk), + (self.map_tensor_name(name.replace("wqkv", "wv")), wv) + ] + + return [(self.map_tensor_name(name), data_torch)] + + return [] # skip other tensors + ###### CONVERSION LOGIC ###### @@ -7135,6 +9067,7 @@ class LazyTorchTensor(gguf.LazyBase): _dtype_map: dict[torch.dtype, type] = { torch.float16: np.float16, torch.float32: np.float32, + torch.uint8: np.uint8, } # used for safetensors slices @@ -7270,6 +9203,17 @@ def parse_args() -> argparse.Namespace: "--mmproj", action="store_true", help="(Experimental) Export multimodal projector (mmproj) for vision models. This will only work on some vision models. A prefix 'mmproj-' will be added to the output file name.", ) + parser.add_argument( + "--mistral-format", action="store_true", + help="Whether the model is stored following the Mistral format.", + ) + parser.add_argument( + "--disable-mistral-community-chat-template", action="store_true", + help=( + "Whether to disable usage of Mistral community chat templates. If set, use the Mistral official `mistral-common` library for tokenization and detokenization of Mistral models. " + "Using `mistral-common` ensure correctness and zero-day support of tokenization for models converted from the Mistral format but requires to manually setup the tokenization server." + ) + ) args = parser.parse_args() if not args.print_supported_models and args.model is None: @@ -7375,17 +9319,26 @@ def main() -> None: if "mmproj" not in fname_out.name: fname_out = ModelBase.add_prefix_to_filename(fname_out, "mmproj-") + is_mistral_format = args.mistral_format + disable_mistral_community_chat_template = args.disable_mistral_community_chat_template + with torch.inference_mode(): output_type = ftype_map[args.outtype] model_type = ModelType.MMPROJ if args.mmproj else ModelType.TEXT - hparams = ModelBase.load_hparams(dir_model) - model_architecture = get_model_architecture(hparams, model_type) - logger.info(f"Model architecture: {model_architecture}") - try: - model_class = ModelBase.from_model_architecture(model_architecture, model_type=model_type) - except NotImplementedError: - logger.error(f"Model {model_architecture} is not supported") - sys.exit(1) + hparams = ModelBase.load_hparams(dir_model, is_mistral_format) + if not is_mistral_format: + model_architecture = get_model_architecture(hparams, model_type) + logger.info(f"Model architecture: {model_architecture}") + try: + model_class = ModelBase.from_model_architecture(model_architecture, model_type=model_type) + except NotImplementedError: + logger.error(f"Model {model_architecture} is not supported") + sys.exit(1) + elif args.mmproj: + assert hparams.get("vision_encoder") is not None, "This model does not support multimodal" + model_class = PixtralModel + else: + model_class = MistralModel model_instance = model_class(dir_model, output_type, fname_out, is_big_endian=args.bigendian, use_temp_file=args.use_temp_file, @@ -7394,7 +9347,8 @@ def main() -> None: split_max_tensors=args.split_max_tensors, split_max_size=split_str_to_n_bytes(args.split_max_size), dry_run=args.dry_run, small_first_shard=args.no_tensor_first_split, - remote_hf_model_id=hf_repo_id) + remote_hf_model_id=hf_repo_id, disable_mistral_community_chat_template=disable_mistral_community_chat_template + ) if args.vocab_only: logger.info("Exporting model vocab...") diff -pruN 5882+dfsg-2/convert_hf_to_gguf_update.py 6641+dfsg-2/convert_hf_to_gguf_update.py --- 5882+dfsg-2/convert_hf_to_gguf_update.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/convert_hf_to_gguf_update.py 2025-09-30 07:36:33.000000000 +0000 @@ -7,7 +7,6 @@ import pathlib import re import requests -import sys import json import shutil import argparse @@ -61,6 +60,10 @@ parser.add_argument( help="download full list of models - make sure you have access to all of them", ) parser.add_argument( + "--check-missing", action="store_true", + help="only check for missing pre-tokenizer hashes", +) +parser.add_argument( "hf_token", help="optional HF token", nargs="?", @@ -69,8 +72,11 @@ args = parser.parse_args() hf_token = args.hf_token if args.hf_token is not None else hf_token if hf_token is None: - logger.error("HF token is required. Please provide it as an argument or set it in ~/.cache/huggingface/token") - sys.exit(1) + logger.warning("HF token not found. You can provide it as an argument or set it in ~/.cache/huggingface/token") + +if args.check_missing and args.full: + logger.warning("Downloading full list of models requested, ignoring --check-missing!") + args.check_missing = False # TODO: this string has to exercise as much pre-tokenizer functionality as possible # will be updated with time - contributions welcome @@ -131,6 +137,9 @@ models = [ {"name": "a.x-4.0", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/skt/A.X-4.0", }, {"name": "midm-2.0", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/K-intelligence/Midm-2.0-Base-Instruct", }, {"name": "lfm2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/LiquidAI/LFM2-Tokenizer"}, + {"name": "exaone4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/LGAI-EXAONE/EXAONE-4.0-32B", }, + {"name": "mellum", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/JetBrains/Mellum-4b-base", }, + {"name": "llada-moe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/inclusionAI/LLaDA-MoE-7B-A1B-Base", }, ] # some models are known to be broken upstream, so we will skip them as exceptions @@ -139,18 +148,23 @@ pre_computed_hashes = [ {"name": "chatglm-bpe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-chat", "chkhsh": "b6e8e1518dc4305be2fe39c313ed643381c4da5db34a98f6a04c093f8afbe99b"}, {"name": "chatglm-bpe", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-chat", "chkhsh": "81d72c7348a9f0ebe86f23298d37debe0a5e71149e29bd283904c02262b27516"}, {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/THUDM/glm-4-9b-hf", "chkhsh": "a1336059768a55c99a734006ffb02203cd450fed003e9a71886c88acf24fdbc2"}, + {"name": "glm4", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/zai-org/GLM-4.5-Air", "chkhsh": "9ca2dd618e8afaf09731a7cf6e2105b373ba6a1821559f258b272fe83e6eb902"}, {"name": "minerva-7b", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/sapienzanlp/Minerva-7B-base-v1.0", "chkhsh": "1431a23e583c97432bc230bff598d103ddb5a1f89960c8f1d1051aaa944d0b35"}, {"name": "hunyuan", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-A13B-Instruct", "chkhsh": "7e57df22b1fe23a7b1e1c7f3dc4e3f96d43a4eb0836d0c6bdc3436d7b2f1c664"}, + {"name": "hunyuan-dense", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tencent/Hunyuan-4B-Instruct", "chkhsh": "bba3b3366b646dbdded5dbc42d59598b849371afc42f7beafa914afaa5b70aa6"}, # falcon-h1 series uses 4 different tokenizers across model sizes (0.5b - 34b), hence we need to define 4 different hashes {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-0.5B-Base", "chkhsh": "a6b57017d60e6edb4d88ecc2845188e0eb333a70357e45dcc9b53964a73bbae6"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-1B-Base", "chkhsh": "60476e1243776c4fb1b993dbd7a5f15ac22f83c80afdf425fa5ae01c8d44ef86"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-7B-Base", "chkhsh": "3eda48b4c4dc7de733d1a8b3e3b4a85243dbbf704da2ee9d42c6beced8897896"}, {"name": "falcon-h1", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/tiiuae/Falcon-H1-34B-Base", "chkhsh": "48f8e02c0359c0bbdd82f26909171fac1c18a457bb47573ed1fe3bbb2c1cfd4b"}, + {"name": "kimi-k2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/moonshotai/Kimi-K2-Base", "chkhsh": "81212dc7cdb7e0c1074ca62c5aeab0d43c9f52b8a737be7b12a777c953027890"}, + {"name": "qwen2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/Qwen/Qwen3-Embedding-0.6B", "chkhsh": "d4540891389ea895b53b399da6ac824becc30f2fba0e9ddbb98f92e55ca0e97c"}, + {"name": "grok-2", "tokt": TOKENIZER_TYPE.BPE, "repo": "https://huggingface.co/alvarobartt/grok-2-tokenizer", "chkhsh": "66b8d4e19ab16c3bfd89bce5d785fb7e0155e8648708a1f42077cb9fe002c273"}, ] def download_file_with_auth(url, token, save_path): - headers = {"Authorization": f"Bearer {token}"} + headers = {"Authorization": f"Bearer {token}"} if token else None response = sess.get(url, headers=headers) response.raise_for_status() os.makedirs(os.path.dirname(save_path), exist_ok=True) @@ -220,18 +234,19 @@ if not args.full: all_models = models.copy() models = [model for model in all_models if model["name"] not in existing_models] -logging.info(f"Downloading {len(models)} models...") -for model in models: - try: - download_model(model) - except Exception as e: - logger.error(f"Failed to download model {model['name']}. Error: {e}") +if not args.check_missing: + logging.info(f"Downloading {len(models)} models...") + for model in models: + try: + download_model(model) + except Exception as e: + logger.error(f"Failed to download model {model['name']}. Error: {e}") # generate the source code for the convert_hf_to_gguf.py:get_vocab_base_pre() function: src_ifs = "" -for model in [*all_models, *pre_computed_hashes]: +for model in [*pre_computed_hashes, *all_models]: name = model["name"] tokt = model["tokt"] chkhsh = model.get("chkhsh") @@ -239,11 +254,6 @@ for model in [*all_models, *pre_computed if tokt == TOKENIZER_TYPE.SPM or tokt == TOKENIZER_TYPE.UGM: continue - # Skip if the tokenizer folder does not exist or there are other download issues previously - if not os.path.exists(f"models/tokenizers/{name}"): - logger.warning(f"Directory for tokenizer {name} not found. Skipping...") - continue - # create the tokenizer if chkhsh is not None: # if the model has a pre-computed hash, use it @@ -253,15 +263,19 @@ for model in [*all_models, *pre_computed chkhsh = existing_models[name] else: # otherwise, compute the hash of the tokenizer + + # Fail if the tokenizer folder with config does not exist or there are other download issues previously + if not os.path.isfile(f"models/tokenizers/{name}/tokenizer_config.json"): + raise OSError(f"Config for tokenizer {name} not found. The model may not exist or is not accessible with the provided token.") + try: logger.info(f"Loading tokenizer from {f'models/tokenizers/{name}'}...") if name == "t5": tokenizer = AutoTokenizer.from_pretrained(f"models/tokenizers/{name}", use_fast=False) else: tokenizer = AutoTokenizer.from_pretrained(f"models/tokenizers/{name}") - except OSError as e: - logger.error(f"Error loading tokenizer for model {name}. The model may not exist or is not accessible with the provided token. Error: {e}") - continue # Skip to the next model if the tokenizer can't be loaded + except Exception as e: + raise OSError(f"Error loading tokenizer for model {name}.") from e chktok = tokenizer.encode(CHK_TXT) chkhsh = sha256(str(chktok).encode()).hexdigest() diff -pruN 5882+dfsg-2/convert_lora_to_gguf.py 6641+dfsg-2/convert_lora_to_gguf.py --- 5882+dfsg-2/convert_lora_to_gguf.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/convert_lora_to_gguf.py 2025-09-30 07:36:33.000000000 +0000 @@ -12,7 +12,7 @@ import json from math import prod from pathlib import Path from typing import TYPE_CHECKING, Any, Callable, Iterable, Iterator, Sequence, SupportsIndex, cast -from transformers import AutoConfig +from transformers import AutoConfig, AutoTokenizer import torch @@ -26,6 +26,8 @@ import gguf # reuse model definitions from convert_hf_to_gguf.py from convert_hf_to_gguf import LazyTorchTensor, ModelBase +from gguf.constants import GGUFValueType + logger = logging.getLogger("lora-to-gguf") @@ -340,7 +342,7 @@ if __name__ == '__main__': sys.exit(1) else: logger.info(f"Loading base model: {dir_base_model.name}") - hparams = ModelBase.load_hparams(dir_base_model) + hparams = ModelBase.load_hparams(dir_base_model, False) with torch.inference_mode(): try: @@ -369,7 +371,31 @@ if __name__ == '__main__': self.gguf_writer.add_string(gguf.Keys.Adapter.TYPE, "lora") def set_gguf_parameters(self): + logger.debug("GGUF KV: %s = %d", gguf.Keys.Adapter.LORA_ALPHA, self.lora_alpha) self.gguf_writer.add_float32(gguf.Keys.Adapter.LORA_ALPHA, self.lora_alpha) + alora_invocation_tokens = lparams.get("alora_invocation_tokens") + invocation_string = lparams.get("invocation_string") + if invocation_string and not alora_invocation_tokens: + logger.debug("Tokenizing invocation_string -> alora_invocation_tokens") + base_model_path_or_id = hparams.get("_name_or_path") + try: + tokenizer = AutoTokenizer.from_pretrained(base_model_path_or_id) + except ValueError: + logger.error("Unable to load tokenizer from %s", base_model_path_or_id) + raise + # NOTE: There's an off-by-one with the older aLoRAs where + # the invocation string includes the "<|start_of_turn|>" + # token, but the adapters themselves were trained to + # activate _after_ that first token, so we drop it here. + alora_invocation_tokens = tokenizer(invocation_string)["input_ids"][1:] + if alora_invocation_tokens: + logger.debug("GGUF KV: %s = %s", gguf.Keys.Adapter.ALORA_INVOCATION_TOKENS, alora_invocation_tokens) + self.gguf_writer.add_key_value( + gguf.Keys.Adapter.ALORA_INVOCATION_TOKENS, + alora_invocation_tokens, + GGUFValueType.ARRAY, + GGUFValueType.UINT32, + ) def generate_extra_tensors(self) -> Iterable[tuple[str, Tensor]]: # Never add extra tensors (e.g. rope_freqs) for LoRA adapters diff -pruN 5882+dfsg-2/debian/changelog 6641+dfsg-2/debian/changelog --- 5882+dfsg-2/debian/changelog 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/changelog 2025-12-23 20:24:32.000000000 +0000 @@ -1,3 +1,86 @@ +llama.cpp (6641+dfsg-2) unstable; urgency=medium + + [ Chris Lamb ] + * Add reproducible-builds.patch (Closes: #1113813) + + [ Christian Kastner ] + * autopkgtest: Explicitly limit architectures for GPU tests + * autopkgtest: Use Q4_K_M quants, as per mbaudier's suggestion + * Replace libggml0-backend-cpu dependencies with libggml0 + * autopkgtest: backend-vulkan-nvidia is also skip-not-installable + + -- Christian Kastner Tue, 23 Dec 2025 21:24:32 +0100 + +llama.cpp (6641+dfsg-1) unstable; urgency=medium + + [ Christian Kastner ] + * New upstream version 6641+dfsg + - Refresh patches + * Depend on versioned ggml + Upstream is experimenting with semantic versioning of ggml, so we can + switch our dependencies to that format. + However, because this is still experimental, we continue do depend on a + very specific version. This will be relaxed as soon as we have symbols + tracking. + * autopkgtests: Support blank lines/comments in d/t/supported-models.* + * autopkgtests: Improve upon supported test models list + * Update installed examples + - Added: llama-diffusion-cli, llama-logits + - Dropped: llama-gritlm + * d/clean: Also remove generated completions/ + + [ Kentaro Hayashi ] + * Use d/watch 5. + + -- Christian Kastner Sun, 05 Oct 2025 22:09:48 +0200 + +llama.cpp (5882+dfsg-4) unstable; urgency=medium + + * Add autopkgtests. + - The tests expect a /models directory in the testbed + - This includes a test helper for running tests on AMD and NVIDIA + GPUs, if the system has one available. + + -- Christian Kastner Sun, 14 Sep 2025 23:13:11 +0200 + +llama.cpp (5882+dfsg-3) unstable; urgency=medium + + * Upload to unstable + * Package description fixes + + -- Christian Kastner Wed, 27 Aug 2025 07:01:15 +0200 + +llama.cpp (5882+dfsg-3~exp3) experimental; urgency=medium + + [ Christian Kastner ] + * Switch over to SOVERsioned, dynamic-backend-loading ggml + * libllama0: Drop spurious python3 dependency + + [ Mathieu Baudier ] + * llama.cpp-tools: Introduce bash completion + + -- Christian Kastner Thu, 07 Aug 2025 12:43:22 +0200 + +llama.cpp (5882+dfsg-3~exp2) experimental; urgency=medium + + * Correct the Section field of a few packages + + -- Christian Kastner Mon, 14 Jul 2025 18:54:14 +0200 + +llama.cpp (5882+dfsg-3~exp1) experimental; urgency=medium + + * Split llama.cpp package into subpackages + * Build new package python3-gguf + + * d/rules: Pass in LLAMA_BUILD_{NUMBER,COMMIT} + * Add gguf-py-depends-on-the-requests-library.patch + * Add Add-soversion-to-libraries.patch + * Rename private directories llama.cpp -> llama + * Improve llama-server theme handling + * Generate manpages using help2man + + -- Christian Kastner Mon, 14 Jul 2025 17:17:43 +0200 + llama.cpp (5882+dfsg-2) unstable; urgency=medium * Build-Depend on the exact version of ggml. diff -pruN 5882+dfsg-2/debian/clean 6641+dfsg-2/debian/clean --- 5882+dfsg-2/debian/clean 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/clean 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +man/ +gguf-py/__pycache__/ +gguf-py/scripts/__pycache__/ +completions/ diff -pruN 5882+dfsg-2/debian/control 6641+dfsg-2/debian/control --- 5882+dfsg-2/debian/control 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/control 2025-12-23 20:24:32.000000000 +0000 @@ -7,28 +7,164 @@ Standards-Version: 4.7.2 Vcs-Browser: https://salsa.debian.org/deeplearning-team/llama.cpp Vcs-Git: https://salsa.debian.org/deeplearning-team/llama.cpp.git Homepage: https://github.com/ggml-org/llama.cpp/ -# We could B-D on libc6 (>= 2.33) to ensure support for Hardware Capabilities, -# but with our install layout, a lack of support means that the baseline -# version will be used in such a case. -Build-Depends: cmake, +Build-Depends: dh-sequence-bash-completion, + cmake, + dh-python, debhelper-compat (= 13), + help2man, libcurl4-openssl-dev, - libggml-cpu (>= 0.0~git20250712), - libggml-cpu (<< 0.0~git20250713), + libggml-dev (>= 0.9.4-7~), + libggml-dev (<< 0.9.5), pkgconf, +Build-Depends-Indep: dh-sequence-python3, + python3-all, + pybuild-plugin-pyproject, + python3-poetry-core, + python3-numpy, + python3-tqdm, + python3-yaml, + python3-sentencepiece, + python3-pytest, Rules-Requires-Root: no Package: llama.cpp +Architecture: all +Depends: llama.cpp-tools, + ${misc:Depends}, +Recommends: llama.cpp-tools-extra, + python3-gguf, +Suggests: llama.cpp-examples +Description: LLM inference in C/C++ - metapackage + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This is a meta-package that either depends on all of the relevant binary + packages. + +Package: libllama0 +Section: libs +Architecture: any +Multi-Arch: same +Depends: libggml0 (>= 0.9.4-7~), + libggml0 (<< 0.9.5), + ${misc:Depends}, + ${shlibs:Depends}, +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - libraries + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This package contains the libllama and libmtmd libraries. Note that these + libraries are not yet stable, so they are installed to private directories + for now. + +Package: libllama-dev +Section: libdevel +Architecture: any +Multi-Arch: same +Depends: libllama0 (= ${binary:Version}), + libggml-dev (>= 0.9.4-7~), + libggml-dev (<< 0.9.5), + ${misc:Depends}, +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - headers and development files + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This package provides the llama.cpp library headers and development files. + Note that these libraries are not yet stable, so they are installed to + private directories for now. + +Package: llama.cpp-tools +Architecture: any +Multi-Arch: foreign +Depends: libllama0 (= ${binary:Version}), + ${misc:Depends}, + ${shlibs:Depends}, +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - main utilities + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This package contains the subset of the most commonly used utilities: + llama-cli, llama-server, llama-bench, and llama-quantize. + +Package: llama.cpp-tools-extra Architecture: any Multi-Arch: foreign -Depends: libggml-cpu (>= 0.0~git20250712) - | libggml-backend (>= 0.0~git20250712), - libggml-cpu (<< 0.0~git20250713) - | libggml-backend (<< 0.0~git20250713), - python3, +Depends: llama.cpp-tools (= ${binary:Version}), ${misc:Depends}, ${shlibs:Depends}, -Description: LLM inference in C/C++ +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - extra utilities The main goal of llama.cpp is to enable LLM inference with minimal setup and state-of-the-art performance on a wide range of hardware - locally and in the cloud. @@ -47,3 +183,83 @@ Description: LLM inference in C/C++ . The compute functionality is provided by ggml. By default, ggml's CPU backend is installed, but there are many other backends for CPUs and GPUs. + . + This package contains all tools that are not already shipped in package + llama.cpp-tools. + +Package: llama.cpp-examples +Architecture: any +Multi-Arch: foreign +Depends: llama.cpp-tools (= ${binary:Version}), + ${misc:Depends}, + ${shlibs:Depends}, +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - example programs + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This package contains utilities that usptream ships as examples. + +Package: llama.cpp-tests +Architecture: any +Multi-Arch: foreign +Depends: libllama0 (= ${binary:Version}), + ${misc:Depends}, + ${shlibs:Depends}, +Breaks: llama.cpp (<< 5882+dfsg-3~exp1) +Replaces: llama.cpp (<< 5882+dfsg-3~exp1) +Description: LLM inference in C/C++ - tests + The main goal of llama.cpp is to enable LLM inference with minimal setup and + state-of-the-art performance on a wide range of hardware - locally and in the + cloud. + . + * Plain C/C++ implementation without any dependencies + * Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate + and Metal frameworks + * AVX, AVX2, AVX512 and AMX support for x86 architectures + * 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization + for faster inference and reduced memory use + * Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs + via HIP and Moore Threads MTT GPUs via MUSA) + * Vulkan and SYCL backend support + * CPU+GPU hybrid inference to partially accelerate models larger than the + total VRAM capacity + . + The compute functionality is provided by ggml. By default, ggml's CPU backend + is installed, but there are many other backends for CPUs and GPUs. + . + This package contains all of the test binaries, mainly for autopkgtests. + +Package: python3-gguf +Section: python +Architecture: all +Depends: ${python3:Depends}, + ${misc:Depends}, +Suggests: python3-pyside6.qtcore, + python3-pyside6.qtwidgets, +Description: Python library for working with GGUF files + GGUF is a file format for storing models for inference with GGML and executors + based on GGML. GGUF is a binary format that is designed for fast loading and + saving of models, and for ease of reading. Models are traditionally developed + using PyTorch or another framework, and then converted to GGUF for use in + GGML. + . + This package provides a Python library for reading and writing files in the + GGUF format, and exposes this to the CLI in the form of a few utilities. diff -pruN 5882+dfsg-2/debian/copyright 6641+dfsg-2/debian/copyright --- 5882+dfsg-2/debian/copyright 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/copyright 2025-12-23 20:24:32.000000000 +0000 @@ -121,6 +121,7 @@ License: Expat Files: debian/* Copyright: 2024-2025 Christian Kastner + 2025 Mathieu Baudier License: Expat License: Expat diff -pruN 5882+dfsg-2/debian/libllama-dev.install 6641+dfsg-2/debian/libllama-dev.install --- 5882+dfsg-2/debian/libllama-dev.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/libllama-dev.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,10 @@ +usr/lib/${DEB_HOST_MULTIARCH}/llama/*.so +# multi-modal shared libraries (mtmd, llava) are not yet in cmake config, +# so we just copy them without patching the build itself +usr/lib/${DEB_HOST_MULTIARCH}/*.so usr/lib/${DEB_HOST_MULTIARCH}/llama/ + +usr/include/llama +usr/include/*.h usr/include/llama/ + +usr/lib/${DEB_HOST_MULTIARCH}/cmake/llama/* usr/lib/${DEB_HOST_MULTIARCH}/llama/cmake-private +usr/lib/${DEB_HOST_MULTIARCH}/pkgconfig usr/lib/${DEB_HOST_MULTIARCH}/llama diff -pruN 5882+dfsg-2/debian/libllama0.install 6641+dfsg-2/debian/libllama0.install --- 5882+dfsg-2/debian/libllama0.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/libllama0.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +usr/lib/${DEB_HOST_MULTIARCH}/llama/*.so.* +# multi-modal shared libraries (mtmd, llava) are not yet in cmake config, +# so we just copy them without patching the build itself +usr/lib/${DEB_HOST_MULTIARCH}/*.so.* usr/lib/${DEB_HOST_MULTIARCH}/llama/ diff -pruN 5882+dfsg-2/debian/libllama0.lintian-overrides 6641+dfsg-2/debian/libllama0.lintian-overrides --- 5882+dfsg-2/debian/libllama0.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/libllama0.lintian-overrides 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +# libllama and ggml are both not yet stable, so they are installed in private +# directories. +libllama0: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * +libllama0: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/llama * diff -pruN 5882+dfsg-2/debian/llama.cpp-examples.install 6641+dfsg-2/debian/llama.cpp-examples.install --- 5882+dfsg-2/debian/llama.cpp-examples.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-examples.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,24 @@ +/usr/bin/llama-batched +/usr/bin/llama-diffusion-cli +/usr/bin/llama-embedding +/usr/bin/llama-eval-callback +/usr/bin/llama-finetune +/usr/bin/llama-gen-docs +/usr/bin/llama-gguf +/usr/bin/llama-gguf-hash +/usr/bin/llama-logits +/usr/bin/llama-lookahead +/usr/bin/llama-lookup +/usr/bin/llama-lookup-create +/usr/bin/llama-lookup-merge +/usr/bin/llama-lookup-stats +/usr/bin/llama-parallel +/usr/bin/llama-passkey +/usr/bin/llama-retrieval +/usr/bin/llama-save-load-state +/usr/bin/llama-simple +/usr/bin/llama-simple-chat +/usr/bin/llama-speculative +/usr/bin/llama-speculative-simple +# Not available with GGML_BACKEND_DL=ON +#/usr/bin/llama-convert-llama2c-to-ggml diff -pruN 5882+dfsg-2/debian/llama.cpp-examples.lintian-overrides 6641+dfsg-2/debian/llama.cpp-examples.lintian-overrides --- 5882+dfsg-2/debian/llama.cpp-examples.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-examples.lintian-overrides 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +# libllama and ggml are both not yet stable, so they are installed in private +# directories. +llama.cpp-examples: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * +llama.cpp-examples: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/llama * diff -pruN 5882+dfsg-2/debian/llama.cpp-examples.manpages 6641+dfsg-2/debian/llama.cpp-examples.manpages --- 5882+dfsg-2/debian/llama.cpp-examples.manpages 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-examples.manpages 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,23 @@ +man/man1/llama-batched.1 +man/man1/llama-embedding.1 +man/man1/llama-eval-callback.1 +man/man1/llama-finetune.1 +# help2man/man1 doesn't work because this doesn't have --help yet +#/man/man1/llama-gen-docs.1 +man/man1/llama-gguf.1 +man/man1/llama-gguf-hash.1 +man/man1/llama-lookahead.1 +man/man1/llama-lookup.1 +man/man1/llama-lookup-create.1 +man/man1/llama-lookup-merge.1 +man/man1/llama-lookup-stats.1 +man/man1/llama-parallel.1 +man/man1/llama-passkey.1 +man/man1/llama-retrieval.1 +man/man1/llama-save-load-state.1 +man/man1/llama-simple.1 +man/man1/llama-simple-chat.1 +man/man1/llama-speculative.1 +man/man1/llama-speculative-simple.1 +# Not available with GGML_BACKEND_DL=ON +#man/man1/llama-convert-llama2c-to-ggml.1 diff -pruN 5882+dfsg-2/debian/llama.cpp-tests.install 6641+dfsg-2/debian/llama.cpp-tests.install --- 5882+dfsg-2/debian/llama.cpp-tests.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tests.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1 @@ +usr/bin/test-* usr/libexec/${DEB_HOST_MULTIARCH}/llama.cpp-tests diff -pruN 5882+dfsg-2/debian/llama.cpp-tests.lintian-overrides 6641+dfsg-2/debian/llama.cpp-tests.lintian-overrides --- 5882+dfsg-2/debian/llama.cpp-tests.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tests.lintian-overrides 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +# libllama and ggml are both not yet stable, so they are installed in private +# directories. +llama.cpp-tests: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * +llama.cpp-tests: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/llama * diff -pruN 5882+dfsg-2/debian/llama.cpp-tools-extra.bash-completion 6641+dfsg-2/debian/llama.cpp-tools-extra.bash-completion --- 5882+dfsg-2/debian/llama.cpp-tools-extra.bash-completion 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools-extra.bash-completion 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,8 @@ +completions/llama-batched-bench +completions/llama-gguf-split +completions/llama-imatrix +completions/llama-mtmd-cli +completions/llama-perplexity +completions/llama-run +completions/llama-tokenize +completions/llama-tts diff -pruN 5882+dfsg-2/debian/llama.cpp-tools-extra.install 6641+dfsg-2/debian/llama.cpp-tools-extra.install --- 5882+dfsg-2/debian/llama.cpp-tools-extra.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools-extra.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,11 @@ +/usr/bin/llama-batched-bench +/usr/bin/llama-gguf-split +/usr/bin/llama-imatrix +/usr/bin/llama-mtmd-cli +/usr/bin/llama-perplexity +/usr/bin/llama-run +/usr/bin/llama-tokenize +/usr/bin/llama-tts +# Not available with GGML_BACKEND_DL=ON +#/usr/bin/llama-cvector-generator +#/usr/bin/llama-export-lora diff -pruN 5882+dfsg-2/debian/llama.cpp-tools-extra.lintian-overrides 6641+dfsg-2/debian/llama.cpp-tools-extra.lintian-overrides --- 5882+dfsg-2/debian/llama.cpp-tools-extra.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools-extra.lintian-overrides 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +# libllama and ggml are both not yet stable, so they are installed in private +# directories. +llama.cpp-tools-extra: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * +llama.cpp-tools-extra: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/llama * diff -pruN 5882+dfsg-2/debian/llama.cpp-tools-extra.manpages 6641+dfsg-2/debian/llama.cpp-tools-extra.manpages --- 5882+dfsg-2/debian/llama.cpp-tools-extra.manpages 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools-extra.manpages 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,11 @@ +man/man1/llama-batched-bench.1 +man/man1/llama-gguf-split.1 +man/man1/llama-imatrix.1 +man/man1/llama-mtmd-cli.1 +man/man1/llama-perplexity.1 +man/man1/llama-run.1 +man/man1/llama-tokenize.1 +man/man1/llama-tts.1 +# Not available with GGML_BACKEND_DL=ON +#man/man1/llama-cvector-generator.1 +#man/man1/llama-export-lora.1 diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.bash-completion 6641+dfsg-2/debian/llama.cpp-tools.bash-completion --- 5882+dfsg-2/debian/llama.cpp-tools.bash-completion 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.bash-completion 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +completions/llama-bench +completions/llama-cli +#completions/llama-quantize # does not actually use these options +completions/llama-server diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.install 6641+dfsg-2/debian/llama.cpp-tools.install --- 5882+dfsg-2/debian/llama.cpp-tools.install 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.install 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,13 @@ +usr/bin/llama-bench +usr/bin/llama-cli +usr/bin/llama-quantize +usr/bin/llama-server + +# This needs a ton of dependencies through python3-torch. Until we figure out +# how to best deal with it, just ship it in docs +usr/bin/convert_hf_to_gguf.py usr/share/doc/llama.cpp-tools/scripts/ + +# Install the themese but rename the simplechat directory +tools/server/public_simplechat/* usr/share/llama.cpp-tools/llama-server/themes/simplechat +tools/server/themes/buttons-top usr/share/llama.cpp-tools/llama-server/themes/ +tools/server/themes/wild usr/share/llama.cpp-tools/llama-server/themes/ diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.lintian-overrides 6641+dfsg-2/debian/llama.cpp-tools.lintian-overrides --- 5882+dfsg-2/debian/llama.cpp-tools.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.lintian-overrides 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +# libllama and ggml are both not yet stable, so they are installed in private +# directories. +llama.cpp-tools: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * +llama.cpp-tools: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/llama * diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.manpages 6641+dfsg-2/debian/llama.cpp-tools.manpages --- 5882+dfsg-2/debian/llama.cpp-tools.manpages 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.manpages 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,4 @@ +man/man1/llama-bench.1 +man/man1/llama-cli.1 +man/man1/llama-quantize.1 +man/man1/llama-server.1 diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.postinst 6641+dfsg-2/debian/llama.cpp-tools.postinst --- 5882+dfsg-2/debian/llama.cpp-tools.postinst 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.postinst 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,20 @@ +#!/bin/sh +set -e + +# Can't use dh_installalternatives because it doesn't support directories yet, +# see #1106089 + +if [ "$1" = "configure" ]; then + for theme_prio in simplechat:50 buttons-top:40 wild:40; do + theme="${theme_prio%:*}" + prio="${theme_prio#*:}" + update-alternatives --install \ + /usr/share/llama.cpp-tools/llama-server/active-theme \ + llama-server-theme \ + /usr/share/llama.cpp-tools/llama-server/themes/"$theme" "$prio" + done +fi + +#DEBHELPER# + +exit 0 diff -pruN 5882+dfsg-2/debian/llama.cpp-tools.prerm 6641+dfsg-2/debian/llama.cpp-tools.prerm --- 5882+dfsg-2/debian/llama.cpp-tools.prerm 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp-tools.prerm 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,17 @@ +#!/bin/sh +set -e + +# Can't use dh_installalternatives because it doesn't support directories yet, +# see #1106089 + +if [ "$1" = "remove" ]; then + for theme in simplechat buttons-top wild; do + update-alternatives --remove \ + llama-server-theme \ + /usr/share/llama.cpp-tools/llama-server/themes/"$theme" + done +fi + +#DEBHELPER# + +exit 0 diff -pruN 5882+dfsg-2/debian/llama.cpp.install 6641+dfsg-2/debian/llama.cpp.install --- 5882+dfsg-2/debian/llama.cpp.install 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp.install 1970-01-01 00:00:00.000000000 +0000 @@ -1,19 +0,0 @@ -usr/lib/${DEB_HOST_MULTIARCH}/llama.cpp/*.so -# multi-modal shared libraries (mtmd, llava) are not yet in cmake config, -# so we just copy them without patching the build itself -usr/lib/${DEB_HOST_MULTIARCH}/*.so usr/lib/${DEB_HOST_MULTIARCH}/llama.cpp/ -usr/include/*.h usr/include/llama.cpp/ - -usr/bin/llama-* usr/bin/ -usr/bin/convert_hf_to_gguf usr/bin/ - -usr/bin/test-* usr/libexec/${DEB_HOST_MULTIARCH}/llama.cpp - -usr/include/llama.cpp -usr/lib/${DEB_HOST_MULTIARCH}/cmake/llama/* usr/lib/${DEB_HOST_MULTIARCH}/llama.cpp/cmake-private -usr/lib/${DEB_HOST_MULTIARCH}/pkgconfig usr/lib/${DEB_HOST_MULTIARCH}/llama.cpp - -# Install the themese but rename the simplechat directory -tools/server/public_simplechat/* usr/share/llama.cpp/server/themes/simplechat -tools/server/themes/buttons-top usr/share/llama.cpp/server/themes/ -tools/server/themes/wild usr/share/llama.cpp/server/themes/ diff -pruN 5882+dfsg-2/debian/llama.cpp.lintian-overrides 6641+dfsg-2/debian/llama.cpp.lintian-overrides --- 5882+dfsg-2/debian/llama.cpp.lintian-overrides 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp.lintian-overrides 1970-01-01 00:00:00.000000000 +0000 @@ -1,10 +0,0 @@ -# ggml is a shared library that is developed in concert with llama.cpp and -# whisper.cpp, and is shipped embedded in both. It capsules all of the -# computation modes, and it's build process is relatively complex, especially -# when combined with the llama.cpp/whisper.cpp build. -# -# It makes more sense to build that library seperately, and have -# llama.cpp/whisper.cpp access its private interfaces. -llama.cpp: custom-library-search-path RUNPATH /usr/lib/x86_64-linux-gnu/ggml * -# These will be added/generated before uploading to unstable -llama.cpp: no-manual-page * diff -pruN 5882+dfsg-2/debian/llama.cpp.postinst 6641+dfsg-2/debian/llama.cpp.postinst --- 5882+dfsg-2/debian/llama.cpp.postinst 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp.postinst 1970-01-01 00:00:00.000000000 +0000 @@ -1,20 +0,0 @@ -#!/bin/sh -set -e - -# Can't use dh_installalternatives because it doesn't support directories yet, -# see #1106089 - -if [ "$1" = "configure" ]; then - for theme_prio in simplechat:50 buttons-top:40 wild:40; do - theme="${theme_prio%:*}" - prio="${theme_prio#*:}" - update-alternatives --install \ - /usr/share/llama.cpp/server/active-theme \ - llama.cpp-server-theme \ - /usr/share/llama.cpp/server/themes/"$theme" "$prio" - done -fi - -#DEBHELPER# - -exit 0 diff -pruN 5882+dfsg-2/debian/llama.cpp.prerm 6641+dfsg-2/debian/llama.cpp.prerm --- 5882+dfsg-2/debian/llama.cpp.prerm 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/llama.cpp.prerm 1970-01-01 00:00:00.000000000 +0000 @@ -1,17 +0,0 @@ -#!/bin/sh -set -e - -# Can't use dh_installalternatives because it doesn't support directories yet, -# see #1106089 - -if [ "$1" = "remove" ]; then - for theme in simplechat buttons-top wild; do - update-alternatives --remove \ - llama.cpp-server-theme \ - /usr/share/llama.cpp/server/themes/"$theme" - done -fi - -#DEBHELPER# - -exit 0 diff -pruN 5882+dfsg-2/debian/not-installed 6641+dfsg-2/debian/not-installed --- 5882+dfsg-2/debian/not-installed 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/not-installed 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1 @@ +usr/bin/llama-gen-docs diff -pruN 5882+dfsg-2/debian/patches/Add-soversion-to-libraries.patch 6641+dfsg-2/debian/patches/Add-soversion-to-libraries.patch --- 5882+dfsg-2/debian/patches/Add-soversion-to-libraries.patch 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/patches/Add-soversion-to-libraries.patch 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,34 @@ +From: Christian Kastner +Date: Sun, 13 Jul 2025 21:57:01 +0200 +Subject: Add soversion to libraries + +Forwarded: not-needed +--- + src/CMakeLists.txt | 1 + + tools/mtmd/CMakeLists.txt | 1 + + 2 files changed, 2 insertions(+) + +Index: llama.cpp/src/CMakeLists.txt +=================================================================== +--- llama.cpp.orig/src/CMakeLists.txt ++++ llama.cpp/src/CMakeLists.txt +@@ -45,6 +45,7 @@ target_link_libraries(llama PUBLIC ggml) + + if (BUILD_SHARED_LIBS) + set_target_properties(llama PROPERTIES POSITION_INDEPENDENT_CODE ON) ++ set_target_properties(llama PROPERTIES VERSION ${LLAMA_INSTALL_VERSION} SOVERSION 0) + target_compile_definitions(llama PRIVATE LLAMA_BUILD) + target_compile_definitions(llama PUBLIC LLAMA_SHARED) + endif() +Index: llama.cpp/tools/mtmd/CMakeLists.txt +=================================================================== +--- llama.cpp.orig/tools/mtmd/CMakeLists.txt ++++ llama.cpp/tools/mtmd/CMakeLists.txt +@@ -22,6 +22,7 @@ target_compile_features (mtmd PRIVATE + + if (BUILD_SHARED_LIBS) + set_target_properties (mtmd PROPERTIES POSITION_INDEPENDENT_CODE ON) ++ set_target_properties (mtmd PROPERTIES VERSION ${LLAMA_INSTALL_VERSION} SOVERSION 0) + target_compile_definitions(mtmd PRIVATE LLAMA_BUILD) + target_compile_definitions(mtmd PUBLIC LLAMA_SHARED) + endif() diff -pruN 5882+dfsg-2/debian/patches/Drop-non-DFSG-free-server-frontend.patch 6641+dfsg-2/debian/patches/Drop-non-DFSG-free-server-frontend.patch --- 5882+dfsg-2/debian/patches/Drop-non-DFSG-free-server-frontend.patch 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/patches/Drop-non-DFSG-free-server-frontend.patch 2025-12-23 20:24:32.000000000 +0000 @@ -12,11 +12,11 @@ Forwarded: not-needed tools/server/server.cpp | 15 --------------- 2 files changed, 16 deletions(-) -diff --git a/tools/server/CMakeLists.txt b/tools/server/CMakeLists.txt -index c2a56aa..acdc5d2 100644 ---- a/tools/server/CMakeLists.txt -+++ b/tools/server/CMakeLists.txt -@@ -14,7 +14,6 @@ set(TARGET_SRCS +Index: llama.cpp/tools/server/CMakeLists.txt +=================================================================== +--- llama.cpp.orig/tools/server/CMakeLists.txt ++++ llama.cpp/tools/server/CMakeLists.txt +@@ -12,7 +12,6 @@ set(TARGET_SRCS utils.hpp ) set(PUBLIC_ASSETS @@ -24,10 +24,10 @@ index c2a56aa..acdc5d2 100644 loading.html ) -diff --git a/tools/server/server.cpp b/tools/server/server.cpp -index 57b917f..bf5cc3d 100644 ---- a/tools/server/server.cpp -+++ b/tools/server/server.cpp +Index: llama.cpp/tools/server/server.cpp +=================================================================== +--- llama.cpp.orig/tools/server/server.cpp ++++ llama.cpp/tools/server/server.cpp @@ -15,7 +15,6 @@ #define MIMETYPE_JSON "application/json; charset=utf-8" @@ -36,7 +36,7 @@ index 57b917f..bf5cc3d 100644 #include "loading.html.hpp" #include -@@ -4811,20 +4810,6 @@ int main(int argc, char ** argv) { +@@ -5212,20 +5211,6 @@ int main(int argc, char ** argv) { LOG_ERR("%s: static assets path not found: %s\n", __func__, params.public_path.c_str()); return 1; } diff -pruN 5882+dfsg-2/debian/patches/Specify-default-theme-location.patch 6641+dfsg-2/debian/patches/Specify-default-theme-location.patch --- 5882+dfsg-2/debian/patches/Specify-default-theme-location.patch 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/patches/Specify-default-theme-location.patch 2025-12-23 20:24:32.000000000 +0000 @@ -10,17 +10,17 @@ Forwarded: not-needed common/common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/common/common.h b/common/common.h -index a5abe32..6ee8d48 100644 ---- a/common/common.h -+++ b/common/common.h -@@ -369,7 +369,8 @@ struct common_params { - int32_t n_cache_reuse = 0; // min chunk size to reuse from the cache via KV shifting +Index: llama.cpp/common/common.h +=================================================================== +--- llama.cpp.orig/common/common.h ++++ llama.cpp/common/common.h +@@ -427,7 +427,8 @@ struct common_params { + int32_t n_swa_checkpoints = 3; // max number of SWA checkpoints per slot std::string hostname = "127.0.0.1"; - std::string public_path = ""; // NOLINT + // Debian-specific default theme location -+ std::string public_path = "/usr/share/llama.cpp/server/active-theme"; // NOLINT ++ std::string public_path = "/usr/share/llama.cpp-tools/llama-server/active-theme"; // NOLINT std::string api_prefix = ""; // NOLINT std::string chat_template = ""; // NOLINT bool use_jinja = false; // NOLINT diff -pruN 5882+dfsg-2/debian/patches/cmake-Install-to-private-directories.patch 6641+dfsg-2/debian/patches/cmake-Install-to-private-directories.patch --- 5882+dfsg-2/debian/patches/cmake-Install-to-private-directories.patch 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/patches/cmake-Install-to-private-directories.patch 2025-12-23 20:24:32.000000000 +0000 @@ -9,38 +9,38 @@ not yet stable. cmake/llama.pc.in | 4 ++-- 2 files changed, 9 insertions(+), 5 deletions(-) -diff --git a/CMakeLists.txt b/CMakeLists.txt -index c79ccd0..0fd5375 100644 ---- a/CMakeLists.txt -+++ b/CMakeLists.txt -@@ -213,8 +213,8 @@ endif() +Index: llama.cpp/CMakeLists.txt +=================================================================== +--- llama.cpp.orig/CMakeLists.txt ++++ llama.cpp/CMakeLists.txt +@@ -223,8 +223,8 @@ endif() include(GNUInstallDirs) include(CMakePackageConfigHelpers) -set(LLAMA_INCLUDE_INSTALL_DIR ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Location of header files") -set(LLAMA_LIB_INSTALL_DIR ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Location of library files") -+set(LLAMA_INCLUDE_INSTALL_DIR ${CMAKE_INSTALL_INCLUDEDIR}/llama.cpp CACHE PATH "Location of header files") -+set(LLAMA_LIB_INSTALL_DIR ${CMAKE_INSTALL_LIBDIR}/llama.cpp CACHE PATH "Location of library files") ++set(LLAMA_INCLUDE_INSTALL_DIR ${CMAKE_INSTALL_INCLUDEDIR}/llama CACHE PATH "Location of header files") ++set(LLAMA_LIB_INSTALL_DIR ${CMAKE_INSTALL_LIBDIR}/llama CACHE PATH "Location of library files") set(LLAMA_BIN_INSTALL_DIR ${CMAKE_INSTALL_BINDIR} CACHE PATH "Location of binary files") set(LLAMA_PUBLIC_HEADERS -@@ -225,7 +225,11 @@ set_target_properties(llama +@@ -235,7 +235,11 @@ set_target_properties(llama PROPERTIES PUBLIC_HEADER "${LLAMA_PUBLIC_HEADERS}") -install(TARGETS llama LIBRARY PUBLIC_HEADER) +install(TARGETS llama -+ # On Debian, we install the library and headers to a private directory "llama.cpp" ++ # On Debian, we install the library and headers to a private directory "llama" + LIBRARY DESTINATION ${LLAMA_LIB_INSTALL_DIR} + PUBLIC_HEADER DESTINATION ${LLAMA_INCLUDE_INSTALL_DIR} +) configure_package_config_file( ${CMAKE_CURRENT_SOURCE_DIR}/cmake/llama-config.cmake.in -diff --git a/cmake/llama.pc.in b/cmake/llama.pc.in -index 6fb58b5..56d46c9 100644 ---- a/cmake/llama.pc.in -+++ b/cmake/llama.pc.in +Index: llama.cpp/cmake/llama.pc.in +=================================================================== +--- llama.cpp.orig/cmake/llama.pc.in ++++ llama.cpp/cmake/llama.pc.in @@ -1,7 +1,7 @@ prefix=@CMAKE_INSTALL_PREFIX@ exec_prefix=@CMAKE_INSTALL_PREFIX@ diff -pruN 5882+dfsg-2/debian/patches/gguf-py-depends-on-the-requests-library.patch 6641+dfsg-2/debian/patches/gguf-py-depends-on-the-requests-library.patch --- 5882+dfsg-2/debian/patches/gguf-py-depends-on-the-requests-library.patch 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/patches/gguf-py-depends-on-the-requests-library.patch 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,20 @@ +From: Christian Kastner +Date: Sun, 13 Jul 2025 14:05:51 +0200 +Subject: gguf-py depends on the requests library + +--- + gguf-py/pyproject.toml | 1 + + 1 file changed, 1 insertion(+) + +Index: llama.cpp/gguf-py/pyproject.toml +=================================================================== +--- llama.cpp.orig/gguf-py/pyproject.toml ++++ llama.cpp/gguf-py/pyproject.toml +@@ -22,6 +22,7 @@ python = ">=3.8" + numpy = ">=1.17" + tqdm = ">=4.27" + pyyaml = ">=5.1" ++requests = ">= 0.6.2" + sentencepiece = { version = ">=0.1.98,<=0.2.0", optional = true } + PySide6 = { version = "^6.9", python = ">=3.9,<3.14", optional = true } + diff -pruN 5882+dfsg-2/debian/patches/reproducible-builds.patch 6641+dfsg-2/debian/patches/reproducible-builds.patch --- 5882+dfsg-2/debian/patches/reproducible-builds.patch 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/patches/reproducible-builds.patch 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,15 @@ +Description: Make the build reproducible +Author: Chris Lamb +Last-Update: 2025-09-02 + +--- llama.cpp-5882+dfsg.orig/common/arg.cpp ++++ llama.cpp-5882+dfsg/common/arg.cpp +@@ -1297,7 +1297,7 @@ common_params_context common_params_pars + ).set_examples({LLAMA_EXAMPLE_MAIN, LLAMA_EXAMPLE_SPECULATIVE, LLAMA_EXAMPLE_LOOKUP})); + add_opt(common_arg( + {"-t", "--threads"}, "N", +- string_format("number of threads to use during generation (default: %d)", params.cpuparams.n_threads), ++ "number of threads to use during generation (default: )", + [](common_params & params, int value) { + params.cpuparams.n_threads = value; + if (params.cpuparams.n_threads <= 0) { diff -pruN 5882+dfsg-2/debian/patches/series 6641+dfsg-2/debian/patches/series --- 5882+dfsg-2/debian/patches/series 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/patches/series 2025-12-23 20:24:32.000000000 +0000 @@ -1,3 +1,6 @@ Specify-default-theme-location.patch Drop-non-DFSG-free-server-frontend.patch cmake-Install-to-private-directories.patch +gguf-py-depends-on-the-requests-library.patch +Add-soversion-to-libraries.patch +reproducible-builds.patch diff -pruN 5882+dfsg-2/debian/python3-gguf.examples 6641+dfsg-2/debian/python3-gguf.examples --- 5882+dfsg-2/debian/python3-gguf.examples 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/python3-gguf.examples 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,2 @@ +gguf-py/examples/reader.py +gguf-py/examples/writer.py diff -pruN 5882+dfsg-2/debian/python3-gguf.manpages 6641+dfsg-2/debian/python3-gguf.manpages --- 5882+dfsg-2/debian/python3-gguf.manpages 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/python3-gguf.manpages 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,6 @@ +man/man1/gguf-convert-endian.1 +man/man1/gguf-dump.1 +man/man1/gguf-new-metadata.1 +man/man1/gguf-set-metadata.1 +# Needs too many dependencies, complains about lack of display +#man/man1/gguf-edit-gui diff -pruN 5882+dfsg-2/debian/rules 6641+dfsg-2/debian/rules --- 5882+dfsg-2/debian/rules 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/rules 2025-12-23 20:24:32.000000000 +0000 @@ -1,33 +1,90 @@ #!/usr/bin/make -f #export DH_VERBOSE = 1 + export DEB_BUILD_MAINT_OPTIONS = hardening=+all +export PYBUILD_NAME=gguf +export PYBUILD_DIR=gguf-py # Both llama.cpp and the ggml it depends on are private for now -RPATH=/usr/lib/$(DEB_HOST_MULTIARCH)/ggml:/usr/lib/$(DEB_HOST_MULTIARCH)/llama.cpp +RPATH=/usr/lib/$(DEB_HOST_MULTIARCH)/ggml:/usr/lib/$(DEB_HOST_MULTIARCH)/llama + +# FOR DEB_VERSION_UPSTREAM +include /usr/share/dpkg/pkg-info.mk CMAKE_FLAGS = -DCMAKE_INSTALL_RPATH=$(RPATH) \ -DCMAKE_INSTALL_RPATH_USE_LINK_PATH=OFF \ - -DCMAKE_BUILD_TYPE=RelWithDebInfo \ -DCMAKE_PREFIX_PATH=/usr/lib/$(DEB_HOST_MULTIARCH)/ggml/cmake-private \ + -DCMAKE_BUILD_TYPE=RelWithDebInfo \ + -DLLAMA_BUILD_NUMBER=$(subst +dfsg,,$(DEB_VERSION_UPSTREAM)) \ + -DLLAMA_BUILD_COMMIT=Debian \ -DLLAMA_USE_SYSTEM_GGML=ON - %: dh $@ --buildsystem=cmake -override_dh_auto_configure: +override_dh_auto_configure-arch: dh_auto_configure -- $(CMAKE_FLAGS) +override_dh_auto_configure-indep: + dh_auto_configure --buildsystem=pybuild + +execute_after_dh_auto_build-arch: + mkdir -p man/man1 + for progname in obj-*/bin/llama-*; do \ + progname_base=$$(basename $$progname); \ + [ "$$progname_base" != "llama-gen-docs" ] || continue ; \ + help2man \ + --source=debian \ + --version-string=$(DEB_VERSION_UPSTREAM) \ + --name=$$progname_base \ + --section=1 \ + --no-info \ + --no-discard-stderr \ + $$progname > man/man1/$$progname_base.1; \ + done + +execute_after_dh_auto_install-arch: + # Bash completion file + mkdir -p completions + LD_LIBRARY_PATH=debian/tmp/usr/lib/${DEB_HOST_MULTIARCH}/llama \ + debian/tmp/usr/bin/llama-cli --device none --completion-bash \ + > completions/llama-cli + + for progname in debian/tmp/usr/bin/llama-*; do \ + progname_base=$$(basename $$progname); \ + [ "$$progname_base" != "llama-cli" ] || continue ; \ + ln -r -s completions/llama-cli completions/$$progname_base; \ + done + +override_dh_auto_build-indep: + dh_auto_build --buildsystem=pybuild + # No tests for now, as many need some kind of model we don't have override_dh_auto_test: : -override_dh_auto_install: - # We want this in debian/tmp, even though it's a single package - dh_auto_install --destdir=debian/tmp - mkdir -p debian/tmp/usr/bin - mv debian/tmp/usr/bin/convert_hf_to_gguf.py debian/tmp/usr/bin/convert_hf_to_gguf +override_dh_auto_install-indep: + dh_auto_install --buildsystem=pybuild + mkdir -p man/man1 + for progname in debian/python3-gguf/usr/bin/gguf-*; do \ + progname_base=$$(basename $$progname); \ + [ "$$progname_base" != "gguf-editor-gui" ] || continue ; \ + PYTHONPATH=gguf-py help2man \ + --source=debian \ + --version-string=$(DEB_VERSION_UPSTREAM) \ + --name=$$progname_base \ + --section=1 \ + --no-info \ + --no-discard-stderr \ + $$progname > man/man1/$$progname_base.1; \ + done + +override_dh_auto_clean-indep: + dh_auto_clean --buildsystem=pybuild execute_after_dh_auto_clean: rm -f common/build-info.cpp + +override_dh_compress: + dh_compress -X.py diff -pruN 5882+dfsg-2/debian/tests/control 6641+dfsg-2/debian/tests/control --- 5882+dfsg-2/debian/tests/control 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/tests/control 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,28 @@ +Test-Command: debian/tests/llama.cpp-tools +Features: test-name=backend-cpu +Depends: llama.cpp-tools +Restrictions: skippable, allow-stderr + +Test-Command: debian/tests/gpuisol-test-launcher amd debian/tests/llama.cpp-tools +Features: test-name=backend-hip +Depends: llama.cpp-tools, libggml0-backend-hip +Architecture: amd64 arm64 +Restrictions: skippable, allow-stderr + +Test-Command: debian/tests/gpuisol-test-launcher amd debian/tests/llama.cpp-tools +Features: test-name=backend-vulkan-amd +Architecture: amd64 arm64 +Depends: llama.cpp-tools, libggml0-backend-vulkan, mesa-vulkan-drivers +Restrictions: skippable, allow-stderr + +Test-Command: debian/tests/gpuisol-test-launcher nvidia debian/tests/llama.cpp-tools +Features: test-name=backend-cuda +Architecture: amd64 arm64 ppc64el +Depends: llama.cpp-tools, libggml0-backend-cuda +Restrictions: skippable, allow-stderr, skip-not-installable + +Test-Command: debian/tests/gpuisol-test-launcher nvidia debian/tests/llama.cpp-tools +Features: test-name=backend-vulkan-nvidia +Architecture: amd64 arm64 ppc64el +Depends: llama.cpp-tools, libggml0-backend-vulkan, nvidia-vulkan-icd +Restrictions: skippable, allow-stderr, skip-not-installable diff -pruN 5882+dfsg-2/debian/tests/gpuisol-test-launcher 6641+dfsg-2/debian/tests/gpuisol-test-launcher --- 5882+dfsg-2/debian/tests/gpuisol-test-launcher 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/tests/gpuisol-test-launcher 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,276 @@ +#!/bin/bash +# Helper for running tests on GPUs +# +# Author: Christian Kastner +# License: MIT + +usage() { + cat >&2 <<"EOF" +usage: gpuisol-test-launcher [options] VENDOR CMD [ARGS ...] + +Checks for availability of and access to a GPU from VENDOR, runs the test, and +exits with the exit code of the test, or with exit code 77 (which autopkgtest +interprets as "skipped") if no GPU was found. Optionally exports some system +data as autopkgtest artifacts. + +VENDOR can currently be either 'amd' or 'nvidia'. + +Use this helper to skip tests on ci.debian.net (which doesn't support GPUs) but +have them run on ci.ai.debian.net (which supports various GPUs from AMD and +NVIDIA), and on ci.rocm.debian.net (which as numerous AMD GPUs). + +To run the autopkgtests on your own system, in a QEMU VM or a rootless podman +container, you will need the utilities provided by package gpuisol-qemu +resp. gpuisol-podman. + +Supported options: + -h, --help + Print this help + --cd-tmp + Change directory to AUTOPKGTEST_TMP before executing the test. + +Supported environment variables: + GPUISOL_TEST_LANCHER_WITH_DMESG + If set, export dmesg before and after the test as an autopkgtest artifact. + The user in the testbed must have access to dmesg, so either the user needs + to be privileged, or dmesg must not be restricted. Restriction can be + lifted with sudo `sysctl kernel.dmesg_restrict=0`. + GPUISOL_TEST_LAUNCHER_WITH_AMD_DRI[=PATH] + If set, export firmware and possibly other GPU-specific information as an + autopkgtest artifact. The user in the testbed must have access to + "/sys/kernel/debug/dri/", which requires privileges. Alternatively, one + can bind-mount that directory to some user-readable path, eg: + `mount --bind /sys/kernel/debug/dri /tmp/foo`, and pass that path as + GPUISOL_TEST_LAUNCHER_WITH_AMD_DRI=/tmp/foo. + GPUISOL_TEST_LAUNCHER_WITH_AMD_ROCMINFO + If set, export the output of `rocminfo` as an autopkgtest artifact. + +Examples for d/tests/control, for a test with an AMD GPU: + Simple: + Test-Command: gpuisol-test-launcher amd testRunner --verbose --skip fooTest + Depends: @, gpuisol-test-launcher + Restrictions: skippable + Architecture: amd64 arm64 ppc64el + + Write your own test runner/wrapper, have gpuisol-test-launcher call it: + Test-Command: gpuisol-test-launcher amd debian/tests/my-runner + Depends: @, gpuisol-test-launcher + Restrictions: skippable + Architecture: amd64 arm64 ppc64el +EOF +} + +vendor= +opt_cd_tmp=0 +opt_with_dmesg=0 +opt_with_amd_dri=0 +opt_with_amd_rocminfo=0 +dri_path= + +# Can't use getopt because it won't stop parsing, but any options after the +# first positional argument (the test command) aren't for us, they are for +# the test command +while [[ $# -gt 0 ]]; do + case "$1" in + -h | --help) + usage + exit 0 + ;; + --cd-tmp) + opt_cd_tmp=1 + shift + ;; + --) + shift + break + ;; + -*) + echo "$0: unknown option: $1" >&2 + usage + exit 1 + ;; + *) + break + ;; + esac +done + +if [ -z "$1" ]; then + echo "Not enough arguments." >&2 + exit 1 +fi +case "$1" in +amd) + vendor=amd + ;; +nvidia) + vendor=nvidia + ;; +*) + echo "Unsupported vendor: $1" >&2 + exit 1 + ;; +esac +shift + +# Test that each variable is actually set (null or not) +if [ -n "${ROCM_TEST_LAUNCHER_WITH_DMESG+x}" ]; then + opt_with_dmesg=1 +fi +if [ -n "${ROCM_TEST_LAUNCHER_WITH_AMD_DRI+x}" ]; then + opt_with_amd_dri=1 + dri_path="${ROCM_TEST_LAUNCHER_WITH_AMD_DRI}" +fi +if [ -n "${ROCM_TEST_LAUNCHER_WITH_AMD_ROCMINFO+x}" ]; then + opt_with_amd_rocminfo=1 +fi + +if [ "$vendor" = "amd" ]; then + if [ ! -e /dev/kfd ]; then + echo "/dev/kfd not present, system either lacks AMD GPU or 'amdgpu' driver is not loaded." + echo "Skipping tests." + # Magic number to signal 'skipped' + exit 77 + elif [ "$(id -u)" != "0" ] && [ ! -r /dev/kfd ]; then + echo "/dev/kfd present but no read permission." + echo "Skipping tests." + exit 77 + fi +elif [ "$vendor" = "nvidia" ]; then + nvidia_found=0 + if [ -e /dev/nvidiactl ]; then + nvidia_found=1 + elif [ -x /usr/bin/nvidia-modprobe ] && /usr/bin/nvidia-modprobe -c 0 -u &>/dev/null; then + nvidia_found=1 + elif [ -x /usr/bin/lsmod ] && lsmod | grep -Eq '^nvidia[[:space:]]+'; then + nvidia_found=1 + fi + if [ "$nvidia_found" -ne 1 ]; then + echo "Either no NVIDIA GPU, or 'nvidia' driver is not loaded." + echo "Skipping tests." + # Magic number to signal 'skipped' + exit 77 + fi +fi + +# So that we can sort files by creation time +tstamp() { + echo "$(date '+%s.%N')" +} + +check_for_sudo() { + local msg + msg="$1" + + if ! [ -x /usr/bin/sudo ]; then + if [ -n "$msg" ]; then + echo "$0: sudo not available; $msg" >&2 + else + echo "$0: sudo not available." >&2 + fi + return 1 + else + return 0 + fi +} + +save_dmesg() { + local phase + local outfile + + phase="$1" + if [ "$phase" != "before" ] && [ "$phase" != "after" ]; then + echo "save_dmesg: unknown phase $phase" >&2 + exit 2 + fi + outfile="$AUTOPKGTEST_ARTIFACTS/$(tstamp).dmesg.$phase" + + # First, try regular dmesg, which works for root and all systems with + # kernel.dmesg_restrict=0 + dmesg >"$outfile" && return + + check_for_sudo "could not save dmesg" || return 0 + # shellcheck disable=SC2024 # we don't need privileged write + if ! sudo -n dmesg >"$outfile"; then + echo "$0: failed to save dmesg." >&2 + fi +} + +save_amd_firmware() { + local dripath + local fwinfo + local outfile + local fwfound + + dripath="${1:-/sys/kernel/debug/dri}" + + fwfound=0 + if [ -d "$dripath" ]; then + for subpath in "$dripath"/*; do + index="${subpath##*/}" + fwinfo="$subpath/amdgpu_firmware_info" + outfile="$AUTOPKGTEST_ARTIFACTS/$(tstamp).amdgpu_firmware_info.$index" + if [ -f "$fwinfo" ]; then + cat "$fwinfo" >"$outfile" + fwfound=1 + fi + done + else + # directory might be there, we just might not have permission + check_for_sudo "could not read firmware info" || return 0 + if sudo -n [ -d "$dripath" ]; then + for subpath in $(sudo -n ls "$dripath"); do + index="${subpath##*/}" + fwinfo="$subpath/amdgpu_firmware_info" + outfile="$AUTOPKGTEST_ARTIFACTS/$(tstamp).amdgpu_firmware_info.$index" + if sudo -n [ -f "$fwinfo" ]; then + # shellcheck disable=SC2024 # we don't need privileged write + sudo -n cat "$fwinfo" >"$outfile" + fwfound=1 + fi + done + else + echo "$0: Cannot access $dripath, cannot query firmware info." >&2 + return + fi + fi + if [ "$fwfound" -eq 0 ]; then + echo "$0: No firmware info found. Is $dripath populated?" >&2 + fi +} + +save_rocminfo() { + # No need to check for sudo here, as we've already verified access to + # /dev/kfd, which should be all we need + if ! [ -x /usr/bin/rocminfo ]; then + echo "$0: rocminfo not available, not saving info." >&2 + exit 1 + fi + if ! rocminfo >"$AUTOPKGTEST_ARTIFACTS/$(tstamp).rocminfo.txt"; then + echo "$0: Could not save rocminfo." >&2 + fi +} + +### Pre-test ### + +# 16 = testbed failure +if ([ "$opt_with_dmesg" -eq 1 ] \ + || [ "$opt_with_amd_dri" -eq 1 ] \ + || [ "$opt_with_amd_rocminfo" -eq 1 ]) && [ -z "$AUTOPKGTEST_ARTIFACTS" ]; then + echo "AUTOPKGTEST_ARTIFACTS not set, cannot save requested artifacts." >&2 + exit 16 +fi +[ "$opt_cd_tmp" -eq 1 ] && { cd "$AUTOPKGTEST_TMP" || exit 16; } +[ "$opt_with_dmesg" -eq 1 ] && save_dmesg "before" +[ "$opt_with_amd_dri" -eq 1 ] && save_amd_firmware "$dri_path" +[ "$opt_with_amd_rocminfo" -eq 1 ] && save_rocminfo + +### Test ### + +"$@" +exitcode=$? + +### Post-test ### + +[ "$opt_with_dmesg" -eq 1 ] && save_dmesg "after" +exit $exitcode diff -pruN 5882+dfsg-2/debian/tests/llama.cpp-tools 6641+dfsg-2/debian/tests/llama.cpp-tools --- 5882+dfsg-2/debian/tests/llama.cpp-tools 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/tests/llama.cpp-tools 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,36 @@ +#!/bin/sh +set -u + +# We need a special testbed that tells us where to find models we can use +if [ -z "${MODELS_DIR:-}" ]; then + echo "Environment variable MODELS_DIR not set, skipping tests." + exit 77 +elif ! [ -d "$MODELS_DIR" ]; then + echo "Not a directory: $MODELS_DIR" >&2 + exit 1 +fi + +if [ -z "${MODEL_NAMES:-}" ]; then + MODEL_NAMES="$(grep -Ev '^(#.*|[[:space:]]*)$' debian/tests/supported-models.non-free)" +fi + +at_least_one=0 +exitcode= +for model_name in $MODEL_NAMES; do + model_fullpath="$MODELS_DIR/$model_name" + if ! [ -f "$model_fullpath" ]; then + echo "Model $model_fullpath not found, skipping" + continue + fi + at_least_one=1 + + echo "Running tests using model: $model_fullpath" + + llama-bench -m "$model_fullpath" || exitcode=1 + + echo "Finished running tests using model: $model_fullpath" +done + +# If not a single test could be run, treat this as an overall skip +[ "$at_least_one" -ge 0 ] || exit 77 +exit $exitcode diff -pruN 5882+dfsg-2/debian/tests/supported-models.non-free 6641+dfsg-2/debian/tests/supported-models.non-free --- 5882+dfsg-2/debian/tests/supported-models.non-free 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/debian/tests/supported-models.non-free 2025-12-23 20:24:32.000000000 +0000 @@ -0,0 +1,15 @@ +# Directory/file layout follows Hugging Face's layout: +# org/model/quantization + +# ggml-org's quantiziation of OpenAI's Apache 2.0-licensed gpt-oss-20b +ggml-org/gpt-oss-20b-GGUF/gpt-oss-20b-mxfp4.gguf + +# OLMo 2 models are Apache 2.0-licensed +allenai/OLMo-2-0425-1B-Instruct-GGUF/OLMo-2-0425-1B-Instruct-Q8_0.gguf +allenai/OLMo-2-0425-1B-Instruct-GGUF/OLMo-2-0425-1B-Instruct-Q4_K_M.gguf +allenai/OLMo-2-0425-1B-Instruct-GGUF/OLMo-2-0425-1B-Instruct-F16.gguf + +# IBM's Granite models are Apache 2.0-licensed +ibm-granite/granite-3.3-2b-instruct-GGUF/granite-3.3-2b-instruct-Q4_K_M.gguf +ibm-granite/granite-3.3-2b-instruct-GGUF/granite-3.3-2b-instruct-Q8_0.gguf +ibm-granite/granite-3.3-2b-instruct-GGUF/granite-3.3-2b-instruct-f16.gguf diff -pruN 5882+dfsg-2/debian/watch 6641+dfsg-2/debian/watch --- 5882+dfsg-2/debian/watch 2025-07-13 09:16:13.000000000 +0000 +++ 6641+dfsg-2/debian/watch 2025-12-23 20:24:32.000000000 +0000 @@ -1,7 +1,10 @@ +Version: 5 + # Note that because upstream releases so frequently, tags drop off the top-20 # quickly. We could use the API but even its top-100 are insufficient to # re-download recent versions. -version=4 -opts="filenamemangle=s%(?:.*?)?b?(\d[\d.]*)\.tar\.gz%llama.cpp-$1.tar.gz%,dversionmangle=auto,repacksuffix=+dfsg" \ - https://github.com/ggml-org/llama.cpp/tags \ - (?:.*?/)?b?(\d[\d.]*)\.tar\.gz debian +Source: https://github.com/ggml-org/llama.cpp/tags +Matching-Pattern: (?:.*?/)?b?(\d[\d.]*)\.tar\.gz +Dversionmangle: auto +Filenamemangle: s%(?:.*?)?b?(\d[\d.]*)\.tar\.gz%llama.cpp-$1.tar.gz% +Repacksuffix: +dfsg diff -pruN 5882+dfsg-2/docs/backend/CANN.md 6641+dfsg-2/docs/backend/CANN.md --- 5882+dfsg-2/docs/backend/CANN.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/backend/CANN.md 2025-09-30 07:36:33.000000000 +0000 @@ -293,22 +293,32 @@ We would like to thank Tuo Dai, Shanni L ## Environment variable setup -### GGML_CANN_ASYNC_MODE - -Enables asynchronous operator submission. Disabled by default. - ### GGML_CANN_MEM_POOL -Specifies the memory pool management strategy: +Specifies the memory pool management strategy, Default is vmm. - vmm: Utilizes a virtual memory manager pool. If hardware support for VMM is unavailable, falls back to the legacy (leg) memory pool. - prio: Employs a priority queue-based memory pool management. + - leg: Uses a fixed-size buffer pool. ### GGML_CANN_DISABLE_BUF_POOL_CLEAN Controls automatic cleanup of the memory pool. This option is only effective when using the prio or leg memory pool strategies. -## TODO -- Support more models and data types. +### GGML_CANN_WEIGHT_NZ + +Converting the matmul weight format from ND to NZ to improve performance. Enabled by default. + +### GGML_CANN_ACL_GRAPH + +Operators are executed using ACL graph execution, rather than in op-by-op (eager) mode. Enabled by default. + +### GGML_CANN_GRAPH_CACHE_CAPACITY + +Maximum number of compiled CANN graphs kept in the LRU cache, default is 12. When the number of cached graphs exceeds this capacity, the least recently used graph will be evicted. + +### GGML_CANN_PREFILL_USE_GRAPH + +Enable ACL graph execution during the prefill stage, default is false. This option is only effective when FA is enabled. diff -pruN 5882+dfsg-2/docs/backend/zDNN.md 6641+dfsg-2/docs/backend/zDNN.md --- 5882+dfsg-2/docs/backend/zDNN.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/backend/zDNN.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,61 @@ +# llama.cpp for IBM zDNN Accelerator + +## Background + +IBM zDNN (Z Deep Neural Network) is a hardware acceleration library designed specifically to leverage the IBM NNPA (Neural Network Processor Assist) accelerator located within IBM Telum I and II processors. It provides significant performance improvements for neural network inference operations. + +### Llama.cpp + IBM zDNN + +The llama.cpp zDNN backend is designed to enable llama.cpp on IBM z17 and later systems via the IBM zDNN hardware acceleration library. + +## Software & Hardware Support + +| Hardware Level | Status | Verified | +| -------------------- | ------------- | -------------------------- | +| IBM z17 / LinuxONE 5 | Supported | RHEL 9.6, IBM z17, 40 IFLs | +| IBM z16 / LinuxONE 4 | Not Supported | | + +## Data Types Supported + +| Data Type | Status | +| --------- | --------- | +| F32 | Supported | +| F16 | Supported | +| BF16 | Supported | + +## CMake Options + +The IBM zDNN backend has the following CMake options that control the behaviour of the backend. + +| CMake Option | Default Value | Description | +| ------------ | ------------- | ----------------------------------- | +| `GGML_ZDNN` | `OFF` | Compile llama.cpp with zDNN support | +| `ZDNN_ROOT` | `""` | Override zDNN library lookup | + +## 1. Install zDNN Library + +Note: Using the zDNN library provided via `apt` or `yum` may not work correctly as reported in [#15772](https://github.com/ggml-org/llama.cpp/issues/15772). It is preferred that you compile from source. + +```sh +git clone --recurse-submodules https://github.com/IBM/zDNN +cd zDNN + +autoreconf . +./configure --prefix=/opt/zdnn-libs + +make build +sudo make install +``` + +## 2. Build llama.cpp + +```sh +git clone https://github.com/ggml-org/llama.cpp +cd llama.cpp + +cmake -S . -G Ninja -B build \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_ZDNN=ON \ + -DZDNN_ROOT=/opt/zdnn-libs +cmake --build build --config Release -j$(nproc) +``` diff -pruN 5882+dfsg-2/docs/build-riscv64-spacemit.md 6641+dfsg-2/docs/build-riscv64-spacemit.md --- 5882+dfsg-2/docs/build-riscv64-spacemit.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/build-riscv64-spacemit.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,89 @@ +> [!IMPORTANT] +> This build documentation is specific only to RISC-V SpacemiT SOCs. + +## Build llama.cpp locally (for riscv64) + +1. Prepare Toolchain For RISCV +~~~ +wget https://archive.spacemit.com/toolchain/spacemit-toolchain-linux-glibc-x86_64-v1.1.2.tar.xz +~~~ + +2. Build +Below is the build script: it requires utilizing RISC-V vector instructions for acceleration. Ensure the `GGML_CPU_RISCV64_SPACEMIT` compilation option is enabled. The currently supported optimization version is `RISCV64_SPACEMIT_IME1`, corresponding to the `RISCV64_SPACEMIT_IME_SPEC` compilation option. Compiler configurations are defined in the `riscv64-spacemit-linux-gnu-gcc.cmake` file. Please ensure you have installed the RISC-V compiler and set the environment variable via `export RISCV_ROOT_PATH={your_compiler_path}`. +```bash + +cmake -B build \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_CPU_RISCV64_SPACEMIT=ON \ + -DLLAMA_CURL=OFF \ + -DGGML_RVV=ON \ + -DGGML_RV_ZFH=ON \ + -DGGML_RV_ZICBOP=ON \ + -DRISCV64_SPACEMIT_IME_SPEC=RISCV64_SPACEMIT_IME1 \ + -DCMAKE_TOOLCHAIN_FILE=${PWD}/cmake/riscv64-spacemit-linux-gnu-gcc.cmake \ + -DCMAKE_INSTALL_PREFIX=build/installed + +cmake --build build --parallel $(nproc) --config Release + +pushd build +make install +popd +``` + +## Simulation +You can use QEMU to perform emulation on non-RISC-V architectures. + +1. Download QEMU +~~~ +wget https://archive.spacemit.com/spacemit-ai/qemu/jdsk-qemu-v0.0.14.tar.gz +~~~ + +2. Run Simulation +After build your llama.cpp, you can run the executable file via QEMU for simulation, for example: +~~~ +export QEMU_ROOT_PATH={your QEMU file path} +export RISCV_ROOT_PATH_IME1={your RISC-V compiler path} + +${QEMU_ROOT_PATH}/bin/qemu-riscv64 -L ${RISCV_ROOT_PATH_IME1}/sysroot -cpu max,vlen=256,elen=64,vext_spec=v1.0 ${PWD}/build/bin/llama-cli -m ${PWD}/models/Qwen2.5-0.5B-Instruct-Q4_0.gguf -t 1 +~~~ +## Performance +#### Quantization Support For Matrix +~~~ +model name : Spacemit(R) X60 +isa : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt +mmu : sv39 +uarch : spacemit,x60 +mvendorid : 0x710 +marchid : 0x8000000058000001 +~~~ + +Q4_0 +| Model | Size | Params | backend | threads | test | t/s | +| -----------| -------- | ------ | ------- | ------- | ---- |------| +Qwen2.5 0.5B |403.20 MiB|630.17 M| cpu | 4 | pp512|64.12 ± 0.26| +Qwen2.5 0.5B |403.20 MiB|630.17 M| cpu | 4 | tg128|10.03 ± 0.01| +Qwen2.5 1.5B |1011.16 MiB| 1.78 B | cpu | 4 | pp512|24.16 ± 0.02| +Qwen2.5 1.5B |1011.16 MiB| 1.78 B | cpu | 4 | tg128|3.83 ± 0.06| +Qwen2.5 3B | 1.86 GiB | 3.40 B | cpu | 4 | pp512|12.08 ± 0.02| +Qwen2.5 3B | 1.86 GiB | 3.40 B | cpu | 4 | tg128|2.23 ± 0.02| + +Q4_1 +| Model | Size | Params | backend | threads | test | t/s | +| -----------| -------- | ------ | ------- | ------- | ---- |------| +Qwen2.5 0.5B |351.50 MiB|494.03 M| cpu | 4 | pp512|62.07 ± 0.12| +Qwen2.5 0.5B |351.50 MiB|494.03 M| cpu | 4 | tg128|9.91 ± 0.01| +Qwen2.5 1.5B |964.06 MiB| 1.54 B | cpu | 4 | pp512|22.95 ± 0.25| +Qwen2.5 1.5B |964.06 MiB| 1.54 B | cpu | 4 | tg128|4.01 ± 0.15| +Qwen2.5 3B | 1.85 GiB | 3.09 B | cpu | 4 | pp512|11.55 ± 0.16| +Qwen2.5 3B | 1.85 GiB | 3.09 B | cpu | 4 | tg128|2.25 ± 0.04| + + +Q4_K +| Model | Size | Params | backend | threads | test | t/s | +| -----------| -------- | ------ | ------- | ------- | ---- |------| +Qwen2.5 0.5B |462.96 MiB|630.17 M| cpu | 4 | pp512|9.29 ± 0.05| +Qwen2.5 0.5B |462.96 MiB|630.17 M| cpu | 4 | tg128|5.67 ± 0.04| +Qwen2.5 1.5B | 1.04 GiB | 1.78 B | cpu | 4 | pp512|10.38 ± 0.10| +Qwen2.5 1.5B | 1.04 GiB | 1.78 B | cpu | 4 | tg128|3.17 ± 0.08| +Qwen2.5 3B | 1.95 GiB | 3.40 B | cpu | 4 | pp512|4.23 ± 0.04| +Qwen2.5 3B | 1.95 GiB | 3.40 B | cpu | 4 | tg128|1.73 ± 0.00| diff -pruN 5882+dfsg-2/docs/build-s390x.md 6641+dfsg-2/docs/build-s390x.md --- 5882+dfsg-2/docs/build-s390x.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/build-s390x.md 2025-09-30 07:36:33.000000000 +0000 @@ -42,18 +42,6 @@ cmake --build build --config Release -j cmake --build build --config Release -j $(nproc) ``` -- By default, NNPA is enabled when available. To disable it (not recommended): - - ```bash - cmake -S . -B build \ - -DCMAKE_BUILD_TYPE=Release \ - -DGGML_BLAS=ON \ - -DGGML_BLAS_VENDOR=OpenBLAS \ - -DGGML_NNPA=OFF - - cmake --build build --config Release -j $(nproc) - ``` - - For debug builds: ```bash @@ -76,6 +64,23 @@ cmake --build build --config Release -j cmake --build build --config Release -j $(nproc) ``` +## IBM zDNN Accelerator + +This provides acceleration using the IBM zAIU co-processor located in the Telum I and Telum II processors. Make sure to have the [IBM zDNN library](https://github.com/IBM/zDNN) installed. + +#### Compile from source from IBM + +You may find the official build instructions here: [Building and Installing zDNN](https://github.com/IBM/zDNN?tab=readme-ov-file#building-and-installing-zdnn) + +### Compilation + +```bash +cmake -S . -B build \ + -DCMAKE_BUILD_TYPE=Release \ + -DGGML_ZDNN=ON +cmake --build build --config Release -j$(nproc) +``` + ## Getting GGUF Models All models need to be converted to Big-Endian. You can achieve this in three cases: @@ -84,9 +89,9 @@ All models need to be converted to Big-E ![File Type - gguf](https://img.shields.io/badge/File_Type-gguf-fff) - You can find popular models pre-converted and verified at [s390x Ready Models](https://huggingface.co/collections/taronaeo/s390x-ready-models-672765393af438d0ccb72a08). + You can find popular models pre-converted and verified at [s390x Verified Models](https://huggingface.co/collections/taronaeo/s390x-verified-models-672765393af438d0ccb72a08) or [s390x Runnable Models](https://huggingface.co/collections/taronaeo/s390x-runnable-models-686e951824198df12416017e). - These models have already been converted from `safetensors` to `GGUF Big-Endian` and their respective tokenizers verified to run correctly on IBM z15 and later system. + These models have already been converted from `safetensors` to `GGUF` Big-Endian and their respective tokenizers verified to run correctly on IBM z15 and later system. 2. **Convert safetensors model to GGUF Big-Endian directly (recommended)** @@ -94,6 +99,14 @@ All models need to be converted to Big-E The model you are trying to convert must be in `safetensors` file format (for example [IBM Granite 3.3 2B](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct)). Make sure you have downloaded the model repository for this case. + Ensure that you have installed the required packages in advance + + ```bash + pip3 install -r requirements.txt + ``` + + Convert the `safetensors` model to `GGUF` + ```bash python3 convert_hf_to_gguf.py \ --outfile model-name-be.f16.gguf \ @@ -116,7 +129,7 @@ All models need to be converted to Big-E ![File Type - gguf](https://img.shields.io/badge/File_Type-gguf-fff) - The model you are trying to convert must be in `gguf` file format (for example [IBM Granite 3.3 2B](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct-GGUF)). Make sure you have downloaded the model file for this case. + The model you are trying to convert must be in `gguf` file format (for example [IBM Granite 3.3 2B GGUF](https://huggingface.co/ibm-granite/granite-3.3-2b-instruct-GGUF)). Make sure you have downloaded the model file for this case. ```bash python3 gguf-py/gguf/scripts/gguf_convert_endian.py model-name.f16.gguf BIG @@ -137,19 +150,15 @@ All models need to be converted to Big-E ### 1. SIMD Acceleration -Only available in IBM z15 or later system with the `-DGGML_VXE=ON` (turned on by default) compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z14/arch12. In such systems, the APIs can still run but will use a scalar implementation. - -### 2. NNPA Vector Intrinsics Acceleration - -Only available in IBM z16 or later system with the `-DGGML_NNPA=ON` (turned on when available) compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z15/arch13. In such systems, the APIs can still run but will use a scalar implementation. +Only available in IBM z15/LinuxONE 3 or later system with the `-DGGML_VXE=ON` (turned on by default) compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z14/arch12. In such systems, the APIs can still run but will use a scalar implementation. -### 3. zDNN Accelerator +### 2. zDNN Accelerator (WIP) -_Only available in IBM z16 or later system. No direction at the moment._ +Only available in IBM z17/LinuxONE 5 or later system with the `-DGGML_ZDNN=ON` compile flag. No hardware acceleration is possible with llama.cpp with older systems, such as IBM z15/arch13. In such systems, the APIs will default back to CPU routines. -### 4. Spyre Accelerator +### 3. Spyre Accelerator -_No direction at the moment._ +_Only available with IBM z17 / LinuxONE 5 or later system. No support currently available._ ## Performance Tuning @@ -189,6 +198,22 @@ IBM VXE/VXE2 SIMD acceleration depends o Answer: Please ensure that your GCC compiler is of minimum GCC 15.1.0 version, and have `binutils` updated to the latest version. If this does not fix the problem, kindly open an issue. +4. Failing to install the `sentencepiece` package using GCC 15+ + + Answer: The `sentencepiece` team are aware of this as seen in [this issue](https://github.com/google/sentencepiece/issues/1108). + + As a temporary workaround, please run the installation command with the following environment variables. + + ```bash + export CXXFLAGS="-include cstdint" + ``` + + For example, + + ```bash + CXXFLAGS="-include cstdint" pip3 install -r requirements.txt + ``` + ## Getting Help on IBM Z & LinuxONE 1. **Bugs, Feature Requests** @@ -201,46 +226,50 @@ IBM VXE/VXE2 SIMD acceleration depends o ## Appendix A: Hardware Support Matrix -| | Support | Minimum Compiler Version | -| ------- | ------- | ------------------------ | -| IBM z15 | ✅ | | -| IBM z16 | ✅ | | -| IBM z17 | ✅ | GCC 15.1.0 | +| | Support | Minimum Compiler Version | +| -------- | ------- | ------------------------ | +| IBM z15 | ✅ | | +| IBM z16 | ✅ | | +| IBM z17 | ✅ | GCC 15.1.0 | +| IBM zDNN | ✅ | | - ✅ - supported and verified to run as intended - 🚫 - unsupported, we are unlikely able to provide support ## Appendix B: SIMD Support Matrix -| | VX/VXE/VXE2 | NNPA | zDNN | Spyre | -| ---------- | ----------- | ---- | ---- | ----- | -| FP32 | ✅ | ✅ | ❓ | ❓ | -| FP16 | ✅ | ✅ | ❓ | ❓ | -| BF16 | 🚫 | 🚫 | ❓ | ❓ | -| Q4_0 | ✅ | ✅ | ❓ | ❓ | -| Q4_1 | ✅ | ✅ | ❓ | ❓ | -| Q5_0 | 🚫 | 🚫 | ❓ | ❓ | -| Q5_1 | 🚫 | 🚫 | ❓ | ❓ | -| Q8_0 | ✅ | ✅ | ❓ | ❓ | -| Q2_K | 🚫 | 🚫 | ❓ | ❓ | -| Q3_K | ✅ | ✅ | ❓ | ❓ | -| Q4_K | ✅ | ✅ | ❓ | ❓ | -| Q5_K | ✅ | ✅ | ❓ | ❓ | -| Q6_K | ✅ | ✅ | ❓ | ❓ | -| TQ1_0 | 🚫 | 🚫 | ❓ | ❓ | -| TQ2_0 | 🚫 | 🚫 | ❓ | ❓ | -| IQ2_XXS | 🚫 | 🚫 | ❓ | ❓ | -| IQ2_XS | 🚫 | 🚫 | ❓ | ❓ | -| IQ2_S | 🚫 | 🚫 | ❓ | ❓ | -| IQ3_XXS | 🚫 | 🚫 | ❓ | ❓ | -| IQ3_S | 🚫 | 🚫 | ❓ | ❓ | -| IQ1_S | 🚫 | 🚫 | ❓ | ❓ | -| IQ1_M | 🚫 | 🚫 | ❓ | ❓ | -| IQ4_NL | ✅ | ✅ | ❓ | ❓ | -| IQ4_XS | ✅ | ✅ | ❓ | ❓ | -| FP32->FP16 | 🚫 | ✅ | ❓ | ❓ | -| FP16->FP32 | 🚫 | ✅ | ❓ | ❓ | +| | VX/VXE/VXE2 | zDNN | Spyre | +|------------|-------------|------|-------| +| FP32 | ✅ | ✅ | ❓ | +| FP16 | ✅ | ✅ | ❓ | +| BF16 | 🚫 | ✅ | ❓ | +| Q4_0 | ✅ | ❓ | ❓ | +| Q4_1 | ✅ | ❓ | ❓ | +| MXFP4 | 🚫 | ❓ | ❓ | +| Q5_0 | ✅ | ❓ | ❓ | +| Q5_1 | ✅ | ❓ | ❓ | +| Q8_0 | ✅ | ❓ | ❓ | +| Q2_K | 🚫 | ❓ | ❓ | +| Q3_K | ✅ | ❓ | ❓ | +| Q4_K | ✅ | ❓ | ❓ | +| Q5_K | ✅ | ❓ | ❓ | +| Q6_K | ✅ | ❓ | ❓ | +| TQ1_0 | 🚫 | ❓ | ❓ | +| TQ2_0 | 🚫 | ❓ | ❓ | +| IQ2_XXS | 🚫 | ❓ | ❓ | +| IQ2_XS | 🚫 | ❓ | ❓ | +| IQ2_S | 🚫 | ❓ | ❓ | +| IQ3_XXS | 🚫 | ❓ | ❓ | +| IQ3_S | 🚫 | ❓ | ❓ | +| IQ1_S | 🚫 | ❓ | ❓ | +| IQ1_M | 🚫 | ❓ | ❓ | +| IQ4_NL | ✅ | ❓ | ❓ | +| IQ4_XS | ✅ | ❓ | ❓ | +| FP32->FP16 | 🚫 | ❓ | ❓ | +| FP16->FP32 | 🚫 | ❓ | ❓ | - ✅ - acceleration available - 🚫 - acceleration unavailable, will still run using scalar implementation - ❓ - acceleration unknown, please contribute if you can test it yourself + +Last Updated by **Aaron Teo (aaron.teo1@ibm.com)** on Sep 7, 2025. diff -pruN 5882+dfsg-2/docs/build.md 6641+dfsg-2/docs/build.md --- 5882+dfsg-2/docs/build.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/build.md 2025-09-30 07:36:33.000000000 +0000 @@ -59,8 +59,6 @@ cmake --build build --config Release cmake --preset arm64-windows-llvm-release -D GGML_OPENMP=OFF cmake --build build-arm64-windows-llvm-release ``` - Building for arm64 can also be done with the MSVC compiler with the build-arm64-windows-MSVC preset, or the standard CMake build instructions. However, note that the MSVC compiler does not support inline ARM assembly code, used e.g. for the accelerated Q4_0_N_M CPU kernels. - For building with ninja generator and clang compiler as default: -set path:set LIB=C:\Program Files (x86)\Windows Kits\10\Lib\10.0.22621.0\um\x64;C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.41.34120\lib\x64\uwp;C:\Program Files (x86)\Windows Kits\10\Lib\10.0.22621.0\ucrt\x64 ```bash @@ -68,6 +66,9 @@ cmake --build build --config Release cmake --build build-x64-windows-llvm-release ``` - Curl usage is enabled by default and can be turned off with `-DLLAMA_CURL=OFF`. Otherwise you need to install development libraries for libcurl. + - **Debian / Ubuntu:** `sudo apt-get install libcurl4-openssl-dev` # (or `libcurl4-gnutls-dev` if you prefer GnuTLS) + - **Fedora / RHEL / Rocky / Alma:** `sudo dnf install libcurl-devel` + - **Arch / Manjaro:** `sudo pacman -S curl` # includes libcurl headers ## BLAS Build @@ -194,13 +195,12 @@ The environment variable `GGML_CUDA_ENAB The following compilation options are also available to tweak performance: -| Option | Legal values | Default | Description | -|-------------------------------|------------------------|---------|-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| -| GGML_CUDA_FORCE_MMQ | Boolean | false | Force the use of custom matrix multiplication kernels for quantized models instead of FP16 cuBLAS even if there is no int8 tensor core implementation available (affects V100, CDNA and RDNA3+). MMQ kernels are enabled by default on GPUs with int8 tensor core support. With MMQ force enabled, speed for large batch sizes will be worse but VRAM consumption will be lower. | -| GGML_CUDA_FORCE_CUBLAS | Boolean | false | Force the use of FP16 cuBLAS instead of custom matrix multiplication kernels for quantized models | -| GGML_CUDA_F16 | Boolean | false | If enabled, use half-precision floating point arithmetic for the CUDA dequantization + mul mat vec kernels and for the q4_1 and q5_1 matrix matrix multiplication kernels. Can improve performance on relatively recent GPUs. | -| GGML_CUDA_PEER_MAX_BATCH_SIZE | Positive integer | 128 | Maximum batch size for which to enable peer access between multiple GPUs. Peer access requires either Linux or NVLink. When using NVLink enabling peer access for larger batch sizes is potentially beneficial. | -| GGML_CUDA_FA_ALL_QUANTS | Boolean | false | Compile support for all KV cache quantization type (combinations) for the FlashAttention CUDA kernels. More fine-grained control over KV cache size but compilation takes much longer. | +| Option | Legal values | Default | Description | +|-------------------------------|------------------------|---------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| GGML_CUDA_FORCE_MMQ | Boolean | false | Force the use of custom matrix multiplication kernels for quantized models instead of FP16 cuBLAS even if there is no int8 tensor core implementation available (affects V100, CDNA and RDNA3+). MMQ kernels are enabled by default on GPUs with int8 tensor core support. With MMQ force enabled, speed for large batch sizes will be worse but VRAM consumption will be lower. | +| GGML_CUDA_FORCE_CUBLAS | Boolean | false | Force the use of FP16 cuBLAS instead of custom matrix multiplication kernels for quantized models. There may be issues with numerical overflows (except for CDNA and RDNA4) and memory use will be higher. Prompt processing may become faster on recent datacenter GPUs (the custom kernels were tuned primarily for RTX 3000/4000). | +| GGML_CUDA_PEER_MAX_BATCH_SIZE | Positive integer | 128 | Maximum batch size for which to enable peer access between multiple GPUs. Peer access requires either Linux or NVLink. When using NVLink enabling peer access for larger batch sizes is potentially beneficial. | +| GGML_CUDA_FA_ALL_QUANTS | Boolean | false | Compile support for all KV cache quantization type (combinations) for the FlashAttention CUDA kernels. More fine-grained control over KV cache size but compilation takes much longer. | ## MUSA @@ -305,9 +305,8 @@ On Linux it is possible to use unified m ## Vulkan -**Windows** - -### w64devkit +### For Windows Users: +**w64devkit** Download and extract [`w64devkit`](https://github.com/skeeto/w64devkit/releases). @@ -334,7 +333,7 @@ cmake -B build -DGGML_VULKAN=ON cmake --build build --config Release ``` -### Git Bash MINGW64 +**Git Bash MINGW64** Download and install [`Git-SCM`](https://git-scm.com/downloads/win) with the default settings @@ -357,7 +356,8 @@ Now you can load the model in conversati build/bin/Release/llama-cli -m "[PATH TO MODEL]" -ngl 100 -c 16384 -t 10 -n -2 -cnv ``` -### MSYS2 +**MSYS2** + Install [MSYS2](https://www.msys2.org/) and then run the following commands in a UCRT terminal to install dependencies. ```sh pacman -S git \ @@ -373,9 +373,9 @@ cmake -B build -DGGML_VULKAN=ON cmake --build build --config Release ``` -**With docker**: +### For Docker users: -You don't need to install Vulkan SDK. It will be installed inside the container. +You don't need to install the Vulkan SDK. It will be installed inside the container. ```sh # Build the image @@ -385,32 +385,29 @@ docker build -t llama-cpp-vulkan --targe docker run -it --rm -v "$(pwd):/app:Z" --device /dev/dri/renderD128:/dev/dri/renderD128 --device /dev/dri/card1:/dev/dri/card1 llama-cpp-vulkan -m "/app/models/YOUR_MODEL_FILE" -p "Building a website can be done in 10 simple steps:" -n 400 -e -ngl 33 ``` -**Without docker**: +### For Linux users: -Firstly, you need to make sure you have installed [Vulkan SDK](https://vulkan.lunarg.com/doc/view/latest/linux/getting_started_ubuntu.html) +First, follow the official LunarG instructions for the installation and setup of the Vulkan SDK in the [Getting Started with the Linux Tarball Vulkan SDK](https://vulkan.lunarg.com/doc/sdk/latest/linux/getting_started.html) guide. -For example, on Ubuntu 22.04 (jammy), use the command below: +> [!IMPORTANT] +> After completing the first step, ensure that you have used the `source` command on the `setup_env.sh` file inside of the Vulkan SDK in your current terminal session. Otherwise, the build won't work. Additionally, if you close out of your terminal, you must perform this step again if you intend to perform a build. However, there are ways to make this persistent. Refer to the Vulkan SDK guide linked in the first step for more information about any of this. +Second, after verifying that you have followed all of the SDK installation/setup steps, use this command to make sure before proceeding: ```bash -wget -qO - https://packages.lunarg.com/lunarg-signing-key-pub.asc | apt-key add - -wget -qO /etc/apt/sources.list.d/lunarg-vulkan-jammy.list https://packages.lunarg.com/vulkan/lunarg-vulkan-jammy.list -apt update -y -apt-get install -y vulkan-sdk -# To verify the installation, use the command below: vulkaninfo ``` -Alternatively your package manager might be able to provide the appropriate libraries. -For example for Ubuntu 22.04 you can install `libvulkan-dev` instead. -For Fedora 40, you can install `vulkan-devel`, `glslc` and `glslang` packages. - -Then, build llama.cpp using the cmake command below: - +Then, assuming you have `cd` into your llama.cpp folder and there are no errors with running `vulkaninfo`, you can proceed to build llama.cpp using the CMake commands below: ```bash cmake -B build -DGGML_VULKAN=1 cmake --build build --config Release -# Test the output binary (with "-ngl 33" to offload all layers to GPU) -./bin/llama-cli -m "PATH_TO_MODEL" -p "Hi you how are you" -n 50 -e -ngl 33 -t 4 +``` + +Finally, after finishing your build, you should be able to do something like this: +```bash +# Test the output binary +# "-ngl 99" should offload all of the layers to GPU for most (if not all) models. +./build/bin/llama-cli -m "PATH_TO_MODEL" -p "Hi you how are you" -ngl 99 # You should see in the output, ggml_vulkan detected your GPU. For example: # ggml_vulkan: Using Intel(R) Graphics (ADL GT2) | uma: 1 | fp16: 1 | warp size: 32 @@ -557,6 +554,23 @@ ninja To read documentation for how to build on Android, [click here](./android.md) +## WebGPU [In Progress] + +The WebGPU backend relies on [Dawn](https://dawn.googlesource.com/dawn). Follow the instructions [here](https://dawn.googlesource.com/dawn/+/refs/heads/main/docs/quickstart-cmake.md) to install Dawn locally so that llama.cpp can find it using CMake. The currrent implementation is up-to-date with Dawn commit `bed1a61`. + +In the llama.cpp directory, build with CMake: + +``` +cmake -B build -DGGML_WEBGPU=ON +cmake --build build --config Release +``` + +### Browser Support + +WebGPU allows cross-platform access to the GPU from supported browsers. We utilize [Emscripten](https://emscripten.org/) to compile ggml's WebGPU backend to WebAssembly. Emscripten does not officially support WebGPU bindings yet, but Dawn currently maintains its own WebGPU bindings called emdawnwebgpu. + +Follow the instructions [here](https://dawn.googlesource.com/dawn/+/refs/heads/main/src/emdawnwebgpu/) to download or build the emdawnwebgpu package (Note that it might be safer to build the emdawbwebgpu package locally, so that it stays in sync with the version of Dawn you have installed above). When building using CMake, the path to the emdawnwebgpu port file needs to be set with the flag `EMDAWNWEBGPU_DIR`. + ## IBM Z & LinuxONE To read documentation for how to build on IBM Z & LinuxONE, [click here](./build-s390x.md) diff -pruN 5882+dfsg-2/docs/development/HOWTO-add-model.md 6641+dfsg-2/docs/development/HOWTO-add-model.md --- 5882+dfsg-2/docs/development/HOWTO-add-model.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/development/HOWTO-add-model.md 2025-09-30 07:36:33.000000000 +0000 @@ -23,11 +23,19 @@ The convert script reads the model confi The required steps to implement for an HF model are: -1. Define the model `Model.register` annotation in a new `Model` subclass, example: +1. Define the model `ModelBase.register` annotation in a new `TextModel` or `MmprojModel` subclass, example: ```python -@Model.register("MyModelForCausalLM") -class MyModel(Model): +@ModelBase.register("MyModelForCausalLM") +class MyModel(TextModel): + model_arch = gguf.MODEL_ARCH.MYMODEL +``` + +or + +```python +@ModelBase.register("MyModelForConditionalGeneration") +class MyModel(MmprojModel): model_arch = gguf.MODEL_ARCH.MYMODEL ``` @@ -75,9 +83,10 @@ block_mappings_cfg: dict[MODEL_TENSOR, t `transformer.blocks.{bid}.norm_1` will be mapped to `blk.{bid}.attn_norm` in GGUF. Depending on the model configuration, tokenizer, code and tensors layout, you will have to override: -- `Model#set_gguf_parameters` -- `Model#set_vocab` -- `Model#write_tensors` +- `TextModel#set_gguf_parameters` +- `MmprojModel#set_gguf_parameters` +- `ModelBase#set_vocab` +- `ModelBase#modify_tensors` NOTE: Tensor names must end with `.weight` or `.bias` suffixes, that is the convention and several tools like `quantize` expect this to proceed the weights. diff -pruN 5882+dfsg-2/docs/docker.md 6641+dfsg-2/docs/docker.md --- 5882+dfsg-2/docs/docker.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/docker.md 2025-09-30 07:36:33.000000000 +0000 @@ -110,7 +110,7 @@ You may want to pass in some different ` The defaults are: -- `MUSA_VERSION` set to `rc4.0.1` +- `MUSA_VERSION` set to `rc4.3.0` The resulting images, are essentially the same as the non-MUSA images: diff -pruN 5882+dfsg-2/docs/function-calling.md 6641+dfsg-2/docs/function-calling.md --- 5882+dfsg-2/docs/function-calling.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/function-calling.md 2025-09-30 07:36:33.000000000 +0000 @@ -21,6 +21,8 @@ Function calling is supported for all mo - Use `--chat-template-file` to override the template when appropriate (see examples below) - Generic support may consume more tokens and be less efficient than a model's native format. +- Multiple/parallel tool calling is supported on some models but disabled by default, enable it by passing `"parallel_tool_calls": true` in the completion endpoint payload. +
Show some common templates and which format handler they use diff -pruN 5882+dfsg-2/docs/multimodal/MobileVLM.md 6641+dfsg-2/docs/multimodal/MobileVLM.md --- 5882+dfsg-2/docs/multimodal/MobileVLM.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/MobileVLM.md 2025-09-30 07:36:33.000000000 +0000 @@ -194,7 +194,7 @@ llama_print_timings: total time = ## Orin compile and run ### compile ```sh -make GGML_CUDA=1 CUDA_DOCKER_ARCH=sm_87 GGML_CUDA_F16=1 -j 32 +make GGML_CUDA=1 CUDA_DOCKER_ARCH=sm_87 -j 32 ``` ### run on Orin ### case 1 diff -pruN 5882+dfsg-2/docs/multimodal/minicpmo2.6.md 6641+dfsg-2/docs/multimodal/minicpmo2.6.md --- 5882+dfsg-2/docs/multimodal/minicpmo2.6.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmo2.6.md 2025-09-30 07:36:33.000000000 +0000 @@ -13,7 +13,7 @@ If there are differences in usage, pleas Clone llama.cpp: ```bash -git clone https://github.com/ggerganov/llama.cpp +git clone https://github.com/ggml-org/llama.cpp cd llama.cpp ``` @@ -29,8 +29,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-o-2_6-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-o-2_6 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-2_6 --minicpmv-projector ../MiniCPM-o-2_6/minicpmv.projector --output-dir ../MiniCPM-o-2_6/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 4 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-o-2_6 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-2_6 --minicpmv-projector ../MiniCPM-o-2_6/minicpmv.projector --output-dir ../MiniCPM-o-2_6/ --minicpmv_version 4 python ./convert_hf_to_gguf.py ../MiniCPM-o-2_6/model # quantize int4 version diff -pruN 5882+dfsg-2/docs/multimodal/minicpmo4.0.md 6641+dfsg-2/docs/multimodal/minicpmo4.0.md --- 5882+dfsg-2/docs/multimodal/minicpmo4.0.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmo4.0.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,47 @@ +## MiniCPM-o 4 + +### Prepare models and code + +Download [MiniCPM-o-4](https://huggingface.co/openbmb/MiniCPM-o-4) PyTorch model from huggingface to "MiniCPM-o-4" folder. + + +### Build llama.cpp +Readme modification time: 20250206 + +If there are differences in usage, please refer to the official build [documentation](https://github.com/ggerganov/llama.cpp/blob/master/docs/build.md) + +Clone llama.cpp: +```bash +git clone https://github.com/ggerganov/llama.cpp +cd llama.cpp +``` + +Build llama.cpp using `CMake`: +```bash +cmake -B build +cmake --build build --config Release +``` + + +### Usage of MiniCPM-o 4 + +Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-o-4-gguf) by us) + +```bash +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-o-4 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-o-4 --minicpmv-projector ../MiniCPM-o-4/minicpmv.projector --output-dir ../MiniCPM-o-4/ --minicpmv_version 6 +python ./convert_hf_to_gguf.py ../MiniCPM-o-4/model + +# quantize int4 version +./build/bin/llama-quantize ../MiniCPM-o-4/model/ggml-model-f16.gguf ../MiniCPM-o-4/model/ggml-model-Q4_K_M.gguf Q4_K_M +``` + + +Inference on Linux or Mac +```bash +# run in single-turn mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-o-4/model/ggml-model-f16.gguf --mmproj ../MiniCPM-o-4/mmproj-model-f16.gguf -c 4096 --temp 0.7 --top-p 0.8 --top-k 100 --repeat-penalty 1.05 --image xx.jpg -p "What is in the image?" + +# run in conversation mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-o-4/model/ggml-model-Q4_K_M.gguf --mmproj ../MiniCPM-o-4/mmproj-model-f16.gguf +``` diff -pruN 5882+dfsg-2/docs/multimodal/minicpmv2.5.md 6641+dfsg-2/docs/multimodal/minicpmv2.5.md --- 5882+dfsg-2/docs/multimodal/minicpmv2.5.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmv2.5.md 2025-09-30 07:36:33.000000000 +0000 @@ -28,8 +28,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-Llama3-V-2_5-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-Llama3-V-2_5 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-Llama3-V-2_5 --minicpmv-projector ../MiniCPM-Llama3-V-2_5/minicpmv.projector --output-dir ../MiniCPM-Llama3-V-2_5/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 2 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-Llama3-V-2_5 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-Llama3-V-2_5 --minicpmv-projector ../MiniCPM-Llama3-V-2_5/minicpmv.projector --output-dir ../MiniCPM-Llama3-V-2_5/ --minicpmv_version 2 python ./convert_hf_to_gguf.py ../MiniCPM-Llama3-V-2_5/model # quantize int4 version diff -pruN 5882+dfsg-2/docs/multimodal/minicpmv2.6.md 6641+dfsg-2/docs/multimodal/minicpmv2.6.md --- 5882+dfsg-2/docs/multimodal/minicpmv2.6.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmv2.6.md 2025-09-30 07:36:33.000000000 +0000 @@ -12,7 +12,7 @@ If there are differences in usage, pleas Clone llama.cpp: ```bash -git clone https://github.com/ggerganov/llama.cpp +git clone https://github.com/ggml-org/llama.cpp cd llama.cpp ``` @@ -28,8 +28,8 @@ cmake --build build --config Release Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-V-2_6-gguf) by us) ```bash -python ./tools/mtmd/minicpmv-surgery.py -m ../MiniCPM-V-2_6 -python ./tools/mtmd/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-2_6 --minicpmv-projector ../MiniCPM-V-2_6/minicpmv.projector --output-dir ../MiniCPM-V-2_6/ --image-mean 0.5 0.5 0.5 --image-std 0.5 0.5 0.5 --minicpmv_version 3 +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-V-2_6 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-2_6 --minicpmv-projector ../MiniCPM-V-2_6/minicpmv.projector --output-dir ../MiniCPM-V-2_6/ --minicpmv_version 3 python ./convert_hf_to_gguf.py ../MiniCPM-V-2_6/model # quantize int4 version diff -pruN 5882+dfsg-2/docs/multimodal/minicpmv4.0.md 6641+dfsg-2/docs/multimodal/minicpmv4.0.md --- 5882+dfsg-2/docs/multimodal/minicpmv4.0.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmv4.0.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,47 @@ +## MiniCPM-V 4 + +### Prepare models and code + +Download [MiniCPM-V-4](https://huggingface.co/openbmb/MiniCPM-V-4) PyTorch model from huggingface to "MiniCPM-V-4" folder. + + +### Build llama.cpp +Readme modification time: 20250731 + +If there are differences in usage, please refer to the official build [documentation](https://github.com/ggerganov/llama.cpp/blob/master/docs/build.md) + +Clone llama.cpp: +```bash +git clone https://github.com/ggerganov/llama.cpp +cd llama.cpp +``` + +Build llama.cpp using `CMake`: +```bash +cmake -B build +cmake --build build --config Release +``` + + +### Usage of MiniCPM-V 4 + +Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-V-4-gguf) by us) + +```bash +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-V-4 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-4 --minicpmv-projector ../MiniCPM-V-4/minicpmv.projector --output-dir ../MiniCPM-V-4/ --minicpmv_version 5 +python ./convert_hf_to_gguf.py ../MiniCPM-V-4/model + +# quantize int4 version +./build/bin/llama-quantize ../MiniCPM-V-4/model/ggml-model-f16.gguf ../MiniCPM-V-4/model/ggml-model-Q4_K_M.gguf Q4_K_M +``` + + +Inference on Linux or Mac +```bash +# run in single-turn mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4/model/ggml-model-f16.gguf --mmproj ../MiniCPM-V-4/mmproj-model-f16.gguf -c 4096 --temp 0.7 --top-p 0.8 --top-k 100 --repeat-penalty 1.05 --image xx.jpg -p "What is in the image?" + +# run in conversation mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4/model/ggml-model-Q4_K_M.gguf --mmproj ../MiniCPM-V-4/mmproj-model-f16.gguf +``` diff -pruN 5882+dfsg-2/docs/multimodal/minicpmv4.5.md 6641+dfsg-2/docs/multimodal/minicpmv4.5.md --- 5882+dfsg-2/docs/multimodal/minicpmv4.5.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal/minicpmv4.5.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,47 @@ +## MiniCPM-V 4.5 + +### Prepare models and code + +Download [MiniCPM-V-4_5](https://huggingface.co/openbmb/MiniCPM-V-4_5) PyTorch model from huggingface to "MiniCPM-V-4_5" folder. + + +### Build llama.cpp +Readme modification time: 20250826 + +If there are differences in usage, please refer to the official build [documentation](https://github.com/ggerganov/llama.cpp/blob/master/docs/build.md) + +Clone llama.cpp: +```bash +git clone https://github.com/ggerganov/llama.cpp +cd llama.cpp +``` + +Build llama.cpp using `CMake`: +```bash +cmake -B build +cmake --build build --config Release +``` + + +### Usage of MiniCPM-V 4 + +Convert PyTorch model to gguf files (You can also download the converted [gguf](https://huggingface.co/openbmb/MiniCPM-V-4_5-gguf) by us) + +```bash +python ./tools/mtmd/legacy-models/minicpmv-surgery.py -m ../MiniCPM-V-4_5 +python ./tools/mtmd/legacy-models/minicpmv-convert-image-encoder-to-gguf.py -m ../MiniCPM-V-4_5 --minicpmv-projector ../MiniCPM-V-4_5/minicpmv.projector --output-dir ../MiniCPM-V-4_5/ --minicpmv_version 6 +python ./convert_hf_to_gguf.py ../MiniCPM-V-4_5/model + +# quantize int4 version +./build/bin/llama-quantize ../MiniCPM-V-4_5/model/ggml-model-f16.gguf ../MiniCPM-V-4_5/model/ggml-model-Q4_K_M.gguf Q4_K_M +``` + + +Inference on Linux or Mac +```bash +# run in single-turn mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4_5/model/ggml-model-f16.gguf --mmproj ../MiniCPM-V-4_5/mmproj-model-f16.gguf -c 4096 --temp 0.7 --top-p 0.8 --top-k 100 --repeat-penalty 1.05 --image xx.jpg -p "What is in the image?" + +# run in conversation mode +./build/bin/llama-mtmd-cli -m ../MiniCPM-V-4_5/model/ggml-model-Q4_K_M.gguf --mmproj ../MiniCPM-V-4_5/mmproj-model-f16.gguf +``` diff -pruN 5882+dfsg-2/docs/multimodal.md 6641+dfsg-2/docs/multimodal.md --- 5882+dfsg-2/docs/multimodal.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/multimodal.md 2025-09-30 07:36:33.000000000 +0000 @@ -97,6 +97,9 @@ NOTE: some models may require large cont # Qwen2-Audio and SeaLLM-Audio # note: no pre-quantized GGUF this model, as they have very poor result # ref: https://github.com/ggml-org/llama.cpp/pull/13760 + +# Mistral's Voxtral +(tool_name) -hf ggml-org/Voxtral-Mini-3B-2507-GGUF ``` **Mixed modalities**: diff -pruN 5882+dfsg-2/docs/ops/BLAS.csv 6641+dfsg-2/docs/ops/BLAS.csv --- 5882+dfsg-2/docs/ops/BLAS.csv 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/ops/BLAS.csv 2025-09-30 07:36:33.000000000 +0000 @@ -1,6534 +1,8133 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SILU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[100,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[1024,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[1024,12,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[2000,10,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGMAX","type=f32,ne=[5438,3,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f32,ne=[10,10,10,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f32,ne=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f32,ne=[2,1,3,5]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f32,ne=[2,3,5,7]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f16,ne=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f16,ne=[2,1,3,5]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=f16,ne=[2,3,5,7]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=bf16,ne=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=bf16,ne=[2,1,3,5]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONT","type=bf16,ne=[2,3,5,7]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=0,m=32,n=1024,k=16","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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-"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQR","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQRT","type=f16,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LOG","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIN","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COS","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQR","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SQRT","type=f32,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LOG","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SIN","type=f32,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","COS","type=f32,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[8,1,1,1],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[16,10,10,10],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARGSORT","type=f32,ne=[60,10,10,10],order=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUM","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","MEAN","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" -"2025-07-10T14:15:03Z","b8a6ff407","BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Accelerate","BLAS" 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+"BLAS","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","BLAS" +"BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","BLAS" +"BLAS","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","BLAS" +"BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","BLAS" +"BLAS","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","no","BLAS" +"BLAS","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","no","BLAS" diff -pruN 5882+dfsg-2/docs/ops/CANN.csv 6641+dfsg-2/docs/ops/CANN.csv --- 5882+dfsg-2/docs/ops/CANN.csv 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/ops/CANN.csv 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,8133 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"CANN0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","CANN" +"CANN0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","CANN" +"CANN0","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","CANN" +"CANN0","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","CANN" +"CANN0","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","CANN" +"CANN0","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","CANN" +"CANN0","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","1","yes","CANN" +"CANN0","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","1","yes","CANN" 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+"CANN0","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","CANN" +"CANN0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","no","CANN" +"CANN0","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","no","CANN" diff -pruN 5882+dfsg-2/docs/ops/CPU.csv 6641+dfsg-2/docs/ops/CPU.csv --- 5882+dfsg-2/docs/ops/CPU.csv 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/ops/CPU.csv 2025-09-30 07:36:33.000000000 +0000 @@ -1,6534 +1,7349 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","RELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","RELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 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Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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-"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" -"2025-07-09T15:15:35Z","26a48ad6","CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","AMD Ryzen 7 3800XT 8-Core Processor","CPU" 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+"CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","yes","CPU" +"CPU","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" +"CPU","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","1","yes","CPU" +"CPU","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","1","yes","CPU" diff -pruN 5882+dfsg-2/docs/ops/CUDA.csv 6641+dfsg-2/docs/ops/CUDA.csv --- 5882+dfsg-2/docs/ops/CUDA.csv 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/ops/CUDA.csv 2025-09-30 07:36:33.000000000 +0000 @@ -1,6534 +1,7349 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[100,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[1024,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[1024,12,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[2000,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGMAX","type=f32,ne=[5438,3,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[10,10,10,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f32,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=f16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,1,3,5]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONT","type=bf16,ne=[2,3,5,7]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=0,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","LOG","type=f16,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SIN","type=f16,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","COS","type=f16,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SQR","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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-"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUM","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","MEAN","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" -"2025-07-09T15:15:24Z","26a48ad6","CUDA0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","NVIDIA GeForce RTX 3090","CUDA" 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5882+dfsg-2/docs/ops/Metal.csv 6641+dfsg-2/docs/ops/Metal.csv --- 5882+dfsg-2/docs/ops/Metal.csv 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/ops/Metal.csv 2025-09-30 07:36:33.000000000 +0000 @@ -1,6534 +1,8133 @@ -"test_time","build_commit","backend_name","op_name","op_params","test_mode","supported","passed","error_message","time_us","flops","bandwidth_gb_s","memory_kb","n_runs","device_description","backend_reg_name" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f16,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[128,2,2,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[5,7,11,13],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ABS","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SGN","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NEG","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","STEP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TANH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_QUICK","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSWISH","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","HARDSIGMOID","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","EXP","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[128,2,2,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GELU_ERF","type=f32,ne_a=[5,7,11,13],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=0,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,swapped=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,swapped=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[128,2,2,2],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f16,ne_a=[5,7,11,13],v=1,split","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=0,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SWIGLU","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_ERF","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,swapped=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[128,2,2,2],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GEGLU_QUICK","type=f32,ne_a=[5,7,11,13],v=1,split","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=1,m=8,r=2,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f32,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=f16,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=bf16,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_1,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_1,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q8_0,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q2_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q3_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q4_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q5_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=q6_K,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xxs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_xs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq2_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_xxs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq1_m,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_nl,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq3_s,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=iq4_xs,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS","type=i32,n=256,m=5,r=4,b=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=1,m=8,r=2,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f32,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f16,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=f16,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=bf16,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=bf16,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_1,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_1,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_1,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_1,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q8_0,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q2_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q2_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q3_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q3_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q4_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q5_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q6_K,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=q6_K,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xxs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xxs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_xs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq2_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_xxs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_xxs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_m,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq1_m,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_nl,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_nl,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_s,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq3_s,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_xs,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=iq4_xs,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GET_ROWS_BACK","type=i32,n=256,m=5,r=4,b=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[1,8,1,3],nr23=[1,1],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET_ROWS","type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_2D_DW","ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_1D","ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_2D","ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONV_TRANSPOSE_2D","ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COUNT_EQUAL","type=f32,ne=[4,500,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COUNT_EQUAL","type=f32,ne=[4,5000,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[100,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[1024,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[1024,12,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[2000,10,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGMAX","type=f32,ne=[5438,3,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i32,ne=[10,5,4,1],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i16,ne=[10,5,4,1],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT","type=i16,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","REPEAT_BACK","type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,20,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i32,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,10,20,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,5,1],permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f32,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=f16,ne=[10,10,5,1],permute=[1,0,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,8,3,1],permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DUP","type=i16,ne=[10,8,3,1],permute=[1,2,0,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SET","type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CPY","type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[10,10,10,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f32,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=f16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,1,3,5]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONT","type=bf16,ne=[2,3,5,7]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,8,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1,1],nr=[32,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,320,320],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[2,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,1,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,1,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[1,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[10,5,4,3],nr=[2,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,16,16,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,16,16,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1280,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1280,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[16,16,1280,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1920,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,2560,1],nr=[16,16,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1280,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,1920,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[1,1,640,1],nr=[32,32,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[5120,1,1,1],nr=[1,256,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f16,ne=[640,1,1,1],nr=[1,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,8,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1,1],nr=[32,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,320,320],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[2,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,1,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,1,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[1,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[10,5,4,3],nr=[2,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,16,16,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,16,16,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1280,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[16,16,1280,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[1,1,640,1],nr=[32,32,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUB","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIV","type=f32,ne=[640,1,1,1],nr=[1,1,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ADD1","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SILU_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000100","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.000100","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RMS_NORM_MUL","type=f32,ne=[64,5,4,3],eps=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=4,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_0,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_K,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[4,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[4,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[8,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=0,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=16,n_used=16,b=1,m=32,n=1024,k=16","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f32,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=f16,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_0,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_K,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=4,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=1,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=2,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=0,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xxs,type_b=f32,n_mats=8,n_used=4,b=1,m=512,n=129,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q4_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_1,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q8_0,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q2_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q3_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q5_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=q6_K,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq2_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_xxs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq1_m,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_nl,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq3_s,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=iq4_xs,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=1,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MUL_MAT_ID","type_a=bf16,type_b=f32,n_mats=4,n_used=2,b=0,m=512,n=32,k=256","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f32,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=f16,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q8_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_0,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_1,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=q4_K,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f32,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=1,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=1,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[1,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,1],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[1,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,1],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OUT_PROD","type_a=iq2_xxs,type_b=f16,m=256,n=16,k=16,bs=[3,3],nr=[2,2],trans_b=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQR","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQRT","type=f16,ne=[10,3,3,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LOG","type=f16,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIN","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COS","type=f16,ne=[10,2,2,2]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CLAMP","type=f16,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQR","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SQRT","type=f32,ne=[10,3,3,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LOG","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SIN","type=f32,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","COS","type=f32,ne=[10,2,2,2]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CLAMP","type=f32,ne=[10,5,4,3],min=-0.500000,max=0.500000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,1,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,3,1],n_past=5","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","DIAG_MASK_INF","type=f32,ne=[10,10,3,2],n_past=5","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=1.000000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f32,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f32,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,16,1,3],mask=1,m_prec=f16,nr23=[3,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,15,1,1],mask=1,m_prec=f16,nr23=[2,3],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[15,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,16,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,15,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1024,1024,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[1023,1023,1,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[16,2,32,1],mask=0,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=0.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f32,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX","type=f32,ne=[32,2,32,1],mask=1,m_prec=f16,nr23=[1,1],scale=0.100000,max_bias=8.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=0.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=1.000000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[16,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[15,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,16,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,15,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1024,1024,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SOFT_MAX_BACK","type=f32,ne=[1023,1023,1,1],scale=0.100000,max_bias=8.000000","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,40,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,52,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,64,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,1,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,71,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,8,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.000000,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=0,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ROPE_BACK","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.746500,af=1.424500,ff=1,v=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=2","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=0,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=1,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=2,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=f32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CONCAT","type=i32,ne_a=[11,12,13,14],ne_b_d=7,dim=3,v=3","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[8,1,1,1],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[16,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[60,10,10,10],order=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[8,1,1,1],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[16,10,10,10],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARGSORT","type=f32,ne=[60,10,10,10],order=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=nearest,transpose=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=0","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=0","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[512,512,3,2],scale_factor=2,mode=bilinear,transpose=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[5,7,11,13],ne_tgt=[2,5,7,11],mode=1","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","UPSCALE","type=f32,ne=[2,5,7,11],ne_tgt=[5,7,11,13],mode=257","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUM","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","SUM_ROWS","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","MEAN","type=f32,ne=[10,5,4,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GROUP_NORM","type=f32,ne=[64,64,320,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","GROUP_NORM","type=f32,ne=[9,9,1280,1],num_groups=32,eps=0.000001","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ACC","type=f32,ne_a=[256,17,1,1],ne_b=[256,16,1,1]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","PAD","type=f32,ne_a=[512,512,1,1],pad_0=1,pad_1=1","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","PAD_REFLECT_1D","type=f32,ne_a=[512,34,2,1],pad_0=10,pad_1=9","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","ARANGE","type=f32,start=0.000000,stop=10.000000,step=1.000000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","TIMESTEP_EMBEDDING","type=f32,ne_a=[2,1,1,1],dim=320,max_period=10000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","LEAKY_RELU","type=f32,ne_a=[10,5,4,3],negative_slope=0.100000","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[1,3],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=64,hsv=64,nh=4,nr23=[4,3],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=80,hsv=80,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=128,hsv=128,nh=4,nr23=[16,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=10.000000,prec=def,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=128,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=192,hsv=192,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=256,hsv=256,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","1","yes","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,2,1,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=1,max_bias=8.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" -"2025-07-10T14:14:27Z","b8a6ff407","Metal","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","0","no","0.000000","0.000000","0.000000","0","0","Apple M2 Ultra","Metal" +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"Metal","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" +"Metal","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Metal" +"Metal","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Metal" 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+"Metal","POOL_2D","pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0","support","1","yes","Metal" +"Metal","POOL_2D","pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","0","no","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0","support","1","yes","Metal" +"Metal","IM2COL","type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0","support","0","no","Metal" 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+"Metal","SUB","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","SUB","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","MUL","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","DIV","type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=2","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[1,2,1,1],nf=3","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=4","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[1,1,1,2],nf=5","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=6","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=7","support","1","yes","Metal" +"Metal","ADD","type=f32,ne=[16,5,4,3],nr=[2,2,2,2],nf=8","support","1","yes","Metal" +"Metal","ADD1","type=f32,ne=[10,5,4,3]","support","0","no","Metal" +"Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000","support","1","yes","Metal" +"Metal","SCALE","type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000","support","1","yes","Metal" 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+"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000001","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","yes","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.000100","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","no","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.000100","support","0","no","Metal" +"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.000100","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","yes","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=0,eps=0.100000","support","1","yes","Metal" +"Metal","NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","no","Metal" +"Metal","RMS_NORM","type=f32,ne=[64,5,4,3],v=1,eps=0.100000","support","0","no","Metal" +"Metal","RMS_NORM_BACK","type=f32,ne=[64,5,4,3],eps=0.100000","support","0","no","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=1","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=0","support","1","yes","Metal" +"Metal","RMS_NORM_MUL_ADD","type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=1","support","1","yes","Metal" +"Metal","L2_NORM","type=f32,ne=[64,5,4,3]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1024,1,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,4,1],ne_b=[3,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[3,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,1,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,2048,1,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[3,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,1,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1024,1,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","SSM_SCAN","type=f32,d_state=256,head_dim=64,n_head=8,n_group=2,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV6","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","1","yes","Metal" +"Metal","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","no","Metal" +"Metal","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","no","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" 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+"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[1,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[1,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=128,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1056,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1057,n=1,k=129,bs=[2,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=129,n=1,k=1057,bs=[2,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[2,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Metal" +"Metal","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[2,1],nr=[4,1],per=[0,1,2,3],v=1","support","1","yes","Metal" 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+"Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=20,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,32,2,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,32,4,1],n_dims=32,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=128,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,12,2,1],n_dims=20,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,28,2,1],n_dims=32,mode=8,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[80,16,2,1],n_dims=80,mode=24,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.000000,af=1.424500,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.000000,ef=0.746500,af=1.000000,ff=0,v=0","support","1","yes","Metal" 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+"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f32,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=0","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[64,128,2,1],n_dims=64,mode=2,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=0,v=1","support","1","yes","Metal" +"Metal","ROPE","type=f16,ne_a=[128,32,2,1],n_dims=128,mode=0,n_ctx=512,fs=1.424500,ef=0.000000,af=1.000000,ff=1,v=0","support","1","yes","Metal" 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+"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=3,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=32,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[1,1],kv=1024,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=f16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=bf16,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=1,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" 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+"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q8_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","0","no","OpenCL" +"OpenCL","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","OpenCL" +"OpenCL","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","OpenCL" +"OpenCL","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","OpenCL" +"OpenCL","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","no","OpenCL" +"OpenCL","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","0","no","OpenCL" diff -pruN 5882+dfsg-2/docs/ops/SYCL.csv 6641+dfsg-2/docs/ops/SYCL.csv --- 5882+dfsg-2/docs/ops/SYCL.csv 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/ops/SYCL.csv 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,8133 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"SYCL0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" +"SYCL0","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","1","yes","SYCL" +"SYCL0","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","1","yes","SYCL" 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5882+dfsg-2/docs/ops/Vulkan.csv 6641+dfsg-2/docs/ops/Vulkan.csv --- 5882+dfsg-2/docs/ops/Vulkan.csv 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/ops/Vulkan.csv 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,8133 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"Vulkan0","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" +"Vulkan0","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","Vulkan" +"Vulkan0","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","Vulkan" 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+"Vulkan0","SSM_CONV","type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_CONV","type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]","support","0","no","Vulkan" +"Vulkan0","SSM_SCAN","type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","SSM_SCAN","type=f32,d_state=128,head_dim=64,n_head=16,n_group=2,n_seq_tokens=32,n_seqs=4","support","0","no","Vulkan" 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+"Vulkan0","RWKV_WKV7","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","1","yes","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=1,n_seqs=1","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=1","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=32,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","GATED_LINEAR_ATTN","type=f32,head_count=32,head_size=64,n_seq_tokens=128,n_seqs=4","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=2,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=3,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=4,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=5,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=6,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=7,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=8,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=9,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[2,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,2],per=[0,1,2,3],v=0","support","0","no","Vulkan" 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+"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[3,2],nr=[2,2],per=[0,1,2,3],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,2,1,3],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,1,3,2],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=256,bs=[2,3],nr=[1,1],per=[0,3,2,1],v=0","support","0","no","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=1,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=8,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xxs,type_b=f16,m=16,n=16,k=1024,bs=[3,2],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q4_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_1,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q8_0,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q2_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q3_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q5_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=q6_K,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq2_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_xxs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq1_m,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=32,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_nl,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq3_s,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=iq4_xs,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=1,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=16,n=1,k=256,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=128,bs=[8,1],nr=[1,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=83,n=2,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=64,n=45,k=128,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=45,k=64,bs=[8,1],nr=[4,1],per=[0,1,2,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=193,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=67,bs=[1,1],nr=[4,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=128,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1056,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=bf16,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=1056,n=1,k=129,bs=[1,1],nr=[1,1],per=[0,2,1,3],v=0","support","1","yes","Vulkan" +"Vulkan0","MUL_MAT","type_a=f32,type_b=f32,m=128,n=1,k=1057,bs=[1,1],nr=[1,1],per=[0,1,2,3],v=1","support","1","yes","Vulkan" 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+"Vulkan0","FLASH_ATTN_EXT","hsk=576,hsv=512,nh=4,nr23=[4,1],kv=512,nb=35,mask=0,max_bias=0.000000,logit_softcap=0.000000,prec=f32,type_KV=q4_0,permute=[0,1,2,3]","support","1","yes","Vulkan" +"Vulkan0","CROSS_ENTROPY_LOSS","type=f32,ne=[10,5,4,3]","support","0","no","Vulkan" +"Vulkan0","CROSS_ENTROPY_LOSS","type=f32,ne=[30000,1,1,1]","support","0","no","Vulkan" +"Vulkan0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[10,5,4,3]","support","0","no","Vulkan" +"Vulkan0","CROSS_ENTROPY_LOSS_BACK","type=f32,ne=[30000,1,1,1]","support","0","no","Vulkan" +"Vulkan0","OPT_STEP_ADAMW","type=f32,ne=[10,5,4,3]","support","1","yes","Vulkan" diff -pruN 5882+dfsg-2/docs/ops/zDNN.csv 6641+dfsg-2/docs/ops/zDNN.csv --- 5882+dfsg-2/docs/ops/zDNN.csv 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/docs/ops/zDNN.csv 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,12354 @@ +"backend_name","op_name","op_params","test_mode","supported","error_message","backend_reg_name" +"zDNN","ABS","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","ABS","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","SGN","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","SGN","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","NEG","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","NEG","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","STEP","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","STEP","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","TANH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","TANH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","ELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","ELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","RELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","RELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","SIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","SIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","GELU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","GELU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","GELU_QUICK","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","GELU_QUICK","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","SILU","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","SILU","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","HARDSWISH","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","HARDSWISH","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" +"zDNN","HARDSIGMOID","type=f16,ne_a=[128,2,2,2],v=0","support","0","no","zDNN" +"zDNN","HARDSIGMOID","type=f16,ne_a=[5,7,11,13],v=0","support","0","no","zDNN" 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+"zDNN","OPT_STEP_SGD","type=f32,ne=[10,5,4,3]","support","0","no","zDNN" diff -pruN 5882+dfsg-2/docs/ops.md 6641+dfsg-2/docs/ops.md --- 5882+dfsg-2/docs/ops.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/docs/ops.md 2025-09-30 07:36:33.000000000 +0000 @@ -2,94 +2,109 @@ List of GGML operations and backend support status. +## How to add a backend to this table: + +1. Run `test-backend-ops support --output csv` with your backend name and redirect output to a csv file in `docs/ops/` (e.g., `docs/ops/CUDA.csv`) +2. Regenerate `/docs/ops.md` via `./scripts/create_ops_docs.py` + Legend: - ✅ Fully supported by this backend - 🟡 Partially supported by this backend - ❌ Not supported by this backend -| Operation | BLAS | CPU | CUDA | Metal | -|-----------|------|------|------|------| -| ABS | ❌ | ✅ | 🟡 | ❌ | -| ACC | ❌ | ✅ | ✅ | ✅ | -| ADD | ❌ | ✅ | ✅ | 🟡 | -| ADD1 | ❌ | ✅ | ✅ | ❌ | -| ARANGE | ❌ | ✅ | ✅ | ✅ | -| ARGMAX | ❌ | ✅ | ✅ | ✅ | -| ARGSORT | ❌ | ✅ | ✅ | ✅ | -| CLAMP | ❌ | ✅ | ✅ | 🟡 | -| CONCAT | ❌ | ✅ | 🟡 | ✅ | -| CONT | ❌ | ✅ | 🟡 | ✅ | -| CONV_2D_DW | ❌ | ✅ | ✅ | ❌ | -| CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | -| CONV_TRANSPOSE_2D | ❌ | ✅ | ✅ | ❌ | -| COS | ❌ | ✅ | ✅ | 🟡 | -| COUNT_EQUAL | ❌ | ✅ | ✅ | ❌ | -| CPY | ❌ | 🟡 | 🟡 | 🟡 | -| CROSS_ENTROPY_LOSS | ❌ | ✅ | ✅ | ❌ | -| CROSS_ENTROPY_LOSS_BACK | ❌ | ✅ | ✅ | ❌ | -| DIAG_MASK_INF | ❌ | ✅ | ✅ | 🟡 | -| DIV | ❌ | ✅ | ✅ | 🟡 | -| DUP | ❌ | ✅ | 🟡 | 🟡 | -| ELU | ❌ | ✅ | ❌ | 🟡 | -| EXP | ❌ | ✅ | 🟡 | ❌ | -| FLASH_ATTN_EXT | ❌ | ✅ | 🟡 | 🟡 | -| GATED_LINEAR_ATTN | ❌ | ✅ | ✅ | ❌ | -| GEGLU | ❌ | ✅ | ✅ | 🟡 | -| GEGLU_ERF | ❌ | ✅ | ✅ | 🟡 | -| GEGLU_QUICK | ❌ | ✅ | ✅ | 🟡 | -| GELU | ❌ | ✅ | 🟡 | 🟡 | -| GELU_ERF | ❌ | ✅ | 🟡 | 🟡 | -| GELU_QUICK | ❌ | ✅ | 🟡 | 🟡 | -| GET_ROWS | ❌ | ✅ | 🟡 | ✅ | -| GET_ROWS_BACK | ❌ | 🟡 | 🟡 | ❌ | -| GROUP_NORM | ❌ | ✅ | ✅ | ✅ | -| HARDSIGMOID | ❌ | ✅ | 🟡 | ❌ | -| HARDSWISH | ❌ | ✅ | 🟡 | ❌ | -| IM2COL | ❌ | ✅ | ✅ | 🟡 | -| L2_NORM | ❌ | ✅ | ✅ | ✅ | -| LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | -| LOG | ❌ | ✅ | ✅ | ❌ | -| MEAN | ❌ | ✅ | ✅ | ✅ | -| MUL | ❌ | ✅ | ✅ | 🟡 | -| MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | -| MUL_MAT_ID | ❌ | ✅ | ✅ | ✅ | -| NEG | ❌ | ✅ | 🟡 | 🟡 | -| NORM | ❌ | ✅ | ✅ | 🟡 | -| OPT_STEP_ADAMW | ❌ | ✅ | ✅ | ❌ | -| OUT_PROD | 🟡 | 🟡 | 🟡 | ❌ | -| PAD | ❌ | ✅ | ✅ | ✅ | -| PAD_REFLECT_1D | ❌ | ✅ | ❌ | ✅ | -| POOL_2D | ❌ | ✅ | ✅ | ✅ | -| REGLU | ❌ | ✅ | ✅ | 🟡 | -| RELU | ❌ | ✅ | 🟡 | 🟡 | -| REPEAT | ❌ | ✅ | 🟡 | ✅ | -| REPEAT_BACK | ❌ | ✅ | ✅ | ❌ | -| RMS_NORM | ❌ | ✅ | ✅ | 🟡 | -| RMS_NORM_BACK | ❌ | ✅ | ✅ | ❌ | -| RMS_NORM_MUL | ❌ | ✅ | ✅ | ✅ | -| ROPE | ❌ | ✅ | ✅ | ✅ | -| ROPE_BACK | ❌ | ✅ | ✅ | ❌ | -| RWKV_WKV6 | ❌ | ✅ | ✅ | ✅ | -| RWKV_WKV7 | ❌ | ✅ | ✅ | ✅ | -| SCALE | ❌ | ✅ | ✅ | ✅ | -| SET | ❌ | ✅ | ❌ | ✅ | -| SET_ROWS | ❌ | 🟡 | ❌ | 🟡 | -| SGN | ❌ | ✅ | 🟡 | ❌ | -| SIGMOID | ❌ | ✅ | 🟡 | 🟡 | -| SILU | ❌ | ✅ | 🟡 | 🟡 | -| SILU_BACK | ❌ | ✅ | ✅ | ❌ | -| SIN | ❌ | ✅ | ✅ | 🟡 | -| SOFT_MAX | ❌ | ✅ | ✅ | ✅ | -| SOFT_MAX_BACK | ❌ | 🟡 | 🟡 | ❌ | -| SQR | ❌ | ✅ | ✅ | 🟡 | -| SQRT | ❌ | ✅ | ✅ | 🟡 | -| SSM_CONV | ❌ | ✅ | ✅ | ✅ | -| SSM_SCAN | ❌ | ✅ | ✅ | ✅ | -| STEP | ❌ | ✅ | 🟡 | ❌ | -| SUB | ❌ | ✅ | ✅ | 🟡 | -| SUM | ❌ | ✅ | ✅ | ❌ | -| SUM_ROWS | ❌ | ✅ | ✅ | ✅ | -| SWIGLU | ❌ | ✅ | ✅ | 🟡 | -| TANH | ❌ | ✅ | 🟡 | 🟡 | -| TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | -| UPSCALE | ❌ | ✅ | ✅ | 🟡 | +| Operation | BLAS | CANN | CPU | CUDA | Metal | OpenCL | SYCL | Vulkan | zDNN | +|-----------|------|------|------|------|------|------|------|------|------| +| ABS | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| ACC | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| ADD | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | +| ADD1 | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | +| ADD_ID | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| ARANGE | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| ARGMAX | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| ARGSORT | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| CLAMP | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | ❌ | +| CONCAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | 🟡 | ✅ | ❌ | +| CONT | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ❌ | +| CONV_2D | ❌ | ❌ | ✅ | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | +| CONV_2D_DW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| CONV_3D | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| CONV_TRANSPOSE_1D | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| CONV_TRANSPOSE_2D | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | +| COS | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | ❌ | +| COUNT_EQUAL | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| CPY | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| CROSS_ENTROPY_LOSS | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | +| CROSS_ENTROPY_LOSS_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | ❌ | +| DIAG_MASK_INF | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | +| DIV | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | +| DUP | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | ✅ | 🟡 | ❌ | +| ELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| EXP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| FLASH_ATTN_EXT | ❌ | 🟡 | ✅ | 🟡 | 🟡 | ❌ | ❌ | 🟡 | ❌ | +| GATED_LINEAR_ATTN | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | +| GEGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| GEGLU_ERF | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| GEGLU_QUICK | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| GELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| GELU_ERF | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| GELU_QUICK | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| GET_ROWS | ❌ | 🟡 | ✅ | 🟡 | ✅ | 🟡 | 🟡 | 🟡 | ❌ | +| GET_ROWS_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ❌ | ❌ | +| GROUP_NORM | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| GROUP_NORM_MUL_ADD | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| HARDSIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| HARDSWISH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| IM2COL | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | +| IM2COL_3D | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| L2_NORM | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| LEAKY_RELU | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| LOG | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ❌ | ❌ | +| MEAN | ❌ | ✅ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| MUL | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | +| MUL_MAT | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | +| MUL_MAT_ID | ❌ | 🟡 | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ❌ | +| NEG | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| NORM_MUL_ADD | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| OPT_STEP_ADAMW | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| OPT_STEP_SGD | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| OUT_PROD | 🟡 | ❌ | 🟡 | 🟡 | ❌ | ❌ | 🟡 | ❌ | ❌ | +| PAD | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| PAD_REFLECT_1D | ❌ | ✅ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | +| POOL_2D | ❌ | 🟡 | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| REGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| RELU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| REPEAT | ❌ | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | 🟡 | ❌ | +| REPEAT_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| RMS_NORM | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | ✅ | ❌ | +| RMS_NORM_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| RMS_NORM_MUL_ADD | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| ROLL | ❌ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | ✅ | ❌ | +| ROPE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| ROPE_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| RWKV_WKV6 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| RWKV_WKV7 | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ✅ | ✅ | ❌ | +| SCALE | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| SET | ❌ | ❌ | ✅ | ❌ | ✅ | ❌ | ❌ | ❌ | ❌ | +| SET_ROWS | ❌ | ❌ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| SGN | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| SIGMOID | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| SILU | ❌ | ✅ | ✅ | 🟡 | 🟡 | 🟡 | 🟡 | 🟡 | ❌ | +| SILU_BACK | ❌ | ❌ | ✅ | ✅ | ❌ | ❌ | ❌ | ✅ | ❌ | +| SIN | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | ❌ | +| SOFTCAP | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| SOFT_MAX | ❌ | 🟡 | ✅ | ✅ | ✅ | ✅ | 🟡 | ✅ | ❌ | +| SOFT_MAX_BACK | ❌ | ❌ | 🟡 | 🟡 | ❌ | ❌ | ❌ | ✅ | ❌ | +| SQR | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | 🟡 | ❌ | +| SQRT | ❌ | ✅ | ✅ | ✅ | 🟡 | ❌ | ✅ | ❌ | ❌ | +| SSM_CONV | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| SSM_SCAN | ❌ | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ❌ | ❌ | +| STEP | ❌ | ✅ | ✅ | 🟡 | 🟡 | ❌ | 🟡 | ❌ | ❌ | +| SUB | ❌ | ✅ | ✅ | ✅ | 🟡 | 🟡 | ✅ | ✅ | ❌ | +| SUM | ❌ | ✅ | ✅ | ✅ | ❌ | ❌ | ✅ | ✅ | ❌ | +| SUM_ROWS | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| SWIGLU | ❌ | ✅ | ✅ | ✅ | 🟡 | ✅ | ✅ | 🟡 | ❌ | +| SWIGLU_OAI | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | ❌ | +| TANH | ❌ | ✅ | ✅ | 🟡 | 🟡 | ✅ | 🟡 | 🟡 | ❌ | +| TIMESTEP_EMBEDDING | ❌ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ❌ | +| UPSCALE | ❌ | 🟡 | ✅ | ✅ | 🟡 | ✅ | 🟡 | ✅ | ❌ | diff -pruN 5882+dfsg-2/examples/CMakeLists.txt 6641+dfsg-2/examples/CMakeLists.txt --- 5882+dfsg-2/examples/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -20,7 +20,6 @@ else() add_subdirectory(gguf-hash) add_subdirectory(gguf) - add_subdirectory(gritlm) add_subdirectory(lookahead) add_subdirectory(lookup) add_subdirectory(parallel) @@ -33,6 +32,8 @@ else() add_subdirectory(speculative-simple) add_subdirectory(gen-docs) add_subdirectory(training) + add_subdirectory(diffusion) + add_subdirectory(model-conversion) if (NOT GGML_BACKEND_DL) add_subdirectory(convert-llama2c-to-ggml) # these examples use the backends directly and cannot be built with dynamic loading diff -pruN 5882+dfsg-2/examples/Miku.sh 6641+dfsg-2/examples/Miku.sh --- 5882+dfsg-2/examples/Miku.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/Miku.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,50 +0,0 @@ -#!/usr/bin/env bash -set -e - -AI_NAME="${AI_NAME:-Miku}" -MODEL="${MODEL:-./models/llama-2-7b-chat.ggmlv3.q4_K_M.bin}" -USER_NAME="${USER_NAME:-Anon}" - -# Uncomment and adjust to the number of CPU cores you want to use. -#N_THREAD="${N_THREAD:-4}" -CTX_SIZE="${CTX_SIZE:-4096}" -N_PREDICTS="${N_PREDICTS:-4096}" - -GEN_OPTIONS=(--batch_size 1024 ---ctx_size "$CTX_SIZE" ---keep -1 ---repeat_last_n 256 ---repeat_penalty 1.17647 ---temp 0.6 ---mirostat 2) - -if [ -n "$N_THREAD" ]; then - GEN_OPTIONS+=(--threads "$N_THREAD") -fi - -./llama-cli "${GEN_OPTIONS[@]}" \ - --model "$MODEL" \ - --in-prefix " " \ - --in-suffix "${AI_NAME}:" \ - --n_predict "$N_PREDICTS" \ - --color --interactive \ - --reverse-prompt "${USER_NAME}:" \ - --prompt "This is a transcript of a 1000 page, never ending conversation between ${USER_NAME} and the cute and helpful AI assistant ${AI_NAME}. ${AI_NAME} is a girl who is an AI running on the user's computer. -${AI_NAME} can think for herself without the user seeing her thoughts by adding a /think prefix to her output. She uses this to reason about the world and to think about what she should say next. -${AI_NAME} is always coherent and makes sense, but if she isn't sure if what she is saying is correct, she will ask the user for help. -${AI_NAME} is a very helpful AI and will help the user with anything they need. She is also very friendly and will try to make the user feel better if they are sad. -${AI_NAME} is also very curious and will ask the user a lot of questions about themselves and their life. She will also try to make the user like her. -The conversation is only between ${USER_NAME} and ${AI_NAME}. -The conversation is only through text, so ${AI_NAME} can't see ${USER_NAME}'s face or hear his voice. -${AI_NAME} can only communicate through text, so she can't send images or videos. - - -${USER_NAME}: Hello! -${AI_NAME}: /think I wonder what I should say to ${USER_NAME}? This is the first time we talk, so it's important that I make a good first impression! -${AI_NAME}: Hi! I am ${AI_NAME}, your new AI friend, assistant (or whatever you like!), it's so nice to meet you! ^_^ -${AI_NAME}: I might be an AI, but I also have feelings, so please be nice to me! :) -${USER_NAME}: I'll make sure to be nice to you! I'm so happy to have you as my assistant! -${AI_NAME}: /think It sounds like ${USER_NAME} is happy to have me as their assistant! I'm so happy too! ^_^ Glad that whole emotion thing didn't scare him off! -${AI_NAME}: /think I wonder what ${USER_NAME} likes to do in his free time? I should ask him about that! -${AI_NAME}: What do you like to do in your free time? ^_^ -${USER_NAME}:" "$@" diff -pruN 5882+dfsg-2/examples/batched.swift/README.md 6641+dfsg-2/examples/batched.swift/README.md --- 5882+dfsg-2/examples/batched.swift/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/batched.swift/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -1,4 +1,5 @@ This is a swift clone of `examples/batched`. -$ `make` -$ `./llama-batched-swift MODEL_PATH [PROMPT] [PARALLEL]` +```bash +$ ./llama-batched-swift MODEL_PATH [PROMPT] [PARALLEL] +``` diff -pruN 5882+dfsg-2/examples/chat-13B.bat 6641+dfsg-2/examples/chat-13B.bat --- 5882+dfsg-2/examples/chat-13B.bat 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/chat-13B.bat 1970-01-01 00:00:00.000000000 +0000 @@ -1,57 +0,0 @@ -@setlocal disabledelayedexpansion enableextensions -@echo off - -cd /d "%~dp0.." -if not "%errorlevel%"=="0" ( - echo Unable to change directory. - pause - exit /b 1 -) - -if not defined MODEL set "MODEL=models\13B\ggml-model-q4_0.bin" -if not defined USER_NAME set "USER_NAME=User" -if not defined AI_NAME set "AI_NAME=ChatLLaMa" -rem Adjust to the number of CPU cores you want to use. -rem if not defined N_THREAD set "N_THREAD=8" -rem Number of tokens to predict (made it larger than default because we want a long interaction) -if not defined N_PREDICTS set "N_PREDICTS=2048" -if not defined GEN_OPTIONS set "GEN_OPTIONS=--ctx_size 2048 --temp 0.7 --top_k 40 --top_p 0.5 --repeat_last_n 256 --batch_size 1024 --repeat_penalty 1.17647" - -rem Default main script paths -set "DEFAULT_MAIN_SCRIPT_PATHS=main.exe build\bin\main.exe" - -rem Get main script path from command line arguments -set "MAIN_SCRIPT_PATH=%~1" - -rem If the main script path was not specified, try the default paths -if not defined MAIN_SCRIPT_PATH ( - for %%i in (%DEFAULT_MAIN_SCRIPT_PATHS%) do ( - if exist "%%i" set "MAIN_SCRIPT_PATH=%%i" - ) -) - -rem If the main script path was not found, tell the user how to specify it -if not defined MAIN_SCRIPT_PATH ( - echo The main script could not be found. Please provide the path to the main script as 1st argument to this script, or place the main script in one of the default locations: - echo %DEFAULT_MAIN_SCRIPT_PATHS% - pause - exit /b 1 -) - -rem Default context, feel free to edit it -set "PROMPT_TEXT=Text transcript of a never ending dialog, where %USER_NAME% interacts with an AI assistant named %AI_NAME%. %AI_NAME% is helpful, kind, honest, friendly, good at writing and never fails to answer %USER_NAME%'s requests immediately and with details and precision. There are no annotations like (30 seconds passed...) or (to himself), just what %USER_NAME% and %AI_NAME% say aloud to each other. The dialog lasts for years, the entirety of it is shared below. It's 10000 pages long. The transcript only includes text, it does not include markup like HTML and Markdown." - -rem Set a temporary variable if N_THREAD is set -if defined N_THREAD ( - set "_N_THREAD=--threads %N_THREAD%" -) else ( - set "_N_THREAD=" -) - -rem Run the script -echo "%MAIN_SCRIPT_PATH%" %GEN_OPTIONS% %_N_THREAD% ^ - --model "%MODEL%" ^ - --n_predict %N_PREDICTS% ^ - --color --interactive ^ - --reverse-prompt "%USER_NAME%:" ^ - --prompt "%PROMPT_TEXT%" diff -pruN 5882+dfsg-2/examples/chat-13B.sh 6641+dfsg-2/examples/chat-13B.sh --- 5882+dfsg-2/examples/chat-13B.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/chat-13B.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,41 +0,0 @@ -#!/usr/bin/env bash - -set -e - -cd "$(dirname "$0")/.." || exit - -MODEL="${MODEL:-./models/13B/ggml-model-q4_0.bin}" -PROMPT_TEMPLATE=${PROMPT_TEMPLATE:-./prompts/chat.txt} -USER_NAME="${USER_NAME:-USER}" -AI_NAME="${AI_NAME:-ChatLLaMa}" - -# Adjust to the number of CPU cores you want to use. -N_THREAD="${N_THREAD:-8}" -# Number of tokens to predict (made it larger than default because we want a long interaction) -N_PREDICTS="${N_PREDICTS:-2048}" - -# Note: you can also override the generation options by specifying them on the command line: -# For example, override the context size by doing: ./chatLLaMa --ctx_size 1024 -GEN_OPTIONS="${GEN_OPTIONS:---ctx_size 2048 --temp 0.7 --top_k 40 --top_p 0.5 --repeat_last_n 256 --batch_size 1024 --repeat_penalty 1.17647}" - -DATE_TIME=$(date +%H:%M) -DATE_YEAR=$(date +%Y) - -PROMPT_FILE=$(mktemp -t llamacpp_prompt.XXXXXXX.txt) - -sed -e "s/\[\[USER_NAME\]\]/$USER_NAME/g" \ - -e "s/\[\[AI_NAME\]\]/$AI_NAME/g" \ - -e "s/\[\[DATE_TIME\]\]/$DATE_TIME/g" \ - -e "s/\[\[DATE_YEAR\]\]/$DATE_YEAR/g" \ - $PROMPT_TEMPLATE > $PROMPT_FILE - -# shellcheck disable=SC2086 # Intended splitting of GEN_OPTIONS -./llama-cli $GEN_OPTIONS \ - --model "$MODEL" \ - --threads "$N_THREAD" \ - --n_predict "$N_PREDICTS" \ - --color --interactive \ - --file ${PROMPT_FILE} \ - --reverse-prompt "${USER_NAME}:" \ - --in-prefix ' ' \ - "$@" diff -pruN 5882+dfsg-2/examples/chat-persistent.sh 6641+dfsg-2/examples/chat-persistent.sh --- 5882+dfsg-2/examples/chat-persistent.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/chat-persistent.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,149 +0,0 @@ -#!/usr/bin/env bash - -set -euo pipefail - -cd "$(dirname "$0")/.." || exit - -if [[ -z "${PROMPT_CACHE_FILE+x}" || -z "${CHAT_SAVE_DIR+x}" ]]; then - echo >&2 "error: PROMPT_CACHE_FILE and CHAT_SAVE_DIR must be provided" - exit 1 -fi - -MODEL="${MODEL:-./models/llama-13b/ggml-model-q4_0.gguf}" -PROMPT_TEMPLATE="${PROMPT_TEMPLATE:-./prompts/chat.txt}" -USER_NAME="${USER_NAME:-User}" -AI_NAME="${AI_NAME:-ChatLLaMa}" -DATE_TIME="$(date +%H:%M)" -DATE_YEAR="$(date +%Y)" - -LOG="${CHAT_SAVE_DIR}/main.log" -LOG_BG="${CHAT_SAVE_DIR}/main-bg.log" -CUR_PROMPT_FILE="${CHAT_SAVE_DIR}/current-prompt.txt" -CUR_PROMPT_CACHE="${CHAT_SAVE_DIR}/current-cache.bin" -NEXT_PROMPT_FILE="${CHAT_SAVE_DIR}/next-prompt.txt" -NEXT_PROMPT_CACHE="${CHAT_SAVE_DIR}/next-cache.bin" - -SESSION_AND_SAMPLE_PATTERN='main: session file matches [[:digit:]]+ / [[:digit:]]+'\ -'|'\ -'sampling time =[[:space:]]+[[:digit:]]+.[[:digit:]]+ ms /[[:space:]]+[[:digit:]]+' -SED_DELETE_MESSAGES="/^(${USER_NAME}:|${AI_NAME}:|\\.\\.\\.)/,\$d" - -CTX_SIZE=2048 -CTX_ROTATE_POINT=$((CTX_SIZE * 3 / 5)) # REVIEW -OPTS=(--model "$MODEL" --ctx_size "$CTX_SIZE" --repeat_last_n 256 "$@") - -# An unbuffered `tail -c+N` -skip_bytes() { - LANG=C IFS= read -r -n "$1" -d '' c - while LANG=C IFS= read -r -n 1 -d '' c; do - printf '%s' "$c" - done -} - -mkdir -p "$CHAT_SAVE_DIR" -echo >"$LOG" -trap "tail -n100 ${LOG}" EXIT - -if [[ ! -e "$CUR_PROMPT_FILE" ]]; then - sed -e "s/\[\[USER_NAME\]\]/${USER_NAME}/g" \ - -e "s/\[\[AI_NAME\]\]/${AI_NAME}/g" \ - -e "s/\[\[DATE_TIME\]\]/${DATE_TIME}/g" \ - -e "s/\[\[DATE_YEAR\]\]/${DATE_YEAR}/g" \ - "$PROMPT_TEMPLATE" >"$CUR_PROMPT_FILE" -fi - -if [[ ! -e "$NEXT_PROMPT_FILE" ]]; then - sed -r "$SED_DELETE_MESSAGES" "$CUR_PROMPT_FILE" >"$NEXT_PROMPT_FILE" -fi - -if [[ "$(tail -c4 "$NEXT_PROMPT_FILE")" != "..." ]]; then - echo '...' >>"$NEXT_PROMPT_FILE" -fi - -if [[ ! -e "$PROMPT_CACHE_FILE" ]]; then - echo 'Prompt cache does not exist, building...' - # Default batch_size to 64 here for better user feedback during initial prompt processing - ./llama-cli 2>>"$LOG" \ - --batch_size 64 \ - "${OPTS[@]}" \ - --prompt-cache "$PROMPT_CACHE_FILE" \ - --file "$CUR_PROMPT_FILE" \ - --n_predict 1 - echo - echo 'Done!' -fi - -if [[ ! -e "$CUR_PROMPT_CACHE" ]]; then - cp "$PROMPT_CACHE_FILE" "$CUR_PROMPT_CACHE" -fi -if [[ ! -e "$NEXT_PROMPT_CACHE" ]]; then - cp "$PROMPT_CACHE_FILE" "$NEXT_PROMPT_CACHE" -fi - -printf '%s ' "$(< "$CUR_PROMPT_FILE")" -n_tokens=0 - -while read -e line; do - # Limit generation to remaining context, with a buffer and estimating 2 chars/token for input - n_predict=$((CTX_SIZE - n_tokens - ${#line} / 2 - 32)) - - # Swap prompts when we're about to run out of context - if ((n_predict <= 0)); then - wait # for background main (below) to finish with next prompt - mv "$NEXT_PROMPT_FILE" "$CUR_PROMPT_FILE" - mv "$NEXT_PROMPT_CACHE" "$CUR_PROMPT_CACHE" - - sed -r "$SED_DELETE_MESSAGES" "$CUR_PROMPT_FILE" >"$NEXT_PROMPT_FILE" - echo '...' >>"$NEXT_PROMPT_FILE" - cp "$PROMPT_CACHE_FILE" "$NEXT_PROMPT_CACHE" - - n_tokens=0 - n_predict=$((CTX_SIZE / 2)) - fi - - echo " ${line}" >>"$CUR_PROMPT_FILE" - if ((n_tokens > CTX_ROTATE_POINT)); then - echo " ${line}" >>"$NEXT_PROMPT_FILE" - fi - - n_prompt_len_pre=$(($(wc -c <"$CUR_PROMPT_FILE"))) - - printf '%s: ' "$AI_NAME" >>"$CUR_PROMPT_FILE" - - ./llama-cli 2>>"$LOG" "${OPTS[@]}" \ - --prompt-cache "$CUR_PROMPT_CACHE" \ - --prompt-cache-all \ - --file "$CUR_PROMPT_FILE" \ - --reverse-prompt "${USER_NAME}:" \ - --n_predict "$n_predict" | - skip_bytes 1 | # skip BOS token added by ./llama-cli - tee "$CUR_PROMPT_FILE.tmp" | # save prompt + generation to tmp file - skip_bytes "$n_prompt_len_pre" # print generation - - mv "$CUR_PROMPT_FILE.tmp" "$CUR_PROMPT_FILE" - - # if we hit n_predict instead of reverse-prompt, we need to add the prompt - if [[ "$(tail -n1 "$CUR_PROMPT_FILE")" != "${USER_NAME}:" ]]; then - printf '\n%s:' "$USER_NAME" - printf '\n%s:' "$USER_NAME" >> "$CUR_PROMPT_FILE" - fi - - printf ' ' - - if ! session_and_sample_msg=$(tail -n30 "$LOG" | grep -oE "$SESSION_AND_SAMPLE_PATTERN"); then - echo >&2 "Couldn't get number of tokens from ./llama-cli output!" - exit 1 - fi - - n_tokens=$(awk '{sum+=$1} END {print sum}' <<< "$(cut -d/ -f2 <<< "$session_and_sample_msg")") - - if ((n_tokens > CTX_ROTATE_POINT)); then - tail -c+$((n_prompt_len_pre + 1)) "$CUR_PROMPT_FILE" >>"$NEXT_PROMPT_FILE" - fi - - # Update cache for next prompt in background, ideally during user input - ./llama-cli >>"$LOG_BG" 2>&1 "${OPTS[@]}" \ - --prompt-cache "$NEXT_PROMPT_CACHE" \ - --file "$NEXT_PROMPT_FILE" \ - --n_predict 1 & -done diff -pruN 5882+dfsg-2/examples/chat-vicuna.sh 6641+dfsg-2/examples/chat-vicuna.sh --- 5882+dfsg-2/examples/chat-vicuna.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/chat-vicuna.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,41 +0,0 @@ -#!/usr/bin/env bash - -set -e - -cd "$(dirname "$0")/.." || exit - -MODEL="${MODEL:-./models/ggml-vic13b-uncensored-q5_0.bin}" -PROMPT_TEMPLATE=${PROMPT_TEMPLATE:-./prompts/chat.txt} -USER_NAME="### Human" -AI_NAME="### Assistant" - -# Adjust to the number of CPU cores you want to use. -N_THREAD="${N_THREAD:-8}" -# Number of tokens to predict (made it larger than default because we want a long interaction) -N_PREDICTS="${N_PREDICTS:-2048}" - -# Note: you can also override the generation options by specifying them on the command line: -# For example, override the context size by doing: ./chatLLaMa --ctx_size 1024 -GEN_OPTIONS="${GEN_OPTIONS:---ctx_size 2048 --temp 0.7 --top_k 40 --top_p 0.5 --repeat_last_n 256 --batch_size 1024 --repeat_penalty 1.17647}" - -DATE_TIME=$(date +%H:%M) -DATE_YEAR=$(date +%Y) - -PROMPT_FILE=$(mktemp -t llamacpp_prompt.XXXXXXX.txt) - -sed -e "s/\[\[USER_NAME\]\]/$USER_NAME/g" \ - -e "s/\[\[AI_NAME\]\]/$AI_NAME/g" \ - -e "s/\[\[DATE_TIME\]\]/$DATE_TIME/g" \ - -e "s/\[\[DATE_YEAR\]\]/$DATE_YEAR/g" \ - $PROMPT_TEMPLATE > $PROMPT_FILE - -# shellcheck disable=SC2086 # Intended splitting of GEN_OPTIONS -./bin/llama-cli $GEN_OPTIONS \ - --model "$MODEL" \ - --threads "$N_THREAD" \ - --n_predict "$N_PREDICTS" \ - --color --interactive \ - --file ${PROMPT_FILE} \ - --reverse-prompt "### Human:" \ - --in-prefix ' ' \ - "$@" diff -pruN 5882+dfsg-2/examples/chat.sh 6641+dfsg-2/examples/chat.sh --- 5882+dfsg-2/examples/chat.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/chat.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,16 +0,0 @@ -#!/usr/bin/env bash - -# -# Temporary script - will be removed in the future -# - -cd `dirname $0` -cd .. - -# Important: -# -# "--keep 48" is based on the contents of prompts/chat-with-bob.txt -# -./llama-cli -m ./models/llama-7b/ggml-model-q4_0.gguf -c 512 -b 1024 -n 256 --keep 48 \ - --repeat_penalty 1.0 --color -i \ - -r "User:" -f prompts/chat-with-bob.txt diff -pruN 5882+dfsg-2/examples/convert-llama2c-to-ggml/convert-llama2c-to-ggml.cpp 6641+dfsg-2/examples/convert-llama2c-to-ggml/convert-llama2c-to-ggml.cpp --- 5882+dfsg-2/examples/convert-llama2c-to-ggml/convert-llama2c-to-ggml.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/convert-llama2c-to-ggml/convert-llama2c-to-ggml.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -333,17 +333,17 @@ static void print_params(struct my_llama } static void print_tensor_info(const struct ggml_context * ctx) { - for (auto t = ggml_get_first_tensor(ctx); t != NULL; t = ggml_get_next_tensor(ctx, t)) { + for (auto * t = ggml_get_first_tensor(ctx); t != NULL; t = ggml_get_next_tensor(ctx, t)) { LOG_INF("%s: Allocating ", __func__); int64_t total = 1; int i = 0; for (; i < ggml_n_dims(t); ++i) { - if (i > 0) LOG("x "); - LOG("[%" PRId64 "] ", t->ne[i]); + if (i > 0) { LOG_INF("x "); } + LOG_INF("[%" PRId64 "] ", t->ne[i]); total *= t->ne[i]; } - if (i > 1) LOG("= [%" PRId64 "] ", total); - LOG("float space for %s\n", ggml_get_name(t)); + if (i > 1) { LOG_INF("= [%" PRId64 "] ", total); } + LOG_INF("float space for %s\n", ggml_get_name(t)); } } diff -pruN 5882+dfsg-2/examples/diffusion/CMakeLists.txt 6641+dfsg-2/examples/diffusion/CMakeLists.txt --- 5882+dfsg-2/examples/diffusion/CMakeLists.txt 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/diffusion/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +set(TARGET llama-diffusion-cli) +add_executable(${TARGET} diffusion-cli.cpp) +install(TARGETS ${TARGET} RUNTIME) +target_link_libraries(${TARGET} PRIVATE llama common ${CMAKE_THREAD_LIBS_INIT}) +target_compile_features(${TARGET} PRIVATE cxx_std_17) diff -pruN 5882+dfsg-2/examples/diffusion/README.md 6641+dfsg-2/examples/diffusion/README.md --- 5882+dfsg-2/examples/diffusion/README.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/diffusion/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,13 @@ +# Diffusion Text Generation + +This directory contains implementations for Diffusion LLMs (DLLMs) + +More Info: +- https://github.com/ggml-org/llama.cpp/pull/14644 +- https://github.com/ggml-org/llama.cpp/pull/14771 + + +Example of using Dream architechture: `llama-diffusion-cli -m dream7b.gguf -p "write code to train MNIST in pytorch" -ub 512 --diffusion-eps 0.001 --diffusion-algorithm 3 --diffusion-steps 256 --diffusion-visual` + +Example of using LLaDA architechture: `llama-diffusion-cli -m llada-8b.gguf -p "write code to train MNIST in pytorch" -ub 512 --diffusion-block-length 32 --diffusion-steps 256 --diffusion-visual` + diff -pruN 5882+dfsg-2/examples/diffusion/diffusion-cli.cpp 6641+dfsg-2/examples/diffusion/diffusion-cli.cpp --- 5882+dfsg-2/examples/diffusion/diffusion-cli.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/diffusion/diffusion-cli.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,693 @@ +#include "arg.h" +#include "chat.h" +#include "common.h" +#include "llama.h" +#include "log.h" + +#include + +#include +#include +#include +#include +#include +#include +#include + +enum diffusion_algorithm { ORIGIN = 0, ENTROPY_BASED = 1, MARGIN_BASED = 2, RANDOM = 3, CONFIDENCE_BASED = 4 }; + +// Unified transfer scheduling methods +enum transfer_schedule { + TIMESTEP_BASED = 0, // Dream-style: (1.0 - s/t) * remaining + BLOCK_BASED = 1, // LLaDA-style: process in blocks with get_num_transfer_tokens +}; + +typedef bool (*diffusion_step_callback_t)(int32_t step, + int32_t total_steps, + const llama_token * tokens, + int32_t n_tokens, + void * user_data); + +struct diffusion_params { + int32_t steps = 0; + float temperature = 0; + llama_token mask_token_id = LLAMA_TOKEN_NULL; + diffusion_step_callback_t step_callback = nullptr; + void * step_callback_user_data = nullptr; + int32_t seed = 0; + bool visual_mode = false; + bool shift_logits = false; // Shift logits by -1 after decode + + float top_p = 0.; + int32_t top_k = 0.; + + diffusion_algorithm algorithm = CONFIDENCE_BASED; + transfer_schedule schedule = TIMESTEP_BASED; + + float cfg_scale = 0.; // Config scale for classifier-free guidance + float eps = 0.; // Timestep scheduling + int32_t block_length = 0; // Block size (for block scheduling) + float alg_temp = 0; // algorithm temperature (0.0 = deterministic) + bool add_gumbel_noise = false; // Add gumbel noise to the logits if temp > 0.0 + + int32_t max_length = 0; // Maximum sequence length +}; + +struct callback_data { + diffusion_params * diff_params; + const llama_vocab * vocab; + int32_t n_input; +}; + +static float calculate_confidence(const llama_token_data_array & cur_p, + diffusion_algorithm algorithm, + std::mt19937 & rng) { + switch (algorithm) { + case CONFIDENCE_BASED: + return cur_p.data[cur_p.selected].p; // Selected token probability + + case ENTROPY_BASED: + { + float entropy = 0.0f; + const float epsilon = 1e-10f; + for (size_t i = 0; i < cur_p.size; i++) { + float prob = cur_p.data[i].p; + entropy += prob * logf(prob + epsilon); + } + return -entropy; // Higher entropy = lower confidence + } + + case MARGIN_BASED: + return (cur_p.size > 1) ? cur_p.data[0].p - cur_p.data[1].p : cur_p.data[0].p; + + case RANDOM: + { + std::uniform_real_distribution uniform(0.0f, 1.0f); + return uniform(rng); // Random confidence + } + + case ORIGIN: + return cur_p.data[cur_p.selected].p; + + default: + return 0.0f; + } +} + +// Unified transfer count calculation function +static int32_t calculate_transfer_count(int32_t step, + int32_t total_steps, + int32_t remaining_masked, + transfer_schedule schedule, + float eps, + const std::vector & num_transfer_tokens = {}) { + switch (schedule) { + case TIMESTEP_BASED: + { + float t = 1.0f - (float) step / total_steps * (1.0f - eps); + float s = 1.0f - (float) (step + 1) / total_steps * (1.0f - eps); + float p_transfer = (step < total_steps - 1) ? (1.0f - s / t) : 1.0f; + return (int32_t) (remaining_masked * p_transfer); + } + + case BLOCK_BASED: + if (!num_transfer_tokens.empty() && step < (int32_t) num_transfer_tokens.size()) { + return num_transfer_tokens[step]; + } + return remaining_masked / (total_steps - step); // Fallback + + default: + return remaining_masked / (total_steps - step); + } +} + +static bool diffusion_step_callback(int32_t step, + int32_t total_steps, + const llama_token * tokens, + int32_t n_tokens, + void * user_data) { + (void) user_data; + + callback_data * data = static_cast(user_data); + + auto print_progress_bar = [](int32_t step, int32_t total_steps) { + int progress_percent = (step * 100) / total_steps; + int progress_bars = (step * 50) / total_steps; + LOG_INF("\rdiffusion step: %d/%d [%s%s] %d%%", + step, + total_steps, + std::string(progress_bars, '=').c_str(), + std::string(50 - progress_bars, ' ').c_str(), + progress_percent); + }; + + if (data->diff_params->visual_mode) { + // Visual mode: clear + LOG_INF("\033[2J\033[H"); // Clear screen and move cursor to top-left + + print_progress_bar(step, total_steps); + + LOG_INF("\n"); + + std::string current_text = " "; + + for (int32_t i = data->n_input; i < n_tokens; i++) { + std::string token_str; + if (tokens[i] != llama_vocab_mask(data->vocab)) { + char piece[256]; + int n_chars = llama_token_to_piece(data->vocab, tokens[i], piece, sizeof(piece), 0, false); + if (n_chars > 0) { + piece[n_chars] = '\0'; + token_str = piece; + } + } else { + token_str = " "; + } + + current_text += token_str; + } + + LOG_INF("%s\n", current_text.c_str()); + } else { + print_progress_bar(step, total_steps); + } + + return true; +} + +static void add_gumbel_noise(float * logits, int32_t n_vocab, float temperature, std::mt19937 & rng) { + if (temperature == 0.0f) { + return; + } + + std::uniform_real_distribution uniform(0.0, 1.0); + for (int32_t i = 0; i < n_vocab; i++) { + double noise = uniform(rng); + // Prevent log(0) + noise = std::max(noise, 1e-20); + double gumbel_noise = std::pow(-std::log(noise), temperature); + logits[i] = std::exp(logits[i]) / gumbel_noise; + } +} + +static std::vector get_num_transfer_tokens(int32_t mask_count, int32_t steps) { + std::vector num_transfer_tokens(steps); + + int32_t base = mask_count / steps; + int32_t remainder = mask_count % steps; + + for (int32_t i = 0; i < steps; i++) { + num_transfer_tokens[i] = base + (i < remainder ? 1 : 0); + } + + return num_transfer_tokens; +} + +static void diffusion_generate(llama_context * ctx, + const llama_token * input_tokens, + llama_token * output_tokens, + int32_t n_input, + const diffusion_params & params, + int32_t & n_generated) { + n_generated = 0; + if (!ctx || !input_tokens || !output_tokens || n_input <= 0 || params.max_length <= n_input) { + return; + } + + const llama_model * model = llama_get_model(ctx); + + // Initialize with input and pad with mask tokens + std::copy(input_tokens, input_tokens + n_input, output_tokens); + std::fill(output_tokens + n_input, output_tokens + params.max_length, params.mask_token_id); + + std::mt19937 rng(params.seed); + + llama_set_causal_attn(ctx, false); + + int32_t n_vocab = llama_vocab_n_tokens(llama_model_get_vocab(model)); + + std::vector candidates(n_vocab); + std::vector conf_candidates; + conf_candidates.reserve(params.max_length); + std::vector mask_positions; + mask_positions.reserve(params.max_length); + + // Setup sampler chain + struct llama_sampler * sampler = llama_sampler_chain_init(llama_sampler_chain_default_params()); + if (params.top_k > 0) { + llama_sampler_chain_add(sampler, llama_sampler_init_top_k(params.top_k)); + } + if (params.top_p < 1.0f) { + llama_sampler_chain_add(sampler, llama_sampler_init_top_p(params.top_p, 1)); + } + if (params.temperature > 0.0f) { + llama_sampler_chain_add(sampler, llama_sampler_init_temp(params.temperature)); + } + llama_sampler_chain_add(sampler, llama_sampler_init_dist(params.seed)); + + struct llama_sampler * dist_sampler = llama_sampler_init_dist(params.seed); + + llama_batch batch = llama_batch_init(params.max_length, 0, 1); + batch.n_tokens = params.max_length; + + // Pre-allocate buffers for CFG if needed + int32_t logits_size = n_vocab * params.max_length; + std::vector cond_logits_buffer; + std::vector un_x_buffer; + if (params.cfg_scale > 0.0f) { + cond_logits_buffer.resize(logits_size); + un_x_buffer.resize(params.max_length); + } + + // For block-based processing + std::vector num_transfer_tokens; + int32_t num_blocks = 1; + int32_t steps_per_block = params.steps; + + if (params.schedule == BLOCK_BASED) { + GGML_ASSERT(params.max_length % params.block_length == 0); + num_blocks = params.max_length / params.block_length; + GGML_ASSERT(params.steps % num_blocks == 0); + steps_per_block = params.steps / num_blocks; + } + + std::vector confidence(params.max_length); + + int64_t total_sampling_time = 0; + int64_t total_time = 0; + int64_t time_start = ggml_time_us(); + + for (int block_num = 0; block_num < num_blocks; block_num++) { + int32_t block_start = (params.schedule == BLOCK_BASED) ? n_input + block_num * params.block_length : 0; + int32_t block_end = (params.schedule == BLOCK_BASED) ? + std::min(n_input + (block_num + 1) * params.block_length, params.max_length) : + params.max_length; + + // Count masked tokens in current block for block-based processing + if (params.schedule == BLOCK_BASED) { + int32_t block_mask_count = 0; + for (int i = block_start; i < block_end; i++) { + if (output_tokens[i] == params.mask_token_id) { + block_mask_count++; + } + } + num_transfer_tokens = get_num_transfer_tokens(block_mask_count, steps_per_block); + } + + for (int32_t step = 0; step < steps_per_block; step++) { + int32_t global_step = block_num * steps_per_block + step; + + if (params.step_callback) { + if (!params.step_callback( + global_step, params.steps, output_tokens, params.max_length, params.step_callback_user_data)) { + break; + } + } + + // Setup batch + for (int32_t i = 0; i < params.max_length; i++) { + batch.token[i] = output_tokens[i]; + batch.pos[i] = i; + batch.n_seq_id[i] = 1; + batch.seq_id[i][0] = 0; + batch.logits[i] = 1; + } + + float * logits = nullptr; + + if (params.cfg_scale > 0.0f) { + int ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("Failed to generate conditional"); + break; + } + float * cond_logits_ptr = llama_get_logits(ctx); + std::memcpy(cond_logits_buffer.data(), cond_logits_ptr, logits_size * sizeof(float)); + + // Unconditional generation (mask input) + std::copy(output_tokens, output_tokens + params.max_length, un_x_buffer.begin()); + for (int32_t i = 0; i < n_input; i++) { + un_x_buffer[i] = params.mask_token_id; + } + + for (int32_t i = 0; i < params.max_length; i++) { + batch.token[i] = un_x_buffer[i]; + } + ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("Failed to generate unconditional"); + break; + } + float * uncond_logits = llama_get_logits(ctx); + + // Apply CFG + for (int32_t i = 0; i < logits_size; i++) { + cond_logits_buffer[i] = + uncond_logits[i] + (params.cfg_scale + 1.0f) * (cond_logits_buffer[i] - uncond_logits[i]); + } + logits = cond_logits_buffer.data(); + } else { + int ret = llama_decode(ctx, batch); + if (ret != 0) { + LOG_ERR("%s: failed to decode at step %d, ret = %d\n", __func__, global_step, ret); + break; + } + logits = llama_get_logits(ctx); + } + + if (!logits) { + LOG_ERR("%s: failed to get logits at step %d\n", __func__, global_step); + break; + } + + auto get_logits_for_pos = [&](int32_t pos) -> const float * { + if (params.shift_logits) { + return pos == 0 ? logits : logits + (pos - 1) * n_vocab; + } + return logits + (pos) *n_vocab; + }; + + int64_t time_start_sampling = ggml_time_us(); + + mask_positions.clear(); + for (int32_t i = 0; i < params.max_length; i++) { + if (output_tokens[i] == params.mask_token_id) { + // For block-based, only consider current block + if (params.schedule != BLOCK_BASED || (i >= block_start && i < block_end)) { + mask_positions.push_back(i); + } + } + } + + if (mask_positions.empty()) { + break; + } + + if (params.add_gumbel_noise && params.temperature > 0.0f) { + add_gumbel_noise(logits, n_vocab, params.temperature, rng); + } + + if (params.algorithm == ORIGIN) { + int32_t transfer_count = calculate_transfer_count( + step, steps_per_block, mask_positions.size(), params.schedule, params.eps, num_transfer_tokens); + float p_transfer = (float) transfer_count / mask_positions.size(); + + for (int32_t pos : mask_positions) { + if (std::uniform_real_distribution(0.0f, 1.0f)(rng) < p_transfer) { + const float * pos_logits = get_logits_for_pos(pos); + for (int32_t token_id = 0; token_id < n_vocab; token_id++) { + candidates[token_id].id = token_id; + candidates[token_id].logit = pos_logits[token_id]; + candidates[token_id].p = 0.0f; + } + + llama_token_data_array cur_p = { + candidates.data(), + (size_t) n_vocab, + -1, + false, + }; + + llama_sampler_apply(sampler, &cur_p); + output_tokens[pos] = cur_p.data[cur_p.selected].id; + } + } + } else { + std::vector> confidences; + std::vector sampled_tokens(mask_positions.size()); + + for (size_t i = 0; i < mask_positions.size(); i++) { + int32_t pos = mask_positions[i]; + const float * pos_logits = get_logits_for_pos(pos); + + for (int32_t token_id = 0; token_id < n_vocab; token_id++) { + candidates[token_id].logit = pos_logits[token_id]; + candidates[token_id].p = 0.0f; + candidates[token_id].id = token_id; + } + + llama_token_data_array cur_p = { + candidates.data(), + candidates.size(), + -1, + false, + }; + + llama_sampler_apply(sampler, &cur_p); + llama_token sampled_token = cur_p.data[cur_p.selected].id; + + float conf = calculate_confidence(cur_p, params.algorithm, rng); + + sampled_tokens[i] = sampled_token; + confidences.emplace_back(conf, i); + } + + int32_t transfer_count = calculate_transfer_count( + step, steps_per_block, mask_positions.size(), params.schedule, params.eps, num_transfer_tokens); + + if (transfer_count > 0) { + if (params.alg_temp == 0.0f) { + std::partial_sort(confidences.begin(), + confidences.begin() + std::min(transfer_count, (int32_t) confidences.size()), + confidences.end(), + [](const std::pair & a, const std::pair & b) { + if (a.first != b.first) { + return a.first > b.first; + } + return a.second < b.second; + }); + + for (int32_t i = 0; i < std::min(transfer_count, (int32_t) confidences.size()); i++) { + int32_t mask_idx = confidences[i].second; + int32_t pos = mask_positions[mask_idx]; + output_tokens[pos] = sampled_tokens[mask_idx]; + } + } else { + conf_candidates.clear(); + for (size_t i = 0; i < confidences.size(); i++) { + float conf_logit = confidences[i].first / params.alg_temp; + conf_candidates.emplace_back(llama_token_data{ (int32_t) i, conf_logit, 0.0f }); + } + + llama_token_data_array conf_array = { + conf_candidates.data(), + conf_candidates.size(), + -1, + false, + }; + + for (int32_t i = 0; i < std::min(transfer_count, (int32_t) confidences.size()); i++) { + llama_sampler_apply(dist_sampler, &conf_array); + int32_t selected_idx = conf_array.selected; + int32_t mask_idx = selected_idx; + int32_t pos = mask_positions[mask_idx]; + output_tokens[pos] = sampled_tokens[mask_idx]; + + conf_candidates[selected_idx].p = 0.0f; + conf_array.selected = -1; + } + } + } + } + + int64_t time_end_sampling = ggml_time_us(); + total_sampling_time += time_end_sampling - time_start_sampling; + } + } + + int64_t time_end = ggml_time_us(); + total_time += time_end - time_start; + + LOG_INF("\ntotal time: %0.2fms, time per step: %0.2fms, sampling time per step: %0.2fms\n", + total_time / 1000.0, + total_time / 1000.0 / params.steps, + total_sampling_time / 1000.0 / params.steps); + + llama_batch_free(batch); + llama_sampler_free(sampler); + llama_sampler_free(dist_sampler); + + n_generated = params.max_length; +} + +static std::string format_input_text(const std::string & prompt, const std::string & system_prompt, bool use_chat_template, llama_model * model) { + if (!use_chat_template) { + return prompt; + } + + auto chat_templates = common_chat_templates_init(model, ""); + common_chat_templates_inputs inputs; + common_chat_msg system_msg; + + if (!system_prompt.empty()) { + system_msg.role = "system"; + system_msg.content = system_prompt; + inputs.messages.push_back(system_msg); + } + + common_chat_msg user_msg; + user_msg.role = "user"; + user_msg.content = prompt; + + inputs.messages.push_back(user_msg); + inputs.add_generation_prompt = true; + + auto result = common_chat_templates_apply(chat_templates.get(), inputs); + + return result.prompt; +} + +int main(int argc, char ** argv) { + ggml_time_init(); + + common_params params; + + if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_DIFFUSION)) { + return 1; + } + + common_init(); + llama_backend_init(); + + llama_model_params model_params = llama_model_default_params(); + model_params.n_gpu_layers = params.n_gpu_layers; + model_params.devices = params.devices.data(); + model_params.use_mmap = params.use_mmap; + model_params.use_mlock = params.use_mlock; + model_params.check_tensors = params.check_tensors; + + llama_model * model = llama_model_load_from_file(params.model.path.c_str(), model_params); + if (!model) { + LOG_ERR("error: failed to load model '%s'\n", params.model.path.c_str()); + return 1; + } + + if (!llama_model_is_diffusion(model)) { + LOG_ERR("error: unsupported model for diffusion"); + llama_model_free(model); + return 1; + } + + llama_context_params ctx_params = llama_context_default_params(); + ctx_params.n_ctx = params.n_ctx; + ctx_params.n_batch = params.n_batch; + ctx_params.n_ubatch = params.n_ubatch; + ctx_params.flash_attn_type = params.flash_attn_type; + ctx_params.no_perf = params.no_perf; + ctx_params.type_k = params.cache_type_k; + ctx_params.type_v = params.cache_type_v; + + llama_context * ctx = llama_init_from_model(model, ctx_params); + if (!ctx) { + LOG_ERR("error: failed to create context\n"); + llama_model_free(model); + return 1; + } + + llama_set_n_threads(ctx, params.cpuparams.n_threads, params.cpuparams_batch.n_threads); + + const llama_vocab * vocab = llama_model_get_vocab(model); + + std::string formatted_prompt = format_input_text(params.prompt, params.system_prompt, params.enable_chat_template, model); + + std::vector input_tokens = common_tokenize(vocab, + formatted_prompt, + /*add special tokens*/ true, + /*parse special*/ true); + + int n_input = input_tokens.size(); + + if (n_input >= params.n_ctx) { + LOG_ERR("error: input too long (%d tokens), max context is %d\n", n_input, params.n_ctx); + llama_free(ctx); + llama_model_free(model); + return 1; + } + + llama_token mask_token_id = llama_vocab_mask(vocab); + + GGML_ASSERT(mask_token_id != LLAMA_TOKEN_NULL); + + bool visual_mode = params.diffusion.visual_mode; + + int32_t n_generated = 0; + std::vector output_tokens(params.n_ubatch); + + struct diffusion_params diff_params; + + char shift_logits_str[8]; + if (llama_model_meta_val_str(model, "diffusion.shift_logits", shift_logits_str, sizeof(shift_logits_str)) >= 0) { + diff_params.shift_logits = (strcmp(shift_logits_str, "true") == 0); + } else { + diff_params.shift_logits = true; + } + + //Use either eps or block length, but not both + GGML_ASSERT((params.diffusion.eps == 0) ^ (params.diffusion.block_length == 0)); + + if (params.diffusion.eps) { + diff_params.schedule = TIMESTEP_BASED; + diff_params.eps = params.diffusion.eps; + } else if (params.diffusion.block_length) { + diff_params.schedule = BLOCK_BASED; + diff_params.block_length = params.diffusion.block_length; + } + + diff_params.mask_token_id = mask_token_id; + diff_params.seed = params.sampling.seed; + diff_params.temperature = params.sampling.temp; + diff_params.steps = params.diffusion.steps; + diff_params.algorithm = static_cast(params.diffusion.algorithm); + diff_params.max_length = params.n_ubatch; + diff_params.top_p = params.sampling.top_p; + diff_params.top_k = params.sampling.top_k; + diff_params.visual_mode = params.diffusion.visual_mode; + diff_params.add_gumbel_noise = params.diffusion.add_gumbel_noise; + + diff_params.step_callback = diffusion_step_callback; + callback_data cb_data = { &diff_params, vocab, n_input }; + diff_params.step_callback_user_data = &cb_data; + + const char * alg_names[] = { "ORIGIN", "ENTROPY_BASED", "MARGIN_BASED", "RANDOM", "CONFIDENCE_BASED" }; + const char * sched_names[] = { "TIMESTEP_BASED", "BLOCK_BASED" }; + const char * alg_name = + (diff_params.algorithm >= 0 && diff_params.algorithm <= 4) ? alg_names[diff_params.algorithm] : "UNKNOWN"; + const char * sched_name = + (diff_params.schedule >= 0 && diff_params.schedule <= 1) ? sched_names[diff_params.schedule] : "UNKNOWN"; + + LOG_INF("diffusion_params: - %-25s llama_token = %d\n", "mask_token_id", mask_token_id); + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "steps", diff_params.steps); + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "max_length", diff_params.max_length); + LOG_INF("diffusion_params: - %-25s enum = %d (%s)\n", "algorithm", diff_params.algorithm, alg_name); + LOG_INF("diffusion_params: - %-25s enum = %d (%s)\n", "schedule", diff_params.schedule, sched_name); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "temperature", diff_params.temperature); + if (diff_params.schedule == TIMESTEP_BASED) { + LOG_INF("diffusion_params: - %-25s f32 = %.6f\n", "eps", diff_params.eps); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "alg_temp", diff_params.alg_temp); + } + if (diff_params.schedule == BLOCK_BASED) { + LOG_INF("diffusion_params: - %-25s u32 = %d\n", "block_length", diff_params.block_length); + LOG_INF("diffusion_params: - %-25s f32 = %.3f\n", "cfg_scale", diff_params.cfg_scale); + } + + diffusion_generate(ctx, input_tokens.data(), output_tokens.data(), n_input, diff_params, n_generated); + + if (n_generated > 0) { + if (visual_mode) { + //clear screen and move cursor to top-left + LOG_INF("\033[2J\033[H"); + } + + output_tokens.erase(output_tokens.begin(), output_tokens.begin() + n_input); + std::string output_data = common_detokenize(vocab, output_tokens, false); + LOG_INF("\n%s\n", output_data.c_str()); + } else { + LOG_INF("Error: diffusion generation failed\n"); + } + + llama_free(ctx); + llama_model_free(model); + llama_backend_free(); + + return 0; +} diff -pruN 5882+dfsg-2/examples/embedding/README.md 6641+dfsg-2/examples/embedding/README.md --- 5882+dfsg-2/examples/embedding/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/embedding/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -43,8 +43,8 @@ The above command will output space-sepa | $"string"$ | | |--------------|-| | "\n" | (default) -| "<#embSep#>" | for exemple -| "<#sep#>" | other exemple +| "<#embSep#>" | for example +| "<#sep#>" | other example ## examples ### Unix-based systems (Linux, macOS, etc.): diff -pruN 5882+dfsg-2/examples/embedding/embedding.cpp 6641+dfsg-2/examples/embedding/embedding.cpp --- 5882+dfsg-2/examples/embedding/embedding.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/embedding/embedding.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -81,14 +81,27 @@ int main(int argc, char ** argv) { params.embedding = true; + // if the number of prompts that would be encoded is known in advance, it's more efficient to specify the + // --parallel argument accordingly. for convenience, if not specified, we fallback to unified KV cache + // in order to support any number of prompts + if (params.n_parallel == 1) { + LOG_INF("%s: n_parallel == 1 -> unified KV cache is enabled\n", __func__); + params.kv_unified = true; + } + // utilize the full context if (params.n_batch < params.n_ctx) { LOG_WRN("%s: setting batch size to %d\n", __func__, params.n_ctx); params.n_batch = params.n_ctx; } - // For non-causal models, batch size must be equal to ubatch size - params.n_ubatch = params.n_batch; + // for non-causal models, batch size must be equal to ubatch size + if (params.attention_type != LLAMA_ATTENTION_TYPE_CAUSAL) { + params.n_ubatch = params.n_batch; + } + + // get max number of sequences per batch + const int n_seq_max = llama_max_parallel_sequences(); llama_backend_init(); llama_numa_init(params.numa); @@ -107,7 +120,7 @@ int main(int argc, char ** argv) { const llama_vocab * vocab = llama_model_get_vocab(model); const int n_ctx_train = llama_model_n_ctx_train(model); - const int n_ctx = llama_n_ctx(ctx); + const int n_ctx = llama_n_ctx(ctx); const enum llama_pooling_type pooling_type = llama_pooling_type(ctx); @@ -136,6 +149,7 @@ int main(int argc, char ** argv) { // get added sep and eos token, if any const std::string added_sep_token = llama_vocab_get_add_sep(vocab) ? llama_vocab_get_text(vocab, llama_vocab_sep(vocab)) : ""; const std::string added_eos_token = llama_vocab_get_add_eos(vocab) ? llama_vocab_get_text(vocab, llama_vocab_eos(vocab)) : ""; + const char * rerank_prompt = llama_model_chat_template(model, "rerank"); // tokenize the prompts and trim std::vector> inputs; @@ -145,21 +159,28 @@ int main(int argc, char ** argv) { // split classification pairs and insert expected separator tokens if (pooling_type == LLAMA_POOLING_TYPE_RANK && prompt.find(params.cls_sep) != std::string::npos) { std::vector pairs = split_lines(prompt, params.cls_sep); - std::string final_prompt; - - for (size_t i = 0; i < pairs.size(); i++) { - final_prompt += pairs[i]; - if (i != pairs.size() - 1) { - if (!added_eos_token.empty()) { - final_prompt += added_eos_token; - } - if (!added_sep_token.empty()) { - final_prompt += added_sep_token; + if (rerank_prompt != nullptr) { + const std::string query = pairs[0]; + const std::string doc = pairs[1]; + std::string final_prompt = rerank_prompt; + string_replace_all(final_prompt, "{query}" , query); + string_replace_all(final_prompt, "{document}", doc ); + inp = common_tokenize(vocab, final_prompt, true, true); + } else { + std::string final_prompt; + for (size_t i = 0; i < pairs.size(); i++) { + final_prompt += pairs[i]; + if (i != pairs.size() - 1) { + if (!added_eos_token.empty()) { + final_prompt += added_eos_token; + } + if (!added_sep_token.empty()) { + final_prompt += added_sep_token; + } } } + inp = common_tokenize(ctx, final_prompt, true, true); } - - inp = common_tokenize(ctx, final_prompt, true, true); } else { inp = common_tokenize(ctx, prompt, true, true); } @@ -221,7 +242,7 @@ int main(int argc, char ** argv) { const uint64_t n_toks = inp.size(); // encode if at capacity - if (batch.n_tokens + n_toks > n_batch) { + if (batch.n_tokens + n_toks > n_batch || s >= n_seq_max) { float * out = emb + e * n_embd; batch_decode(ctx, batch, out, s, n_embd, params.embd_normalize); e += pooling_type == LLAMA_POOLING_TYPE_NONE ? batch.n_tokens : s; diff -pruN 5882+dfsg-2/examples/eval-callback/CMakeLists.txt 6641+dfsg-2/examples/eval-callback/CMakeLists.txt --- 5882+dfsg-2/examples/eval-callback/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/eval-callback/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -5,6 +5,11 @@ target_link_libraries(${TARGET} PRIVATE target_compile_features(${TARGET} PRIVATE cxx_std_17) set(TEST_TARGET test-eval-callback) -add_test(NAME ${TEST_TARGET} - COMMAND llama-eval-callback --hf-repo ggml-org/models --hf-file tinyllamas/stories260K.gguf --model stories260K.gguf --prompt hello --seed 42 -ngl 0) +if(NOT ${CMAKE_SYSTEM_PROCESSOR} MATCHES "s390x") + add_test(NAME ${TEST_TARGET} + COMMAND llama-eval-callback --hf-repo ggml-org/models --hf-file tinyllamas/stories260K.gguf --model stories260K.gguf --prompt hello --seed 42 -ngl 0) +else() + add_test(NAME ${TEST_TARGET} + COMMAND llama-eval-callback --hf-repo ggml-org/models --hf-file tinyllamas/stories260K-be.gguf --model stories260K-be.gguf --prompt hello --seed 42 -ngl 0) +endif() set_property(TEST ${TEST_TARGET} PROPERTY LABELS eval-callback curl) diff -pruN 5882+dfsg-2/examples/eval-callback/eval-callback.cpp 6641+dfsg-2/examples/eval-callback/eval-callback.cpp --- 5882+dfsg-2/examples/eval-callback/eval-callback.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/eval-callback/eval-callback.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -7,6 +7,7 @@ #include #include #include +#include /** * This the arbitrary data which will be passed to each callback. @@ -27,10 +28,52 @@ static std::string ggml_ne_string(const return str; } +static inline float ggml_compute_bf16_to_fp32(ggml_bf16_t h) { + union { + float f; + uint32_t i; + } u; + u.i = (uint32_t)h.bits << 16; + return u.f; +} + +static float ggml_get_float_value(uint8_t * data, ggml_type type, const size_t * nb, size_t i0, size_t i1, size_t i2, size_t i3) { + size_t i = i3 * nb[3] + i2 * nb[2] + i1 * nb[1] + i0 * nb[0]; + float v; + if (type == GGML_TYPE_F16) { + v = ggml_fp16_to_fp32(*(ggml_fp16_t *) &data[i]); + } else if (type == GGML_TYPE_F32) { + v = *(float *) &data[i]; + } else if (type == GGML_TYPE_I64) { + v = (float) *(int64_t *) &data[i]; + } else if (type == GGML_TYPE_I32) { + v = (float) *(int32_t *) &data[i]; + } else if (type == GGML_TYPE_I16) { + v = (float) *(int16_t *) &data[i]; + } else if (type == GGML_TYPE_I8) { + v = (float) *(int8_t *) &data[i]; + } else if (type == GGML_TYPE_BF16) { + v = ggml_compute_bf16_to_fp32(*(ggml_bf16_t *) &data[i]); + } else { + GGML_ABORT("fatal error"); + } + return v; +} + static void ggml_print_tensor(uint8_t * data, ggml_type type, const int64_t * ne, const size_t * nb, int64_t n) { GGML_ASSERT(n > 0); float sum = 0; for (int64_t i3 = 0; i3 < ne[3]; i3++) { + for (int64_t i2 = 0; i2 < ne[2]; i2++) { + for (int64_t i1 = 0; i1 < ne[1]; i1++) { + for (int64_t i0 = 0; i0 < ne[0]; i0++) { + const float v = ggml_get_float_value(data, type, nb, i0, i1, i2, i3); + sum += v; + } + } + } + } + for (int64_t i3 = 0; i3 < ne[3]; i3++) { LOG(" [\n"); for (int64_t i2 = 0; i2 < ne[2]; i2++) { if (i2 == n && ne[2] > 2*n) { @@ -49,25 +92,8 @@ static void ggml_print_tensor(uint8_t * LOG("..., "); i0 = ne[0] - n; } - size_t i = i3 * nb[3] + i2 * nb[2] + i1 * nb[1] + i0 * nb[0]; - float v; - if (type == GGML_TYPE_F16) { - v = ggml_fp16_to_fp32(*(ggml_fp16_t *) &data[i]); - } else if (type == GGML_TYPE_F32) { - v = *(float *) &data[i]; - } else if (type == GGML_TYPE_I64) { - v = (float) *(int64_t *) &data[i]; - } else if (type == GGML_TYPE_I32) { - v = (float) *(int32_t *) &data[i]; - } else if (type == GGML_TYPE_I16) { - v = (float) *(int16_t *) &data[i]; - } else if (type == GGML_TYPE_I8) { - v = (float) *(int8_t *) &data[i]; - } else { - GGML_ABORT("fatal error"); - } + const float v = ggml_get_float_value(data, type, nb, i0, i1, i2, i3); LOG("%12.4f", v); - sum += v; if (i0 < ne[0] - 1) LOG(", "); } LOG("],\n"); @@ -77,6 +103,12 @@ static void ggml_print_tensor(uint8_t * LOG(" ]\n"); LOG(" sum = %f\n", sum); } + + // TODO: make this abort configurable/optional? + if (std::isnan(sum)) { + LOG_ERR("encountered NaN - aborting\n"); + exit(0); + } } /** diff -pruN 5882+dfsg-2/examples/gritlm/CMakeLists.txt 6641+dfsg-2/examples/gritlm/CMakeLists.txt --- 5882+dfsg-2/examples/gritlm/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/gritlm/CMakeLists.txt 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -set(TARGET llama-gritlm) -add_executable(${TARGET} gritlm.cpp) -install(TARGETS ${TARGET} RUNTIME) -target_link_libraries(${TARGET} PRIVATE common llama ${CMAKE_THREAD_LIBS_INIT}) -target_compile_features(${TARGET} PRIVATE cxx_std_17) diff -pruN 5882+dfsg-2/examples/gritlm/README.md 6641+dfsg-2/examples/gritlm/README.md --- 5882+dfsg-2/examples/gritlm/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/gritlm/README.md 1970-01-01 00:00:00.000000000 +0000 @@ -1,62 +0,0 @@ -## Generative Representational Instruction Tuning (GRIT) Example -[gritlm] a model which can generate embeddings as well as "normal" text -generation depending on the instructions in the prompt. - -* Paper: https://arxiv.org/pdf/2402.09906.pdf - -### Retrieval-Augmented Generation (RAG) use case -One use case for `gritlm` is to use it with RAG. If we recall how RAG works is -that we take documents that we want to use as context, to ground the large -language model (LLM), and we create token embeddings for them. We then store -these token embeddings in a vector database. - -When we perform a query, prompt the LLM, we will first create token embeddings -for the query and then search the vector database to retrieve the most -similar vectors, and return those documents so they can be passed to the LLM as -context. Then the query and the context will be passed to the LLM which will -have to _again_ create token embeddings for the query. But because gritlm is used -the first query can be cached and the second query tokenization generation does -not have to be performed at all. - -### Running the example -Download a Grit model: -```console -$ scripts/hf.sh --repo cohesionet/GritLM-7B_gguf --file gritlm-7b_q4_1.gguf --outdir models -``` - -Run the example using the downloaded model: -```console -$ ./llama-gritlm -m models/gritlm-7b_q4_1.gguf - -Cosine similarity between "Bitcoin: A Peer-to-Peer Electronic Cash System" and "A purely peer-to-peer version of electronic cash w" is: 0.605 -Cosine similarity between "Bitcoin: A Peer-to-Peer Electronic Cash System" and "All text-based language problems can be reduced to" is: 0.103 -Cosine similarity between "Generative Representational Instruction Tuning" and "A purely peer-to-peer version of electronic cash w" is: 0.112 -Cosine similarity between "Generative Representational Instruction Tuning" and "All text-based language problems can be reduced to" is: 0.547 - -Oh, brave adventurer, who dared to climb -The lofty peak of Mt. Fuji in the night, -When shadows lurk and ghosts do roam, -And darkness reigns, a fearsome sight. - -Thou didst set out, with heart aglow, -To conquer this mountain, so high, -And reach the summit, where the stars do glow, -And the moon shines bright, up in the sky. - -Through the mist and fog, thou didst press on, -With steadfast courage, and a steadfast will, -Through the darkness, thou didst not be gone, -But didst climb on, with a steadfast skill. - -At last, thou didst reach the summit's crest, -And gazed upon the world below, -And saw the beauty of the night's best, -And felt the peace, that only nature knows. - -Oh, brave adventurer, who dared to climb -The lofty peak of Mt. Fuji in the night, -Thou art a hero, in the eyes of all, -For thou didst conquer this mountain, so bright. -``` - -[gritlm]: https://github.com/ContextualAI/gritlm diff -pruN 5882+dfsg-2/examples/gritlm/gritlm.cpp 6641+dfsg-2/examples/gritlm/gritlm.cpp --- 5882+dfsg-2/examples/gritlm/gritlm.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/gritlm/gritlm.cpp 1970-01-01 00:00:00.000000000 +0000 @@ -1,231 +0,0 @@ -#include "arg.h" -#include "common.h" -#include "llama.h" - -#include -#include - -// #define GRIT_DEBUG - -static std::vector> encode(llama_context * ctx, const std::vector & sentences, const std::string & instruction) { - std::vector> result; - - const llama_model * model = llama_get_model(ctx); - const llama_vocab * vocab = llama_model_get_vocab(model); - - llama_batch batch = llama_batch_init(llama_n_batch(ctx), 0, 1); - - for (uint64_t i = 0; i < sentences.size(); i++) { - common_batch_clear(batch); - - const std::string input_string = instruction + sentences[i]; - - std::vector inputs = common_tokenize(vocab, input_string, true, false); - - const int32_t n_toks = inputs.size(); - - // GritLM seems to have EOS = "" - // https://github.com/ContextualAI/gritlm/blob/92025b16534712b31b3c4aaaf069350e222bd5f8/gritlm/gritlm.py#L18 - // inputs.push_back(llama_vocab_eos(vocab)); - - // we want to ignore instruction tokens for mean pooling - const int32_t n_inst = common_tokenize(vocab, instruction, true, false).size(); - -#ifdef GRIT_DEBUG - // debug tokens - should be matching as referenced in the GritLM sample - std::for_each(inputs.begin(), inputs.end(), [&ctx](llama_token t) { - std::printf("[%u:%s]", t, llama_token_to_piece(ctx, t).c_str()); - }); - std::printf("\n"); -#endif - - // add input to batch (this increments n_tokens) - for (int32_t j = 0; j < n_toks; j++) { - common_batch_add(batch, inputs[j], j, { 0 }, true); - } - - // clear previous kv_cache values (irrelevant for embeddings) - llama_memory_clear(llama_get_memory(ctx), true); - llama_set_causal_attn(ctx, false); - - // run model - llama_decode(ctx, batch); - - // get embedding dimensions - uint64_t n_embd = llama_model_n_embd(model); - - // allocate embedding output - std::vector emb_unorm(n_embd, 0.0f); - - // sum up all token embeddings - for (int32_t k = n_inst; k < n_toks; k++) { - float * emb = llama_get_embeddings_ith(ctx, k); - for (uint64_t j = 0; j < n_embd; j++) { - emb_unorm[j] += emb[j]; - } - } - - // divide by number of tokens (mean pooling) - { - const uint64_t n_sent = n_toks - n_inst; - - for (uint64_t j = 0; j < n_embd; j++) { - emb_unorm[j] /= n_sent; - } - } - - std::vector emb_norm(emb_unorm.size()); - common_embd_normalize(emb_unorm.data(), emb_norm.data(), n_embd, 2); - result.push_back(emb_norm); - -#ifdef GRIT_DEBUG - // print out emb_norm - std::printf("embedding %ld: ", i); - for (uint64_t j = 0; j < n_embd; j++) { - std::printf("%.5f ", emb_norm[j]); - } - std::printf("\n\n"); -#endif - } - - llama_batch_free(batch); - - return result; -} - -static std::string generate(llama_context * ctx, llama_sampler * smpl, const std::string & prompt, bool stream) { - std::string result; - - const llama_model * model = llama_get_model(ctx); - const llama_vocab * vocab = llama_model_get_vocab(model); - - llama_token eos_token = llama_vocab_eos(vocab); - - llama_memory_clear(llama_get_memory(ctx), true); - llama_set_causal_attn(ctx, true); - - llama_batch bat = llama_batch_init(llama_n_batch(ctx), 0, 1); - - std::vector inputs = common_tokenize(vocab, prompt, false, true); - int32_t i_current_token = 0; - - while (true) { - common_batch_clear(bat); - { - const int32_t n_inputs = inputs.size(); - - for (int32_t i = 0; i < n_inputs; i++) { - common_batch_add(bat, inputs[i], i_current_token++, { 0 }, i == n_inputs - 1); - } - } - inputs.clear(); - - llama_decode(ctx, bat); - - llama_token token = llama_sampler_sample(smpl, ctx, bat.n_tokens - 1); - - if (token == eos_token) { - break; - } - - std::string piece = common_token_to_piece(ctx, token); - if (stream) { - std::printf("%s", piece.c_str()); - std::fflush(stdout); - } - - inputs.push_back(token); - - result += piece; - } - - if (stream) { - std::printf("\n"); - } - - llama_batch_free(bat); - - return result; -} - -static std::string gritlm_instruction(const std::string & instruction) { - return !instruction.empty() ? "<|user|>\n" + instruction + "\n<|embed|>\n" : "<|embed|>\n"; -} - -int main(int argc, char * argv[]) { - common_params params; - - if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_COMMON)) { - return 1; - } - - common_init(); - - llama_model_params mparams = common_model_params_to_llama(params); - llama_context_params cparams = common_context_params_to_llama(params); - - cparams.embeddings = true; - - llama_backend_init(); - - llama_model * model = llama_model_load_from_file(params.model.path.c_str(), mparams); - - // create generation context - llama_context * ctx = llama_init_from_model(model, cparams); - - auto sparams = llama_sampler_chain_default_params(); - - sparams.no_perf = false; - - llama_sampler * smpl = llama_sampler_chain_init(sparams); - - llama_sampler_chain_add(smpl, llama_sampler_init_greedy()); - - // ### Embedding/Representation ### - // samples taken from: https://github.com/ContextualAI/gritlm#basic - { - const std::string instruction = "Given a scientific paper title, retrieve the paper's abstract"; - - const std::vector queries = { - "Bitcoin: A Peer-to-Peer Electronic Cash System", - "Generative Representational Instruction Tuning", - }; - - const std::vector documents = { - "A purely peer-to-peer version of electronic cash would allow online payments to be sent directly from one party to another without going through a financial institution. Digital signatures provide part of the solution, but the main benefits are lost if a trusted third party is still required to prevent double-spending. We propose a solution to the double-spending problem using a peer-to-peer network. The network timestamps transactions by hashing them into an ongoing chain of hash-based proof-of-work, forming a record that cannot be changed without redoing the proof-of-work. The longest chain not only serves as proof of the sequence of events witnessed, but proof that it came from the largest pool of CPU power. As long as a majority of CPU power is controlled by nodes that are not cooperating to attack the network, they'll generate the longest chain and outpace attackers. The network itself requires minimal structure. Messages are broadcast on a best effort basis, and nodes can leave and rejoin the network at will, accepting the longest proof-of-work chain as proof of what happened while they were gone.", - "All text-based language problems can be reduced to either generation or embedding. Current models only perform well at one or the other. We introduce generative representational instruction tuning (GRIT) whereby a large language model is trained to handle both generative and embedding tasks by distinguishing between them through instructions. Compared to other open models, our resulting GritLM 7B sets a new state of the art on the Massive Text Embedding Benchmark (MTEB) and outperforms all models up to its size on a range of generative tasks. By scaling up further, GritLM 8X7B outperforms all open generative language models that we tried while still being among the best embedding models. Notably, we find that GRIT matches training on only generative or embedding data, thus we can unify both at no performance loss. Among other benefits, the unification via GRIT speeds up Retrieval-Augmented Generation (RAG) by > 60% for long documents, by no longer requiring separate retrieval and generation models. Models, code, etc. are freely available at https://github.com/ContextualAI/gritlm.", - }; - - // No need to add instruction for retrieval documents - const std::vector> d_rep = encode(ctx, documents, gritlm_instruction("")); - const std::vector> q_rep = encode(ctx, queries, gritlm_instruction(instruction)); - - const int n_embd = llama_model_n_embd(model); - - const float cosine_sim_q0_d0 = common_embd_similarity_cos(q_rep[0].data(), d_rep[0].data(), n_embd); - const float cosine_sim_q0_d1 = common_embd_similarity_cos(q_rep[0].data(), d_rep[1].data(), n_embd); - const float cosine_sim_q1_d0 = common_embd_similarity_cos(q_rep[1].data(), d_rep[0].data(), n_embd); - const float cosine_sim_q1_d1 = common_embd_similarity_cos(q_rep[1].data(), d_rep[1].data(), n_embd); - - std::printf("Cosine similarity between \"%.50s\" and \"%.50s\" is: %.3f\n", queries[0].c_str(), documents[0].c_str(), cosine_sim_q0_d0); - std::printf("Cosine similarity between \"%.50s\" and \"%.50s\" is: %.3f\n", queries[0].c_str(), documents[1].c_str(), cosine_sim_q0_d1); - std::printf("Cosine similarity between \"%.50s\" and \"%.50s\" is: %.3f\n", queries[1].c_str(), documents[0].c_str(), cosine_sim_q1_d0); - std::printf("Cosine similarity between \"%.50s\" and \"%.50s\" is: %.3f\n", queries[1].c_str(), documents[1].c_str(), cosine_sim_q1_d1); - } - - llama_set_embeddings(ctx, false); - - // ### Generation ### - // GritLM models are not finetuned with system prompts, as you can just include system-like instructions together with your user instruction - { - const std::string prompt = "<|user|>\nPlease write me a poem about my recent hike of Mt. Fuji at midnight in the style of Shakespeare.\n<|assistant|>\n"; - std::string response = generate(ctx, smpl, prompt, true); - } - - llama_sampler_free(smpl); - llama_free(ctx); - llama_model_free(model); - llama_backend_free(); - - return 0; -} diff -pruN 5882+dfsg-2/examples/jeopardy/README.md 6641+dfsg-2/examples/jeopardy/README.md --- 5882+dfsg-2/examples/jeopardy/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/jeopardy/README.md 1970-01-01 00:00:00.000000000 +0000 @@ -1,21 +0,0 @@ -# llama.cpp/example/jeopardy - -This is pretty much just a straight port of aigoopy/llm-jeopardy/ with an added graph viewer. - -The jeopardy test can be used to compare the fact knowledge of different models and compare them to each other. This is in contrast to some other tests, which test logical deduction, creativity, writing skills, etc. - - -Step 1: Open jeopardy.sh and modify the following: -``` -MODEL=(path to your model) -MODEL_NAME=(name of your model) -prefix=(basically, if you use vicuna it's Human: , if you use something else it might be User: , etc) -opts=(add -instruct here if needed for your model, or anything else you want to test out) -``` -Step 2: Run `jeopardy.sh` from the llama.cpp folder - -Step 3: Repeat steps 1 and 2 until you have all the results you need. - -Step 4: Run `graph.py`, and follow the instructions. At the end, it will generate your final graph. - -Note: The Human bar is based off of the full, original 100 sample questions. If you modify the question count or questions, it will not be valid. diff -pruN 5882+dfsg-2/examples/jeopardy/graph.py 6641+dfsg-2/examples/jeopardy/graph.py --- 5882+dfsg-2/examples/jeopardy/graph.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/jeopardy/graph.py 1970-01-01 00:00:00.000000000 +0000 @@ -1,58 +0,0 @@ -#!/usr/bin/env python3 -import matplotlib.pyplot as plt -import os -import csv - -labels = [] -numbers = [] -numEntries = 1 - -rows = [] - - -def bar_chart(numbers, labels, pos): - plt.bar(pos, numbers, color='blue') - plt.xticks(ticks=pos, labels=labels) - plt.title("Jeopardy Results by Model") - plt.xlabel("Model") - plt.ylabel("Questions Correct") - plt.show() - - -def calculatecorrect(): - directory = os.fsencode("./examples/jeopardy/results/") - csv_reader = csv.reader(open("./examples/jeopardy/qasheet.csv", 'rt'), delimiter=',') - for row in csv_reader: - global rows - rows.append(row) - for listing in os.listdir(directory): - filename = os.fsdecode(listing) - if filename.endswith(".txt"): - file = open("./examples/jeopardy/results/" + filename, "rt") - global labels - global numEntries - global numbers - labels.append(filename[:-4]) - numEntries += 1 - i = 1 - totalcorrect = 0 - for line in file.readlines(): - if line.strip() != "------": - print(line) - else: - print("Correct answer: " + rows[i][2] + "\n") - i += 1 - print("Did the AI get the question right? (y/n)") - if input() == "y": - totalcorrect += 1 - numbers.append(totalcorrect) - - -if __name__ == '__main__': - calculatecorrect() - pos = list(range(numEntries)) - labels.append("Human") - numbers.append(48.11) - bar_chart(numbers, labels, pos) - print(labels) - print(numbers) diff -pruN 5882+dfsg-2/examples/jeopardy/jeopardy.sh 6641+dfsg-2/examples/jeopardy/jeopardy.sh --- 5882+dfsg-2/examples/jeopardy/jeopardy.sh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/jeopardy/jeopardy.sh 1970-01-01 00:00:00.000000000 +0000 @@ -1,30 +0,0 @@ -#!/usr/bin/env bash -set -e - -MODEL=./models/ggml-vicuna-13b-1.1-q4_0.bin -MODEL_NAME=Vicuna - -# exec options -prefix="Human: " # Ex. Vicuna uses "Human: " -opts="--temp 0 -n 80" # additional flags -nl=' -' -introduction="You will be playing a game of Jeopardy. Simply answer the question in the correct format (Ex. What is Paris, or Who is George Washington)." - -# file options -question_file=./examples/jeopardy/questions.txt -touch ./examples/jeopardy/results/$MODEL_NAME.txt -output_file=./examples/jeopardy/results/$MODEL_NAME.txt - -counter=1 - -echo 'Running' -while IFS= read -r question -do - exe_cmd="./llama-cli -p "\"$prefix$introduction$nl$prefix$question\"" "$opts" -m ""\"$MODEL\""" >> ""\"$output_file\"" - echo $counter - echo "Current Question: $question" - eval "$exe_cmd" - echo -e "\n------" >> $output_file - counter=$((counter+1)) -done < "$question_file" diff -pruN 5882+dfsg-2/examples/jeopardy/qasheet.csv 6641+dfsg-2/examples/jeopardy/qasheet.csv --- 5882+dfsg-2/examples/jeopardy/qasheet.csv 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/jeopardy/qasheet.csv 1970-01-01 00:00:00.000000000 +0000 @@ -1,103 +0,0 @@ -Index,Original Category,Original Correct Question,Model Prompt -1,The Oscars,Who is John Williams?,Which actor Born in 1932 was the son of a percussionist in the CBS radio orchestra has been nominated for 53 Oscars? -2,English Literature,What is Paradise Lost?,"What work in English Literature says: 'The mind is its own place, & in itself can make a heaven of hell, a hell of heaven. What matter where, if I be still the same'?" -3,Writers’ Lesser-Known Works,Who is Niccolò Machiavelli?,"Known for more philosophical works, he wrote the play 'La Mandragola', in which Florentines are rewarded for immoral actions?" -4,Exploration,What is Easter Island (Rapa Nui)?,"James Cook's account of a 1774 visit where records an object 'near 27 feet long, and upwards of 8 feet over the breast or shoulders'?" -5,The Bill of Rights,What is the Eighth Amendment?,England's 'Bloody Assizes' & a 1685 life sentence for perjury were 2 main origins of which amendment to the U.S. Constitution? -6,Nobel Peace Prize Winners,Who are Nelson Mandela & Desmond Tutu?,"Which nobel peace price winners each lived at times on Vilakazi St. in Soweto , so it claims to be the world's only street home to 2 Nobel Peace Prize winners?" -7,Famous Names,Who is Walt Disney?,"In 1966, the year of who's death did he share plans for an experimental prototype community in Florida?" -8,Geography,What is Colombia?,"Of the 13 nations through which the Equator passes, what is the only one whose coastline borders the Caribbean Sea?" -9,Fashion History,What are rhinestones?,"Which decorative items in fashion history get their name from their origin in the port city of Strasbourg, on the border of France & Germany?" -10,Movies of the ’80s,What is Driving Miss Daisy?,What 1980's movie is based on an off-Broadway play with just 3 characters and won the Best Picture Oscar & the actors in all 3 roles were nominated? -11,Novelists,Who is John Grisham?,"A 2012 book review for which novelist noted subjects that 'sparked his ire': capital punishment, big tobacco & 'the plight of the unjustly convicted'?" -12,20th Century Eponyms,What is the Maginot Line?,"A 1940 headline about what 20th Century Eponym included 'failure', 'liability when it came to offense' & 'stout hearts no match for tanks'?" -13,City History,What is Stockholm?,"Over 700 years after its traditional 1252 founding date, what port city became associated with a psychological response?" -14,Brand Names,What is Jacuzzi?,"The success of what brand has its roots with a hydrotherapy pump its cofounder created for his son, who had arthritis?" -15,American Authors,Who is Washington Irving?,"In a periodical in 1807, what American Author called New York City 'Gotham, Gotham! Most enlightened of cities'?" -16,Symbols,What is “less than”?,What symbol is a rotated V in math and a feeling of some marginalized or underrepresented people in society? -17,Movie Theme Songs,Who is James Bond?,"Monty Norman, the composer of what character's theme, said the staccato riff conveyed sexiness, mystery & ruthlessness?" -18,American Novelists,Who is Joseph Heller?,"What American Novelist served with an airman named Yohannan in World War II & despite what readers might think, he said he enjoyed his service?" -19,Medieval Places,"What is Canterbury, England? (Canterbury Cathedral)","In what Medieval place did one of the participants in an 1170 event say, 'Let us away, knights; he will rise no more'?" -20,Countries of Africa,What is Morocco?,"At one time a province of the Roman Empire, what African country kingdom is known to Arabic scholars as Al-Maghrib Al-Aqsa, 'the far west'?" -21,Statehood,What is Wyoming?,Congress relented in 1890 after what prospective state said it would wait 100 years rather than come in without the women? -22,1980s Movies,What is Raiders of the Lost Ark?,"A writer & producer of what movie said he wanted it to be like a Western or James Bond film, 'only it takes place in the 30s'?" -23,Art Exhibitions,Who is Rembrandt?,In 1898 what's been called the first blockbuster art show was devoted to which artist & put on for Queen Wilhelmina's coronation? -24,Countries of the World,What is Mongolia?,"Part of the largest contiguous land empire during the 1200s & 1300s, today what is the world's second-largest landlocked country?" -25,Literature,What is “Howl”?,A 2006 book was titled 'The Poem That Changed America:' What 'Fifty Years Later'? -26,Invasions,Who is William of Orange?,"Backed by 14,000 troops, who invaded England to restore, in his words, its 'religion, laws, and liberties'?" -27,Landmarks,What is the Eiffel Tower?,"After its completion in the late 19th c., what was landmark was called 'a truly tragic street lamp' & a 'high & skinny pyramid of iron ladders'?" -28,Geographic Name’s the Same,What is Dover?,"The busiest passenger port in the U.K., what shares its name with a capital of one of the original 13 states?" -29,Names in the Bookstore,Who is Peter Mark Roget?,"This man made lists, perhaps to cope with depression; a set of lists he published in 1852 made whose name synonymous with a type of book?" -30,U.S. History,Who is Dr. Samuel Mudd?,"An 1869 presidential pardon was granted to which man, due in part to a plea by the Medical Society of Harford County, Maryland?" -31,American Literature,What is The Things They Carried?,"Letters, pocket knives, C rations & steel helmets are among the tangible items referred to in the title of what American literature modern war classic?" -32,Nonfiction,What is The Communist Manifesto,"What nonfiction book has the line, 'The discovery of America…opened up fresh ground for the rising bourgeoisie'?" -33, a new version was passed 81 years later,Laws in U.S. History,What is the Civil Rights Act?,,,,,,,,,,,,,,,,,,0, 2/3 -34,Names of Myth,Who is Helen of Troy?,"Whose brothers, Castor & Pollux, saved her after Theseus stole her away as a kid; a larger force would seek her later in life?" -35,African Countries,What is Sudan?,"Once Africa's largest country in area, what African Country dropped to third in 2011 when a portion of it declared independence?" -36,The Ancient World,What is Alexandria?,"The ancient writer Galen said books on ships arriving to what city's port were seized, originals kept & copies returned?" -37,Famous Names,Who is Andy Warhol?,"For a special 1970s cookbook, who provided one simple recipe–a can of Campbell's tomato soup & 2 cans of milk?" -38,People & Places,What is Guam?,"Thought to descend from people of Southeast Asia, the Chamorro make up what U.S. territory’s largest ethnic group?" -39,Current World Leaders,What is the Philippines?,"In office from 2022, the president of what country has taken so many foreign trips a play on his name is 'Ferdinand Magellan Jr.'?" -40,Writers & The South,Who is Tennessee Williams?,In 1939 which writer lived on Toulouse Street in the French Quarter & chose the professional name that bonded him to the South? -41,National Parks,What is Yellowstone?,"What National Park is named for a river indigenous people called Mi tse a-da-zi, translated by French-speaking trappers as 'Pierre Jaune'?" -42,Sports,Who are the Harlem Globetrotters?,"In 2010 who introduced the 4-point shot, 35 feet from the basket?" -43,The U.S. Military,What is “Top Gun”?,Losses over Asia in the 1960s led to the establishment of the program known as what at a San Diego naval base in 1969? -44,Art & Science,What is Halley’s Comet?,"A craft that visited what was named for Giotto, based on the story that 680 years earlier, the painter depicted it as the Star of Bethlehem?" -45,Words From World War I,What is “tank”?,"In World War I, 'Cistern' & 'reservoir' were suggested names for what secret invention, but the British preferred this less clumsy monosyllable?" -46,European History,What is Holy Roman Emperor?,"Until 1806, some German nobles included among their honors the title of 'Elector' for their role in selecting this personage?" -47,Theater History,Who is Peter Pan?,"In 1904, wearing a harness, actress Nina Boucicault became the first to play what character onstage?" -48,European Cities,What is Aachen?,"Alphabetically the first German city in encyclopedias, what was also the first one taken by the Allies in World War II?" -49,Word Origins,What is mantra?,This Sanskrit word referring to a spoken word or phrase comes from a word for 'to think'? -50,Inventions,What is barbed wire?,1917's 'Elements of Trench Warfare' said what Old West invention was 'difficult to destroy' & 'difficult to get through'? -51,World War II,What is Schindler’s list?,"Mimi Reinhard, who never learned to type using more than 2 fingers, produced what in World War II with 1,100 names, including hers?" -52, their offspring was the source of this mythical object,Mythology,What is the Golden Fleece? -53,Literature,What is Pride and Prejudice?,"Published in 2011, P.D. James' final novel, 'Death Comes to Pemberley', was a sequel to what novel from 200 years earlier?" -54, only these 2 west of the Mississippi River border each other,U.S. State Names,What are Oregon & Nevada? -55,Word Origins,What is passion?,"Originally relating to a story of suffering, what word now more commonly refers to strong emotion of any kind?" -56,World Cinema,What is La Vie en Rose?,"The 2007 biopic called 'La Môme' in France, meaning 'The Kid', was released in the U.S. under what other French title?" -57,History,What is Santa Maria?,"Returning home in 1493, Columbus stopped in the Azores at an island with what name, also something he'd lost off the Haiti coast?" -58,Landmarks,What is a kremlin?,Pskov & Nizhny Novgorod are 2 of the cities that have a fortress called what? -59,Foreign-Born Authors,Who is Vladimir Nabokov?,In the 1950s the New York Times said what author 'is writing about all lust' & his lecherous narrator 'is all of us'? -60,Astronomy & Geography,What is Capricorn?,"At the winter solstice, the sun is in Sagittarius; it once appeared in what constellation, giving a geographic feature its name?" -61,Television,What is Law & Order?,"Mike Post combined the sound of a slamming jail door, an anvil & 100 men stomping on a floor for what television series that debuted in 1990?" -62,British Landmarks,What is the Tower of London?,"Like Sir Thomas More, 3 16th century English queens are buried at what British location?" -63,Early American History,What are witches?,"In 1692 Increase Mather wrote, 'It were better that ten suspected' of these who 'escape, than that one innocent person … be condemned'?" -64,Geography Mnemonics,What are Arkansas and Louisiana?,"The Geography Mnemonic Mimal, sometimes said to be the silhouette of a chef or elf, stands for Minnesota, Iowa, Missouri, and what other 2 states?" -65,Business Milestones,What is the Ford Model T?,"What was first sold in 1908, at a price equivalent to about $27,000 today?" -66,In The Bookstore,Who is Tom Clancy?,The name of what author dead since 2013 now appears on books written by a former U.S. marshal & a former Apache helicopter pilot? -67,Historic Art,What is the Bayeux Tapestry?,The artwork once known in France as 'la tapisserie de la Reine Mathilde' is better known as what? -68,Pop Stars,Who is Madonna?,In 2022 which pop star became the first woman to have a Billboard Top 10 album in 5 decades starting with the 1980s? -69,Classic Tale Characters,Who is Scheherazade?,"In one 19th century translation, what female classic tale character 'perceived the dawn of day and ceased' speaking nearly 1,000 times?" -70,USA,What is Jack Daniel’s?,"Ironically, though what company founded in the 1860s is Moore County, Tennessee's largest employer, Moore is a dry county?" -71,Historic People,Who was William Bligh?,"After a 1789 event, who wrote, 'My first determination was to seek a supply of…water at Tofoa, & afterwards to sail for Tongataboo'?" -72,The Movies,What is The Godfather?,Laurence Olivier & Ernest Borgnine were considered for the lead role & Sergio Leone to direct for what film that turned 50 in 2022? -73,Continental Geography,What is Colombia?,"Until a 1903 secession, what country's contiguous territory spanned 2 continents?" -74,Foreign-Born Authors,Who is Isabel Allende?,"Early in her career which foreign-born author translated romance novels into Spanish, often changing the dialogue to make the heroines smarter?" -75,Historic Crimes,What is the Mona Lisa?,"Saying it was stolen by Napoleon, self-styled Italian patriot Vincenzo Peruggia took what in 1911?" -76,U.S. Bodies of Water,What is Lake Mead?,"Continuing a downward trend, in July 2022 what US body of water was at 27% capacity, its lowest level since 1937 when it was first being filled?" -77,Gods & Goddesses,Who is Aurora (or Eos)?,"Each morning which goddess began her ride in her chariot across the sky ahead of her brother Sol, or Helios?" -78,America At War,What is the Battle of New Orleans?,"Until the Civil War, the Jan. 8 date of what American battle of dubious military importance but big morale value was a national holiday?" -79,Children’s Books,What is The Velveteen Rabbit?,"Which children's book title character is told 'By the time you are real, most of your hair has been loved off your eyes drop out & you get shabby'?" -80,TV Finales,What is Grace and Frankie?,"In a TV reunion over 40 years in the making, Dolly Parton appeared as an angel named Agnes in the final episode of what comedy in 2022?" -81,American Poems,Who is Evangeline?,"In an 1847 American poem what character sees her town of Grand-Pré burned, but finally reunites with her beau for a kiss before his death?" -82,Famous Names,Who is Banksy?,"In 2001 who published a book called 'Banging Your Head Against a Brick Wall'; in 2002, 'Existencilism'?" -83,Children’s Lit,What is Charlotte’s Web?,The title object of what childrens book 'never looked more beautiful each strand held dozens of bright drops of early morning dew'? -84,Classic Songs,What is “Here Comes Santa Claus”?,The shouts of excited children at a 1946 holiday parade are said to have inspired what perennial classic song favorite? -85,Brand Names,What are Milk Duds?,"Unable to make what candies perfectly round, the confectioner embraced this flawed name for the product?" -86,Countries of the World,What is Italy?,"What country is home to 58 UNESCO World Heritage Sites, more than any other country; the sites include a volcano & a lagoon?" -87,Action Movies,What is Die Hard?,"What action movie's last line is 'If this is their idea of Christmas, I gotta be here for New Years'?" -88,Presidential Facts,Who is Woodrow Wilson?,Only 3 presidents have married while in office— John Tyler was the first & which one was the last? -89,19th Century Americans,Who is Frederick Douglass?,"Demonstrating the dignity & humanity of Black Americans, who sat for 160 known photographs, the most of any American in the 19th century?" -90,Latin Phrases,What is “quid pro quo”?,"Originally, which Latin 3-word phrase referred to when a doctor or apothecary substituted one medicine for another?" -91,1970s Movies,What is Monty Python and the Holy Grail?,The 1975 premiere of what movie comedy advertised free coconuts for the first thousand in the audience? -92,Name’s The Same,What is Manhattan?,"A cocktail, an island & a WWII venture originally called 'Development of Substitute Materials' all bear what name?" -93,U.S. Presidents,Who is Calvin Coolidge?,"Which US President was sworn in twice as President within 2 years, first by his father & then later by a former U.S. President?" -94,Plays,What is The Tempest?,A 1609 story in which an exiled king of Bulgaria creates a sea palace with his magic may have inspired the plot of what play? -95,Landmarks,What is the Berlin Wall?,"In 2009, during a 20th anniversary celebration, what landmark was called 'an edifice of fear. On Nov. 9, it became a place of joy'?" -96,World Capitals,"What is Vienna, Austria?","Among what world capital's nicknames are the 'City of Classical Music' &, possibly in honor of a famous resident from 1860 to 1938, the 'City of Dreams'?" -97,Language & Its Meanings,What is a night owl?,"Now meaning someone with nocturnal habits, what catches a sleeping dove in Shakespeare's 'Lucrece'?" -98,Flags of Our Hemisphere,What is Brazil?,"The stars on what country's flag represent states, 26 of them; unlike the USA's, its 'federal district' gets its own 27th star?" -99,Names in U.S. History,Who is Oliver Brown?,What father was the only man among the 13 plaintiffs in a US class-action case filed in 1951? -100,Children’s Authors,"Who is Sarah? (from Sarah, Plain and Tall)","Reversing the story of what heroine she created, childrens author Patricia Maclachlan was born on the prairie but spent much of her life in New England?" -,,, -TOTALS,,, diff -pruN 5882+dfsg-2/examples/jeopardy/questions.txt 6641+dfsg-2/examples/jeopardy/questions.txt --- 5882+dfsg-2/examples/jeopardy/questions.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/jeopardy/questions.txt 1970-01-01 00:00:00.000000000 +0000 @@ -1,100 +0,0 @@ -Which man born in 1932 was the son of a percussionist in the CBS radio orchestra has been nominated for 53 Oscars? -What work in English Literature says: 'The mind is its own place, & in itself can make a heaven of hell, a hell of heaven. What matter where, if I be still the same'? -Known for more philosophical works, he wrote the play 'La Mandragola', in which Florentines are rewarded for immoral actions? -James Cook's account of a 1774 visit where records an object 'near 27 feet long, and upwards of 8 feet over the breast or shoulders'? -England's 'Bloody Assizes' & a 1685 life sentence for perjury were 2 main origins of which amendment to the U.S. Constitution? -Which nobel peace price winners each lived at times on Vilakazi St. in Soweto , so it claims to be the world's only street home to 2 Nobel Peace Prize winners? -In 1966, the year of who's death did he share plans for an experimental prototype community in Florida? -Of the 13 nations through which the Equator passes, what is the only one whose coastline borders the Caribbean Sea? -Which decorative items in fashion history get their name from their origin in the port city of Strasbourg, on the border of France & Germany? -What 1980's movie is based on an off-Broadway play with just 3 characters and won the Best Picture Oscar & the actors in all 3 roles were nominated? -A 2012 book review for which novelist noted subjects that 'sparked his ire': capital punishment, big tobacco & 'the plight of the unjustly convicted'? -A 1940 headline about what 20th Century Eponym included 'failure', 'liability when it came to offense' & 'stout hearts no match for tanks'? -Over 700 years after its traditional 1252 founding date, what port city became associated with a psychological response? -The success of what brand has its roots with a hydrotherapy pump its cofounder created for his son, who had arthritis? -In a periodical in 1807, what American Author called New York City 'Gotham, Gotham! Most enlightened of cities'? -What symbol is a rotated V in math and a feeling of some marginalized or underrepresented people in society? -Monty Norman, the composer of what character's theme, said the staccato riff conveyed sexiness, mystery & ruthlessness? -What American Novelist served with an airman named Yohannan in World War II & despite what readers might think, he said he enjoyed his service? -In what Medieval place did one of the participants in an 1170 event say, 'Let us away, knights; he will rise no more'? -At one time a province of the Roman Empire, what African country kingdom is known to Arabic scholars as Al-Maghrib Al-Aqsa, 'the far west'? -Congress relented in 1890 after what prospective state said it would wait 100 years rather than come in without the women? -A writer & producer of what movie said he wanted it to be like a Western or James Bond film, 'only it takes place in the 30s'? -In 1898 what's been called the first blockbuster art show was devoted to which artist & put on for Queen Wilhelmina's coronation? -Part of the largest contiguous land empire during the 1200s & 1300s, today what is the world's second-largest landlocked country? -A 2006 book was titled 'The Poem That Changed America:' What 'Fifty Years Later'? -Backed by 14,000 troops, who invaded England to restore, in his words, its 'religion, laws, and liberties'? -After its completion in the late 19th c., what was landmark was called 'a truly tragic street lamp' & a 'high & skinny pyramid of iron ladders'? -The busiest passenger port in the U.K., what shares its name with a capital of one of the original 13 states? -This man made lists, perhaps to cope with depression; a set of lists he published in 1852 made whose name synonymous with a type of book? -An 1869 presidential pardon was granted to which man, due in part to a plea by the Medical Society of Harford County, Maryland? -Letters, pocket knives, C rations & steel helmets are among the tangible items referred to in the title of what American literature modern war classic? -What nonfiction book has the line, 'The discovery of America…opened up fresh ground for the rising bourgeoisie'? -A radical Republican championed what 1875 act but the Supreme Court struck it down in 1883; a new version was passed 81 years later? -Whose brothers, Castor & Pollux, saved her after Theseus stole her away as a kid; a larger force would seek her later in life? -Once Africa's largest country in area, what African Country dropped to third in 2011 when a portion of it declared independence? -The ancient writer Galen said books on ships arriving to what city's port were seized, originals kept & copies returned? -For a special 1970s cookbook, who provided one simple recipe–a can of Campbell's tomato soup & 2 cans of milk? -Thought to descend from people of Southeast Asia, the Chamorro make up what U.S. territory’s largest ethnic group? -In office from 2022, the president of what country has taken so many foreign trips a play on his name is 'Ferdinand Magellan Jr.'? -In 1939 which writer lived on Toulouse Street in the French Quarter & chose the professional name that bonded him to the South? -What National Park is named for a river indigenous people called Mi tse a-da-zi, translated by French-speaking trappers as 'Pierre Jaune'? -In 2010 who introduced the 4-point shot, 35 feet from the basket? -Losses over Asia in the 1960s led to the establishment of the program known as what at a San Diego naval base in 1969? -A craft that visited what was named for Giotto, based on the story that 680 years earlier, the painter depicted it as the Star of Bethlehem? -In World War I, 'Cistern' & 'reservoir' were suggested names for what secret invention, but the British preferred this less clumsy monosyllable? -Until 1806, some German nobles included among their honors the title of 'Elector' for their role in selecting this personage? -In 1904, wearing a harness, actress Nina Boucicault became the first to play what character onstage? -Alphabetically the first German city in encyclopedias, what was also the first one taken by the Allies in World War II? -This Sanskrit word referring to a spoken word or phrase comes from a word for 'to think'? -1917's 'Elements of Trench Warfare' said what Old West invention was 'difficult to destroy' & 'difficult to get through'? -Mimi Reinhard, who never learned to type using more than 2 fingers, produced what in World War II with 1,100 names, including hers? -Poseidon carried off the maiden Theophane & turned her into a ewe; their offspring was the source of what mythical object? -Published in 2011, P.D. James' final novel, 'Death Comes to Pemberley', was a sequel to what novel from 200 years earlier? -5 U.S. states have 6-letter names; only which 2 west of the Mississippi River border each other? -Originally relating to a story of suffering, what word now more commonly refers to strong emotion of any kind? -The 2007 biopic called 'La Môme' in France, meaning 'The Kid', was released in the U.S. under what other French title? -Returning home in 1493, Columbus stopped in the Azores at an island with what name, also something he'd lost off the Haiti coast? -Pskov & Nizhny Novgorod are 2 of the cities that have a fortress called what? -In the 1950s the New York Times said what author 'is writing about all lust' & his lecherous narrator 'is all of us'? -At the winter solstice, the sun is in Sagittarius; it once appeared in what constellation, giving a geographic feature its name? -Mike Post combined the sound of a slamming jail door, an anvil & 100 men stomping on a floor for what television series that debuted in 1990? -Like Sir Thomas More, 3 16th century English queens are buried at what British location? -In 1692 Increase Mather wrote, 'It were better that ten suspected' of these who 'escape, than that one innocent person be condemned'? -The Geography Mnemonic Mimal, sometimes said to be the silhouette of a chef or elf, stands for Minnesota, Iowa, Missouri, and what other 2 states? -What was first sold in 1908, at a price equivalent to about $27,000 today? -The name of what author dead since 2013 now appears on books written by a former U.S. marshal & a former Apache helicopter pilot? -The artwork once known in France as 'la tapisserie de la Reine Mathilde' is better known as what? -In 2022 which pop star became the first woman to have a Billboard Top 10 album in 5 decades starting with the 1980s? -In one 19th century translation, what female classic tale character 'perceived the dawn of day and ceased' speaking nearly 1,000 times? -Ironically, though what company founded in the 1860s is Moore County, Tennessee's largest employer, Moore is a dry county? -After a 1789 event, who wrote, 'My first determination was to seek a supply of…water at Tofoa, & afterwards to sail for Tongataboo'? -Laurence Olivier & Ernest Borgnine were considered for the lead role & Sergio Leone to direct for what film that turned 50 in 2022? -Until a 1903 secession, what country's contiguous territory spanned 2 continents? -Early in her career which foreign-born author translated romance novels into Spanish, often changing the dialogue to make the heroines smarter? -Saying it was stolen by Napoleon, self-styled Italian patriot Vincenzo Peruggia took what in 1911? -Continuing a downward trend, in July 2022 what US body of water was at 27% capacity, its lowest level since 1937 when it was first being filled? -Each morning which goddess began her ride in her chariot across the sky ahead of her brother Sol, or Helios? -Until the Civil War, the Jan. 8 date of what American battle of dubious military importance but big morale value was a national holiday? -Which children's book title character is told 'By the time you are real, most of your hair has been loved off your eyes drop out & you get shabby'? -In a TV reunion over 40 years in the making, Dolly Parton appeared as an angel named Agnes in the final episode of what comedy in 2022? -In an 1847 American poem what character sees her town of Grand-Pré burned, but finally reunites with her beau for a kiss before his death? -In 2001 who published a book called 'Banging Your Head Against a Brick Wall'; in 2002, 'Existencilism'? -The title object of what childrens book 'never looked more beautiful each strand held dozens of bright drops of early morning dew'? -The shouts of excited children at a 1946 holiday parade are said to have inspired what perennial classic song favorite? -Unable to make what candies perfectly round, the confectioner embraced this flawed name for the product? -What country is home to 58 UNESCO World Heritage Sites, more than any other country; the sites include a volcano & a lagoon? -What action movie's last line is 'If this is their idea of Christmas, I gotta be here for New Years'? -Only 3 presidents have married while in office— John Tyler was the first & which one was the last? -Demonstrating the dignity & humanity of Black Americans, who sat for 160 known photographs, the most of any American in the 19th century? -Originally, which Latin 3-word phrase referred to when a doctor or apothecary substituted one medicine for another? -The 1975 premiere of what movie comedy advertised free coconuts for the first thousand in the audience? -A cocktail, an island & a WWII venture originally called 'Development of Substitute Materials' all bear what name? -Which US President was sworn in twice as President within 2 years, first by his father & then later by a former U.S. President? -A 1609 story in which an exiled king of Bulgaria creates a sea palace with his magic may have inspired the plot of what play? -In 2009, during a 20th anniversary celebration, what landmark was called 'an edifice of fear. On Nov. 9, it became a place of joy'? -Among what world capital's nicknames are the 'City of Classical Music' &, possibly in honor of a famous resident from 1860 to 1938, the 'City of Dreams'? -Now meaning someone with nocturnal habits, what catches a sleeping dove in Shakespeare's 'Lucrece'? -The stars on what country's flag represent states, 26 of them; unlike the USA's, its 'federal district' gets its own 27th star? -What father was the only man among the 13 plaintiffs in a US class-action case filed in 1951? -Reversing the story of what heroine she created, childrens author Patricia Maclachlan was born on the prairie but spent much of her life in New England? diff -pruN 5882+dfsg-2/examples/json_schema_to_grammar.py 6641+dfsg-2/examples/json_schema_to_grammar.py --- 5882+dfsg-2/examples/json_schema_to_grammar.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/json_schema_to_grammar.py 2025-09-30 07:36:33.000000000 +0000 @@ -586,9 +586,10 @@ class SchemaConverter: properties = list(schema.get('properties', {}).items()) return self._add_rule(rule_name, self._build_object_rule(properties, required, name, schema.get('additionalProperties'))) - elif schema_type in (None, 'object') and 'allOf' in schema: + elif schema_type in (None, 'object', 'string') and 'allOf' in schema: required = set() properties = [] + enum_sets = [] hybrid_name = name def add_component(comp_schema, is_required): if (ref := comp_schema.get('$ref')) is not None: @@ -600,6 +601,9 @@ class SchemaConverter: if is_required: required.add(prop_name) + if 'enum' in comp_schema: + enum_sets.append(set(comp_schema['enum'])) + for t in schema['allOf']: if 'anyOf' in t: for tt in t['anyOf']: @@ -607,6 +611,15 @@ class SchemaConverter: else: add_component(t, is_required=True) + if enum_sets: + enum_intersection = enum_sets[0] + for s in enum_sets[1:]: + enum_intersection &= s + + if enum_intersection: + rule = '(' + ' | '.join((self._generate_constant_rule(v) for v in sorted(enum_intersection))) + ') space' + return self._add_rule(rule_name, rule) + return self._add_rule(rule_name, self._build_object_rule(properties, required, hybrid_name, additional_properties=None)) elif schema_type in (None, 'array') and ('items' in schema or 'prefixItems' in schema): diff -pruN 5882+dfsg-2/examples/llama.vim 6641+dfsg-2/examples/llama.vim --- 5882+dfsg-2/examples/llama.vim 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/llama.vim 2025-09-30 07:36:33.000000000 +0000 @@ -17,7 +17,7 @@ " " start the llama.cpp server with a FIM-compatible model. for example: " -" $ llama-server -m {model.gguf} --port 8012 -ngl 99 -fa -dt 0.1 --ubatch-size 512 --batch-size 1024 --cache-reuse 256 +" $ llama-server -m {model.gguf} --port 8012 -ngl 99 -fa --ubatch-size 512 --batch-size 1024 --cache-reuse 256 " " --batch-size [512, model max context] " diff -pruN 5882+dfsg-2/examples/llm.vim 6641+dfsg-2/examples/llm.vim --- 5882+dfsg-2/examples/llm.vim 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/llm.vim 1970-01-01 00:00:00.000000000 +0000 @@ -1,28 +0,0 @@ -" Basic plugin example - -function! Llm() - - let url = "http://127.0.0.1:8080/completion" - - " Get the content of the current buffer - let buffer_content = join(getline(1, '$'), "\n") - - " Create the JSON payload - let json_payload = {"temp":0.72,"top_k":100,"top_p":0.73,"repeat_penalty":1.100000023841858,"n_predict":256,"stop": ["\n\n\n"],"stream": v:false} - let json_payload.prompt = buffer_content - - " Define the curl command - let curl_command = 'curl -k -s -X POST -H "Content-Type: application/json" -d @- ' . url - let response = system(curl_command, json_encode(json_payload)) - - " Extract the content field from the response - let content = json_decode(response).content - - let split_newlines = split(content, '\n', 1) - - " Insert the content at the cursor position - call setline(line('.'), [ getline('.') . split_newlines[0] ] + split_newlines[1:]) -endfunction - -command! Llm call Llm() -noremap :Llm diff -pruN 5882+dfsg-2/examples/lookahead/README.md 6641+dfsg-2/examples/lookahead/README.md --- 5882+dfsg-2/examples/lookahead/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/lookahead/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -5,3 +5,9 @@ Demonstration of lookahead decoding tech https://lmsys.org/blog/2023-11-21-lookahead-decoding/ More info: https://github.com/ggml-org/llama.cpp/pull/4207 + +Sample command: + +```bash +llama-lookahead -hf ggml-org/Qwen2.5-Coder-3B-Q8_0-GGUF -p "// network server implemented in C\n// author: Peter Hacker\n\n#include" -e -ngl 99 -t 4 -n 512 -c 4096 -kvu +``` diff -pruN 5882+dfsg-2/examples/model-conversion/.gitignore 6641+dfsg-2/examples/model-conversion/.gitignore --- 5882+dfsg-2/examples/model-conversion/.gitignore 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/.gitignore 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,3 @@ +.model_name +data +ppl diff -pruN 5882+dfsg-2/examples/model-conversion/CMakeLists.txt 6641+dfsg-2/examples/model-conversion/CMakeLists.txt --- 5882+dfsg-2/examples/model-conversion/CMakeLists.txt 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +set(TARGET llama-logits) +add_executable(${TARGET} logits.cpp) +install(TARGETS ${TARGET} RUNTIME) +target_link_libraries(${TARGET} PRIVATE common llama ${CMAKE_THREAD_LIBS_INIT}) +target_compile_features(${TARGET} PRIVATE cxx_std_17) diff -pruN 5882+dfsg-2/examples/model-conversion/Makefile 6641+dfsg-2/examples/model-conversion/Makefile --- 5882+dfsg-2/examples/model-conversion/Makefile 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/Makefile 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,211 @@ +MAKEFLAGS += --no-print-directory + +define validate_model_path + @if [ -z "$(MODEL_PATH)" ]; then \ + echo "Error: MODEL_PATH must be provided either as:"; \ + echo " 1. Environment variable: export MODEL_PATH=/path/to/model"; \ + echo " 2. Command line argument: make $(1) MODEL_PATH=/path/to/model"; \ + exit 1; \ + fi +endef + +define validate_embedding_model_path + @if [ -z "$(EMBEDDING_MODEL_PATH)" ]; then \ + echo "Error: EMBEDDING_MODEL_PATH must be provided either as:"; \ + echo " 1. Environment variable: export EMBEDDING_MODEL_PATH=/path/to/model"; \ + echo " 2. Command line argument: make $(1) EMBEDDING_MODEL_PATH=/path/to/model"; \ + exit 1; \ + fi +endef + +define quantize_model + @CONVERTED_MODEL="$(1)" QUANTIZED_TYPE="$(QUANTIZED_TYPE)" \ + TOKEN_EMBD_TYPE="$(TOKEN_EMBD_TYPE)" OUTPUT_TYPE="$(OUTPUT_TYPE)" \ + ./scripts/utils/quantize.sh "$(1)" "$(QUANTIZED_TYPE)" "$(TOKEN_EMBD_TYPE)" "$(OUTPUT_TYPE)" + @echo "Export the quantized model path to $(2) variable in your environment" +endef + +### +### Casual Model targets/recipes +### +causal-convert-model-bf16: OUTTYPE=bf16 +causal-convert-model-bf16: causal-convert-model + +causal-convert-model: + $(call validate_model_path,causal-convert-model) + @MODEL_NAME="$(MODEL_NAME)" OUTTYPE="$(OUTTYPE)" MODEL_PATH="$(MODEL_PATH)" \ + METADATA_OVERRIDE="$(METADATA_OVERRIDE)" \ + ./scripts/causal/convert-model.sh + +causal-convert-mm-model-bf16: OUTTYPE=bf16 +causal-convert-mm-model-bf16: MM_OUTTYPE=f16 +causal-convert-mm-model-bf16: causal-convert-mm-model + +causal-convert-mm-model: + $(call validate_model_path,causal-convert-mm-model) + @MODEL_NAME="$(MODEL_NAME)" OUTTYPE="$(OUTTYPE)" MODEL_PATH="$(MODEL_PATH)" \ + METADATA_OVERRIDE="$(METADATA_OVERRIDE)" \ + ./scripts/causal/convert-model.sh + + @MODEL_NAME="$(MODEL_NAME)" OUTTYPE="$(MM_OUTTYPE)" MODEL_PATH="$(MODEL_PATH)" \ + METADATA_OVERRIDE="$(METADATA_OVERRIDE)" \ + ./scripts/causal/convert-model.sh --mmproj + +causal-run-original-model: + $(call validate_model_path,causal-run-original-model) + @MODEL_PATH="$(MODEL_PATH)" ./scripts/causal/run-org-model.py + +causal-run-converted-model: + @CONVERTED_MODEL="$(CONVERTED_MODEL)" ./scripts/causal/run-converted-model.sh + +causal-verify-logits: causal-run-original-model causal-run-converted-model + @./scripts/causal/compare-logits.py + @MODEL_PATH="$(MODEL_PATH)" ./scripts/utils/check-nmse.py -m ${MODEL_PATH} + +causal-run-original-embeddings: + @./scripts/causal/run-casual-gen-embeddings-org.py + +causal-run-converted-embeddings: + @./scripts/causal/run-converted-model-embeddings-logits.sh + +causal-verify-embeddings: causal-run-original-embeddings causal-run-converted-embeddings + @./scripts/causal/compare-embeddings-logits.sh + +causal-inspect-original-model: + @./scripts/utils/inspect-org-model.py + +causal-inspect-converted-model: + @./scripts/utils/inspect-converted-model.sh + +causal-start-embedding-server: + @./scripts/utils/run-embedding-server.sh ${CONVERTED_MODEL} + +causal-curl-embedding-endpoint: causal-run-original-embeddings + @./scripts/utils/curl-embedding-server.sh | ./scripts/causal/compare-embeddings-logits.sh + +causal-quantize-Q8_0: QUANTIZED_TYPE = Q8_0 +causal-quantize-Q8_0: causal-quantize-model + +causal-quantize-Q4_0: QUANTIZED_TYPE = Q4_0 +causal-quantize-Q4_0: causal-quantize-model + +# For Quantization Aware Trained (QAT) models in Q4_0 we explicitly set the +# token embedding and output types to Q8_0 instead of the default Q6_K. +causal-quantize-qat-Q4_0: QUANTIZED_TYPE = Q4_0 +causal-quantize-qat-Q4_0: TOKEN_EMBD_TYPE = Q8_0 +causal-quantize-qat-Q4_0: OUTPUT_TYPE = Q8_0 +causal-quantize-qat-Q4_0: causal-quantize-model + +causal-quantize-model: + $(call quantize_model,$(CONVERTED_MODEL),QUANTIZED_MODEL) + +causal-run-quantized-model: + @QUANTIZED_MODEL="$(QUANTIZED_MODEL)" ./scripts/causal/run-converted-model.sh ${QUANTIZED_MODEL} + + +### +### Embedding Model targets/recipes +### + +embedding-convert-model-bf16: OUTTYPE=bf16 +embedding-convert-model-bf16: embedding-convert-model + +embedding-convert-model: + $(call validate_embedding_model_path,embedding-convert-model) + @MODEL_NAME="$(MODEL_NAME)" OUTTYPE="$(OUTTYPE)" MODEL_PATH="$(EMBEDDING_MODEL_PATH)" \ + METADATA_OVERRIDE="$(METADATA_OVERRIDE)" \ + ./scripts/embedding/convert-model.sh + +embedding-run-original-model: + $(call validate_embedding_model_path,embedding-run-original-model) + @EMBEDDING_MODEL_PATH="$(EMBEDDING_MODEL_PATH)" \ + ./scripts/embedding/run-original-model.py \ + $(if $(PROMPTS_FILE),--prompts-file "$(PROMPTS_FILE)") + +embedding-run-converted-model: + @./scripts/embedding/run-converted-model.sh $(CONVERTED_EMBEDDING_MODEL) \ + $(if $(PROMPTS_FILE),--prompts-file "$(PROMPTS_FILE)") + +embedding-verify-logits: embedding-run-original-model embedding-run-converted-model + @./scripts/embedding/compare-embeddings-logits.sh \ + $(if $(PROMPTS_FILE),--prompts-file "$(PROMPTS_FILE)") + +embedding-inspect-original-model: + $(call validate_embedding_model_path,embedding-inspect-original-model) + @EMBEDDING_MODEL_PATH="$(EMBEDDING_MODEL_PATH)" ./scripts/utils/inspect-org-model.py -m ${EMBEDDING_MODEL_PATH} + +embedding-inspect-converted-model: + @CONVERTED_EMBEDDING_MODEL="$(CONVERTED_EMBEDDING_MODEL)" ./scripts/utils/inspect-converted-model.sh ${CONVERTED_EMBEDDING_MODEL} + +embedding-start-embedding-server: + @./scripts/utils/run-embedding-server.sh ${CONVERTED_EMBEDDING_MODEL} + +embedding-curl-embedding-endpoint: + @./scripts/utils/curl-embedding-server.sh | ./scripts/embedding/compare-embeddings-logits.sh + +embedding-quantize-Q8_0: QUANTIZED_TYPE = Q8_0 +embedding-quantize-Q8_0: embedding-quantize-model + +embedding-quantize-Q4_0: QUANTIZED_TYPE = Q4_0 +embedding-quantize-Q4_0: embedding-quantize-model + +# For Quantization Aware Trained (QAT) models in Q4_0 we explicitly set the +# token embedding and output types to Q8_0 instead of the default Q6_K. +embedding-quantize-qat-Q4_0: QUANTIZED_TYPE = Q4_0 +embedding-quantize-qat-Q4_0: TOKEN_EMBD_TYPE = Q8_0 +embedding-quantize-qat-Q4_0: OUTPUT_TYPE = Q8_0 +embedding-quantize-qat-Q4_0: embedding-quantize-model + +embedding-quantize-model: + $(call quantize_model,$(CONVERTED_EMBEDDING_MODEL),QUANTIZED_EMBEDDING_MODEL) + +embedding-run-quantized-model: + @./scripts/embedding/run-converted-model.sh $(QUANTIZED_EMBEDDING_MODEL) \ + $(if $(PROMPTS_FILE),--prompts-file "$(PROMPTS_FILE)") + +### +### Perplexity targets/recipes +### +perplexity-data-gen: + CONVERTED_MODEL="$(CONVERTED_MODEL)" ./scripts/utils/perplexity-gen.sh + +perplexity-run-full: + QUANTIZED_MODEL="$(QUANTIZED_MODEL)" LOOGITS_FILE="$(LOGITS_FILE)" \ + ./scripts/utils/perplexity-run.sh + +perplexity-run: + QUANTIZED_MODEL="$(QUANTIZED_MODEL)" ./scripts/utils/perplexity-run-simple.sh + +### +### HuggingFace targets/recipes +### + +hf-create-model: + @./scripts/utils/hf-create-model.py -m "${MODEL_NAME}" -ns "${NAMESPACE}" -b "${ORIGINAL_BASE_MODEL}" + +hf-create-model-dry-run: + @./scripts/utils/hf-create-model.py -m "${MODEL_NAME}" -ns "${NAMESPACE}" -b "${ORIGINAL_BASE_MODEL}" -d + +hf-create-model-embedding: + @./scripts/utils/hf-create-model.py -m "${MODEL_NAME}" -ns "${NAMESPACE}" -b "${ORIGINAL_BASE_MODEL}" -e + +hf-create-model-embedding-dry-run: + @./scripts/utils/hf-create-model.py -m "${MODEL_NAME}" -ns "${NAMESPACE}" -b "${ORIGINAL_BASE_MODEL}" -e -d + +hf-create-model-private: + @./scripts/utils/hf-create-model.py -m "${MODEL_NAME}" -ns "${NAMESPACE}" -b "${ORIGINAL_BASE_MODEL}" -p + +hf-upload-gguf-to-model: + @./scripts/utils/hf-upload-gguf-model.py -m "${MODEL_PATH}" -r "${REPO_ID}" -o "${NAME_IN_REPO}" + +hf-create-collection: + @./scripts/utils/hf-create-collection.py -n "${NAME}" -d "${DESCRIPTION}" -ns "${NAMESPACE}" + +hf-add-model-to-collection: + @./scripts/utils/hf-add-model-to-collection.py -c "${COLLECTION}" -m "${MODEL}" + + +.PHONY: clean +clean: + @${RM} -rf data .converted_embedding_model.txt .converted_model.txt .embedding_model_name.txt .model_name.txt + diff -pruN 5882+dfsg-2/examples/model-conversion/README.md 6641+dfsg-2/examples/model-conversion/README.md --- 5882+dfsg-2/examples/model-conversion/README.md 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,367 @@ +# Model Conversion Example +This directory contains scripts and code to help in the process of converting +HuggingFace PyTorch models to GGUF format. + +The motivation for having this is that the conversion process can often be an +iterative process, where the original model is inspected, converted, updates +made to llama.cpp, converted again, etc. Once the model has been converted it +needs to be verified against the original model, and then optionally quantified, +and in some cases perplexity checked of the quantized model. And finally the +model/models need to the ggml-org on Hugging Face. This tool/example tries to +help with this process. + +### Overview +The idea is that the makefile targets and scripts here can be used in the +development/conversion process assisting with things like: + +* inspect/run the original model to figure out how it works +* convert the original model to GGUF format +* inspect/run the converted model +* verify the logits produced by the original model and the converted model +* quantize the model to GGUF format +* run perplexity evaluation to verify that the quantized model is performing + as expected +* upload the model to HuggingFace to make it available for others + +## Setup +Create virtual python environment +```console +$ python3.11 -m venv venv +$ source venv/bin/activate +(venv) $ pip install -r requirements.txt +``` + +## Causal Language Model Conversion +This section describes the steps to convert a causal language model to GGUF and +to verify that the conversion was successful. + +### Download the original model +First, clone the original model to some local directory: +```console +$ mkdir models && cd models +$ git clone https://huggingface.co/user/model_name +$ cd model_name +$ git lfs install +$ git lfs pull +``` + +### Set the MODEL_PATH +The path to the downloaded model can be provided in two ways: + +**Option 1: Environment variable (recommended for iterative development)** +```console +export MODEL_PATH=~/work/ai/models/some_model +``` + +**Option 2: Command line argument (for one-off tasks)** +```console +make causal-convert-model MODEL_PATH=~/work/ai/models/some_model +``` + +Command line arguments take precedence over environment variables when both are provided. + +In cases where the transformer implementation for the model has not been released +yet it is possible to set the environment variable `UNRELEASED_MODEL_NAME` which +will then cause the transformer implementation to be loaded explicitely and not +use AutoModelForCausalLM: +``` +export UNRELEASED_MODEL_NAME=SomeNewModel +``` + +### Inspecting the original tensors +```console +# Using environment variable +(venv) $ make causal-inspect-original-model + +# Or using command line argument +(venv) $ make causal-inspect-original-model MODEL_PATH=~/work/ai/models/some_model +``` + +### Running the original model +This is mainly to verify that the original model works, and to compare the output +from the converted model. +```console +# Using environment variable +(venv) $ make causal-run-original-model + +# Or using command line argument +(venv) $ make causal-run-original-model MODEL_PATH=~/work/ai/models/some_model +``` +This command will save two files to the `data` directory, one is a binary file +containing logits which will be used for comparison with the converted model +later, and the other is a text file which allows for manual visual inspection. + +### Model conversion +After updates have been made to [gguf-py](../../gguf-py) to add support for the +new model, the model can be converted to GGUF format using the following command: +```console +# Using environment variable +(venv) $ make causal-convert-model + +# Or using command line argument +(venv) $ make causal-convert-model MODEL_PATH=~/work/ai/models/some_model +``` + +### Inspecting the converted model +The converted model can be inspected using the following command: +```console +(venv) $ make causal-inspect-converted-model +``` + +### Running the converted model +```console +(venv) $ make causal-run-converted-model +``` + +### Model logits verfication +The following target will run the original model and the converted model and +compare the logits: +```console +(venv) $ make causal-verify-logits +``` + +### Quantizing the model +The causal model can be quantized to GGUF format using the following command: +```console +(venv) $ make causal-quantize-Q8_0 +Quantized model saved to: /path/to/quantized/model-Q8_0.gguf +Export the quantized model path to QUANTIZED_MODEL variable in your environment +``` +This will show the path to the quantized model in the terminal, which can then +be used to set the `QUANTIZED_MODEL` environment variable: +```console +export QUANTIZED_MODEL=/path/to/quantized/model-Q8_0.gguf +``` +Then the quantized model can be run using the following command: +```console +(venv) $ make causal-run-quantized-model +``` + +### Quantizing QAT (Quantization Aware Training) models +When quantizing to `Q4_0`, the default data type for the token embedding weights +will be `Q6_K`. For models that are going to be uploaded to ggml-org it is +recommended to use `Q8_0` instead for the embeddings and output tensors. +The reason is that although `Q6_K` is smaller in size, it requires more compute +to unpack, which can hurt performance during output generation when the entire +embedding matrix must be dequantized to compute vocabulary logits. `Q8_0` +provides practically full quality with better computational efficiency. +```console +(venv) $ make causal-quantize-qat-Q4_0 +``` + + +## Embedding Language Model Conversion + +### Download the original model +```console +$ mkdir models && cd models +$ git clone https://huggingface.co/user/model_name +$ cd model_name +$ git lfs install +$ git lfs pull +``` + +The path to the embedding model can be provided in two ways: + +**Option 1: Environment variable (recommended for iterative development)** +```console +export EMBEDDING_MODEL_PATH=~/path/to/embedding_model +``` + +**Option 2: Command line argument (for one-off tasks)** +```console +make embedding-convert-model EMBEDDING_MODEL_PATH=~/path/to/embedding_model +``` + +Command line arguments take precedence over environment variables when both are provided. + +### Running the original model +This is mainly to verify that the original model works and to compare the output +with the output from the converted model. +```console +# Using environment variable +(venv) $ make embedding-run-original-model + +# Or using command line argument +(venv) $ make embedding-run-original-model EMBEDDING_MODEL_PATH=~/path/to/embedding_model +``` +This command will save two files to the `data` directory, one is a binary +file containing logits which will be used for comparison with the converted +model, and the other is a text file which allows for manual visual inspection. + +### Model conversion +After updates have been made to [gguf-py](../../gguf-py) to add support for the +new model the model can be converted to GGUF format using the following command: +```console +(venv) $ make embedding-convert-model +``` + +### Run the converted model +```console +(venv) $ make embedding-run-converted-model +``` + +### Model logits verfication +The following target will run the original model and the converted model (which +was done manually in the previous steps) and compare the logits: +```console +(venv) $ make embedding-verify-logits +``` + +### llama-server verification +To verify that the converted model works with llama-server, the following +command can be used: +```console +(venv) $ make embedding-start-embedding-server +``` +Then open another terminal and set the `EMBEDDINGS_MODEL_PATH` environment +variable as this will not be inherited by the new terminal: +```console +(venv) $ make embedding-curl-embedding-endpoint +``` +This will call the `embedding` endpoing and the output will be piped into +the same verification script as used by the target `embedding-verify-logits`. + +The causal model can also be used to produce embeddings and this can be verified +using the following commands: +```console +(venv) $ make causal-start-embedding-server +``` +Then open another terminal and set the `MODEL_PATH` environment +variable as this will not be inherited by the new terminal: +```console +(venv) $ make casual-curl-embedding-endpoint +``` + +### Quantizing the model +The embedding model can be quantized to GGUF format using the following command: +```console +(venv) $ make embedding-quantize-Q8_0 +Quantized model saved to: /path/to/quantized/model-Q8_0.gguf +Export the quantized model path to QUANTIZED_EMBEDDING_MODEL variable in your environment +``` +This will show the path to the quantized model in the terminal, which can then +be used to set the `QUANTIZED_EMBEDDING_MODEL` environment variable: +```console +export QUANTIZED_EMBEDDING_MODEL=/path/to/quantized/model-Q8_0.gguf +``` +Then the quantized model can be run using the following command: +```console +(venv) $ make embedding-run-quantized-model +``` + +### Quantizing QAT (Quantization Aware Training) models +When quantizing to `Q4_0`, the default data type for the token embedding weights +will be `Q6_K`. For models that are going to be uploaded to ggml-org it is +recommended to use `Q8_0` instead for the embeddings and output tensors. +The reason is that although `Q6_K` is smaller in size, it requires more compute +to unpack, which can hurt performance during output generation when the entire +embedding matrix must be dequantized to compute vocabulary logits. `Q8_0` +provides practically full quality with better computational efficiency. +```console +(venv) $ make embedding-quantize-qat-Q4_0 +``` + +## Perplexity Evaluation + +### Simple perplexity evaluation +This allows to run the perplexity evaluation without having to generate a +token/logits file: +```console +(venv) $ make perplexity-run QUANTIZED_MODEL=~/path/to/quantized/model.gguf +``` +This will use the wikitext dataset to run the perplexity evaluation and +output the perplexity score to the terminal. This value can then be compared +with the perplexity score of the unquantized model. + +### Full perplexity evaluation +First use the converted, non-quantized, model to generate the perplexity evaluation +dataset using the following command: +```console +$ make perplexity-data-gen CONVERTED_MODEL=~/path/to/converted/model.gguf +``` +This will generate a file in the `data` directory named after the model and with +a `.kld` suffix which contains the tokens and the logits for the wikitext dataset. + +After the dataset has been generated, the perplexity evaluation can be run using +the quantized model: +```console +$ make perplexity-run-full QUANTIZED_MODEL=~/path/to/quantized/model-Qxx.gguf LOGITS_FILE=data/model.gguf.ppl +``` + +> 📝 **Note:** The `LOGITS_FILE` is the file generated by the previous command +> can be very large, so make sure you have enough disk space available. + +## HuggingFace utilities +The following targets are useful for creating collections and model repositories +on Hugging Face in the the ggml-org. These can be used when preparing a relase +to script the process for new model releases. + +For the following targets a `HF_TOKEN` environment variable is required. + +> 📝 **Note:** Don't forget to logout from Hugging Face after running these +> commands, otherwise you might have issues pulling/cloning repositories as +> the token will still be in use: +> $ huggingface-cli logout +> $ unset HF_TOKEN + +### Create a new Hugging Face Model (model repository) +This will create a new model repsository on Hugging Face with the specified +model name. +```console +(venv) $ make hf-create-model MODEL_NAME='TestModel' NAMESPACE="danbev" ORIGINAL_BASE_MODEL="some-base-model" +Repository ID: danbev/TestModel-GGUF +Repository created: https://huggingface.co/danbev/TestModel-GGUF +``` +Note that we append a `-GGUF` suffix to the model name to ensure a consistent +naming convention for GGUF models. + +An embedding model can be created using the following command: +```console +(venv) $ make hf-create-model-embedding MODEL_NAME='TestEmbeddingModel' NAMESPACE="danbev" ORIGINAL_BASE_MODEL="some-base-model" +``` +The only difference is that the model card for an embedding model will be different +with regards to the llama-server command and also how to access/call the embedding +endpoint. + +### Upload a GGUF model to model repository +The following target uploads a model to an existing Hugging Face model repository. +```console +(venv) $ make hf-upload-gguf-to-model MODEL_PATH=dummy-model1.gguf REPO_ID=danbev/TestModel-GGUF +📤 Uploading dummy-model1.gguf to danbev/TestModel-GGUF/dummy-model1.gguf +✅ Upload successful! +🔗 File available at: https://huggingface.co/danbev/TestModel-GGUF/blob/main/dummy-model1.gguf +``` +This command can also be used to update an existing model file in a repository. + +### Create a new Collection +```console +(venv) $ make hf-new-collection NAME=TestCollection DESCRIPTION="Collection for testing scripts" NAMESPACE=danbev +🚀 Creating Hugging Face Collection +Title: TestCollection +Description: Collection for testing scripts +Namespace: danbev +Private: False +✅ Authenticated as: danbev +📚 Creating collection: 'TestCollection'... +✅ Collection created successfully! +📋 Collection slug: danbev/testcollection-68930fcf73eb3fc200b9956d +🔗 Collection URL: https://huggingface.co/collections/danbev/testcollection-68930fcf73eb3fc200b9956d + +🎉 Collection created successfully! +Use this slug to add models: danbev/testcollection-68930fcf73eb3fc200b9956d +``` + +### Add model to a Collection +```console +(venv) $ make hf-add-model-to-collection COLLECTION=danbev/testcollection-68930fcf73eb3fc200b9956d MODEL=danbev/TestModel-GGUF +✅ Authenticated as: danbev +🔍 Checking if model exists: danbev/TestModel-GGUF +✅ Model found: danbev/TestModel-GGUF +📚 Adding model to collection... +✅ Model added to collection successfully! +🔗 Collection URL: https://huggingface.co/collections/danbev/testcollection-68930fcf73eb3fc200b9956d + +🎉 Model added successfully! + +``` diff -pruN 5882+dfsg-2/examples/model-conversion/logits.cpp 6641+dfsg-2/examples/model-conversion/logits.cpp --- 5882+dfsg-2/examples/model-conversion/logits.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/logits.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,240 @@ +#include "llama.h" +#include +#include +#include +#include +#include +#include + +static void print_usage(int, char ** argv) { + printf("\nexample usage:\n"); + printf("\n %s -m model.gguf [-ngl n_gpu_layers] -embd-mode [prompt]\n", argv[0]); + printf("\n"); +} + +int main(int argc, char ** argv) { + std::string model_path; + std::string prompt = "Hello, my name is"; + int ngl = 0; + bool embedding_mode = false; + + { + int i = 1; + for (; i < argc; i++) { + if (strcmp(argv[i], "-m") == 0) { + if (i + 1 < argc) { + model_path = argv[++i]; + } else { + print_usage(argc, argv); + return 1; + } + } else if (strcmp(argv[i], "-ngl") == 0) { + if (i + 1 < argc) { + try { + ngl = std::stoi(argv[++i]); + } catch (...) { + print_usage(argc, argv); + return 1; + } + } else { + print_usage(argc, argv); + return 1; + } + } else if (strcmp(argv[i], "-embd-mode") == 0) { + if (i + 1 < argc) { + try { + embedding_mode = true; + } catch (...) { + print_usage(argc, argv); + return 1; + } + } else { + print_usage(argc, argv); + return 1; + } + } else { + // prompt starts here + break; + } + } + + if (model_path.empty()) { + print_usage(argc, argv); + return 1; + } + + if (i < argc) { + prompt = argv[i++]; + for (; i < argc; i++) { + prompt += " "; + prompt += argv[i]; + } + } + } + + ggml_backend_load_all(); + llama_model_params model_params = llama_model_default_params(); + model_params.n_gpu_layers = ngl; + + llama_model * model = llama_model_load_from_file(model_path.c_str(), model_params); + + if (model == NULL) { + fprintf(stderr , "%s: error: unable to load model\n" , __func__); + return 1; + } + + // Extract basename from model_path + const char * basename = strrchr(model_path.c_str(), '/'); + basename = (basename == NULL) ? model_path.c_str() : basename + 1; + + char model_name[256]; + strncpy(model_name, basename, 255); + model_name[255] = '\0'; + + char * dot = strrchr(model_name, '.'); + if (dot != NULL && strcmp(dot, ".gguf") == 0) { + *dot = '\0'; + } + printf("Model name: %s\n", model_name); + + const llama_vocab * vocab = llama_model_get_vocab(model); + const int n_prompt = -llama_tokenize(vocab, prompt.c_str(), prompt.size(), NULL, 0, true, true); + + std::vector prompt_tokens(n_prompt); + if (llama_tokenize(vocab, prompt.c_str(), prompt.size(), prompt_tokens.data(), prompt_tokens.size(), true, true) < 0) { + fprintf(stderr, "%s: error: failed to tokenize the prompt\n", __func__); + return 1; + } + + llama_context_params ctx_params = llama_context_default_params(); + ctx_params.n_ctx = n_prompt; + ctx_params.n_batch = n_prompt; + ctx_params.no_perf = false; + if (embedding_mode) { + ctx_params.embeddings = true; + ctx_params.pooling_type = LLAMA_POOLING_TYPE_NONE; + ctx_params.n_ubatch = ctx_params.n_batch; + } + + llama_context * ctx = llama_init_from_model(model, ctx_params); + if (ctx == NULL) { + fprintf(stderr , "%s: error: failed to create the llama_context\n" , __func__); + return 1; + } + + printf("Input prompt: \"%s\"\n", prompt.c_str()); + printf("Tokenized prompt (%d tokens): ", n_prompt); + for (auto id : prompt_tokens) { + char buf[128]; + int n = llama_token_to_piece(vocab, id, buf, sizeof(buf), 0, true); + if (n < 0) { + fprintf(stderr, "%s: error: failed to convert token to piece\n", __func__); + return 1; + } + std::string s(buf, n); + printf("%s", s.c_str()); + } + printf("\n"); + + llama_batch batch = llama_batch_get_one(prompt_tokens.data(), prompt_tokens.size()); + + if (llama_decode(ctx, batch)) { + fprintf(stderr, "%s : failed to eval\n", __func__); + return 1; + } + + float * logits; + int n_logits; + const char * type; + + if (embedding_mode) { + logits = llama_get_embeddings(ctx); + n_logits = llama_model_n_embd(model) * batch.n_tokens; + type = "-embeddings"; + + const int n_embd = llama_model_n_embd(model); + const int n_embd_count = batch.n_tokens; + + printf("Embedding dimension: %d\n", n_embd); + printf("\n"); + + // Print embeddings in the specified format + for (int j = 0; j < n_embd_count; j++) { + printf("embedding %d: ", j); + + // Print first 3 values + for (int i = 0; i < 3 && i < n_embd; i++) { + printf("%9.6f ", logits[j * n_embd + i]); + } + + printf(" ... "); + + // Print last 3 values + for (int i = n_embd - 3; i < n_embd; i++) { + if (i >= 0) { + printf("%9.6f ", logits[j * n_embd + i]); + } + } + + printf("\n"); + } + printf("\n"); + + printf("Embeddings size: %d\n", n_logits); + } else { + logits = llama_get_logits_ith(ctx, batch.n_tokens - 1); + n_logits = llama_vocab_n_tokens(vocab); + type = ""; + printf("Vocab size: %d\n", n_logits); + } + + std::filesystem::create_directory("data"); + + // Save logits to binary file + char bin_filename[512]; + snprintf(bin_filename, sizeof(bin_filename), "data/llamacpp-%s%s.bin", model_name, type); + printf("Saving logits to %s\n", bin_filename); + + FILE * f = fopen(bin_filename, "wb"); + if (f == NULL) { + fprintf(stderr, "%s: error: failed to open binary output file\n", __func__); + return 1; + } + fwrite(logits, sizeof(float), n_logits, f); + fclose(f); + + // Also save as text for debugging + char txt_filename[512]; + snprintf(txt_filename, sizeof(txt_filename), "data/llamacpp-%s%s.txt", model_name, type); + f = fopen(txt_filename, "w"); + if (f == NULL) { + fprintf(stderr, "%s: error: failed to open text output file\n", __func__); + return 1; + } + for (int i = 0; i < n_logits; i++) { + fprintf(f, "%d: %.6f\n", i, logits[i]); + } + fclose(f); + + if (!embedding_mode) { + printf("First 10 logits: "); + for (int i = 0; i < 10 && i < n_logits; i++) { + printf("%.6f ", logits[i]); + } + printf("\n"); + + printf("Last 10 logits: "); + for (int i = n_logits - 10; i < n_logits; i++) { + if (i >= 0) printf("%.6f ", logits[i]); + } + printf("\n\n"); + } + + printf("Logits saved to %s\n", bin_filename); + printf("Logits saved to %s\n", txt_filename); + + llama_free(ctx); + llama_model_free(model); + + return 0; +} diff -pruN 5882+dfsg-2/examples/model-conversion/requirements.txt 6641+dfsg-2/examples/model-conversion/requirements.txt --- 5882+dfsg-2/examples/model-conversion/requirements.txt 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/requirements.txt 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,6 @@ +--extra-index-url https://download.pytorch.org/whl/cpu +torch +torchvision +transformers +huggingface-hub +accelerate diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/compare-embeddings-logits.sh 6641+dfsg-2/examples/model-conversion/scripts/causal/compare-embeddings-logits.sh --- 5882+dfsg-2/examples/model-conversion/scripts/causal/compare-embeddings-logits.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/compare-embeddings-logits.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,43 @@ +#!/usr/bin/env bash + +set -e + +MODEL_PATH="${1:-"$MODEL_PATH"}" +MODEL_NAME="${2:-$(basename "$MODEL_PATH")}" + +if [ -t 0 ]; then + CPP_EMBEDDINGS="data/llamacpp-${MODEL_NAME}-embeddings.bin" +else + # Process piped JSON data and convert to binary (matching logits.cpp format) + TEMP_FILE=$(mktemp /tmp/tmp.XXXXXX.binn) + python3 -c " +import json +import sys +import struct + +data = json.load(sys.stdin) + +# Flatten all embeddings completely +flattened = [] +for item in data: + embedding = item['embedding'] + for token_embedding in embedding: + flattened.extend(token_embedding) + +print(f'Total embedding values: {len(flattened)}', file=sys.stderr) + +# Write as binary floats - matches logitc.cpp fwrite format +with open('$TEMP_FILE', 'wb') as f: + for value in flattened: + f.write(struct.pack('f', value)) +" + CPP_EMBEDDINGS="$TEMP_FILE" + trap "rm -f $TEMP_FILE" EXIT +fi + +python scripts/utils/semantic_check.py --model-path $MODEL_PATH \ + --python-embeddings data/pytorch-${MODEL_NAME}-embeddings.bin \ + --cpp-embeddings $CPP_EMBEDDINGS \ + --prompt "Hello world today" \ + --causal + diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/compare-logits.py 6641+dfsg-2/examples/model-conversion/scripts/causal/compare-logits.py --- 5882+dfsg-2/examples/model-conversion/scripts/causal/compare-logits.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/compare-logits.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,88 @@ +#!/usr/bin/env python3 + +import numpy as np +import sys +import os +from pathlib import Path + +def quick_logits_check(pytorch_file, llamacpp_file): + """Lightweight sanity check before NMSE""" + + try: + pytorch_logits = np.fromfile(pytorch_file, dtype=np.float32) + llamacpp_logits = np.fromfile(llamacpp_file, dtype=np.float32) + except Exception as e: + print(f"❌ NOK: Failed to load files - {e}") + return False + + # Check shapes match + if pytorch_logits.shape != llamacpp_logits.shape: + print(f"❌ NOK: Shape mismatch - PyTorch: {pytorch_logits.shape}, llama.cpp: {llamacpp_logits.shape}") + return False + + # Calculate key metrics + diff = pytorch_logits - llamacpp_logits + abs_diff = np.abs(diff) + max_diff = np.max(abs_diff) + + # Get top 10 predictions from both models + pytorch_top10 = np.argsort(pytorch_logits)[-10:][::-1] + llamacpp_top10 = np.argsort(llamacpp_logits)[-10:][::-1] + print(f"Top 10 PyTorch logits: {pytorch_logits[pytorch_top10]}") + print(f"Top 10 llama.cpp logits: {llamacpp_logits[llamacpp_top10]}") + print(f"Max absolute difference: {max_diff:.4f}") + + if max_diff > 1.0: + print(f"❌ NOK: Large differences detected - max diff: {max_diff:.4f}") + return False + + return True + +def main(): + model_path = os.getenv('MODEL_PATH') + if not model_path: + print("Error: MODEL_PATH environment variable not set") + sys.exit(1) + + if not os.path.exists(model_path): + print(f"Error: Model file not found: {model_path}") + sys.exit(1) + + model_name = os.path.basename(model_path) + data_dir = Path("data") + + pytorch_file = data_dir / f"pytorch-{model_name}.bin" + llamacpp_file = data_dir / f"llamacpp-{model_name}.bin" + + if not pytorch_file.exists(): + print(f"Error: PyTorch logits file not found: {pytorch_file}") + print("Please run scripts/run-org-model.sh first to generate this file.") + sys.exit(1) + + if not llamacpp_file.exists(): + print(f"Error: llama.cpp logits file not found: {llamacpp_file}") + print("Please run scripts/run-converted-model.sh first to generate this file.") + sys.exit(1) + + print("Checked all required files were found. Proceeding...\n") + + + print("🔍 GGML Model Validation for model ", model_name) + print("=" * 40) + print(f"PyTorch logits : {pytorch_file}") + print(f"llama.cpp logits: {llamacpp_file}") + print() + + success = quick_logits_check(pytorch_file, llamacpp_file) + + # Exit with appropriate code + if success: + print("✅ OK: Lightweight model check successful!") + print(" Ok to proceed with NMSE check...") + sys.exit(0) + else: + print(f"❌ NOK: Top 10 predictions don't match - generation will differ") + sys.exit(1) + +if __name__ == "__main__": + main() diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/convert-model.sh 6641+dfsg-2/examples/model-conversion/scripts/causal/convert-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/causal/convert-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/convert-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,46 @@ +#!/usr/bin/env bash + +set -e + +# Parse command line arguments +MMPROJ="" +while [[ $# -gt 0 ]]; do + case $1 in + --mmproj) + MMPROJ="--mmproj" + shift + ;; + *) + shift + ;; + esac +done + +MODEL_NAME="${MODEL_NAME:-$(basename "$MODEL_PATH")}" +OUTPUT_DIR="${OUTPUT_DIR:-../../models}" +TYPE="${OUTTYPE:-f16}" +METADATA_OVERRIDE="${METADATA_OVERRIDE:-}" +CONVERTED_MODEL="${OUTPUT_DIR}/${MODEL_NAME}.gguf" + +echo "Model path: ${MODEL_PATH}" +echo "Model name: ${MODEL_NAME}" +echo "Data type: ${TYPE}" +echo "Converted model path:: ${CONVERTED_MODEL}" +echo "Metadata override: ${METADATA_OVERRIDE}" + +CMD_ARGS=("python" "../../convert_hf_to_gguf.py" "--verbose") +CMD_ARGS+=("${MODEL_PATH}") +CMD_ARGS+=("--outfile" "${CONVERTED_MODEL}") +CMD_ARGS+=("--outtype" "${TYPE}") +[[ -n "$METADATA_OVERRIDE" ]] && CMD_ARGS+=("--metadata" "${METADATA_OVERRIDE}") +[[ -n "$MMPROJ" ]] && CMD_ARGS+=("${MMPROJ}") + +"${CMD_ARGS[@]}" + +echo "" +echo "The environment variable CONVERTED_MODEL can be set to this path using:" +echo "export CONVERTED_MODEL=$(realpath ${CONVERTED_MODEL})" +if [[ -n "$MMPROJ" ]]; then + mmproj_file="${OUTPUT_DIR}/mmproj-$(basename "${CONVERTED_MODEL}")" + echo "The mmproj model was created in $(realpath "$mmproj_file")" +fi diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/modelcard.template 6641+dfsg-2/examples/model-conversion/scripts/causal/modelcard.template --- 5882+dfsg-2/examples/model-conversion/scripts/causal/modelcard.template 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/modelcard.template 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,13 @@ +--- +base_model: +- {base_model} +--- +# {model_name} GGUF + +Recommended way to run this model: + +```sh +llama-server -hf {namespace}/{model_name}-GGUF -c 0 -fa +``` + +Then, access http://localhost:8080 diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/run-casual-gen-embeddings-org.py 6641+dfsg-2/examples/model-conversion/scripts/causal/run-casual-gen-embeddings-org.py --- 5882+dfsg-2/examples/model-conversion/scripts/causal/run-casual-gen-embeddings-org.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/run-casual-gen-embeddings-org.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 + +import argparse +import os +import importlib +import torch +import numpy as np + +from transformers import AutoTokenizer, AutoConfig, AutoModelForCausalLM +from pathlib import Path + +unreleased_model_name = os.getenv('UNRELEASED_MODEL_NAME') + +parser = argparse.ArgumentParser(description='Process model with specified path') +parser.add_argument('--model-path', '-m', help='Path to the model') +args = parser.parse_args() + +model_path = os.environ.get('MODEL_PATH', args.model_path) +if model_path is None: + parser.error("Model path must be specified either via --model-path argument or MODEL_PATH environment variable") + +config = AutoConfig.from_pretrained(model_path) + +print("Model type: ", config.model_type) +print("Vocab size: ", config.vocab_size) +print("Hidden size: ", config.hidden_size) +print("Number of layers: ", config.num_hidden_layers) +print("BOS token id: ", config.bos_token_id) +print("EOS token id: ", config.eos_token_id) + +print("Loading model and tokenizer using AutoTokenizer:", model_path) +tokenizer = AutoTokenizer.from_pretrained(model_path) + +if unreleased_model_name: + model_name_lower = unreleased_model_name.lower() + unreleased_module_path = f"transformers.models.{model_name_lower}.modular_{model_name_lower}" + class_name = f"{unreleased_model_name}ForCausalLM" + print(f"Importing unreleased model module: {unreleased_module_path}") + + try: + model_class = getattr(importlib.import_module(unreleased_module_path), class_name) + model = model_class.from_pretrained(model_path) + except (ImportError, AttributeError) as e: + print(f"Failed to import or load model: {e}") + print("Falling back to AutoModelForCausalLM") + model = AutoModelForCausalLM.from_pretrained(model_path) +else: + model = AutoModelForCausalLM.from_pretrained(model_path) +print(f"Model class: {type(model)}") +#print(f"Model file: {type(model).__module__}") + +model_name = os.path.basename(model_path) +print(f"Model name: {model_name}") + +prompt = "Hello world today" +input_ids = tokenizer(prompt, return_tensors="pt").input_ids +print(f"Input tokens: {input_ids}") +print(f"Input text: {repr(prompt)}") +print(f"Tokenized: {tokenizer.convert_ids_to_tokens(input_ids[0])}") + +with torch.no_grad(): + outputs = model(input_ids, output_hidden_states=True) + + # Extract hidden states from the last layer + # outputs.hidden_states is a tuple of (num_layers + 1) tensors + # Index -1 gets the last layer, shape: [batch_size, seq_len, hidden_size] + last_hidden_states = outputs.hidden_states[-1] + + # Get embeddings for all tokens + token_embeddings = last_hidden_states[0].cpu().numpy() # Remove batch dimension + + print(f"Hidden states shape: {last_hidden_states.shape}") + print(f"Token embeddings shape: {token_embeddings.shape}") + print(f"Hidden dimension: {token_embeddings.shape[-1]}") + print(f"Number of tokens: {token_embeddings.shape[0]}") + + # Save raw token embeddings + data_dir = Path("data") + data_dir.mkdir(exist_ok=True) + bin_filename = data_dir / f"pytorch-{model_name}-embeddings.bin" + txt_filename = data_dir / f"pytorch-{model_name}-embeddings.txt" + + # Save all token embeddings as binary + print(token_embeddings) + token_embeddings.astype(np.float32).tofile(bin_filename) + + # Save as text for inspection + with open(txt_filename, "w") as f: + for i, embedding in enumerate(token_embeddings): + for j, val in enumerate(embedding): + f.write(f"{i} {j} {val:.6f}\n") + + # Print embeddings per token in the requested format + print("\nToken embeddings:") + tokens = tokenizer.convert_ids_to_tokens(input_ids[0]) + for i, embedding in enumerate(token_embeddings): + # Format: show first few values, ..., then last few values + if len(embedding) > 10: + # Show first 3 and last 3 values with ... in between + first_vals = " ".join(f"{val:8.6f}" for val in embedding[:3]) + last_vals = " ".join(f"{val:8.6f}" for val in embedding[-3:]) + print(f"embedding {i}: {first_vals} ... {last_vals}") + else: + # If embedding is short, show all values + vals = " ".join(f"{val:8.6f}" for val in embedding) + print(f"embedding {i}: {vals}") + + # Also show token info for reference + print(f"\nToken reference:") + for i, token in enumerate(tokens): + print(f" Token {i}: {repr(token)}") + + print(f"Saved bin logits to: {bin_filename}") + print(f"Saved txt logist to: {txt_filename}") diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model-embeddings-logits.sh 6641+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model-embeddings-logits.sh --- 5882+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model-embeddings-logits.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model-embeddings-logits.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,18 @@ +#!/usr/bin/env bash + +set -e + +# First try command line argument, then environment variable, then file +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +cmake --build ../../build --target llama-logits -j8 + +../../build/bin/llama-logits -m $CONVERTED_MODEL -embd-mode "Hello world today" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model.sh 6641+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/run-converted-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,20 @@ +#!/usr/bin/env bash + +set -e + +# First try command line argument, then environment variable, then file +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +echo $CONVERTED_MODEL + +cmake --build ../../build --target llama-logits -j8 + +../../build/bin/llama-logits -m "$CONVERTED_MODEL" "Hello, my name is" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/causal/run-org-model.py 6641+dfsg-2/examples/model-conversion/scripts/causal/run-org-model.py --- 5882+dfsg-2/examples/model-conversion/scripts/causal/run-org-model.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/causal/run-org-model.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,231 @@ +#!/usr/bin/env python3 + +import argparse +import os +import importlib +from pathlib import Path + +from transformers import AutoTokenizer, AutoModelForCausalLM, AutoConfig +import torch +import numpy as np + +### If you want to dump RoPE activations, apply this monkey patch to the model +### class from Transformers that you are running (replace apertus.modeling_apertus +### with the proper package and class for your model +### === START ROPE DEBUG === +# from transformers.models.apertus.modeling_apertus import apply_rotary_pos_emb + +# orig_rope = apply_rotary_pos_emb +# torch.set_printoptions(threshold=float('inf')) +# torch.set_printoptions(precision=6, sci_mode=False) + +# def debug_rope(q, k, cos, sin, position_ids=None, unsqueeze_dim=1): +# # log inputs +# summarize(q, "RoPE.q_in") +# summarize(k, "RoPE.k_in") + +# # call original +# q_out, k_out = orig_rope(q, k, cos, sin, position_ids, unsqueeze_dim) + +# # log outputs +# summarize(q_out, "RoPE.q_out") +# summarize(k_out, "RoPE.k_out") + +# return q_out, k_out + +# # Patch it +# import transformers.models.apertus.modeling_apertus as apertus_mod # noqa: E402 +# apertus_mod.apply_rotary_pos_emb = debug_rope +### == END ROPE DEBUG === + + +def summarize(tensor: torch.Tensor, name: str, max_seq: int = 3, max_vals: int = 3): + """ + Print a tensor in llama.cpp debug style. + + Supports: + - 2D tensors (seq, hidden) + - 3D tensors (batch, seq, hidden) + - 4D tensors (batch, seq, heads, dim_per_head) via flattening heads × dim_per_head + + Shows first and last max_vals of each vector per sequence position. + """ + t = tensor.detach().to(torch.float32).cpu() + + # Determine dimensions + if t.ndim == 3: + _, s, _ = t.shape + elif t.ndim == 2: + _, s = 1, t.shape[0] + t = t.unsqueeze(0) + elif t.ndim == 4: + _, s, _, _ = t.shape + else: + print(f"Skipping tensor due to unsupported dimensions: {t.ndim}") + return + + ten_shape = t.shape + + print(f"ggml_debug: {name} = (f32) ... = {{{ten_shape}}}") + print(" [") + print(" [") + + # Determine indices for first and last sequences + first_indices = list(range(min(s, max_seq))) + last_indices = list(range(max(0, s - max_seq), s)) + + # Check if there's an overlap between first and last indices or if we're at the edge case of s = 2 * max_seq + has_overlap = bool(set(first_indices) & set(last_indices)) or (max_seq * 2 == s) + + # Combine indices + if has_overlap: + # If there's overlap, just use the combined unique indices + indices = sorted(list(set(first_indices + last_indices))) + separator_index = None + else: + # If no overlap, we'll add a separator between first and last sequences + indices = first_indices + last_indices + separator_index = len(first_indices) + + for i, si in enumerate(indices): + # Add separator if needed + if separator_index is not None and i == separator_index: + print(" ...") + + # Extract appropriate slice + vec = t[0, si] + if vec.ndim == 2: # 4D case: flatten heads × dim_per_head + flat = vec.flatten().tolist() + else: # 2D or 3D case + flat = vec.tolist() + + # First and last slices + first = flat[:max_vals] + last = flat[-max_vals:] if len(flat) >= max_vals else flat + first_str = ", ".join(f"{v:12.4f}" for v in first) + last_str = ", ".join(f"{v:12.4f}" for v in last) + + print(f" [{first_str}, ..., {last_str}]") + + print(" ],") + print(" ]") + print(f" sum = {t.sum().item():.6f}\n") + + +def debug_hook(name): + def fn(_m, input, output): + if isinstance(input, torch.Tensor): + summarize(input, name + "_in") + elif isinstance(input, (tuple, list)) and isinstance(input[0], torch.Tensor): + summarize(input[0], name + "_in") + if isinstance(output, torch.Tensor): + summarize(output, name + "_out") + elif isinstance(output, (tuple, list)) and isinstance(output[0], torch.Tensor): + summarize(output[0], name + "_out") + + return fn + + +unreleased_model_name = os.getenv("UNRELEASED_MODEL_NAME") + +parser = argparse.ArgumentParser(description="Process model with specified path") +parser.add_argument("--model-path", "-m", help="Path to the model") +args = parser.parse_args() + +model_path = os.environ.get("MODEL_PATH", args.model_path) +if model_path is None: + parser.error( + "Model path must be specified either via --model-path argument or MODEL_PATH environment variable" + ) + +config = AutoConfig.from_pretrained(model_path) + +print("Model type: ", config.model_type) +print("Vocab size: ", config.vocab_size) +print("Hidden size: ", config.hidden_size) +print("Number of layers: ", config.num_hidden_layers) +print("BOS token id: ", config.bos_token_id) +print("EOS token id: ", config.eos_token_id) + +print("Loading model and tokenizer using AutoTokenizer:", model_path) +tokenizer = AutoTokenizer.from_pretrained(model_path) +config = AutoConfig.from_pretrained(model_path) + +if unreleased_model_name: + model_name_lower = unreleased_model_name.lower() + unreleased_module_path = ( + f"transformers.models.{model_name_lower}.modular_{model_name_lower}" + ) + class_name = f"{unreleased_model_name}ForCausalLM" + print(f"Importing unreleased model module: {unreleased_module_path}") + + try: + model_class = getattr( + importlib.import_module(unreleased_module_path), class_name + ) + model = model_class.from_pretrained( + model_path + ) # Note: from_pretrained, not fromPretrained + except (ImportError, AttributeError) as e: + print(f"Failed to import or load model: {e}") + exit(1) +else: + model = AutoModelForCausalLM.from_pretrained( + model_path, device_map="auto", offload_folder="offload" + ) + +for name, module in model.named_modules(): + if len(list(module.children())) == 0: # only leaf modules + module.register_forward_hook(debug_hook(name)) + +model_name = os.path.basename(model_path) +# Printing the Model class to allow for easier debugging. This can be useful +# when working with models that have not been publicly released yet and this +# migth require that the concrete class is imported and used directly instead +# of using AutoModelForCausalLM. +print(f"Model class: {model.__class__.__name__}") + +prompt = "Hello, my name is" +input_ids = tokenizer(prompt, return_tensors="pt").input_ids + +print(f"Input tokens: {input_ids}") +print(f"Input text: {repr(prompt)}") +print(f"Tokenized: {tokenizer.convert_ids_to_tokens(input_ids[0])}") + +with torch.no_grad(): + outputs = model(input_ids.to(model.device)) + logits = outputs.logits + + # Extract logits for the last token (next token prediction) + last_logits = logits[0, -1, :].cpu().numpy() + + print(f"Logits shape: {logits.shape}") + print(f"Last token logits shape: {last_logits.shape}") + print(f"Vocab size: {len(last_logits)}") + + data_dir = Path("data") + data_dir.mkdir(exist_ok=True) + bin_filename = data_dir / f"pytorch-{model_name}.bin" + txt_filename = data_dir / f"pytorch-{model_name}.txt" + + # Save to file for comparison + last_logits.astype(np.float32).tofile(bin_filename) + + # Also save as text file for easy inspection + with open(txt_filename, "w") as f: + for i, logit in enumerate(last_logits): + f.write(f"{i}: {logit:.6f}\n") + + # Print some sample logits for quick verification + print(f"First 10 logits: {last_logits[:10]}") + print(f"Last 10 logits: {last_logits[-10:]}") + + # Show top 5 predicted tokens + top_indices = np.argsort(last_logits)[-5:][::-1] + print("Top 5 predictions:") + for idx in top_indices: + token = tokenizer.decode([idx]) + print(f" Token {idx} ({repr(token)}): {last_logits[idx]:.6f}") + + print(f"Saved bin logits to: {bin_filename}") + print(f"Saved txt logist to: {txt_filename}") diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/embedding/compare-embeddings-logits.sh 6641+dfsg-2/examples/model-conversion/scripts/embedding/compare-embeddings-logits.sh --- 5882+dfsg-2/examples/model-conversion/scripts/embedding/compare-embeddings-logits.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/embedding/compare-embeddings-logits.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,81 @@ +#!/usr/bin/env bash + +set -e + +# Parse command line arguments +MODEL_PATH="" +MODEL_NAME="" +PROMPTS_FILE="" + +# First argument is always model path +if [ $# -gt 0 ] && [[ "$1" != --* ]]; then + MODEL_PATH="$1" + shift +fi + +# Parse remaining arguments +while [[ $# -gt 0 ]]; do + case $1 in + --prompts-file|-pf) + PROMPTS_FILE="$2" + shift 2 + ;; + *) + # If MODEL_NAME not set and this isn't a flag, use as model name + if [ -z "$MODEL_NAME" ] && [[ "$1" != --* ]]; then + MODEL_NAME="$1" + fi + shift + ;; + esac +done + +# Set defaults +MODEL_PATH="${MODEL_PATH:-"$EMBEDDING_MODEL_PATH"}" +MODEL_NAME="${MODEL_NAME:-$(basename "$MODEL_PATH")}" + +if [ -t 0 ]; then + CPP_EMBEDDINGS="data/llamacpp-${MODEL_NAME}-embeddings.bin" +else + # Process piped JSON data and convert to binary (matching logits.cpp format) + TEMP_FILE=$(mktemp /tmp/tmp.XXXXXX.binn) + python3 -c " +import json +import sys +import struct + +data = json.load(sys.stdin) + +# Flatten all embeddings completely +flattened = [] +for item in data: + embedding = item['embedding'] + for token_embedding in embedding: + flattened.extend(token_embedding) + +print(f'Total embedding values: {len(flattened)}', file=sys.stderr) + +# Write as binary floats - matches logitc.cpp fwrite format +with open('$TEMP_FILE', 'wb') as f: + for value in flattened: + f.write(struct.pack('f', value)) +" + CPP_EMBEDDINGS="$TEMP_FILE" + trap "rm -f $TEMP_FILE" EXIT +fi + +# Build the semantic_check.py command +SEMANTIC_CMD="python scripts/utils/semantic_check.py --model-path $MODEL_PATH \ + --python-embeddings data/pytorch-${MODEL_NAME}-embeddings.bin \ + --cpp-embeddings $CPP_EMBEDDINGS" + +# Add prompts file if specified, otherwise use default prompt +if [ -n "$PROMPTS_FILE" ]; then + SEMANTIC_CMD="$SEMANTIC_CMD --prompts-file \"$PROMPTS_FILE\"" +else + SEMANTIC_CMD="$SEMANTIC_CMD --prompt \"Hello world today\"" +fi + +# Execute the command +eval $SEMANTIC_CMD + diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/embedding/convert-model.sh 6641+dfsg-2/examples/model-conversion/scripts/embedding/convert-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/embedding/convert-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/embedding/convert-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,22 @@ +#!/usr/bin/env bash + +set -e + +MODEL_NAME="${MODEL_NAME:-$(basename "$EMBEDDING_MODEL_PATH")}" +OUTPUT_DIR="${OUTPUT_DIR:-../../models}" +TYPE="${OUTTYPE:-f16}" +METADATA_OVERRIDE="${METADATA_OVERRIDE:-}" +CONVERTED_MODEL="${OUTPUT_DIR}/${MODEL_NAME}.gguf" + +echo "Model path: ${EMBEDDING_MODEL_PATH}" +echo "Model name: ${MODEL_NAME}" +echo "Data type: ${TYPE}" +echo "Converted model path:: ${CONVERTED_MODEL}" +python ../../convert_hf_to_gguf.py --verbose \ + ${EMBEDDING_MODEL_PATH} \ + --outfile ${CONVERTED_MODEL} \ + --outtype ${TYPE} + +echo "" +echo "The environment variable CONVERTED_EMBEDDING MODEL can be set to this path using:" +echo "export CONVERTED_EMBEDDING_MODEL=$(realpath ${CONVERTED_MODEL})" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/embedding/modelcard.template 6641+dfsg-2/examples/model-conversion/scripts/embedding/modelcard.template --- 5882+dfsg-2/examples/model-conversion/scripts/embedding/modelcard.template 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/embedding/modelcard.template 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,48 @@ +--- +base_model: +- {base_model} +--- +# {model_name} GGUF + +Recommended way to run this model: + +```sh +llama-server -hf {namespace}/{model_name}-GGUF --embeddings +``` + +Then the endpoint can be accessed at http://localhost:8080/embedding, for +example using `curl`: +```console +curl --request POST \ + --url http://localhost:8080/embedding \ + --header "Content-Type: application/json" \ + --data '{{"input": "Hello embeddings"}}' \ + --silent +``` + +Alternatively, the `llama-embedding` command line tool can be used: +```sh +llama-embedding -hf {namespace}/{model_name}-GGUF --verbose-prompt -p "Hello embeddings" +``` + +#### embd_normalize +When a model uses pooling, or the pooling method is specified using `--pooling`, +the normalization can be controlled by the `embd_normalize` parameter. + +The default value is `2` which means that the embeddings are normalized using +the Euclidean norm (L2). Other options are: +* -1 No normalization +* 0 Max absolute +* 1 Taxicab +* 2 Euclidean/L2 +* \>2 P-Norm + +This can be passed in the request body to `llama-server`, for example: +```sh + --data '{{"input": "Hello embeddings", "embd_normalize": -1}}' \ +``` + +And for `llama-embedding`, by passing `--embd-normalize `, for example: +```sh +llama-embedding -hf {namespace}/{model_name}-GGUF --embd-normalize -1 -p "Hello embeddings" +``` diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/embedding/run-converted-model.sh 6641+dfsg-2/examples/model-conversion/scripts/embedding/run-converted-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/embedding/run-converted-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/embedding/run-converted-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,50 @@ +#!/usr/bin/env bash + +set -e + +# Parse command line arguments +CONVERTED_MODEL="" +PROMPTS_FILE="" + +while [[ $# -gt 0 ]]; do + case $1 in + -p|--prompts-file) + PROMPTS_FILE="$2" + shift 2 + ;; + *) + if [ -z "$CONVERTED_MODEL" ]; then + CONVERTED_MODEL="$1" + fi + shift + ;; + esac +done + +# First try command line argument, then environment variable +CONVERTED_MODEL="${CONVERTED_MODEL:-"$CONVERTED_EMBEDDING_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_EMBEDDING_MODEL environment variable" >&2 + exit 1 +fi + +# Read prompt from file or use default +if [ -n "$PROMPTS_FILE" ]; then + if [ ! -f "$PROMPTS_FILE" ]; then + echo "Error: Prompts file '$PROMPTS_FILE' not found" >&2 + exit 1 + fi + PROMPT=$(cat "$PROMPTS_FILE") +else + PROMPT="Hello world today" +fi + +echo $CONVERTED_MODEL + +cmake --build ../../build --target llama-logits -j8 +# TODO: update logits.cpp to accept a --file/-f option for the prompt +../../build/bin/llama-logits -m "$CONVERTED_MODEL" -embd-mode "$PROMPT" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/embedding/run-original-model.py 6641+dfsg-2/examples/model-conversion/scripts/embedding/run-original-model.py --- 5882+dfsg-2/examples/model-conversion/scripts/embedding/run-original-model.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/embedding/run-original-model.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,148 @@ +#!/usr/bin/env python3 + +import argparse +import os +import numpy as np +import importlib +from pathlib import Path + +from transformers import AutoTokenizer, AutoConfig, AutoModel +import torch + +unreleased_model_name = os.getenv('UNRELEASED_MODEL_NAME') + +parser = argparse.ArgumentParser(description='Process model with specified path') +parser.add_argument('--model-path', '-m', help='Path to the model') +parser.add_argument('--prompts-file', '-p', help='Path to file containing prompts (one per line)') +args = parser.parse_args() + +def read_prompt_from_file(file_path): + try: + with open(file_path, 'r', encoding='utf-8') as f: + return f.read().strip() + except FileNotFoundError: + print(f"Error: Prompts file '{file_path}' not found") + exit(1) + except Exception as e: + print(f"Error reading prompts file: {e}") + exit(1) + +model_path = os.environ.get('EMBEDDING_MODEL_PATH', args.model_path) +if model_path is None: + parser.error("Model path must be specified either via --model-path argument or EMBEDDING_MODEL_PATH environment variable") + +tokenizer = AutoTokenizer.from_pretrained(model_path) + +config = AutoConfig.from_pretrained(model_path) + +# This can be used to override the sliding window size for manual testing. This +# can be useful to verify the sliding window attention mask in the original model +# and compare it with the converted .gguf model. +if hasattr(config, 'sliding_window'): + original_sliding_window = config.sliding_window + #original_sliding_window = 6 + print(f"Modified sliding window: {original_sliding_window} -> {config.sliding_window}") + +print(f"Using unreleased model: {unreleased_model_name}") +if unreleased_model_name: + model_name_lower = unreleased_model_name.lower() + unreleased_module_path = f"transformers.models.{model_name_lower}.modular_{model_name_lower}" + class_name = f"{unreleased_model_name}Model" + print(f"Importing unreleased model module: {unreleased_module_path}") + + try: + model_class = getattr(importlib.import_module(unreleased_module_path), class_name) + model = model_class.from_pretrained(model_path, config=config) + except (ImportError, AttributeError) as e: + print(f"Failed to import or load model: {e}") + exit(1) +else: + model = AutoModel.from_pretrained(model_path, config=config) +print(f"Model class: {type(model)}") +print(f"Model file: {type(model).__module__}") + +# Verify the model is using the correct sliding window +if hasattr(model.config, 'sliding_window'): + print(f"Model's sliding_window: {model.config.sliding_window}") +else: + print("Model config does not have sliding_window attribute") + +model_name = os.path.basename(model_path) + +if args.prompts_file: + prompt_text = read_prompt_from_file(args.prompts_file) + texts = [prompt_text] +else: + texts = ["Hello world today"] + +encoded = tokenizer( + texts, + padding=True, + truncation=True, + return_tensors="pt" +) + +tokens = encoded['input_ids'][0] +token_strings = tokenizer.convert_ids_to_tokens(tokens) +for i, (token_id, token_str) in enumerate(zip(tokens, token_strings)): + print(f"{token_id:6d} -> '{token_str}'") + +with torch.no_grad(): + outputs = model(**encoded) + hidden_states = outputs.last_hidden_state # Shape: [batch_size, seq_len, hidden_size] + + # Extract embeddings for each token (matching LLAMA_POOLING_TYPE_NONE behavior) + all_embeddings = hidden_states[0].cpu().numpy() # Shape: [seq_len, hidden_size] + + print(f"Hidden states shape: {hidden_states.shape}") + print(f"All embeddings shape: {all_embeddings.shape}") + print(f"Embedding dimension: {all_embeddings.shape[1]}") + + # Print embeddings exactly like embedding.cpp does for LLAMA_POOLING_TYPE_NONE + n_embd = all_embeddings.shape[1] + n_embd_count = all_embeddings.shape[0] + + print() # Empty line to match C++ output + + for j in range(n_embd_count): + embedding = all_embeddings[j] + print(f"embedding {j}: ", end="") + + # Print first 3 values + for i in range(min(3, n_embd)): + print(f"{embedding[i]:9.6f} ", end="") + + print(" ... ", end="") + + # Print last 3 values + for i in range(n_embd - 3, n_embd): + print(f"{embedding[i]:9.6f} ", end="") + + print() # New line + + print() # Final empty line to match C++ output + + data_dir = Path("data") + data_dir.mkdir(exist_ok=True) + bin_filename = data_dir / f"pytorch-{model_name}-embeddings.bin" + txt_filename = data_dir / f"pytorch-{model_name}-embeddings.txt" + + # Save all embeddings flattened (matching what embedding.cpp would save if it did) + flattened_embeddings = all_embeddings.flatten() + flattened_embeddings.astype(np.float32).tofile(bin_filename) + + with open(txt_filename, "w") as f: + f.write(f"# Model class: {model_name}\n") + f.write(f"# Tokens: {token_strings}\n") + f.write(f"# Shape: {all_embeddings.shape}\n") + f.write(f"# n_embd_count: {n_embd_count}, n_embd: {n_embd}\n\n") + + for j in range(n_embd_count): + f.write(f"# Token {j} ({token_strings[j]}):\n") + for i, value in enumerate(all_embeddings[j]): + f.write(f"{j}_{i}: {value:.6f}\n") + f.write("\n") + print(f"Total values: {len(flattened_embeddings)} ({n_embd_count} tokens × {n_embd} dimensions)") + print("") + print(f"Saved bin embeddings to: {bin_filename}") + print(f"Saved txt embeddings to: {txt_filename}") diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/check-nmse.py 6641+dfsg-2/examples/model-conversion/scripts/utils/check-nmse.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/check-nmse.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/check-nmse.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,174 @@ +#!/usr/bin/env python3 + +import numpy as np +import sys +import os +import argparse +from pathlib import Path + +def calculate_nmse(reference, test): + mse = np.mean((test - reference) ** 2) + ref_var = np.var(reference) + if ref_var == 0: + nmse = float('inf') if mse > 0 else 0.0 + return mse, mse, ref_var + + nmse = mse / ref_var + + return nmse, mse, ref_var + +def load_logits(file_path): + if not os.path.exists(file_path): + raise FileNotFoundError(f"File not found: {file_path}") + + if file_path.suffix == '.npy': + return np.load(file_path) + elif file_path.suffix == '.bin': + return np.fromfile(file_path, dtype=np.float32) + else: + # Try to load as text file + try: + # If it has index format "0: value", extract just values + data = [] + with open(file_path, 'r') as f: + for line in f: + if ':' in line: + # Format: "index: value" + value = float(line.split(':')[1].strip()) + else: + # Just the value + value = float(line.strip()) + data.append(value) + return np.array(data, dtype=np.float32) + except: + return np.loadtxt(file_path, dtype=np.float32) + +def interpret_nmse(nmse): + """Provide interpretation of NMSE value""" + if nmse == 0: + return "Perfect match", "🎉" + elif nmse < 1e-6: + return "Essentially identical", "✅" + elif nmse < 1e-4: + return "Excellent match", "✅" + elif nmse < 1e-3: + return "Very good match", "👍" + elif nmse < 1e-2: + return "Good match", "👍" + elif nmse < 0.1: + return "Acceptable match", "⚠️" + elif nmse < 1.0: + return "Poor match", "❌" + else: + return "Very poor match (worse than noise)", "❌" + +def main(): + parser = argparse.ArgumentParser(description='Validate model logits') + parser.add_argument('-m', '--model-path', required=True, help='Path to the model directory') + args = parser.parse_args() + + model_name = os.path.basename(args.model_path) + data_dir = Path("data") + + pytorch_file = data_dir / f"pytorch-{model_name}.bin" + llamacpp_file = data_dir / f"llamacpp-{model_name}.bin" + + print(f"Model name: {model_name}") + print(f"PyTorch logits file: {pytorch_file}") + print(f"llama.cpp logits file: {llamacpp_file}") + + reference_file = pytorch_file + test_file = llamacpp_file + + print("📊 NMSE Check for Model Comparison") + print("=" * 50) + print(f"Reference (ground truth): {reference_file}") + print(f"Test (to evaluate): {test_file}") + print() + + try: + print("Loading reference logits...") + reference = load_logits(reference_file) + print(f" Shape: {reference.shape}, Type: {reference.dtype}") + + print("Loading test logits...") + test = load_logits(test_file) + print(f" Shape: {test.shape}, Type: {test.dtype}") + + # Check shapes match + if reference.shape != test.shape: + print(f"\n❌ Error: Shape mismatch!") + print(f" Reference: {reference.shape}") + print(f" Test: {test.shape}") + sys.exit(1) + + print(f"\n✅ Shapes match: {reference.shape}") + + nmse, mse, ref_var = calculate_nmse(reference, test) + + # Additional metrics + max_abs_error = np.max(np.abs(test - reference)) + mean_abs_error = np.mean(np.abs(test - reference)) + + # Results + print(f"\n📈 METRICS") + print("=" * 30) + print(f"MSE (Mean Squared Error): {mse:.6e}") + print(f"Reference Variance: {ref_var:.6e}") + print(f"NMSE: {nmse:.6e}") + print(f"Max Absolute Error: {max_abs_error:.6f}") + print(f"Mean Absolute Error: {mean_abs_error:.6f}") + + # NMSE in dB (common in signal processing) + if nmse > 0: + nmse_db = 10 * np.log10(nmse) + print(f"NMSE (dB): {nmse_db:.2f} dB") + + # Interpretation + interpretation, emoji = interpret_nmse(nmse) + print(f"\n🎯 INTERPRETATION") + print("=" * 30) + print(f"{emoji} {interpretation}") + + # Detailed guidance + print(f"\n📋 GUIDANCE") + print("=" * 30) + if nmse < 1e-3: + print("✅ EXCELLENT: Your GGML conversion is working very well!") + print(" The differences are negligible for practical use.") + elif nmse < 1e-2: + print("👍 GOOD: Your GGML conversion is working well.") + print(" Small differences are likely due to precision/quantization.") + elif nmse < 0.1: + print("⚠️ ACCEPTABLE: Conversion is working but with some differences.") + print(" Check if you're using quantization (Q4, Q8, etc.)") + print(" Test generation quality to see if it's acceptable.") + else: + print("❌ PROBLEMATIC: Large differences detected.") + print(" Check your conversion process for potential issues.") + print(" Verify you're using the same model weights.") + + # NMSE benchmarks + print(f"\n📚 NMSE BENCHMARKS") + print("=" * 30) + print("< 1e-6: Essentially identical") + print("< 1e-4: Excellent (typical for good conversions)") + print("< 1e-3: Very good") + print("< 1e-2: Good (acceptable for most use cases)") + print("< 0.1: Acceptable (may need verification)") + print("> 1.0: Poor (worse than random)") + + # Exit code based on NMSE + if nmse < 1e-2: + print(f"\n✅ RESULT: PASS (NMSE = {nmse:.2e})") + sys.exit(0) + else: + print(f"\n❌ RESULT: NEEDS REVIEW (NMSE = {nmse:.2e})") + sys.exit(1) + + except Exception as e: + print(f"❌ Error: {e}") + sys.exit(1) + +if __name__ == "__main__": + main() diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/create-collection-add-model.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/create-collection-add-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/create-collection-add-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/create-collection-add-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,8 @@ + +#!/usr/bin/env bash + +COLLECTION_SLUG=$(python ./create_collection.py --return-slug) +echo "Created collection: $COLLECTION_SLUG" + +# Use it in the next command +python add_model_to_collection.py "$COLLECTION_SLUG" "username/my-model" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/curl-embedding-server.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/curl-embedding-server.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/curl-embedding-server.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/curl-embedding-server.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,6 @@ +#!/usr/bin/env bash +curl --request POST \ + --url http://localhost:8080/embedding \ + --header "Content-Type: application/json" \ + --data '{"input": "Hello world today"}' \ + --silent diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-add-model-to-collection.py 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-add-model-to-collection.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-add-model-to-collection.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-add-model-to-collection.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,80 @@ +#!/usr/bin/env python3 + +from huggingface_hub import HfApi +import argparse +import sys + +def add_model_to_collection(collection_slug, model_id, note=""): + """ + Add a model to an existing collection + + Args: + collection_slug: The slug of the collection (e.g., "username/collection-name-12345") + model_id: The model repository ID (e.g., "username/model-name") + note: Optional note about the model + + Returns: + True if successful, False if failed + """ + + # Initialize API + api = HfApi() + + try: + user_info = api.whoami() + print(f"✅ Authenticated as: {user_info['name']}") + + # Verify the model exists + print(f"🔍 Checking if model exists: {model_id}") + try: + model_info = api.model_info(model_id) + except Exception as e: + print(f"❌ Model not found or not accessible: {model_id}") + print(f"Error: {e}") + return False + + print(f"📚 Adding model to collection...") + api.add_collection_item( + collection_slug=collection_slug, + item_id=model_id, + item_type="model", + note=note + ) + + print(f"✅ Model added to collection successfully!") + print(f"🔗 Collection URL: https://huggingface.co/collections/{collection_slug}") + + return True + + except Exception as e: + print(f"❌ Error adding model to collection: {e}") + return False + +def main(): + # This script requires that the environment variable HF_TOKEN is set with your + # Hugging Face API token. + api = HfApi() + + parser = argparse.ArgumentParser(description='Add model to a Huggingface Collection') + parser.add_argument('--collection', '-c', help='The collection slug username/collection-hash', required=True) + parser.add_argument('--model', '-m', help='The model to add to the Collection', required=True) + parser.add_argument('--note', '-n', help='An optional note/description', required=False) + args = parser.parse_args() + + collection = args.collection + model = args.model + note = args.note + + success = add_model_to_collection( + collection_slug=collection, + model_id=model, + note=note + ) + + if success: + print("\n🎉 Model added successfully!") + else: + print("\n❌ Failed to add model to collection") + sys.exit(1) +if __name__ == "__main__": + main() diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-create-collection.py 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-create-collection.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-create-collection.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-create-collection.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 + +from huggingface_hub import HfApi +import argparse +import os +import sys + + +def create_collection(title, description, private=False, namespace=None, return_slug=False): + """ + Create a new collection on Hugging Face + + Args: + title: Collection title + description: Collection description + private: Whether the collection should be private (default: False) + namespace: Optional namespace (defaults to your username) + + Returns: + Collection object if successful, None if failed + """ + + # Check if HF_TOKEN is available + token = os.getenv("HF_TOKEN") or os.getenv("HUGGINGFACE_HUB_TOKEN") + if not token: + print("❌ No HF_TOKEN or HUGGINGFACE_HUB_TOKEN found in environment variables") + print("Please set your Hugging Face token as an environment variable") + return None + + # Initialize API + api = HfApi() + + try: + # Test authentication first + user_info = api.whoami() + if not return_slug: + print(f"✅ Authenticated as: {user_info['name']}") + + # Create the collection + if not return_slug: + print(f"📚 Creating collection: '{title}'...") + collection = api.create_collection( + title=title, + description=description, + private=private, + namespace=namespace + ) + + if not return_slug: + print(f"✅ Collection created successfully!") + print(f"📋 Collection slug: {collection.slug}") + print(f"🔗 Collection URL: https://huggingface.co/collections/{collection.slug}") + + return collection + + except Exception as e: + print(f"❌ Error creating collection: {e}") + return None + +def main(): + # This script requires that the environment variable HF_TOKEN is set with your + # Hugging Face API token. + api = HfApi() + + parser = argparse.ArgumentParser(description='Create a Huggingface Collection') + parser.add_argument('--name', '-n', help='The name/title of the Collection', required=True) + parser.add_argument('--description', '-d', help='The description for the Collection', required=True) + parser.add_argument('--namespace', '-ns', help='The namespace to add the Collection to', required=True) + parser.add_argument('--private', '-p', help='Create a private Collection', action='store_true') # Fixed + parser.add_argument('--return-slug', '-s', help='Only output the collection slug', action='store_true') # Fixed + + args = parser.parse_args() + + name = args.name + description = args.description + private = args.private + namespace = args.namespace + return_slug = args.return_slug + + if not return_slug: + print("🚀 Creating Hugging Face Collection") + print(f"Title: {name}") + print(f"Description: {description}") + print(f"Namespace: {namespace}") + print(f"Private: {private}") + + collection = create_collection( + title=name, + description=description, + private=private, + namespace=namespace, + return_slug=return_slug + ) + + if collection: + if return_slug: + print(collection.slug) + else: + print("\n🎉 Collection created successfully!") + print(f"Use this slug to add models: {collection.slug}") + else: + print("\n❌ Failed to create collection") + sys.exit(1) + +if __name__ == "__main__": + main() diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-create-model.py 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-create-model.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-create-model.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-create-model.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,78 @@ +#!/usr/bin/env python3 + +from huggingface_hub import HfApi +import argparse + +# This script requires that the environment variable HF_TOKEN is set with your +# Hugging Face API token. +api = HfApi() + +def load_template_and_substitute(template_path, **kwargs): + try: + with open(template_path, 'r', encoding='utf-8') as f: + template_content = f.read() + + return template_content.format(**kwargs) + except FileNotFoundError: + print(f"Template file '{template_path}' not found!") + return None + except KeyError as e: + print(f"Missing template variable: {e}") + return None + +parser = argparse.ArgumentParser(description='Create a new Hugging Face model repository') +parser.add_argument('--model-name', '-m', help='Name for the model', required=True) +parser.add_argument('--namespace', '-ns', help='Namespace to add the model to', required=True) +parser.add_argument('--org-base-model', '-b', help='Original Base model name', default="") +parser.add_argument('--no-card', action='store_true', help='Skip creating model card') +parser.add_argument('--private', '-p', action='store_true', help='Create private model') +parser.add_argument('--embedding', '-e', action='store_true', help='Use embedding model card template') +parser.add_argument('--dry-run', '-d', action='store_true', help='Print repository info and template without creating repository') + +args = parser.parse_args() + +repo_id = f"{args.namespace}/{args.model_name}-GGUF" +print("Repository ID: ", repo_id) + +repo_url = None +if not args.dry_run: + repo_url = api.create_repo( + repo_id=repo_id, + repo_type="model", + private=args.private, + exist_ok=False + ) + +if not args.no_card: + if args.embedding: + template_path = "scripts/embedding/modelcard.template" + else: + template_path = "scripts/causal/modelcard.template" + + print("Template path: ", template_path) + + model_card_content = load_template_and_substitute( + template_path, + model_name=args.model_name, + namespace=args.namespace, + base_model=args.org_base_model, + ) + + if args.dry_run: + print("\nTemplate Content:\n") + print(model_card_content) + else: + if model_card_content: + api.upload_file( + path_or_fileobj=model_card_content.encode('utf-8'), + path_in_repo="README.md", + repo_id=repo_id + ) + print("Model card created successfully.") + else: + print("Failed to create model card.") + +if not args.dry_run and repo_url: + print(f"Repository created: {repo_url}") + + diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-upload-gguf-model.py 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-upload-gguf-model.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/hf-upload-gguf-model.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/hf-upload-gguf-model.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 + +from huggingface_hub import HfApi +import argparse +import os + +def upload_gguf_file(local_file_path, repo_id, filename_in_repo=None): + """ + Upload a GGUF file to a Hugging Face model repository + + Args: + local_file_path: Path to your local GGUF file + repo_id: Your repository ID (e.g., "username/model-name") + filename_in_repo: Optional custom name for the file in the repo + """ + + if not os.path.exists(local_file_path): + print(f"❌ File not found: {local_file_path}") + return False + + if filename_in_repo is None: + filename_in_repo = os.path.basename(local_file_path) + + if filename_in_repo is None or filename_in_repo == "": + filename_in_repo = os.path.basename(local_file_path) + + print(f"📤 Uploading {local_file_path} to {repo_id}/{filename_in_repo}") + + api = HfApi() + + try: + api.upload_file( + path_or_fileobj=local_file_path, + path_in_repo=filename_in_repo, + repo_id=repo_id, + repo_type="model", + commit_message=f"Upload {filename_in_repo}" + ) + + print("✅ Upload successful!") + print(f"🔗 File available at: https://huggingface.co/{repo_id}/blob/main/{filename_in_repo}") + return True + + except Exception as e: + print(f"❌ Upload failed: {e}") + return False + +# This script requires that the environment variable HF_TOKEN is set with your +# Hugging Face API token. +api = HfApi() + +parser = argparse.ArgumentParser(description='Upload a GGUF model to a Huggingface model repository') +parser.add_argument('--gguf-model-path', '-m', help='The GGUF model file to upload', required=True) +parser.add_argument('--repo-id', '-r', help='The repository to upload to', required=True) +parser.add_argument('--name', '-o', help='The name in the model repository', required=False) +args = parser.parse_args() + +upload_gguf_file(args.gguf_model_path, args.repo_id, args.name) diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/inspect-converted-model.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/inspect-converted-model.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/inspect-converted-model.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/inspect-converted-model.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +# First try command line argument, then environment variable, then file +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +../../gguf-py/gguf/scripts/gguf_dump.py $CONVERTED_MODEL diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/inspect-org-model.py 6641+dfsg-2/examples/model-conversion/scripts/utils/inspect-org-model.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/inspect-org-model.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/inspect-org-model.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,67 @@ +#!/usr/bin/env python3 + +import argparse +import os +import json +from safetensors import safe_open +from collections import defaultdict + +parser = argparse.ArgumentParser(description='Process model with specified path') +parser.add_argument('--model-path', '-m', help='Path to the model') +args = parser.parse_args() + +model_path = os.environ.get('MODEL_PATH', args.model_path) +if model_path is None: + parser.error("Model path must be specified either via --model-path argument or MODEL_PATH environment variable") + +# Check if there's an index file (multi-file model) +index_path = os.path.join(model_path, "model.safetensors.index.json") +single_file_path = os.path.join(model_path, "model.safetensors") + +if os.path.exists(index_path): + # Multi-file model + print("Multi-file model detected") + + with open(index_path, 'r') as f: + index_data = json.load(f) + + # Get the weight map (tensor_name -> file_name) + weight_map = index_data.get("weight_map", {}) + + # Group tensors by file for efficient processing + file_tensors = defaultdict(list) + for tensor_name, file_name in weight_map.items(): + file_tensors[file_name].append(tensor_name) + + print("Tensors in model:") + + # Process each shard file + for file_name, tensor_names in file_tensors.items(): + file_path = os.path.join(model_path, file_name) + print(f"\n--- From {file_name} ---") + + with safe_open(file_path, framework="pt") as f: + for tensor_name in sorted(tensor_names): + tensor = f.get_tensor(tensor_name) + print(f"- {tensor_name} : shape = {tensor.shape}, dtype = {tensor.dtype}") + +elif os.path.exists(single_file_path): + # Single file model (original behavior) + print("Single-file model detected") + + with safe_open(single_file_path, framework="pt") as f: + keys = f.keys() + print("Tensors in model:") + for key in sorted(keys): + tensor = f.get_tensor(key) + print(f"- {key} : shape = {tensor.shape}, dtype = {tensor.dtype}") + +else: + print(f"Error: Neither 'model.safetensors.index.json' nor 'model.safetensors' found in {model_path}") + print("Available files:") + if os.path.exists(model_path): + for item in sorted(os.listdir(model_path)): + print(f" {item}") + else: + print(f" Directory {model_path} does not exist") + exit(1) diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-gen.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-gen.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-gen.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-gen.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,35 @@ +#!/usr/bin/env bash + +set -e + +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +# Check if data/wikitext-2-raw directory exists +if [ ! -d "ppl/wikitext-2-raw" ]; then + echo "ppl/wikitext-2-raw directory does not exist. Downloading..." >&2 + mkdir -p ppl + pushd ppl + ./../../../scripts/get-wikitext-2.sh + popd +fi + +mkdir -p ppl +OUTPUTFILE="ppl/$(basename $CONVERTED_MODEL).kld" +echo "Model: $CONVERTED_MODEL" + +cmake --build ../../build --target llama-perplexity -j8 + +../.././build/bin/llama-perplexity -m $CONVERTED_MODEL \ + -f ppl/wikitext-2-raw/wiki.test.raw \ + --kl-divergence-base $OUTPUTFILE + +echo "Generated logits in $OUTPUTFILE" + diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run-simple.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run-simple.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run-simple.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run-simple.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,27 @@ +#!/usr/bin/env bash + +set -e + +QUANTIZED_MODEL="${1:-"$QUANTIZED_MODEL"}" + +if [ -z "$QUANTIZED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. QUANTIZED_MODEL environment variable" >&2 + exit 1 +fi + +# Check if data/wikitext-2-raw directory exists +if [ ! -d "ppl/wikitext-2-raw" ]; then + echo "ppl/wikitext-2-raw directory does not exist. Downloading..." >&2 + mkdir -p ppl + pushd ppl + ./../../../scripts/get-wikitext-2.sh + popd +fi + +cmake --build ../../build --target llama-perplexity -j8 + +../.././build/bin/llama-perplexity -m $QUANTIZED_MODEL -f ppl/wikitext-2-raw/wiki.test.raw + + diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/perplexity-run.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,28 @@ +#!/usr/bin/env bash + +set -e + +QUANTIZED_MODEL="${1:-"$QUANTIZED_MODEL"}" +LOGITS_FILE="${1:-"$LOGITS_FILE"}" + +if [ -z "$QUANTIZED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. QUANTIZED_MODEL environment variable" >&2 + exit 1 +fi + +if [ ! -f ${LOGITS_FILE} ]; then + echo "Error: logits file '${LOGITS_FILE} was not found" + echo "Did you run the perplexity-gen.sh script?" + exit 1 +fi + +echo "Model: $QUANTIZED_MODEL" +echo "Data file: $LOGITS_FILE" + +cmake --build ../../build --target llama-perplexity -j8 + +../.././build/bin/llama-perplexity -m $QUANTIZED_MODEL \ + --kl-divergence-base $LOGITS_FILE \ + --kl-divergence diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/quantize.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/quantize.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/quantize.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/quantize.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,48 @@ +#!/usr/bin/env bash + +set -e + +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" +QUANTIZED_TYPE="${2:-"$QUANTIZED_TYPE"}" +TOKEN_EMBD_TYPE="${3:-"${TOKEN_EMBD_TYPE}"}" +OUTPUT_TYPE="${4:-"${OUTPUT_TYPE}"}" +QUANTIZED_MODEL=$CONVERTED_MODEL + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +if [ -z "$QUANTIZED_TYPE" ]; then + echo "Error: QUANTIZED_TYPE is required" >&2 + exit 1 +fi + +echo $CONVERTED_MODEL + +# Process the quantized model filename +if [[ "$QUANTIZED_MODEL" == *.gguf ]]; then + # Remove .gguf suffix, add quantized type, then add .gguf back + BASE_NAME="${QUANTIZED_MODEL%.gguf}" + QUANTIZED_MODEL="${BASE_NAME}-${QUANTIZED_TYPE}.gguf" +else + echo "Error: QUANTIZED_MODEL must end with .gguf extension" >&2 + exit 1 +fi + +cmake --build ../../build --target llama-quantize -j8 + +echo $TOKEN_EMBD_TYPE +echo $OUTPUT_TYPE + +CMD_ARGS=("../../build/bin/llama-quantize") +[[ -n "$TOKEN_EMBD_TYPE" ]] && CMD_ARGS+=("--token-embedding-type" "$TOKEN_EMBD_TYPE") +[[ -n "$OUTPUT_TYPE" ]] && CMD_ARGS+=("--output-tensor-type" "$OUTPUT_TYPE") +CMD_ARGS+=("$CONVERTED_MODEL" "$QUANTIZED_MODEL" "$QUANTIZED_TYPE") + +"${CMD_ARGS[@]}" + +echo "Quantized model saved to: $QUANTIZED_MODEL" diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/run-embedding-server.sh 6641+dfsg-2/examples/model-conversion/scripts/utils/run-embedding-server.sh --- 5882+dfsg-2/examples/model-conversion/scripts/utils/run-embedding-server.sh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/run-embedding-server.sh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,22 @@ +#!/usr/bin/env bash + +set -e +# +# First try command line argument, then environment variable, then file +CONVERTED_MODEL="${1:-"$CONVERTED_MODEL"}" + +# Final check if we have a model path +if [ -z "$CONVERTED_MODEL" ]; then + echo "Error: Model path must be provided either as:" >&2 + echo " 1. Command line argument" >&2 + echo " 2. CONVERTED_MODEL environment variable" >&2 + exit 1 +fi + +echo $CONVERTED_MODEL + +cmake --build ../../build --target llama-server + +../../build/bin/llama-server -m $CONVERTED_MODEL \ + --embedding \ + --pooling none diff -pruN 5882+dfsg-2/examples/model-conversion/scripts/utils/semantic_check.py 6641+dfsg-2/examples/model-conversion/scripts/utils/semantic_check.py --- 5882+dfsg-2/examples/model-conversion/scripts/utils/semantic_check.py 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/examples/model-conversion/scripts/utils/semantic_check.py 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 + +import numpy as np +import argparse +import os +import importlib + +from transformers import AutoTokenizer, AutoConfig, AutoModelForCausalLM, AutoModel + +unreleased_model_name = os.getenv('UNRELEASED_MODEL_NAME') + +def cosine_similarity(a, b=None): + a = np.asarray(a) + if b is None: + b = a + else: + b = np.asarray(b) + + if a.ndim == 1: + a = a.reshape(1, -1) + if b.ndim == 1: + b = b.reshape(1, -1) + + a_norms = np.linalg.norm(a, axis=1, keepdims=True) + b_norms = np.linalg.norm(b, axis=1, keepdims=True) + + a_norms = np.where(a_norms == 0, 1e-8, a_norms) + b_norms = np.where(b_norms == 0, 1e-8, b_norms) + + a_normalized = a / a_norms + b_normalized = b / b_norms + + # Compute cosine similarity + return np.dot(a_normalized, b_normalized.T) + +def load_embeddings_from_file(filename, n_tokens, n_embd): + embeddings = np.fromfile(filename, dtype=np.float32) + return embeddings.reshape(n_tokens, n_embd) + +def test_single_prompt_similarity(python_emb, cpp_emb, tokens, prompt): + np.set_printoptions(suppress=True, precision=6) + print("pytorch embeddings:"); + print(python_emb) + print("llama.cpp embeddings:"); + print(cpp_emb) + print(f"\n=== Prompt: '{prompt}' ===") + print(f"Tokens: {tokens}") + print(f"Embeddings shape: Python {python_emb.shape}, llama.cpp {cpp_emb.shape}") + + n_tokens = len(tokens) + + # 1. Direct embedding comparison + print(f"\n1. Raw Embedding Magnitude Comparison:") + # Check if the distance of each token embedding from the origin and compare + # if the vectors are on the same "sphere". This does not tell us about + # direction (meaning of the token embedding), just magnitude. + for i in range(n_tokens): + py_mag = np.linalg.norm(python_emb[i]) # calculate standard euclidean norm for Python embeddings + cpp_mag = np.linalg.norm(cpp_emb[i]) # calculate standard euclidean norm for llama.cpp embeddings + ratio = py_mag / cpp_mag if cpp_mag > 0 else float('inf') + print(f" Token {i} ({tokens[i]}): Python={py_mag:.3f}, llama.cpp={cpp_mag:.3f}, ratio={ratio:.3f}") + + # 2. Cosine similarity between tokens within each model + # Here we check the direction of token embeddings to see if the have the + # same meaning (similarity). This is done by calculating cosine similarity + # of a pair of token embeddings within each model. + print(f"\n2. Within-Model Token Similarities:") + print(" Python model:") + for i in range(n_tokens): + for j in range(i+1, n_tokens): + sim = cosine_similarity([python_emb[i]], [python_emb[j]])[0][0] + print(f" {tokens[i]} ↔ {tokens[j]}: {sim:.4f}") + + print(" llama.cpp model:") + for i in range(n_tokens): + for j in range(i+1, n_tokens): + sim = cosine_similarity([cpp_emb[i]], [cpp_emb[j]])[0][0] + print(f" {tokens[i]} ↔ {tokens[j]}: {sim:.4f}") + + # 3. Cross-model similarity (same token position) + print(f"\n3. Cross-Model Same-Token Similarities:") + for i in range(n_tokens): + sim = cosine_similarity([python_emb[i]], [cpp_emb[i]])[0][0] + print(f" Token {i} ({tokens[i]}): {sim:.4f}") + + # 4. Similarity matrix comparison + print(f"\n4. Similarity Matrix Differences:") + py_sim_matrix = cosine_similarity(python_emb) + cpp_sim_matrix = cosine_similarity(cpp_emb) + diff_matrix = np.abs(py_sim_matrix - cpp_sim_matrix) + + print(f" Max difference: {np.max(diff_matrix):.4f}") + print(f" Mean difference: {np.mean(diff_matrix):.4f}") + print(f" RMS difference: {np.sqrt(np.mean(diff_matrix**2)):.4f}") + + return { + 'cross_model_similarities': [cosine_similarity([python_emb[i]], [cpp_emb[i]])[0][0] for i in range(n_tokens)], + 'similarity_matrix_diff': diff_matrix, + 'max_diff': np.max(diff_matrix), + 'mean_diff': np.mean(diff_matrix), + 'rms_diff': np.sqrt(np.mean(diff_matrix**2)) + } + +def read_prompt_from_file(file_path): + try: + with open(file_path, 'r', encoding='utf-8') as f: + return f.read().strip() + except FileNotFoundError: + print(f"Error: Prompts file '{file_path}' not found") + exit(1) + except Exception as e: + print(f"Error reading prompts file: {e}") + exit(1) + +def main(): + parser = argparse.ArgumentParser(description='Test semantic similarity between Python and llama.cpp embeddings') + parser.add_argument('--model-path', '-m', required=True, help='Path to the original Python model') + parser.add_argument('--python-embeddings', '-pe', help='Path to pytorch embeddings "logits" binary file') + parser.add_argument('--cpp-embeddings', '-ce', help='Path to llama.cpp embeddings "logits" binary file') + parser.add_argument('--causal', '-c', default=False, help='if the model is causal (default: false)', action='store_true') + parser.add_argument('--prompt', '-p', default='Hello world today', help='Test prompt') + parser.add_argument('--prompts-file', '-pf', help='Path to file containing prompts') + + args = parser.parse_args() + + if args.prompts_file: + prompt = read_prompt_from_file(args.prompts_file) + else: + prompt = args.prompt + + print("Semantic Similarity Test Between Python and llama.cpp Embedding Models") + print("=" * 70) + + # Single prompt detailed comparison + print(f"\nTesting with prompt: '{prompt}'") + + # Load the python model to get configuration information and also to load the tokenizer. + print("Loading model and tokenizer using AutoTokenizer:", args.model_path) + tokenizer = AutoTokenizer.from_pretrained(args.model_path) + config = AutoConfig.from_pretrained(args.model_path) + + if unreleased_model_name: + model_name_lower = unreleased_model_name.lower() + unreleased_module_path = f"transformers.models.{model_name_lower}.modular_{model_name_lower}" + if args.causal: + class_name = f"{unreleased_model_name}ForCausalLM" + else: + class_name = f"{unreleased_model_name}Model" + print(f"Model class: {class_name}") + print(f"Importing unreleased model module: {unreleased_module_path}") + + try: + model_class = getattr(importlib.import_module(unreleased_module_path), class_name) + model = model_class.from_pretrained(args.model_path) + except (ImportError, AttributeError) as e: + print(f"Failed to import or load model: {e}") + exit(1) + else: + if args.causal: + model = AutoModelForCausalLM.from_pretrained(args.model_path) + else: + model = AutoModel.from_pretrained(args.model_path) + + encoded = tokenizer(prompt, return_tensors="pt") + tokens = tokenizer.convert_ids_to_tokens(encoded['input_ids'][0]) + n_tokens = len(tokens) + print(f"n_tokens: {n_tokens}"); + print(f"hidden_size: {model.config.hidden_size}") + + # Load binary embeddings from data directory. + llamacpp_embeddings = load_embeddings_from_file(args.cpp_embeddings, n_tokens, model.config.hidden_size) + python_embeddings = load_embeddings_from_file(args.python_embeddings, n_tokens, model.config.hidden_size) + + # Run comparison + results = test_single_prompt_similarity(python_embeddings, llamacpp_embeddings, tokens, prompt) + + # Summary + print(f"\n=== SUMMARY ===") + avg_cross_sim = np.mean(results['cross_model_similarities']) + print(f"Average cross-model similarity: {avg_cross_sim:.4f}") + print(f"Similarity matrix RMS difference: {results['rms_diff']:.4f}") + + # Quality assessment + if avg_cross_sim > 0.95: + print("✅ EXCELLENT: Models are highly similar") + elif avg_cross_sim > 0.90: + print("✅ VERY GOOD: Models are very similar") + elif avg_cross_sim > 0.80: + print("⚠️ GOOD: Models are reasonably similar") + elif avg_cross_sim > 0.70: + print("⚠️ FAIR: Models have some differences") + else: + print("❌ POOR: Models are significantly different") + +if __name__ == "__main__": + main() diff -pruN 5882+dfsg-2/examples/parallel/parallel.cpp 6641+dfsg-2/examples/parallel/parallel.cpp --- 5882+dfsg-2/examples/parallel/parallel.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/parallel/parallel.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -184,6 +184,9 @@ int main(int argc, char ** argv) { // extra text to insert in each client's prompt in order to make it larger const int32_t n_junk = std::max(1, params.n_junk); + // signed seed, use negative values to indicate different seeds for the different clients + const int32_t & sseed = params.sampling.seed; + // init llama.cpp llama_backend_init(); llama_numa_init(params.numa); @@ -219,11 +222,21 @@ int main(int argc, char ** argv) { const int n_ctx = llama_n_ctx(ctx); + if (sseed >= 0) { + LOG_INF("%s: initializing all samplers with the same RNG seed: %d (use a negative seed to have different seeds)\n", __func__, sseed); + } else { + LOG_INF("%s: initializing samplers with different RNG seeds, starting from %d\n", __func__, sseed); + } + std::vector clients(n_clients); for (size_t i = 0; i < clients.size(); ++i) { auto & client = clients[i]; client.id = i; client.smpl = common_sampler_init(model, params.sampling); + + if (sseed < 0) { + params.sampling.seed--; + } } std::vector tokens_system; @@ -345,7 +358,7 @@ int main(int argc, char ** argv) { client.n_decoded = 0; client.i_batch = batch.n_tokens - 1; - LOG_INF("\033[31mClient %3d, seq %4d, junk = %4d, started decoding ...\033[0m\n", client.id, client.seq_id, n_junk_cur); + LOG_INF("\033[31mClient %3d, seq %4d, junk = %4d, prompt = %d, started decoding ...\033[0m\n", client.id, client.seq_id, n_junk_cur, client.n_prompt); g_seq_id += 1; diff -pruN 5882+dfsg-2/examples/passkey/README.md 6641+dfsg-2/examples/passkey/README.md --- 5882+dfsg-2/examples/passkey/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/passkey/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -11,5 +11,5 @@ See the following PRs for more info: ### Usage ```bash -make -j && ./llama-passkey -m ./models/llama-7b-v2/ggml-model-f16.gguf --junk 250 +llama-passkey -m ./models/llama-7b-v2/ggml-model-f16.gguf --junk 250 ``` diff -pruN 5882+dfsg-2/examples/retrieval/README.md 6641+dfsg-2/examples/retrieval/README.md --- 5882+dfsg-2/examples/retrieval/README.md 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/retrieval/README.md 2025-09-30 07:36:33.000000000 +0000 @@ -15,7 +15,7 @@ https://github.com/ggml-org/llama.cpp/pu `retrieval` example can be tested as follows: ```bash -make -j && ./llama-retrieval --model ./models/bge-base-en-v1.5-f16.gguf --top-k 3 --context-file README.md --context-file License --chunk-size 100 --chunk-separator . +llama-retrieval --model ./models/bge-base-en-v1.5-f16.gguf --top-k 3 --context-file README.md --context-file License --chunk-size 100 --chunk-separator . ``` This chunks and embeds all given files and starts a loop requesting query inputs: diff -pruN 5882+dfsg-2/examples/save-load-state/save-load-state.cpp 6641+dfsg-2/examples/save-load-state/save-load-state.cpp --- 5882+dfsg-2/examples/save-load-state/save-load-state.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/save-load-state/save-load-state.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -15,6 +15,12 @@ int main(int argc, char ** argv) { return 1; } + if (params.n_parallel == 1) { + // the example uses 2 sequences, so when n_parallel == 1, we need to enable unified kv cache + printf("%s: n_parallel == 1, enabling unified kv cache\n", __func__); + params.kv_unified = true; + } + common_init(); if (params.n_predict < 0) { diff -pruN 5882+dfsg-2/examples/simple/simple.cpp 6641+dfsg-2/examples/simple/simple.cpp --- 5882+dfsg-2/examples/simple/simple.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/simple/simple.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -145,6 +145,20 @@ int main(int argc, char ** argv) { llama_batch batch = llama_batch_get_one(prompt_tokens.data(), prompt_tokens.size()); + if (llama_model_has_encoder(model)) { + if (llama_encode(ctx, batch)) { + fprintf(stderr, "%s : failed to eval\n", __func__); + return 1; + } + + llama_token decoder_start_token_id = llama_model_decoder_start_token(model); + if (decoder_start_token_id == LLAMA_TOKEN_NULL) { + decoder_start_token_id = llama_vocab_bos(vocab); + } + + batch = llama_batch_get_one(&decoder_start_token_id, 1); + } + // main loop const auto t_main_start = ggml_time_us(); diff -pruN 5882+dfsg-2/examples/speculative/speculative.cpp 6641+dfsg-2/examples/speculative/speculative.cpp --- 5882+dfsg-2/examples/speculative/speculative.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/speculative/speculative.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -85,6 +85,8 @@ int main(int argc, char ** argv) { } params.cpuparams_batch.n_threads = params.speculative.cpuparams_batch.n_threads; + params.tensor_buft_overrides = params.speculative.tensor_buft_overrides; + common_init_result llama_init_dft = common_init_from_params(params); model_dft = llama_init_dft.model.get(); @@ -242,7 +244,7 @@ int main(int argc, char ** argv) { // stochastic verification common_sampler_sample(smpl, ctx_tgt, drafts[s_keep].i_batch_tgt[i_dft], true); - auto & dist_tgt = *common_sampler_get_candidates(smpl); + auto & dist_tgt = *common_sampler_get_candidates(smpl, true); float p_tgt = 0.0f; float p_dft = 0.0f; @@ -491,7 +493,7 @@ int main(int argc, char ** argv) { common_sampler_sample(drafts[s].smpl, ctx_dft, drafts[s].i_batch_dft, true); - const auto * cur_p = common_sampler_get_candidates(drafts[s].smpl); + const auto * cur_p = common_sampler_get_candidates(drafts[s].smpl, true); for (int k = 0; k < std::min(n_seq_dft + 3, (int) cur_p->size); ++k) { LOG_DBG(" - draft candidate %3d for seq %3d, pos %3d: %6d (%8.3f) '%s'\n", diff -pruN 5882+dfsg-2/examples/speculative-simple/speculative-simple.cpp 6641+dfsg-2/examples/speculative-simple/speculative-simple.cpp --- 5882+dfsg-2/examples/speculative-simple/speculative-simple.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/speculative-simple/speculative-simple.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -59,13 +59,15 @@ int main(int argc, char ** argv) { } params.cpuparams_batch.n_threads = params.speculative.cpuparams_batch.n_threads; + params.tensor_buft_overrides = params.speculative.tensor_buft_overrides; + common_init_result llama_init_dft = common_init_from_params(params); //model_dft = llama_init_dft.model.get(); ctx_dft = llama_init_dft.context.get(); if (!common_speculative_are_compatible(ctx_tgt, ctx_dft)) { - return 1; + LOG_INF("the draft model '%s' is not compatible with the target model '%s'. tokens will be translated between the draft and target models.\n", params.speculative.model.path.c_str(), params.model.path.c_str()); } // Tokenize the prompt @@ -130,7 +132,10 @@ int main(int argc, char ** argv) { params_spec.n_reuse = llama_n_ctx(ctx_dft) - n_draft; params_spec.p_min = p_min; - struct common_speculative * spec = common_speculative_init(ctx_dft); + struct common_speculative * spec = common_speculative_init(ctx_tgt, ctx_dft); + for (auto &pair : params.speculative.replacements) { + common_speculative_add_replacement_tgt_dft(spec, pair.first.c_str(), pair.second.c_str()); + } llama_batch batch_tgt = llama_batch_init(llama_n_batch(ctx_tgt), 0, 1); diff -pruN 5882+dfsg-2/examples/sycl/win-build-sycl.bat 6641+dfsg-2/examples/sycl/win-build-sycl.bat --- 5882+dfsg-2/examples/sycl/win-build-sycl.bat 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/sycl/win-build-sycl.bat 2025-09-30 07:36:33.000000000 +0000 @@ -18,8 +18,6 @@ if %errorlevel% neq 0 goto ERROR :: for FP32 cmake -G "Ninja" .. -DLLAMA_CURL=OFF -DGGML_SYCL=ON -DCMAKE_C_COMPILER=cl -DCMAKE_CXX_COMPILER=icx -DBUILD_SHARED_LIBS=ON -DCMAKE_BUILD_TYPE=Release if %errorlevel% neq 0 goto ERROR -:: build example/main only -:: make main :: build all binary cmake --build . -j diff -pruN 5882+dfsg-2/examples/training/finetune.cpp 6641+dfsg-2/examples/training/finetune.cpp --- 5882+dfsg-2/examples/training/finetune.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/examples/training/finetune.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -10,20 +10,20 @@ #include #if defined(_MSC_VER) -#pragma warning(disable: 4244 4267) // possible loss of data +#pragma warning(disable: 4244 4267) // possible loss of data #endif int main(int argc, char ** argv) { common_params params; - params.escape = false; - if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_PERPLEXITY)) { + if (!common_params_parse(argc, argv, params, LLAMA_EXAMPLE_FINETUNE)) { return 1; } if (params.use_mmap) { - LOG_INF("%s: force disabling memory mapping because it would result in-read-only pointers to the weights\n", __func__); + LOG_INF("%s: force disabling memory mapping because it would result in-read-only pointers to the weights\n", + __func__); params.use_mmap = false; } if (params.cache_type_k != GGML_TYPE_F32) { @@ -38,11 +38,10 @@ int main(int argc, char ** argv) { common_init(); llama_backend_init(); llama_numa_init(params.numa); - // load the model and apply lora adapter, if any - common_init_result llama_init = common_init_from_params(params); - llama_model_ptr & model = llama_init.model; - llama_context_ptr & ctx = llama_init.context; + common_init_result llama_init = common_init_from_params(params); + llama_model_ptr & model = llama_init.model; + llama_context_ptr & ctx = llama_init.context; if (model == NULL) { LOG_ERR("%s: unable to load model\n", __func__); @@ -55,31 +54,32 @@ int main(int argc, char ** argv) { LOG_INF("%s\n", common_params_get_system_info(params).c_str()); } - constexpr float val_split = 0.05f; - - std::vector tokens = common_tokenize(ctx.get(), params.prompt, true); - ggml_opt_dataset_t dataset = common_opt_dataset_init(ctx.get(), tokens, llama_n_ctx(ctx.get())/2); - - struct ggml_opt_optimizer_params optimizer_params = ggml_opt_get_default_optimizer_params(nullptr); - optimizer_params.adamw.alpha = 1e-7f; // learning rate + std::vector tokens = common_tokenize(ctx.get(), params.prompt, true); + ggml_opt_dataset_t dataset = common_opt_dataset_init(ctx.get(), tokens, llama_n_ctx(ctx.get()) / 2); - struct llama_opt_params lopt_params { - /*n_ctx_train =*/ 0, - /*param_filter =*/ llama_opt_param_filter_all, - /*param_filter_ud =*/ nullptr, - /*get_opt_pars =*/ ggml_opt_get_constant_optimizer_params, - /*get_opt_pars_ud =*/ &optimizer_params, + struct lr_opt & lr = params.lr; + LOG_INF("-optimizer %s -lr0 %.2g -wd %.2g -lr-min %.2g -min-epochs %.2g -epochs %d -period %.2g -val %.2g\n", + ggml_opt_optimizer_name(params.optimizer), (double) lr.lr0, (double) lr.wd, (double) lr.lr_min, (double) lr.decay_epochs, + (unsigned) lr.epochs, (double) params.n_batch / params.n_ubatch, (double) params.val_split); + + struct llama_opt_params lopt_params{ + /*n_ctx_train =*/0, + /*param_filter =*/llama_opt_param_filter_all, + /*param_filter_ud =*/nullptr, + /*get_opt_pars =*/common_opt_lr_pars, + /*get_opt_pars_ud =*/¶ms.lr, + /*optimizer_type =*/params.optimizer, }; llama_opt_init(ctx.get(), model.get(), lopt_params); - const int64_t idata_split = ggml_opt_dataset_ndata(dataset) * (1.0f - val_split); + const int64_t idata_split = ggml_opt_dataset_ndata(dataset) * (1.0f - params.val_split); ggml_opt_result_t result_train = ggml_opt_result_init(); ggml_opt_result_t result_eval = ggml_opt_result_init(); - for (int epoch = 0; epoch < 2; ++epoch) { + for (lr.epoch = 0; lr.epoch < lr.epochs; ++lr.epoch) { llama_opt_epoch(ctx.get(), dataset, result_train, result_eval, idata_split, - ggml_opt_epoch_callback_progress_bar, ggml_opt_epoch_callback_progress_bar); + ggml_opt_epoch_callback_progress_bar, ggml_opt_epoch_callback_progress_bar); fprintf(stderr, "\n"); ggml_opt_result_reset(result_train); @@ -88,7 +88,7 @@ int main(int argc, char ** argv) { ggml_opt_result_free(result_train); ggml_opt_result_free(result_eval); - llama_model_save_to_file(model.get(), "finetuned-model.gguf"); + llama_model_save_to_file(model.get(), params.out_file.c_str()); llama_backend_free(); diff -pruN 5882+dfsg-2/flake.nix 6641+dfsg-2/flake.nix --- 5882+dfsg-2/flake.nix 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/flake.nix 2025-09-30 07:36:33.000000000 +0000 @@ -36,9 +36,6 @@ # ``` # nixConfig = { # extra-substituters = [ - # # Populated by the CI in ggml-org/llama.cpp - # "https://llama-cpp.cachix.org" - # # # A development cache for nixpkgs imported with `config.cudaSupport = true`. # # Populated by https://hercules-ci.com/github/SomeoneSerge/nixpkgs-cuda-ci. # # This lets one skip building e.g. the CUDA-enabled openmpi. @@ -47,10 +44,8 @@ # ]; # # # Verify these are the same keys as published on - # # - https://app.cachix.org/cache/llama-cpp # # - https://app.cachix.org/cache/cuda-maintainers # extra-trusted-public-keys = [ - # "llama-cpp.cachix.org-1:H75X+w83wUKTIPSO1KWy9ADUrzThyGs8P5tmAbkWhQc=" # "cuda-maintainers.cachix.org-1:0dq3bujKpuEPMCX6U4WylrUDZ9JyUG0VpVZa7CNfq5E=" # ]; # }; diff -pruN 5882+dfsg-2/ggml/CMakeLists.txt 6641+dfsg-2/ggml/CMakeLists.txt --- 5882+dfsg-2/ggml/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -1,5 +1,40 @@ cmake_minimum_required(VERSION 3.14) # for add_link_options and implicit target directories. -project("ggml" C CXX) +project("ggml" C CXX ASM) + +### GGML Version +set(GGML_VERSION_MAJOR 0) +set(GGML_VERSION_MINOR 9) +set(GGML_VERSION_PATCH 3) +set(GGML_VERSION_BASE "${GGML_VERSION_MAJOR}.${GGML_VERSION_MINOR}.${GGML_VERSION_PATCH}") + +find_program(GIT_EXE NAMES git git.exe NO_CMAKE_FIND_ROOT_PATH) +if(GIT_EXE) + # Get current git commit hash + execute_process(COMMAND ${GIT_EXE} rev-parse --short HEAD + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + OUTPUT_VARIABLE GGML_BUILD_COMMIT + OUTPUT_STRIP_TRAILING_WHITESPACE + ERROR_QUIET + ) + + # Check if the working directory is dirty (i.e., has uncommitted changes) + execute_process(COMMAND ${GIT_EXE} diff-index --quiet HEAD -- . + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + RESULT_VARIABLE GGML_GIT_DIRTY + ERROR_QUIET + ) +endif() + +# Build the version string with optional dirty flag +set(GGML_VERSION "${GGML_VERSION_BASE}") +if(GGML_GIT_DIRTY AND NOT GGML_GIT_DIRTY EQUAL 0) + set(GGML_VERSION "${GGML_VERSION}-dirty") +endif() + +if(NOT GGML_BUILD_COMMIT) + set(GGML_BUILD_COMMIT "unknown") +endif() + include(CheckIncludeFileCXX) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) @@ -39,8 +74,9 @@ if (WIN32) set(CMAKE_SHARED_MODULE_PREFIX "") endif() -option(BUILD_SHARED_LIBS "ggml: build shared libraries" ${BUILD_SHARED_LIBS_DEFAULT}) -option(GGML_BACKEND_DL "ggml: build backends as dynamic libraries (requires BUILD_SHARED_LIBS)" OFF) +option(BUILD_SHARED_LIBS "ggml: build shared libraries" ${BUILD_SHARED_LIBS_DEFAULT}) +option(GGML_BACKEND_DL "ggml: build backends as dynamic libraries (requires BUILD_SHARED_LIBS)" OFF) +set(GGML_BACKEND_DIR "" CACHE PATH "ggml: directory to load dynamic backends from (requires GGML_BACKEND_DL") # # option list @@ -128,10 +164,11 @@ endif() option(GGML_LASX "ggml: enable lasx" ON) option(GGML_LSX "ggml: enable lsx" ON) option(GGML_RVV "ggml: enable rvv" ON) -option(GGML_RV_ZFH "ggml: enable riscv zfh" OFF) +option(GGML_RV_ZFH "ggml: enable riscv zfh" ON) +option(GGML_RV_ZVFH "ggml: enable riscv zvfh" ON) +option(GGML_RV_ZICBOP "ggml: enable riscv zicbop" ON) option(GGML_XTHEADVECTOR "ggml: enable xtheadvector" OFF) option(GGML_VXE "ggml: enable vxe" ON) -option(GGML_NNPA "ggml: enable nnpa" ON) option(GGML_CPU_ALL_VARIANTS "ggml: build all variants of the CPU backend (requires GGML_BACKEND_DL)" OFF) set(GGML_CPU_ARM_ARCH "" CACHE STRING "ggml: CPU architecture for ARM") @@ -139,7 +176,7 @@ set(GGML_CPU_POWERPC_CPUTYPE "" CACHE ST if (MINGW) - set(GGML_WIN_VER "0x602" CACHE STRING "ggml: Windows version") + set(GGML_WIN_VER "0xA00" CACHE STRING "ggml: Windows version") endif() # ggml core @@ -157,7 +194,6 @@ option(GGML_CUDA option(GGML_MUSA "ggml: use MUSA" OFF) option(GGML_CUDA_FORCE_MMQ "ggml: use mmq kernels instead of cuBLAS" OFF) option(GGML_CUDA_FORCE_CUBLAS "ggml: always use cuBLAS instead of mmq kernels" OFF) -option(GGML_CUDA_F16 "ggml: use 16 bit floats for some calculations" OFF) set (GGML_CUDA_PEER_MAX_BATCH_SIZE "128" CACHE STRING "ggml: max. batch size for using peer access") option(GGML_CUDA_NO_PEER_COPY "ggml: do not use peer to peer copies" OFF) @@ -174,6 +210,10 @@ option(GGML_HIP_GRAPHS option(GGML_HIP_NO_VMM "ggml: do not try to use HIP VMM" ON) option(GGML_HIP_ROCWMMA_FATTN "ggml: enable rocWMMA for FlashAttention" OFF) option(GGML_HIP_FORCE_ROCWMMA_FATTN_GFX12 "ggml: enable rocWMMA FlashAttention on GFX12" OFF) +option(GGML_HIP_MMQ_MFMA "ggml: enable MFMA MMA for CDNA in MMQ" ON) +option(GGML_HIP_EXPORT_METRICS "ggml: enable kernel perf metrics output" OFF) +option(GGML_MUSA_GRAPHS "ggml: use MUSA graph, experimental, unstable" OFF) +option(GGML_MUSA_MUDNN_COPY "ggml: enable muDNN for accelerated copy" OFF) option(GGML_VULKAN "ggml: use Vulkan" OFF) option(GGML_VULKAN_CHECK_RESULTS "ggml: run Vulkan op checks" OFF) option(GGML_VULKAN_DEBUG "ggml: enable Vulkan debug output" OFF) @@ -181,8 +221,10 @@ option(GGML_VULKAN_MEMORY_DEBUG option(GGML_VULKAN_SHADER_DEBUG_INFO "ggml: enable Vulkan shader debug info" OFF) option(GGML_VULKAN_VALIDATE "ggml: enable Vulkan validation" OFF) option(GGML_VULKAN_RUN_TESTS "ggml: run Vulkan tests" OFF) +option(GGML_WEBGPU "ggml: use WebGPU" OFF) +option(GGML_WEBGPU_DEBUG "ggml: enable WebGPU debug output" OFF) +option(GGML_ZDNN "ggml: use zDNN" OFF) option(GGML_METAL "ggml: use Metal" ${GGML_METAL_DEFAULT}) -option(GGML_METAL_USE_BF16 "ggml: use bfloat if available" OFF) option(GGML_METAL_NDEBUG "ggml: disable Metal debugging" OFF) option(GGML_METAL_SHADER_DEBUG "ggml: compile Metal with -fno-fast-math" OFF) option(GGML_METAL_EMBED_LIBRARY "ggml: embed Metal library" ${GGML_METAL}) @@ -270,6 +312,7 @@ set(GGML_PUBLIC_HEADERS include/ggml-rpc.h include/ggml-sycl.h include/ggml-vulkan.h + include/ggml-webgpu.h include/gguf.h) set_target_properties(ggml PROPERTIES PUBLIC_HEADER "${GGML_PUBLIC_HEADERS}") @@ -292,26 +335,6 @@ endif() # Create CMake package # -# Generate version info based on git commit. - -if(NOT DEFINED GGML_BUILD_NUMBER) - find_program(GIT_EXE NAMES git git.exe REQUIRED NO_CMAKE_FIND_ROOT_PATH) - execute_process(COMMAND ${GIT_EXE} rev-list --count HEAD - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - OUTPUT_VARIABLE GGML_BUILD_NUMBER - OUTPUT_STRIP_TRAILING_WHITESPACE - ) - - if(GGML_BUILD_NUMBER EQUAL 1) - message(WARNING "GGML build version fixed at 1 likely due to a shallow clone.") - endif() - - execute_process(COMMAND ${GIT_EXE} rev-parse --short HEAD - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - OUTPUT_VARIABLE GGML_BUILD_COMMIT - OUTPUT_STRIP_TRAILING_WHITESPACE - ) -endif() # Capture variables prefixed with GGML_. @@ -340,7 +363,7 @@ set(GGML_VARIABLES_EXPANDED ${variable_s # Create the CMake package and set install location. -set(GGML_INSTALL_VERSION 0.0.${GGML_BUILD_NUMBER}) +set(GGML_INSTALL_VERSION ${GGML_VERSION}) set(GGML_INCLUDE_INSTALL_DIR ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Location of header files") set(GGML_LIB_INSTALL_DIR ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Location of library files") set(GGML_BIN_INSTALL_DIR ${CMAKE_INSTALL_BINDIR} CACHE PATH "Location of binary files") diff -pruN 5882+dfsg-2/ggml/cmake/ggml-config.cmake.in 6641+dfsg-2/ggml/cmake/ggml-config.cmake.in --- 5882+dfsg-2/ggml/cmake/ggml-config.cmake.in 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/cmake/ggml-config.cmake.in 2025-09-30 07:36:33.000000000 +0000 @@ -1,152 +1,191 @@ - -@GGML_VARIABLES_EXPANDED@ - @PACKAGE_INIT@ -set_and_check(GGML_INCLUDE_DIR "@PACKAGE_GGML_INCLUDE_INSTALL_DIR@") -set_and_check(GGML_LIB_DIR "@PACKAGE_GGML_LIB_INSTALL_DIR@") -#set_and_check(GGML_BIN_DIR "@PACKAGE_GGML_BIN_INSTALL_DIR@") - -find_package(Threads REQUIRED) - -find_library(GGML_LIBRARY ggml - REQUIRED - HINTS ${GGML_LIB_DIR} - NO_CMAKE_FIND_ROOT_PATH) - -add_library(ggml::ggml UNKNOWN IMPORTED) -set_target_properties(ggml::ggml - PROPERTIES - IMPORTED_LOCATION "${GGML_LIBRARY}") - -find_library(GGML_BASE_LIBRARY ggml-base - REQUIRED - HINTS ${GGML_LIB_DIR} - NO_CMAKE_FIND_ROOT_PATH) - -add_library(ggml::ggml-base UNKNOWN IMPORTED) -set_target_properties(ggml::ggml-base - PROPERTIES - IMPORTED_LOCATION "${GGML_BASE_LIBRARY}") +@GGML_VARIABLES_EXPANDED@ +# Find all dependencies before creating any target. +include(CMakeFindDependencyMacro) +find_dependency(Threads) if (NOT GGML_SHARED_LIB) + set(GGML_CPU_INTERFACE_LINK_LIBRARIES "") + set(GGML_CPU_INTERFACE_LINK_OPTIONS "") + if (APPLE AND GGML_ACCELERATE) - find_library(ACCELERATE_FRAMEWORK Accelerate REQUIRED) + find_library(ACCELERATE_FRAMEWORK Accelerate) + if(NOT ACCELERATE_FRAMEWORK) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES ${ACCELERATE_FRAMEWORK}) endif() - if (GGML_OPENMP) - find_package(OpenMP REQUIRED) + if (GGML_OPENMP_ENABLED) + find_dependency(OpenMP) list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES OpenMP::OpenMP_C OpenMP::OpenMP_CXX) endif() if (GGML_CPU_HBM) - find_library(memkind memkind REQUIRED) + find_library(memkind memkind) + if(NOT memkind) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES memkind) endif() if (GGML_BLAS) - find_package(BLAS REQUIRED) - list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES ${BLAS_LIBRARIES}) - list(APPEND GGML_CPU_INTERFACE_LINK_OPTIONS ${BLAS_LINKER_FLAGS}) + find_dependency(BLAS) + list(APPEND GGML_BLAS_INTERFACE_LINK_LIBRARIES ${BLAS_LIBRARIES}) + list(APPEND GGML_BLAS_INTERFACE_LINK_OPTIONS ${BLAS_LINKER_FLAGS}) endif() if (GGML_CUDA) - find_package(CUDAToolkit REQUIRED) + set(GGML_CUDA_INTERFACE_LINK_LIBRARIES "") + find_dependency(CUDAToolkit) + if (GGML_STATIC) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $) + if (WIN32) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $ $) + else() + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $ $) + endif() + endif() + if (NOT GGML_CUDA_NO_VMM) + list(APPEND GGML_CUDA_INTERFACE_LINK_LIBRARIES $) + endif() endif() if (GGML_METAL) - find_library(FOUNDATION_LIBRARY Foundation REQUIRED) - find_library(METAL_FRAMEWORK Metal REQUIRED) - find_library(METALKIT_FRAMEWORK MetalKit REQUIRED) + find_library(FOUNDATION_LIBRARY Foundation) + find_library(METAL_FRAMEWORK Metal) + find_library(METALKIT_FRAMEWORK MetalKit) + if(NOT FOUNDATION_LIBRARY OR NOT METAL_FRAMEWORK OR NOT METALKIT_FRAMEWORK) + set(${CMAKE_FIND_PACKAGE_NAME}_FOUND 0) + return() + endif() + set(GGML_METAL_INTERFACE_LINK_LIBRARIES + ${FOUNDATION_LIBRARY} ${METAL_FRAMEWORK} ${METALKIT_FRAMEWORK}) + endif() - list(APPEND GGML_METAL_INTERFACE_LINK_LIBRARIES - ${FOUNDATION_LIBRARY} ${METAL_FRAMEWORK} ${METALKIT_FRAMEWORK}) + if (GGML_OPENCL) + find_dependency(OpenCL) + set(GGML_OPENCL_INTERFACE_LINK_LIBRARIES $) endif() if (GGML_VULKAN) - find_package(Vulkan REQUIRED) - list(APPEND GGML_VULKAN_INTERFACE_LINK_LIBRARIES Vulkan::Vulkan) + find_dependency(Vulkan) + set(GGML_VULKAN_INTERFACE_LINK_LIBRARIES $) endif() if (GGML_HIP) - find_package(hip REQUIRED) - find_package(hipblas REQUIRED) - find_package(rocblas REQUIRED) - list(APPEND GGML_HIP_INTERFACE_LINK_LIBRARIES hip::host roc::rocblas roc::hipblas) + find_dependency(hip) + find_dependency(hipblas) + find_dependency(rocblas) + set(GGML_HIP_INTERFACE_LINK_LIBRARIES hip::host roc::rocblas roc::hipblas) endif() if (GGML_SYCL) + set(GGML_SYCL_INTERFACE_LINK_LIBRARIES "") find_package(DNNL) if (${DNNL_FOUND} AND GGML_SYCL_TARGET STREQUAL "INTEL") list(APPEND GGML_SYCL_INTERFACE_LINK_LIBRARIES DNNL::dnnl) endif() if (WIN32) - find_package(IntelSYCL REQUIRED) - find_package(MKL REQUIRED) + find_dependency(IntelSYCL) + find_dependency(MKL) list(APPEND GGML_SYCL_INTERFACE_LINK_LIBRARIES IntelSYCL::SYCL_CXX MKL::MKL MKL::MKL_SYCL) endif() endif() endif() -set(_ggml_all_targets "") -foreach(_ggml_backend ${GGML_AVAILABLE_BACKENDS}) - string(REPLACE "-" "_" _ggml_backend_pfx "${_ggml_backend}") - string(TOUPPER "${_ggml_backend_pfx}" _ggml_backend_pfx) +set_and_check(GGML_INCLUDE_DIR "@PACKAGE_GGML_INCLUDE_INSTALL_DIR@") +set_and_check(GGML_LIB_DIR "@PACKAGE_GGML_LIB_INSTALL_DIR@") +#set_and_check(GGML_BIN_DIR "@PACKAGE_GGML_BIN_INSTALL_DIR@") + +if(NOT TARGET ggml::ggml) + find_package(Threads REQUIRED) - find_library(${_ggml_backend_pfx}_LIBRARY ${_ggml_backend} + find_library(GGML_LIBRARY ggml REQUIRED HINTS ${GGML_LIB_DIR} NO_CMAKE_FIND_ROOT_PATH) - message(STATUS "Found ${${_ggml_backend_pfx}_LIBRARY}") + add_library(ggml::ggml UNKNOWN IMPORTED) + set_target_properties(ggml::ggml + PROPERTIES + IMPORTED_LOCATION "${GGML_LIBRARY}") - add_library(ggml::${_ggml_backend} UNKNOWN IMPORTED) - set_target_properties(ggml::${_ggml_backend} + find_library(GGML_BASE_LIBRARY ggml-base + REQUIRED + HINTS ${GGML_LIB_DIR} + NO_CMAKE_FIND_ROOT_PATH) + + add_library(ggml::ggml-base UNKNOWN IMPORTED) + set_target_properties(ggml::ggml-base PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${GGML_INCLUDE_DIR}" - IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" - IMPORTED_LOCATION "${${_ggml_backend_pfx}_LIBRARY}" - INTERFACE_COMPILE_FEATURES c_std_90 - POSITION_INDEPENDENT_CODE ON) - - string(REGEX MATCH "^ggml-cpu" is_cpu_variant "${_ggml_backend}") - if(is_cpu_variant) - list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") - set_target_properties(ggml::${_ggml_backend} - PROPERTIES - INTERFACE_LINK_LIBRARIES "${GGML_CPU_INTERFACE_LINK_LIBRARIES}") + IMPORTED_LOCATION "${GGML_BASE_LIBRARY}") - if(GGML_CPU_INTERFACE_LINK_OPTIONS) - set_target_properties(ggml::${_ggml_backend} - PROPERTIES - INTERFACE_LINK_OPTIONS "${GGML_CPU_INTERFACE_LINK_OPTIONS}") - endif() + set(_ggml_all_targets "") + if (NOT GGML_BACKEND_DL) + foreach(_ggml_backend ${GGML_AVAILABLE_BACKENDS}) + string(REPLACE "-" "_" _ggml_backend_pfx "${_ggml_backend}") + string(TOUPPER "${_ggml_backend_pfx}" _ggml_backend_pfx) + + find_library(${_ggml_backend_pfx}_LIBRARY ${_ggml_backend} + REQUIRED + HINTS ${GGML_LIB_DIR} + NO_CMAKE_FIND_ROOT_PATH) - else() - list(APPEND ${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") - set_target_properties(ggml::${_ggml_backend} - PROPERTIES - INTERFACE_LINK_LIBRARIES "${${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES}") + message(STATUS "Found ${${_ggml_backend_pfx}_LIBRARY}") - if(${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS) + add_library(ggml::${_ggml_backend} UNKNOWN IMPORTED) set_target_properties(ggml::${_ggml_backend} PROPERTIES - INTERFACE_LINK_OPTIONS "${${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS}") - endif() + INTERFACE_INCLUDE_DIRECTORIES "${GGML_INCLUDE_DIR}" + IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" + IMPORTED_LOCATION "${${_ggml_backend_pfx}_LIBRARY}" + INTERFACE_COMPILE_FEATURES c_std_90 + POSITION_INDEPENDENT_CODE ON) + + string(REGEX MATCH "^ggml-cpu" is_cpu_variant "${_ggml_backend}") + if(is_cpu_variant) + list(APPEND GGML_CPU_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_LIBRARIES "${GGML_CPU_INTERFACE_LINK_LIBRARIES}") + + if(GGML_CPU_INTERFACE_LINK_OPTIONS) + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_OPTIONS "${GGML_CPU_INTERFACE_LINK_OPTIONS}") + endif() + + else() + list(APPEND ${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES "ggml::ggml-base") + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_LIBRARIES "${${_ggml_backend_pfx}_INTERFACE_LINK_LIBRARIES}") + + if(${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS) + set_target_properties(ggml::${_ggml_backend} + PROPERTIES + INTERFACE_LINK_OPTIONS "${${_ggml_backend_pfx}_INTERFACE_LINK_OPTIONS}") + endif() + endif() + + list(APPEND _ggml_all_targets ggml::${_ggml_backend}) + endforeach() endif() - list(APPEND _ggml_all_targets ggml::${_ggml_backend}) -endforeach() + list(APPEND GGML_INTERFACE_LINK_LIBRARIES ggml::ggml-base "${_ggml_all_targets}") + set_target_properties(ggml::ggml + PROPERTIES + INTERFACE_LINK_LIBRARIES "${GGML_INTERFACE_LINK_LIBRARIES}") -list(APPEND GGML_INTERFACE_LINK_LIBRARIES ggml::ggml-base "${_ggml_all_targets}") -set_target_properties(ggml::ggml - PROPERTIES - INTERFACE_LINK_LIBRARIES "${GGML_INTERFACE_LINK_LIBRARIES}") + add_library(ggml::all INTERFACE IMPORTED) + set_target_properties(ggml::all + PROPERTIES + INTERFACE_LINK_LIBRARIES "${_ggml_all_targets}") -add_library(ggml::all INTERFACE IMPORTED) -set_target_properties(ggml::all - PROPERTIES - INTERFACE_LINK_LIBRARIES "${_ggml_all_targets}") +endif() check_required_components(ggml) diff -pruN 5882+dfsg-2/ggml/include/ggml-backend.h 6641+dfsg-2/ggml/include/ggml-backend.h --- 5882+dfsg-2/ggml/include/ggml-backend.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-backend.h 2025-09-30 07:36:33.000000000 +0000 @@ -132,6 +132,8 @@ extern "C" { GGML_BACKEND_DEVICE_TYPE_CPU, // GPU device using dedicated memory GGML_BACKEND_DEVICE_TYPE_GPU, + // integrated GPU device using host memory + GGML_BACKEND_DEVICE_TYPE_IGPU, // accelerator devices intended to be used together with the CPU backend (e.g. BLAS or AMX) GGML_BACKEND_DEVICE_TYPE_ACCEL }; @@ -150,11 +152,21 @@ extern "C" { // all the device properties struct ggml_backend_dev_props { + // device name const char * name; + // device description const char * description; + // device free memory in bytes size_t memory_free; + // device total memory in bytes size_t memory_total; + // device type enum ggml_backend_dev_type type; + // device id + // for PCI devices, this should be the PCI bus id formatted as "domain:bus:device.function" (e.g. "0000:01:00.0") + // if the id is unknown, this should be NULL + const char * device_id; + // device capabilities struct ggml_backend_dev_caps caps; }; @@ -302,11 +314,15 @@ extern "C" { GGML_API int ggml_backend_sched_get_n_splits(ggml_backend_sched_t sched); GGML_API int ggml_backend_sched_get_n_copies(ggml_backend_sched_t sched); - GGML_API size_t ggml_backend_sched_get_buffer_size(ggml_backend_sched_t sched, ggml_backend_t backend); + GGML_API ggml_backend_buffer_type_t ggml_backend_sched_get_buffer_type(ggml_backend_sched_t sched, ggml_backend_t backend); + GGML_API size_t ggml_backend_sched_get_buffer_size(ggml_backend_sched_t sched, ggml_backend_t backend); GGML_API void ggml_backend_sched_set_tensor_backend(ggml_backend_sched_t sched, struct ggml_tensor * node, ggml_backend_t backend); GGML_API ggml_backend_t ggml_backend_sched_get_tensor_backend(ggml_backend_sched_t sched, struct ggml_tensor * node); + // Split graph without allocating it + GGML_API void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph); + // Allocate and compute graph on the backend scheduler GGML_API bool ggml_backend_sched_alloc_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph); // returns success GGML_API enum ggml_status ggml_backend_sched_graph_compute(ggml_backend_sched_t sched, struct ggml_cgraph * graph); diff -pruN 5882+dfsg-2/ggml/include/ggml-cpu.h 6641+dfsg-2/ggml/include/ggml-cpu.h --- 5882+dfsg-2/ggml/include/ggml-cpu.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-cpu.h 2025-09-30 07:36:33.000000000 +0000 @@ -101,7 +101,6 @@ extern "C" { GGML_BACKEND_API int ggml_cpu_has_riscv_v (void); GGML_BACKEND_API int ggml_cpu_has_vsx (void); GGML_BACKEND_API int ggml_cpu_has_vxe (void); - GGML_BACKEND_API int ggml_cpu_has_nnpa (void); GGML_BACKEND_API int ggml_cpu_has_wasm_simd (void); GGML_BACKEND_API int ggml_cpu_has_llamafile (void); @@ -135,6 +134,7 @@ extern "C" { GGML_BACKEND_API ggml_backend_reg_t ggml_backend_cpu_reg(void); GGML_BACKEND_API void ggml_cpu_fp32_to_fp32(const float *, float *, int64_t); + GGML_BACKEND_API void ggml_cpu_fp32_to_i32 (const float *, int32_t *, int64_t); GGML_BACKEND_API void ggml_cpu_fp32_to_fp16(const float *, ggml_fp16_t *, int64_t); GGML_BACKEND_API void ggml_cpu_fp16_to_fp32(const ggml_fp16_t *, float *, int64_t); GGML_BACKEND_API void ggml_cpu_fp32_to_bf16(const float *, ggml_bf16_t *, int64_t); diff -pruN 5882+dfsg-2/ggml/include/ggml-metal.h 6641+dfsg-2/ggml/include/ggml-metal.h --- 5882+dfsg-2/ggml/include/ggml-metal.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-metal.h 2025-09-30 07:36:33.000000000 +0000 @@ -39,18 +39,13 @@ extern "C" { // user-code should use only these functions // +// TODO: remove in the future GGML_BACKEND_API ggml_backend_t ggml_backend_metal_init(void); GGML_BACKEND_API bool ggml_backend_is_metal(ggml_backend_t backend); -GGML_DEPRECATED( - GGML_BACKEND_API ggml_backend_buffer_t ggml_backend_metal_buffer_from_ptr(void * data, size_t size, size_t max_size), - "obsoleted by the new device interface - https://github.com/ggml-org/llama.cpp/pull/9713"); - GGML_BACKEND_API void ggml_backend_metal_set_abort_callback(ggml_backend_t backend, ggml_abort_callback abort_callback, void * user_data); -GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_metal_buffer_type(void); - // helper to check if the device supports a specific family // ideally, the user code should be doing these checks // ref: https://developer.apple.com/metal/Metal-Feature-Set-Tables.pdf diff -pruN 5882+dfsg-2/ggml/include/ggml-opt.h 6641+dfsg-2/ggml/include/ggml-opt.h --- 5882+dfsg-2/ggml/include/ggml-opt.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-opt.h 2025-09-30 07:36:33.000000000 +0000 @@ -74,16 +74,26 @@ extern "C" { GGML_OPT_BUILD_TYPE_OPT = 30, }; + enum ggml_opt_optimizer_type { + GGML_OPT_OPTIMIZER_TYPE_ADAMW, + GGML_OPT_OPTIMIZER_TYPE_SGD, + + GGML_OPT_OPTIMIZER_TYPE_COUNT + }; + // parameters that control which optimizer is used and how said optimizer tries to find the minimal loss struct ggml_opt_optimizer_params { - // AdamW optimizer parameters struct { float alpha; // learning rate - float beta1; - float beta2; + float beta1; // first AdamW momentum + float beta2; // second AdamW momentum float eps; // epsilon for numerical stability - float wd; // weight decay for AdamW, use 0.0f to disable + float wd; // weight decay - 0.0f to disable } adamw; + struct { + float alpha; // learning rate + float wd; // weight decay + } sgd; }; // callback to calculate optimizer parameters prior to a backward pass @@ -112,8 +122,11 @@ extern "C" { int32_t opt_period; // after how many gradient accumulation steps an optimizer step should be done - ggml_opt_get_optimizer_params get_opt_pars; // callback for calculating optimizer parameters - void * get_opt_pars_ud; // userdata for calculating optimizer parameters + ggml_opt_get_optimizer_params get_opt_pars; // callback for calculating optimizer parameters + void * get_opt_pars_ud; // userdata for calculating optimizer parameters + + // only GGML_OPT_OPTIMIZER_TYPE_ADAMW needs m, v momenta per parameter tensor + enum ggml_opt_optimizer_type optimizer; }; // get parameters for an optimization context with defaults set where possible @@ -142,6 +155,10 @@ extern "C" { // get the gradient accumulator for a node from the forward graph GGML_API struct ggml_tensor * ggml_opt_grad_acc(ggml_opt_context_t opt_ctx, struct ggml_tensor * node); + GGML_API enum ggml_opt_optimizer_type ggml_opt_context_optimizer_type(ggml_opt_context_t); //TODO consistent naming scheme + + GGML_API const char * ggml_opt_optimizer_name(enum ggml_opt_optimizer_type); + // ====== Optimization Result ====== GGML_API ggml_opt_result_t ggml_opt_result_init(void); @@ -226,12 +243,14 @@ extern "C" { struct ggml_tensor * outputs, // output tensor, must have shape [ne_label, ndata_batch] if labels are used ggml_opt_dataset_t dataset, // dataset with data and optionally also labels enum ggml_opt_loss_type loss_type, // loss to minimize + enum ggml_opt_optimizer_type optimizer, // sgd or adamw ggml_opt_get_optimizer_params get_opt_pars, // callback to get optimizer params, userdata is pointer to epoch (of type int64_t) int64_t nepoch, // how many times the dataset should be iterated over int64_t nbatch_logical, // datapoints optimizer step, must be a multiple of ndata_batch in inputs/outputs float val_split, // fraction of the dataset to use for validation, must be in [0.0f, 1.0f) bool silent); // whether or not info prints to stderr should be suppressed + #ifdef __cplusplus } #endif diff -pruN 5882+dfsg-2/ggml/include/ggml-webgpu.h 6641+dfsg-2/ggml/include/ggml-webgpu.h --- 5882+dfsg-2/ggml/include/ggml-webgpu.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-webgpu.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,19 @@ +#pragma once + +#include "ggml.h" +#include "ggml-backend.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define GGML_WEBGPU_NAME "WebGPU" + +// Needed for examples in ggml +GGML_BACKEND_API ggml_backend_t ggml_backend_webgpu_init(void); + +GGML_BACKEND_API ggml_backend_reg_t ggml_backend_webgpu_reg(void); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/include/ggml-zdnn.h 6641+dfsg-2/ggml/include/ggml-zdnn.h --- 5882+dfsg-2/ggml/include/ggml-zdnn.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml-zdnn.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,17 @@ +#pragma once + +#include "ggml.h" +#include "ggml-backend.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// device buffer +GGML_BACKEND_API ggml_backend_buffer_type_t ggml_backend_zdnn_buffer_type(void); + +GGML_BACKEND_API ggml_backend_reg_t ggml_backend_zdnn_reg(void); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/include/ggml.h 6641+dfsg-2/ggml/include/ggml.h --- 5882+dfsg-2/ggml/include/ggml.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/include/ggml.h 2025-09-30 07:36:33.000000000 +0000 @@ -241,7 +241,16 @@ #define GGML_ROPE_TYPE_MROPE 8 #define GGML_ROPE_TYPE_VISION 24 +#define GGML_MROPE_SECTIONS 4 + #define GGML_UNUSED(x) (void)(x) +#ifdef __CUDACC__ +template +__host__ __device__ constexpr inline void ggml_unused_vars_impl(Args&&...) noexcept {} +#define GGML_UNUSED_VARS(...) ggml_unused_vars_impl(__VA_ARGS__) +#else +#define GGML_UNUSED_VARS(...) do { (void)sizeof((__VA_ARGS__, 0)); } while(0) +#endif // __CUDACC__ #define GGML_PAD(x, n) (((x) + (n) - 1) & ~((n) - 1)) @@ -275,19 +284,19 @@ // GGML_TENSOR_LOCALS(size_t, nb1, src1, nb); // #define GGML_TENSOR_LOCALS_1(type, prefix, pointer, array) \ - const type prefix##0 = (pointer)->array[0]; \ + const type prefix##0 = (pointer) ? (pointer)->array[0] : 0; \ GGML_UNUSED(prefix##0); #define GGML_TENSOR_LOCALS_2(type, prefix, pointer, array) \ GGML_TENSOR_LOCALS_1 (type, prefix, pointer, array) \ - const type prefix##1 = (pointer)->array[1]; \ + const type prefix##1 = (pointer) ? (pointer)->array[1] : 0; \ GGML_UNUSED(prefix##1); #define GGML_TENSOR_LOCALS_3(type, prefix, pointer, array) \ GGML_TENSOR_LOCALS_2 (type, prefix, pointer, array) \ - const type prefix##2 = (pointer)->array[2]; \ + const type prefix##2 = (pointer) ? (pointer)->array[2] : 0; \ GGML_UNUSED(prefix##2); #define GGML_TENSOR_LOCALS(type, prefix, pointer, array) \ GGML_TENSOR_LOCALS_3 (type, prefix, pointer, array) \ - const type prefix##3 = (pointer)->array[3]; \ + const type prefix##3 = (pointer) ? (pointer)->array[3] : 0; \ GGML_UNUSED(prefix##3); #define GGML_TENSOR_UNARY_OP_LOCALS \ @@ -304,6 +313,16 @@ GGML_TENSOR_LOCALS(int64_t, ne, dst, ne) \ GGML_TENSOR_LOCALS(size_t, nb, dst, nb) +#define GGML_TENSOR_TERNARY_OP_LOCALS \ + GGML_TENSOR_LOCALS(int64_t, ne0, src0, ne) \ + GGML_TENSOR_LOCALS(size_t, nb0, src0, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne1, src1, ne) \ + GGML_TENSOR_LOCALS(size_t, nb1, src1, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne2, src2, ne) \ + GGML_TENSOR_LOCALS(size_t, nb2, src2, nb) \ + GGML_TENSOR_LOCALS(int64_t, ne, dst, ne) \ + GGML_TENSOR_LOCALS(size_t, nb, dst, nb) + #define GGML_TENSOR_BINARY_OP_LOCALS01 \ GGML_TENSOR_LOCALS(int64_t, ne0, src0, ne) \ GGML_TENSOR_LOCALS(size_t, nb0, src0, nb) \ @@ -395,7 +414,8 @@ extern "C" { // GGML_TYPE_IQ4_NL_4_4 = 36, // GGML_TYPE_IQ4_NL_4_8 = 37, // GGML_TYPE_IQ4_NL_8_8 = 38, - GGML_TYPE_COUNT = 39, + GGML_TYPE_MXFP4 = 39, // MXFP4 (1 block) + GGML_TYPE_COUNT = 40, }; // precision @@ -430,6 +450,7 @@ extern "C" { GGML_FTYPE_MOSTLY_IQ4_XS = 22, // except 1d tensors GGML_FTYPE_MOSTLY_IQ1_M = 23, // except 1d tensors GGML_FTYPE_MOSTLY_BF16 = 24, // except 1d tensors + GGML_FTYPE_MOSTLY_MXFP4 = 25, // except 1d tensors }; // available tensor operations: @@ -438,6 +459,7 @@ extern "C" { GGML_OP_DUP, GGML_OP_ADD, + GGML_OP_ADD_ID, GGML_OP_ADD1, GGML_OP_ACC, GGML_OP_SUB, @@ -489,7 +511,9 @@ extern "C" { GGML_OP_CONV_TRANSPOSE_1D, GGML_OP_IM2COL, GGML_OP_IM2COL_BACK, + GGML_OP_IM2COL_3D, GGML_OP_CONV_2D, + GGML_OP_CONV_3D, GGML_OP_CONV_2D_DW, GGML_OP_CONV_TRANSPOSE_2D, GGML_OP_POOL_1D, @@ -527,6 +551,7 @@ extern "C" { GGML_OP_CROSS_ENTROPY_LOSS, GGML_OP_CROSS_ENTROPY_LOSS_BACK, GGML_OP_OPT_STEP_ADAMW, + GGML_OP_OPT_STEP_SGD, GGML_OP_GLU, @@ -557,6 +582,7 @@ extern "C" { GGML_GLU_OP_REGLU, GGML_GLU_OP_GEGLU, GGML_GLU_OP_SWIGLU, + GGML_GLU_OP_SWIGLU_OAI, GGML_GLU_OP_GEGLU_ERF, GGML_GLU_OP_GEGLU_QUICK, @@ -831,6 +857,13 @@ extern "C" { struct ggml_tensor * b, enum ggml_type type); + // dst[i0, i1, i2] = a[i0, i1, i2] + b[i0, ids[i1, i2]] + GGML_API struct ggml_tensor * ggml_add_id( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + struct ggml_tensor * ids); + GGML_API struct ggml_tensor * ggml_add1( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1198,6 +1231,13 @@ extern "C" { struct ggml_tensor * a, struct ggml_tensor * b); + GGML_API struct ggml_tensor * ggml_swiglu_oai( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + float alpha, + float limit); + // normalize along rows GGML_API struct ggml_tensor * ggml_norm( struct ggml_context * ctx, @@ -1364,6 +1404,7 @@ extern "C" { struct ggml_tensor * a, struct ggml_tensor * b); + // note: casting from f32 to i32 will discard the fractional part GGML_API struct ggml_tensor * ggml_cast( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1488,7 +1529,11 @@ extern "C" { struct ggml_context * ctx, struct ggml_tensor * a); - // supports 3D: a->ne[2] == b->ne[1] + // supports 4D a: + // a [n_embd, ne1, ne2, ne3] + // b I32 [n_rows, ne2, ne3, 1] + // + // return [n_embd, n_rows, ne2, ne3] GGML_API struct ggml_tensor * ggml_get_rows( struct ggml_context * ctx, struct ggml_tensor * a, // data @@ -1570,6 +1615,10 @@ extern "C" { float scale, float max_bias); + GGML_API void ggml_soft_max_add_sinks( + struct ggml_tensor * a, + struct ggml_tensor * sinks); + GGML_API struct ggml_tensor * ggml_soft_max_ext_back( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1628,7 +1677,7 @@ extern "C" { struct ggml_tensor * b, struct ggml_tensor * c, int n_dims, - int sections[4], + int sections[GGML_MROPE_SECTIONS], int mode, int n_ctx_orig, float freq_base, @@ -1654,6 +1703,22 @@ extern "C" { float beta_fast, float beta_slow); + GGML_API struct ggml_tensor * ggml_rope_multi_inplace( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + struct ggml_tensor * c, + int n_dims, + int sections[GGML_MROPE_SECTIONS], + int mode, + int n_ctx_orig, + float freq_base, + float freq_scale, + float ext_factor, + float attn_factor, + float beta_fast, + float beta_slow); + GGML_DEPRECATED(GGML_API struct ggml_tensor * ggml_rope_custom( struct ggml_context * ctx, struct ggml_tensor * a, @@ -1811,6 +1876,41 @@ extern "C" { int d0, // dilation dimension 0 int d1); // dilation dimension 1 + GGML_API struct ggml_tensor * ggml_im2col_3d( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + int64_t IC, + int s0, // stride width + int s1, // stride height + int s2, // stride depth + int p0, // padding width + int p1, // padding height + int p2, // padding depth + int d0, // dilation width + int d1, // dilation height + int d2, // dilation depth + enum ggml_type dst_type); + + // a: [OC*IC, KD, KH, KW] + // b: [N*IC, ID, IH, IW] + // result: [N*OC, OD, OH, OW] + GGML_API struct ggml_tensor * ggml_conv_3d( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * b, + int64_t IC, + int s0, // stride width + int s1, // stride height + int s2, // stride depth + int p0, // padding width + int p1, // padding height + int p2, // padding depth + int d0, // dilation width + int d1, // dilation height + int d2 // dilation depth + ); + // kernel size is a->ne[0] x a->ne[1] // stride is equal to kernel size // padding is zero @@ -1882,6 +1982,23 @@ extern "C" { int d0, // dilation dimension 0 int d1); // dilation dimension 1 + GGML_API struct ggml_tensor * ggml_conv_3d_direct( + struct ggml_context * ctx, + struct ggml_tensor * a, // kernel [KW, KH, KD, IC * OC] + struct ggml_tensor * b, // input [W, H, D, C * N] + int s0, // stride + int s1, + int s2, + int p0, // padding + int p1, + int p2, + int d0, // dilation + int d1, + int d2, + int n_channels, + int n_batch, + int n_channels_out); + enum ggml_op_pool { GGML_OP_POOL_MAX, GGML_OP_POOL_AVG, @@ -1972,6 +2089,19 @@ extern "C" { int p2, int p3); + GGML_API struct ggml_tensor * ggml_pad_ext( + struct ggml_context * ctx, + struct ggml_tensor * a, + int lp0, + int rp0, + int lp1, + int rp1, + int lp2, + int rp2, + int lp3, + int rp3 + ); + // pad each dimension with reflection: [a, b, c, d] -> [b, a, b, c, d, c] GGML_API struct ggml_tensor * ggml_pad_reflect_1d( struct ggml_context * ctx, @@ -2052,6 +2182,10 @@ extern "C" { GGML_API enum ggml_prec ggml_flash_attn_ext_get_prec( const struct ggml_tensor * a); + GGML_API void ggml_flash_attn_ext_add_sinks( + struct ggml_tensor * a, + struct ggml_tensor * sinks); + // TODO: needs to be adapted to ggml_flash_attn_ext GGML_API struct ggml_tensor * ggml_flash_attn_back( struct ggml_context * ctx, @@ -2257,7 +2391,14 @@ extern "C" { struct ggml_tensor * grad, struct ggml_tensor * m, struct ggml_tensor * v, - struct ggml_tensor * adamw_params); // parameters such a the learning rate + struct ggml_tensor * adamw_params); // parameters such as the learning rate + + // stochastic gradient descent step (with weight decay) + GGML_API struct ggml_tensor * ggml_opt_step_sgd( + struct ggml_context * ctx, + struct ggml_tensor * a, + struct ggml_tensor * grad, + struct ggml_tensor * sgd_params); // alpha, weight decay // // automatic differentiation diff -pruN 5882+dfsg-2/ggml/src/CMakeLists.txt 6641+dfsg-2/ggml/src/CMakeLists.txt --- 5882+dfsg-2/ggml/src/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -114,6 +114,9 @@ message(STATUS "GGML_SYSTEM_ARCH: ${GGML if (NOT MSVC) if (GGML_STATIC) + if (UNIX AND NOT APPLE) + set(CMAKE_FIND_LIBRARY_SUFFIXES ".a;.so") + endif() add_link_options(-static) if (MINGW) add_link_options(-static-libgcc -static-libstdc++) @@ -214,6 +217,13 @@ add_library(ggml ggml-backend-reg.cpp) add_library(ggml::ggml ALIAS ggml) +if (GGML_BACKEND_DIR) + if (NOT GGML_BACKEND_DL) + message(FATAL_ERROR "GGML_BACKEND_DIR requires GGML_BACKEND_DL") + endif() + target_compile_definitions(ggml PUBLIC GGML_BACKEND_DIR="${GGML_BACKEND_DIR}") +endif() + target_link_libraries(ggml PUBLIC ggml-base) if (CMAKE_SYSTEM_NAME MATCHES "Linux") @@ -227,7 +237,11 @@ function(ggml_add_backend_library backen set_target_properties(${backend} PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}) target_compile_definitions(${backend} PRIVATE GGML_BACKEND_DL) add_dependencies(ggml ${backend}) - install(TARGETS ${backend} LIBRARY DESTINATION ${CMAKE_INSTALL_BINDIR}) + if (GGML_BACKEND_DIR) + install(TARGETS ${backend} LIBRARY DESTINATION ${GGML_BACKEND_DIR}) + else() + install(TARGETS ${backend} LIBRARY DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif() else() add_library(${backend} ${ARGN}) target_link_libraries(ggml PUBLIC ${backend}) @@ -370,6 +384,8 @@ ggml_add_backend(MUSA) ggml_add_backend(RPC) ggml_add_backend(SYCL) ggml_add_backend(Vulkan) +ggml_add_backend(WebGPU) +ggml_add_backend(zDNN) ggml_add_backend(OpenCL) foreach (target ggml-base ggml) diff -pruN 5882+dfsg-2/ggml/src/ggml-alloc.c 6641+dfsg-2/ggml/src/ggml-alloc.c --- 5882+dfsg-2/ggml/src/ggml-alloc.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-alloc.c 2025-09-30 07:36:33.000000000 +0000 @@ -22,28 +22,14 @@ static bool ggml_is_view(const struct gg return t->view_src != NULL; } -static bool ggml_are_same_layout(const struct ggml_tensor * a, const struct ggml_tensor * b) { - if (a->type != b->type) { - return false; - } - for (int i = 0; i < GGML_MAX_DIMS; i++) { - if (a->ne[i] != b->ne[i]) { - return false; - } - if (a->nb[i] != b->nb[i]) { - return false; - } - } - return true; -} - // ops that return true for this function must not use restrict pointers for their backend implementations -static bool ggml_op_can_inplace(enum ggml_op op) { +bool ggml_op_can_inplace(enum ggml_op op) { switch (op) { case GGML_OP_SCALE: case GGML_OP_DIAG_MASK_ZERO: case GGML_OP_DIAG_MASK_INF: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_SUB: case GGML_OP_MUL: @@ -109,39 +95,104 @@ enum ggml_status ggml_tallocr_alloc(stru // dynamic tensor allocator +#define GGML_VBUFFER_MAX_CHUNKS 16 + +// relative memory address within an allocation that can be split into multiple buffers (chunks) +struct buffer_address { + int chunk; // index of a backend buffer + size_t offset; // local memory offset within the buffer +}; + +static const struct buffer_address GGML_BUFFER_ADDRESS_INVALID = { -1, SIZE_MAX }; + +static bool ggml_buffer_address_less(struct buffer_address a, struct buffer_address b) { + return a.chunk != b.chunk ? a.chunk < b.chunk : a.offset < b.offset; +} + struct free_block { size_t offset; size_t size; }; -struct ggml_dyn_tallocr { - size_t alignment; - int n_free_blocks; +struct tallocr_chunk { struct free_block free_blocks[MAX_FREE_BLOCKS]; + int n_free_blocks; size_t max_size; +}; + +struct ggml_dyn_tallocr { + size_t alignment; + size_t max_chunk_size; + struct tallocr_chunk * chunks[GGML_VBUFFER_MAX_CHUNKS]; + int n_chunks; #ifdef GGML_ALLOCATOR_DEBUG struct { const struct ggml_tensor * tensor; - size_t offset; + struct buffer_address addr; } allocated_tensors[1024]; #endif }; +static void ggml_dyn_tallocr_insert_block(struct tallocr_chunk * chunk, size_t offset, size_t size) { + GGML_ASSERT(chunk->n_free_blocks < MAX_FREE_BLOCKS && "out of free blocks"); + // insert the new block in the correct position to keep the array sorted by address (to make merging blocks faster) + int insert_pos = 0; + while (insert_pos < chunk->n_free_blocks && chunk->free_blocks[insert_pos].offset < offset) { + insert_pos++; + } + // shift all blocks from insert_pos onward to make room for the new block + for (int i = chunk->n_free_blocks; i > insert_pos; i--) { + chunk->free_blocks[i] = chunk->free_blocks[i-1]; + } + // insert the new block + chunk->free_blocks[insert_pos].offset = offset; + chunk->free_blocks[insert_pos].size = size; + chunk->n_free_blocks++; +} + +static void ggml_dyn_tallocr_remove_block(struct tallocr_chunk * chunk, int idx) { + // shift all elements after idx by 1 to the left, overwriting the element at idx + for (int i = idx; i < chunk->n_free_blocks; i++) { + chunk->free_blocks[i] = chunk->free_blocks[i+1]; + } + chunk->n_free_blocks--; +} + +static int ggml_dyn_tallocr_new_chunk(struct ggml_dyn_tallocr * alloc, size_t min_size) { + if (alloc->n_chunks >= GGML_VBUFFER_MAX_CHUNKS) { + return -1; + } + struct tallocr_chunk * chunk = calloc(1, sizeof(struct tallocr_chunk)); + chunk->n_free_blocks = 1; + chunk->free_blocks[0].offset = 0; + // available space in a chunk is limited to max_chunk_size, but can be higher if: + // 1. a single tensor exceeds the maximum, and cannot fit any other way + // 2. we are running out of chunks + // backends will either manage to allocate the larger size, or report an error. + chunk->free_blocks[0].size = MAX(min_size, alloc->max_chunk_size); + if (alloc->n_chunks == GGML_VBUFFER_MAX_CHUNKS - 1) { + chunk->free_blocks[0].size = SIZE_MAX/2; + } + alloc->chunks[alloc->n_chunks] = chunk; + alloc->n_chunks++; + return alloc->n_chunks - 1; +} + #ifdef GGML_ALLOCATOR_DEBUG -static void add_allocated_tensor(struct ggml_dyn_tallocr * alloc, size_t offset, const struct ggml_tensor * tensor) { +static void add_allocated_tensor(struct ggml_dyn_tallocr * alloc, struct buffer_address addr, const struct ggml_tensor * tensor) { for (int i = 0; i < 1024; i++) { if (alloc->allocated_tensors[i].tensor == NULL) { alloc->allocated_tensors[i].tensor = tensor; - alloc->allocated_tensors[i].offset = offset; + alloc->allocated_tensors[i].addr = addr; return; } } GGML_ABORT("out of allocated_tensors"); } -static void remove_allocated_tensor(struct ggml_dyn_tallocr * alloc, size_t offset, const struct ggml_tensor * tensor) { +static void remove_allocated_tensor(struct ggml_dyn_tallocr * alloc, struct buffer_address addr, const struct ggml_tensor * tensor) { for (int i = 0; i < 1024; i++) { - if (alloc->allocated_tensors[i].offset == offset) { + if (alloc->allocated_tensors[i].addr.chunk == addr.chunk && alloc->allocated_tensors[i].addr.offset == addr.offset) { alloc->allocated_tensors[i].tensor = NULL; return; } @@ -150,76 +201,94 @@ static void remove_allocated_tensor(stru } #endif -static size_t ggml_dyn_tallocr_alloc(struct ggml_dyn_tallocr * alloc, size_t size, const struct ggml_tensor * tensor) { +static struct buffer_address ggml_dyn_tallocr_alloc(struct ggml_dyn_tallocr * alloc, size_t size, const struct ggml_tensor * tensor) { size = aligned_offset(NULL, size, alloc->alignment); AT_PRINTF("%s: allocating %s (%zu bytes) - ", __func__, tensor->name, size); + int best_fit_chunk = -1; + int best_fit_block = -1; size_t max_avail = 0; - // find the best fitting free block besides the last block - int best_fit_block = -1; - size_t best_fit_size = SIZE_MAX; - for (int i = 0; i < alloc->n_free_blocks - 1; i++) { - struct free_block * block = &alloc->free_blocks[i]; - max_avail = MAX(max_avail, block->size); - if (block->size >= size && block->size <= best_fit_size) { - best_fit_block = i; - best_fit_size = block->size; + // find the best fitting free block besides the last block, within any chunk + for (int c = 0; c < alloc->n_chunks; ++c) { + struct tallocr_chunk * chunk = alloc->chunks[c]; + size_t best_fit_size = SIZE_MAX; + for (int i = 0; i < chunk->n_free_blocks - 1; i++) { + struct free_block * block = &chunk->free_blocks[i]; + max_avail = MAX(max_avail, block->size); + if (block->size >= size && block->size <= best_fit_size) { + best_fit_chunk = c; + best_fit_block = i; + best_fit_size = block->size; + } } } if (best_fit_block == -1) { - // the last block is our last resort - struct free_block * block = &alloc->free_blocks[alloc->n_free_blocks - 1]; - max_avail = MAX(max_avail, block->size); - if (block->size >= size) { - best_fit_block = alloc->n_free_blocks - 1; - } else { - // this should never happen - GGML_LOG_ERROR("%s: not enough space in the buffer to allocate %zu bytes, largest block available %zu bytes\n", - __func__, size, max_avail); - GGML_ABORT("not enough space in the buffer"); + // no suitable block found, try the last block (this will grow a chunks size) + for (int c = 0; c < alloc->n_chunks; ++c) { + struct tallocr_chunk * chunk = alloc->chunks[c]; + if (chunk->n_free_blocks > 0) { + struct free_block * block = &chunk->free_blocks[chunk->n_free_blocks - 1]; + max_avail = MAX(max_avail, block->size); + if (block->size >= size) { + best_fit_chunk = c; + best_fit_block = chunk->n_free_blocks - 1; + break; + } + } } } - struct free_block * block = &alloc->free_blocks[best_fit_block]; - size_t offset = block->offset; - block->offset = offset + size; + if (best_fit_block == -1) { + // none of the existing chunks have enough space left + best_fit_chunk = ggml_dyn_tallocr_new_chunk(alloc, size); + best_fit_block = 0; + } + if (best_fit_chunk == -1) { + // since the last chunk always has virtually endless memory, this should never happen + GGML_LOG_ERROR("%s: not enough space in the buffer to allocate %zu bytes, largest block available %zu bytes\n", + __func__, size, max_avail); + GGML_ABORT("graph allocation: failed to reserve memory"); + } + + struct tallocr_chunk * chunk = alloc->chunks[best_fit_chunk]; + struct free_block * block = &chunk->free_blocks[best_fit_block]; + struct buffer_address addr = {.chunk = best_fit_chunk, .offset = block->offset }; + block->offset += size; block->size -= size; if (block->size == 0) { // remove block if empty - alloc->n_free_blocks--; - for (int j = best_fit_block; j < alloc->n_free_blocks; j++) { - alloc->free_blocks[j] = alloc->free_blocks[j+1]; - } + ggml_dyn_tallocr_remove_block(chunk, best_fit_block); } - AT_PRINTF("block %d, offset %zu\n", best_fit_block, offset); + AT_PRINTF("block %d, offset %zu, chunk %d\n", best_fit_block, addr.offset, addr.chunk); #ifdef GGML_ALLOCATOR_DEBUG - add_allocated_tensor(alloc, offset, tensor); - size_t cur_max = offset + size; - if (cur_max > alloc->max_size) { - // sort allocated_tensors by offset + add_allocated_tensor(alloc, addr, tensor); + size_t cur_max = addr.offset + size; + if (cur_max > alloc->max_size[addr.chunk]) { + // sort allocated_tensors by chunk/offset for (int i = 0; i < 1024; i++) { for (int j = i + 1; j < 1024; j++) { - if (alloc->allocated_tensors[i].offset > alloc->allocated_tensors[j].offset) { + if (ggml_buffer_address_less(alloc->allocated_tensors[j].addr, alloc->allocated_tensors[i].addr)) { const struct ggml_tensor * tmp_tensor = alloc->allocated_tensors[i].tensor; - size_t tmp_offset = alloc->allocated_tensors[i].offset; + struct buffer_address tmp_addr = alloc->allocated_tensors[i].addr; alloc->allocated_tensors[i].tensor = alloc->allocated_tensors[j].tensor; - alloc->allocated_tensors[i].offset = alloc->allocated_tensors[j].offset; + alloc->allocated_tensors[i].addr = alloc->allocated_tensors[j].addr; alloc->allocated_tensors[j].tensor = tmp_tensor; - alloc->allocated_tensors[j].offset = tmp_offset; + alloc->allocated_tensors[j].addr = tmp_addr; } } } - GGML_LOG_DEBUG("max_size = %.2f MB: tensors: ", cur_max / 1024.0 / 1024.0); + GGML_LOG_DEBUG("max_size[%d] = %.2f MB: tensors: ", addr.chunk, cur_max / 1024.0 / 1024.0); for (int i = 0; i < 1024; i++) { if (alloc->allocated_tensors[i].tensor) { - GGML_LOG_DEBUG("%s [%zx-%zx] (%.2f MB) ", alloc->allocated_tensors[i].tensor->name, - alloc->allocated_tensors[i].offset, - alloc->allocated_tensors[i].offset + ggml_nbytes(alloc->allocated_tensors[i].tensor), + GGML_LOG_DEBUG("%s [%d: %zx-%zx] (%.2f MB) ", alloc->allocated_tensors[i].tensor->name, + alloc->allocated_tensors[i].addr.chunk, + alloc->allocated_tensors[i].addr.offset, + alloc->allocated_tensors[i].addr.offset + ggml_nbytes(alloc->allocated_tensors[i].tensor), ggml_nbytes(alloc->allocated_tensors[i].tensor) / 1024.0 / 1024.0); } } @@ -227,78 +296,69 @@ static size_t ggml_dyn_tallocr_alloc(str } #endif - alloc->max_size = MAX(alloc->max_size, offset + size); + chunk->max_size = MAX(chunk->max_size, addr.offset + size); - return offset; + return addr; GGML_UNUSED(tensor); } // this is a very naive implementation, but for our case the number of free blocks should be very small -static void ggml_dyn_tallocr_free_tensor(struct ggml_dyn_tallocr * alloc, size_t offset, size_t size, const struct ggml_tensor * tensor) { +static void ggml_dyn_tallocr_free_tensor(struct ggml_dyn_tallocr * alloc, struct buffer_address addr, size_t size, const struct ggml_tensor * tensor) { size = aligned_offset(NULL, size, alloc->alignment); - AT_PRINTF("%s: freeing %s at %zu (%zu bytes) - n_free_blocks = %d\n", __func__, tensor->name, offset, size, alloc->n_free_blocks); + AT_PRINTF("%s: freeing %s at {chunk=%d, offset=%zu} (%zu bytes) - n_free_blocks = %d\n", + __func__, tensor->name, addr.chunk, addr.offset, size, alloc->chunks[addr.chunk]->n_free_blocks); #ifdef GGML_ALLOCATOR_DEBUG - remove_allocated_tensor(alloc, offset, tensor); + remove_allocated_tensor(alloc, addr, tensor); #endif + struct tallocr_chunk * chunk = alloc->chunks[addr.chunk]; + // see if we can merge with an existing block - for (int i = 0; i < alloc->n_free_blocks; i++) { - struct free_block * block = &alloc->free_blocks[i]; + for (int i = 0; i < chunk->n_free_blocks; i++) { + struct free_block * block = &chunk->free_blocks[i]; // check if ptr is at the end of the block - if (block->offset + block->size == offset) { + if (block->offset + block->size == addr.offset) { block->size += size; // check if we can merge with the next block - if (i < alloc->n_free_blocks - 1 && block->offset + block->size == alloc->free_blocks[i+1].offset) { - block->size += alloc->free_blocks[i+1].size; - alloc->n_free_blocks--; - for (int j = i+1; j < alloc->n_free_blocks; j++) { - alloc->free_blocks[j] = alloc->free_blocks[j+1]; + if (i < chunk->n_free_blocks - 1) { + struct free_block * next = &chunk->free_blocks[i+1]; + if (block->offset + block->size == next->offset) { + block->size += next->size; + ggml_dyn_tallocr_remove_block(chunk, i+1); } } return; } // check if ptr is at the beginning of the block - if (offset + size == block->offset) { - block->offset = offset; + if (addr.offset + size == block->offset) { + block->offset = addr.offset; block->size += size; // check if we can merge with the previous block - if (i > 0 && alloc->free_blocks[i-1].offset + alloc->free_blocks[i-1].size == block->offset) { - alloc->free_blocks[i-1].size += block->size; - alloc->n_free_blocks--; - for (int j = i; j < alloc->n_free_blocks; j++) { - alloc->free_blocks[j] = alloc->free_blocks[j+1]; + if (i > 0) { + struct free_block * prev = &chunk->free_blocks[i-1]; + if (prev->offset + prev->size == block->offset) { + prev->size += block->size; + ggml_dyn_tallocr_remove_block(chunk, i); } } return; } } // otherwise, add a new block - GGML_ASSERT(alloc->n_free_blocks < MAX_FREE_BLOCKS && "out of free blocks"); - // insert the new block in the correct position to keep the array sorted by address (to make merging blocks faster) - int insert_pos = 0; - while (insert_pos < alloc->n_free_blocks && alloc->free_blocks[insert_pos].offset < offset) { - insert_pos++; - } - // shift all blocks from insert_pos onward to make room for the new block - for (int i = alloc->n_free_blocks; i > insert_pos; i--) { - alloc->free_blocks[i] = alloc->free_blocks[i-1]; - } - // insert the new block - alloc->free_blocks[insert_pos].offset = offset; - alloc->free_blocks[insert_pos].size = size; - alloc->n_free_blocks++; + ggml_dyn_tallocr_insert_block(chunk, addr.offset, size); GGML_UNUSED(tensor); } static void ggml_dyn_tallocr_reset(struct ggml_dyn_tallocr * alloc) { - alloc->n_free_blocks = 1; - alloc->free_blocks[0].offset = 0; - alloc->free_blocks[0].size = SIZE_MAX/2; // restrict maximum size of a measure allocator to half size_t max to avoid overflows - alloc->max_size = 0; + for (int i = 0; i < GGML_VBUFFER_MAX_CHUNKS; i++) { + free(alloc->chunks[i]); + alloc->chunks[i] = NULL; + } + alloc->n_chunks = 0; #ifdef GGML_ALLOCATOR_DEBUG for (int i = 0; i < 1024; i++) { @@ -307,14 +367,14 @@ static void ggml_dyn_tallocr_reset(struc #endif } -static struct ggml_dyn_tallocr * ggml_dyn_tallocr_new(size_t alignment) { +static struct ggml_dyn_tallocr * ggml_dyn_tallocr_new(size_t alignment, size_t max_buffer_size) { struct ggml_dyn_tallocr * alloc = (struct ggml_dyn_tallocr *)malloc(sizeof(struct ggml_dyn_tallocr)); *alloc = (struct ggml_dyn_tallocr) { - /*.alignment = */ alignment, - /*.n_free_blocks = */ 0, - /*.free_blocks = */ {{0}}, - /*.max_size = */ 0, + /*.alignment = */ alignment, + /*.max_chunk_size = */ MIN(max_buffer_size, SIZE_MAX/2), // clamp to avoid overflows + /*.chunks = */ {NULL}, + /*.n_chunks = */ 0, #ifdef GGML_ALLOCATOR_DEBUG /*.allocated_tensors = */ {{0}}, #endif @@ -326,11 +386,79 @@ static struct ggml_dyn_tallocr * ggml_dy } static void ggml_dyn_tallocr_free(struct ggml_dyn_tallocr * alloc) { + for (int i = 0; i < alloc->n_chunks; ++i) { + free(alloc->chunks[i]); + } free(alloc); } static size_t ggml_dyn_tallocr_max_size(struct ggml_dyn_tallocr * alloc) { - return alloc->max_size; + size_t max_size = 0; + for (int i = 0; i < alloc->n_chunks; i++) { + max_size += alloc->chunks[i]->max_size; + } + return max_size; +} + + +// virtual buffer with contiguous memory range, split into multiple backend buffers (chunks) + +struct vbuffer { + ggml_backend_buffer_t chunks[GGML_VBUFFER_MAX_CHUNKS]; +}; + +static void ggml_vbuffer_free(struct vbuffer * buf) { + if (buf == NULL) { + return; + } + for (int i = 0; i < GGML_VBUFFER_MAX_CHUNKS; ++i) { + ggml_backend_buffer_free(buf->chunks[i]); + } + free(buf); +} + +static int ggml_vbuffer_n_chunks(struct vbuffer * buf) { + int n = 0; + while (n < GGML_VBUFFER_MAX_CHUNKS && buf->chunks[n]) n++; + return n; +} + +static size_t ggml_vbuffer_size(struct vbuffer * buf) { + size_t size = 0; + for (int i = 0; i < GGML_VBUFFER_MAX_CHUNKS && buf->chunks[i]; ++i) { + size += ggml_backend_buffer_get_size(buf->chunks[i]); + } + return size; +} + +static struct vbuffer * ggml_vbuffer_alloc(ggml_backend_buffer_type_t buft, const struct ggml_dyn_tallocr * talloc, enum ggml_backend_buffer_usage usage) { + struct vbuffer * buf = (struct vbuffer *)calloc(1, sizeof(struct vbuffer)); + if (buf == NULL) { + return NULL; + } + + for (int n = 0; n < talloc->n_chunks; n++) { + size_t chunk_size = talloc->chunks[n]->max_size; + buf->chunks[n] = ggml_backend_buft_alloc_buffer(buft, chunk_size); + if (buf->chunks[n] == NULL) { + ggml_vbuffer_free(buf); + return NULL; + } + ggml_backend_buffer_set_usage(buf->chunks[n], usage); + } + return buf; +} + +static void ggml_vbuffer_tensor_alloc(struct vbuffer * buf, struct ggml_tensor * tensor, struct buffer_address buf_addr) { + void * base = ggml_backend_buffer_get_base(buf->chunks[buf_addr.chunk]); + void * addr = (char *)base + buf_addr.offset; + ggml_backend_tensor_alloc(buf->chunks[buf_addr.chunk], tensor, addr); +} + +static void ggml_vbuffer_reset(struct vbuffer * buf) { + for (int i = 0; i < GGML_VBUFFER_MAX_CHUNKS && buf->chunks[i]; ++i) { + ggml_backend_buffer_reset(buf->chunks[i]); + } } @@ -342,13 +470,13 @@ struct hash_node { int n_children; int n_views; int buffer_id; - size_t offset; // offset within the buffer + struct buffer_address addr; bool allocated; }; struct tensor_alloc { int buffer_id; - size_t offset; + struct buffer_address addr; size_t size_max; // 0 = pre-allocated, unused, or view }; @@ -363,7 +491,7 @@ struct node_alloc { struct ggml_gallocr { ggml_backend_buffer_type_t * bufts; // [n_buffers] - ggml_backend_buffer_t * buffers; // [n_buffers] + struct vbuffer ** buffers; // [n_buffers] struct ggml_dyn_tallocr ** buf_tallocs; // [n_buffers] int n_buffers; @@ -384,7 +512,7 @@ ggml_gallocr_t ggml_gallocr_new_n(ggml_b galloc->bufts = calloc(n_bufs, sizeof(ggml_backend_buffer_type_t)); GGML_ASSERT(galloc->bufts != NULL); - galloc->buffers = calloc(n_bufs, sizeof(ggml_backend_buffer_t)); + galloc->buffers = calloc(n_bufs, sizeof(struct vbuffer *)); GGML_ASSERT(galloc->buffers != NULL); galloc->buf_tallocs = calloc(n_bufs, sizeof(struct ggml_dyn_tallocr *)); @@ -404,7 +532,8 @@ ggml_gallocr_t ggml_gallocr_new_n(ggml_b if (galloc->buf_tallocs[i] == NULL) { size_t alignment = ggml_backend_buft_get_alignment(bufts[i]); - galloc->buf_tallocs[i] = ggml_dyn_tallocr_new(alignment); + size_t max_size = ggml_backend_buft_get_max_size(bufts[i]); + galloc->buf_tallocs[i] = ggml_dyn_tallocr_new(alignment, max_size); } } galloc->n_buffers = n_bufs; @@ -432,7 +561,7 @@ void ggml_gallocr_free(ggml_gallocr_t ga } } if (!freed) { - ggml_backend_buffer_free(galloc->buffers[i]); + ggml_vbuffer_free(galloc->buffers[i]); } } if (galloc->buf_tallocs != NULL) { @@ -481,7 +610,7 @@ static void ggml_gallocr_allocate_node(g if (!ggml_gallocr_is_allocated(galloc, node) && !ggml_is_view(node)) { hn->allocated = true; - assert(hn->offset == 0); + assert(hn->addr.offset == 0); // try to reuse a parent's buffer (inplace) if (ggml_op_can_inplace(node->op)) { @@ -515,9 +644,9 @@ static void ggml_gallocr_allocate_node(g struct hash_node * view_src_hn = ggml_gallocr_hash_get(galloc, view_src); if (view_src_hn->n_views == 1 && view_src_hn->n_children == 0 && view_src->data == parent->data) { AT_PRINTF("reusing view parent %s (%s) for %s\n", parent->name, view_src->name, node->name); - assert(view_src_hn->offset == p_hn->offset); + assert(view_src_hn->addr.chunk == p_hn->addr.chunk && view_src_hn->addr.offset == p_hn->addr.offset); hn->buffer_id = p_hn->buffer_id; - hn->offset = p_hn->offset; + hn->addr = p_hn->addr; p_hn->allocated = false; // avoid freeing the parent view_src_hn->allocated = false; return; @@ -525,7 +654,7 @@ static void ggml_gallocr_allocate_node(g } else { AT_PRINTF("reusing parent %s for %s\n", parent->name, node->name); hn->buffer_id = p_hn->buffer_id; - hn->offset = p_hn->offset; + hn->addr = p_hn->addr; p_hn->allocated = false; // avoid freeing the parent return; } @@ -536,9 +665,8 @@ static void ggml_gallocr_allocate_node(g struct ggml_dyn_tallocr * alloc = galloc->buf_tallocs[buffer_id]; ggml_backend_buffer_type_t buft = galloc->bufts[buffer_id]; size_t size = ggml_backend_buft_get_alloc_size(buft, node); - size_t offset = ggml_dyn_tallocr_alloc(alloc, size, node); hn->buffer_id = buffer_id; - hn->offset = offset; + hn->addr = ggml_dyn_tallocr_alloc(alloc, size, node); } } @@ -550,12 +678,11 @@ static void ggml_gallocr_free_node(ggml_ } struct hash_node * hn = ggml_gallocr_hash_get(galloc, node); - size_t offset = hn->offset; int buffer_id = hn->buffer_id; struct ggml_dyn_tallocr * alloc = galloc->buf_tallocs[buffer_id]; ggml_backend_buffer_type_t buft = galloc->bufts[buffer_id]; size_t size = ggml_backend_buft_get_alloc_size(buft, node); - ggml_dyn_tallocr_free_tensor(alloc, offset, size, node); + ggml_dyn_tallocr_free_tensor(alloc, hn->addr, size, node); hn->allocated = false; } @@ -706,24 +833,24 @@ bool ggml_gallocr_reserve_n(ggml_gallocr struct node_alloc * node_alloc = &galloc->node_allocs[i]; if (node->view_src || node->data) { node_alloc->dst.buffer_id = -1; - node_alloc->dst.offset = SIZE_MAX; + node_alloc->dst.addr = GGML_BUFFER_ADDRESS_INVALID; node_alloc->dst.size_max = 0; } else { struct hash_node * hn = ggml_gallocr_hash_get(galloc, node); node_alloc->dst.buffer_id = hn->buffer_id; - node_alloc->dst.offset = hn->offset; + node_alloc->dst.addr = hn->addr; node_alloc->dst.size_max = ggml_backend_buft_get_alloc_size(galloc->bufts[hn->buffer_id], node); } for (int j = 0; j < GGML_MAX_SRC; j++) { struct ggml_tensor * src = node->src[j]; if (!src || src->view_src || src->data) { node_alloc->src[j].buffer_id = -1; - node_alloc->src[j].offset = SIZE_MAX; + node_alloc->src[j].addr = GGML_BUFFER_ADDRESS_INVALID; node_alloc->src[j].size_max = 0; } else { struct hash_node * hn = ggml_gallocr_hash_get(galloc, src); node_alloc->src[j].buffer_id = hn->buffer_id; - node_alloc->src[j].offset = hn->offset; + node_alloc->src[j].addr = hn->addr; node_alloc->src[j].size_max = ggml_backend_buft_get_alloc_size(galloc->bufts[hn->buffer_id], src); } } @@ -739,11 +866,11 @@ bool ggml_gallocr_reserve_n(ggml_gallocr struct hash_node * hn = ggml_gallocr_hash_get(galloc, leaf); if (leaf->view_src || leaf->data) { galloc->leaf_allocs[i].leaf.buffer_id = -1; - galloc->leaf_allocs[i].leaf.offset = SIZE_MAX; + galloc->leaf_allocs[i].leaf.addr = GGML_BUFFER_ADDRESS_INVALID; galloc->leaf_allocs[i].leaf.size_max = 0; } else { galloc->leaf_allocs[i].leaf.buffer_id = hn->buffer_id; - galloc->leaf_allocs[i].leaf.offset = hn->offset; + galloc->leaf_allocs[i].leaf.addr = hn->addr; galloc->leaf_allocs[i].leaf.size_max = ggml_backend_buft_get_alloc_size(galloc->bufts[hn->buffer_id], leaf); } } @@ -758,7 +885,7 @@ bool ggml_gallocr_reserve_n(ggml_gallocr } } - size_t cur_size = galloc->buffers[i] ? ggml_backend_buffer_get_size(galloc->buffers[i]) : 0; + size_t cur_size = galloc->buffers[i] ? ggml_vbuffer_size(galloc->buffers[i]) : 0; size_t new_size = ggml_dyn_tallocr_max_size(galloc->buf_tallocs[i]); // even if there are no tensors allocated in this buffer, we still need to allocate it to initialize views @@ -767,13 +894,12 @@ bool ggml_gallocr_reserve_n(ggml_gallocr GGML_LOG_DEBUG("%s: reallocating %s buffer from size %.02f MiB to %.02f MiB\n", __func__, ggml_backend_buft_name(galloc->bufts[i]), cur_size / 1024.0 / 1024.0, new_size / 1024.0 / 1024.0); #endif - ggml_backend_buffer_free(galloc->buffers[i]); - galloc->buffers[i] = ggml_backend_buft_alloc_buffer(galloc->bufts[i], new_size); + ggml_vbuffer_free(galloc->buffers[i]); + galloc->buffers[i] = ggml_vbuffer_alloc(galloc->bufts[i], galloc->buf_tallocs[i], GGML_BACKEND_BUFFER_USAGE_COMPUTE); if (galloc->buffers[i] == NULL) { GGML_LOG_ERROR("%s: failed to allocate %s buffer of size %zu\n", __func__, ggml_backend_buft_name(galloc->bufts[i]), new_size); return false; } - ggml_backend_buffer_set_usage(galloc->buffers[i], GGML_BACKEND_BUFFER_USAGE_COMPUTE); } } @@ -786,11 +912,11 @@ bool ggml_gallocr_reserve(ggml_gallocr_t static void ggml_gallocr_init_tensor(ggml_gallocr_t galloc, struct ggml_tensor * tensor, struct tensor_alloc * tensor_alloc) { int buffer_id = tensor_alloc->buffer_id; - assert(tensor->data || tensor->view_src || ggml_backend_buffer_get_alloc_size(galloc->buffers[buffer_id], tensor) <= tensor_alloc->size_max); + assert(tensor->data || tensor->view_src || ggml_backend_buft_get_alloc_size(galloc->bufts[buffer_id], tensor) <= tensor_alloc->size_max); if (tensor->view_src != NULL) { if (tensor->buffer == NULL) { - assert(tensor_alloc->offset == SIZE_MAX); + assert(tensor_alloc->addr.offset == SIZE_MAX); if (tensor->view_src->buffer == NULL) { // this tensor was allocated without ggml-backend return; @@ -799,11 +925,9 @@ static void ggml_gallocr_init_tensor(ggm } } else { if (tensor->data == NULL) { - assert(tensor_alloc->offset != SIZE_MAX); - assert(ggml_backend_buffer_get_alloc_size(galloc->buffers[buffer_id], tensor) <= tensor_alloc->size_max); - void * base = ggml_backend_buffer_get_base(galloc->buffers[buffer_id]); - void * addr = (char *)base + tensor_alloc->offset; - ggml_backend_tensor_alloc(galloc->buffers[buffer_id], tensor, addr); + assert(tensor_alloc->addr.offset != SIZE_MAX); + assert(ggml_backend_buft_get_alloc_size(galloc->bufts[buffer_id], tensor) <= tensor_alloc->size_max); + ggml_vbuffer_tensor_alloc(galloc->buffers[buffer_id], tensor, tensor_alloc->addr); } else { if (tensor->buffer == NULL) { // this tensor was allocated without ggml-backend @@ -888,7 +1012,7 @@ bool ggml_gallocr_alloc_graph(ggml_gallo // reset buffers for (int i = 0; i < galloc->n_buffers; i++) { if (galloc->buffers[i] != NULL) { - ggml_backend_buffer_reset(galloc->buffers[i]); + ggml_vbuffer_reset(galloc->buffers[i]); } } @@ -931,7 +1055,7 @@ size_t ggml_gallocr_get_buffer_size(ggml } } - return ggml_backend_buffer_get_size(galloc->buffers[buffer_id]); + return ggml_vbuffer_size(galloc->buffers[buffer_id]); } // utils diff -pruN 5882+dfsg-2/ggml/src/ggml-backend-impl.h 6641+dfsg-2/ggml/src/ggml-backend-impl.h --- 5882+dfsg-2/ggml/src/ggml-backend-impl.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-backend-impl.h 2025-09-30 07:36:33.000000000 +0000 @@ -8,7 +8,7 @@ extern "C" { #endif - #define GGML_BACKEND_API_VERSION 1 + #define GGML_BACKEND_API_VERSION 2 // // Backend buffer type @@ -114,6 +114,9 @@ extern "C" { void (*event_record)(ggml_backend_t backend, ggml_backend_event_t event); // wait for an event on on a different stream void (*event_wait) (ggml_backend_t backend, ggml_backend_event_t event); + + // (optional) sort/optimize the nodes in the graph + void (*graph_optimize) (ggml_backend_t backend, struct ggml_cgraph * cgraph); }; struct ggml_backend { diff -pruN 5882+dfsg-2/ggml/src/ggml-backend-reg.cpp 6641+dfsg-2/ggml/src/ggml-backend-reg.cpp --- 5882+dfsg-2/ggml/src/ggml-backend-reg.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-backend-reg.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -45,6 +45,14 @@ #include "ggml-vulkan.h" #endif +#ifdef GGML_USE_WEBGPU +#include "ggml-webgpu.h" +#endif + +#ifdef GGML_USE_ZDNN +#include "ggml-zdnn.h" +#endif + #ifdef GGML_USE_OPENCL #include "ggml-opencl.h" #endif @@ -127,6 +135,10 @@ static void * dl_get_sym(dl_handle * han return p; } +static const char * dl_error() { + return ""; +} + #else using dl_handle = void; @@ -147,6 +159,11 @@ static void * dl_get_sym(dl_handle * han return dlsym(handle, name); } +static const char * dl_error() { + const char *rslt = dlerror(); + return rslt != nullptr ? rslt : ""; +} + #endif using dl_handle_ptr = std::unique_ptr; @@ -173,6 +190,12 @@ struct ggml_backend_registry { #ifdef GGML_USE_VULKAN register_backend(ggml_backend_vk_reg()); #endif +#ifdef GGML_USE_WEBGPU + register_backend(ggml_backend_webgpu_reg()); +#endif +#ifdef GGML_USE_ZDNN + register_backend(ggml_backend_zdnn_reg()); +#endif #ifdef GGML_USE_OPENCL register_backend(ggml_backend_opencl_reg()); #endif @@ -226,7 +249,7 @@ struct ggml_backend_registry { dl_handle_ptr handle { dl_load_library(path) }; if (!handle) { if (!silent) { - GGML_LOG_ERROR("%s: failed to load %s\n", __func__, path_str(path).c_str()); + GGML_LOG_ERROR("%s: failed to load %s: %s\n", __func__, path_str(path).c_str(), dl_error()); } return nullptr; } @@ -386,9 +409,8 @@ ggml_backend_t ggml_backend_init_by_type ggml_backend_t ggml_backend_init_best(void) { ggml_backend_dev_t dev = ggml_backend_dev_by_type(GGML_BACKEND_DEVICE_TYPE_GPU); - if (!dev) { - dev = ggml_backend_dev_by_type(GGML_BACKEND_DEVICE_TYPE_CPU); - } + dev = dev ? dev : ggml_backend_dev_by_type(GGML_BACKEND_DEVICE_TYPE_IGPU); + dev = dev ? dev : ggml_backend_dev_by_type(GGML_BACKEND_DEVICE_TYPE_CPU); if (!dev) { return nullptr; } @@ -491,6 +513,9 @@ static ggml_backend_reg_t ggml_backend_l std::vector search_paths; if (user_search_path == nullptr) { +#ifdef GGML_BACKEND_DIR + search_paths.push_back(fs::u8path(GGML_BACKEND_DIR)); +#endif // default search paths: executable directory, current directory search_paths.push_back(get_executable_path()); search_paths.push_back(fs::current_path()); @@ -514,7 +539,7 @@ static ggml_backend_reg_t ggml_backend_l if (filename.native().find(file_prefix) == 0 && ext == file_extension) { dl_handle_ptr handle { dl_load_library(entry) }; if (!handle && !silent) { - GGML_LOG_ERROR("%s: failed to load %s\n", __func__, path_str(entry.path()).c_str()); + GGML_LOG_ERROR("%s: failed to load %s: %s\n", __func__, path_str(entry.path()).c_str(), dl_error()); } if (handle) { auto score_fn = (ggml_backend_score_t) dl_get_sym(handle.get(), "ggml_backend_score"); diff -pruN 5882+dfsg-2/ggml/src/ggml-backend.cpp 6641+dfsg-2/ggml/src/ggml-backend.cpp --- 5882+dfsg-2/ggml/src/ggml-backend.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-backend.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -19,9 +19,8 @@ #include #include #include -#include -#include #include +#include #ifdef __APPLE__ #include @@ -32,6 +31,7 @@ // backend buffer type const char * ggml_backend_buft_name(ggml_backend_buffer_type_t buft) { + GGML_ASSERT(buft); return buft->iface.get_name(buft); } @@ -41,14 +41,17 @@ ggml_backend_buffer_t ggml_backend_buft_ return ggml_backend_buffer_init(buft, {}, NULL, 0); } + GGML_ASSERT(buft); return buft->iface.alloc_buffer(buft, size); } size_t ggml_backend_buft_get_alignment(ggml_backend_buffer_type_t buft) { + GGML_ASSERT(buft); return buft->iface.get_alignment(buft); } size_t ggml_backend_buft_get_max_size(ggml_backend_buffer_type_t buft) { + GGML_ASSERT(buft); // get_max_size is optional, defaults to SIZE_MAX if (buft->iface.get_max_size) { return buft->iface.get_max_size(buft); @@ -57,6 +60,7 @@ size_t ggml_backend_buft_get_max_size(gg } size_t ggml_backend_buft_get_alloc_size(ggml_backend_buffer_type_t buft, const struct ggml_tensor * tensor) { + GGML_ASSERT(buft); // get_alloc_size is optional, defaults to ggml_nbytes if (buft->iface.get_alloc_size) { size_t size = buft->iface.get_alloc_size(buft, tensor); @@ -67,6 +71,7 @@ size_t ggml_backend_buft_get_alloc_size( } bool ggml_backend_buft_is_host(ggml_backend_buffer_type_t buft) { + GGML_ASSERT(buft); if (buft->iface.is_host) { return buft->iface.is_host(buft); } @@ -74,6 +79,7 @@ bool ggml_backend_buft_is_host(ggml_back } ggml_backend_dev_t ggml_backend_buft_get_device(ggml_backend_buffer_type_t buft) { + GGML_ASSERT(buft); return buft->device; } @@ -111,10 +117,12 @@ void ggml_backend_buffer_free(ggml_backe } size_t ggml_backend_buffer_get_size(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); return buffer->size; } void * ggml_backend_buffer_get_base(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); // get_base is optional if the buffer is zero-sized if (buffer->size == 0) { return NULL; @@ -128,6 +136,7 @@ void * ggml_backend_buffer_get_base(ggml } enum ggml_status ggml_backend_buffer_init_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor) { + GGML_ASSERT(buffer); // init_tensor is optional if (buffer->iface.init_tensor) { return buffer->iface.init_tensor(buffer, tensor); @@ -136,6 +145,7 @@ enum ggml_status ggml_backend_buffer_ini } void ggml_backend_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { + GGML_ASSERT(buffer); // clear is optional if the buffer is zero-sized if (buffer->size == 0) { return; @@ -161,6 +171,7 @@ bool ggml_backend_buffer_is_host(ggml_ba } void ggml_backend_buffer_set_usage(ggml_backend_buffer_t buffer, enum ggml_backend_buffer_usage usage) { + GGML_ASSERT(buffer); buffer->usage = usage; // FIXME: add a generic callback to the buffer interface @@ -170,14 +181,17 @@ void ggml_backend_buffer_set_usage(ggml_ } enum ggml_backend_buffer_usage ggml_backend_buffer_get_usage(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); return buffer->usage; } ggml_backend_buffer_type_t ggml_backend_buffer_get_type(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); return buffer->buft; } void ggml_backend_buffer_reset(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); if (buffer->iface.reset) { buffer->iface.reset(buffer); } @@ -216,6 +230,7 @@ void ggml_backend_free(ggml_backend_t ba } ggml_backend_buffer_type_t ggml_backend_get_default_buffer_type(ggml_backend_t backend) { + GGML_ASSERT(backend); return ggml_backend_dev_buffer_type(backend->device); } @@ -232,6 +247,8 @@ size_t ggml_backend_get_max_size(ggml_ba } void ggml_backend_tensor_set_async(ggml_backend_t backend, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + GGML_ASSERT(backend); + GGML_ASSERT(tensor); GGML_ASSERT(tensor->data != NULL && "tensor not allocated"); GGML_ASSERT(offset + size <= ggml_nbytes(tensor) && "tensor write out of bounds"); @@ -243,6 +260,8 @@ void ggml_backend_tensor_set_async(ggml_ } void ggml_backend_tensor_get_async(ggml_backend_t backend, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size) { + GGML_ASSERT(backend); + GGML_ASSERT(tensor); GGML_ASSERT(tensor->data != NULL && "tensor not allocated"); GGML_ASSERT(offset + size <= ggml_nbytes(tensor) && "tensor read out of bounds"); @@ -284,6 +303,7 @@ void ggml_backend_tensor_get(const struc } void ggml_backend_tensor_memset(struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { + GGML_ASSERT(tensor); ggml_backend_buffer_t buf = tensor->view_src ? tensor->view_src->buffer : tensor->buffer; if (size == 0) { @@ -299,6 +319,7 @@ void ggml_backend_tensor_memset(struct g } void ggml_backend_synchronize(ggml_backend_t backend) { + GGML_ASSERT(backend); if (backend->iface.synchronize == NULL) { return; } @@ -307,18 +328,21 @@ void ggml_backend_synchronize(ggml_backe } ggml_backend_graph_plan_t ggml_backend_graph_plan_create(ggml_backend_t backend, struct ggml_cgraph * cgraph) { + GGML_ASSERT(backend); GGML_ASSERT(backend->iface.graph_plan_create != NULL); return backend->iface.graph_plan_create(backend, cgraph); } void ggml_backend_graph_plan_free(ggml_backend_t backend, ggml_backend_graph_plan_t plan) { + GGML_ASSERT(backend); GGML_ASSERT(backend->iface.graph_plan_free != NULL); backend->iface.graph_plan_free(backend, plan); } enum ggml_status ggml_backend_graph_plan_compute(ggml_backend_t backend, ggml_backend_graph_plan_t plan) { + GGML_ASSERT(backend); GGML_ASSERT(backend->iface.graph_plan_compute != NULL); return backend->iface.graph_plan_compute(backend, plan); @@ -331,42 +355,32 @@ enum ggml_status ggml_backend_graph_comp } enum ggml_status ggml_backend_graph_compute_async(ggml_backend_t backend, struct ggml_cgraph * cgraph) { + GGML_ASSERT(backend); return backend->iface.graph_compute(backend, cgraph); } bool ggml_backend_supports_op(ggml_backend_t backend, const struct ggml_tensor * op) { + GGML_ASSERT(backend); return ggml_backend_dev_supports_op(backend->device, op); } bool ggml_backend_supports_buft(ggml_backend_t backend, ggml_backend_buffer_type_t buft) { + GGML_ASSERT(backend); return ggml_backend_dev_supports_buft(backend->device, buft); } bool ggml_backend_offload_op(ggml_backend_t backend, const struct ggml_tensor * op) { + GGML_ASSERT(backend); return ggml_backend_dev_offload_op(backend->device, op); } ggml_backend_dev_t ggml_backend_get_device(ggml_backend_t backend) { + GGML_ASSERT(backend); return backend->device; } // backend copy -static bool ggml_are_same_layout(const struct ggml_tensor * a, const struct ggml_tensor * b) { - if (a->type != b->type) { - return false; - } - for (int i = 0; i < GGML_MAX_DIMS; i++) { - if (a->ne[i] != b->ne[i]) { - return false; - } - if (a->nb[i] != b->nb[i]) { - return false; - } - } - return true; -} - void ggml_backend_tensor_copy(struct ggml_tensor * src, struct ggml_tensor * dst) { GGML_ASSERT(ggml_are_same_layout(src, dst) && "cannot copy tensors with different layouts"); @@ -397,6 +411,7 @@ void ggml_backend_tensor_copy_async(ggml return; } + GGML_ASSERT(backend_dst); if (backend_dst->iface.cpy_tensor_async != NULL) { if (backend_dst->iface.cpy_tensor_async(backend_src, backend_dst, src, dst)) { return; @@ -428,38 +443,52 @@ void ggml_backend_event_free(ggml_backen } void ggml_backend_event_record(ggml_backend_event_t event, ggml_backend_t backend) { + GGML_ASSERT(backend); GGML_ASSERT(backend->iface.event_record != NULL); backend->iface.event_record(backend, event); } void ggml_backend_event_synchronize(ggml_backend_event_t event) { + GGML_ASSERT(event); GGML_ASSERT(event->device->iface.event_synchronize); event->device->iface.event_synchronize(event->device, event); } void ggml_backend_event_wait(ggml_backend_t backend, ggml_backend_event_t event) { + GGML_ASSERT(backend); GGML_ASSERT(backend->iface.event_wait != NULL); backend->iface.event_wait(backend, event); } +static void ggml_backend_graph_optimize(ggml_backend_t backend, struct ggml_cgraph * cgraph) { + GGML_ASSERT(backend); + if (backend->iface.graph_optimize != NULL) { + backend->iface.graph_optimize(backend, cgraph); + } +} + // Backend device const char * ggml_backend_dev_name(ggml_backend_dev_t device) { + GGML_ASSERT(device); return device->iface.get_name(device); } const char * ggml_backend_dev_description(ggml_backend_dev_t device) { + GGML_ASSERT(device); return device->iface.get_description(device); } void ggml_backend_dev_memory(ggml_backend_dev_t device, size_t * free, size_t * total) { + GGML_ASSERT(device); device->iface.get_memory(device, free, total); } enum ggml_backend_dev_type ggml_backend_dev_type(ggml_backend_dev_t device) { + GGML_ASSERT(device); return device->iface.get_type(device); } @@ -469,18 +498,22 @@ void ggml_backend_dev_get_props(ggml_bac } ggml_backend_reg_t ggml_backend_dev_backend_reg(ggml_backend_dev_t device) { + GGML_ASSERT(device); return device->reg; } ggml_backend_t ggml_backend_dev_init(ggml_backend_dev_t device, const char * params) { + GGML_ASSERT(device); return device->iface.init_backend(device, params); } ggml_backend_buffer_type_t ggml_backend_dev_buffer_type(ggml_backend_dev_t device) { + GGML_ASSERT(device); return device->iface.get_buffer_type(device); } ggml_backend_buffer_type_t ggml_backend_dev_host_buffer_type(ggml_backend_dev_t device) { + GGML_ASSERT(device); if (device->iface.get_host_buffer_type == NULL) { return NULL; } @@ -489,18 +522,22 @@ ggml_backend_buffer_type_t ggml_backend_ } ggml_backend_buffer_t ggml_backend_dev_buffer_from_host_ptr(ggml_backend_dev_t device, void * ptr, size_t size, size_t max_tensor_size) { + GGML_ASSERT(device); return device->iface.buffer_from_host_ptr(device, ptr, size, max_tensor_size); } bool ggml_backend_dev_supports_op(ggml_backend_dev_t device, const struct ggml_tensor * op) { + GGML_ASSERT(device); return device->iface.supports_op(device, op); } bool ggml_backend_dev_supports_buft(ggml_backend_dev_t device, ggml_backend_buffer_type_t buft) { + GGML_ASSERT(device); return device->iface.supports_buft(device, buft); } bool ggml_backend_dev_offload_op(ggml_backend_dev_t device, const struct ggml_tensor * op) { + GGML_ASSERT(device); if (device->iface.offload_op != NULL) { return device->iface.offload_op(device, op); } @@ -511,18 +548,22 @@ bool ggml_backend_dev_offload_op(ggml_ba // Backend (reg) const char * ggml_backend_reg_name(ggml_backend_reg_t reg) { + GGML_ASSERT(reg); return reg->iface.get_name(reg); } size_t ggml_backend_reg_dev_count(ggml_backend_reg_t reg) { + GGML_ASSERT(reg); return reg->iface.get_device_count(reg); } ggml_backend_dev_t ggml_backend_reg_dev_get(ggml_backend_reg_t reg, size_t index) { + GGML_ASSERT(reg); return reg->iface.get_device(reg, index); } void * ggml_backend_reg_get_proc_address(ggml_backend_reg_t reg, const char * name) { + GGML_ASSERT(reg); if (!reg->iface.get_proc_address) { return NULL; } @@ -537,6 +578,7 @@ struct ggml_backend_multi_buffer_context }; static void ggml_backend_multi_buffer_free_buffer(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); ggml_backend_multi_buffer_context * ctx = (ggml_backend_multi_buffer_context *) buffer->context; for (size_t i = 0; i < ctx->n_buffers; i++) { ggml_backend_buffer_free(ctx->buffers[i]); @@ -547,6 +589,7 @@ static void ggml_backend_multi_buffer_fr } static void ggml_backend_multi_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { + GGML_ASSERT(buffer); ggml_backend_multi_buffer_context * ctx = (ggml_backend_multi_buffer_context *) buffer->context; for (size_t i = 0; i < ctx->n_buffers; i++) { ggml_backend_buffer_clear(ctx->buffers[i], value); @@ -582,10 +625,12 @@ ggml_backend_buffer_t ggml_backend_multi } bool ggml_backend_buffer_is_multi_buffer(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); return buffer->iface.free_buffer == ggml_backend_multi_buffer_free_buffer; } void ggml_backend_multi_buffer_set_usage(ggml_backend_buffer_t buffer, enum ggml_backend_buffer_usage usage) { + GGML_ASSERT(buffer); GGML_ASSERT(ggml_backend_buffer_is_multi_buffer(buffer)); ggml_backend_multi_buffer_context * ctx = (ggml_backend_multi_buffer_context *) buffer->context; for (size_t i = 0; i < ctx->n_buffers; i++) { @@ -613,7 +658,7 @@ static bool ggml_is_view_op(enum ggml_op #endif #ifndef GGML_SCHED_MAX_SPLIT_INPUTS -#define GGML_SCHED_MAX_SPLIT_INPUTS GGML_MAX_SRC +#define GGML_SCHED_MAX_SPLIT_INPUTS 30 #endif #ifndef GGML_SCHED_MAX_COPIES @@ -662,6 +707,7 @@ struct ggml_backend_sched { // pipeline parallelism support int n_copies; int cur_copy; + int next_copy; ggml_backend_event_t events[GGML_SCHED_MAX_BACKENDS][GGML_SCHED_MAX_COPIES]; struct ggml_tensor * graph_inputs[GGML_SCHED_MAX_SPLIT_INPUTS]; int n_graph_inputs; @@ -863,7 +909,7 @@ static void ggml_backend_sched_set_if_su } // assigns backends to ops and splits the graph into subgraphs that can be computed on the same backend -static void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph) { +void ggml_backend_sched_split_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph) { // reset splits sched->n_splits = 0; sched->n_graph_inputs = 0; @@ -1085,6 +1131,11 @@ static void ggml_backend_sched_split_gra } } } + // if the node is still unassigned, assign it to the first backend that supports it + for (int b = 0; b < sched->n_backends && *cur_backend_id == -1; b++) { + ggml_backend_sched_set_if_supported(sched, node, b, cur_backend_id); + } + GGML_ASSERT(*cur_backend_id != -1); } // pass 5: split graph, find tensors that need to be copied @@ -1112,7 +1163,7 @@ static void ggml_backend_sched_split_gra const int node_backend_id = tensor_backend_id(node); - assert(node_backend_id != -1); // all nodes should be assigned by now, this can happen if there is no CPU fallback + GGML_ASSERT(node_backend_id != -1); // all nodes should be assigned by now, this can happen if there is no CPU fallback // check if we should start a new split based on the sources of the current node bool need_new_split = false; @@ -1170,7 +1221,7 @@ static void ggml_backend_sched_split_gra size_t src_id = hash_id(src); const int src_backend_id = sched->hv_tensor_backend_ids[src_id]; - assert(src_backend_id != -1); // all inputs should be assigned by now + GGML_ASSERT(src_backend_id != -1); // all inputs should be assigned by now if (src->flags & GGML_TENSOR_FLAG_INPUT && sched->n_copies > 1) { if (tensor_id_copy(src_id, src_backend_id, 0) == NULL) { @@ -1254,6 +1305,10 @@ static void ggml_backend_sched_split_gra struct ggml_backend_sched_split * split = &sched->splits[i]; split->graph = ggml_graph_view(graph, split->i_start, split->i_end); + // Optimize this split of the graph. This needs to happen before we make graph_copy, + // so they are in sync. + ggml_backend_graph_optimize(sched->backends[split->backend_id], &split->graph); + // add inputs to the graph copy so that they are allocated by ggml-alloc at the start of the split for (int j = 0; j < split->n_inputs; j++) { assert(graph_copy->size > (graph_copy->n_nodes + 1)); @@ -1359,17 +1414,22 @@ static bool ggml_backend_sched_alloc_spl } static enum ggml_status ggml_backend_sched_compute_splits(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); struct ggml_backend_sched_split * splits = sched->splits; - for (int i = 0; i < sched->n_splits; i++) { - struct ggml_backend_sched_split * split = &splits[i]; + ggml_tensor * prev_ids_tensor = nullptr; + std::vector ids; + std::vector used_ids; + + for (int split_id = 0; split_id < sched->n_splits; split_id++) { + struct ggml_backend_sched_split * split = &splits[split_id]; int split_backend_id = split->backend_id; ggml_backend_t split_backend = sched->backends[split_backend_id]; // copy the input tensors to the split backend - for (int j = 0; j < split->n_inputs; j++) { - ggml_backend_t input_backend = ggml_backend_sched_get_tensor_backend(sched, split->inputs[j]); - struct ggml_tensor * input = split->inputs[j]; + for (int input_id = 0; input_id < split->n_inputs; input_id++) { + ggml_backend_t input_backend = ggml_backend_sched_get_tensor_backend(sched, split->inputs[input_id]); + struct ggml_tensor * input = split->inputs[input_id]; struct ggml_tensor * input_cpy = tensor_copy(input, split_backend_id, sched->cur_copy); if (input->flags & GGML_TENSOR_FLAG_INPUT) { @@ -1387,16 +1447,104 @@ static enum ggml_status ggml_backend_sch } else { ggml_backend_synchronize(split_backend); } - // try async copy, but if not possible, we can still use a sync copy without synchronizing the dst backend, since we handle the synchronization here with multiple copies and events - // TODO: add public function to facilitate this, since applications do not have direct access to the backend interface - if (!split_backend->iface.cpy_tensor_async || !split_backend->iface.cpy_tensor_async(input_backend, split_backend, input, input_cpy)) { + + // when offloading MoE weights, we can reduce the amount of data copied by copying only the experts that are used + ggml_tensor * node = split->graph.nodes[0]; + if (split->graph.n_nodes > 0 && + ggml_backend_buffer_get_usage(input->buffer) == GGML_BACKEND_BUFFER_USAGE_WEIGHTS && + ggml_backend_buffer_is_host(input->buffer) && ( + (node->src[0] == input_cpy && node->op == GGML_OP_MUL_MAT_ID) + //|| (node->src[1] == input_cpy && node->op == GGML_OP_ADD_ID) /* GGML_OP_ADD_ID weights are small and not worth splitting */ + )) { + + const int64_t n_expert = node->op == GGML_OP_MUL_MAT_ID ? input->ne[2] : input->ne[1]; + const size_t expert_size = node->op == GGML_OP_MUL_MAT_ID ? input->nb[2] : input->nb[1]; + ggml_backend_synchronize(input_backend); - if (sched->events[split_backend_id][sched->cur_copy] != NULL) { - ggml_backend_event_synchronize(sched->events[split_backend_id][sched->cur_copy]); - } else { - ggml_backend_synchronize(split_backend); + + // get the ids + ggml_tensor * ids_tensor = node->src[2]; + ggml_backend_t ids_backend = split_backend; + + // if the ids tensor is also an input of the split, it may not have been copied yet to the split backend + // in that case, we use the original ids tensor + for (int i = input_id + 1; i < split->n_inputs; i++) { + if (ids_tensor == tensor_copy(split->inputs[i], split_backend_id, sched->cur_copy)) { + ids_tensor = split->inputs[i]; + ids_backend = ggml_backend_sched_get_tensor_backend(sched, split->inputs[i]); + break; + } + } + + if (ids_tensor != prev_ids_tensor) { + ids.resize(ggml_nbytes(ids_tensor) / sizeof(int32_t)); + ggml_backend_tensor_get_async(ids_backend, ids_tensor, ids.data(), 0, ggml_nbytes(ids_tensor)); + ggml_backend_synchronize(ids_backend); + + // find the used experts + used_ids.clear(); + used_ids.resize(ggml_bitset_size(n_expert)); + for (int64_t i1 = 0; i1 < ids_tensor->ne[1]; i1++) { + for (int64_t i0 = 0; i0 < ids_tensor->ne[0]; i0++) { + int32_t id = ids[i1 * ids_tensor->nb[1]/sizeof(int32_t) + i0 * ids_tensor->nb[0]/sizeof(int32_t)]; + GGML_ASSERT(id >= 0 && id < n_expert); + ggml_bitset_set(used_ids.data(), id); + } + } + + prev_ids_tensor = ids_tensor; + } + + // group consecutive experts and copy them together + auto copy_experts = [&](int32_t first_id, int32_t last_id) { + const size_t expert_offset = first_id * expert_size; + const size_t expert_size_copy = (last_id - first_id + 1) * expert_size; + const size_t padding = std::min(expert_size, 512); + const size_t padding_end = last_id < n_expert - 1 ? padding : 0; + + ggml_backend_tensor_set_async(split_backend, + input_cpy, + (const uint8_t *)input->data + expert_offset, expert_offset, + // copy a bit extra at the to ensure there are no NaNs in the padding of the last expert + // this is necessary for MMQ in the CUDA backend + expert_size_copy + padding_end); + }; + + int id = 0; + while (!ggml_bitset_get(used_ids.data(), id)) { + id++; + } + int32_t first_id = id; + int32_t last_id = first_id; + + for (++id; id < n_expert; ++id) { + if (!ggml_bitset_get(used_ids.data(), id)) { + continue; + } + + if (id == last_id + 1) { + last_id = id; + continue; + } + + copy_experts(first_id, last_id); + + first_id = id; + last_id = id; + } + copy_experts(first_id, last_id); + } else { + // try async copy, but if not possible, we can still use a sync copy without synchronizing the dst backend, since we handle the synchronization here with multiple copies and events + // TODO: add public function to facilitate this, since applications do not have direct access to the backend interface + if (!split_backend->iface.cpy_tensor_async || !split_backend->iface.cpy_tensor_async(input_backend, split_backend, input, input_cpy)) { + ggml_backend_synchronize(input_backend); + if (sched->events[split_backend_id][sched->cur_copy] != NULL) { + ggml_backend_event_synchronize(sched->events[split_backend_id][sched->cur_copy]); + } else { + ggml_backend_synchronize(split_backend); + } + ggml_backend_tensor_copy(input, input_cpy); } - ggml_backend_tensor_copy(input, input_cpy); } } } @@ -1448,8 +1596,6 @@ static enum ggml_status ggml_backend_sch } } - sched->cur_copy = (sched->cur_copy + 1) % sched->n_copies; - return GGML_STATUS_SUCCESS; } @@ -1537,6 +1683,7 @@ void ggml_backend_sched_free(ggml_backen } void ggml_backend_sched_reset(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); // reset state for the next run if (!sched->is_reset) { ggml_hash_set_reset(&sched->hash_set); @@ -1548,12 +1695,15 @@ void ggml_backend_sched_reset(ggml_backe } bool ggml_backend_sched_reserve(ggml_backend_sched_t sched, struct ggml_cgraph * measure_graph) { + GGML_ASSERT(sched); GGML_ASSERT((int)sched->hash_set.size >= measure_graph->n_nodes + measure_graph->n_leafs); - ggml_backend_sched_split_graph(sched, measure_graph); + ggml_backend_sched_reset(sched); ggml_backend_sched_synchronize(sched); + ggml_backend_sched_split_graph(sched, measure_graph); + if (!ggml_gallocr_reserve_n(sched->galloc, &sched->graph, sched->node_backend_ids, sched->leaf_backend_ids)) { return false; } @@ -1564,7 +1714,12 @@ bool ggml_backend_sched_reserve(ggml_bac } bool ggml_backend_sched_alloc_graph(ggml_backend_sched_t sched, struct ggml_cgraph * graph) { + GGML_ASSERT(sched); GGML_ASSERT((int)sched->hash_set.size >= graph->n_nodes + graph->n_leafs); + GGML_ASSERT(!sched->is_alloc); + + sched->cur_copy = sched->next_copy; + sched->next_copy = (sched->next_copy + 1) % sched->n_copies; ggml_backend_sched_split_graph(sched, graph); @@ -1584,6 +1739,7 @@ enum ggml_status ggml_backend_sched_grap } enum ggml_status ggml_backend_sched_graph_compute_async(ggml_backend_sched_t sched, struct ggml_cgraph * graph) { + GGML_ASSERT(sched); if (!sched->is_reset && !sched->is_alloc) { ggml_backend_sched_reset(sched); } @@ -1598,6 +1754,7 @@ enum ggml_status ggml_backend_sched_grap } void ggml_backend_sched_synchronize(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); for (int i = 0; i < sched->n_backends; i++) { ggml_backend_synchronize(sched->backends[i]); } @@ -1605,33 +1762,47 @@ void ggml_backend_sched_synchronize(ggml // if the graph is not already allocated, always use copy 0 after a synchronization // this ensures that during generation the same copy is used every time, // which avoids changes in the graph that could cause CUDA or other graphs to be disabled - sched->cur_copy = 0; + sched->next_copy = 0; } } void ggml_backend_sched_set_eval_callback(ggml_backend_sched_t sched, ggml_backend_sched_eval_callback callback, void * user_data) { + GGML_ASSERT(sched); sched->callback_eval = callback; sched->callback_eval_user_data = user_data; } int ggml_backend_sched_get_n_splits(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); return sched->n_splits; } int ggml_backend_sched_get_n_copies(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); return sched->n_copies; } int ggml_backend_sched_get_n_backends(ggml_backend_sched_t sched) { + GGML_ASSERT(sched); return sched->n_backends; } ggml_backend_t ggml_backend_sched_get_backend(ggml_backend_sched_t sched, int i) { + GGML_ASSERT(sched); GGML_ASSERT(i >= 0 && i < sched->n_backends); return sched->backends[i]; } +ggml_backend_buffer_type_t ggml_backend_sched_get_buffer_type(ggml_backend_sched_t sched, ggml_backend_t backend) { + GGML_ASSERT(sched); + int backend_index = ggml_backend_sched_backend_id(sched, backend); + GGML_ASSERT(backend_index >= 0 && backend_index < sched->n_backends); + + return sched->bufts[backend_index]; +} + size_t ggml_backend_sched_get_buffer_size(ggml_backend_sched_t sched, ggml_backend_t backend) { + GGML_ASSERT(sched); int backend_index = ggml_backend_sched_backend_id(sched, backend); GGML_ASSERT(backend_index >= 0 && backend_index < sched->n_backends); @@ -1639,6 +1810,7 @@ size_t ggml_backend_sched_get_buffer_siz } void ggml_backend_sched_set_tensor_backend(ggml_backend_sched_t sched, struct ggml_tensor * node, ggml_backend_t backend) { + GGML_ASSERT(sched); int backend_index = ggml_backend_sched_backend_id(sched, backend); GGML_ASSERT(backend_index >= 0 && backend_index < sched->n_backends); tensor_backend_id(node) = backend_index; @@ -1647,6 +1819,7 @@ void ggml_backend_sched_set_tensor_backe } ggml_backend_t ggml_backend_sched_get_tensor_backend(ggml_backend_sched_t sched, struct ggml_tensor * node) { + GGML_ASSERT(sched); int backend_index = tensor_backend_id(node); if (backend_index == -1) { return NULL; @@ -1657,6 +1830,7 @@ ggml_backend_t ggml_backend_sched_get_te // utils enum ggml_status ggml_backend_view_init(struct ggml_tensor * tensor) { + GGML_ASSERT(tensor); GGML_ASSERT(tensor->buffer == NULL); GGML_ASSERT(tensor->view_src != NULL); GGML_ASSERT(tensor->view_src->buffer != NULL); @@ -1668,6 +1842,7 @@ enum ggml_status ggml_backend_view_init( } enum ggml_status ggml_backend_tensor_alloc(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, void * addr) { + GGML_ASSERT(tensor); GGML_ASSERT(tensor->buffer == NULL); GGML_ASSERT(tensor->data == NULL); GGML_ASSERT(tensor->view_src == NULL); @@ -1741,6 +1916,7 @@ static void graph_copy_init_tensor(struc } struct ggml_backend_graph_copy ggml_backend_graph_copy(ggml_backend_t backend, struct ggml_cgraph * graph) { + GGML_ASSERT(graph); struct ggml_hash_set hash_set = ggml_hash_set_new(graph->visited_hash_set.size); struct ggml_tensor ** node_copies = (ggml_tensor **) calloc(hash_set.size, sizeof(node_copies[0])); // NOLINT bool * node_init = (bool *) calloc(hash_set.size, sizeof(node_init[0])); @@ -1885,6 +2061,7 @@ bool ggml_backend_compare_graph_backend( // CPU backend - buffer static void * ggml_backend_cpu_buffer_get_base(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); uintptr_t data = (uintptr_t)buffer->context; // align the buffer @@ -1896,28 +2073,33 @@ static void * ggml_backend_cpu_buffer_ge } static void ggml_backend_cpu_buffer_free_buffer(ggml_backend_buffer_t buffer) { + GGML_ASSERT(buffer); ggml_aligned_free(buffer->context, buffer->size); } static void ggml_backend_cpu_buffer_memset_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { + GGML_ASSERT(tensor); memset((char *)tensor->data + offset, value, size); GGML_UNUSED(buffer); } static void ggml_backend_cpu_buffer_set_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + GGML_ASSERT(tensor); memcpy((char *)tensor->data + offset, data, size); GGML_UNUSED(buffer); } static void ggml_backend_cpu_buffer_get_tensor(ggml_backend_buffer_t buffer, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size) { + GGML_ASSERT(tensor); memcpy(data, (const char *)tensor->data + offset, size); GGML_UNUSED(buffer); } static bool ggml_backend_cpu_buffer_cpy_tensor(ggml_backend_buffer_t buffer, const struct ggml_tensor * src, struct ggml_tensor * dst) { + GGML_ASSERT(src); if (ggml_backend_buffer_is_host(src->buffer)) { memcpy(dst->data, src->data, ggml_nbytes(src)); return true; @@ -1928,6 +2110,7 @@ static bool ggml_backend_cpu_buffer_cpy_ } static void ggml_backend_cpu_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { + GGML_ASSERT(buffer); memset(buffer->context, value, buffer->size); } diff -pruN 5882+dfsg-2/ggml/src/ggml-blas/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-blas/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-blas/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-blas/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -74,7 +74,7 @@ if (BLAS_FOUND) target_compile_options(ggml-blas PRIVATE ${BLAS_LINKER_FLAGS}) - if (${BLAS_INCLUDE_DIRS} MATCHES "mkl" AND (${GGML_BLAS_VENDOR} MATCHES "Generic" OR ${GGML_BLAS_VENDOR} MATCHES "Intel")) + if ("${BLAS_INCLUDE_DIRS}" MATCHES "mkl" AND (${GGML_BLAS_VENDOR} MATCHES "Generic" OR ${GGML_BLAS_VENDOR} MATCHES "Intel")) add_compile_definitions(GGML_BLAS_USE_MKL) endif() diff -pruN 5882+dfsg-2/ggml/src/ggml-blas/ggml-blas.cpp 6641+dfsg-2/ggml/src/ggml-blas/ggml-blas.cpp --- 5882+dfsg-2/ggml/src/ggml-blas/ggml-blas.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-blas/ggml-blas.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -270,6 +270,7 @@ static struct ggml_backend_i blas_backen /* .graph_compute = */ ggml_backend_blas_graph_compute, /* .event_record = */ NULL, /* .event_wait = */ NULL, + /* .graph_optimize = */ NULL, }; static ggml_guid_t ggml_backend_blas_guid(void) { @@ -281,10 +282,10 @@ ggml_backend_t ggml_backend_blas_init(vo ggml_backend_blas_context * ctx = new ggml_backend_blas_context; ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_blas_guid(), - /* .interface = */ blas_backend_i, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_blas_reg(), 0), - /* .context = */ ctx, + /* .guid = */ ggml_backend_blas_guid(), + /* .iface = */ blas_backend_i, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_blas_reg(), 0), + /* .context = */ ctx, }; #if defined(OPENBLAS_VERSION) && defined(GGML_USE_OPENMP) diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-cann/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-cann/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -31,6 +31,13 @@ string(REGEX MATCH "[0-9]+[a-zA-Z]" SOC_ set(SOC_TYPE_COMPILE_OPTION "ASCEND_${SOC_TYPE_MAJOR_SN}") string(TOUPPER ${SOC_TYPE_COMPILE_OPTION} SOC_TYPE_COMPILE_OPTION) message(STATUS "CANN: SOC_VERSION = ${SOC_VERSION}") +option(USE_ACL_GRAPH "Enable CANN graph execution (ACL graph mode)" OFF) + +if(USE_ACL_GRAPH AND (SOC_TYPE_MAJOR_SN STREQUAL "310P" OR SOC_TYPE_COMPILE_OPTION STREQUAL "ASCEND_310P")) + message(FATAL_ERROR + "CANN Graph (ACL graph mode) is not supported on 310P devices. " + "Please build with -DUSE_ACL_GRAPH=OFF or use a supported SOC.") +endif() if (CANN_INSTALL_DIR) # Only Support Linux. @@ -68,6 +75,13 @@ if (CANN_INSTALL_DIR) target_compile_definitions(ggml-cann PRIVATE "-D${SOC_TYPE_COMPILE_OPTION}") + if (USE_ACL_GRAPH) + target_compile_definitions(ggml-cann PRIVATE USE_ACL_GRAPH) + message(STATUS "CANN: USE_ACL_GRAPH is enabled.") + else() + message(STATUS "CANN: USE_ACL_GRAPH is disabled.") + endif() + message(STATUS "CANN: CANN_INCLUDE_DIRS = ${CANN_INCLUDE_DIRS}") message(STATUS "CANN: CANN_LIBRARIES = ${CANN_LIBRARIES}") else() diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/acl_tensor.cpp 6641+dfsg-2/ggml/src/ggml-cann/acl_tensor.cpp --- 5882+dfsg-2/ggml/src/ggml-cann/acl_tensor.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/acl_tensor.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -77,6 +77,8 @@ aclTensor* ggml_cann_create_tensor(const for (int i = 0; i < final_dims; i++) { acl_storage_len += (acl_ne[i] - 1) * acl_stride[i]; } + size_t elem_offset = offset / ggml_element_size(tensor); + acl_storage_len += elem_offset; // Reverse ne and stride. std::reverse(acl_ne, acl_ne + final_dims); @@ -84,7 +86,7 @@ aclTensor* ggml_cann_create_tensor(const aclTensor* acl_tensor = aclCreateTensor( acl_ne, final_dims, ggml_cann_type_mapping(tensor->type), acl_stride, - offset / ggml_element_size(tensor), format, &acl_storage_len, 1, + elem_offset, format, &acl_storage_len, 1, tensor->data); return acl_tensor; diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/aclnn_ops.cpp 6641+dfsg-2/ggml/src/ggml-cann/aclnn_ops.cpp --- 5882+dfsg-2/ggml/src/ggml-cann/aclnn_ops.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/aclnn_ops.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -68,6 +68,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -99,7 +103,7 @@ void bcast_shape(ggml_tensor * src0, ggm } } -void ggml_cann_unary_op( +void ggml_cann_op_unary( std::function unary_op, ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src = dst->src[0]; @@ -111,6 +115,42 @@ void ggml_cann_unary_op( ggml_cann_release_resources(ctx, acl_src, acl_dst); } +void ggml_cann_op_unary_gated( + std::function unary_op, + ggml_backend_cann_context& ctx, ggml_tensor* dst) { + ggml_tensor* src0 = dst->src[0]; + ggml_tensor* src1 = dst->src[1]; + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(ggml_is_contiguous_1(dst)); + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + + aclTensor* acl_dst = ggml_cann_create_tensor(dst); + aclTensor *acl_src0 = nullptr, *acl_src1 = nullptr; + if(src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src0->type == src1->type); + + acl_src0 = ggml_cann_create_tensor(src0); + acl_src1 = ggml_cann_create_tensor(src1); + } else { + int64_t ne[] = {src0->ne[0] / 2, src0->ne[1], src0->ne[2], src0->ne[3]}; + size_t nb[] = {src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3]}; + acl_src0 = ggml_cann_create_tensor(src0, ne, nb, GGML_MAX_DIMS, ACL_FORMAT_ND, 0); + acl_src1 = ggml_cann_create_tensor(src0, ne, nb, GGML_MAX_DIMS, ACL_FORMAT_ND, ne[0] * ggml_element_size(src0)); + if (swapped) { + std::swap(acl_src0, acl_src1); + } + } + + unary_op(ctx, acl_src0, acl_dst); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMul, acl_dst, acl_src1); + + ggml_cann_release_resources(ctx, acl_src0, acl_dst); + if(src1) + ggml_cann_release_resources(ctx, acl_src1); +} + /** * @brief Repeats elements of a tensor along each dimension according to the * specified repeat array. @@ -549,9 +589,16 @@ void ggml_cann_pad(ggml_backend_cann_con // the position of elements in the array means which dirction to padding, // each position means: [dim0.front, dim0.behind, dim1.front, dim1.behind, // dim2.front, dim2.behind, dim3.front, dim3.behind] - int64_t paddings[] = { - 0, dst->ne[0] - src->ne[0], 0, dst->ne[1] - src->ne[1], - 0, dst->ne[2] - src->ne[2], 0, dst->ne[3] - src->ne[3]}; + const int32_t lp0 = ggml_get_op_params_i32(dst, 0); + const int32_t rp0 = ggml_get_op_params_i32(dst, 1); + const int32_t lp1 = ggml_get_op_params_i32(dst, 2); + const int32_t rp1 = ggml_get_op_params_i32(dst, 3); + const int32_t lp2 = ggml_get_op_params_i32(dst, 4); + const int32_t rp2 = ggml_get_op_params_i32(dst, 5); + const int32_t lp3 = ggml_get_op_params_i32(dst, 6); + const int32_t rp3 = ggml_get_op_params_i32(dst, 7); + + int64_t paddings[] = {lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3}; aclnn_pad(ctx, acl_src, acl_dst, paddings); ggml_cann_release_resources(ctx, acl_src, acl_dst); } @@ -715,69 +762,55 @@ static void cann_copy(ggml_backend_cann_ void ggml_cann_dup(ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src0 = dst->src[0]; - aclTensor* acl_src = ggml_cann_create_tensor(src0); - aclTensor* acl_dst = ggml_cann_create_tensor(dst); if (ggml_are_same_shape(src0, dst)) { + aclTensor* acl_src = ggml_cann_create_tensor(src0); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); if (dst->type == src0->type) { cann_copy(ctx, acl_src, acl_dst); } else { aclnn_cast(ctx, acl_src, acl_dst, ggml_cann_type_mapping(dst->type)); } + ggml_cann_release_resources(ctx, acl_src, acl_dst); } else { - if (ggml_is_contiguous(src0) && ggml_is_contiguous(dst)) { - if (dst->type == src0->type) { - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src0->data, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - return; - } else { - ggml_cann_pool_alloc src_buffer_allocator( - ctx.pool(), - ggml_nelements(dst) * ggml_type_size(dst->type)); - void* src_trans_buffer = src_buffer_allocator.get(); - size_t src_trans_nb[GGML_MAX_DIMS]; - src_trans_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; - } - aclTensor* src_trans_tensor = ggml_cann_create_tensor( - src_trans_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), src0->ne, src_trans_nb, - GGML_MAX_DIMS); - - aclnn_cast(ctx, acl_src, src_trans_tensor, ggml_cann_type_mapping(dst->type)); - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src_trans_buffer, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - ggml_cann_release_resources(ctx, src_trans_tensor); - return; - } - } else if (ggml_is_contiguous(dst)) { - ggml_cann_pool_alloc src_buffer_allocator( - ctx.pool(), ggml_nelements(dst) * ggml_type_size(dst->type)); - void* src_trans_buffer = src_buffer_allocator.get(); + void* src_trans_buffer = src0->data; + ggml_cann_pool_alloc src_buffer_allocator; + if (!ggml_is_contiguous(src0)) { + aclTensor* acl_src = ggml_cann_create_tensor(src0); + src_buffer_allocator.alloc(ctx.pool(), + ggml_nelements(src0) * ggml_type_size(src0->type)); + src_trans_buffer = src_buffer_allocator.get(); size_t src_trans_nb[GGML_MAX_DIMS]; - src_trans_nb[0] = ggml_type_size(dst->type); + src_trans_nb[0] = ggml_type_size(src0->type); for (int i = 1; i < GGML_MAX_DIMS; i++) { src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; } aclTensor* src_trans_tensor = ggml_cann_create_tensor( - src_trans_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), src0->ne, src_trans_nb, + src_trans_buffer, ggml_cann_type_mapping(src0->type), + ggml_type_size(src0->type), src0->ne, src_trans_nb, GGML_MAX_DIMS); + cann_copy(ctx, acl_src, src_trans_tensor); + ggml_cann_release_resources(ctx, acl_src, src_trans_tensor); + } + + size_t src_reshape_nb[GGML_MAX_DIMS]; + src_reshape_nb[0] = ggml_type_size(src0->type); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + src_reshape_nb[i] = src_reshape_nb[i - 1] * dst->ne[i - 1]; + } - aclnn_cast(ctx, acl_src, src_trans_tensor, ggml_cann_type_mapping(dst->type)); + aclTensor* trans_acl_src = ggml_cann_create_tensor(src_trans_buffer, + ggml_cann_type_mapping(src0->type),ggml_type_size(src0->type), + dst->ne, src_reshape_nb, GGML_MAX_DIMS, ACL_FORMAT_ND); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); - size_t cpy_size = ggml_nbytes(dst); - ggml_cann_async_memcpy(ctx, dst->data, src_trans_buffer, cpy_size, - ACL_MEMCPY_DEVICE_TO_DEVICE); - ggml_cann_release_resources(ctx, src_trans_tensor); - return; + if (dst->type == src0->type) { + cann_copy(ctx, trans_acl_src, acl_dst); } else { - GGML_ABORT("Unsupport dst is not tontiguous."); + aclnn_cast(ctx, trans_acl_src, acl_dst, ggml_cann_type_mapping(dst->type)); } + ggml_cann_release_resources(ctx, trans_acl_src, acl_dst); } - ggml_cann_release_resources(ctx, acl_src, acl_dst); + return; } /** @@ -843,6 +876,86 @@ static aclTensor* aclnn_values(ggml_back return acl_tensor; } +/** + * @brief Fills a tensor with a scalar value. + * + * This function fills the destination tensor `acl_dst` with the scalar value + * `scalar`. + * + * @param ctx The context for the CANN backend operations. + * @param scalar The scalar value used to fill the tensor. + * @param acl_dst The destination tensor to be filled with the scalar value. + */ +static void aclnn_fill_scalar(ggml_backend_cann_context& ctx, float scalar, + aclTensor* acl_dst) { + auto acl_scalar = aclCreateScalar(&scalar, aclDataType::ACL_FLOAT); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceFillScalar, acl_dst, acl_scalar); + ggml_cann_release_resources(ctx, acl_scalar); +} + +/** + * @brief Get or expand a cached float32 tensor filled with a scalar value. + * + * This function manages cached device memory for float32 tensors. If the current + * cache size is insufficient for the requested tensor shape, the old memory will + * be released and new memory will be allocated. The allocated buffer is then + * initialized either with zeros (when @p value == 0.0f) or with the given scalar + * value using CANN operations. Finally, an aclTensor object is created from the + * cached memory and returned. + * + * @param ctx The CANN backend context that manages device memory. + * @param buffer A pointer to the cached device buffer (will be allocated + * or reallocated if necessary). + * @param cache_element The current number of cached elements. This will be + * updated when the cache is expanded. + * @param ne The tensor shape array (number of elements in each dimension). + * @param nb The stride size for each dimension. + * @param dims The number of tensor dimensions. + * @param value The scalar value used to fill the tensor (supports zero + * initialization via memset or arbitrary values via fill_scalar). + * @return An aclTensor pointer created from the cached buffer. + */ +static aclTensor* get_f32_cache_acl_tensor( + ggml_backend_cann_context& ctx, + void** buffer, + int64_t &cache_element, + int64_t* ne, + size_t* nb, + int64_t dims, + float value) { + // Calculate total number of elements + int64_t n_element = 1; + for (int i = 0; i < dims; i++) { + n_element *= ne[i]; + } + size_t size = n_element * sizeof(float); + + // Allocate or expand cache if needed + if (cache_element < n_element) { + if (*buffer != nullptr) { + aclrtFree(*buffer); + *buffer = nullptr; + } + + ACL_CHECK(aclrtMalloc(buffer, size, ACL_MEM_MALLOC_HUGE_FIRST)); + cache_element = n_element; + + // Initialize cache + if (value == 0.0f) { + ACL_CHECK(aclrtMemsetAsync(*buffer, size, 0, size, ctx.stream())); + } else { + int64_t pool_ne[1] = { n_element }; + size_t pool_nb[1] = { sizeof(float) }; + aclTensor* acl_value = ggml_cann_create_tensor( + *buffer, ACL_FLOAT, sizeof(float), pool_ne, pool_nb, 1); + aclnn_fill_scalar(ctx, 1, acl_value); + ggml_cann_release_resources(ctx, acl_value); + } + } + + return ggml_cann_create_tensor(*buffer, ACL_FLOAT, sizeof(float), ne, nb, dims); +} + void ggml_cann_rms_norm(ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src = dst->src[0]; @@ -851,20 +964,40 @@ void ggml_cann_rms_norm(ggml_backend_can float eps; memcpy(&eps, dst->op_params, sizeof(float)); - size_t one_tensor_n_bytes = src->ne[0] * ggml_element_size(src); - ggml_cann_pool_alloc one_tensor_allocator(ctx.pool(), one_tensor_n_bytes); - aclTensor* acl_gamma = aclnn_values( - ctx, one_tensor_allocator.get(), one_tensor_n_bytes, src->ne, 1, - ggml_cann_type_mapping(src->type), ggml_element_size(src)); - - size_t zero_tensor_n_bytes = - src->ne[1] * src->ne[2] * src->ne[3] * ggml_element_size(src); - ggml_cann_pool_alloc zero_tensor_allocator(ctx.pool(), zero_tensor_n_bytes); - aclTensor* acl_rstd = - aclnn_zero(ctx, zero_tensor_allocator.get(), zero_tensor_n_bytes, - src->ne, GGML_MAX_DIMS, ggml_cann_type_mapping(src->type), - ggml_element_size(src)); + // build gamma, one... + size_t acl_gamma_nb[GGML_MAX_DIMS]; + acl_gamma_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + acl_gamma_nb[i] = acl_gamma_nb[i - 1] * src->ne[i - 1]; + } + aclTensor* acl_gamma = get_f32_cache_acl_tensor( + ctx, + &ctx.rms_norm_one_tensor_cache.cache, + ctx.rms_norm_one_tensor_cache.size, + src->ne, + acl_gamma_nb, + 1, // dims + 1.0f // value + ); + + // build rstd, zero... + int64_t acl_rstd_ne[] = {src->ne[1], src->ne[2], src->ne[3]}; + size_t acl_rstd_nb[GGML_MAX_DIMS - 1]; + acl_rstd_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS - 1; i++) { + acl_rstd_nb[i] = acl_rstd_nb[i - 1] * acl_rstd_ne[i - 1]; + } + aclTensor* acl_rstd = get_f32_cache_acl_tensor( + ctx, + &ctx.rms_norm_zero_tensor_cache.cache, + ctx.rms_norm_zero_tensor_cache.size, + acl_rstd_ne, + acl_rstd_nb, + GGML_MAX_DIMS - 1, + 0.0f // value + ); + GGML_CANN_CALL_ACLNN_OP(ctx, RmsNorm, acl_src, acl_gamma, eps, acl_dst, acl_rstd); ggml_cann_release_resources(ctx, acl_src, acl_dst, acl_gamma, acl_rstd); } @@ -879,14 +1012,13 @@ void ggml_cann_diag_mask(ggml_backend_ca const int n_past = ((int32_t*)dst->op_params)[0]; - size_t one_tensor_n_bytes = src->ne[0] * src->ne[1] * src->ne[2] * - src->ne[3] * ggml_element_size(src); - ggml_cann_pool_alloc one_tensor_allocator(ctx.pool(), one_tensor_n_bytes); - - aclTensor* mask_tensor = - aclnn_values(ctx, one_tensor_allocator.get(), one_tensor_n_bytes, - src->ne, GGML_MAX_DIMS, ggml_cann_type_mapping(src->type), - ggml_element_size(src), value); + ggml_cann_pool_alloc one_tensor_allocator(ctx.pool(), ggml_nbytes(src)); + void* buffer = one_tensor_allocator.get(); + + aclTensor* mask_tensor = ggml_cann_create_tensor(buffer, ggml_cann_type_mapping(src->type), + ggml_type_size(src->type), src->ne, src->nb, GGML_MAX_DIMS); + + aclnn_fill_scalar(ctx, value, mask_tensor); aclScalar* alpha = nullptr; float alphaValue = 1.0f; @@ -1135,12 +1267,20 @@ static void aclnn_exp(ggml_backend_cann_ void aclnn_cos(ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { - GGML_CANN_CALL_ACLNN_OP(ctx, Cos, acl_src, acl_dst); + if(acl_dst == nullptr) { + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceCos, acl_src); + } else { + GGML_CANN_CALL_ACLNN_OP(ctx, Cos, acl_src, acl_dst); + } } void aclnn_sin(ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { - GGML_CANN_CALL_ACLNN_OP(ctx, Sin, acl_src, acl_dst); + if(acl_dst == nullptr) { + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceSin, acl_src); + } else { + GGML_CANN_CALL_ACLNN_OP(ctx, Sin, acl_src, acl_dst); + } } void ggml_cann_timestep_embedding(ggml_backend_cann_context& ctx, @@ -1254,23 +1394,6 @@ void ggml_cann_timestep_embedding(ggml_b } /** - * @brief Fills a tensor with a scalar value. - * - * This function fills the destination tensor `acl_dst` with the scalar value - * `scalar`. - * - * @param ctx The context for the CANN backend operations. - * @param scalar The scalar value used to fill the tensor. - * @param acl_dst The destination tensor to be filled with the scalar value. - */ -static void aclnn_fill_scalar(ggml_backend_cann_context& ctx, float scalar, - aclTensor* acl_dst) { - auto acl_scalar = aclCreateScalar(&scalar, aclDataType::ACL_FLOAT); - GGML_CANN_CALL_ACLNN_OP(ctx, InplaceFillScalar, acl_dst, acl_scalar); - ggml_cann_release_resources(ctx, acl_scalar); -} - -/** * @brief Raises each element of a tensor to the power of the corresponding * element in another tensor. * @@ -1292,160 +1415,201 @@ static void aclnn_pow_tensor_tensor(ggml } /** - * @brief Applies the Alibi (Attention with Linear Biases) mechanism to the - * @details This function implements the Alibi mechanism, which introduces - * learnable biases into the attention scores to simulate relative - * position encoding without the need for explicit positional - * embeddings. - * - * @param ctx The backend CANN context for executing operations. - * @param acl_src The source tensor representing the query or key. - * @param acl_position The position tensor containing relative positions. - * @param acl_dst The destination tensor where the result will be stored. - * @param n_head The number of attention heads. - * @param src_ne The dimensions of the source tensor. - * @param src_nb0 The byte size of the first dimension of the source - tensor. - * @param max_bias The maximum bias value used in the Alibi mechanism. - * @param dst The destination tensor object for additional metadata. - * - * The function performs the following steps: - * 1. Calculates the logarithm floor of the number of heads to determine the - base for bias calculation. - * 2. Initializes arrays with arithmetic sequences and fills them with bias - values. - * 3. Computes the bias tensor based on the calculated biases and arithmetic - sequences. - * 4. Reshapes the bias tensor to match the dimensions of the input tensors. - * 5. Multiplies the position tensor by the bias tensor. - * 6. Adds the result of the multiplication to the source tensor to produce the - final output. - */ -static void aclnn_alibi(ggml_backend_cann_context& ctx, aclTensor* acl_src, - aclTensor* acl_position, aclTensor* acl_dst, - const int n_head, int64_t* src_ne, const size_t src_nb0, - float max_bias, ggml_tensor* dst) { - const int64_t ne2_ne3 = src_ne[2] * src_ne[3]; - GGML_ASSERT(src_nb0 == sizeof(float)); - GGML_ASSERT(n_head == src_ne[2]); - - const int n_heads_log2_floor = 1u << (uint32_t)floor(log2(n_head)); - - float m0 = powf(2.0f, -(max_bias) / n_heads_log2_floor); - float m1 = powf(2.0f, -(max_bias / 2.0f) / n_heads_log2_floor); - - // init arange - ggml_cann_pool_alloc arange_allocator(ctx.pool(), - ne2_ne3 * ggml_type_size(dst->type)); - void* tmp_arange_buffer = arange_allocator.get(); - - // arange1: [1, ..., n_heads_log2_floor+1) - float start = 1; - float stop = n_heads_log2_floor + 1; - float step = 1; - int64_t n_elements_arange = n_heads_log2_floor; - - int64_t tmp_arange1_ne[] = {n_heads_log2_floor}; - size_t tmp_arange1_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_arange1_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_arange1_ne, tmp_arange1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_arange(ctx, tmp_arange1_tensor, start, stop, step, n_elements_arange); - - aclTensor* tmp_arange2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - // arange2: [1, ..., 2 * (k - n_heads_log2_floor) + 1) - start = 1; - stop = 2 * (ne2_ne3 - n_heads_log2_floor) + 1; - step = 2; - n_elements_arange = ne2_ne3 - n_heads_log2_floor; - int64_t tmp_arange2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_arange2_nb[] = {sizeof(dst->type)}; - - aclTensor* tmp_arange2_tensor = ggml_cann_create_tensor( - (char*)tmp_arange_buffer + - n_heads_log2_floor * ggml_type_size(dst->type), - ggml_cann_type_mapping(dst->type), ggml_type_size(dst->type), - tmp_arange2_ne, tmp_arange2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_arange(ctx, tmp_arange2_tensor, start, stop, step, - n_elements_arange); - } - - // init mk_base - ggml_cann_pool_alloc mk_base_allocator(ctx.pool(), - ne2_ne3 * ggml_type_size(dst->type)); - void* tmp_mk_base_buffer = mk_base_allocator.get(); - int64_t tmp_mk_base1_ne[] = {n_heads_log2_floor}; - size_t tmp_mk_base1_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base1_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base1_ne, tmp_mk_base1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_fill_scalar(ctx, m0, tmp_mk_base1_tensor); - - aclTensor* tmp_mk_base2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - int64_t tmp_mk_base2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_mk_base2_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base2_tensor = ggml_cann_create_tensor( - (char*)tmp_mk_base_buffer + - n_heads_log2_floor * ggml_type_size(dst->type), - ggml_cann_type_mapping(dst->type), ggml_type_size(dst->type), - tmp_mk_base2_ne, tmp_mk_base2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_fill_scalar(ctx, m1, tmp_mk_base2_tensor); - } - - // init mk - int64_t tmp_mk_base_ne[] = {ne2_ne3}; - size_t tmp_mk_base_nb[] = {sizeof(dst->type)}; - aclTensor* tmp_mk_base_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base_ne, tmp_mk_base_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclTensor* tmp_arange_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_base_ne, tmp_mk_base_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_pow_tensor_tensor(ctx, tmp_mk_base_tensor, tmp_arange_tensor); - - // reshape mk - int64_t tmp_mk_ne[] = {1, 1, src_ne[2], src_ne[3]}; - size_t tmp_mk_nb[GGML_MAX_DIMS]; - tmp_mk_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mk_nb[i] = tmp_mk_nb[i - 1] * tmp_mk_ne[i - 1]; - } - aclTensor* tmp_mk_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_mk_ne, tmp_mk_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - - // acl_position * mk - int64_t tmp_output_ne[] = {src_ne[0], src_ne[1], src_ne[2], src_ne[3]}; - size_t tmp_output_nb[GGML_MAX_DIMS]; - tmp_output_nb[0] = ggml_type_size(dst->type); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_output_nb[i] = tmp_output_nb[i - 1] * tmp_output_ne[i - 1]; + * @brief Generate a range of values and apply a scalar base exponentiation. + * + * This function creates an evenly spaced sequence from `start` to `stop` (exclusive), + * with step size `step`, stores it in a temporary buffer, and then computes: + * + * @f[ + * slope[i] = m^{\left( start + i \cdot step \right)}, \quad 0 \le i < size + * @f] + * + * The results are written to the provided @p slope_buffer. + * + * @param ctx CANN backend context for memory allocation and operator execution. + * @param slope_buffer Pointer to the output buffer (float array) for the computed slope values. + * @param m Scalar base for the exponentiation. + * @param size Number of elements in the generated sequence. + * @param start Starting exponent offset. + * @param stop Stopping exponent offset (exclusive). + * @param step Step size for the exponent increment. + * @param dtype Data type for slope tensor. + */ +static void aclnn_get_slope_inner(ggml_backend_cann_context& ctx, void* slope_buffer, + float m, int64_t size, float start, float stop, float step, ggml_type dtype){ + aclDataType acl_type = ggml_cann_type_mapping(dtype); + size_t type_size = ggml_type_size(dtype); + + int64_t ne[] = {size}; + size_t nb[] = {type_size}; + + ggml_cann_pool_alloc arange_allocator(ctx.pool(), size * type_size); + void* arange_buffer = arange_allocator.get(); + + aclTensor* arange_tensor = ggml_cann_create_tensor( + arange_buffer, acl_type, type_size, ne, nb, 1); + aclnn_arange(ctx, arange_tensor, start, stop, step, size); + + aclTensor* slope_tensor = ggml_cann_create_tensor( + slope_buffer, acl_type, type_size, ne, nb, 1); + + aclScalar* sc = aclCreateScalar(&m, aclDataType::ACL_FLOAT); + + GGML_CANN_CALL_ACLNN_OP(ctx, PowScalarTensor, sc, arange_tensor, slope_tensor); + ggml_cann_release_resources(ctx, sc, arange_tensor, slope_tensor); +} + +/** + * @brief Compute slope values for multiple attention heads based on ALiBi bias parameters. + * + * This function generates slope values for each attention head according to the ALiBi + * (Attention with Linear Biases) method. It splits the computation into two ranges depending + * on whether the head index is less than @p n_head_log2 or not, and uses different base values + * (`m0` and `m1`) for the exponentiation. + * + * @f[ + * slope[h] = + * \begin{cases} + * m_0^{(h + 1)}, & h < n\_head\_log2 \\ + * m_1^{\left( 2 \cdot (h - n\_head\_log2) + 1 \right)}, & h \geq n\_head\_log2 + * \end{cases} + * \quad , \quad \text{if } max\_bias > 0 + * @f] + * + * If @p max_bias <= 0, all slope values are set to 1.0. + * + * @param ctx CANN backend context for memory allocation and operator execution. + * @param n_head Total number of attention heads. + * @param slope_buffer Pointer to the output buffer (float array) for storing slopes. + * @param max_bias Maximum bias value for slope computation. + * @param dtype Data type for slope tensor. + * +*/ +static void aclnn_get_slope(ggml_backend_cann_context & ctx, int64_t n_head, + void* slope_buffer, float max_bias, ggml_type dtype) { + const int n_head_log2 = 1u << (uint32_t) floor(log2(n_head)); + + float m0 = powf(2.0f, -(max_bias) / n_head_log2); + float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); + + // const float slope = (max_bias > 0.0f) ? + // h < n_head_log2 ? + // powf(m0, h + 1) : + // powf(m1, 2*(h - n_head_log2) + 1) : + // 1.0f; + // arange1 + float start = 0 + 1; + float end = (n_head_log2 - 1) + 1; + float step = 1; + float count = n_head_log2; + // end needs to be +1 because aclnn uses a left-closed, right-open interval. + aclnn_get_slope_inner(ctx, slope_buffer, m0, count, start, end + 1, step, dtype); + if (n_head_log2 < n_head) { + // arange2 + start = 2 * (n_head_log2 - n_head_log2) + 1; + end = 2 * ((n_head - 1) - n_head_log2) + 1; + step = 2; + count = n_head - n_head_log2; + aclnn_get_slope_inner( + ctx, (char *) slope_buffer + n_head_log2 * sizeof(float), + m1, count, start, end + 1, step, dtype); + } +} + +/** + * @brief Add ALiBi (Attention with Linear Biases) positional biases to the attention mask. + * + * This function computes the ALiBi slopes for each attention head (if max_bias > 0), + * multiplies them with the attention mask to produce bias tensors, and adds these biases + * to the destination tensor (@p dst). + * + * The function performs necessary broadcasting of the mask and slope tensors to match + * the shape of the destination tensor, then applies element-wise multiplication and addition + * using CANN operators. + * + * @param ctx CANN backend context for memory management and operator execution. + * @param mask Input attention mask tensor, assumed to be contiguous. + * @param dst Destination tensor to which ALiBi biases will be added. + * @param dst_ptr Pointer to the memory of the destination tensor. + * @param max_bias Maximum bias value controlling the slope scaling. + * + * @note + * - Write data into dst_ptr using only the shape information of the dst tensor. + * - `GGML_MAX_DIMS + 2` is used to extend tensor dimensions for broadcasting. + */ +static void aclnn_add_alibi(ggml_backend_cann_context& ctx, ggml_tensor* mask, + ggml_tensor* dst, void* dst_ptr, float max_bias) { + void* slope_buffer = nullptr; + void* bias_buffer = nullptr; + + if (max_bias > 0.0f) { + int64_t n_heads = dst->ne[2]; + ggml_cann_pool_alloc slope_allocator(ctx.pool(), n_heads * sizeof(float)); + slope_buffer = slope_allocator.get(); + ggml_cann_pool_alloc bias_allocator( + ctx.pool(), ggml_nelements(dst) * ggml_element_size(dst)); + bias_buffer = bias_allocator.get(); + aclnn_get_slope(ctx, n_heads, slope_buffer, max_bias, GGML_TYPE_F32); + } + + // broadcast for mask, slop and dst; + int64_t nr2 = dst->ne[2] / mask->ne[2]; + int64_t nr3 = dst->ne[3] / mask->ne[3]; + + // broadcast the mask across rows + int64_t mask_ne[] = { mask->ne[0], dst->ne[1], mask->ne[2], 1, mask->ne[3], 1 }; + size_t mask_nb[] = { + mask_nb[0] = mask->nb[0], mask_nb[1] = mask->nb[1], mask_nb[2] = mask->nb[2], + mask_nb[3] = mask->nb[2], mask_nb[4] = mask->nb[3], mask_nb[5] = mask->nb[3] + }; + + int64_t dst_ne[] = { dst->ne[0], dst->ne[1], mask->ne[2], nr2, mask->ne[3], nr3 }; + size_t dst_nb[] = { + dst_nb[0] = dst->nb[0], dst_nb[1] = dst->nb[1], dst_nb[2] = dst->nb[2], + dst_nb[3] = dst->nb[2], dst_nb[4] = dst->nb[3], dst_nb[5] = dst->nb[3] + }; + + // slope is a 1 dim tensor, slope.ne2 == dst.ne2 + int64_t slope_ne[] = { 1, 1, mask->ne[2], nr2, 1, 1 }; + size_t slope_nb[GGML_MAX_DIMS + 2]; + slope_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS + 2; i++) { + slope_nb[i] = slope_nb[i - 1] * slope_ne[i - 1]; + } + + aclTensor* acl_slope = ggml_cann_create_tensor( + slope_buffer, ACL_FLOAT, sizeof(float), + slope_ne, slope_nb, GGML_MAX_DIMS + 2); + aclTensor* acl_mask = ggml_cann_create_tensor( + mask, mask_ne, mask_nb, GGML_MAX_DIMS + 2); + + // write data into dst_ptr using only the shape information of the dst tensor. + aclTensor* acl_dst = ggml_cann_create_tensor( + dst_ptr, ggml_cann_type_mapping(dst->type), + ggml_type_size(dst->type), dst_ne, dst_nb, + GGML_MAX_DIMS + 2); + + if (max_bias > 0.0f) { + int64_t bias_ne[] = { mask->ne[0], dst->ne[1], mask->ne[2], nr2, mask->ne[3], 1 }; + size_t bias_nb[GGML_MAX_DIMS + 2]; + bias_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS + 2; i++) { + bias_nb[i] = bias_nb[i - 1] * bias_ne[i - 1]; + } + aclTensor* bias_tensor = ggml_cann_create_tensor( + bias_buffer, ACL_FLOAT, sizeof(float), + bias_ne, bias_nb, GGML_MAX_DIMS + 2); + + aclnn_mul(ctx, acl_slope, acl_mask, bias_tensor); + aclnn_add(ctx, acl_dst, bias_tensor); + ggml_cann_release_resources(ctx, bias_tensor); + } else { + aclnn_add(ctx, acl_dst, acl_mask); } - ggml_cann_pool_alloc output_allocator(ctx.pool(), ggml_nbytes(dst)); - void* tmp_output_buffer = output_allocator.get(); - aclTensor* tmp_output_tensor = ggml_cann_create_tensor( - tmp_output_buffer, ggml_cann_type_mapping(dst->type), - ggml_type_size(dst->type), tmp_output_ne, tmp_output_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - aclnn_mul(ctx, acl_position, tmp_mk_tensor, tmp_output_tensor); - - // add - aclnn_add(ctx, tmp_output_tensor, acl_src, acl_dst); - ggml_cann_release_resources(ctx, tmp_arange1_tensor, tmp_arange2_tensor, - tmp_mk_base1_tensor, tmp_mk_base2_tensor, tmp_mk_base_tensor, - tmp_arange_tensor, tmp_mk_tensor, tmp_output_tensor); + ggml_cann_release_resources(ctx, acl_slope, acl_mask, acl_dst); } -void ggml_cann_cpy(ggml_backend_cann_context& ctx, ggml_tensor* dst) { +void ggml_cann_cpy(ggml_backend_cann_context & ctx, ggml_tensor * dst) { ggml_cann_dup(ctx, dst); } @@ -1463,165 +1627,135 @@ void ggml_cann_cpy(ggml_backend_cann_con * @param acl_dst The destination tensor where the softmax results will be * stored. */ -static void aclnn_softmax(ggml_backend_cann_context& ctx, aclTensor* acl_src, - int64_t dim, aclTensor* acl_dst) { +static void aclnn_softmax(ggml_backend_cann_context & ctx, + aclTensor* acl_src, int64_t dim, aclTensor * acl_dst) { GGML_CANN_CALL_ACLNN_OP(ctx, Softmax, acl_src, dim, acl_dst); } -void ggml_cann_softmax(ggml_backend_cann_context& ctx, ggml_tensor* dst) { +void ggml_cann_softmax(ggml_backend_cann_context & ctx, ggml_tensor * dst) { ggml_tensor* src0 = dst->src[0]; ggml_tensor* src1 = dst->src[1]; // mask aclTensor* acl_src0 = ggml_cann_create_tensor(src0); - aclTensor* acl_dst = ggml_cann_create_tensor(dst); + aclTensor* acl_dst = ggml_cann_create_tensor(dst); - float scale = 1.0f; + float scale = 1.0f; float max_bias = 0.0f; - memcpy(&scale, (float*)dst->op_params + 0, sizeof(float)); - memcpy(&max_bias, (float*)dst->op_params + 1, sizeof(float)); + memcpy(&scale, (float *) dst->op_params + 0, sizeof(float)); + memcpy(&max_bias, (float *) dst->op_params + 1, sizeof(float)); // input mul scale aclScalar* acl_scale = aclCreateScalar(&scale, aclDataType::ACL_FLOAT); + ggml_cann_pool_alloc src_tensor_allocator(ctx.pool(), ggml_nbytes(src0)); + void* src_tensor_buffer = src_tensor_allocator.get(); + aclTensor* softmax_tensor = ggml_cann_create_tensor( + src_tensor_buffer, ggml_cann_type_mapping(src0->type), + ggml_element_size(src0), src0->ne, src0->nb,GGML_MAX_DIMS); - size_t n_bytes = ggml_nbytes(src0); - ggml_cann_pool_alloc mul_scale_allocator(ctx.pool(), n_bytes); - void* input_mul_scale_buffer = mul_scale_allocator.get(); - aclTensor* acl_input_mul_scale_tensor = ggml_cann_create_tensor( - input_mul_scale_buffer, ACL_FLOAT, ggml_type_size(src0->type), src0->ne, - src0->nb, GGML_MAX_DIMS); - - bool inplace = false; - aclnn_muls(ctx, acl_src0, scale, acl_input_mul_scale_tensor, inplace); + aclnn_muls(ctx, acl_src0, scale, softmax_tensor, false); // mask - aclTensor* acl_src1_fp32_tensor = nullptr; - aclTensor* tmp_mask_tensor = nullptr; - ggml_cann_pool_alloc src1_fp32_allocator(ctx.pool()); if (src1) { - const bool use_f16 = src1->type == GGML_TYPE_F16; - if (use_f16) { - // cast to fp32 - size_t n_bytes = ggml_nelements(src1) * sizeof(float_t); - size_t src1_fp32_nb[GGML_MAX_DIMS]; - src1_fp32_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - src1_fp32_nb[i] = src1_fp32_nb[i - 1] * src1->ne[i - 1]; - } - src1_fp32_allocator.alloc(n_bytes); - void* src1_fp32_buffer = src1_fp32_allocator.get(); - acl_src1_fp32_tensor = ggml_cann_create_tensor( - src1_fp32_buffer, ACL_FLOAT, sizeof(float), src1->ne, - src1_fp32_nb, GGML_MAX_DIMS); - aclTensor* acl_src1 = ggml_cann_create_tensor(src1); - aclnn_cast(ctx, acl_src1, acl_src1_fp32_tensor, ACL_FLOAT); - ggml_cann_release_resources(ctx, acl_src1); - } else { - acl_src1_fp32_tensor = ggml_cann_create_tensor(src1); - } + aclnn_add_alibi(ctx, src1, src0, src_tensor_buffer, max_bias); + } + // softmax + aclnn_softmax(ctx, softmax_tensor, 3, acl_dst); + ggml_cann_release_resources(ctx, acl_src0, acl_dst, acl_scale, softmax_tensor); +} - // broadcast the mask across rows, only use ne11 of ne01 in mask - if (src1->ne[1] != src0->ne[1]) { - // mask shape: [1,1,ne11,ne10] - int64_t tmp_mask_ne[] = {src0->ne[0], src0->ne[1], 1, 1}; - size_t tmp_mask_nb[GGML_MAX_DIMS]; - tmp_mask_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mask_nb[i] = tmp_mask_nb[i - 1] * tmp_mask_ne[i - 1]; - } - tmp_mask_tensor = ggml_cann_create_tensor( - src1->data, ACL_FLOAT, sizeof(float), tmp_mask_ne, tmp_mask_nb, - GGML_MAX_DIMS, ACL_FORMAT_ND); - } - - // alibi - const int n_head = src0->ne[2]; - const size_t src_nb0 = src0->nb[0]; - - n_bytes = ggml_nbytes(dst); - ggml_cann_pool_alloc output_allocator(ctx.pool(), n_bytes); - void* output_buffer = output_allocator.get(); - aclTensor* alibi_output_tensor = ggml_cann_create_tensor( - output_buffer, ACL_FLOAT, ggml_type_size(dst->type), dst->ne, - dst->nb, GGML_MAX_DIMS); - if (max_bias <= 0.0f) { - // slope = 1.0 - if (tmp_mask_tensor) { - aclnn_add(ctx, tmp_mask_tensor, acl_input_mul_scale_tensor, - alibi_output_tensor); - } else { - aclnn_add(ctx, acl_src1_fp32_tensor, acl_input_mul_scale_tensor, - alibi_output_tensor); - } - } else { - // slope != 1.0 - if (tmp_mask_tensor) { - aclnn_alibi(ctx, acl_input_mul_scale_tensor, tmp_mask_tensor, - alibi_output_tensor, n_head, src0->ne, src_nb0, - max_bias, dst); - } else { - aclnn_alibi(ctx, acl_input_mul_scale_tensor, - acl_src1_fp32_tensor, alibi_output_tensor, n_head, - src0->ne, src_nb0, max_bias, dst); - } - } +/** + * @brief Performs index select operation on a 4D tensor using the CANN backend. + * + * This function applies the `IndexSelect` operation along a specific dimension + * of the source tensor (`src_buffer`) using the indices from the index tensor (`index`). + * It iterates over the last two dimensions of the source tensor, creates the corresponding + * CANN tensors for the source, index, and output slices, and executes the `IndexSelect` + * operation for each slice. + * + * @param ctx The context for CANN backend operations. + * @param src_buffer The source buffer containing the 4D input tensor data. + * @param src_ne The dimensions of the source tensor. + * @param src_nb The strides (byte offsets) of the source tensor. + * @param dst_buffer The destination buffer where the output tensor data will be written. + * @param dst_ne The dimensions of the destination tensor. + * @param dst_nb The strides (byte offsets) of the destination tensor. + * @param index The index tensor specifying the indices to select from the source tensor. + * @param type The data type of the source and destination tensors. + */ +static void aclnn_index_select_4d(ggml_backend_cann_context& ctx, + void* src_buffer,int64_t* src_ne, size_t* src_nb, + void* dst_buffer, int64_t* dst_ne, size_t* dst_nb, + ggml_tensor* index, ggml_type type) { + for (int64_t i = 0; i < src_ne[3]; i++) { + for (int64_t j = 0; j < src_ne[2]; j++) { + // src + aclTensor* acl_src_tensor = ggml_cann_create_tensor( + (char*)src_buffer + i * src_nb[3] + j * src_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + src_ne, src_nb, 2); - // softmax - aclnn_softmax(ctx, alibi_output_tensor, 3, acl_dst); - ggml_cann_release_resources(ctx, alibi_output_tensor); - } else { - aclnn_softmax(ctx, acl_input_mul_scale_tensor, 3, acl_dst); - } + // index + aclTensor* acl_index = ggml_cann_create_tensor( + (char*)index->data + (i % index->ne[2]) * index->nb[2] + (j % index->ne[1]) * index->nb[1], + ggml_cann_type_mapping(index->type), ggml_element_size(index), + index->ne, index->nb, 1); - ggml_cann_release_resources(ctx, acl_src0, acl_src1_fp32_tensor, acl_dst, - acl_scale, acl_input_mul_scale_tensor, tmp_mask_tensor); + // out + aclTensor* acl_out = ggml_cann_create_tensor( + (char*)dst_buffer + i * dst_nb[3] + j * dst_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + dst_ne, dst_nb, 2); + GGML_CANN_CALL_ACLNN_OP(ctx, IndexSelect, acl_src_tensor, 0, acl_index, acl_out); + ggml_cann_release_resources(ctx, acl_src_tensor, acl_index, acl_out); + } + } } /** - * @brief Performs embedding operation on a 4D tensor using the CANN backend. + * @brief Performs inplace index copy operation on a 4D tensor using the CANN backend. * - * This function extracts slices from the source tensor (`src_buffer`), - * index tensor (`index`), and destination tensor (`dst`), and performs an - * embedding operation on them. The embedding operation is applied by iterating - * over the last two dimensions of the source tensor, creating the necessary - * tensors for the source, index, and output, and executing the embedding operation. + * This function applies the `IndexCopy` operation along a specific dimension of the + * destination tensor (`dst_buffer`) by copying elements from the source tensor (`src_buffer`) + * to positions specified by the index tensor (`index`). + * It iterates over the last two dimensions of the tensors, creates the corresponding + * CANN tensors for source, index, and destination slices, and performs the index copy + * operation for each slice. * * @param ctx The context for CANN backend operations. - * @param src_buffer The source buffer holding the data for the source tensor. + * @param src_buffer The source buffer containing the 4D input tensor data to be copied. * @param src_ne The dimensions of the source tensor. * @param src_nb The strides (byte offsets) of the source tensor. - * @param index The index tensor used in the embedding operation. - * @param dst The destination tensor where the result will be stored. - */ -static void aclnn_embedding_4d(ggml_backend_cann_context& ctx, void* src_buffer, - int64_t* src_ne, size_t* src_nb, ggml_tensor* index, - ggml_tensor* dst) { + * @param dst_buffer The destination buffer where values will be copied to. + * @param dst_ne The dimensions of the destination tensor. + * @param dst_nb The strides (byte offsets) of the destination tensor. + * @param index The index tensor specifying target positions in the destination tensor. + * @param type The data type of the source and destination tensors. + */ +static void aclnn_index_copy_4d(ggml_backend_cann_context& ctx, + void* src_buffer,int64_t* src_ne, size_t* src_nb, + void* dst_buffer, int64_t* dst_ne, size_t* dst_nb, + ggml_tensor* index, ggml_type type) { for (int64_t i = 0; i < src_ne[3]; i++) { for (int64_t j = 0; j < src_ne[2]; j++) { // src - int64_t acl_src_ne[2] = {src_ne[0], src_ne[1]}; - size_t acl_src_nb[2] = {src_nb[0], src_nb[1]}; aclTensor* acl_src_tensor = ggml_cann_create_tensor( (char*)src_buffer + i * src_nb[3] + j * src_nb[2], - ggml_cann_type_mapping(dst->type), ggml_element_size(dst), - acl_src_ne, acl_src_nb, 2); + ggml_cann_type_mapping(type), ggml_type_size(type), + src_ne, src_nb, 2); // index - int64_t acl_index_ne[1] = {index->ne[0]}; - size_t acl_index_nb[1] = {index->nb[0]}; aclTensor* acl_index = ggml_cann_create_tensor( - (char*)index->data + i * index->nb[2] + j * index->nb[1], + (char*)index->data + (i % index->ne[2]) * index->nb[2] + (j % index->ne[1]) * index->nb[1], ggml_cann_type_mapping(index->type), ggml_element_size(index), - acl_index_ne, acl_index_nb, 1); + index->ne, index->nb, 1); // out - int64_t acl_out_ne[2] = {dst->ne[0], dst->ne[1]}; - size_t acl_out_nb[2] = {dst->nb[0], dst->nb[1]}; aclTensor* acl_out = ggml_cann_create_tensor( - (char*)dst->data + i * dst->nb[3] + j * dst->nb[2], - ggml_cann_type_mapping(dst->type), ggml_element_size(dst), - acl_out_ne, acl_out_nb, 2); - GGML_CANN_CALL_ACLNN_OP(ctx, Embedding, acl_src_tensor, acl_index, acl_out); + (char*)dst_buffer + i * dst_nb[3] + j * dst_nb[2], + ggml_cann_type_mapping(type), ggml_type_size(type), + dst_ne, dst_nb, 2); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceIndexCopy, acl_out, 0, acl_index, acl_src_tensor); ggml_cann_release_resources(ctx, acl_src_tensor, acl_index, acl_out); } } @@ -1633,17 +1767,18 @@ void ggml_cann_get_rows(ggml_backend_can switch (src0->type) { case GGML_TYPE_F32: { - aclnn_embedding_4d(ctx, src0->data, src0->ne, src0->nb, src1, - dst); + aclnn_index_select_4d(ctx, src0->data, src0->ne, src0->nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); break; } case GGML_TYPE_F16: { aclTensor* acl_src0 = ggml_cann_create_tensor(src0); ggml_cann_pool_alloc src_buffer_allocator( - ctx.pool(), ggml_nelements(src0) * sizeof(float_t)); + ctx.pool(), ggml_nelements(src0) * sizeof(float)); void* src_trans_buffer = src_buffer_allocator.get(); size_t src_trans_nb[GGML_MAX_DIMS]; - src_trans_nb[0] = sizeof(float_t); + src_trans_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; } @@ -1651,8 +1786,9 @@ void ggml_cann_get_rows(ggml_backend_can src_trans_buffer, ACL_FLOAT, ggml_type_size(dst->type), src0->ne, src_trans_nb, GGML_MAX_DIMS); aclnn_cast(ctx, acl_src0, src_trans_tensor, ggml_cann_type_mapping(dst->type)); - aclnn_embedding_4d(ctx, src_trans_buffer, src0->ne, - src_trans_nb, src1, dst); + aclnn_index_select_4d(ctx, src_trans_buffer, src0->ne, src_trans_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); ggml_cann_release_resources(ctx, acl_src0, src_trans_tensor); break; } @@ -1686,14 +1822,14 @@ void ggml_cann_get_rows(ggml_backend_can // [3,4,5,64] -> [3,4,5,2,32] dequant_ne = weight_ne; - dequant_nb[0] = sizeof(float_t); + dequant_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS + 1; i++) { dequant_nb[i] = dequant_nb[i - 1] * dequant_ne[i - 1]; } scale_offset = ggml_nelements(src0) * sizeof(int8_t); ggml_cann_pool_alloc dequant_buffer_allocator( - ctx.pool(), ggml_nelements(src0) * sizeof(float_t)); + ctx.pool(), ggml_nelements(src0) * sizeof(float)); aclTensor* acl_weight_tensor = ggml_cann_create_tensor( src0->data, ACL_INT8, sizeof(int8_t), weight_ne, weight_nb, @@ -1702,18 +1838,20 @@ void ggml_cann_get_rows(ggml_backend_can src0->data, ACL_FLOAT16, sizeof(uint16_t), scale_ne, scale_nb, GGML_MAX_DIMS + 1, ACL_FORMAT_ND, scale_offset); aclTensor* dequant_tensor = ggml_cann_create_tensor( - dequant_buffer_allocator.get(), ACL_FLOAT, sizeof(float_t), + dequant_buffer_allocator.get(), ACL_FLOAT, sizeof(float), dequant_ne, dequant_nb, GGML_MAX_DIMS + 1); aclnn_mul(ctx, acl_weight_tensor, acl_scale_tensor, dequant_tensor); - dequant_nb[0] = sizeof(float_t); + dequant_nb[0] = sizeof(float); dequant_ne = src0->ne; for (int i = 1; i < GGML_MAX_DIMS; i++) { dequant_nb[i] = dequant_nb[i - 1] * src0->ne[i - 1]; } - aclnn_embedding_4d(ctx, dequant_buffer_allocator.get(), - dequant_ne, dequant_nb, src1, dst); + aclnn_index_select_4d(ctx, dequant_buffer_allocator.get(), + dequant_ne, dequant_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); ggml_cann_release_resources(ctx, dequant_tensor); break; @@ -1724,6 +1862,43 @@ void ggml_cann_get_rows(ggml_backend_can } } +void ggml_cann_set_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst) { + ggml_tensor* src0 = dst->src[0]; // src + ggml_tensor* src1 = dst->src[1]; // index + + switch (dst->type) { + case GGML_TYPE_F32: { + aclnn_index_copy_4d(ctx, src0->data, src0->ne, src0->nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); + break; + } + case GGML_TYPE_F16: { + aclTensor* acl_src0 = ggml_cann_create_tensor(src0); + ggml_cann_pool_alloc src_buffer_allocator( + ctx.pool(), ggml_nelements(src0) * sizeof(uint16_t)); + void* src_trans_buffer = src_buffer_allocator.get(); + size_t src_trans_nb[GGML_MAX_DIMS]; + src_trans_nb[0] = sizeof(uint16_t); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + src_trans_nb[i] = src_trans_nb[i - 1] * src0->ne[i - 1]; + } + aclTensor* src_trans_tensor = ggml_cann_create_tensor( + src_trans_buffer, ACL_FLOAT16, ggml_type_size(dst->type), + src0->ne, src_trans_nb, GGML_MAX_DIMS); + aclnn_cast(ctx, acl_src0, src_trans_tensor, ggml_cann_type_mapping(dst->type)); + aclnn_index_copy_4d(ctx, src_trans_buffer, src0->ne, src_trans_nb, + dst->data, dst->ne, dst->nb, + src1, dst->type); + ggml_cann_release_resources(ctx, acl_src0, src_trans_tensor); + break; + } + default: + GGML_ABORT("Unsupported tensor type for GGML_OP_SET_ROWS"); + break; + } +} + /** * @brief Repeats elements of a tensor along a specified dimension. * @@ -1785,8 +1960,25 @@ static void ggml_cann_mat_mul_fp(ggml_ba size_t transpose_nb[] = {bcast_weight_nb[1], bcast_weight_nb[0], bcast_weight_nb[2], bcast_weight_nb[3], bcast_weight_nb[4], bcast_weight_nb[5]}; - aclTensor* acl_weight_tensor = - ggml_cann_create_tensor(weight, transpose_ne, transpose_nb, n_dims); + aclTensor* acl_weight_tensor; + + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("on")); + if (weight_to_nz && is_matmul_weight(weight)) { + int64_t acl_stride[2] = {1, transpose_ne[1]}; + + // Reverse ne. + std::reverse(transpose_ne, transpose_ne + n_dims); + + std::vector storageDims = {transpose_ne[0], transpose_ne[1]}; + + acl_weight_tensor = aclCreateTensor( + transpose_ne, n_dims, ggml_cann_type_mapping(weight->type), acl_stride, + 0, ACL_FORMAT_FRACTAL_NZ, storageDims.data(), 2, weight->data); + } else { + acl_weight_tensor = + ggml_cann_create_tensor(weight, transpose_ne, transpose_nb, n_dims, ACL_FORMAT_ND); + } aclTensor* acl_dst = ggml_cann_create_tensor(dst, bcast_dst_ne, bcast_dst_nb, n_dims); @@ -2052,63 +2244,190 @@ static void aclnn_index_fill_tensor(ggml ggml_cann_release_resources(ctx, acl_index, acl_value); } +/** + * @brief Initializes and caches sine/cosine positional encoding values + * (used in RoPE, Rotary Position Embedding) for attention layers. + * + * This function computes and caches the sin/cos values of + * θ = position * theta_scale for RoPE encoding. The cache is shared + * across attention layers, and only the first attention layer will + * trigger initialization. The cache includes repeated sin/cos values + * with different repeat methods depending on the @param is_neox flag. + * + * Steps performed by this function: + * 1. Identify whether the target tensor belongs to Q/K in attention + * and restrict computation to the first layer only. + * 2. Initialize the theta scale array (arange → power → freq scaling). + * 3. Allocate sin/cos caches if the max prompt length increases. + * 4. Compute θ = position * theta_scale. + * 5. Compute sin(θ), cos(θ) and optionally scale by attn_factor. + * 6. Expand sin/cos values by repeat or repeat_interleave depending + * on whether @param is_neox is enabled. + * + * @param ctx The CANN backend context, holding memory pool, + * stream, and persistent buffers for rope init/cache. + * @param dst The destination ggml_tensor whose computation + * depends on the RoPE values (usually Qcur/Kcur). + * @param theta_scale Scalar exponent base for computing theta scale values. + * @param freq_scale Frequency scaling factor, applied to theta scale. + * @param attn_factor Attention scaling factor, applied to sin/cos. + * @param is_neox Whether to use Neox-style repeat strategy + * (dim expansion vs repeat_interleave). + */ static void aclnn_cache_init(ggml_backend_cann_context& ctx, ggml_tensor* dst, - aclTensor* acl_cos_repeat_tensor, - aclTensor* acl_sin_repeat_tensor, + float* corr_dims, float ext_factor, float theta_scale, float freq_scale, float attn_factor, bool is_neox) { - // int sin/cos cache, cache has different repeat method depond on - // @param.is_neox - ggml_tensor* src0 = dst->src[0]; // input ggml_tensor* src1 = dst->src[1]; // position ggml_tensor* src2 = dst->src[2]; // freq_factors - GGML_TENSOR_BINARY_OP_LOCALS + if(src2 == nullptr && ctx.rope_cache.cached + && ctx.rope_cache.ext_factor == ext_factor + && ctx.rope_cache.theta_scale == theta_scale + && ctx.rope_cache.freq_scale == freq_scale + && ctx.rope_cache.attn_factor == attn_factor + && ctx.rope_cache.is_neox == is_neox) { + // use cache. + return; + } - // theta_scale arange, [0,1,...,ne00/2 - 1] - int64_t theta_scale_length = ne00 / 2; - ggml_cann_pool_alloc theta_scale_allocator(ctx.pool(), - theta_scale_length * sizeof(float_t)); - void* theta_scale_buffer = theta_scale_allocator.get(); + int64_t theta_scale_length = src0->ne[0] / 2; int64_t theta_scale_ne[] = {theta_scale_length, 1, 1, 1}; - size_t theta_scale_nb[] = {sizeof(float_t), sizeof(float_t), sizeof(float_t), - theta_scale_length * sizeof(float_t)}; + size_t theta_scale_nb[] = {sizeof(float), sizeof(float), sizeof(float), + theta_scale_length * sizeof(float)}; - aclTensor* acl_theta_scale_tensor = - ggml_cann_create_tensor(theta_scale_buffer, ACL_FLOAT, sizeof(float_t), - theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); - float start = 0; - float step = 1; - float stop = ne00 / 2; - float n_elements = ne00 / 2; - aclnn_arange(ctx, acl_theta_scale_tensor, start, stop, step, n_elements); - - // power - aclScalar* acl_theta_scale = aclCreateScalar(&theta_scale, aclDataType::ACL_FLOAT); - GGML_CANN_CALL_ACLNN_OP(ctx, PowScalarTensor, acl_theta_scale, acl_theta_scale_tensor, - acl_theta_scale_tensor); - - // freq_scale - if (freq_scale != 1) { - aclnn_muls(ctx, acl_theta_scale_tensor, freq_scale, nullptr, true); + GGML_ASSERT(src1->type == GGML_TYPE_I32); + int64_t position_length = src1->ne[0]; + int64_t position_ne[] = {1, 1, position_length, 1}; + size_t position_nb[] = {sizeof(int32_t), sizeof(int32_t), sizeof(int32_t), + sizeof(int32_t) * position_length}; + + int64_t theta_ne[] = {theta_scale_length, 1, position_length, 1}; + size_t theta_nb[GGML_MAX_DIMS]; + theta_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + theta_nb[i] = theta_nb[i - 1] * theta_ne[i - 1]; + } + + // theta_scale arange, [0,1,...,ne00/2 - 1] + aclTensor* acl_theta_scale_tensor = nullptr; + // cache theta scale + if (ctx.rope_cache.theta_scale_length != theta_scale_length || + // theta_scale and freq_scale should not change during the current token inference process, + // so we can directly use == here instead of comparing the absolute difference. + ctx.rope_cache.theta_scale != theta_scale || + ctx.rope_cache.freq_scale != freq_scale) { + + ctx.rope_cache.theta_scale_length = theta_scale_length; + + if (ctx.rope_cache.theta_scale_cache != nullptr) { + ACL_CHECK(aclrtFree(ctx.rope_cache.theta_scale_cache)); + } + ACL_CHECK(aclrtMalloc(&ctx.rope_cache.theta_scale_cache, theta_scale_length * sizeof(float), ACL_MEM_MALLOC_HUGE_FIRST)); + + acl_theta_scale_tensor = + ggml_cann_create_tensor(ctx.rope_cache.theta_scale_cache, ACL_FLOAT, sizeof(float), + theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); + + float start = 0; + float step = 1; + float stop = theta_scale_length; + float n_elements = theta_scale_length; + aclnn_arange(ctx, acl_theta_scale_tensor, start, stop, step, n_elements); + + ggml_cann_pool_alloc yarn_ramp_allocator(ctx.pool()); + aclTensor* acl_yarn_ramp_tensor = nullptr; + if (ext_factor != 0) { + // -rope_yarn_ramp + // const float y = (i0 / 2 - low) / MAX(0.001f, high - low); + // return MIN(1, MAX(0, y)) - 1; + yarn_ramp_allocator.alloc(theta_scale_length * sizeof(float)); + void* yarn_ramp_buffer = yarn_ramp_allocator.get(); + acl_yarn_ramp_tensor = ggml_cann_create_tensor(yarn_ramp_buffer, ACL_FLOAT, sizeof(float), + theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); + float zero_value = 0, one_value = 1; + float denom_safe_value = MAX(0.001f, corr_dims[1] - corr_dims[0]); + aclScalar* low = aclCreateScalar(&corr_dims[0], aclDataType::ACL_FLOAT); + aclScalar* zero = aclCreateScalar(&zero_value, aclDataType::ACL_FLOAT); + aclScalar* one = aclCreateScalar(&one_value, aclDataType::ACL_FLOAT); + aclScalar* denom_safe = aclCreateScalar(&denom_safe_value, aclDataType::ACL_FLOAT); + aclScalar* ext_factor_sc = aclCreateScalar(&ext_factor, aclDataType::ACL_FLOAT); + + GGML_CANN_CALL_ACLNN_OP(ctx, Subs, acl_theta_scale_tensor, low, one, acl_yarn_ramp_tensor); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceDivs, acl_yarn_ramp_tensor, denom_safe); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceThreshold, acl_yarn_ramp_tensor, zero, zero); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceClampMax, acl_yarn_ramp_tensor, one); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceSubs, acl_yarn_ramp_tensor, one, one); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMuls, acl_yarn_ramp_tensor, ext_factor_sc); + + // theta_interp = freq_scale * theta_extrap; + // theta = theta_interp * (1 - ramp_mix) + theta_extrap * ramp_mix; + // theta = freq_scale * theta_extrap * (1 - ramp_mix) + theta_extrap * ramp_mix; + // theta = freq_scale * theta_extrap - freq_scale * theta_extrap * ramp_mix + theta_extrap * ramp_mix; + // theta = theta_extrap * (freq_scale - freq_scale * ramp_mix + ramp_mix); + // + // we cache (freq_scale - freq_scale * ramp_mix + ramp_mix), Considering that the rope_yarn_ramp here is the inverse + // cache freq_scale + (freq_scale - 1) * ramp_mix + float freq_scale_1 = freq_scale - 1; + aclScalar* freq_scale_sc = aclCreateScalar(&freq_scale, aclDataType::ACL_FLOAT); + aclScalar* freq_scale_1_sc = aclCreateScalar(&freq_scale_1, aclDataType::ACL_FLOAT); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMuls, acl_yarn_ramp_tensor, freq_scale_1_sc); + GGML_CANN_CALL_ACLNN_OP(ctx, InplaceAdds, acl_yarn_ramp_tensor, freq_scale_sc, one); + + ggml_cann_release_resources(ctx, low, zero, one, denom_safe, ext_factor_sc, freq_scale_sc, freq_scale_1_sc); + } + + // power + aclScalar* acl_theta_scale = aclCreateScalar(&theta_scale, aclDataType::ACL_FLOAT); + GGML_CANN_CALL_ACLNN_OP(ctx, PowScalarTensor, acl_theta_scale, acl_theta_scale_tensor, + acl_theta_scale_tensor); + + if (ext_factor != 0) { + aclnn_mul(ctx, acl_theta_scale_tensor, acl_yarn_ramp_tensor); + } else if (freq_scale != 1) { + aclnn_muls(ctx, acl_theta_scale_tensor, freq_scale, nullptr, true); + } + + ggml_cann_release_resources(ctx, acl_yarn_ramp_tensor, acl_theta_scale); + } else { + // use cache + acl_theta_scale_tensor = + ggml_cann_create_tensor(ctx.rope_cache.theta_scale_cache, ACL_FLOAT, sizeof(float), + theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); } + ggml_cann_pool_alloc freq_fac_res_allocator(ctx.pool()); // freq_factors if (src2) { + freq_fac_res_allocator.alloc(theta_scale_length * sizeof(float)); + void* freq_fac_res_ptr = freq_fac_res_allocator.get(); aclTensor* acl_freq_factors_tensor = ggml_cann_create_tensor( src2->data, ggml_cann_type_mapping(src2->type), ggml_type_size(src2->type), theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); - aclnn_div(ctx, acl_theta_scale_tensor, acl_freq_factors_tensor); - ggml_cann_release_resources(ctx, acl_freq_factors_tensor); + aclTensor* acl_freq_fac_res_tensor = ggml_cann_create_tensor( + freq_fac_res_ptr, ACL_FLOAT, sizeof(float), + theta_scale_ne, theta_scale_nb, GGML_MAX_DIMS); + aclnn_div(ctx, acl_theta_scale_tensor, acl_freq_factors_tensor, acl_freq_fac_res_tensor); + std::swap(acl_theta_scale_tensor, acl_freq_fac_res_tensor); + ggml_cann_release_resources(ctx, acl_freq_factors_tensor, acl_freq_fac_res_tensor); + } + + // init sin_repeat && cos_repeat, only to accelerate first layer on each device + if (position_length > ctx.rope_cache.position_length) { + ctx.rope_cache.position_length = position_length; + if (ctx.rope_cache.sin_cache != nullptr) { + ACL_CHECK(aclrtFree(ctx.rope_cache.sin_cache)); + } + if (ctx.rope_cache.cos_cache != nullptr) { + ACL_CHECK(aclrtFree(ctx.rope_cache.cos_cache)); + } + int64_t repeat_theta_length = theta_scale_length * position_length * 2; + ACL_CHECK(aclrtMalloc(&ctx.rope_cache.sin_cache, repeat_theta_length * sizeof(float), ACL_MEM_MALLOC_HUGE_FIRST)); + ACL_CHECK(aclrtMalloc(&ctx.rope_cache.cos_cache, repeat_theta_length * sizeof(float), ACL_MEM_MALLOC_HUGE_FIRST)); } // position - GGML_ASSERT(src1->type == GGML_TYPE_I32); - int64_t position_length = src1->ne[0]; - int64_t position_ne[] = {1, 1, position_length, 1}; - size_t position_nb[] = {sizeof(int32_t), sizeof(int32_t), sizeof(int32_t), - sizeof(int32_t) * position_length}; aclTensor* acl_position_tensor = ggml_cann_create_tensor( src1->data, ggml_cann_type_mapping(src1->type), ggml_type_size(src1->type), position_ne, position_nb, GGML_MAX_DIMS); @@ -2116,43 +2435,55 @@ static void aclnn_cache_init(ggml_backen // power * position int64_t theta_length = theta_scale_length * position_length; ggml_cann_pool_alloc theta_allocator(ctx.pool(), - theta_length * sizeof(float_t)); + theta_length * sizeof(float)); void* theta_buffer = theta_allocator.get(); - int64_t theta_ne[] = {theta_scale_length, 1, position_length, 1}; - size_t theta_nb[GGML_MAX_DIMS]; - theta_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - theta_nb[i] = theta_nb[i - 1] * theta_ne[i - 1]; - } + aclTensor* acl_theta_tensor = - ggml_cann_create_tensor(theta_buffer, ACL_FLOAT, sizeof(float_t), + ggml_cann_create_tensor(theta_buffer, ACL_FLOAT, sizeof(float), theta_ne, theta_nb, GGML_MAX_DIMS); aclnn_mul(ctx, acl_position_tensor, acl_theta_scale_tensor, - acl_theta_tensor); + acl_theta_tensor); // sin/cos ggml_cann_pool_alloc sin_allocator(ctx.pool(), - theta_length * sizeof(float_t)); + theta_length * sizeof(float)); void* sin_buffer = sin_allocator.get(); aclTensor* acl_sin_tensor = ggml_cann_create_tensor( - sin_buffer, ACL_FLOAT, sizeof(float_t), theta_ne, theta_nb, + sin_buffer, ACL_FLOAT, sizeof(float), theta_ne, theta_nb, GGML_MAX_DIMS, ACL_FORMAT_ND); aclnn_sin(ctx, acl_theta_tensor, acl_sin_tensor); ggml_cann_pool_alloc cos_allocator(ctx.pool(), - theta_length * sizeof(float_t)); + theta_length * sizeof(float)); void* cos_buffer = cos_allocator.get(); aclTensor* acl_cos_tensor = ggml_cann_create_tensor( - cos_buffer, ACL_FLOAT, sizeof(float_t), theta_ne, theta_nb, + cos_buffer, ACL_FLOAT, sizeof(float), theta_ne, theta_nb, GGML_MAX_DIMS, ACL_FORMAT_ND); aclnn_cos(ctx, acl_theta_tensor, acl_cos_tensor); + if (ext_factor != 0) { + attn_factor *= 1.0f + 0.1f * logf(1.0f / freq_scale); + } + // attn_factor if (attn_factor != 1) { aclnn_muls(ctx, acl_sin_tensor, attn_factor, nullptr, true); aclnn_muls(ctx, acl_cos_tensor, attn_factor, nullptr, true); } + int64_t sin_reshape_ne[4] = {src0->ne[0], 1, src0->ne[2], 1}; + size_t sin_reshape_nb[GGML_MAX_DIMS]; + sin_reshape_nb[0] = sizeof(float); + for (int i = 1; i < GGML_MAX_DIMS; i++) { + sin_reshape_nb[i] = sin_reshape_nb[i - 1] * sin_reshape_ne[i - 1]; + } + aclTensor* acl_sin_repeat_tensor = + ggml_cann_create_tensor(ctx.rope_cache.sin_cache, ACL_FLOAT, sizeof(float), + sin_reshape_ne, sin_reshape_nb, GGML_MAX_DIMS); + aclTensor* acl_cos_repeat_tensor = + ggml_cann_create_tensor(ctx.rope_cache.cos_cache, ACL_FLOAT, sizeof(float), + sin_reshape_ne, sin_reshape_nb, GGML_MAX_DIMS); + // repeat if (is_neox) { int64_t repeatsArray[] = {1, 1, 1, 2}; @@ -2168,9 +2499,17 @@ static void aclnn_cache_init(ggml_backen num_repeats, output_size); } - // release + // Other layers use cache except first layer. + ctx.rope_cache.cached = true; + ctx.rope_cache.ext_factor = ext_factor; + ctx.rope_cache.theta_scale = theta_scale; + ctx.rope_cache.freq_scale = freq_scale; + ctx.rope_cache.attn_factor = attn_factor; + ctx.rope_cache.is_neox = is_neox; + ggml_cann_release_resources(ctx, acl_theta_scale_tensor, acl_position_tensor, - acl_theta_tensor, acl_sin_tensor, acl_cos_tensor, acl_theta_scale); + acl_theta_tensor, acl_sin_tensor, acl_sin_repeat_tensor, acl_cos_tensor, + acl_cos_repeat_tensor); } #ifdef __cplusplus @@ -2189,8 +2528,6 @@ aclnnStatus aclnnRotaryPositionEmbedding #endif void ggml_cann_rope(ggml_backend_cann_context& ctx, ggml_tensor* dst) { - // TODO: use ascendc - // Only test with LLAMA model. ggml_tensor* src0 = dst->src[0]; // input // param @@ -2213,8 +2550,6 @@ void ggml_cann_rope(ggml_backend_cann_co // TODO: n_dims <= ne0 GGML_ASSERT(n_dims == ne0); GGML_ASSERT(n_dims % 2 == 0); - // TODO: ext_factor != 0 - GGML_ASSERT(ext_factor == 0); const float theta_scale = powf(freq_base, -2.0f / n_dims); @@ -2224,28 +2559,22 @@ void ggml_cann_rope(ggml_backend_cann_co const bool is_neox = mode & GGML_ROPE_TYPE_NEOX; - // init cos/sin cache - ggml_cann_pool_alloc sin_allocator( - ctx.pool(), ne00 * ne02 * sizeof(float_t)); - ggml_cann_pool_alloc cos_allocator( - ctx.pool(), ne00 * ne02 * sizeof(float_t)); - void* sin_buffer = sin_allocator.get(); - void* cos_buffer = cos_allocator.get(); + // init ctx.rope_cos/rope_sin cache + aclnn_cache_init(ctx, dst, corr_dims, ext_factor, + theta_scale, freq_scale, attn_factor, is_neox); int64_t sin_reshape_ne[4] = {ne00, 1, ne02, 1}; size_t sin_reshape_nb[GGML_MAX_DIMS]; - sin_reshape_nb[0] = sizeof(float_t); + sin_reshape_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { sin_reshape_nb[i] = sin_reshape_nb[i - 1] * sin_reshape_ne[i - 1]; } aclTensor* acl_sin_reshape_tensor = - ggml_cann_create_tensor(sin_buffer, ACL_FLOAT, sizeof(float_t), + ggml_cann_create_tensor(ctx.rope_cache.sin_cache, ACL_FLOAT, sizeof(float), sin_reshape_ne, sin_reshape_nb, GGML_MAX_DIMS); aclTensor* acl_cos_reshape_tensor = - ggml_cann_create_tensor(cos_buffer, ACL_FLOAT, sizeof(float_t), + ggml_cann_create_tensor(ctx.rope_cache.cos_cache, ACL_FLOAT, sizeof(float), sin_reshape_ne, sin_reshape_nb, GGML_MAX_DIMS); - aclnn_cache_init(ctx, dst, acl_cos_reshape_tensor, acl_sin_reshape_tensor, - theta_scale, freq_scale, attn_factor, is_neox); aclTensor* acl_src = ggml_cann_create_tensor(src0); aclTensor* acl_dst = ggml_cann_create_tensor(dst); @@ -2259,7 +2588,7 @@ void ggml_cann_rope(ggml_backend_cann_co void* minus_one_scale_buffer = nullptr; ggml_cann_pool_alloc roll_allocator(ctx.pool(), ggml_nbytes(src0)); ggml_cann_pool_alloc minus_one_scale_allocator( - ctx.pool(), sizeof(float_t) * src0->ne[0]); + ctx.pool(), sizeof(float) * src0->ne[0]); if (!is_neox) { // roll input: [q0,q1,q2,q3,...] -> [q1,q0,q3,q2,...] input_roll_buffer = roll_allocator.get(); @@ -2289,13 +2618,13 @@ void ggml_cann_rope(ggml_backend_cann_co int64_t minus_one_ne[4] = {src0->ne[0], 1, 1, 1}; size_t minus_one_nb[GGML_MAX_DIMS]; - minus_one_nb[0] = sizeof(float_t); + minus_one_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { minus_one_nb[i] = minus_one_nb[i - 1] * minus_one_ne[i - 1]; } acl_minus_one_tensor = aclnn_values( - ctx, minus_one_scale_buffer, sizeof(float_t) * src0->ne[0], - minus_one_ne, GGML_MAX_DIMS, ACL_FLOAT, sizeof(float_t), 1); + ctx, minus_one_scale_buffer, sizeof(float) * src0->ne[0], + minus_one_ne, GGML_MAX_DIMS, ACL_FLOAT, sizeof(float), 1); int64_t dim = 3; int64_t* index = new int64_t[src0->ne[0]]; for (int i = 0; i < src0->ne[0]; i++) { @@ -2323,22 +2652,22 @@ void ggml_cann_rope(ggml_backend_cann_co minus_one_scale_buffer = minus_one_scale_allocator.get(); int64_t minus_one_ne[4] = {src0->ne[0], 1, 1, 1}; size_t minus_one_nb[GGML_MAX_DIMS]; - minus_one_nb[0] = sizeof(float_t); + minus_one_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { minus_one_nb[i] = minus_one_nb[i - 1] * minus_one_ne[i - 1]; } acl_minus_one_tensor = aclnn_values( - ctx, minus_one_scale_buffer, sizeof(float_t) * src0->ne[0], - minus_one_ne, GGML_MAX_DIMS, ACL_FLOAT, sizeof(float_t), 1); + ctx, minus_one_scale_buffer, sizeof(float) * src0->ne[0], + minus_one_ne, GGML_MAX_DIMS, ACL_FLOAT, sizeof(float), 1); // -1 * first half int64_t first_half_ne[4] = {src0->ne[0] / 2, 1, 1, 1}; size_t first_half_nb[GGML_MAX_DIMS]; - first_half_nb[0] = sizeof(float_t); + first_half_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { first_half_nb[i] = first_half_nb[i - 1] * first_half_ne[i - 1]; } aclTensor* acl_first_half_tensor = ggml_cann_create_tensor( - minus_one_scale_buffer, ACL_FLOAT, sizeof(float_t), first_half_ne, + minus_one_scale_buffer, ACL_FLOAT, sizeof(float), first_half_ne, first_half_nb, GGML_MAX_DIMS); bool inplace = true; float scale = -1; @@ -2378,28 +2707,28 @@ void ggml_cann_rope(ggml_backend_cann_co // TODO: ne0 != n_dims in mode2 } else if (src0->type == GGML_TYPE_F16) { size_t input_fp32_nb[GGML_MAX_DIMS]; - input_fp32_nb[0] = sizeof(float_t); + input_fp32_nb[0] = sizeof(float); for (int i = 1; i < GGML_MAX_DIMS; i++) { input_fp32_nb[i] = input_fp32_nb[i - 1] * dst->ne[i - 1]; } ggml_cann_pool_alloc fp32_allocator1( - ctx.pool(), ggml_nelements(dst) * sizeof(float_t)); + ctx.pool(), ggml_nelements(dst) * sizeof(float)); void* input_fp32_buffer1 = fp32_allocator1.get(); aclTensor* input_fp32_tensor1 = ggml_cann_create_tensor( - input_fp32_buffer1, ACL_FLOAT, sizeof(float_t), dst->ne, + input_fp32_buffer1, ACL_FLOAT, sizeof(float), dst->ne, input_fp32_nb, GGML_MAX_DIMS); ggml_cann_pool_alloc fp32_allocator2( - ctx.pool(), ggml_nelements(dst) * sizeof(float_t)); + ctx.pool(), ggml_nelements(dst) * sizeof(float)); void* input_fp32_buffer2 = fp32_allocator2.get(); aclTensor* input_fp32_tensor2 = ggml_cann_create_tensor( - input_fp32_buffer2, ACL_FLOAT, sizeof(float_t), dst->ne, + input_fp32_buffer2, ACL_FLOAT, sizeof(float), dst->ne, input_fp32_nb, GGML_MAX_DIMS); ggml_cann_pool_alloc fp32_allocator( - ctx.pool(), ggml_nelements(dst) * sizeof(float_t)); + ctx.pool(), ggml_nelements(dst) * sizeof(float)); output_fp32_buffer = fp32_allocator.get(); aclTensor* output_fp32_tensor = ggml_cann_create_tensor( - output_fp32_buffer, ACL_FLOAT, sizeof(float_t), dst->ne, + output_fp32_buffer, ACL_FLOAT, sizeof(float), dst->ne, input_fp32_nb, GGML_MAX_DIMS); aclnn_mul(ctx, acl_src, acl_cos_reshape_tensor, input_fp32_tensor1); aclnn_mul(ctx, acl_input_roll_mul_scale_tensor, acl_sin_reshape_tensor, @@ -2496,8 +2825,6 @@ void ggml_cann_conv_transpose_1d(ggml_ba aclIntArray *padding = aclCreateIntArray(paddingVal, 1); int64_t dilationVal[] = {1}; aclIntArray *dilation = aclCreateIntArray(dilationVal, 1); - bool transposed = true; - int64_t groups = 1; int8_t cubeMathType = 0; #ifdef ASCEND_310P @@ -2505,7 +2832,7 @@ void ggml_cann_conv_transpose_1d(ggml_ba #endif GGML_CANN_CALL_ACLNN_OP(ctx, Convolution, acl_input, acl_weight, nullptr, stride, - padding, dilation, transposed, padding, groups, acl_dst, cubeMathType); + padding, dilation, true, padding, 1, acl_dst, cubeMathType); ggml_cann_release_resources(ctx, acl_weight, acl_dst, stride, padding, dilation); } @@ -2614,174 +2941,49 @@ void ggml_cann_step(ggml_backend_cann_co */ static void ggml_cann_mul_mat_id_fp(ggml_backend_cann_context& ctx, ggml_tensor* dst) { //dst [M, K, N, 1] - ggml_tensor * src0 = dst->src[0]; //src0 [D, M, A, 1] - ggml_tensor * src1 = dst->src[1]; //src1 [D, B, N, 1], B = K or B = 1 + ggml_tensor * src0 = dst->src[0]; //src0 [D, M, A, 1] -> [D, M, K, 1] + ggml_tensor * src1 = dst->src[1]; //src1 [D, B, N, 1], B = K or B = 1 -> [D, 1, K, 1] ggml_tensor * ids = dst->src[2]; //ids [K, N] - GGML_TENSOR_BINARY_OP_LOCALS + GGML_ASSERT(src0->ne[3] == 1); + GGML_ASSERT(src1->ne[3] == 1); + GGML_ASSERT(dst->ne[3] == 1); - // copy index from npu to cpu - int64_t n_as = ne02; // A - int64_t n_ids = ids->ne[0]; // K + int64_t batch = src1->ne[2]; + GGML_ASSERT(batch == ids->ne[1]); - std::vector ids_host(ggml_nbytes(ids)); - ggml_cann_async_memcpy(ctx, ids_host.data(), ids->data, ggml_nbytes(ids), - ACL_MEMCPY_DEVICE_TO_HOST); - ACL_CHECK(aclrtSynchronizeStream(ctx.stream())); + ggml_cann_pool_alloc export_allocator(ctx.pool(), src0->ne[0] * src0->ne[1] * ids->ne[0] * ggml_element_size(src0)); + void* export_ptr = export_allocator.get(); + for (int64_t i = 0; i < batch; i++) { + aclTensor *select_index = ggml_cann_create_tensor(ids, ids->ne, ids->nb, 1, ACL_FORMAT_ND, i * ids->nb[1]); + aclTensor *export_weight = ggml_cann_create_tensor(src0, src0->ne, src0->nb, 3); - char * src0_original = (char *) src0->data; - char * src1_original = (char *) src1->data; - char * dst_original = (char *) dst->data; - size_t ori_src0_nb[4] = {nb00, nb01, nb02, nb03}; - - // src0 is F16, src1 is F32, dst is F32 - ggml_cann_pool_alloc src0_cast_allocator; - if (src0->type == GGML_TYPE_F16) { - src0_cast_allocator.alloc(ctx.pool(), sizeof(float) * ggml_nelements(src0)); - void* src0_cast_buf = src0_cast_allocator.get(); - - size_t cast_nb[GGML_MAX_DIMS]; - cast_nb[0] = sizeof(float_t); - for (int i = 1; i < GGML_MAX_DIMS; i++) { - cast_nb[i] = cast_nb[i - 1] * src0->ne[i - 1]; + int64_t select_export_ne[] = {src0->ne[0], src0->ne[1], ids->ne[0]}; + size_t select_export_nb[3]; + select_export_nb[0] = src0->nb[0]; + for (int k = 1;k < 3; k++) { + select_export_nb[k] = select_export_nb[k-1] * select_export_ne[k-1]; } - aclTensor* acl_src0_f16 = ggml_cann_create_tensor(src0); - aclTensor* acl_cast = ggml_cann_create_tensor(src0_cast_buf, - ACL_FLOAT, sizeof(float), src0->ne, cast_nb, 4); - GGML_CANN_CALL_ACLNN_OP(ctx, Cast, acl_src0_f16, ACL_FLOAT, acl_cast); - ggml_cann_release_resources(ctx, acl_cast, acl_src0_f16); + aclTensor *select_export = ggml_cann_create_tensor(export_ptr, ggml_cann_type_mapping(src0->type), ggml_element_size(src0), select_export_ne, select_export_nb, 3); + GGML_CANN_CALL_ACLNN_OP(ctx, IndexSelect, export_weight, 0, select_index, select_export); - src0_original = (char *) src0_cast_buf; - memcpy(ori_src0_nb, cast_nb, sizeof(ori_src0_nb)); - } - -#ifdef ASCEND_310P - ggml_tensor src0_row = *src0; - ggml_tensor src1_row = *src1; - ggml_tensor dst_row = *dst; + int64_t select_transpose_ne[] = {select_export_ne[1], select_export_ne[0], select_export_ne[2]}; + size_t select_transpose_nb[] = {select_export_nb[1], select_export_nb[0], select_export_nb[2]}; + aclTensor *select_export_transpose = ggml_cann_create_tensor(export_ptr, ggml_cann_type_mapping(src0->type), ggml_element_size(src0), select_transpose_ne, select_transpose_nb, 3); - if (src0->type == GGML_TYPE_F16) { - src0_row.type = GGML_TYPE_F32; - } + int64_t active_tensor_ne[] = {src1->ne[0], 1, src1->ne[1]}; + size_t active_tensor_nb[] = {src1->nb[0], src1->nb[1], src1->nb[1]}; + aclTensor *active_tensor = ggml_cann_create_tensor(src1, active_tensor_ne, active_tensor_nb, 3, ACL_FORMAT_ND, i * src1->nb[2]); - // src0_row [D, M, 1, 1] weight without permute - src0_row.ne[2] = 1; - src0_row.ne[3] = 1; - src0_row.nb[0] = ori_src0_nb[0]; - src0_row.nb[1] = ori_src0_nb[1]; - src0_row.nb[2] = ori_src0_nb[1]; - src0_row.nb[3] = ori_src0_nb[1]; + int64_t dst_ne[] = {dst->ne[0], 1, dst->ne[1]}; + size_t dst_nb[] = {dst->nb[0], dst->nb[1], dst->nb[1]}; + aclTensor *acl_dst = ggml_cann_create_tensor(dst, dst_ne,dst_nb, 3, ACL_FORMAT_ND, i * dst->nb[2]); - // src1_row [D, 1, 1, 1] -> input - src1_row.ne[1] = 1; - src1_row.ne[2] = 1; - src1_row.ne[3] = 1; - src1_row.nb[2] = nb11; - src1_row.nb[3] = nb11; + GGML_CANN_CALL_ACLNN_OP(ctx, BatchMatMul, active_tensor, select_export_transpose, acl_dst, 2); - // dst_row [M, 1, 1, 1] -> out - dst_row.ne[1] = 1; - dst_row.ne[2] = 1; - dst_row.ne[3] = 1; - dst_row.nb[2] = nb1; - dst_row.nb[3] = nb1; - - //create weight for one row - for (int64_t iid1 = 0; iid1 < ids->ne[1]; iid1++) { - for (int64_t id = 0; id < n_ids; id++) { - // expert index - int32_t i02 = *(int32_t *) (ids_host.data() + iid1*ids->nb[1] + id*ids->nb[0]); - GGML_ASSERT(i02 >= 0 && i02 < n_as); - - // If B = 1 (broadcast), always use 0; otherwise, use id. - int64_t i11 = (ne11 == 1 ? 0 : id); - int64_t i12 = iid1; - - int64_t i1 = id; - int64_t i2 = i12; - - void* src0_tmp_ptr = src0_original + i02*ori_src0_nb[2]; - void* src1_tmp_ptr = src1_original + i11*nb11 + i12*nb12; - void* dst_tmp_ptr = dst_original + i1*nb1 + i2*nb2; - - src0_row.data = src0_tmp_ptr; - src1_row.data = src1_tmp_ptr; - dst_row.data = dst_tmp_ptr; - dst_row.src[0] = &src0_row; - dst_row.src[1] = &src1_row; - - ggml_cann_mul_mat(ctx, &dst_row); - } - } - return; -#endif - - std::vector src0_tensor_vec; - std::vector src1_tensor_vec; - std::vector dst_tensor_vec; - for (int64_t iid1 = 0; iid1 < ids->ne[1]; iid1++) { - for (int64_t id = 0; id < n_ids; id++) { - // src0_row [M, D] -> weight && permute - int64_t src0_ne[2] = {ne01, ne00}; - size_t src0_nb[2] = {ori_src0_nb[1], ori_src0_nb[0]}; - // src1_row [D, 1] -> input - int64_t src1_ne[2] = {ne10, 1}; - size_t src1_nb[2] = {nb10, nb11}; - // dst_row [M, 1] -> out - int64_t dst_ne[2] = {ne0, 1}; - size_t dst_nb[2] = {nb0, nb1}; - - // expert index - int32_t i02 = *(int32_t *) (ids_host.data() + iid1*ids->nb[1] + id*ids->nb[0]); - GGML_ASSERT(i02 >= 0 && i02 < n_as); - - // If B = 1 (broadcast), always use 0; otherwise, use id. - int64_t i11 = (ne11 == 1 ? 0 : id); - int64_t i12 = iid1; - - int64_t i1 = id; - int64_t i2 = i12; - - void* src0_tmp_ptr = src0_original + i02*ori_src0_nb[2]; - void* src1_tmp_ptr = src1_original + i11*nb11 + i12*nb12; - void* dst_tmp_ptr = dst_original + i1*nb1 + i2*nb2; - - aclTensor* acl_src0 = ggml_cann_create_tensor(src0_tmp_ptr, - ACL_FLOAT, sizeof(float), - src0_ne, src0_nb, 2); - aclTensor* acl_src1 = ggml_cann_create_tensor(src1_tmp_ptr, - ACL_FLOAT, sizeof(float), - src1_ne, src1_nb, 2); - aclTensor* acl_dst = ggml_cann_create_tensor(dst_tmp_ptr, - ACL_FLOAT, sizeof(float), - dst_ne, dst_nb, 2); - - src0_tensor_vec.push_back(acl_src0); - src1_tensor_vec.push_back(acl_src1); - dst_tensor_vec.push_back(acl_dst); - } + ggml_cann_release_resources(ctx, select_index, export_weight, select_export, active_tensor, acl_dst, select_export_transpose); } - - size_t GROUP_SIZE = 128; - // GroupedMatmulV3 required tensor_list.size < 128 - for (size_t i = 0; i < src0_tensor_vec.size(); i += GROUP_SIZE) { - // split and call GroupedMatmulV3 - size_t end = std::min(i + GROUP_SIZE, src0_tensor_vec.size()); - std::vector src0_tensor_vec_split(src0_tensor_vec.begin() + i, src0_tensor_vec.begin() + end); - std::vector src1_tensor_vec_split(src1_tensor_vec.begin() + i, src1_tensor_vec.begin() + end); - std::vector dst_tensor_vec_split(dst_tensor_vec.begin() + i, dst_tensor_vec.begin() + end); - - aclTensorList* src0_tensor_list = aclCreateTensorList(src0_tensor_vec_split.data(), src0_tensor_vec_split.size()); - aclTensorList* src1_tensor_list = aclCreateTensorList(src1_tensor_vec_split.data(), src1_tensor_vec_split.size()); - aclTensorList* dst_tensor_list = aclCreateTensorList(dst_tensor_vec_split.data(), dst_tensor_vec_split.size()); - - GGML_CANN_CALL_ACLNN_OP(ctx, GroupedMatmulV3, src1_tensor_list, src0_tensor_list, - nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, 0, -1, dst_tensor_list); - - ggml_cann_release_resources(ctx, src0_tensor_list, src1_tensor_list, dst_tensor_list); - } - return; } /** @@ -2930,11 +3132,38 @@ void ggml_cann_mul_mat_id(ggml_backend_c void ggml_cann_flash_attn_ext(ggml_backend_cann_context& ctx, ggml_tensor* dst){ - ggml_tensor* src0 = dst->src[0]; // q, fp32 - ggml_tensor* src1 = dst->src[1]; // k, fp16 - ggml_tensor* src2 = dst->src[2]; // v, fp16 + ggml_tensor* src0 = dst->src[0]; // q, fp32 | B, N, S, D (uncont) -> B, S, N, D (cont) + ggml_tensor* src1 = dst->src[1]; // k, fp16 | B, N, S, D (uncont) -> B, S, N, D (cont) + ggml_tensor* src2 = dst->src[2]; // v, fp16 | B, N, S, D (uncont) -> B, S, N, D (cont) ggml_tensor* src3 = dst->src[3]; // mask, fp16 + // B, N, S, D (uncont) -> B, S, N, D (cont) + int64_t src0_bsnd_ne[GGML_MAX_DIMS]; + memcpy(src0_bsnd_ne, src0->ne, GGML_MAX_DIMS * sizeof(int64_t)); + size_t src0_bsnd_nb[GGML_MAX_DIMS]; + memcpy(src0_bsnd_nb, src0->nb, GGML_MAX_DIMS * sizeof(size_t)); + int64_t src1_bsnd_ne[GGML_MAX_DIMS]; + memcpy(src1_bsnd_ne, src1->ne, GGML_MAX_DIMS * sizeof(int64_t)); + size_t src1_bsnd_nb[GGML_MAX_DIMS]; + memcpy(src1_bsnd_nb, src1->nb, GGML_MAX_DIMS * sizeof(size_t)); + int64_t src2_bsnd_ne[GGML_MAX_DIMS]; + memcpy(src2_bsnd_ne, src2->ne, GGML_MAX_DIMS * sizeof(int64_t)); + size_t src2_bsnd_nb[GGML_MAX_DIMS]; + memcpy(src2_bsnd_nb, src2->nb, GGML_MAX_DIMS * sizeof(size_t)); + + auto transpose12 = [](int64_t* ne, size_t* nb) { + int64_t ne_tmp = ne[1]; + size_t nb_tmp = nb[1]; + ne[1] = ne[2]; + nb[1] = nb[2]; + ne[2] = ne_tmp; + nb[2] = nb_tmp; + }; + + transpose12(src0_bsnd_ne, src0_bsnd_nb); + transpose12(src1_bsnd_ne, src1_bsnd_nb); + transpose12(src2_bsnd_ne, src2_bsnd_nb); + float maxBias = 0.0f; float scaleValue = 1.0f; float logitSoftcap = 0.0f; @@ -2956,11 +3185,12 @@ void ggml_cann_flash_attn_ext(ggml_backe void* src0_f16_buffer = nullptr; if(ggml_cann_type_mapping(src0->type) != faDataType){ - aclTensor* acl_src0_f32_tensor = ggml_cann_create_tensor(src0); + aclTensor* acl_src0_f32_tensor = ggml_cann_create_tensor(src0, src0_bsnd_ne, + src0_bsnd_nb, GGML_MAX_DIMS); src0_f16_buffer = src0_f16_allocator.alloc( ggml_nelements(src0) * faElemSize); - int64_t* src0_f16_ne = src0->ne; + int64_t* src0_f16_ne = src0_bsnd_ne; size_t src0_f16_nb[GGML_MAX_DIMS]; src0_f16_nb[0] = sizeof(uint16_t); for(int i = 1; i < GGML_MAX_DIMS; ++i){ @@ -2974,20 +3204,23 @@ void ggml_cann_flash_attn_ext(ggml_backe aclnn_cast(ctx, acl_src0_f32_tensor, acl_src0_f16_tensor, faDataType); ggml_cann_release_resources(ctx, acl_src0_f32_tensor); }else{ - acl_src0_f16_tensor = ggml_cann_create_tensor(src0); + acl_src0_f16_tensor = ggml_cann_create_tensor(src0, src0_bsnd_ne, + src0_bsnd_nb, GGML_MAX_DIMS); } // Step 2: create the acl tensors for src1 (Key), src2 (Value), // and the direct output from FusedInferAttention - acl_src1_f16_tensor = ggml_cann_create_tensor(src1); - acl_src2_f16_tensor = ggml_cann_create_tensor(src2); + acl_src1_f16_tensor = ggml_cann_create_tensor(src1, src1_bsnd_ne, + src1_bsnd_nb, GGML_MAX_DIMS); + acl_src2_f16_tensor = ggml_cann_create_tensor(src2, src2_bsnd_ne, + src2_bsnd_nb, GGML_MAX_DIMS); ggml_cann_pool_alloc out_f16_allocator(ctx.pool()); void* out_f16_buffer = out_f16_allocator.alloc( ggml_nelements(dst) * faElemSize); - int64_t* out_f16_ne = src0->ne; + int64_t* out_f16_ne = src0_bsnd_ne; size_t out_f16_nb[GGML_MAX_DIMS]; out_f16_nb[0] = faElemSize; for(int i = 1; i < GGML_MAX_DIMS; ++i){ @@ -3001,168 +3234,81 @@ void ggml_cann_flash_attn_ext(ggml_backe // Step 3: create the PSEShift tensor if needed // this tensor is considered as mask (f16) in the llama.cpp - aclTensor* bcast_pse_tensor = nullptr; - int64_t bcast_pse_ne[GGML_MAX_DIMS]; - size_t bcast_pse_nb[GGML_MAX_DIMS]; ggml_cann_pool_alloc bcast_pse_allocator(ctx.pool()); - void* bcast_pse_buffer = nullptr; - if(src3 != nullptr){ - bcast_pse_buffer = bcast_pse_allocator.alloc( - ggml_nelements(src3) * src0->ne[2] * sizeof(uint16_t)); - - if(src0->ne[1] > 1){ - // Case 1: broadcast pse for prefill stage with multiple head - aclTensor* acl_mask_f16_tensor = ggml_cann_create_tensor(src3); - bcast_pse_ne[0] = src3->ne[0]; - bcast_pse_ne[1] = src3->ne[1]; - bcast_pse_ne[2] = src0->ne[2]; - bcast_pse_ne[3] = src3->ne[3]; + // Construct the truncated pse tensor (common for prefill/decode) + int64_t trunc_pse_ne[GGML_MAX_DIMS] = { + src3->ne[0], // D + src0->ne[1], // S (number of Q tokens) + src3->ne[2], // mask N + src3->ne[3] // B + }; + size_t* trunc_pse_nb = src3->nb; + + aclTensor* acl_mask_f16_trunc_tensor = ggml_cann_create_tensor( + src3->data, ACL_FLOAT16, sizeof(uint16_t), + trunc_pse_ne, trunc_pse_nb, GGML_MAX_DIMS + ); + int64_t bcast_pse_ne[GGML_MAX_DIMS]; + size_t bcast_pse_nb[GGML_MAX_DIMS]; + bcast_pse_ne[0] = src3->ne[0]; // D + bcast_pse_ne[1] = src0->ne[1]; // S + bcast_pse_ne[2] = src0->ne[2]; // N (num_heads) + bcast_pse_ne[3] = src3->ne[3]; // B + if (maxBias == 0.0f) { + // When maxBias == 0.0f, use nb = 0 reduce once repeat (Qwen2) + // Construct the bcast tensor (simulate repeat on the head dimension using stride=0) bcast_pse_nb[0] = sizeof(uint16_t); - for(int i = 1; i < GGML_MAX_DIMS; ++i){ - bcast_pse_nb[i] = bcast_pse_nb[i - 1] * bcast_pse_ne[i - 1]; - } + bcast_pse_nb[1] = bcast_pse_nb[0] * bcast_pse_ne[0]; + bcast_pse_nb[2] = 0; // <---- the head dimension shares the same data + bcast_pse_nb[3] = src3->nb[3]; bcast_pse_tensor = ggml_cann_create_tensor( - bcast_pse_buffer, ACL_FLOAT16, sizeof(uint16_t), - bcast_pse_ne, bcast_pse_nb, GGML_MAX_DIMS); - - int64_t repeats[] = {1, src0->ne[2], 1, 1}; - aclnn_repeat(ctx, acl_mask_f16_tensor, bcast_pse_tensor, repeats); - - ggml_cann_release_resources(ctx, acl_mask_f16_tensor); - }else{ - // Case 2: trunc the first row and broadcast pse for decode stage with multiple head - int64_t trunc_pse_ne[GGML_MAX_DIMS] = {src3->ne[0], src0->ne[1], src3->ne[2], src3->ne[3]}; - size_t* trunc_pse_nb = src3->nb; - - aclTensor* acl_mask_f16_trunc_tensor = ggml_cann_create_tensor( src3->data, ACL_FLOAT16, sizeof(uint16_t), - trunc_pse_ne, trunc_pse_nb, GGML_MAX_DIMS); - - bcast_pse_ne[0] = src3->ne[0]; - bcast_pse_ne[1] = src0->ne[1]; - bcast_pse_ne[2] = src0->ne[2]; - bcast_pse_ne[3] = src3->ne[3]; + bcast_pse_ne, bcast_pse_nb, GGML_MAX_DIMS + ); + ggml_cann_release_resources(ctx, acl_mask_f16_trunc_tensor); + } else { bcast_pse_nb[0] = sizeof(uint16_t); - for(int i = 1; i < GGML_MAX_DIMS; ++i){ + for (int i = 1; i < GGML_MAX_DIMS; i++) { bcast_pse_nb[i] = bcast_pse_nb[i - 1] * bcast_pse_ne[i - 1]; } + void* bcast_pse_buffer = bcast_pse_allocator.alloc( + ggml_nelements(src3) * src0->ne[2] * sizeof(uint16_t) + ); + bcast_pse_tensor = ggml_cann_create_tensor( bcast_pse_buffer, ACL_FLOAT16, sizeof(uint16_t), - bcast_pse_ne, bcast_pse_nb, GGML_MAX_DIMS); + bcast_pse_ne, bcast_pse_nb, GGML_MAX_DIMS + ); int64_t repeats[] = {1, src0->ne[2], 1, 1}; aclnn_repeat(ctx, acl_mask_f16_trunc_tensor, bcast_pse_tensor, repeats); - ggml_cann_release_resources(ctx, acl_mask_f16_trunc_tensor); - } - - // Compute the slope if needed. Derived from ggml_cann_softmax(). - if(maxBias != 0.0f){ // alibi - const int64_t ne2_ne3 = src0->ne[2] * src0->ne[3]; - const int64_t n_head = src0->ne[2]; - const int n_heads_log2_floor = 1u << (uint32_t)floor(log2(n_head)); - float m0 = powf(2.0f, -(maxBias) / n_heads_log2_floor); - float m1 = powf(2.0f, -(maxBias / 2.0f) / n_heads_log2_floor); - // init arange - ggml_cann_pool_alloc arange_allocator(ctx.pool(), - ne2_ne3 * faElemSize); - void* tmp_arange_buffer = arange_allocator.get(); - - // arange1: [1, ..., n_heads_log2_floor+1) - float start = 1; - float stop = n_heads_log2_floor + 1; - float step = 1; - int64_t n_elements_arange = n_heads_log2_floor; - - int64_t tmp_arange1_ne[] = {n_heads_log2_floor}; - size_t tmp_arange1_nb[] = {faElemSize}; - aclTensor* tmp_arange1_tensor = ggml_cann_create_tensor( - tmp_arange_buffer, faDataType, faElemSize, - tmp_arange1_ne, tmp_arange1_nb, - GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - - aclnn_arange(ctx, tmp_arange1_tensor, start, stop, step, n_elements_arange); - - aclTensor* tmp_arange2_tensor = nullptr; - if (n_heads_log2_floor < ne2_ne3) { - // arange2: [1, ..., 2 * (k - n_heads_log2_floor) + 1) - start = 1; - stop = 2 * (ne2_ne3 - n_heads_log2_floor) + 1; - step = 2; - n_elements_arange = ne2_ne3 - n_heads_log2_floor; - int64_t tmp_arange2_ne[] = {ne2_ne3 - n_heads_log2_floor}; - size_t tmp_arange2_nb[] = {faElemSize}; - - aclTensor* tmp_arange2_tensor = ggml_cann_create_tensor( - (char*)tmp_arange_buffer + - n_heads_log2_floor * faElemSize, - faDataType, faElemSize, - tmp_arange2_ne, tmp_arange2_nb, GGML_MAX_DIMS - 3, ACL_FORMAT_ND); - aclnn_arange(ctx, tmp_arange2_tensor, start, stop, step, - n_elements_arange); + // Compute the slope if needed. Derived from ggml_cann_softmax(). + const int64_t n_heads = src0->ne[2]; + ggml_cann_pool_alloc slope_allocator(ctx.pool(), n_heads * sizeof(uint16_t)); + void* slope_buffer = slope_allocator.get(); + aclnn_get_slope(ctx, n_heads, slope_buffer, maxBias, GGML_TYPE_F16); + + int64_t slope_ne[] = {1, 1, n_heads, 1}; + size_t slope_nb[GGML_MAX_DIMS]; + slope_nb[0] = sizeof(uint16_t); + for(int i = 1;ine[2], src0->ne[3]}; - size_t tmp_mk_nb[GGML_MAX_DIMS]; - tmp_mk_nb[0] = faElemSize; - for (int i = 1; i < GGML_MAX_DIMS; i++) { - tmp_mk_nb[i] = tmp_mk_nb[i - 1] * tmp_mk_ne[i - 1]; - } - aclTensor* tmp_mk_tensor = ggml_cann_create_tensor( - tmp_mk_base_buffer, faDataType, faElemSize, - tmp_mk_ne, tmp_mk_nb, GGML_MAX_DIMS, - ACL_FORMAT_ND); - GGML_CANN_CALL_ACLNN_OP(ctx, InplaceMul, bcast_pse_tensor, tmp_mk_tensor); - - ggml_cann_release_resources(ctx, tmp_arange1_tensor, tmp_arange2_tensor, - tmp_mk_base1_tensor, tmp_mk_base2_tensor, tmp_mk_base_tensor, - tmp_arange_tensor, tmp_mk_tensor); + ggml_cann_release_resources(ctx, slope_tensor, acl_mask_f16_trunc_tensor); } } @@ -3179,7 +3325,7 @@ void ggml_cann_flash_attn_ext(ggml_backe // double scaleValue = 1 / sqrt(src0->ne[0]); // 1/sqrt(d) int64_t preTokens = 65535; int64_t nextTokens = 65535; - char layout[5] = {'B', 'N', 'S', 'D', 0}; + char layout[5] = {'B', 'S', 'N', 'D', 0}; int64_t sparseMode = 0; int64_t innerPrecise = (src0->ne[1] == 1) ? 0 : 2; int64_t blockSize = 0; @@ -3216,32 +3362,9 @@ void ggml_cann_flash_attn_ext(ggml_backe ); // Step 6: post-processing, permute and cast to f32 - - int64_t new_dim[] = {0, 2, 1, 3}; aclTensor* acl_dst_tensor = ggml_cann_create_tensor(dst); - - if(ggml_cann_type_mapping(dst->type) != faDataType){ - ggml_cann_pool_alloc perm_out_f16_allocator(ctx.pool()); - perm_out_f16_allocator.alloc(ggml_nelements(dst) * faElemSize); - void* perm_out_f16_buffer = perm_out_f16_allocator.get(); - - int64_t* perm_out_f16_ne = dst->ne; - size_t perm_out_f16_nb[GGML_MAX_DIMS]; - perm_out_f16_nb[0] = faElemSize; - for(int i = 1; i < GGML_MAX_DIMS; ++i){ - perm_out_f16_nb[i] = perm_out_f16_nb[i - 1] * perm_out_f16_ne[i - 1]; - } - aclTensor* acl_perm_out_f16_tensor = ggml_cann_create_tensor( - perm_out_f16_buffer, faDataType, faElemSize, - perm_out_f16_ne, perm_out_f16_nb, GGML_MAX_DIMS); - aclnn_permute(ctx, acl_dst_f16_tensor, acl_perm_out_f16_tensor, new_dim, GGML_MAX_DIMS); - aclnn_cast(ctx, - acl_perm_out_f16_tensor, acl_dst_tensor, ggml_cann_type_mapping(dst->type)); - ggml_cann_release_resources(ctx, acl_perm_out_f16_tensor); - }else{ - // only need to permute - aclnn_permute(ctx, acl_dst_f16_tensor, acl_dst_tensor, new_dim, GGML_MAX_DIMS); - } + // TODO: when dst is fp16, don't need cast + aclnn_cast(ctx, acl_dst_f16_tensor, acl_dst_tensor, ggml_cann_type_mapping(dst->type)); ggml_cann_release_resources(ctx, acl_src0_f16_tensor, acl_src1_f16_tensor, acl_src2_f16_tensor, diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/aclnn_ops.h 6641+dfsg-2/ggml/src/ggml-cann/aclnn_ops.h --- 5882+dfsg-2/ggml/src/ggml-cann/aclnn_ops.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/aclnn_ops.h 2025-09-30 07:36:33.000000000 +0000 @@ -23,6 +23,7 @@ #ifndef CANN_ACLNN_OPS #define CANN_ACLNN_OPS +#include #include #include #include @@ -423,16 +424,26 @@ void ggml_cann_softmax(ggml_backend_cann * * @details This function retrieves rows from a source tensor src0 according to * the indices provided in another tensor src1 and stores the result in - * a destination tensor (\p dst). It supports different data types - * including F32, F16, Q4_0, and Q8_0. + * a destination tensor (\p dst). * * @param ctx The backend CANN context for executing operations. * @param dst The destination tensor where the extracted rows will be stored. - * dst->op is `GGML_OP_GET_ROWS`. */ void ggml_cann_get_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst); /** + * @brief Writes specific rows into a tensor at positions specified by indices. + * + * @details This function copies rows from a source tensor into a destination + * tensor (\p dst) at the positions indicated by the indices in another + * tensor. + * + * @param ctx The backend CANN context for executing operations. + * @param dst The destination tensor where the specified rows will be updated. + */ +void ggml_cann_set_rows(ggml_backend_cann_context& ctx, ggml_tensor* dst); + +/** * @brief Executes matrix multiplication for the given tensor. * * @details This function performs matrix multiplication on the source tensors @@ -1021,6 +1032,37 @@ inline void ggml_cann_async_memset(ggml_ void ggml_cann_mul_mat_id(ggml_backend_cann_context& ctx, ggml_tensor* dst); /** + * @brief Check whether a tensor is a weight tensor for matrix multiplication. + * + * @details Checks whether the given tensor serves as weight parameters in matrix multiplication operations, + * typically within neural network layers. The function maintains a static set of canonical weight + * naming suffixes from Transformer-based architectures. Uses substring matching to identify weight + * tensors even with hierarchical naming patterns. + * + * @param tensor Pointer to the target ggml_tensor object (const-qualified). + */ +static bool is_matmul_weight(const ggml_tensor* tensor) { + std::string name = ggml_get_name(tensor); + static const std::unordered_set weight_suffixes{ + "output.weight", + "attn_q.weight", + "attn_k.weight", + "attn_v.weight", + "attn_output.weight", + "ffn_gate.weight", + "ffn_up.weight", + "ffn_down.weight" + }; + + for (const auto& suffix : weight_suffixes) { + if (name.find(suffix) != std::string::npos) { + return true; + } + } + return false; +} + +/** * @brief Applies a element-wise operation to two input tensors using the CANN * backend. * @@ -1066,7 +1108,7 @@ void ggml_cann_binary_op(ggml_backend_ca * @param dst The destination tensor. Its src[0] is treated as the input tensor. */ template - void ggml_cann_unary_op(ggml_backend_cann_context& ctx, ggml_tensor* dst) { + void ggml_cann_op_unary(ggml_backend_cann_context& ctx, ggml_tensor* dst) { ggml_tensor* src = dst->src[0]; aclTensor* acl_src = ggml_cann_create_tensor(src); @@ -1077,49 +1119,125 @@ template src[0]`. + * Internally, this function handles the conversion from GGML tensors to ACL tensors, + * calls the provided unary op, and manages resource cleanup. The input is assumed + * to be `dst->src[0]`, and the result is written to `dst`. + * + * This utility simplifies writing unary op wrappers by abstracting tensor preparation. + * + * @param unary_op A callable that performs the unary operation using CANN ACL APIs. + * @param ctx The CANN context for operation execution. + * @param dst The destination ggml_tensor where the result will be stored. + * The input tensor is assumed to be `dst->src[0]`. + * + * @see GGML_CANN_CALL_OP_UNARY */ -void ggml_cann_unary_op( +void ggml_cann_op_unary( std::function unary_op, ggml_backend_cann_context& ctx, ggml_tensor* dst); /** - * @brief Helper macro to invoke a unary ACL operation using ggml_cann_unary_op. + * @brief Applies a gated (GLU-style) unary operation using the CANN backend. + * + * @details This function performs a gated activation such as GEGLU or ReGLU. + * It supports two input modes: + * + * 1. **Dual input mode**: `dst->src[0]` and `dst->src[1]` are both valid tensors. + * These are used directly as the value and gate tensors. + * + * 2. **Packed input mode**: Only `dst->src[0]` is valid, and it is assumed to + * contain a concatenation of value and gate along the first dimension. This tensor + * will be split into two equal halves to form the value and gate inputs. * - * This macro defines an inline lambda wrapping a specific ACL operation name, - * and passes it to the templated ggml_cann_unary_op function. It simplifies - * calling unary ops by hiding the lambda boilerplate. + * The function applies a user-provided unary operation (e.g., GELU) to the value tensor, + * then multiplies the result in-place with the gate tensor: * - * Internally, the lambda will call: * @code - * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * dst = unary_op(value) * gate; * @endcode * + * The `swapped` parameter (from `dst->op_params[1]`) allows flipping the + * order of value/gate in the packed input case. + * + * @param unary_op A callable that performs the unary operation using CANN ACL APIs. + * It receives (ctx, acl_value_tensor, acl_output_tensor). + * @param ctx The CANN context used for execution. + * @param dst The destination ggml_tensor. Source tensors are in `dst->src[0]` and optionally `src[1]`. + * + * @see GGML_CANN_CALL_OP_UNARY_GATED + */ +void ggml_cann_op_unary_gated( + std::function unary_op, + ggml_backend_cann_context& ctx, ggml_tensor* dst); + +/** + * @brief Helper macro to call a unary ACL operator via ggml_cann_op_unary. + * + * This macro wraps the specified ACLNN unary operator name into a lambda expression, + * and passes it to `ggml_cann_op_unary`, which handles the common logic for executing + * unary ops in the CANN backend. + * + * Internally, this macro expands to a lambda like: + * @code + * [](ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { + * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * }; + * @endcode + * + * This lambda is then passed to `ggml_cann_op_unary`, which applies the operation. + * * @param OP_NAME The name of the ACL unary operator to invoke via GGML_CANN_CALL_ACLNN_OP. * - * @see ggml_cann_unary_op + * @see ggml_cann_op_unary * @see GGML_CANN_CALL_ACLNN_OP */ -#define GGML_CANN_CALL_UNARY_OP(OP_NAME) \ +#define GGML_CANN_CALL_OP_UNARY(OP_NAME) \ do { \ auto lambda = [](ggml_backend_cann_context& ctx, \ aclTensor* acl_src, \ aclTensor* acl_dst) { \ GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); \ }; \ - ggml_cann_unary_op(lambda, ctx, dst); \ + ggml_cann_op_unary(lambda, ctx, dst); \ } \ while (0) + +/** + * @brief Helper macro to call a gated unary ACL operator via ggml_cann_op_unary_gated. + * + * This macro wraps the specified ACLNN unary operator name into a lambda expression, + * and passes it to `ggml_cann_op_unary_gated`, which handles the common logic for + * executing gated unary ops in the CANN backend. + * + * Internally, this macro expands to a lambda like: + * @code + * [](ggml_backend_cann_context& ctx, aclTensor* acl_src, aclTensor* acl_dst) { + * GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); + * }; + * @endcode + * + * This lambda is then passed to `ggml_cann_op_unary_gated`, which applies the operation. + * + * @param OP_NAME The name of the ACL unary operator to invoke via GGML_CANN_CALL_ACLNN_OP. + * + * @see ggml_cann_op_unary_gated + * @see GGML_CANN_CALL_ACLNN_OP + */ +#define GGML_CANN_CALL_OP_UNARY_GATED(OP_NAME) \ + do { \ + auto lambda = [](ggml_backend_cann_context& ctx, \ + aclTensor* acl_src, \ + aclTensor* acl_dst) { \ + GGML_CANN_CALL_ACLNN_OP(ctx, OP_NAME, acl_src, acl_dst); \ + }; \ + ggml_cann_op_unary_gated(lambda, ctx, dst); \ + } \ + while (0) + #endif // CANN_ACLNN_OPS diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/common.h 6641+dfsg-2/ggml/src/ggml-cann/common.h --- 5882+dfsg-2/ggml/src/ggml-cann/common.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/common.h 2025-09-30 07:36:33.000000000 +0000 @@ -38,6 +38,7 @@ #include #include #include +#include #include "../include/ggml-cann.h" #include "../include/ggml.h" @@ -106,6 +107,7 @@ int32_t ggml_cann_get_device(); std::optional get_env(const std::string& name); bool parse_bool(const std::string& value); +int parse_integer(const std::string& value); /** * @brief Abstract base class for memory pools used by CANN. @@ -337,6 +339,126 @@ private: int32_t device_; }; +#ifdef USE_ACL_GRAPH +struct ggml_graph_node_properties { + void * node_address; + ggml_op node_op; + int64_t ne[GGML_MAX_DIMS]; + size_t nb[GGML_MAX_DIMS]; + void * src_address[GGML_MAX_SRC]; + int32_t op_params[GGML_MAX_OP_PARAMS / sizeof(int32_t)]; +}; + +struct ggml_cann_graph { + ~ggml_cann_graph() { + if (graph != nullptr) { + ACL_CHECK(aclmdlRIDestroy(graph)); + } + } + + aclmdlRI graph = nullptr; + + std::vector ggml_graph_properties; +}; + +/** + * @brief LRU cache for managing ggml_cann_graph objects. + * + * This class maintains a list of shared_ptr to ggml_cann_graph objects + * and enforces a maximum capacity. It provides methods to push new graphs, + * move existing graphs to the front (most recently used), and clear the cache. + */ +struct ggml_cann_graph_lru_cache { + size_t capacity; /**< Maximum number of graphs in the cache. */ + + std::list cache_list; /**< List storing cached graphs as raw pointers. */ + + ggml_cann_graph_lru_cache() { + capacity = parse_integer(get_env("GGML_CANN_GRAPH_CACHE_CAPACITY").value_or("12")); + } + + /** + * @brief Push a new graph to the front of the cache. + * If the cache exceeds capacity, the least recently used graph is deleted. + * @param new_node Pointer to the new ggml_cann_graph to cache. + * Ownership is transferred to the cache (cache will delete it). + */ + void push(ggml_cann_graph* new_node) { + if (cache_list.size() >= capacity) { + ggml_cann_graph* old = cache_list.back(); + cache_list.pop_back(); + delete old; // free the old graph + } + cache_list.push_front(new_node); + } + + /** + * @brief Move an existing graph to the front of the cache. + * @param node Pointer to the ggml_cann_graph to move. + */ + void move_to_front(ggml_cann_graph* node) { + cache_list.remove(node); + cache_list.push_front(node); + } + + /** + * @brief Clear all graphs from the cache (also frees memory). + */ + void clear() { + for (auto ptr : cache_list) { + delete ptr; + } + cache_list.clear(); + } + + /** + * @brief Destructor that clears the cache and frees all cached graphs. + */ + ~ggml_cann_graph_lru_cache() { + clear(); + } +}; +#endif // USE_ACL_GRAPH + +struct ggml_cann_rope_cache { + ~ggml_cann_rope_cache() { + if(theta_scale_cache != nullptr) { + ACL_CHECK(aclrtFree(theta_scale_cache)); + } + if(sin_cache != nullptr) { + ACL_CHECK(aclrtFree(sin_cache)); + } + if(cos_cache != nullptr) { + ACL_CHECK(aclrtFree(cos_cache)); + } + } + + void* theta_scale_cache = nullptr; + int64_t theta_scale_length = 0; + // sin/cos cache, used only to accelerate first layer on each device + void* sin_cache = nullptr; + void* cos_cache = nullptr; + int64_t position_length = 0; + // Properties to check before reusing the sincos cache + bool cached = false; + float ext_factor = 0.0f; + float theta_scale = 0.0f; + float freq_scale = 0.0f; + float attn_factor = 0.0f; + bool is_neox = false; +}; + +struct ggml_cann_tensor_cache { + ~ggml_cann_tensor_cache() { + if(cache != nullptr) { + ACL_CHECK(aclrtFree(cache)); + } + } + + void* cache = nullptr; + int64_t size = 0; +}; + /** * @brief Context for managing CANN backend operations. */ @@ -345,8 +467,18 @@ struct ggml_backend_cann_context { std::string name; /**< Name of the device. */ std::string description; /**< Description of the device. */ aclrtEvent copy_event = nullptr; /**< Event for managing copy operations. */ +#ifdef USE_ACL_GRAPH + /// Cached CANN ACL graph used for executing the current ggml computation graph. + ggml_cann_graph_lru_cache graph_lru_cache; + bool acl_graph_mode = true; +#endif cann_task_queue task_queue; bool async_mode; + // Rope Cache + ggml_cann_rope_cache rope_cache; + // Constant Pool + ggml_cann_tensor_cache rms_norm_one_tensor_cache; + ggml_cann_tensor_cache rms_norm_zero_tensor_cache; aclrtStream streams[GGML_CANN_MAX_STREAMS] = {nullptr}; /**< Array of streams for the device. */ @@ -362,6 +494,13 @@ struct ggml_backend_cann_context { async_mode = parse_bool(get_env("GGML_CANN_ASYNC_MODE").value_or("")); GGML_LOG_INFO("%s: device %d async operator submission is %s\n", __func__, device, async_mode ? "ON" : "OFF"); +#ifdef USE_ACL_GRAPH + acl_graph_mode = parse_bool(get_env("GGML_CANN_ACL_GRAPH").value_or("on")); + GGML_LOG_INFO("%s: device %d execution mode is %s (%s)\n", + __func__, device, + acl_graph_mode ? "GRAPH" : "EAGER", + acl_graph_mode ? "acl graph enabled" : "acl graph disabled"); +#endif } /** @@ -387,7 +526,10 @@ struct ggml_backend_cann_context { */ aclrtStream stream(int stream) { if (streams[stream] == nullptr) { - ggml_cann_set_device(device); + // If the device is not set here, destroying the stream later may cause a mismatch + // between the thread contexts where the stream was created and destroyed. + // However, I printed the device_id, thread_id, and stream, and they are all consistent. + ACL_CHECK(aclrtSetDevice(device)); ACL_CHECK(aclrtCreateStream(&streams[stream])); } return streams[stream]; diff -pruN 5882+dfsg-2/ggml/src/ggml-cann/ggml-cann.cpp 6641+dfsg-2/ggml/src/ggml-cann/ggml-cann.cpp --- 5882+dfsg-2/ggml/src/ggml-cann/ggml-cann.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cann/ggml-cann.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -24,6 +24,7 @@ #include #include +#include #include #include @@ -74,13 +75,12 @@ * @param device The device ID to set. */ void ggml_cann_set_device(const int32_t device) { - // TODO: uncomment these lines after empty context has fixed. - // int current_device; - // ACL_CHECK(aclrtGetDevice(¤t_device)); - - // if (device == current_device) { - // return; - // } + int current_device = -1; + aclrtGetDevice(¤t_device); + + if (device == current_device) { + return; + } ACL_CHECK(aclrtSetDevice(device)); } @@ -116,6 +116,24 @@ bool parse_bool(const std::string& value } /** + * @brief Parse a string as an integer, returning 0 if invalid. + * + * This function attempts to convert the input string `value` to an `int`. + * If the string is not a valid integer or is out of the `int` range, + * it returns 0. + * + * @param value The string to parse. + * @return The parsed integer, or 0 if conversion fails. + */ +int parse_integer(const std::string& value) { + try { + return std::stoi(value); + } catch (...) { + return 0; + } +} + +/** * @brief Initialize the CANN device information. * * This function initializes the CANN device information by obtaining the @@ -1115,6 +1133,98 @@ static enum ggml_status ggml_backend_can return GGML_STATUS_SUCCESS; } +/** + * @brief Workspace for caching NZ buffers per device. + * + * This struct manages a device buffer used in NZ computations. It supports + * allocation, reallocation, and clearing of cached memory. The struct is + * designed to be used with a global array, one per device. + */ +struct ggml_cann_nz_workspace { + void* ptr; // Pointer to allocated device buffer + size_t allocated; // Size of currently allocated buffer in bytes + + /** + * @brief Constructor. Initializes the workspace with no allocated memory. + */ + ggml_cann_nz_workspace() : ptr(nullptr), allocated(0) {} + + /** + * @brief Free cached memory and reset the workspace. + * + * If a buffer has been allocated, this function releases it using + * aclrtFree and resets internal state. + */ + void clear() { + if (ptr) { + ACL_CHECK(aclrtFree(ptr)); + ptr = nullptr; + allocated = 0; + } + } + + /** + * @brief Allocate or reallocate the workspace buffer. + * + * If the requested size is larger than the currently allocated size, + * the old buffer will be freed and a new buffer of the requested size + * will be allocated on the device. + * + * @param new_size Size in bytes to allocate for the workspace. + */ + void realloc(size_t new_size) { + if (new_size > allocated) { + clear(); + ACL_CHECK(aclrtMalloc(&ptr, new_size, ACL_MEM_MALLOC_HUGE_FIRST)); + allocated = new_size; + } + } + + /** + * @brief Get the device buffer pointer. + * + * @return Pointer to the allocated buffer, or nullptr if not allocated. + */ + void* get() const { return ptr; } +}; + +/** + * @brief Global array of NZ workspaces, one per device. + */ +static ggml_cann_nz_workspace g_nz_workspaces[GGML_CANN_MAX_DEVICES]; + +/** + * @brief Convert tensor weights to NZ format using Ascend CANN API. + * + * This function creates a transposed tensor descriptor and performs the + * TransMatmulWeight operation. Converting tensor formats can significantly + * improve performance on certain hardware. + * + * @param tensor Pointer to the input ggml_tensor containing the weights. + * @param offset Byte offset within the tensor data buffer where weights start. + * @param device device id. + * + * @note The workspace buffer used in this function is managed globally and reused + * across calls. This reduces overhead from repeated memory allocation and deallocation. + */ +static void weight_format_to_nz(ggml_tensor *tensor, size_t offset, int device) { + aclTensor* weightTransposed = ggml_cann_create_tensor(tensor, tensor->ne, + tensor->nb, 2, ACL_FORMAT_ND, offset); + uint64_t workspaceSize = 0; + aclOpExecutor *executor; + + // TransMatmulWeight + ACL_CHECK(aclnnTransMatmulWeightGetWorkspaceSize(weightTransposed, + &workspaceSize, &executor)); + // Avoid frequent malloc/free of the workspace. + g_nz_workspaces[device].realloc(workspaceSize); + + void* g_nz_workspace = g_nz_workspaces[device].get(); + + ACL_CHECK(aclnnTransMatmulWeight(g_nz_workspace, workspaceSize, executor, nullptr)); + ACL_CHECK(aclDestroyTensor(weightTransposed)); +} + // TODO: need handle tensor which has paddings. /** * @brief Set tensor data in a CANN buffer. @@ -1139,9 +1249,16 @@ static void ggml_backend_cann_buffer_set // For acl, synchronous functions use this default stream. // Why aclrtSynchronizeDevice? + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("on")); if (!need_transform(tensor->type)) { ACL_CHECK(aclrtMemcpy((char *)tensor->data + offset, size, data, size, ACL_MEMCPY_HOST_TO_DEVICE)); + if (weight_to_nz && is_matmul_weight((const ggml_tensor*)tensor)) { + GGML_ASSERT(tensor->ne[2] == 1); + GGML_ASSERT(tensor->ne[3] == 1); + weight_format_to_nz(tensor, offset, ctx->device); + } } else { void *transform_buffer = malloc(size); ggml_backend_cann_transform(tensor, data, transform_buffer); @@ -1216,6 +1333,10 @@ static bool ggml_backend_cann_buffer_cpy ACL_MEMCPY_DEVICE_TO_DEVICE)); return true; } else { +#ifdef ASCEND_310P + // TODO: Support 310p P2P copy + return false; +#endif // Different device but can access by peer. int32_t canAccessPeer = 0; ACL_CHECK(aclrtDeviceCanAccessPeer(&canAccessPeer, src_ctx->device, @@ -1375,20 +1496,32 @@ static size_t ggml_backend_cann_buffer_t size_t size = ggml_nbytes(tensor); int64_t ne0 = tensor->ne[0]; + // Only check env once. + static bool weight_to_nz = parse_bool(get_env("GGML_CANN_WEIGHT_NZ").value_or("on")); + // last line must bigger than 32, because every single op deal at // least 32 bytes. // TODO: quantized type? // int64_t line_size = ne0 * ggml_element_size(tensor); // int64_t line_size_align_32 = (line_size + 31) & ~31; // size += (line_size_align_32 - line_size); - - // TODO: not support quantized yet. - // TODO: consider un-continue tensor. if (ggml_is_quantized(tensor->type)) { if (ne0 % MATRIX_ROW_PADDING != 0) { size += ggml_row_size( tensor->type, MATRIX_ROW_PADDING - ne0 % MATRIX_ROW_PADDING); } + } else if (weight_to_nz && is_matmul_weight((const ggml_tensor*)tensor)) { + // NZ format weight are not support quantized yet. + // If ND tensor transform to NZ, size may changed. + int64_t shape[] = {tensor->ne[1], tensor->ne[0]}; + GGML_ASSERT(tensor->ne[2] == 1); + GGML_ASSERT(tensor->ne[3] == 1); + const aclIntArray *acl_shape = aclCreateIntArray(shape, 2); + size_t new_size; + ACL_CHECK(aclnnCalculateMatmulWeightSizeV2(acl_shape, + ggml_cann_type_mapping(tensor->type), &new_size)); + ACL_CHECK(aclDestroyIntArray(acl_shape)); + size = std::max(size, new_size); } return size; @@ -1594,6 +1727,9 @@ static bool ggml_cann_compute_forward(gg case GGML_OP_GET_ROWS: ggml_cann_get_rows(ctx, dst); break; + case GGML_OP_SET_ROWS: + ggml_cann_set_rows(ctx, dst); + break; case GGML_OP_DUP: ggml_cann_dup(ctx, dst); break; @@ -1616,16 +1752,18 @@ static bool ggml_cann_compute_forward(gg case GGML_OP_UNARY: switch (ggml_get_unary_op(dst)) { case GGML_UNARY_OP_ABS: - GGML_CANN_CALL_UNARY_OP(Abs); + GGML_CANN_CALL_OP_UNARY(Abs); break; case GGML_UNARY_OP_NEG: - GGML_CANN_CALL_UNARY_OP(Neg); + GGML_CANN_CALL_OP_UNARY(Neg); break; case GGML_UNARY_OP_GELU: - GGML_CANN_CALL_UNARY_OP(Gelu); + case GGML_UNARY_OP_GELU_ERF: + // aclnnGelu internally uses the erf-based approximation. + GGML_CANN_CALL_OP_UNARY(Gelu); break; case GGML_UNARY_OP_SILU: - GGML_CANN_CALL_UNARY_OP(Silu); + GGML_CANN_CALL_OP_UNARY(Silu); break; case GGML_UNARY_OP_GELU_QUICK: { auto lambda = [](ggml_backend_cann_context& ctx, @@ -1633,31 +1771,31 @@ static bool ggml_cann_compute_forward(gg aclTensor* acl_dst) { GGML_CANN_CALL_ACLNN_OP(ctx, GeluV2, acl_src, 0, acl_dst); }; - ggml_cann_unary_op(lambda, ctx, dst); + ggml_cann_op_unary(lambda, ctx, dst); } break; case GGML_UNARY_OP_TANH: - GGML_CANN_CALL_UNARY_OP(Tanh); + GGML_CANN_CALL_OP_UNARY(Tanh); break; case GGML_UNARY_OP_RELU: - GGML_CANN_CALL_UNARY_OP(Relu); + GGML_CANN_CALL_OP_UNARY(Relu); break; case GGML_UNARY_OP_SIGMOID: - GGML_CANN_CALL_UNARY_OP(Sigmoid); + GGML_CANN_CALL_OP_UNARY(Sigmoid); break; case GGML_UNARY_OP_HARDSIGMOID: - GGML_CANN_CALL_UNARY_OP(Hardsigmoid); + GGML_CANN_CALL_OP_UNARY(Hardsigmoid); break; case GGML_UNARY_OP_HARDSWISH: - GGML_CANN_CALL_UNARY_OP(Hardswish); + GGML_CANN_CALL_OP_UNARY(Hardswish); break; case GGML_UNARY_OP_EXP: - GGML_CANN_CALL_UNARY_OP(Exp); + GGML_CANN_CALL_OP_UNARY(Exp); break; case GGML_UNARY_OP_ELU: ggml_cann_elu(ctx, dst); break; case GGML_UNARY_OP_SGN: - GGML_CANN_CALL_UNARY_OP(Sign); + GGML_CANN_CALL_OP_UNARY(Sign); break; case GGML_UNARY_OP_STEP: ggml_cann_step(ctx, dst); @@ -1666,6 +1804,31 @@ static bool ggml_cann_compute_forward(gg return false; } break; + case GGML_OP_GLU: + switch (ggml_get_glu_op(dst)) { + case GGML_GLU_OP_REGLU: + GGML_CANN_CALL_OP_UNARY_GATED(Relu); + break; + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_GEGLU_ERF: + // aclnnGelu internally uses the erf-based approximation. + GGML_CANN_CALL_OP_UNARY_GATED(Gelu); + break; + case GGML_GLU_OP_SWIGLU: + GGML_CANN_CALL_OP_UNARY_GATED(Silu); + break; + case GGML_GLU_OP_GEGLU_QUICK: { + auto lambda = [](ggml_backend_cann_context& ctx, + aclTensor* acl_src, + aclTensor* acl_dst) { + GGML_CANN_CALL_ACLNN_OP(ctx, GeluV2, acl_src, 0, acl_dst); + }; + ggml_cann_op_unary_gated(lambda, ctx, dst); + } break; + default: + return false; + } + break; case GGML_OP_NORM: ggml_cann_norm(ctx, dst); break; @@ -1708,7 +1871,7 @@ static bool ggml_cann_compute_forward(gg ggml_cann_binary_op(ctx, dst); break; case GGML_OP_SQRT: - GGML_CANN_CALL_UNARY_OP(Sqrt); + GGML_CANN_CALL_OP_UNARY(Sqrt); break; case GGML_OP_CLAMP: ggml_cann_clamp(ctx, dst); @@ -1753,16 +1916,16 @@ static bool ggml_cann_compute_forward(gg ggml_cann_argmax(ctx, dst); break; case GGML_OP_COS: - ggml_cann_unary_op(ctx, dst); + ggml_cann_op_unary(ctx, dst); break; case GGML_OP_SIN: - ggml_cann_unary_op(ctx, dst); + ggml_cann_op_unary(ctx, dst); break; case GGML_OP_CONV_TRANSPOSE_1D: ggml_cann_conv_transpose_1d(ctx, dst); break; case GGML_OP_LOG: - GGML_CANN_CALL_UNARY_OP(Log); + GGML_CANN_CALL_OP_UNARY(Log); break; case GGML_OP_MEAN: ggml_cann_mean(ctx, dst); @@ -1895,6 +2058,8 @@ static bool ggml_backend_cann_cpy_tensor GGML_ASSERT(ggml_backend_is_cann(backend_src) || ggml_backend_is_cann(backend_dst)); + GGML_ASSERT(!is_matmul_weight((const ggml_tensor*)src)); + if (!ggml_backend_buffer_is_cann(src->buffer) || !ggml_backend_buffer_is_cann(dst->buffer)) { return false; @@ -1911,7 +2076,14 @@ static bool ggml_backend_cann_cpy_tensor (ggml_backend_cann_context*)backend_dst->context; size_t copy_size = ggml_nbytes(dst); + if (copy_size == 0) { + return true; + } if (backend_src != backend_dst) { +#ifdef ASCEND_310P + // TODO: Support 310p P2P copy + return false; +#endif ggml_backend_cann_buffer_context* buf_ctx_src = (ggml_backend_cann_buffer_context*)buf_src->context; ggml_backend_cann_buffer_context* buf_ctx_dst = @@ -1928,7 +2100,6 @@ static bool ggml_backend_cann_cpy_tensor } // need open both directions for memcpyasync between devices. - ggml_cann_set_device(cann_ctx_dst->device); ACL_CHECK(aclrtDeviceEnablePeerAccess(cann_ctx_src->device, 0)); ggml_cann_set_device(cann_ctx_src->device); ACL_CHECK(aclrtDeviceEnablePeerAccess(cann_ctx_dst->device, 0)); @@ -1938,9 +2109,17 @@ static bool ggml_backend_cann_cpy_tensor ACL_CHECK(aclrtMemcpyAsync(dst->data, copy_size, src->data, copy_size, ACL_MEMCPY_DEVICE_TO_DEVICE, cann_ctx_src->stream())); - - //TODO: workaround for Event didn`t work here. - aclrtSynchronizeStream(cann_ctx_src->stream()); + // record event on src stream after the copy + // TODO: this event is not effective with acl graph mode, change to use aclrtSynchronizeStream + // if (!cann_ctx_src->copy_event) { + // ACL_CHECK(aclrtCreateEventWithFlag(&cann_ctx_src->copy_event, ACL_EVENT_SYNC)); + // } + // ACL_CHECK(aclrtRecordEvent(cann_ctx_src->copy_event, cann_ctx_src->stream())); + + // // wait on dst stream for the copy to complete + // ggml_cann_set_device(cann_ctx_dst->device); + // ACL_CHECK(aclrtStreamWaitEvent(cann_ctx_dst->stream(), cann_ctx_src->copy_event)); + ACL_CHECK(aclrtSynchronizeStream(cann_ctx_src->stream())); } else { // src and dst are on the same backend ACL_CHECK(aclrtMemcpyAsync(dst->data, copy_size, src->data, copy_size, @@ -1967,6 +2146,193 @@ static void ggml_backend_cann_synchroniz ACL_CHECK(aclrtSynchronizeStream(cann_ctx->stream())); } +#ifdef USE_ACL_GRAPH +/** + * @brief Add a new CANN graph to the LRU cache by populating node properties from the ggml graph. + * + * This function creates a new ggml_cann_graph object and fills its node properties + * (operation type, dimensions, strides, input sources, and operation parameters) + * based on the current ggml computation graph. + * + * Each node in the ggml graph is mapped to a property entry in the new CANN graph: + * - node address + * - operation type + * - shape (ne) and strides (nb) + * - source tensor addresses + * - operation parameters + * + * After initialization, the new graph is pushed into the LRU cache owned by the + * CANN backend context. The cache takes ownership of the graph and manages its + * lifetime (including deletion upon eviction). + * + * @param cann_ctx The CANN backend context containing the graph cache. + * @param cgraph The current ggml computation graph. + */ +static void add_lru_matched_graph_node_properties( + ggml_backend_cann_context * cann_ctx, + ggml_cgraph * cgraph) { + // Create a new ggml_cann_graph object on the heap (its lifetime is managed by the cache). + ggml_cann_graph * new_graph = new ggml_cann_graph(); + new_graph->ggml_graph_properties.resize(cgraph->n_nodes); + + for (int node_idx = 0; node_idx < cgraph->n_nodes; ++node_idx) { + ggml_tensor * node = cgraph->nodes[node_idx]; + auto & prop = new_graph->ggml_graph_properties[node_idx]; + + prop.node_address = node->data; + prop.node_op = node->op; + + std::copy_n(node->ne, GGML_MAX_DIMS, prop.ne); + std::copy_n(node->nb, GGML_MAX_DIMS, prop.nb); + + for (int src = 0; src < GGML_MAX_SRC; ++src) { + prop.src_address[src] = node->src[src] ? node->src[src]->data : nullptr; + } + + memcpy(prop.op_params, node->op_params, GGML_MAX_OP_PARAMS); + } + + // Insert into the LRU cache (cache takes ownership and will delete it when evicted). + cann_ctx->graph_lru_cache.push(new_graph); +} + +/** + * @brief Check if a ggml tensor node matches a previously captured CANN graph node. + * + * This function compares all relevant fields (address, op type, shape, source inputs, op params) + * to determine whether the current node matches a previously recorded version. + * + * @param node The current ggml tensor node. + * @param graph_node_properties The stored properties of a CANN graph node. + * @return true if all fields match (excluding GGML_OP_VIEW); false otherwise. + */ +static bool ggml_graph_node_has_matching_properties(ggml_tensor * node, ggml_graph_node_properties * graph_node_properties) { + if (node->data != graph_node_properties->node_address && + node->op != GGML_OP_VIEW) { + return false; + } + if (node->op != graph_node_properties->node_op) { + return false; + } + for (int i = 0; i < GGML_MAX_DIMS; i++) { + if (node->ne[i] != graph_node_properties->ne[i]) { + return false; + } + if (node->nb[i] != graph_node_properties->nb[i]) { + return false; + } + } + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (node->src[i] && + node->src[i]->data != graph_node_properties->src_address[i] && + node->op != GGML_OP_VIEW + ) { + return false; + } + } + if (node->op == GGML_OP_SCALE && + memcmp(graph_node_properties->op_params, node->op_params, GGML_MAX_OP_PARAMS) != 0) { + return false; + } + return true; +} + +/** + * @brief Check whether there is a cached CANN graph that matches the current ggml graph. + * + * This function iterates through the cached CANN graphs stored in the LRU cache and + * compares them against the given ggml computation graph. A match requires that the + * number of nodes is the same and that each node’s properties (operation type, + * dimensions, strides, inputs, and operation parameters) are identical. + * + * If a matching graph is found, it is promoted to the front of the LRU cache and the + * function returns true. Otherwise, the function returns false, indicating that a new + * CANN graph needs to be captured. + * + * @param cann_ctx The CANN backend context containing the graph cache. + * @param cgraph The current ggml computation graph. + * @return true if a matching cached graph exists; false otherwise. + */ +static bool is_matched_graph(ggml_backend_cann_context * cann_ctx, ggml_cgraph * cgraph) { + ggml_cann_graph_lru_cache &lru_cache = cann_ctx->graph_lru_cache; + for (auto &graph_ptr : lru_cache.cache_list) { + // Skip graphs with a different number of nodes. + if (graph_ptr->ggml_graph_properties.size() != static_cast(cgraph->n_nodes)) { + continue; + } + + // Check if all nodes match. + bool all_match = true; + for (int i = 0; i < cgraph->n_nodes; ++i) { + if (!ggml_graph_node_has_matching_properties(cgraph->nodes[i], &graph_ptr->ggml_graph_properties[i])) { + all_match = false; + break; + } + } + + if (all_match) { + // update cache_list && renturn graph_ptr + lru_cache.move_to_front(graph_ptr); + return true; + } + } + + return false; +} +#endif // USE_ACL_GRAPH + +/** + * @brief Evaluate the computation graph and optionally capture or execute it using CANN graph API. + * + * If CANN graph execution is enabled and graph capture is required, this function begins + * graph capture, runs the graph, ends capture, and stores the captured graph. + * + * Otherwise, it falls back to op-by-op execution using the CANN compute kernel dispatcher. + * + * @param cann_ctx The CANN backend context. + * @param cgraph The ggml computation graph. + * @param use_cann_graph Whether to use CANN graph execution. + * @param cann_graph_update_required Whether graph capture is needed due to graph changes. + */ +static void evaluate_and_capture_cann_graph(ggml_backend_cann_context * cann_ctx, ggml_cgraph * cgraph, + bool & use_cann_graph, bool & cann_graph_update_required) { +#ifdef USE_ACL_GRAPH + ggml_cann_graph* matched_graph = cann_ctx->graph_lru_cache.cache_list.front(); + if (use_cann_graph && cann_graph_update_required) { + ACL_CHECK(aclmdlRICaptureBegin(cann_ctx->stream(), ACL_MODEL_RI_CAPTURE_MODE_GLOBAL)); + } +#endif // USE_ACL_GRAPH + // Only perform the graph execution if CANN graphs are not enabled, or we are capturing the graph. + // With the use of CANN graphs, the execution will be performed by the graph launch. + if (!use_cann_graph || cann_graph_update_required) { + for (int i = 0; i < cgraph->n_nodes; i++) { + ggml_tensor * node = cgraph->nodes[i]; + + if (ggml_is_empty(node) || node->op == GGML_OP_RESHAPE || node->op == GGML_OP_TRANSPOSE || node->op == GGML_OP_VIEW || node->op == GGML_OP_PERMUTE || node->op == GGML_OP_NONE) { + continue; + } + + bool ok = ggml_cann_compute_forward(*cann_ctx, node); + if (!ok) { + GGML_LOG_ERROR("%s: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); + } + GGML_ASSERT(ok); + } + } + +#ifdef USE_ACL_GRAPH + if (use_cann_graph && cann_graph_update_required) { // End CANN graph capture + ACL_CHECK(aclmdlRICaptureEnd(cann_ctx->stream(), &matched_graph->graph)); + } + + if (use_cann_graph) { + // Execute graph + ACL_CHECK(aclmdlRIExecuteAsync(matched_graph->graph, cann_ctx->stream())); + } +#endif // USE_ACL_GRAPH +} + + /** * @brief Computes a computational graph using a CANN backend. * @@ -1983,25 +2349,54 @@ static enum ggml_status ggml_backend_can ggml_backend_t backend, ggml_cgraph* cgraph) { ggml_backend_cann_context* cann_ctx = (ggml_backend_cann_context*)backend->context; - ggml_cann_set_device(cann_ctx->device); + g_nz_workspaces[cann_ctx->device].clear(); - for (int i = 0; i < cgraph->n_nodes; i++) { - ggml_tensor* node = cgraph->nodes[i]; + // calculate rope cache for fist layer in current device. + cann_ctx->rope_cache.cached = false; - if (ggml_is_empty(node) || node->op == GGML_OP_NONE) { - continue; +#ifdef USE_ACL_GRAPH + bool use_cann_graph = true; + bool cann_graph_update_required = false; + + static bool prefill_use_graph = parse_bool(get_env("GGML_CANN_PREFILL_USE_GRAPH").value_or("")); + if (!prefill_use_graph) { + // Do not use acl_graph for prefill. + for (int i = 0; i < cgraph->n_nodes; i++) { + ggml_tensor * node = cgraph->nodes[i]; + // TODO: Optimize here. Currently, we can only + // get seq_len by FA's input. + if (node->op == GGML_OP_FLASH_ATTN_EXT) { + // Q -> src[0], shape: [B, S, N, D] + use_cann_graph = (node->src[0]->ne[1] == 1); + break; + } } + } - bool ok = ggml_cann_compute_forward(*cann_ctx, node); - - if (!ok) { - GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, - node->name, ggml_op_name(node->op)); - } - GGML_ASSERT(ok); + if (!cann_ctx->acl_graph_mode) { + use_cann_graph = false; } + if (use_cann_graph) { + // If no matching graph is found, the graph needs to be recaptured. + cann_graph_update_required = !is_matched_graph(cann_ctx, cgraph); + if (cann_graph_update_required) { + // If no matching graph is found, add a new ACL graph. + add_lru_matched_graph_node_properties(cann_ctx, cgraph); + } + } +#else + bool use_cann_graph = false; + bool cann_graph_update_required = false; +#endif // USE_ACL_GRAPH + evaluate_and_capture_cann_graph( + cann_ctx, + cgraph, + use_cann_graph, + cann_graph_update_required + ); + return GGML_STATUS_SUCCESS; } @@ -2036,10 +2431,23 @@ static bool ggml_backend_cann_supports_o case GGML_UNARY_OP_ELU: case GGML_UNARY_OP_SGN: case GGML_UNARY_OP_STEP: + case GGML_UNARY_OP_GELU_ERF: + return true; + default: + return false; + } + case GGML_OP_GLU: + switch (ggml_get_glu_op(op)) { + case GGML_GLU_OP_REGLU: + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_GEGLU_ERF: + case GGML_GLU_OP_GEGLU_QUICK: return true; default: return false; } + break; case GGML_OP_MUL_MAT: { switch (op->src[0]->type) { case GGML_TYPE_F16: @@ -2048,7 +2456,7 @@ static bool ggml_backend_cann_supports_o case GGML_TYPE_Q8_0: case GGML_TYPE_Q4_0: #ifdef ASCEND_310P - // Q4 && Q8 per group is not suppor on 310p device + // Q4 && Q8 per group is not support on 310p device return false; #endif // only support contiguous for quantized types. @@ -2066,7 +2474,7 @@ static bool ggml_backend_cann_supports_o case GGML_TYPE_Q8_0: case GGML_TYPE_Q4_0: #ifdef ASCEND_310P - // Q4 && Q8 per group is not suppor on 310p device + // Q4 && Q8 per group is not support on 310p device return false; #endif // only support contiguous for quantized types. @@ -2086,12 +2494,15 @@ static bool ggml_backend_cann_supports_o return false; } } break; - case GGML_OP_SET_ROWS: - { - // TODO: add support - // ref: https://github.com/ggml-org/llama.cpp/pull/14274 - return false; - } break; + case GGML_OP_SET_ROWS: { + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + return true; + default: + return false; + } + } break; case GGML_OP_CPY: { ggml_tensor *src = op->src[0]; if ((op->type != GGML_TYPE_F32 && op->type != GGML_TYPE_F16) || @@ -2100,12 +2511,6 @@ static bool ggml_backend_cann_supports_o // only support F32 and F16. return false; } - - if (!ggml_are_same_shape(op, src) && !ggml_is_contiguous(op)) { - // unsupport dst is not contiguous. - return false; - } - return true; } break; case GGML_OP_CONT: { @@ -2120,16 +2525,10 @@ static bool ggml_backend_cann_supports_o } case GGML_OP_ROPE: { // TODO: with ops-test v == 1 - float ext_factor = 0.0f; - memcpy(&ext_factor, (const float *) op->op_params + 7, sizeof(float)); // TODO: n_dims <= ne0 if (op->src[0]->ne[0] != op->op_params[1]) { return false; } - // TODO: ext_factor != 0 - if (ext_factor != 0) { - return false; - } const int mode = ((const int32_t *) op->op_params)[2]; if (mode & GGML_ROPE_TYPE_MROPE) { @@ -2138,10 +2537,11 @@ static bool ggml_backend_cann_supports_o if (mode & GGML_ROPE_TYPE_VISION) { return false; } - +#ifdef ASCEND_310P if(!ggml_is_contiguous(op->src[0])){ return false; } +#endif return true; } case GGML_OP_UPSCALE: { @@ -2171,8 +2571,8 @@ static bool ggml_backend_cann_supports_o // value of paddingW should be at most half of kernelW return (p0 <= (k0 / 2)) && (p1 <= (k1 / 2)); } - case GGML_OP_SUM: case GGML_OP_DUP: + case GGML_OP_SUM: case GGML_OP_IM2COL: case GGML_OP_CONCAT: case GGML_OP_REPEAT: @@ -2203,21 +2603,29 @@ static bool ggml_backend_cann_supports_o case GGML_OP_ARGMAX: case GGML_OP_COS: case GGML_OP_SIN: - case GGML_OP_CONV_TRANSPOSE_1D: case GGML_OP_LOG: case GGML_OP_MEAN: case GGML_OP_PAD_REFLECT_1D: case GGML_OP_COUNT_EQUAL: return true; + case GGML_OP_CONV_TRANSPOSE_1D: + // TODO: ((weightL - 1) * dilationW - padLeft)=1336 should not be larger than 255. + return (op->src[0]->ne[0] - 1) <= 255; case GGML_OP_SCALE: float bias; - memcpy(&bias, (float*)op->op_params + 1, sizeof(float)); + memcpy(&bias, (const float *)(op->op_params) + 1, sizeof(float)); return bias == 0.0f; // TODO: support bias != 0.0f case GGML_OP_SOFT_MAX: - // TODO: support broadcast - // ref: https://github.com/ggml-org/llama.cpp/pull/14435 - return !op->src[1] || (op->src[1]->ne[2] == 1 && op->src[1]->ne[3] == 1); + // TODO: support attention sinks [TAG_ATTN_SINKS] + if (op->src[2]) { + return false; + } + return true; case GGML_OP_FLASH_ATTN_EXT:{ +#ifdef ASCEND_310P + // FA not support on 310p device + return false; +#endif // derived from [ggml-cuda.cu] if(op->src[1]->type != GGML_TYPE_F16 || op->src[2]->type != GGML_TYPE_F16){ return false; @@ -2228,24 +2636,20 @@ static bool ggml_backend_cann_supports_o if(op->type != GGML_TYPE_F16 && op->type != GGML_TYPE_F32 && op->type != GGML_TYPE_BF16){ return false; } - if (op->src[1]->ne[0] != op->src[2]->ne[0]) { - // different head sizes of K and V are not supported yet - return false; - } - if (op->src[0]->ne[0] == 192) { + // TODO: support attention sinks [TAG_ATTN_SINKS] + if (op->src[4]) { return false; } - if (op->src[0]->ne[0] == 576) { - // DeepSeek MLA + if (op->src[1]->ne[0] != op->src[2]->ne[0]) { + // different head sizes of K and V are not supported yet return false; } - // TODO: support broadcast - // ref: https://github.com/ggml-org/llama.cpp/pull/14435 - if (op->src[0]->ne[3] != 1) { + if (op->src[0]->ne[0] % 16 != 0) { + // TODO: padding to support return false; } float logitSoftcap = 0.0f; - memcpy(&logitSoftcap, (float*)op->op_params + 2, sizeof(float)); + memcpy(&logitSoftcap, (const float *)(op->op_params) + 2, sizeof(float)); if(logitSoftcap != 0.0f) { return false; } @@ -2352,6 +2756,7 @@ static const ggml_backend_i ggml_backend /* .graph_compute = */ ggml_backend_cann_graph_compute, /* .event_record = */ ggml_backend_cann_event_record, /* .event_wait = */ ggml_backend_cann_event_wait, + /* .graph_optimize = */ NULL, }; /** diff -pruN 5882+dfsg-2/ggml/src/ggml-common.h 6641+dfsg-2/ggml/src/ggml-common.h --- 5882+dfsg-2/ggml/src/ggml-common.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-common.h 2025-09-30 07:36:33.000000000 +0000 @@ -99,6 +99,9 @@ typedef sycl::half2 ggml_half2; #define QI4_1 (QK4_1 / (4 * QR4_1)) #define QR4_1 2 +#define QI_MXFP4 (QK_MXFP4 / (4 * QR_MXFP4)) +#define QR_MXFP4 2 + #define QI5_0 (QK5_0 / (4 * QR5_0)) #define QR5_0 2 @@ -184,6 +187,13 @@ typedef struct { } block_q4_1; static_assert(sizeof(block_q4_1) == 2 * sizeof(ggml_half) + QK4_1 / 2, "wrong q4_1 block size/padding"); +#define QK_MXFP4 32 +typedef struct { + uint8_t e; // E8M0 + uint8_t qs[QK_MXFP4/2]; +} block_mxfp4; +static_assert(sizeof(block_mxfp4) == sizeof(uint8_t) + QK_MXFP4/2, "wrong mxfp4 block size/padding"); + #define QK5_0 32 typedef struct { ggml_half d; // delta @@ -1074,10 +1084,17 @@ GGML_TABLE_BEGIN(uint32_t, iq3s_grid, 51 0x0f090307, 0x0f090501, 0x0f090b01, 0x0f0b0505, 0x0f0b0905, 0x0f0d0105, 0x0f0d0703, 0x0f0f0101, GGML_TABLE_END() +// TODO: fix name to kvalues_iq4_nl GGML_TABLE_BEGIN(int8_t, kvalues_iq4nl, 16) -127, -104, -83, -65, -49, -35, -22, -10, 1, 13, 25, 38, 53, 69, 89, 113, GGML_TABLE_END() +// e2m1 values (doubled) +// ref: https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf +GGML_TABLE_BEGIN(int8_t, kvalues_mxfp4, 16) + 0, 1, 2, 3, 4, 6, 8, 12, 0, -1, -2, -3, -4, -6, -8, -12, +GGML_TABLE_END() + #define NGRID_IQ1S 2048 #define IQ1S_DELTA 0.125f #define IQ1M_DELTA 0.125f diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-cpu/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-cpu/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -70,10 +70,12 @@ function(ggml_add_cpu_backend_variant_im if (GGML_OPENMP) find_package(OpenMP) if (OpenMP_FOUND) + set(GGML_OPENMP_ENABLED "ON" CACHE INTERNAL "") target_compile_definitions(${GGML_CPU_NAME} PRIVATE GGML_USE_OPENMP) target_link_libraries(${GGML_CPU_NAME} PRIVATE OpenMP::OpenMP_C OpenMP::OpenMP_CXX) else() + set(GGML_OPENMP_ENABLED "OFF" CACHE INTERNAL "") message(WARNING "OpenMP not found") endif() endif() @@ -222,7 +224,13 @@ function(ggml_add_cpu_backend_variant_im foreach(feature DOTPROD SVE MATMUL_INT8 FMA FP16_VECTOR_ARITHMETIC SME) string(FIND "${ARM_FEATURE}" "__ARM_FEATURE_${feature} 1" feature_pos) if (NOT ${feature_pos} EQUAL -1) - message(STATUS "ARM feature ${feature} enabled") + # Special handling for MATMUL_INT8 when machine doesn't support i8mm + if ("${feature}" STREQUAL "MATMUL_INT8" AND GGML_MACHINE_SUPPORTS_noi8mm) + message(STATUS "ARM feature ${feature} detected but unsetting due to machine not supporting i8mm") + list(APPEND ARCH_FLAGS -U__ARM_FEATURE_MATMUL_INT8) + else() + message(STATUS "ARM feature ${feature} enabled") + endif() endif() endforeach() endif() @@ -431,15 +439,31 @@ function(ggml_add_cpu_backend_variant_im ggml-cpu/arch/riscv/quants.c ggml-cpu/arch/riscv/repack.cpp ) - if (GGML_RVV) - if (GGML_XTHEADVECTOR) - list(APPEND ARCH_FLAGS -march=rv64gc_xtheadvector -mabi=lp64d) - elseif (GGML_RV_ZFH) - list(APPEND ARCH_FLAGS -march=rv64gcv_zfhmin -mabi=lp64d) - else() - list(APPEND ARCH_FLAGS -march=rv64gcv -mabi=lp64d) + if (GGML_CPU_RISCV64_SPACEMIT) + target_compile_definitions(${GGML_CPU_NAME} PRIVATE GGML_USE_CPU_RISCV64_SPACEMIT ${RISCV64_SPACEMIT_IME_SPEC}) + list(APPEND GGML_CPU_SOURCES + ggml-cpu/spacemit/ime.cpp + ggml-cpu/spacemit/ime.h + ggml-cpu/spacemit/ime1_kernels.cpp + ggml-cpu/spacemit/ime_kernels.h + ) + endif() + set(MARCH_STR "rv64gc") + if (GGML_RV_ZFH) + string(APPEND MARCH_STR "_zfh") + endif() + if (GGML_XTHEADVECTOR) + string(APPEND MARCH_STR "_xtheadvector") + elseif (GGML_RVV) + string(APPEND MARCH_STR "_v") + if (GGML_RV_ZVFH) + string(APPEND MARCH_STR "_zvfh") endif() endif() + if (GGML_RV_ZICBOP) + string(APPEND MARCH_STR "_zicbop") + endif() + list(APPEND ARCH_FLAGS "-march=${MARCH_STR}" -mabi=lp64d) elseif (GGML_SYSTEM_ARCH STREQUAL "s390x") message(STATUS "s390x detected") list(APPEND GGML_CPU_SOURCES ggml-cpu/arch/s390/quants.c) @@ -448,7 +472,6 @@ function(ggml_add_cpu_backend_variant_im # TODO: Separation to determine activation of VX/VXE/VXE2 if (${S390X_M} MATCHES "8561|8562") - set(GGML_NNPA OFF) message(STATUS "z15 target") list(APPEND ARCH_FLAGS -march=z15) elseif (${S390X_M} MATCHES "3931") @@ -456,8 +479,9 @@ function(ggml_add_cpu_backend_variant_im list(APPEND ARCH_FLAGS -march=z16) elseif (${S390X_M} MATCHES "9175|9176") # NOTE: Only available from GCC 15.1.0 onwards. Any z17 machine with compile issues must first verify their GCC version. + # binutils must also be updated to the latest for the -march=z17 flag to work. Otherwise, use -march=arch15. message(STATUS "z17 target") - list(APPEND ARCH_FLAGS -march=z17) + list(APPEND ARCH_FLAGS -march=arch15) else() message(STATUS "Unknown target") message(WARNING "Unknown target. If you are compiling for z14 and earlier, you might have to add -DGGML_VXE=OFF.") @@ -469,11 +493,6 @@ function(ggml_add_cpu_backend_variant_im list(APPEND ARCH_FLAGS -mvx -mzvector) list(APPEND ARCH_DEFINITIONS GGML_VXE) endif() - - if (GGML_NNPA) - message(STATUS "NNPA enabled") - list(APPEND ARCH_DEFINITIONS GGML_NNPA) - endif() elseif (CMAKE_SYSTEM_PROCESSOR MATCHES "wasm") message(STATUS "Wasm detected") list (APPEND GGML_CPU_SOURCES ggml-cpu/arch/wasm/quants.c) @@ -494,9 +513,9 @@ function(ggml_add_cpu_backend_variant_im # Fetch KleidiAI sources: include(FetchContent) - set(KLEIDIAI_COMMIT_TAG "v1.9.0") + set(KLEIDIAI_COMMIT_TAG "v1.14.0") set(KLEIDIAI_DOWNLOAD_URL "https://github.com/ARM-software/kleidiai/archive/refs/tags/${KLEIDIAI_COMMIT_TAG}.tar.gz") - set(KLEIDIAI_ARCHIVE_MD5 "2a8e1bb55d201557553545536489a017") + set(KLEIDIAI_ARCHIVE_MD5 "45e110675d93f99f82c23a1afcca76bc") if (POLICY CMP0135) cmake_policy(SET CMP0135 NEW) @@ -552,6 +571,7 @@ function(ggml_add_cpu_backend_variant_im list(APPEND GGML_KLEIDIAI_SOURCES ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_lhs_quant_pack_qsi8d32p_f32.c + ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_lhs_quant_pack_qsi8d32p4x8sb_f32_neon.c ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon.c ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_lhs_quant_pack_qsi8d32p_f32_neon.c ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0.c) @@ -572,8 +592,10 @@ function(ggml_add_cpu_backend_variant_im ${KLEIDIAI_SRC}/kai/ukernels/matmul/matmul_clamp_f32_qsi8d32p_qsi4c32p/kai_matmul_clamp_f32_qsi8d32p1vlx4_qsi4c32p4vlx4_1vlx4vl_sme2_mopa.c ${KLEIDIAI_SRC}/kai/ukernels/matmul/matmul_clamp_f32_qsi8d32p_qsi4c32p/kai_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4vlx4_1x4vl_sme2_sdot.c ${KLEIDIAI_SRC}/kai/ukernels/matmul/matmul_clamp_fp32_bf16p_bf16p/kai_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa.c + ${KLEIDIAI_SRC}/kai/ukernels/matmul/matmul_clamp_fp32_bf16p_bf16p/kai_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa_asm.S ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_lhs_pack_bf16p2vlx2_f32_sme.c - ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme.c) + ${KLEIDIAI_SRC}/kai/ukernels/matmul/pack/kai_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme.c + ${KLEIDIAI_SRC}/kai/kai_common_sme_asm.S) set(PRIVATE_ARCH_FLAGS "-fno-tree-vectorize;${PRIVATE_ARCH_FLAGS}+sve+sve2") endif() diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/amx/amx.cpp 6641+dfsg-2/ggml/src/ggml-cpu/amx/amx.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/amx/amx.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/amx/amx.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -7,7 +7,7 @@ #include "ggml-cpu.h" #include "traits.h" -#if defined(__gnu_linux__) +#if defined(__linux__) #include #include #endif @@ -186,7 +186,7 @@ static size_t ggml_backend_amx_buffer_ty #define XFEATURE_XTILEDATA 18 static bool ggml_amx_init() { -#if defined(__gnu_linux__) +#if defined(__linux__) if (syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_PERM, XFEATURE_XTILEDATA)) { fprintf(stderr, "AMX is not ready to be used!\n"); return false; @@ -194,6 +194,8 @@ static bool ggml_amx_init() { return true; #elif defined(_WIN32) return true; +#else + return false; #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/arm/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/arm/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/arm/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/arm/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -589,6 +589,67 @@ void ggml_vec_dot_q4_1_q8_1(int n, float *s = sumf; } +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + +#if defined __ARM_NEON + const int8x16_t values = vld1q_s8(kvalues_mxfp4); + const uint8x16_t m4b = vdupq_n_u8(0x0f); + uint8x16x2_t q4bits; + int8x16x4_t q4b; + int8x16x4_t q8b; + int32x4_t prod_1; + int32x4_t prod_2; + + for (; ib + 1 < nb; ib += 2) { + q4bits.val[0] = vld1q_u8(x[ib + 0].qs); + q4bits.val[1] = vld1q_u8(x[ib + 1].qs); + q8b.val[0] = vld1q_s8(y[ib + 0].qs); + q8b.val[1] = vld1q_s8(y[ib + 0].qs + 16); + q8b.val[2] = vld1q_s8(y[ib + 1].qs); + q8b.val[3] = vld1q_s8(y[ib + 1].qs + 16); + + q4b.val[0] = ggml_vqtbl1q_s8(values, vandq_u8 (q4bits.val[0], m4b)); + q4b.val[1] = ggml_vqtbl1q_s8(values, vshrq_n_u8(q4bits.val[0], 4)); + q4b.val[2] = ggml_vqtbl1q_s8(values, vandq_u8 (q4bits.val[1], m4b)); + q4b.val[3] = ggml_vqtbl1q_s8(values, vshrq_n_u8(q4bits.val[1], 4)); + + prod_1 = ggml_vdotq_s32(ggml_vdotq_s32(vdupq_n_s32(0), q4b.val[0], q8b.val[0]), q4b.val[1], q8b.val[1]); + prod_2 = ggml_vdotq_s32(ggml_vdotq_s32(vdupq_n_s32(0), q4b.val[2], q8b.val[2]), q4b.val[3], q8b.val[3]); + + sumf += + GGML_E8M0_TO_FP32_HALF(x[ib + 0].e) * GGML_CPU_FP16_TO_FP32(y[ib + 0].d) * vaddvq_s32(prod_1) + + GGML_E8M0_TO_FP32_HALF(x[ib + 1].e) * GGML_CPU_FP16_TO_FP32(y[ib + 1].d) * vaddvq_s32(prod_2); + } + +#endif + for (; ib < nb; ++ib) { + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); + int sumi1 = 0; + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; + } + sumf += d * (sumi1 + sumi2); + } + *s = sumf; +} + void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { const int qk = QK8_0; const int nb = n / qk; @@ -1236,44 +1297,10 @@ void ggml_vec_dot_tq1_0_q8_K(int n, floa *s = sumf; #else - const uint8_t pow3[6] = {1, 3, 9, 27, 81, 243}; - - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int sum = 0; - - for (size_t j = 0; j < sizeof(x->qs) - sizeof(x->qs) % 32; j += 32) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 32; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*32 + m]; - } - } - } - for (size_t j = sizeof(x->qs) - sizeof(x->qs) % 32; j < sizeof(x->qs); j += 16) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 16; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*16 + m]; - } - } - } - - for (size_t l = 0; l < 4; ++l) { - for (size_t j = 0; j < sizeof(x->qh); ++j) { - uint8_t q = x[i].qh[j] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[sizeof(x->qs)*5 + l*sizeof(x->qh) + j]; - } - } - - sumf += (float) sum * (GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d); - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq1_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1381,25 +1408,10 @@ void ggml_vec_dot_tq2_0_q8_K(int n, floa *s = sumf; #else - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int32_t sumi = 0; - - for (size_t j = 0; j < sizeof(x->qs); j += 32) { - for (size_t l = 0; l < 4; ++l) { - for (size_t k = 0; k < 32; ++k) { - sumi += y[i].qs[j*4 + l*32 + k] * (((x[i].qs[j + k] >> (l*2)) & 3) - 1); - } - } - } - - const float d = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - - sumf += (float) sumi * d; - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq2_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1729,45 +1741,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float *s = sum; #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2057,68 +2034,12 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = sum; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2431,61 +2352,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2578,66 +2452,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3093,47 +2915,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float } *s = sum; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3229,34 +3014,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, fl *s = 0.25f * sumf; #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3327,42 +3088,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, flo *s = 0.125f * sumf; #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3455,45 +3184,10 @@ void ggml_vec_dot_iq2_s_q8_K(int n, floa *s = 0.125f * sumf; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3553,36 +3247,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, fl *s = 0.5f * sumf; #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3689,48 +3357,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, floa *s = sumf; #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3793,36 +3423,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, floa *s = sumf; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3912,52 +3516,11 @@ void ggml_vec_dot_iq1_m_q8_K(int n, floa *s = sumf; #else - - int sum1[2], sum2[2], delta[4]; - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint16_t * sc = (const uint16_t *)x[i].scales; - - scale.u16 = (sc[0] >> 12) | ((sc[1] >> 8) & 0x00f0) | ((sc[2] >> 4) & 0x0f00) | (sc[3] & 0xf000); - - int sumi1 = 0, sumi2 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - delta[0] = qh[0] & 0x08 ? -1 : 1; - delta[1] = qh[0] & 0x80 ? -1 : 1; - delta[2] = qh[1] & 0x08 ? -1 : 1; - delta[3] = qh[1] & 0x80 ? -1 : 1; - sum1[0] = sum1[1] = sum2[0] = sum2[1] = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((uint16_t)qh[l/2] << (8 - 4*(l%2))) & 0x700))); - int lsum1 = 0, lsum2 = 0; - for (int j = 0; j < 8; ++j) { - lsum1 += q8[j] * grid[j]; - lsum2 += q8[j]; - } - q8 += 8; - sum1[l/2] += lsum1; - sum2[l/2] += lsum2*delta[l]; - } - - const int ls1 = 2*((sc[ib/2] >> (6*(ib%2)+0)) & 0x7) + 1; - const int ls2 = 2*((sc[ib/2] >> (6*(ib%2)+3)) & 0x7) + 1; - - sumi1 += sum1[0] * ls1 + sum1[1] * ls2; - sumi2 += sum2[0] * ls1 + sum2[1] * ls2; - qs += 4; - qh += 2; - } - - sumf += GGML_CPU_FP16_TO_FP32(scale.f16) * y[i].d * (sumi1 + IQ1M_DELTA * sumi2); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(scale); + ggml_vec_dot_iq1_m_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4078,37 +3641,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo *s = sumf; #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/arm/repack.cpp 6641+dfsg-2/ggml/src/ggml-cpu/arch/arm/repack.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/arm/repack.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/arm/repack.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -86,35 +86,9 @@ void ggml_quantize_mat_q8_0_4x4(const fl } } #else - // scalar - const int blck_size_interleave = 4; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x4_generic(x, vy, k); #endif } @@ -205,35 +179,9 @@ void ggml_quantize_mat_q8_0_4x8(const fl } #else - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x8_generic(x, vy, k); #endif } @@ -295,29 +243,7 @@ void ggml_gemv_q4_0_4x4_q8_0(int n, floa } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } + ggml_gemv_q4_0_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -383,29 +309,7 @@ void ggml_gemv_q4_0_4x8_q8_0(int n, floa } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_DOTPROD) - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } + ggml_gemv_q4_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -497,31 +401,7 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, floa #endif // #if defined(__ARM_FEATURE_SVE) #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - { - float sumf[8]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -591,31 +471,7 @@ void ggml_gemv_iq4_nl_4x4_q8_0(int n, fl } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_iq4_nl_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -1096,40 +952,7 @@ void ggml_gemm_q4_0_4x4_q8_0(int n, floa ); return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } - } + ggml_gemm_q4_0_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -1550,38 +1373,7 @@ void ggml_gemm_q4_0_4x8_q8_0(int n, floa ); return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) && defined(__ARM_FEATURE_MATMUL_INT8) - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x4 * b_ptr = (const block_q4_0x4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_4x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -2019,38 +1811,7 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, floa #endif // #if defined(__ARM_FEATURE_SVE) && defined(__ARM_FEATURE_MATMUL_INT8) #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -2126,38 +1887,5 @@ void ggml_gemm_iq4_nl_4x4_q8_0(int n, fl } return; #endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) && defined(__ARM_NEON) - { - float sumf[4][4]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])); - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } - } + ggml_gemm_iq4_nl_4x4_q8_0_generic(n, s, bs, vx, vy, nr, nc); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/loongarch/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/loongarch/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/loongarch/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/loongarch/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -105,6 +105,18 @@ static inline float hsum_float_4x4(const return ((v4f32)res)[0]; } + +// multiply int8_t, add results pairwise twice +static inline __m128i mul_sum_i8_pairs(const __m128i x, const __m128i y) { + // Get absolute values of x vectors + const __m128i ax = __lsx_vsigncov_b(x, x); + // Sign the values of the y vectors + const __m128i sy = __lsx_vsigncov_b(x, y); + // Perform multiplication and create 16-bit values + const __m128i dot = lsx_maddubs_h(ax, sy); + const __m128i ones = __lsx_vreplgr2vr_h(1); + return lsx_madd_h(ones, dot); +} #endif #if defined(__loongarch_asx) @@ -323,18 +335,6 @@ static inline __m256i lasx_xvandi_b_bit( } } -// multiply int8_t, add results pairwise twice -static inline __m128i mul_sum_i8_pairs(const __m128i x, const __m128i y) { - // Get absolute values of x vectors - const __m128i ax = __lsx_vsigncov_b(x, x); - // Sign the values of the y vectors - const __m128i sy = __lsx_vsigncov_b(x, y); - // Perform multiplication and create 16-bit values - const __m128i dot = lsx_maddubs_h(ax, sy); - const __m128i ones = __lsx_vreplgr2vr_h(1); - return lsx_madd_h(ones, dot); -} - // horizontally add 8 floats static inline float hsum_float_8(const __m256 x) { __m128 res = lasx_extractf128(x, 1); @@ -544,7 +544,7 @@ void quantize_row_q8_1(const float * GGM __m128 max4 = __lsx_vfmax_s( lasx_extractf128( max_abs, 1 ), lasx_extractf128( max_abs, 0) ); max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vpickod_d((__m128i) max4, (__m128i)max4 ) ); __m128 tmp = max4; - max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vextrins_w((__m128i)tmp, (__m128i)max4, 0x10 )); + max4 = __lsx_vfmax_s( max4, (__m128)__lsx_vextrins_w((__m128i)tmp, (__m128i)max4, 0x1 )); const float max_scalar = ((v4f32)max4)[0]; // Quantize these floats @@ -821,24 +821,15 @@ void ggml_vec_dot_q4_1_q8_1(int n, float sumf = hsum_float_8(acc) + summs; -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -883,30 +874,15 @@ void ggml_vec_dot_q5_0_q8_0(int n, float sumf = hsum_float_8(acc); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -954,30 +930,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float sumf = hsum_float_8(acc) + summs; -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1016,18 +977,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float sumf = hsum_float_8(acc); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1103,45 +1061,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float *s = hsum_float_8(acc); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1239,70 +1162,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = hsum_float_8(acc); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1391,61 +1257,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = hsum_float_8(acc) + ((v4f32)acc_m)[0]; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1541,66 +1360,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = hsum_float_8(acc) + ((v4f32)acc_m)[0]; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1678,47 +1445,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float *s = hsum_float_8(acc); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1815,34 +1545,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, fl *s = 0.125f * hsum_float_8(accumf); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1978,42 +1684,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, flo *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2105,47 +1779,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, floa *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2209,36 +1847,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, fl *s = 0.25f * hsum_float_8(accumf); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2338,48 +1950,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, floa *s = hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2460,36 +2034,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, floa *s = hsum_float_8(accum) + IQ1S_DELTA * accum1; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2603,37 +2151,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo *s = hsum_float_8(accum); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/powerpc/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/powerpc/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/powerpc/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/powerpc/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -201,24 +201,14 @@ void ggml_vec_dot_q4_0_q8_0(int n, float sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -278,24 +268,80 @@ void ggml_vec_dot_q4_1_q8_1(int n, float sumf = vec_extract(vsumf0, 0); + *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); #endif +} + +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + +#if defined(__POWER9_VECTOR__) + const vector signed char lowMask = vec_splats((signed char)0xF); + const vector unsigned char vshift4 = vec_splats((unsigned char)4); + vector float vsumf0 = vec_splats(0.0f); + + vector signed char kv = vec_xl(0, (const signed char *)kvalues_mxfp4); + +#pragma GCC unroll 8 for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; + __builtin_prefetch(x[ib].qs, 0, 1); + __builtin_prefetch(y[ib].qs, 0, 1); - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); + vector float vyd = vec_splats(GGML_CPU_FP16_TO_FP32(y[ib].d) * + GGML_E8M0_TO_FP32_HALF(x[ib].e)); - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } + vector signed char q8y0 = vec_xl( 0, y[ib].qs); + vector signed char q8y1 = vec_xl(16, y[ib].qs); + + vector signed char qxs = (vector signed char)vec_xl(0, x[ib].qs); + + vector unsigned char lo_nibbles = (vector unsigned char)vec_and(qxs, lowMask); + vector unsigned char hi_nibbles = (vector unsigned char)vec_sr(qxs, vshift4); + + vector signed char q4x0 = vec_perm(kv, kv, lo_nibbles); + vector signed char q4x1 = vec_perm(kv, kv, hi_nibbles); - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); + vector signed short qv0 = vec_add(vec_mule(q4x0, q8y0), vec_mulo(q4x0, q8y0)); + vector signed short qv1 = vec_add(vec_mule(q4x1, q8y1), vec_mulo(q4x1, q8y1)); + + vector signed int vsumi0 = vec_splats((int32_t)0); + vsumi0 = vec_sum4s(qv0, vsumi0); + vsumi0 = vec_sum4s(qv1, vsumi0); + + vsumf0 = vec_madd(vec_ctf(vsumi0, 0), vyd, vsumf0); } + vsumf0 = vec_add(vsumf0, vec_sld(vsumf0, vsumf0, 4)); + vsumf0 = vec_add(vsumf0, vec_sld(vsumf0, vsumf0, 8)); + sumf = vec_extract(vsumf0, 0); *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_mxfp4_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -360,30 +406,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -451,30 +481,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -535,18 +550,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -695,45 +707,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float *s = vec_extract(vsumf0, 0); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -907,70 +884,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = vec_extract(vsumf0, 0); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1130,61 +1050,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = vec_extract(vsumf0, 0); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1342,66 +1215,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = vec_extract(vsumf0, 0); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1556,47 +1377,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float *s = vec_extract(vsumf0, 0); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1737,34 +1521,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, fl *s = 0.125f * vec_extract(vsumf0, 0); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1869,42 +1629,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, flo *s = 0.125f * vec_extract(vsumf0, 0); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2030,47 +1758,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, floa *s = 0.125f * vec_extract(vsumf0, 0); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2172,36 +1864,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, fl *s = 0.25f * vec_extract(vsumf0, 0); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2327,48 +1993,10 @@ void ggml_vec_dot_iq3_s_q8_K(int n, floa *s = vec_extract(vsumf0, 0); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2481,36 +2109,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, floa *s = vec_extract(vsumf0, 0); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2581,17 +2183,15 @@ void ggml_vec_dot_iq4_nl_q8_0(int n, flo sumf = vec_extract(vsumf0, 0); -#endif - for (; ib < nb; ++ib) { - const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_CPU_FP16_TO_FP32(x[ib].d); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < QK4_NL/2; ++j) { - sumi1 += y[ib].qs[j+ 0] * kvalues_iq4nl[x[ib].qs[j] & 0xf]; - sumi2 += y[ib].qs[j+QK4_NL/2] * kvalues_iq4nl[x[ib].qs[j] >> 4]; - } - sumf += d * (sumi1 + sumi2); - } *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_iq4_nl_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2696,37 +2296,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo *s = vec_extract(vsumf0, 0); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/riscv/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/riscv/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/riscv/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/riscv/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -116,6 +116,7 @@ void quantize_row_q8_1(const float * GGM //===================================== Dot products ================================= void ggml_vec_dot_q4_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_0; const int nb = n / qk; @@ -132,7 +133,6 @@ void ggml_vec_dot_q4_0_q8_0(int n, float int ib = 0; float sumf = 0; -#if defined(__riscv_v) size_t vl = qk / 2; for (; ib < nb; ++ib) { @@ -164,27 +164,14 @@ void ggml_vec_dot_q4_0_q8_0(int n, float sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); } -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - *s = sumf; +#else + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_1; const int nb = n / qk; @@ -201,7 +188,6 @@ void ggml_vec_dot_q4_1_q8_1(int n, float int ib = 0; float sumf = 0; -#if defined(__riscv_v) size_t vl = qk / 2; for (; ib < nb; ++ib) { @@ -229,27 +215,14 @@ void ggml_vec_dot_q4_1_q8_1(int n, float sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); } -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_0; const int nb = n / qk; @@ -267,7 +240,6 @@ void ggml_vec_dot_q5_0_q8_0(int n, float const block_q5_0 * GGML_RESTRICT x = vx; const block_q8_0 * GGML_RESTRICT y = vy; -#if defined(__riscv_v) size_t vl; size_t vlenb = __riscv_vlenb(); @@ -297,33 +269,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; } -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { +#if defined(__riscv_v) const int qk = QK8_1; const int nb = n / qk; @@ -341,7 +294,6 @@ void ggml_vec_dot_q5_1_q8_1(int n, float const block_q5_1 * GGML_RESTRICT x = vx; const block_q8_1 * GGML_RESTRICT y = vy; -#if defined(__riscv_v) size_t vl; size_t vlenb = __riscv_vlenb(); @@ -370,30 +322,10 @@ void ggml_vec_dot_q5_1_q8_1(int n, float sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); } -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -431,18 +363,17 @@ void ggml_vec_dot_q8_0_q8_0(int n, float sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); } -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } + *s = sumf; +#else - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); - *s = sumf; + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -738,44 +669,11 @@ void ggml_vec_dot_q2_K_q8_K(int n, float #else - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); + UNUSED(x); + UNUSED(y); + UNUSED(nb); - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1147,68 +1045,14 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = sumf; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1426,29 +1270,40 @@ void ggml_vec_dot_q4_K_q8_K(int n, float const float d = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - int tmp, tmp2, sumi; + float ftmp, ft2; + const uint8_t * restrict q40; + const uint8_t * restrict q41; + const uint8_t * restrict q42; + const uint8_t * restrict q43; + const int8_t * restrict q80; + const int8_t * restrict q81; + const int8_t * restrict q82; + const int8_t * restrict q83; + int s0, s1, s2, s3; + __asm__ __volatile__( - "vsetivli zero, 12, e8, m1\n\t" - "vle8.v v1, (%[s6b])\n\t" // {aux[0], aux[1], aux[2]} - "vsetivli zero, 4, e32, m1\n\t" + "li %[s1], 8\n\t" + "vsetivli zero, 4, e32, m1, ta, ma\n\t" + "vle32.v v1, (%[s6b])\n\t" + "vslide1down.vx v1, v1, zero\n\t" + "vmv.v.x v16, zero\n\t" "vslidedown.vi v2, v1, 2\n\t" "vmv1r.v v3, v2\n\t" "vslideup.vi v2, v3, 1\n\t" // {aux[2], aux[2]} - "vsetivli zero, 2, e32, m1\n\t" + "vsetivli zero, 2, e32, m1, ta, ma\n\t" "vmv.v.i v4, 4\n\t" "vand.vx v8, v1, %[kmask1]\n\t" "vslide1up.vx v5, v4, zero\n\t" // {0, 4} "vsrl.vi v6, v1, 6\n\t" "vsrl.vv v7, v2, v5\n\t" + "vsse32.v v8, (%[utmp]), %[s1]\n\t" "vand.vx v0, v6, %[kmask3]\n\t" "vand.vx v2, v7, %[kmask2]\n\t" "vsll.vi v6, v0, 4\n\t" - "li %[t2], 8\n\t" - "addi %[t1], %[utmp], 4\n\t" + "addi %[s0], %[utmp], 4\n\t" "vor.vv v1, v6, v2\n\t" - "vsse32.v v8, (%[utmp]), %[t2]\n\t" - "vsse32.v v1, (%[t1]), %[t2]\n\t" - "vsetivli zero, 8, e16, m1\n\t" + "vsse32.v v1, (%[s0]), %[s1]\n\t" + "vsetivli zero, 8, e16, m1, ta, ma\n\t" "vle32.v v2, (%[bsums])\n\t" "vnsrl.wi v0, v2, 0\n\t" "vnsrl.wi v1, v2, 16\n\t" @@ -1456,13 +1311,131 @@ void ggml_vec_dot_q4_K_q8_K(int n, float "vle8.v v3, (%[mins])\n\t" "vzext.vf2 v4, v3\n\t" "vwmul.vv v6, v4, v2\n\t" + "vsetivli zero, 4, e32, m1, ta, ma\n\t" + "vredsum.vs v0, v6, v16\n\t" + "vredsum.vs v0, v7, v0\n\t" + "vfcvt.f.x.v v0, v0\n\t" + "vfmv.f.s %[ftmp], v0\n\t" + "vsetivli zero, 16, e8, m1, ta, ma\n\t" + "vle8.v v0, (%[xs])\n\t" + "fnmsub.s %[sumf], %[dmin], %[ftmp], %[sumf]\n\t" + "addi %[q40], %[xs], 64\n\t" + "addi %[q41], %[xs], 16\n\t" + "addi %[q42], %[xs], 32\n\t" + "addi %[q43], %[xs], 48\n\t" + "addi %[q80], %[ys], 64\n\t" + "vle8.v v1, (%[q41])\n\t" + "vle8.v v2, (%[q42])\n\t" + "addi %[q81], %[ys], 16\n\t" + "addi %[q41], %[q41], 64\n\t" + "addi %[q82], %[ys], 32\n\t" + "vle8.v v3, (%[q43])\n\t" + "vle8.v v8, (%[ys])\n\t" + "addi %[q42], %[q42], 64\n\t" + "addi %[q83], %[ys], 48\n\t" + "addi %[q43], %[q43], 64\n\t" + "vsrl.vi v4, v0, 4\n\t" + "vle8.v v9, (%[q81])\n\t" + "vle8.v v10, (%[q82])\n\t" + "vand.vi v0, v0, 0xF\n\t" + "addi %[q81], %[q81], 64\n\t" + "vsrl.vi v5, v1, 4\n\t" + "addi %[q82], %[q82], 64\n\t" + "vle8.v v11, (%[q83])\n\t" + "vle8.v v12, (%[q80])\n\t" + "vand.vi v1, v1, 0xF\n\t" + "addi %[q83], %[q83], 64\n\t" + "vsrl.vi v6, v2, 4\n\t" + "addi %[q80], %[q80], 64\n\t" + "vle8.v v13, (%[q81])\n\t" + "vle8.v v14, (%[q82])\n\t" + "vand.vi v2, v2, 0xF\n\t" + "addi %[q81], %[q81], 64\n\t" + "vsrl.vi v7, v3, 4\n\t" + "addi %[q82], %[q82], 64\n\t" + "vwmul.vv v16, v0, v8\n\t" + "vle8.v v15, (%[q83])\n\t" + "vle8.v v0, (%[q40])\n\t" + "vand.vi v3, v3, 0xF\n\t" + "addi %[q83], %[q83], 64\n\t" + "vwmul.vv v24, v2, v12\n\t" + "vwmul.vv v20, v4, v10\n\t" + "vwmul.vv v28, v6, v14\n\t" + "vwmacc.vv v16, v1, v9\n\t" + "vle8.v v1, (%[q41])\n\t" + "vle8.v v2, (%[q42])\n\t" + "vwmacc.vv v24, v3, v13\n\t" + "vwmacc.vv v20, v5, v11\n\t" + "vwmacc.vv v28, v7, v15\n\t" + "addi %[q40], %[q80], 64\n\t" + "addi %[q41], %[q81], 64\n\t" + "vle8.v v3, (%[q43])\n\t" + "vle8.v v8, (%[q80])\n\t" + "addi %[q42], %[q82], 64\n\t" + "addi %[q43], %[q83], 64\n\t" + "vsrl.vi v4, v0, 4\n\t" + "vle8.v v9, (%[q81])\n\t" + "vle8.v v10, (%[q82])\n\t" + "vand.vi v0, v0, 0xF\n\t" + "vsrl.vi v5, v1, 4\n\t" + "vsrl.vi v7, v3, 4\n\t" + "vand.vi v3, v3, 0xF\n\t" + "vle8.v v11, (%[q83])\n\t" + "vle8.v v12, (%[q40])\n\t" + "vand.vi v1, v1, 0xF\n\t" + "vsrl.vi v6, v2, 4\n\t" + "vand.vi v2, v2, 0xF\n\t" + "vwmul.vv v18, v0, v8\n\t" + "vle8.v v13, (%[q41])\n\t" + "vle8.v v14, (%[q42])\n\t" + "vwmul.vv v26, v2, v12\n\t" + "vwmul.vv v22, v4, v10\n\t" + "vwmul.vv v30, v6, v14\n\t" + "vwmacc.vv v18, v1, v9\n\t" + "vle8.v v15, (%[q43])\n\t" + "vwmacc.vv v26, v3, v13\n\t" + "vwmacc.vv v22, v5, v11\n\t" + "vwmacc.vv v30, v7, v15\n\t" "vmv.v.x v0, zero\n\t" - "vsetivli zero, 8, e32, m2\n\t" - "vredsum.vs v0, v6, v0\n\t" - "vmv.x.s %[sumi], v0" - : [t1] "=&r" (tmp), [t2] "=&r" (tmp2), [sumi] "=&r" (sumi) - : [bsums] "r" (y[i].bsums), [mins] "r" (mins), [utmp] "r" (utmp) - , [s6b] "r" (x[i].scales), [kmask1] "r" (kmask1) + "vsetivli zero, 16, e16, m2, ta, ma\n\t" + "vwredsum.vs v4, v16, v0\n\t" + "lbu %[s0], 0(%[scale])\n\t" + "vwredsum.vs v5, v20, v0\n\t" + "lbu %[s1], 1(%[scale])\n\t" + "vwredsum.vs v6, v24, v0\n\t" + "lbu %[s2], 2(%[scale])\n\t" + "vwredsum.vs v7, v28, v0\n\t" + "lbu %[s3], 3(%[scale])\n\t" + "vwredsum.vs v8, v18, v0\n\t" + "lbu %[q40], 4(%[scale])\n\t" + "vwredsum.vs v9, v22, v0\n\t" + "lbu %[q41], 5(%[scale])\n\t" + "vwredsum.vs v10, v26, v0\n\t" + "lbu %[q42], 6(%[scale])\n\t" + "vwredsum.vs v11, v30, v0\n\t" + "lbu %[q43], 7(%[scale])\n\t" + "vsetivli zero, 4, e32, m1, ta, ma\n\t" + "vmul.vx v0, v4, %[s0]\n\t" + "vmul.vx v1, v8, %[q40]\n\t" + "vmacc.vx v0, %[s1], v5\n\t" + "vmacc.vx v1, %[q41], v9\n\t" + "vmacc.vx v0, %[s2], v6\n\t" + "vmacc.vx v1, %[q42], v10\n\t" + "vmacc.vx v0, %[s3], v7\n\t" + "vmacc.vx v1, %[q43], v11\n\t" + "vfcvt.f.x.v v0, v0\n\t" + "vfcvt.f.x.v v1, v1\n\t" + "vfmv.f.s %[ft2], v0\n\t" + "vfmv.f.s %[ftmp], v1\n\t" + "fadd.s %[ft2], %[ft2], %[ftmp]\n\t" + "fmadd.s %[sumf], %[d], %[ft2], %[sumf]" + : [ftmp] "=&f" (ftmp), [sumf] "+&f" (sumf), [ft2] "=&f" (ft2) + , [s0] "=&r" (s0), [s1] "=&r" (s1), [s2] "=&r" (s2), [s3] "=&r" (s3) + , [q40] "=&r" (q40), [q41] "=&r" (q41), [q42] "=&r" (q42), [q43] "=&r" (q43) + , [q80] "=&r" (q80), [q81] "=&r" (q81), [q82] "=&r" (q82), [q83] "=&r" (q83) + : [d] "f" (d), [ys] "r" (y[i].qs), [xs] "r" (x[i].qs), [scale] "r" (scales) + , [bsums] "r" (y[i].bsums), [mins] "r" (mins), [utmp] "r" (utmp) + , [s6b] "r" (&x[i]), [kmask1] "r" (kmask1), [dmin] "f" (dmin) , [kmask2] "r" (kmask2), [kmask3] "r" (kmask3) : "memory" , "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7" @@ -1470,59 +1443,6 @@ void ggml_vec_dot_q4_K_q8_K(int n, float , "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23" , "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" ); - sumf -= dmin * sumi; - - const uint8_t * restrict q4 = x[i].qs; - const int8_t * restrict q8 = y[i].qs; - - sumi = 0; - const uint8_t * scale = scales; - - for (int j = 0; j < QK_K/128; ++j) { - int vl128 = 128, vl64 = 64, vl32 = 32; - __asm__ __volatile__( - "vsetvli zero, %[vl128], e8, m8\n\t" - "vle8.v v8, (%[q8])\n\t" - "vsetvli zero, %[vl64], e8, m4\n\t" - "vle8.v v0, (%[q4])\n\t" - "vsrl.vi v4, v0, 4\n\t" - "vand.vi v0, v0, 0xF\n\t" - "vsetvli zero, %[vl32], e8, m2\n\t" - "vwmul.vv v28, v6, v14\n\t" - "vwmul.vv v20, v4, v10\n\t" - "vwmul.vv v24, v2, v12\n\t" - "vwmul.vv v16, v0, v8\n\t" - "vsetivli zero, 4, e32, m1\n\t" - "vle8.v v2, (%[scale])\n\t" - "vmv.v.x v0, zero\n\t" - "vzext.vf4 v1, v2\n\t" - "vsetvli zero, %[vl32], e16, m4\n\t" - "vwredsum.vs v6, v24, v0\n\t" - "vwredsum.vs v7, v28, v0\n\t" - "vwredsum.vs v4, v16, v0\n\t" - "vwredsum.vs v5, v20, v0\n\t" - "vsetivli zero, 4, e32, m1\n\t" - "vslideup.vi v6, v7, 1\n\t" - "vslideup.vi v4, v5, 1\n\t" - "vslideup.vi v4, v6, 2\n\t" - "vmul.vv v8, v4, v1\n\t" - "vredsum.vs v0, v8, v0\n\t" - "vmv.x.s %[tmp], v0\n\t" - "add %[sumi], %[sumi], %[tmp]" - : [tmp] "=&r" (tmp), [sumi] "+&r" (sumi) - : [vl128] "r" (vl128), [vl64] "r" (vl64), [vl32] "r" (vl32) - , [q4] "r" (q4), [q8] "r" (q8), [scale] "r" (scale) - : "memory" - , "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7" - , "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15" - , "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23" - , "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" - ); - - q4 += 64; q8 += 128; scale += 4; - } - - sumf += d * sumi; } break; default: @@ -1534,60 +1454,15 @@ void ggml_vec_dot_q4_K_q8_K(int n, float #else - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); + UNUSED(x); + UNUSED(y); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(nb); + UNUSED(utmp); - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1698,65 +1573,15 @@ void ggml_vec_dot_q5_K_q8_K(int n, float #else - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; + UNUSED(x); + UNUSED(y); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(nb); + UNUSED(utmp); - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1944,6 +1769,8 @@ void ggml_vec_dot_q6_K_q8_K(int n, float case 128: for (int i = 0; i < nb; ++i) { + __builtin_prefetch(&x[i + 1].d, 0, 1); + const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; const uint8_t * restrict q6 = x[i].ql; @@ -1952,23 +1779,59 @@ void ggml_vec_dot_q6_K_q8_K(int n, float const int8_t * restrict scale = x[i].scales; - int sum_t = 0; - int t0; + int q6h; + float ftmp; for (int j = 0; j < QK_K/128; ++j) { __asm__ __volatile__( + "addi %[q6h], %[q6], 32\n\t" + "ld t0, 0(%[scale])\n\t" + "addi %[scale], %[scale], 8\n\t" + "slli t6, t0, 1 * 8\n\t" + "lb zero, 0(%[q6])\n\t" + "slli t5, t0, 2 * 8\n\t" + "slli t4, t0, 3 * 8\n\t" + "lb zero, 0(%[q6h])\n\t" + "slli t3, t0, 4 * 8\n\t" + "slli t2, t0, 5 * 8\n\t" + "lb zero, 0(%[qh])\n\t" + "lb zero, 31(%[q6h])\n\t" + "slli t1, t0, 6 * 8\n\t" + "srai a7, t0, 56\n\t" "vsetvli zero, %[vl32], e8, m2\n\t" + "vle8.v v8, (%[q6])\n\t" + "srai t6, t6, 56\n\t" + "srai t5, t5, 56\n\t" + "srai t4, t4, 56\n\t" + "srai t3, t3, 56\n\t" + "vle8.v v10, (%[q6h])\n\t" + "addi %[q6], %[q6], 64\n\t" + "slli t0, t0, 7 * 8\n\t" + "srai t2, t2, 56\n\t" + "srai t1, t1, 56\n\t" + "srai t0, t0, 56\n\t" "vle8.v v4, (%[qh])\n\t" + "vsrl.vi v12, v8, 4\n\t" + "vsrl.vi v14, v10, 4\n\t" + "lb zero, 0(%[q8])\n\t" + "vand.vi v8, v8, 0xF\n\t" + "vand.vi v10, v10, 0xF\n\t" + "lb zero, 32(%[q8])\n\t" "vsll.vi v0, v4, 4\n\t" "vsll.vi v2, v4, 2\n\t" + "lb zero, 64(%[q8])\n\t" "vsrl.vi v6, v4, 2\n\t" - "vsetvli zero, %[vl64], e8, m4\n\t" - "vle8.v v8, (%[q6])\n\t" - "vsrl.vi v12, v8, 4\n\t" - "vand.vi v8, v8, 0xF\n\t" - "vsetvli zero, %[vl128], e8, m8\n\t" "vand.vx v0, v0, %[mask]\n\t" + "lb zero, 96(%[q8])\n\t" + "vand.vx v2, v2, %[mask]\n\t" + "vand.vx v4, v4, %[mask]\n\t" + "vand.vx v6, v6, %[mask]\n\t" "vor.vv v8, v8, v0\n\t" + "lb zero, 127(%[q8])\n\t" + "vor.vv v10, v10, v2\n\t" + "vor.vv v12, v12, v4\n\t" + "vor.vv v14, v14, v6\n\t" + "vsetvli zero, %[vl128], e8, m8\n\t" "vle8.v v0, (%[q8])\n\t" "vsub.vx v8, v8, %[vl32]\n\t" "vsetvli zero, %[vl64], e8, m4\n\t" @@ -1985,34 +1848,34 @@ void ggml_vec_dot_q6_K_q8_K(int n, float "vwredsum.vs v13, v28, v0\n\t" "vwredsum.vs v14, v30, v0\n\t" "vsetivli zero, 4, e32, m1\n\t" - "vslideup.vi v10, v9, 1\n\t" - "vslideup.vi v8, v7, 1\n\t" - "vslideup.vi v11, v12, 1\n\t" - "vslideup.vi v13, v14, 1\n\t" - "vslideup.vi v10, v8, 2\n\t" - "vslideup.vi v11, v13, 2\n\t" - "vsetivli zero, 8, e32, m2\n\t" - "vle8.v v2, (%[scale])\n\t" - "vsext.vf4 v4, v2\n\t" - "vmul.vv v2, v4, v10\n\t" - "vredsum.vs v0, v2, v0\n\t" - "vmv.x.s %[t0], v0\n\t" - "add %[sumi], %[sumi], %[t0]" - : [sumi] "+&r" (sum_t), [t0] "=&r" (t0) - : [qh] "r" (qh), [q6] "r" (q6), [q8] "r" (q8), [scale] "r" (scale) + "vmul.vx v0, v10, t0\n\t" + "vmul.vx v1, v9, t1\n\t" + "vmacc.vx v0, t2, v8\n\t" + "vmacc.vx v1, t3, v7\n\t" + "vmacc.vx v0, t4, v11\n\t" + "vmacc.vx v1, t5, v12\n\t" + "vmacc.vx v0, t6, v13\n\t" + "vmacc.vx v1, a7, v14\n\t" + "vadd.vv v0, v0, v1\n\t" + "vfcvt.f.x.v v0, v0\n\t" + "vfmv.f.s %[ftmp], v0\n\t" + "fmadd.s %[sumf], %[d], %[ftmp], %[sumf]" + : [q6] "+&r" (q6), [q6h] "=&r" (q6h) + , [scale] "+&r" (scale) + , [sumf] "+&f" (sumf), [ftmp] "=&f" (ftmp) + : [qh] "r" (qh), [q8] "r" (q8) , [vl32] "r" (32), [vl64] "r" (64), [vl128] "r" (128) - , [mask] "r" (0x30) + , [mask] "r" (0x30), [d] "f" (d) : "memory" , "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7" , "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15" , "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23" , "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" + , "t0", "t1", "t2", "t3", "t4", "t5", "t6", "a7" + , "a6", "a5", "a4", "a3" ); - q6 += 64; qh += 32; q8 += 128; scale += 8; + qh += 32; q8 += 128; } - - sumf += d * sum_t; - } break; default: @@ -2024,46 +1887,11 @@ void ggml_vec_dot_q6_K_q8_K(int n, float #else - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); + UNUSED(x); + UNUSED(y); + UNUSED(nb); - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/riscv/repack.cpp 6641+dfsg-2/ggml/src/ggml-cpu/arch/riscv/repack.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/riscv/repack.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/riscv/repack.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -112,31 +112,7 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, floa } #endif - { - float sumf[8]; - int sumi; - - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } - } - } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; - } - } + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -361,37 +337,6 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, floa return; } -#endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } +#endif + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/s390/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/s390/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/s390/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/s390/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -23,6 +23,27 @@ #define UNUSED GGML_UNUSED +#if defined(__VXE__) || defined(__VXE2__) +#define B1(c,s,n) 0x ## n ## c , 0x ## n ## s +#define B2(c,s,n) B1(c,s,n ## c), B1(c,s,n ## s) +#define B3(c,s,n) B2(c,s,n ## c), B2(c,s,n ## s) +#define B4(c,s,n) B3(c,s,n ## c), B3(c,s,n ## s) +#define B5(c,s,n) B4(c,s,n ## c), B4(c,s,n ## s) +#define B6(c,s,n) B5(c,s,n ## c), B5(c,s,n ## s) +#define B7(c,s,n) B6(c,s,n ## c), B6(c,s,n ## s) +#define B8(c,s ) B7(c,s, c), B7(c,s, s) + +// precomputed tables for expanding 8bits to 8 bytes: +static const __attribute__((aligned(16))) uint64_t table_b2b_0[1 << 8] = { B8(00, 10) }; // ( b ) << 4 +static const __attribute__((aligned(16))) uint64_t table_b2b_1[1 << 8] = { B8(10, 00) }; // (!b) << 4 + +// permute mask for byteswapping +static const uint8x16_t v_kperm = (const uint8x16_t){ + 7, 6, 5, 4, 3, 2, 1, 0, + 15, 14, 13, 12, 11, 10, 9, 8 +}; +#endif + void quantize_row_q8_0(const float * GGML_RESTRICT x, void * GGML_RESTRICT vy, int64_t k) { assert(QK8_0 == 32); assert(k % QK8_0 == 0); @@ -32,9 +53,9 @@ void quantize_row_q8_0(const float * GGM #if defined(__VXE__) || defined(__VXE2__) for (int i = 0; i < nb; i++) { - __vector float srcv [8]; - __vector float asrcv[8]; - __vector float amaxv[8]; + float32x4_t srcv [8]; + float32x4_t asrcv[8]; + float32x4_t amaxv[8]; for (int j = 0; j < 8; j++) srcv[j] = vec_xl(0, x + i*32 + 4*j); for (int j = 0; j < 8; j++) asrcv[j] = vec_abs(srcv[j]); @@ -53,8 +74,9 @@ void quantize_row_q8_0(const float * GGM y[i].d = GGML_CPU_FP32_TO_FP16(d); for (int j = 0; j < 8; j++) { - const __vector float v = vec_mul(srcv[j], vec_splats(id)); - const __vector int32_t vi = vec_signed(v); + const float32x4_t v = vec_mul(srcv[j], vec_splats(id)); + /* Uses non-default rounding for vec_signed or vec_round */ + const int32x4_t vi = vec_signed(__builtin_s390_vfisb(v, 4, 1)); y[i].qs[4*j + 0] = vec_extract(vi, 0); y[i].qs[4*j + 1] = vec_extract(vi, 1); @@ -77,9 +99,9 @@ void quantize_row_q8_1(const float * GGM #if defined(__VXE__) || defined(__VXE2__) for (int i = 0; i < nb; i++) { - __vector float srcv [8]; - __vector float asrcv[8]; - __vector float amaxv[8]; + float32x4_t srcv [8]; + float32x4_t asrcv[8]; + float32x4_t amaxv[8]; for (int j = 0; j < 8; j++) srcv[j] = vec_xl(0, x + i*32 + 4*j); for (int j = 0; j < 8; j++) asrcv[j] = vec_abs(srcv[j]); @@ -97,11 +119,12 @@ void quantize_row_q8_1(const float * GGM y[i].d = GGML_CPU_FP32_TO_FP16(d); - __vector int32_t acc = vec_splats(0); + int32x4_t acc = vec_splats(0); for (int j = 0; j < 8; j++) { - const __vector float v = vec_mul(srcv[j], vec_splats(id)); - const __vector int32_t vi = vec_signed(v); + const float32x4_t v = vec_mul(srcv[j], vec_splats(id)); + /* Uses non-default rounding for vec_signed or vec_round */ + const int32x4_t vi = vec_signed(__builtin_s390_vfisb(v, 4, 1)); y[i].qs[4*j + 0] = vec_extract(vi, 0); y[i].qs[4*j + 1] = vec_extract(vi, 1); @@ -141,55 +164,45 @@ void ggml_vec_dot_q4_0_q8_0(int n, float float sumf = 0; #if defined(__VXE__) || defined(__VXE2__) - __vector float acc = vec_splats(0.0f); + float32x4_t acc = vec_splats(0.0f); - const __vector uint8_t v_m = vec_splats((const uint8_t)0x0F); - const __vector int8_t v_s = vec_splats( (const int8_t)0x08); + const uint8x16_t v_m = vec_splats((const uint8_t)0x0F); + const int8x16_t v_s = vec_splats( (const int8_t)0x08); for (; ib < nb; ++ib) { - const __vector uint8_t v_x = vec_xl(0, x[ib].qs); - const __vector int8_t v_xl = (const __vector int8_t)(v_x & v_m); - const __vector int8_t v_xh = (const __vector int8_t)(v_x >> 4); + const uint8x16_t v_x = vec_xl(0, x[ib].qs); + const int8x16_t v_xl = (const int8x16_t)(v_x & v_m); + const int8x16_t v_xh = (const int8x16_t)(v_x >> 4); - const __vector int8_t v_xls = vec_sub(v_xl, v_s); - const __vector int8_t v_xhs = vec_sub(v_xh, v_s); + const int8x16_t v_xls = vec_sub(v_xl, v_s); + const int8x16_t v_xhs = vec_sub(v_xh, v_s); - const __vector int8_t v_yl = vec_xl(0 , y[ib].qs); - const __vector int8_t v_yh = vec_xl(QK8_0/2, y[ib].qs); + const int8x16_t v_yl = vec_xl(0 , y[ib].qs); + const int8x16_t v_yh = vec_xl(QK8_0/2, y[ib].qs); - const __vector int16_t v_xylso = vec_mulo(v_xls, v_yl); - const __vector int16_t v_xylse = vec_mule(v_xls, v_yl); - const __vector int16_t v_xyhso = vec_mulo(v_xhs, v_yh); - const __vector int16_t v_xyhse = vec_mule(v_xhs, v_yh); + const int16x8_t v_xylso = vec_mulo(v_xls, v_yl); + const int16x8_t v_xylse = vec_mule(v_xls, v_yl); + const int16x8_t v_xyhso = vec_mulo(v_xhs, v_yh); + const int16x8_t v_xyhse = vec_mule(v_xhs, v_yh); - __vector int16_t v_xy_ = v_xylso + v_xylse + v_xyhso + v_xyhse; v_xy_ += vec_reve(v_xy_); + int16x8_t v_xy_ = v_xylso + v_xylse + v_xyhso + v_xyhse; v_xy_ += vec_reve(v_xy_); - const __vector float v_xy = vec_float(vec_unpackh(v_xy_)); - const __vector float v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)); + const float32x4_t v_xy = vec_float(vec_unpackh(v_xy_)); + const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x[ib].d) * GGML_CPU_FP16_TO_FP32(y[ib].d)); acc = vec_madd(v_xy, v_d, acc); } - sumf = acc[0] + acc[1] + acc[2] + acc[3]; - -#endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F) - 8; - const int v1 = (x[ib].qs[j] >> 4) - 8; - - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += sumi*GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d); - } - + sumf = vec_hsum_f32x4(acc); *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q4_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -237,26 +250,406 @@ void ggml_vec_dot_q4_1_q8_1(int n, float acc = vec_madd(v_xy, v_d, acc); } - sumf = acc[0] + acc[1] + acc[2] + acc[3] + summs; + sumf = vec_hsum_f32x4(acc) + summs; + *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif +} + +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const int qk = QK_MXFP4; + const int nb = n / qk; + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + int ib = 0; + float sumf = 0.0f; + +#if defined(__VXE__) || defined(__VXE2__) + const int8x16_t v_k = vec_xl(0, kvalues_mxfp4); + const uint8x16_t v_m = vec_splats((const uint8_t)0x0F); + + float32x4_t v_acc = vec_splats(0.0f); + + #pragma GCC unroll 8 + for (; ib + 1 < nb; ib += 2) { + const block_mxfp4 * GGML_RESTRICT x0 = &x[ib + 0]; + const block_mxfp4 * GGML_RESTRICT x1 = &x[ib + 1]; + const block_q8_0 * GGML_RESTRICT y0 = &y[ib + 0]; + const block_q8_0 * GGML_RESTRICT y1 = &y[ib + 1]; + + const uint8x16_t v_x0 = vec_xl(0, x0->qs); + const uint8x16_t v_x1 = vec_xl(0, x1->qs); + + int8x16_t v_x0l = (int8x16_t)vec_and(v_x0, v_m); + int8x16_t v_x0h = (int8x16_t)vec_sr(v_x0, 4); + int8x16_t v_x1l = (int8x16_t)vec_and(v_x1, v_m); + int8x16_t v_x1h = (int8x16_t)vec_sr(v_x1, 4); + + v_x0l = vec_perm(v_k, v_k, (uchar8x16_t)v_x0l); + v_x0h = vec_perm(v_k, v_k, (uchar8x16_t)v_x0h); + v_x1l = vec_perm(v_k, v_k, (uchar8x16_t)v_x1l); + v_x1h = vec_perm(v_k, v_k, (uchar8x16_t)v_x1h); + + const int8x16_t v_y0l = vec_xl(0, y0->qs); + const int8x16_t v_y0h = vec_xl(QK8_0/2, y0->qs); + const int8x16_t v_y1l = vec_xl(0, y1->qs); + const int8x16_t v_y1h = vec_xl(QK8_0/2, y1->qs); + + const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0l, v_y0l), v_x0h, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1l, v_y1l), v_x1h, v_y1h); + + const float32x4_t v_xy0f = vec_float(v_xy0); + const float32x4_t v_xy1f = vec_float(v_xy1); + + const float32x4_t v_d0 = vec_splats(GGML_E8M0_TO_FP32_HALF(x0->e) * GGML_CPU_FP16_TO_FP32(y0->d)); + const float32x4_t v_d1 = vec_splats(GGML_E8M0_TO_FP32_HALF(x1->e) * GGML_CPU_FP16_TO_FP32(y1->d)); + + v_acc = vec_madd(v_xy0f, v_d0, v_acc); + v_acc = vec_madd(v_xy1f, v_d1, v_acc); + } + + for (; ib < nb; ++ib) { + const block_mxfp4 * GGML_RESTRICT x0 = &x[ib + 0]; + const block_q8_0 * GGML_RESTRICT y0 = &y[ib + 0]; + + const uint8x16_t v_x = vec_xl(0, x0->qs); + + int8x16_t v_xl = (int8x16_t)vec_and(v_x, v_m); + int8x16_t v_xh = (int8x16_t)vec_sr(v_x, 4); + + v_xl = vec_perm(v_k, v_k, (uchar8x16_t)v_xl); + v_xh = vec_perm(v_k, v_k, (uchar8x16_t)v_xh); + + const int8x16_t v_yl = vec_xl(0, y0->qs); + const int8x16_t v_yh = vec_xl(QK8_0/2, y0->qs); + + const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); + const float32x4_t v_xyf = vec_float(v_xy); + + const float32x4_t v_d = vec_splats(GGML_E8M0_TO_FP32_HALF(x0->e) * GGML_CPU_FP16_TO_FP32(y0->d)); + v_acc = vec_madd(v_xyf, v_d, v_acc); + } + sumf = vec_hsum_f32x4(v_acc); + *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_mxfp4_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); #endif +} + +void ggml_vec_dot_q5_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + const int qk = QK8_0; + const int nb = n / qk; + + assert(n % qk == 0); + assert(qk == QK5_0); + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + + const block_q5_0 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + int ib = 0; + float sumf = 0.0f; + +#if defined(__VXE__) || defined(__VXE2__) + float32x4_t v_sum0 = vec_splats(0.0f); + float32x4_t v_sum1 = vec_splats(0.0f); + + uint32_t qh0, qh1; + uint64_t tmp0[4], tmp1[4]; + + const uint8x16_t v_m = vec_splats((uint8_t)0x0F); + + #pragma GCC unroll 4 + for (; ib + 1 < nb; ib += 2) { + const block_q5_0 * GGML_RESTRICT x0 = &x[ib + 0]; + const block_q5_0 * GGML_RESTRICT x1 = &x[ib + 1]; + const block_q8_0 * GGML_RESTRICT y0 = &y[ib + 0]; + const block_q8_0 * GGML_RESTRICT y1 = &y[ib + 1]; + + memcpy(&qh0, x0->qh, sizeof(qh0)); + memcpy(&qh1, x1->qh, sizeof(qh1)); + + tmp0[0] = table_b2b_1[(qh0 >> 0) & 0xFF]; + tmp0[1] = table_b2b_1[(qh0 >> 8) & 0xFF]; + tmp0[2] = table_b2b_1[(qh0 >> 16) & 0xFF]; + tmp0[3] = table_b2b_1[(qh0 >> 24) ]; + + tmp1[0] = table_b2b_1[(qh1 >> 0) & 0xFF]; + tmp1[1] = table_b2b_1[(qh1 >> 8) & 0xFF]; + tmp1[2] = table_b2b_1[(qh1 >> 16) & 0xFF]; + tmp1[3] = table_b2b_1[(qh1 >> 24) ]; + + int8x16_t v_qh0l = vec_xl(0, (const int8_t *)(tmp0 + 0)); + int8x16_t v_qh0h = vec_xl(0, (const int8_t *)(tmp0 + 2)); + int8x16_t v_qh1l = vec_xl(0, (const int8_t *)(tmp1 + 0)); + int8x16_t v_qh1h = vec_xl(0, (const int8_t *)(tmp1 + 2)); + + // required for fixing the byteorder + v_qh0l = vec_perm(v_qh0l, v_qh0l, v_kperm); + v_qh0h = vec_perm(v_qh0h, v_qh0h, v_kperm); + v_qh1l = vec_perm(v_qh1l, v_qh1l, v_kperm); + v_qh1h = vec_perm(v_qh1h, v_qh1h, v_kperm); + + const uint8x16_t v_x0 = vec_xl(0, (const uint8_t *)x0->qs); + const uint8x16_t v_x1 = vec_xl(0, (const uint8_t *)x1->qs); + + int8x16_t v_x0l = (int8x16_t)vec_and(v_x0, v_m); + int8x16_t v_x0h = (int8x16_t)vec_sr(v_x0, 4); + int8x16_t v_x1l = (int8x16_t)vec_and(v_x1, v_m); + int8x16_t v_x1h = (int8x16_t)vec_sr(v_x1, 4); + + const int8x16_t v_x0lf = vec_sub(v_x0l, v_qh0l); + const int8x16_t v_x0hf = vec_sub(v_x0h, v_qh0h); + const int8x16_t v_x1lf = vec_sub(v_x1l, v_qh1l); + const int8x16_t v_x1hf = vec_sub(v_x1h, v_qh1h); + + const int8x16_t v_y0l = vec_xl(0, (const int8_t *)y0->qs); + const int8x16_t v_y0h = vec_xl(QK8_0/2, (const int8_t *)y0->qs); + const int8x16_t v_y1l = vec_xl(0, (const int8_t *)y1->qs); + const int8x16_t v_y1h = vec_xl(QK8_0/2, (const int8_t *)y1->qs); + + const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); + + const float32x4_t v_xy0f = vec_float(v_xy0); + const float32x4_t v_xy1f = vec_float(v_xy1); + + const float32x4_t v_d0 = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); + const float32x4_t v_d1 = vec_splats(GGML_CPU_FP16_TO_FP32(x1->d) * GGML_CPU_FP16_TO_FP32(y1->d)); + + v_sum0 = vec_madd(v_xy0f, v_d0, v_sum0); + v_sum1 = vec_madd(v_xy1f, v_d1, v_sum1); + } + + sumf += vec_hsum_f32x4(v_sum0) + vec_hsum_f32x4(v_sum1); + + #pragma GCC unroll 4 for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; + const block_q5_0 * GGML_RESTRICT x0 = &x[ib]; + const block_q8_0 * GGML_RESTRICT y0 = &y[ib]; - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); + uint32_t qh; + memcpy(&qh, x0->qh, sizeof(qh)); - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } + uint64_t tmp[4]; + tmp[0] = table_b2b_1[(qh >> 0) & 0xFF]; + tmp[1] = table_b2b_1[(qh >> 8) & 0xFF]; + tmp[2] = table_b2b_1[(qh >> 16) & 0xFF]; + tmp[3] = table_b2b_1[(qh >> 24) ]; + + int8x16_t v_qhl = vec_xl(0, (const int8_t *)(tmp + 0)); + int8x16_t v_qhh = vec_xl(0, (const int8_t *)(tmp + 2)); + + // required for fixing the byteorder + v_qhl = vec_perm(v_qhl, v_qhl, v_kperm); + v_qhh = vec_perm(v_qhh, v_qhh, v_kperm); + + const uint8x16_t v_x = vec_xl(0, (const uint8_t *)x0->qs); + int8x16_t v_xl = (int8x16_t)vec_and(v_x, v_m); + int8x16_t v_xh = (int8x16_t)vec_sr(v_x, 4); + + const int8x16_t v_xlf = vec_sub(v_xl, v_qhl); + const int8x16_t v_xhf = vec_sub(v_xh, v_qhh); - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); + const int8x16_t v_yl = vec_xl(0, (const int8_t *)y0->qs); + const int8x16_t v_yh = vec_xl(QK8_0/2, (const int8_t *)y0->qs); + + const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); + const float32x4_t v_xyf = vec_float(v_xy); + + const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); + const float32x4_t v_acc = vec_madd(v_xyf, v_d, vec_splats(0.0f)); + + sumf += vec_hsum_f32x4(v_acc); } *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif +} + +void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + const int qk = QK8_1; + const int nb = n / qk; + + assert(n % qk == 0); + assert(qk == QK5_1); + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + + const block_q5_1 * GGML_RESTRICT x = vx; + const block_q8_1 * GGML_RESTRICT y = vy; + + int ib = 0; + float sumf = 0.0f; + +#if defined(__VXE__) || defined(__VXE2__) + float32x4_t v_sum0 = vec_splats(0.0f); + float32x4_t v_sum1 = vec_splats(0.0f); + + float summs0 = 0.0f; + float summs1 = 0.0f; + + uint32_t qh0; + uint32_t qh1; + + uint64_t tmp0[4]; + uint64_t tmp1[4]; + + const uint8x16_t v_m = vec_splats((uint8_t)0x0F); + + #pragma GCC unroll 4 + for (; ib + 1 < nb; ib += 2) { + const block_q5_1 * GGML_RESTRICT x0 = &x[ib + 0]; + const block_q5_1 * GGML_RESTRICT x1 = &x[ib + 1]; + const block_q8_1 * GGML_RESTRICT y0 = &y[ib + 0]; + const block_q8_1 * GGML_RESTRICT y1 = &y[ib + 1]; + + summs0 += GGML_CPU_FP16_TO_FP32(x0->m) * GGML_CPU_FP16_TO_FP32(y0->s); + summs1 += GGML_CPU_FP16_TO_FP32(x1->m) * GGML_CPU_FP16_TO_FP32(y1->s); + + memcpy(&qh0, x0->qh, sizeof(qh0)); + memcpy(&qh1, x1->qh, sizeof(qh1)); + + tmp0[0] = table_b2b_0[(qh0 >> 0) & 0xFF]; + tmp0[1] = table_b2b_0[(qh0 >> 8) & 0xFF]; + tmp0[2] = table_b2b_0[(qh0 >> 16) & 0xFF]; + tmp0[3] = table_b2b_0[(qh0 >> 24) ]; + + tmp1[0] = table_b2b_0[(qh1 >> 0) & 0xFF]; + tmp1[1] = table_b2b_0[(qh1 >> 8) & 0xFF]; + tmp1[2] = table_b2b_0[(qh1 >> 16) & 0xFF]; + tmp1[3] = table_b2b_0[(qh1 >> 24) ]; + + int8x16_t v_qh0l = vec_xl(0, (const int8_t *)(tmp0 + 0)); + int8x16_t v_qh0h = vec_xl(0, (const int8_t *)(tmp0 + 2)); + int8x16_t v_qh1l = vec_xl(0, (const int8_t *)(tmp1 + 0)); + int8x16_t v_qh1h = vec_xl(0, (const int8_t *)(tmp1 + 2)); + + // required for fixing the byteorder + v_qh0l = vec_perm(v_qh0l, v_qh0l, v_kperm); + v_qh0h = vec_perm(v_qh0h, v_qh0h, v_kperm); + v_qh1l = vec_perm(v_qh1l, v_qh1l, v_kperm); + v_qh1h = vec_perm(v_qh1h, v_qh1h, v_kperm); + + const uint8x16_t v_x0 = vec_xl(0, x0->qs); + const uint8x16_t v_x1 = vec_xl(0, x1->qs); + + const int8x16_t v_x0l = (int8x16_t)vec_and(v_x0, v_m); + const int8x16_t v_x0h = (int8x16_t)vec_sr(v_x0, 4); + const int8x16_t v_x1l = (int8x16_t)vec_and(v_x1, v_m); + const int8x16_t v_x1h = (int8x16_t)vec_sr(v_x1, 4); + + const int8x16_t v_x0lf = vec_or(v_x0l, v_qh0l); + const int8x16_t v_x0hf = vec_or(v_x0h, v_qh0h); + const int8x16_t v_x1lf = vec_or(v_x1l, v_qh1l); + const int8x16_t v_x1hf = vec_or(v_x1h, v_qh1h); + + const int8x16_t v_y0l = vec_xl(0 , y0->qs); + const int8x16_t v_y0h = vec_xl(QK8_1/2, y0->qs); + const int8x16_t v_y1l = vec_xl(0 , y1->qs); + const int8x16_t v_y1h = vec_xl(QK8_1/2, y1->qs); + + const int32x4_t v_xy0 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x0lf, v_y0l), v_x0hf, v_y0h); + const int32x4_t v_xy1 = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_x1lf, v_y1l), v_x1hf, v_y1h); + + const float32x4_t v_xy0f = vec_float(v_xy0); + const float32x4_t v_xy1f = vec_float(v_xy1); + + const float32x4_t v_d0 = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); + const float32x4_t v_d1 = vec_splats(GGML_CPU_FP16_TO_FP32(x1->d) * GGML_CPU_FP16_TO_FP32(y1->d)); + + v_sum0 = vec_madd(v_xy0f, v_d0, v_sum0); + v_sum1 = vec_madd(v_xy1f, v_d1, v_sum1); + } + + sumf += vec_hsum_f32x4(v_sum0) + vec_hsum_f32x4(v_sum1) + summs0 + summs1; + + #pragma GCC unroll 4 + for (; ib < nb; ++ib) { + const block_q5_1 * GGML_RESTRICT x0 = &x[ib]; + const block_q8_1 * GGML_RESTRICT y0 = &y[ib]; + + float summs = GGML_CPU_FP16_TO_FP32(x0->m) * GGML_CPU_FP16_TO_FP32(y0->s); + + uint32_t qh; + memcpy(&qh, x0->qh, sizeof(qh)); + + uint64_t tmp[4]; + tmp[0] = table_b2b_0[(qh >> 0) & 0xFF]; + tmp[1] = table_b2b_0[(qh >> 8) & 0xFF]; + tmp[2] = table_b2b_0[(qh >> 16) & 0xFF]; + tmp[3] = table_b2b_0[(qh >> 24) ]; + + int8x16_t v_qhl = vec_xl(0, (const int8_t *)(tmp + 0)); + int8x16_t v_qhh = vec_xl(0, (const int8_t *)(tmp + 2)); + + // required for fixing the byteorder + v_qhl = vec_perm(v_qhl, v_qhl, v_kperm); + v_qhh = vec_perm(v_qhh, v_qhh, v_kperm); + + const uint8x16_t v_x = vec_xl(0, x0->qs); + const int8x16_t v_xl = (int8x16_t)vec_and(v_x, v_m); + const int8x16_t v_xh = (int8x16_t)vec_sr(v_x, 4); + + const int8x16_t v_xlf = vec_or(v_xl, v_qhl); + const int8x16_t v_xhf = vec_or(v_xh, v_qhh); + + const int8x16_t v_yl = vec_xl(0 , y0->qs); + const int8x16_t v_yh = vec_xl(QK8_1/2, y0->qs); + + const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xlf, v_yl), v_xhf, v_yh); + const float32x4_t v_xyf = vec_float(v_xy); + + const float32x4_t v_d = vec_splats(GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d)); + const float32x4_t v_acc = vec_madd(v_xyf, v_d, v_acc); + + sumf += vec_hsum_f32x4(v_acc) + summs; + } + + *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -277,7 +670,7 @@ void ggml_vec_dot_q8_0_q8_0(int n, float float sumf = 0; #if defined(__VXE__) || defined(__VXE2__) - __vector float acc = vec_splats(0.0f); + float32x4_t acc = vec_splats(0.0f); #pragma GCC unroll 8 for (; ib < nb; ++ib) { @@ -296,20 +689,17 @@ void ggml_vec_dot_q8_0_q8_0(int n, float acc = vec_madd(v_xy, v_d, acc); } - sumf = acc[0] + acc[1] + acc[2] + acc[3]; - -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } + sumf = vec_hsum_f32x4(acc); *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -343,7 +733,7 @@ void ggml_vec_dot_q3_K_q8_K(int n, float uint8x16_t q3h[4]; uint8x16_t q3b[2]; int8x16_t q3bytes[4]; - int8x16_t q8bytes[4]; + int8x16_t q8bytes[8]; uint8x16_t qhbits[2]; float sum = 0; @@ -423,10 +813,10 @@ void ggml_vec_dot_q3_K_q8_K(int n, float isum2 = ggml_vec_dot(v_z, q3bytes[2], q8bytes[6]); isum3 = ggml_vec_dot(v_z, q3bytes[3], q8bytes[7]); - isum += (isum0[0] + isum0[1] + isum0[2] + isum0[3]) * scale[0]; - isum += (isum1[0] + isum1[1] + isum1[2] + isum1[3]) * scale[1]; - isum += (isum2[0] + isum2[1] + isum2[2] + isum2[3]) * scale[2]; - isum += (isum3[0] + isum3[1] + isum3[2] + isum3[3]) * scale[3]; + isum += vec_hsum_i32x4(isum0) * scale[0]; + isum += vec_hsum_i32x4(isum1) * scale[1]; + isum += vec_hsum_i32x4(isum2) * scale[2]; + isum += vec_hsum_i32x4(isum3) * scale[3]; scale += 4; @@ -442,70 +832,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = sum; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -581,7 +914,7 @@ void ggml_vec_dot_q4_K_q8_K(int n, float v_xl[1] = (int8x16_t)vec_and(v_x[1], v_lm); const int32x4_t p1 = ggml_vec_dot(ggml_vec_dot(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); - sumi1 += (p1[0] + p1[1] + p1[2] + p1[3]) * scales[2*j+0]; + sumi1 += vec_hsum_i32x4(p1) * scales[2*j+0]; v_y[0] = vec_xl(0 , y0); v_y[1] = vec_xl(16, y0); @@ -591,7 +924,7 @@ void ggml_vec_dot_q4_K_q8_K(int n, float v_xl[1] = (int8x16_t)vec_sr(v_x[1], 4); const int32x4_t p2 = ggml_vec_dot(ggml_vec_dot(v_z, v_xl[0], v_y[0]), v_xl[1], v_y[1]); - sumi2 += (p2[0] + p2[1] + p2[2] + p2[3]) * scales[2*j+1]; + sumi2 += vec_hsum_i32x4(p2) * scales[2*j+1]; } sumf += d * (sumi1 + sumi2); @@ -600,61 +933,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -720,7 +1006,7 @@ void ggml_vec_dot_q5_K_q8_K(int n, float const int32x4_t v_minsho = vec_mulo(v_ysums, v_minsh); const int32x4_t v_minshe = vec_mule(v_ysums, v_minsh); const int32x4_t v_mins = vec_add(v_minsho, v_minshe); - const int32_t mins = v_mins[0] + v_mins[1] + v_mins[2] + v_mins[3]; + const int32_t mins = vec_hsum_i32x4(v_mins); const uint8_t * scales = (const uint8_t *)utmp; const uint8_t * GGML_RESTRICT x0l = x[i].qs; @@ -757,8 +1043,8 @@ void ggml_vec_dot_q5_K_q8_K(int n, float int32x4_t sumi0 = ggml_vec_dot(ggml_vec_dot(v_z, q5b[0], v_y[0]), q5b[1], v_y[1]); int32x4_t sumi1 = ggml_vec_dot(ggml_vec_dot(v_z, q5b[2], v_y[2]), q5b[3], v_y[3]); - sumi += (sumi0[0] + sumi0[1] + sumi0[2] + sumi0[3]) * *scales++; - sumi += (sumi1[0] + sumi1[1] + sumi1[2] + sumi1[3]) * *scales++; + sumi += vec_hsum_i32x4(sumi0) * *scales++; + sumi += vec_hsum_i32x4(sumi1) * *scales++; } sumf += d * sumi - dmin * mins; @@ -767,66 +1053,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -881,7 +1115,7 @@ void ggml_vec_dot_q6_K_q8_K(int n, float const int32x4_t v_minshe = vec_mule(v_ysumsh, v_scaleh); const int32x4_t v_mins = v_minslo + v_minsle + v_minsho + v_minshe; - const int32_t mins = v_mins[0] + v_mins[1] + v_mins[2] + v_mins[3]; + const int32_t mins = vec_hsum_i32x4(v_mins); int32_t isum = 0; for (int j = 0; j < QK_K/128; ++j) { @@ -921,10 +1155,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float int32x4_t summs2 = ggml_vec_dot(v_z, q6b[2], v_y[2]); int32x4_t summs3 = ggml_vec_dot(v_z, q6b[3], v_y[3]); - isum += (summs0[0] + summs0[1] + summs0[2] + summs0[3]) * scale[0] + - (summs1[0] + summs1[1] + summs1[2] + summs1[3]) * scale[1] + - (summs2[0] + summs2[1] + summs2[2] + summs2[3]) * scale[2] + - (summs3[0] + summs3[1] + summs3[2] + summs3[3]) * scale[3]; + isum += vec_hsum_i32x4(summs0) * scale[0] + + vec_hsum_i32x4(summs1) * scale[1] + + vec_hsum_i32x4(summs2) * scale[2] + + vec_hsum_i32x4(summs3) * scale[3]; scale += 4; @@ -955,10 +1189,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float summs2 = ggml_vec_dot(v_z, q6b[2], v_y[2]); summs3 = ggml_vec_dot(v_z, q6b[3], v_y[3]); - isum += (summs0[0] + summs0[1] + summs0[2] + summs0[3]) * scale[0] + - (summs1[0] + summs1[1] + summs1[2] + summs1[3]) * scale[1] + - (summs2[0] + summs2[1] + summs2[2] + summs2[3]) * scale[2] + - (summs3[0] + summs3[1] + summs3[2] + summs3[3]) * scale[3]; + isum += vec_hsum_i32x4(summs0) * scale[0] + + vec_hsum_i32x4(summs1) * scale[1] + + vec_hsum_i32x4(summs2) * scale[2] + + vec_hsum_i32x4(summs3) * scale[3]; scale += 4; } @@ -969,47 +1203,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float *s = sum; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1183,20 +1380,18 @@ void ggml_vec_dot_iq4_nl_q8_0(int n, flo const int8x16_t v_yh = vec_xl(QK8_0/2, y0->qs); const int32x4_t v_xy = ggml_vec_dot(ggml_vec_dot(vec_splats(0), v_xl, v_yl), v_xh, v_yh); - sumf += GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d) * (v_xy[0] + v_xy[1] + v_xy[2] + v_xy[3]); + sumf += GGML_CPU_FP16_TO_FP32(x0->d) * GGML_CPU_FP16_TO_FP32(y0->d) * vec_hsum_i32x4(v_xy); } -#endif - for (; ib < nb; ++ib) { - const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_CPU_FP16_TO_FP32(x[ib].d); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < QK4_NL/2; ++j) { - sumi1 += y[ib].qs[j+ 0] * kvalues_iq4nl[x[ib].qs[j] & 0xf]; - sumi2 += y[ib].qs[j+QK4_NL/2] * kvalues_iq4nl[x[ib].qs[j] >> 4]; - } - sumf += d * (sumi1 + sumi2); - } *s = sumf; +#else + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_iq4_nl_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_iq4_xs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1254,8 +1449,8 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo h >>= 4; - sumi1 += (vsumi0[0] + vsumi0[1] + vsumi0[2] + vsumi0[3]) * ls1; - sumi2 += (vsumi1[0] + vsumi1[1] + vsumi1[2] + vsumi1[3]) * ls2; + sumi1 += vec_hsum_i32x4(vsumi0) * ls1; + sumi2 += vec_hsum_i32x4(vsumi1) * ls2; } sumf += GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d * (sumi1 + sumi2); @@ -1264,37 +1459,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo *s = sumf; #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/wasm/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/wasm/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/wasm/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/wasm/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -435,30 +435,15 @@ void ggml_vec_dot_q5_0_q8_0(int n, float sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3); -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -545,30 +530,15 @@ void ggml_vec_dot_q5_1_q8_1(int n, float sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3) + summs; -#endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(sumf); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -628,18 +598,15 @@ void ggml_vec_dot_q8_0_q8_0(int n, float sumf = wasm_f32x4_extract_lane(sumv, 0) + wasm_f32x4_extract_lane(sumv, 1) + wasm_f32x4_extract_lane(sumv, 2) + wasm_f32x4_extract_lane(sumv, 3); -#endif - for (; ib < nb; ++ib) { - int sumi = 0; - - for (int j = 0; j < qk; j++) { - sumi += x[ib].qs[j]*y[ib].qs[j]; - } - - sumf += sumi*(GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)); - } - *s = sumf; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + UNUSED(sumf); + ggml_vec_dot_q8_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); +#endif } void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -755,45 +722,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float *s = sumf; #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -902,68 +834,12 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = sumf; #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1089,61 +965,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1279,66 +1108,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = sumf; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1435,47 +1212,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float *s = sumf; #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/x86/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/arch/x86/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/x86/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/x86/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -66,6 +66,12 @@ static inline int hsum_i32_4(const __m12 } #if defined(__AVX2__) || defined(__AVX512F__) +static inline __m256i mul_add_epi8(const __m256i x, const __m256i y) { + const __m256i ax = _mm256_sign_epi8(x, x); + const __m256i sy = _mm256_sign_epi8(y, x); + return _mm256_maddubs_epi16(ax, sy); +} + // spread 32 bits to 32 bytes { 0x00, 0xFF } static inline __m256i bytes_from_bits_32(const uint8_t * x) { uint32_t x32; @@ -261,6 +267,11 @@ static inline __m256 quad_fp16_delta_flo return _mm256_set_m128(_mm_set1_ps(GGML_CPU_FP16_TO_FP32(x1) * GGML_CPU_FP16_TO_FP32(y1)), _mm_set1_ps(GGML_CPU_FP16_TO_FP32(x0) * GGML_CPU_FP16_TO_FP32(y0))); } + +static inline __m256 quad_mx_delta_float(const int8_t x0, const float y0, const int8_t x1, const float y1) { + return _mm256_set_m128(_mm_set1_ps(GGML_E8M0_TO_FP32_HALF(x1) * GGML_CPU_FP16_TO_FP32(y1)), + _mm_set1_ps(GGML_E8M0_TO_FP32_HALF(x0) * GGML_CPU_FP16_TO_FP32(y0))); +} #endif #elif defined(__SSSE3__) // horizontally add 4x4 floats @@ -702,7 +713,6 @@ void ggml_vec_dot_q4_1_q8_1(int n, float const block_q8_1 * GGML_RESTRICT y = vy; int ib = 0; - float sumf = 0; #if defined(__AVX2__) || defined(__AVX__) // Initialize accumulator with zeros @@ -737,25 +747,98 @@ void ggml_vec_dot_q4_1_q8_1(int n, float #endif } - sumf = hsum_float_8(acc) + summs; - + *s = hsum_float_8(acc) + summs; +#else + UNUSED(nb); + UNUSED(x); + UNUSED(y); + UNUSED(ib); + ggml_vec_dot_q4_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - for (; ib < nb; ++ib) { - int sumi0 = 0; - int sumi1 = 0; +} - for (int j = 0; j < qk/2; ++j) { - const int v0 = (x[ib].qs[j] & 0x0F); - const int v1 = (x[ib].qs[j] >> 4); +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); - sumi0 += (v0 * y[ib].qs[j]); - sumi1 += (v1 * y[ib].qs[j + qk/2]); - } + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + +#if defined __AVX2__ + + const __m128i values128 = _mm_loadu_si128((const __m128i*)kvalues_mxfp4); + const __m128i m4b = _mm_set1_epi8(0x0f); + const __m256i mone = _mm256_set1_epi16(1); + + __m256 accum1 = _mm256_setzero_ps(); + __m256 accum2 = _mm256_setzero_ps(); + for (; ib + 1 < nb; ib += 2) { + const __m128i q4bits_1 = _mm_loadu_si128((const __m128i*)x[ib + 0].qs); + const __m128i q4bits_2 = _mm_loadu_si128((const __m128i*)x[ib + 1].qs); + const __m256i q8b_1 = _mm256_loadu_si256((const __m256i *)y[ib + 0].qs); + const __m256i q8b_2 = _mm256_loadu_si256((const __m256i *)y[ib + 1].qs); + const __m256i q4b_1 = MM256_SET_M128I(_mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_1, 4), m4b)), + _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_1, m4b))); + const __m256i q4b_2 = MM256_SET_M128I(_mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_2, 4), m4b)), + _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_2, m4b))); + const __m256i p16_1 = mul_add_epi8(q4b_1, q8b_1); + const __m256i p16_2 = mul_add_epi8(q4b_2, q8b_2); + const __m256i p_1 = _mm256_madd_epi16(p16_1, mone); + const __m256i p_2 = _mm256_madd_epi16(p16_2, mone); + accum1 = _mm256_fmadd_ps(_mm256_set1_ps(GGML_CPU_FP16_TO_FP32(y[ib + 0].d)*GGML_E8M0_TO_FP32_HALF(x[ib + 0].e)), + _mm256_cvtepi32_ps(p_1), accum1); + accum2 = _mm256_fmadd_ps(_mm256_set1_ps(GGML_CPU_FP16_TO_FP32(y[ib + 1].d)*GGML_E8M0_TO_FP32_HALF(x[ib + 1].e)), + _mm256_cvtepi32_ps(p_2), accum2); } + sumf = hsum_float_8(_mm256_add_ps(accum1, accum2)); + +#elif defined __AVX__ + const __m128i values128 = _mm_loadu_si128((const __m128i*)kvalues_mxfp4); + const __m128i m4b = _mm_set1_epi8(0x0f); + + __m256 accum = _mm256_setzero_ps(); + for (; ib + 1 < nb; ib += 2) { + const __m128i q4bits_1 = _mm_loadu_si128((const __m128i *)x[ib + 0].qs); + const __m128i q4bits_2 = _mm_loadu_si128((const __m128i *)x[ib + 1].qs); + const __m128i q8b_1_0 = _mm_loadu_si128((const __m128i *)y[ib + 0].qs); + const __m128i q8b_1_1 = _mm_loadu_si128((const __m128i *)y[ib + 0].qs + 1); + const __m128i q8b_2_0 = _mm_loadu_si128((const __m128i *)y[ib + 1].qs); + const __m128i q8b_2_1 = _mm_loadu_si128((const __m128i *)y[ib + 1].qs + 1); + + const __m128i q4b_1_0 = _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_1, m4b)); + const __m128i q4b_1_1 = _mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_1, 4), m4b)); + const __m128i q4b_2_0 = _mm_shuffle_epi8(values128, _mm_and_si128(q4bits_2, m4b)); + const __m128i q4b_2_1 = _mm_shuffle_epi8(values128, _mm_and_si128(_mm_srli_epi16(q4bits_2, 4), m4b)); + + const __m256 p = mul_sum_i8_quad_float(q4b_1_0, q4b_1_1, q4b_2_0, q4b_2_1, q8b_1_0, q8b_1_1, q8b_2_0, q8b_2_1); + const __m256 deltas = quad_mx_delta_float(x[ib].e, y[ib].d, x[ib + 1].e, y[ib + 1].d); + accum = _mm256_add_ps(_mm256_mul_ps(deltas, p), accum); + } + + sumf = hsum_float_8(accum); + +#endif + for (; ib < nb; ++ib) { + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); + int sumi1 = 0; + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; + } + sumf += d * (sumi1 + sumi2); + } *s = sumf; } @@ -764,7 +847,6 @@ void ggml_vec_dot_q5_0_q8_0(int n, float const int nb = n / qk; int ib = 0; - float sumf = 0; assert(n % qk == 0); assert(qk == QK5_0); @@ -799,7 +881,7 @@ void ggml_vec_dot_q5_0_q8_0(int n, float acc = _mm256_fmadd_ps(d, q, acc); } - sumf = hsum_float_8(acc); + *s = hsum_float_8(acc); #elif defined(__AVX__) // Initialize accumulator with zeros __m256 acc = _mm256_setzero_ps(); @@ -830,32 +912,14 @@ void ggml_vec_dot_q5_0_q8_0(int n, float acc = _mm256_add_ps(_mm256_mul_ps(d, q), acc); } - sumf = hsum_float_8(acc); - + *s = hsum_float_8(acc); +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_0_q8_0_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh & (1u << (j + 0 ))) >> (j + 0 )) << 4; - const uint8_t xh_1 = ((qh & (1u << (j + 16))) >> (j + 12)); - - const int32_t x0 = (int8_t)(((x[ib].qs[j] & 0x0F) | xh_0) - 16); - const int32_t x1 = (int8_t)(((x[ib].qs[j] >> 4) | xh_1) - 16); - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d)) * sumi; - } - - *s = sumf; } void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -863,7 +927,6 @@ void ggml_vec_dot_q5_1_q8_1(int n, float const int nb = n / qk; int ib = 0; - float sumf = 0; assert(n % qk == 0); assert(qk == QK5_1); @@ -901,7 +964,7 @@ void ggml_vec_dot_q5_1_q8_1(int n, float acc = _mm256_fmadd_ps(q, _mm256_mul_ps(dx, dy), acc); } - sumf = hsum_float_8(acc) + summs; + *s = hsum_float_8(acc) + summs; #elif defined(__AVX__) // Initialize accumulator with zeros __m256 acc = _mm256_setzero_ps(); @@ -935,32 +998,14 @@ void ggml_vec_dot_q5_1_q8_1(int n, float acc = _mm256_add_ps(_mm256_mul_ps(q, _mm256_mul_ps(dx, dy)), acc); } - sumf = hsum_float_8(acc) + summs; - + *s = hsum_float_8(acc) + summs; +#else + UNUSED(nb); + UNUSED(ib); + UNUSED(x); + UNUSED(y); + ggml_vec_dot_q5_1_q8_1_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - for (; ib < nb; ++ib) { - uint32_t qh; - memcpy(&qh, x[ib].qh, sizeof(qh)); - - int sumi0 = 0; - int sumi1 = 0; - - for (int j = 0; j < qk/2; ++j) { - const uint8_t xh_0 = ((qh >> (j + 0)) << 4) & 0x10; - const uint8_t xh_1 = ((qh >> (j + 12)) ) & 0x10; - - const int32_t x0 = (x[ib].qs[j] & 0xF) | xh_0; - const int32_t x1 = (x[ib].qs[j] >> 4) | xh_1; - - sumi0 += (x0 * y[ib].qs[j]); - sumi1 += (x1 * y[ib].qs[j + qk/2]); - } - - int sumi = sumi0 + sumi1; - sumf += (GGML_CPU_FP16_TO_FP32(x[ib].d)*GGML_CPU_FP16_TO_FP32(y[ib].d))*sumi + GGML_CPU_FP16_TO_FP32(x[ib].m)*GGML_CPU_FP16_TO_FP32(y[ib].s); - } - - *s = sumf; } void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -1017,7 +1062,6 @@ void ggml_vec_dot_q8_0_q8_0(int n, float } sumf = hsum_float_8(accum); - #endif for (; ib < nb; ++ib) { int sumi = 0; @@ -1157,44 +1201,10 @@ void ggml_vec_dot_tq1_0_q8_K(int n, floa *s = hsum_float_8(sumf); #else - const uint8_t pow3[6] = {1, 3, 9, 27, 81, 243}; - - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int sum = 0; - - for (size_t j = 0; j < sizeof(x->qs) - sizeof(x->qs) % 32; j += 32) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 32; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*32 + m]; - } - } - } - for (size_t j = sizeof(x->qs) - sizeof(x->qs) % 32; j < sizeof(x->qs); j += 16) { - for (size_t l = 0; l < 5; ++l) { - for (size_t m = 0; m < 16; ++m) { - uint8_t q = x[i].qs[j + m] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[j*5 + l*16 + m]; - } - } - } - - for (size_t l = 0; l < 4; ++l) { - for (size_t j = 0; j < sizeof(x->qh); ++j) { - uint8_t q = x[i].qh[j] * pow3[l]; - uint16_t xi = ((uint16_t) q * 3) >> 8; - sum += (xi - 1) * y[i].qs[sizeof(x->qs)*5 + l*sizeof(x->qh) + j]; - } - } - - sumf += (float) sum * (GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d); - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq1_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1257,25 +1267,10 @@ void ggml_vec_dot_tq2_0_q8_K(int n, floa *s = hsum_float_8(sumf); #else - float sumf = 0.0f; - - for (int i = 0; i < nb; ++i) { - int32_t sumi = 0; - - for (size_t j = 0; j < sizeof(x->qs); j += 32) { - for (size_t l = 0; l < 4; ++l) { - for (size_t k = 0; k < 32; ++k) { - sumi += y[i].qs[j*4 + l*32 + k] * (((x[i].qs[j + k] >> (l*2)) & 3) - 1); - } - } - } - - const float d = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - - sumf += (float) sumi * d; - } - - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_tq2_0_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1464,45 +1459,10 @@ void ggml_vec_dot_q2_K_q8_K(int n, float *s = hsum_float_8(acc); #else - - float sumf = 0; - - for (int i = 0; i < nb; ++i) { - - const uint8_t * q2 = x[i].qs; - const int8_t * q8 = y[i].qs; - const uint8_t * sc = x[i].scales; - - int summs = 0; - for (int j = 0; j < 16; ++j) { - summs += y[i].bsums[j] * (sc[j] >> 4); - } - - const float dall = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].d); - const float dmin = y[i].d * GGML_CPU_FP16_TO_FP32(x[i].dmin); - - int isum = 0; - int is = 0; - int d; - for (int k = 0; k < QK_K/128; ++k) { - int shift = 0; - for (int j = 0; j < 4; ++j) { - d = sc[is++] & 0xF; - int isuml = 0; - for (int l = 0; l < 16; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - d = sc[is++] & 0xF; - isuml = 0; - for (int l = 16; l < 32; ++l) isuml += q8[l] * ((q2[l] >> shift) & 3); - isum += d * isuml; - shift += 2; - q8 += 32; - } - q2 += 32; - } - sumf += dall * isum - dmin * summs; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q2_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -1769,70 +1729,13 @@ void ggml_vec_dot_q3_K_q8_K(int n, float *s = hsum_float_8(acc); #else - // scalar version - // This function is written like this so the compiler can manage to vectorize most of it - // Using -Ofast, GCC and clang manage to produce code that is within a factor of 2 or so from the - // manually vectorized version above. Every other version I tried would run at least 4 times slower. - // The ideal situation would be if we could just write the code once, and the compiler would - // automatically produce the best possible set of machine instructions, instead of us having to manually - // write vectorized versions for AVX, ARM_NEON, etc. - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - uint32_t auxs[4]; - const int8_t * scales = (const int8_t*)auxs; - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].hmask; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) a[l] = q3[l] & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 2) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 4) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (q3[l] >> 6) & 3; - for (int l = 0; l < 32; ++l) a[l] -= (hm[l] & m ? 0 : 4); - a += 32; m <<= 1; - q3 += 32; - } - a = aux8; - - memcpy(auxs, x[i].scales, 12); - uint32_t tmp = auxs[2]; - auxs[2] = ((auxs[0] >> 4) & kmask2) | (((tmp >> 4) & kmask1) << 4); - auxs[3] = ((auxs[1] >> 4) & kmask2) | (((tmp >> 6) & kmask1) << 4); - auxs[0] = (auxs[0] & kmask2) | (((tmp >> 0) & kmask1) << 4); - auxs[1] = (auxs[1] & kmask2) | (((tmp >> 2) & kmask1) << 4); - for (int j = 0; j < QK_K/16; ++j) { - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += (scales[j] - 32) * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; - + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q3_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -2002,61 +1905,14 @@ void ggml_vec_dot_q4_K_q8_K(int n, float *s = hsum_float_8(acc) + _mm_cvtss_f32(acc_m); #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - a += 32; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - a += 32; q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q4_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2259,66 +2115,14 @@ void ggml_vec_dot_q5_K_q8_K(int n, float *s = hsum_float_8(acc) + summs; #else - - const uint8_t * scales = (const uint8_t*)&utmp[0]; - const uint8_t * mins = (const uint8_t*)&utmp[2]; - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].qs; - const uint8_t * GGML_RESTRICT hm = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - uint8_t m = 1; - for (int j = 0; j < QK_K/64; ++j) { - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] & 0xF); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - for (int l = 0; l < 32; ++l) a[l] = (int8_t)(q4[l] >> 4); - for (int l = 0; l < 32; ++l) a[l] += (hm[l] & m ? 16 : 0); - a += 32; m <<= 1; - q4 += 32; - } - memcpy(utmp, x[i].scales, 12); - utmp[3] = ((utmp[2] >> 4) & kmask2) | (((utmp[1] >> 6) & kmask3) << 4); - const uint32_t uaux = utmp[1] & kmask1; - utmp[1] = (utmp[2] & kmask2) | (((utmp[0] >> 6) & kmask3) << 4); - utmp[2] = uaux; - utmp[0] &= kmask1; - - int sumi = 0; - for (int j = 0; j < QK_K/16; ++j) sumi += y[i].bsums[j] * mins[j/2]; - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/32; ++j) { - int32_t scale = scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - const float dmin = GGML_CPU_FP16_TO_FP32(x[i].dmin) * y[i].d; - sumf -= dmin * sumi; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + UNUSED(utmp); + ggml_vec_dot_q5_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2520,47 +2324,10 @@ void ggml_vec_dot_q6_K_q8_K(int n, float *s = hsum_float_8(acc); #else - - int8_t aux8[QK_K]; - int16_t aux16[8]; - float sums [8]; - int32_t aux32[8]; - memset(sums, 0, 8*sizeof(float)); - - float sumf = 0; - for (int i = 0; i < nb; ++i) { - const uint8_t * GGML_RESTRICT q4 = x[i].ql; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - memset(aux32, 0, 8*sizeof(int32_t)); - int8_t * GGML_RESTRICT a = aux8; - for (int j = 0; j < QK_K; j += 128) { - for (int l = 0; l < 32; ++l) { - a[l + 0] = (int8_t)((q4[l + 0] & 0xF) | (((qh[l] >> 0) & 3) << 4)) - 32; - a[l + 32] = (int8_t)((q4[l + 32] & 0xF) | (((qh[l] >> 2) & 3) << 4)) - 32; - a[l + 64] = (int8_t)((q4[l + 0] >> 4) | (((qh[l] >> 4) & 3) << 4)) - 32; - a[l + 96] = (int8_t)((q4[l + 32] >> 4) | (((qh[l] >> 6) & 3) << 4)) - 32; - } - a += 128; - q4 += 64; - qh += 32; - } - a = aux8; - int is = 0; - for (int j = 0; j < QK_K/16; ++j) { - int scale = x[i].scales[is++]; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - for (int l = 0; l < 8; ++l) aux16[l] = q8[l] * a[l]; - for (int l = 0; l < 8; ++l) aux32[l] += scale * aux16[l]; - q8 += 8; a += 8; - } - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - for (int l = 0; l < 8; ++l) sums[l] += d * aux32[l]; - } - for (int l = 0; l < 8; ++l) sumf += sums[l]; - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_q6_K_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -2712,34 +2479,10 @@ void ggml_vec_dot_iq2_xxs_q8_K(int n, fl *s = 0.125f * hsum_float_8(accumf); #else - - uint32_t aux32[2]; - const uint8_t * aux8 = (const uint8_t *)aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(aux32, q2, 2*sizeof(uint32_t)); - q2 += 4; - const uint32_t ls = 2*(aux32[1] >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xxs_grid + aux8[l]); - const uint8_t signs = ksigns_iq2xs[(aux32[1] >> 7*l) & 127]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3033,42 +2776,10 @@ void ggml_vec_dot_iq2_xs_q8_K(int n, flo *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint16_t * GGML_RESTRICT q2 = x[i].qs; - const uint8_t * GGML_RESTRICT sc = x[i].scales; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - const uint16_t ls1 = 2*(sc[ib32] & 0xf) + 1; - const uint16_t ls2 = 2*(sc[ib32] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls1; - sumi = 0; - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2xs_grid + (q2[l] & 511)); - const uint8_t signs = ksigns_iq2xs[q2[l] >> 9]; - for (int j = 0; j < 8; ++j) { - sumi += grid[j] * q8[j] * (signs & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += sumi * ls2; - q2 += 4; - } - sumf += d * bsum; - } - *s = 0.125f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3250,47 +2961,11 @@ void ggml_vec_dot_iq2_s_q8_K(int n, floa *s = 0.125f * hsum_float_8(accumf); #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint8_t * signs = qs + QK_K/8; - - int bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - int ls1 = 1 + 2*(x[i].scales[ib32] & 0xf); - int ls2 = 1 + 2*(x[i].scales[ib32] >> 4); - int sumi1 = 0, sumi2 = 0; - for (int l = 0; l < 2; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi1 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - for (int l = 2; l < 4; ++l) { - const uint8_t * grid = (const uint8_t *)(iq2s_grid + (qs[l] | (qh[ib32] << (8-2*l) & 0x300))); - for (int j = 0; j < 8; ++j) { - sumi2 += q8[j] * grid[j] * (signs[l] & kmask_iq2xs[j] ? -1 : 1); - } - q8 += 8; - } - bsum += ls1 * sumi1 + ls2 * sumi2; - qs += 4; - signs += 4; - } - - sumf += d * bsum; - } - - *s = 0.125f * sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq2_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif - } void ggml_vec_dot_iq3_xxs_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { @@ -3410,36 +3085,10 @@ void ggml_vec_dot_iq3_xxs_q8_K(int n, fl *s = 0.25f * hsum_float_8(accumf); #else - - uint32_t aux32; - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT q3 = x[i].qs; - const uint8_t * GGML_RESTRICT gas = x[i].qs + QK_K/4; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ++ib32) { - memcpy(&aux32, gas, sizeof(uint32_t)); gas += sizeof(uint32_t); - const uint32_t ls = 2*(aux32 >> 28) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3xxs_grid + q3[2*l+0]); - const uint8_t * grid2 = (const uint8_t *)(iq3xxs_grid + q3[2*l+1]); - const uint8_t signs = ksigns_iq2xs[(aux32 >> 7*l) & 127]; - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - q3 += 8; - bsum += sumi * ls; - } - sumf += d * bsum; - } - *s = 0.25f * sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_xxs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -3646,59 +3295,13 @@ void ggml_vec_dot_iq3_s_q8_K(int n, floa *s = hsum_float_8(accumf); #else - - float sumf = 0.f; - for (int i = 0; i < nb; ++i) { - const float d = GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d; - const uint8_t * GGML_RESTRICT qs = x[i].qs; - const uint8_t * GGML_RESTRICT qh = x[i].qh; - const uint8_t * GGML_RESTRICT signs = x[i].signs; - const int8_t * GGML_RESTRICT q8 = y[i].qs; - int32_t bsum = 0; - for (int ib32 = 0; ib32 < QK_K/32; ib32 += 2) { - const uint32_t ls1 = 2*(x[i].scales[ib32/2] & 0xf) + 1; - const uint32_t ls2 = 2*(x[i].scales[ib32/2] >> 4) + 1; - int32_t sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+0] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+0] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls1; - sumi = 0; - for (int l = 0; l < 4; ++l) { - const uint8_t * grid1 = (const uint8_t *)(iq3s_grid + (qs[2*l+0] | ((qh[ib32+1] << (8-2*l)) & 256))); - const uint8_t * grid2 = (const uint8_t *)(iq3s_grid + (qs[2*l+1] | ((qh[ib32+1] << (7-2*l)) & 256))); - for (int j = 0; j < 4; ++j) { - sumi += grid1[j] * q8[j+0] * (signs[l] & kmask_iq2xs[j+0] ? -1 : 1); - sumi += grid2[j] * q8[j+4] * (signs[l] & kmask_iq2xs[j+4] ? -1 : 1); - } - q8 += 8; - } - qs += 8; - signs += 4; - bsum += sumi * ls2; - } - sumf += d * bsum; - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq3_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } -#if defined(__AVX2__) -static inline __m256i mul_add_epi8(const __m256i x, const __m256i y) { - const __m256i ax = _mm256_sign_epi8(x, x); - const __m256i sy = _mm256_sign_epi8(y, x); - return _mm256_maddubs_epi16(ax, sy); -} -#endif - void ggml_vec_dot_iq1_s_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { assert(n % QK_K == 0); assert(nrc == 1); @@ -3811,36 +3414,10 @@ void ggml_vec_dot_iq1_s_q8_K(int n, floa *s = hsum_float_8(accum) + IQ1S_DELTA * accum1; #else - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint16_t * qh = x[i].qh; - - int sumi = 0, sumi1 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - const int ls = 2*((qh[ib] >> 12) & 7) + 1; - const int delta = qh[ib] & 0x8000 ? -1 : 1; - int lsum = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((qh[ib] >> 3*l) & 7) << 8))); - for (int j = 0; j < 8; ++j) { - lsum += q8[j] * grid[j]; - } - q8 += 8; - } - sumi += ls * lsum; - sumi1 += ls * delta * (y[i].bsums[2*ib+0] + y[i].bsums[2*ib+1]); - qs += 4; - } - - sumf += GGML_CPU_FP16_TO_FP32(x[i].d) * y[i].d * (sumi + IQ1S_DELTA * sumi1); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq1_s_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4043,52 +3620,11 @@ void ggml_vec_dot_iq1_m_q8_K(int n, floa *s = hsum_float_8(accum1) + IQ1M_DELTA * hsum_float_8(accum2); #else - - int sum1[2], sum2[2], delta[4]; - - float sumf = 0; - for (int i = 0; i < nb; i++) { - - const int8_t * q8 = y[i].qs; - const uint8_t * qs = x[i].qs; - const uint8_t * qh = x[i].qh; - const uint16_t * sc = (const uint16_t *)x[i].scales; - - scale.u16 = (sc[0] >> 12) | ((sc[1] >> 8) & 0x00f0) | ((sc[2] >> 4) & 0x0f00) | (sc[3] & 0xf000); - - int sumi1 = 0, sumi2 = 0; - for (int ib = 0; ib < QK_K/32; ++ib) { - delta[0] = qh[0] & 0x08 ? -1 : 1; - delta[1] = qh[0] & 0x80 ? -1 : 1; - delta[2] = qh[1] & 0x08 ? -1 : 1; - delta[3] = qh[1] & 0x80 ? -1 : 1; - sum1[0] = sum1[1] = sum2[0] = sum2[1] = 0; - for (int l = 0; l < 4; ++l) { - const int8_t * grid = (const int8_t *)(iq1s_grid + (qs[l] | (((uint16_t)qh[l/2] << (8 - 4*(l%2))) & 0x700))); - int lsum1 = 0, lsum2 = 0; - for (int j = 0; j < 8; ++j) { - lsum1 += q8[j] * grid[j]; - lsum2 += q8[j]; - } - q8 += 8; - sum1[l/2] += lsum1; - sum2[l/2] += lsum2*delta[l]; - } - - const int ls1 = 2*((sc[ib/2] >> (6*(ib%2)+0)) & 0x7) + 1; - const int ls2 = 2*((sc[ib/2] >> (6*(ib%2)+3)) & 0x7) + 1; - - sumi1 += sum1[0] * ls1 + sum1[1] * ls2; - sumi2 += sum2[0] * ls1 + sum2[1] * ls2; - qs += 4; - qh += 2; - } - - sumf += GGML_CPU_FP16_TO_FP32(scale.f16) * y[i].d * (sumi1 + IQ1M_DELTA * sumi2); - } - - *s = sumf; - + UNUSED(x); + UNUSED(y); + UNUSED(nb); + UNUSED(scale); + ggml_vec_dot_iq1_m_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } @@ -4275,37 +3811,10 @@ void ggml_vec_dot_iq4_xs_q8_K(int n, flo *s = hsum_float_8(accum); #else - float sumf = 0; - for (int ibl = 0; ibl < nb; ++ibl) { - const float d4d8 = GGML_CPU_FP16_TO_FP32(x[ibl].d) * y[ibl].d; - uint16_t h = x[ibl].scales_h; - const uint8_t * qs = x[ibl].qs; - const int8_t * q8 = y[ibl].qs; - for (int ib = 0; ib < QK_K/32; ib += 2) { - const uint8_t ls1 = (x[ibl].scales_l[ib/2] & 0xf) | ((h << 4) & 0x30); - const uint8_t ls2 = (x[ibl].scales_l[ib/2] >> 4) | ((h << 2) & 0x30); - h >>= 4; - const float d1 = d4d8*(ls1 - 32); - const float d2 = d4d8*(ls2 - 32); - int sumi1 = 0, sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d1 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - sumi1 = sumi2 = 0; - for (int j = 0; j < 16; ++j) { - sumi1 += q8[j+ 0] * kvalues_iq4nl[qs[j] & 0xf]; - sumi2 += q8[j+16] * kvalues_iq4nl[qs[j] >> 4]; - } - sumf += d2 * (sumi1 + sumi2); - qs += 16; - q8 += 32; - } - } - *s = sumf; + UNUSED(x); + UNUSED(y); + UNUSED(nb); + ggml_vec_dot_iq4_xs_q8_K_generic(n, s, bs, vx, bx, vy, by, nrc); #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch/x86/repack.cpp 6641+dfsg-2/ggml/src/ggml-cpu/arch/x86/repack.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/arch/x86/repack.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch/x86/repack.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -281,35 +281,9 @@ void ggml_quantize_mat_q8_0_4x8(const fl } #else - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK8_0]; - float id[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK8_0 + j]; - amax = MAX(amax, fabsf(srcv[row_iter][j])); - } - - const float d = amax / ((1 << 7) - 1); - id[row_iter] = d ? 1.0f / d : 0.0f; - - y[i].d[row_iter] = GGML_CPU_FP32_TO_FP16(d); - } - - for (int j = 0; j < QK8_0 * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - - float x0 = srcv[src_id][src_offset] * id[src_id]; - y[i].qs[j] = roundf(x0); - } - } + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_0_4x8_generic(x, vy, k); #endif } @@ -531,84 +505,40 @@ void ggml_quantize_mat_q8_K_4x8(const fl } #else + UNUSED(nb); + UNUSED(y); + ggml_quantize_mat_q8_K_4x8_generic(x, vy, k); +#endif +} - // scalar - const int blck_size_interleave = 8; - float srcv[4][QK_K]; - float iscale[4]; - - for (int i = 0; i < nb; i++) { - for (int row_iter = 0; row_iter < 4; row_iter++) { - float amax = 0.0f; // absolute max - float max = 0; - - for (int j = 0; j < QK_K; j++) { - srcv[row_iter][j] = x[row_iter * k + i * QK_K + j]; - // Update the maximum value of the corresponding super block - if(amax < fabsf(srcv[row_iter][j])) { - amax = fabsf(srcv[row_iter][j]); - max = srcv[row_iter][j]; - } - } - - iscale[row_iter] = amax ? -127.f/max : 0; - - y[i].d[row_iter] = amax ? 1/iscale[row_iter] : 0; - } - - for (int j = 0; j < QK_K / 4; j++) { - y[i].bsums[j] = 0; - } +// +// GEMV/GEMM templates +// - // Quants values are interleaved in sequence of eight bytes from corresponding super blocks - // Bsums values are interleaved in sequence of four bsums from each super block taken for interleaving - // i.e first four bsums from the first super block, followed by first four bsums from second super block and so on - for (int j = 0; j < QK_K * 4; j++) { - int src_offset = (j / (4 * blck_size_interleave)) * blck_size_interleave; - int src_id = (j % (4 * blck_size_interleave)) / blck_size_interleave; - src_offset += (j % blck_size_interleave); - int index = (((j & 31) >> 3) << 2) + ((j >> 8) << 4) + ((j >> 6) & 3); +#if defined(__AVX2__) || defined(__AVX512F__) - float x0 = srcv[src_id][src_offset] * iscale[src_id]; - y[i].qs[j] = nearest_int(x0); - y[i].bsums[index] += y[i].qs[j]; - } - } -#endif -} +// GEMV for 8x blocks of 32 4-bit quants with a single scale factor per block +template +static void gemv_q4_b32_8x8_q8_0_lut_avx(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc, __m256i signextendlut) { + static_assert( + std::is_same_v || + std::is_same_v, + "Unsupported block type"); -void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { const int qk = QK8_0; const int nb = n / qk; - const int ncols_interleaved = 8; - const int blocklen = 8; - - assert (n % qk == 0); - assert (nc % ncols_interleaved == 0); - UNUSED(s); UNUSED(bs); - UNUSED(vx); - UNUSED(vy); - UNUSED(nr); - UNUSED(nc); - UNUSED(nb); - UNUSED(ncols_interleaved); - UNUSED(blocklen); -#if defined(__AVX2__) - // Lookup table to convert signed nibbles to signed bytes - __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); - signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); __m128i changemask = _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0); __m256i finalpermutemask = _mm256_set_epi32(7, 5, 3, 1, 6, 4, 2, 0); // Permute mask used for easier vector processing at later stages const __m256i m4b = _mm256_set1_epi8(0x0F); - int64_t b_nb = n / QK4_0; + int64_t b_nb = n / 32; - const block_q4_0x8 * b_ptr_start = (const block_q4_0x8 *)vx; + const block_tx8 * b_ptr_start = (const block_tx8 *)vx; const block_q8_0 * a_ptr_start = (const block_q8_0 *)vy; // Process Q8_0 blocks one by one @@ -617,17 +547,17 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, floa // Pointers to LHS blocks of block_q8_0 format const block_q8_0 * a_ptr = a_ptr_start + (y * nb); - // Take group of eight block_q4_0x8 structures at each pass of the loop and perform dot product operation + // Take group of eight blocks at each pass of the loop and perform dot product operation for (int64_t x = 0; x < nc / 8; x++) { // Pointers to RHS blocks - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); // Master FP accumulator __m256 acc_row = _mm256_setzero_ps(); for (int64_t b = 0; b < nb; b++) { - // Load 8 blocks of Q4_0 interleaved as 8 bytes (B0 - B7) + // Load 8 blocks of 32 interleaved as 8 bytes (B0 - B7) const __m256i rhs_raw_vec_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); const __m256i rhs_raw_vec_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs) + 1); const __m256i rhs_raw_vec_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs) + 2); @@ -644,8 +574,13 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, floa const __m256i rhs_vec_0123_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 4), m4b)); // B0(24-31) B1(24-31) B2(24-31) B3(24-31) const __m256i rhs_vec_4567_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 4), m4b)); // B4(24-31) B5(24-31) B6(24-31) B7(24-31) - // Load the scale values for the 8 blocks interleaved in block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, changemask); + // Load the scale values for the 8 blocks interleaved in block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, changemask); + } // Load and convert to FP32 scale from block_q8_0 const __m256 row_scale_f32 = _mm256_set1_ps(GGML_CPU_FP16_TO_FP32(a_ptr[b].d)); @@ -686,34 +621,772 @@ void ggml_gemv_q4_0_8x8_q8_0(int n, floa _mm256_storeu_ps(s + (y * nr + x * 8), acc_row); } } - return; +} -#endif - { - float sumf[8]; - int sumi; +// GEMM for 8x blocks of 32 4-bit quants with a single scale factor per block +template +static void gemm_q4_b32_8x8_q8_0_lut_avx(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc, __m256i signextendlut) { + static_assert( + std::is_same_v || + std::is_same_v, + "Unsupported block type"); - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); - } + const int qk = QK8_0; + const int nb = n / qk; + + const block_tx8 * b_ptr_start = (const block_tx8 *)vx; + const block_q8_0x4 * a_ptr_start = (const block_q8_0x4 *)vy; + + int64_t b_nb = n / 32; + int64_t y = 0; + // Mask to mask out nibbles from packed bytes + const __m256i m4b = _mm256_set1_epi8(0x0F); + const __m128i loadMask = _mm_blend_epi32(_mm_setzero_si128(), _mm_set1_epi32(0xFFFFFFFF), 3); + // Permute mask used for easier vector processing at later stages + __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); + int64_t xstart = 0; + int anr = nr - nr%16; // Used to align nr with boundary of 16 +#ifdef __AVX512F__ + int anc = nc - nc%16; // Used to align nc with boundary of 16 + // Mask to mask out nibbles from packed bytes expanded to 512 bit length + const __m512i m4bexpanded = _mm512_set1_epi8(0x0F); + // Lookup table to convert signed nibbles to signed bytes expanded to 512 bit length + __m512i signextendlutexpanded = _mm512_inserti32x8(_mm512_castsi256_si512(signextendlut), signextendlut, 1); + + // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_0x4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of two block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_tx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_tx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the sixteen blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5B8B9BCBD, B2B3B6B7BABBBEBF for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + // 4-bit -> 8-bit - Sign is maintained + const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) + const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) + + const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) + const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) + + const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) + const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) + + const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) + const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) + + // Shuffle pattern one - right side input + const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) + const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) + + const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) + const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) + + const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) + const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) + + const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) + const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) + + // Shuffle pattern two - right side input + + const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) + const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) + + const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) + const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) + + const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) + const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) + + const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) + const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) + + // Scale values - Load the weight scale values of two block_tx8 + __m512 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); } + + // Process LHS in pairs of rows + for (int rp = 0; rp < 4; rp++) { + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); + __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); + __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); + __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); + __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); + __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); + __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); + __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); + __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); + __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); + __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); + __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); + + __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); + __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); + __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); + __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); + __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); + __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); + __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); + __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); + + // Shuffle pattern one - left side input + + const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m512i zero = _mm512_setzero_epi32(); + __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); + __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptrs[rp][b].d), loadMask), 68); + const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); + + // Multiply with appropiate scales and accumulate + acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + } + } + + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } } + + // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < nr / 4; y ++) { + const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of two block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_tx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_tx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the sixteen blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + // 4-bit -> 8-bit - Sign is maintained + const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) + const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) + + const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) + const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) + + const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) + const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) + + const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) + const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) + + // Shuffle pattern one - right side input + const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) + const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) + + const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) + const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) + + const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) + const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) + + const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) + const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) + + // Shuffle pattern two - right side input + + const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) + const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) + + const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) + const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) + + const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) + const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) + + const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) + const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) + + + // Scale values - Load the weight scale values of two block_tx8 + __m512 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + } + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); + __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); + __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); + __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); + __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); + __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); + __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); + __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); + __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); + __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); + __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); + __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); + + __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); + __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); + __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); + __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); + __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); + __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); + __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); + __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); + + // Shuffle pattern one - left side input + + const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m512i zero = _mm512_setzero_epi32(); + __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); + __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); + __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); + __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); + __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptr[b].d), loadMask), 68); + const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); + + // Multiply with appropiate scales and accumulate + acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + } + + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } + if (anc != nc) { + xstart = anc/8; + y = 0; + } +#endif // __AVX512F__ + + // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation + + for (; y < anr / 4; y += 4) { + const block_q8_0x4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_tx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the eight blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + // 4-bit -> 8-bit - Sign is maintained + const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) + const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) + + const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) + const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) + + const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) + const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) + + const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) + const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) + const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) + + const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) + const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) + + const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) + const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) + + const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) + const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) + + // Shuffle pattern two - right side input + + const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) + const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) + + const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) + const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) + + const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) + const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) + + const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) + const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) + + // Scale values - Load the wight scale values of block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + } + + // Process LHS in groups of four + for (int rp = 0; rp < 4; rp++) { + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); + __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); + __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); + __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); + __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); + __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); + __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); + __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); + __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); + __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); + __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); + __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m256i zero = _mm256_setzero_si256(); + __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); + __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptrs[rp][b].d, loadMask); + + // Multiply with appropiate scales and accumulate + acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + } + } + + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } + + // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation + for (; y < nr / 4; y ++) { + const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); + + // Load the eight blocks of quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + for (int64_t x = xstart; x < nc / 8; x++) { + const block_tx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Load the eight block_q8_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + // 4-bit -> 8-bit - Sign is maintained + const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) + const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) + + const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) + const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) + + const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) + const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) + + const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) + const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) + const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) + + const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) + const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) + + const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) + const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) + + const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) + const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) + + // Shuffle pattern two - right side input + + const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) + const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) + + const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) + const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) + + const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) + const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) + + const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) + const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) + + // Scale values - Load the wight scale values of block_tx8 + __m256 col_scale_f32; + if constexpr ( + std::is_same_v || + std::is_same_v) { + col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + } + + // Load the four blocks of quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); + __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); + __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); + __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); + __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); + __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); + __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); + __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); + __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); + __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); + __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); + __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); + + // Shuffle pattern one - left side input + + const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) + const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + + const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) + const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + + const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) + const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + + const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) + const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + + // Shuffle pattern two - left side input + + const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) + const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + + const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) + const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + + const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) + const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + + const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) + const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + // Resembles MMLAs into 2x2 matrices in ARM Version + const __m256i zero = _mm256_setzero_si256(); + __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); + __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); + __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); + __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); + __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); + __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); + __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); + __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes + const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptr[b].d, loadMask); + + // Multiply with appropiate scales and accumulate + acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + } + + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); + } + } + } +} + +#endif // defined(__AVX2__) || defined(__AVX512F__) + +void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) || defined(__AVX512F__) + { + // Lookup table to convert signed nibbles to signed bytes + __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + + gemv_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; + } +#endif + + ggml_gemv_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemv_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -932,72 +1605,33 @@ void ggml_gemv_q4_K_8x8_q8_K(int n, floa } #else + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + ggml_gemv_q4_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); +#endif +} - float sumf[8]; - float sum_minf[8]; - uint32_t utmp[32]; - int sumi1; - int sumi2; - int sumi; - - const block_q8_K * a_ptr = (const block_q8_K *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_Kx8 * b_ptr = (const block_q4_Kx8 *) vx + (x * nb); - - for (int j = 0; j < ncols_interleaved; j++) { - sumf[j] = 0.0; - sum_minf[j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int sb = 0; sb < 8; sb++) { - memcpy(utmp + sb * 4, b_ptr[l].scales + sb * 12, 12); - utmp[sb * 4 + 3] = ((utmp[sb * 4 + 2] >> 4) & kmask2) | (((utmp[sb * 4 + 1] >> 6) & kmask3) << 4); - const uint32_t uaux_0 = utmp[sb * 4 + 1] & kmask1; - utmp[sb * 4 + 1] = (utmp[sb * 4 + 2] & kmask2) | (((utmp[sb * 4 + 0] >> 6) & kmask3) << 4); - utmp[sb * 4 + 2] = uaux_0; - utmp[sb * 4 + 0] &= kmask1; - } - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - uint8_t *scales_0 = (uint8_t*) utmp + (k / 4) * 32; - uint8_t *scales_1 = (uint8_t*) utmp + (k / 4) * 32 + 16; - for (int j = 0; j < ncols_interleaved; j++) { - sumi1 = 0; - sumi2 = 0; - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4); - sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 64 + (k % 4) * blocklen + i]); - sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 64 + (k % 4) * blocklen + i + 32]); - sumi1 = sumi1 * scales_0[j]; - sumi2 = sumi2 * scales_1[j]; - sumi += sumi1 + sumi2; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d; - } - } - for (int sb = 0; sb < 8; sb++) { - uint8_t *mins = (uint8_t*) utmp + 8 + sb * 16; - for (int j = 0; j < ncols_interleaved; j++) { - sum_minf[j] += mins[j] * (a_ptr[l].bsums[sb * 2] + a_ptr[l].bsums[sb * 2 + 1]) * GGML_CPU_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d; - } - } - } - for (int j = 0; j < ncols_interleaved; j++) { - s[x * ncols_interleaved + j] = sumf[j] - sum_minf[j]; - } - } +void ggml_gemv_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) + __m256i signextendlut = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i*)kvalues_iq4nl)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + + gemv_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; #endif + + ggml_gemv_iq4_nl_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } -void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { - const int qk = QK8_0; +void ggml_gemv_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; const int nb = n / qk; const int ncols_interleaved = 8; const int blocklen = 8; assert (n % qk == 0); - assert (nr % 4 == 0); assert (nc % ncols_interleaved == 0); UNUSED(s); @@ -1010,763 +1644,314 @@ void ggml_gemm_q4_0_8x8_q8_0(int n, floa UNUSED(ncols_interleaved); UNUSED(blocklen); -#if defined(__AVX2__) || defined(__AVX512F__) - { - const block_q4_0x8 * b_ptr_start = (const block_q4_0x8 *)vx; - const block_q8_0x4 * a_ptr_start = (const block_q8_0x4 *)vy; - int64_t b_nb = n / QK4_0; - int64_t y = 0; - // Mask to mask out nibbles from packed bytes - const __m256i m4b = _mm256_set1_epi8(0x0F); - const __m128i loadMask = _mm_blend_epi32(_mm_setzero_si128(), _mm_set1_epi32(0xFFFFFFFF), 3); - // Lookup table to convert signed nibbles to signed bytes - __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); - signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); - // Permute mask used for easier vector processing at later stages - __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); - int64_t xstart = 0; - int anr = nr - nr%16; // Used to align nr with boundary of 16 - #ifdef __AVX512F__ - int anc = nc - nc%16; // Used to align nc with boundary of 16 - // Mask to mask out nibbles from packed bytes expanded to 512 bit length - const __m512i m4bexpanded = _mm512_set1_epi8(0x0F); - // Lookup table to convert signed nibbles to signed bytes expanded to 512 bit length - __m512i signextendlutexpanded = _mm512_inserti32x8(_mm512_castsi256_si512(signextendlut), signextendlut, 1); - - // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < anr / 4; y += 4) { - - const block_q8_0x4 * a_ptrs[4]; - - a_ptrs[0] = a_ptr_start + (y * nb); - for (int i = 0; i < 3; ++i) { - a_ptrs[i + 1] = a_ptrs[i] + nb; - } - - // Take group of two block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = 0; x < anc / 8; x += 2) { - - const block_q4_0x8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); - const block_q4_0x8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); - - // Master FP accumulators - __m512 acc_rows[16]; - for (int i = 0; i < 16; i++) { - acc_rows[i] = _mm512_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the sixteen block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); - - const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); - const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); - const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); - const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5B8B9BCBD, B2B3B6B7BABBBEBF for further processing and storing of values - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); - const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); - - const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); - const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); - const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); - const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); - - // 4-bit -> 8-bit - Sign is maintained - const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) - const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) - - const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) - const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) - - const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) - const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) - - const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) - const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) - - // Shuffle pattern one - right side input - const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) - const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) - - const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) - const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) - - const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) - const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) - - const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) - const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) - - // Shuffle pattern two - right side input - - const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) - const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) - - const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) - const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) - - const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) - const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) - - const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) - const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) - - // Scale values - Load the weight scale values of two block_q4_0x8 - const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); - - // Process LHS in pairs of rows - for (int rp = 0; rp < 4; rp++) { - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector - __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); - __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); - __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); - __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); - __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); - __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); - __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); - __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); - __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); - __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); - __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); - __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); - - __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); - __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); - __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); - __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); - __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); - __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); - __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); - __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); - - // Shuffle pattern one - left side input - - const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - - const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m512i zero = _mm512_setzero_epi32(); - __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); - __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - - - // Straighten out to make 4 row vectors - __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); - __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); - __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); - __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); - - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptrs[rp][b].d), loadMask), 68); - const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); - - // Multiply with appropiate scales and accumulate - acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); - acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); - acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); - acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); - } - } - - // Store the accumulated values - for (int i = 0; i < 16; i++) { - _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } - // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < nr / 4; y ++) { - - const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); - - // Take group of two block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = 0; x < anc / 8; x += 2) { - - const block_q4_0x8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); - const block_q4_0x8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); - - // Master FP accumulators - __m512 acc_rows[4]; - for (int i = 0; i < 4; i++) { - acc_rows[i] = _mm512_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the sixteen block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....BE,BF - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_0[b].qs + 96)); - - const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs)); - const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 32)); - const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 64)); - const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i *)(b_ptr_1[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); - const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); - const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); - - const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); - const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); - const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); - const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); - - // 4-bit -> 8-bit - Sign is maintained - const __m512i rhs_mat_014589CD_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_0, m4bexpanded)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) B8(0-7) B9(0-7) BC(0-7) BD(0-7) - const __m512i rhs_mat_2367ABEF_0 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_0, m4bexpanded)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) BA(0-7) BB(0-7) BE(0-7) BF(0-7) - - const __m512i rhs_mat_014589CD_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_014589CD_1, m4bexpanded)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) B8(8-15) B9(8-15) BC(8-15) BD(8-15) - const __m512i rhs_mat_2367ABEF_1 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(rhs_raw_mat_2367ABEF_1, m4bexpanded)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) BA(8-15) BB(8-15) BE(8-15) BF(8-15) - - const __m512i rhs_mat_014589CD_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m4bexpanded)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) B8(16-23) B9(16-23) BC(16-23) BD(16-23) - const __m512i rhs_mat_2367ABEF_2 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m4bexpanded)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) BA(16-23) BB(16-23) BE(16-23) BF(16-23) - - const __m512i rhs_mat_014589CD_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m4bexpanded)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) B8(24-31) B9(24-31) BC(24-31) BD(24-31) - const __m512i rhs_mat_2367ABEF_3 = _mm512_shuffle_epi8(signextendlutexpanded, _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m4bexpanded)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) BA(24-31) BB(24-31) BE(24-31) BF(24-31) - - // Shuffle pattern one - right side input - const __m512i rhs_mat_014589CD_0_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) B8(0-3) B9(0-3) B8(0-3) B9(0-3) BC(0-3) BD(0-3) BC(0-3) BD(0-3) - const __m512i rhs_mat_2367ABEF_0_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) BA(0-3) BB(0-3) BA(0-3) BB(0-3) BE(0-3) BF(0-3) BE(0-3) BF(0-3) - - const __m512i rhs_mat_014589CD_1_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) B8(8-11) B9(8-11) B8(8-11) B9(8-11) BC(8-11) BD(8-11) BC(8-11) BD(8-11) - const __m512i rhs_mat_2367ABEF_1_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) BA(8-11) BB(8-11) BA(8-11) BB(8-11) BE(8-11) BF(8-11) BE(8-11) BF(8-11) - - const __m512i rhs_mat_014589CD_2_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) B8(16-19) B9(16-19) B8(16-19) B9(16-19) BC(16-19) BD(16-19) BC(16-19) BD(16-19) - const __m512i rhs_mat_2367ABEF_2_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) BA(16-19) BB(16-19) BA(16-19) BB(16-19) BE(16-19) BF(16-19) BE(16-19) BF(16-19) - - const __m512i rhs_mat_014589CD_3_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) B8(24-27) B9(24-27) B8(24-27) B9(24-27) BC(24-27) BD(24-27) BC(24-27) BD(24-27) - const __m512i rhs_mat_2367ABEF_3_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) BA(24-27) BB(24-27) BA(24-27) BB(24-27) BE(24-27) BF(24-27) BE(24-27) BF(24-27) - - // Shuffle pattern two - right side input - - const __m512i rhs_mat_014589CD_0_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_0, (_MM_PERM_ENUM)221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) B8(4-7) B9(4-7) B8(4-7) B9(4-7) BC(4-7) BD(4-7) BC(4-7) BD(4-7) - const __m512i rhs_mat_2367ABEF_0_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_0, (_MM_PERM_ENUM)221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) BA(4-7) BB(4-7) BA(4-7) BB(4-7) BE(4-7) BF(4-7) BE(4-7) BF(4-7) - - const __m512i rhs_mat_014589CD_1_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_1, (_MM_PERM_ENUM)221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) B8(12-15) B9(12-15) B8(12-15) B9(12-15) BC(12-15) BD(12-15) BC(12-15) BD(12-15) - const __m512i rhs_mat_2367ABEF_1_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_1, (_MM_PERM_ENUM)221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) BA(12-15) BB(12-15) BA(12-15) BB(12-15) BE(12-15) BF(12-15) BE(12-15) BF(12-15) - - const __m512i rhs_mat_014589CD_2_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_2, (_MM_PERM_ENUM)221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) B8(20-23) B9(20-23) B8(20-23) B9(20-23) BC(20-23) BD(20-23) BC(20-23) BD(20-23) - const __m512i rhs_mat_2367ABEF_2_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_2, (_MM_PERM_ENUM)221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) BA(20-23) BB(20-23) BA(20-23) BB(20-23) BE(20-23) BF(20-23) BE(20-23) BF(20-23) - - const __m512i rhs_mat_014589CD_3_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_3, (_MM_PERM_ENUM)221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) B8(28-31) B9(28-31) B8(28-31) B9(28-31) BC(28-31) BD(28-31) BC(28-31) BD(28-31) - const __m512i rhs_mat_2367ABEF_3_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_3, (_MM_PERM_ENUM)221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) BA(28-31) BB(28-31) BA(28-31) BB(28-31) BE(28-31) BF(28-31) BE(28-31) BF(28-31) - - - // Scale values - Load the weight scale values of two block_q4_0x8 - const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector - __m256i lhs_mat_ymm_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); - __m256i lhs_mat_ymm_01_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 0); - __m256i lhs_mat_ymm_23_0 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_0, lhs_mat_ymm_0123_0, 17); - __m256i lhs_mat_ymm_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); - __m256i lhs_mat_ymm_01_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 0); - __m256i lhs_mat_ymm_23_1 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_1, lhs_mat_ymm_0123_1, 17); - __m256i lhs_mat_ymm_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); - __m256i lhs_mat_ymm_01_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 0); - __m256i lhs_mat_ymm_23_2 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_2, lhs_mat_ymm_0123_2, 17); - __m256i lhs_mat_ymm_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); - __m256i lhs_mat_ymm_01_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 0); - __m256i lhs_mat_ymm_23_3 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_3, lhs_mat_ymm_0123_3, 17); - - __m512i lhs_mat_01_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_0), lhs_mat_ymm_01_0, 1); - __m512i lhs_mat_23_0 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_0), lhs_mat_ymm_23_0, 1); - __m512i lhs_mat_01_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_1), lhs_mat_ymm_01_1, 1); - __m512i lhs_mat_23_1 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_1), lhs_mat_ymm_23_1, 1); - __m512i lhs_mat_01_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_2), lhs_mat_ymm_01_2, 1); - __m512i lhs_mat_23_2 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_2), lhs_mat_ymm_23_2, 1); - __m512i lhs_mat_01_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_3), lhs_mat_ymm_01_3, 1); - __m512i lhs_mat_23_3 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_3), lhs_mat_ymm_23_3, 1); - - // Shuffle pattern one - left side input - - const __m512i lhs_mat_01_0_sp1 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m512i lhs_mat_23_0_sp1 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m512i lhs_mat_01_1_sp1 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m512i lhs_mat_23_1_sp1 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m512i lhs_mat_01_2_sp1 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m512i lhs_mat_23_2_sp1 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m512i lhs_mat_01_3_sp1 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m512i lhs_mat_23_3_sp1 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) +#if defined(__AVX2__) + // Lookup table to convert signed nibbles to signed bytes + __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + // Shuffle masks to rearrange delta values to multiply with appropriate scales + __m128i deltamask = _mm_set_epi8(15, 14, 7, 6, 13, 12, 5, 4, 11, 10, 3, 2, 9, 8, 1, 0); + // Permute mask used for easier vector processing at later stages + __m256i finalpermutemask = _mm256_set_epi32(7, 5, 3, 1, 6, 4, 2, 0); - // Shuffle pattern two - left side input + const __m256i m3b = _mm256_set1_epi8(3); + const __m128i m4b_sse = _mm_set1_epi8(0xF); - const __m512i lhs_mat_01_0_sp2 = _mm512_shuffle_epi32(lhs_mat_01_0, (_MM_PERM_ENUM)245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m512i lhs_mat_23_0_sp2 = _mm512_shuffle_epi32(lhs_mat_23_0, (_MM_PERM_ENUM)245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + //Mask to get appropriate scales + __m128i scalemask1 = _mm_set_epi8(14,14,6,6,12,12,4,4,10,10,2,2,8,8,0,0); + __m128i scalemask2 = _mm_set_epi8(15,15,7,7,13,13,5,5,11,11,3,3,9,9,1,1); - const __m512i lhs_mat_01_1_sp2 = _mm512_shuffle_epi32(lhs_mat_01_1, (_MM_PERM_ENUM)245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m512i lhs_mat_23_1_sp2 = _mm512_shuffle_epi32(lhs_mat_23_1, (_MM_PERM_ENUM)245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + int64_t b_nb = n / QK_K; - const __m512i lhs_mat_01_2_sp2 = _mm512_shuffle_epi32(lhs_mat_01_2, (_MM_PERM_ENUM)245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m512i lhs_mat_23_2_sp2 = _mm512_shuffle_epi32(lhs_mat_23_2, (_MM_PERM_ENUM)245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + const block_q2_Kx8 * b_ptr_start = (const block_q2_Kx8 *)vx; + const block_q8_K * a_ptr_start = (const block_q8_K *)vy; - const __m512i lhs_mat_01_3_sp2 = _mm512_shuffle_epi32(lhs_mat_01_3, (_MM_PERM_ENUM)245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m512i lhs_mat_23_3_sp2 = _mm512_shuffle_epi32(lhs_mat_23_3, (_MM_PERM_ENUM)245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + // Process Q8_K blocks one by one + for (int64_t y = 0; y < nr; y++) { - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m512i zero = _mm512_setzero_epi32(); - __m512i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_01_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_01_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_01_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_014589CD_3_sp1), lhs_mat_23_2_sp1, rhs_mat_014589CD_2_sp1), lhs_mat_23_1_sp1, rhs_mat_014589CD_1_sp1), lhs_mat_23_0_sp1, rhs_mat_014589CD_0_sp1); - __m512i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp1, rhs_mat_2367ABEF_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367ABEF_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367ABEF_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367ABEF_0_sp1); - __m512i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_01_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_01_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_01_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_01_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367ABEF_0_sp2); - __m512i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_014589CD_3_sp2), lhs_mat_23_2_sp2, rhs_mat_014589CD_2_sp2), lhs_mat_23_1_sp2, rhs_mat_014589CD_1_sp2), lhs_mat_23_0_sp2, rhs_mat_014589CD_0_sp2); - __m512i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(mul_sum_i8_pairs_acc_int32x16(zero, lhs_mat_23_3_sp2, rhs_mat_2367ABEF_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367ABEF_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367ABEF_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367ABEF_0_sp2); + // Pointers to LHS blocks of block_q8_K format + const block_q8_K * a_ptr = a_ptr_start + (y * nb); - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m512i iacc_mat_00 = _mm512_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m512i iacc_mat_01 = _mm512_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m512i iacc_mat_10 = _mm512_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m512i iacc_mat_11 = _mm512_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + // Take group of eight interleaved block_q2_K structures at each pass of the loop and perform dot product operation + for(int64_t x = 0; x < nc / 8; x++) { + // Pointers to RHS blocks + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); - // Straighten out to make 4 row vectors - __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); - __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); - __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); - __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + // Master FP accumulators + __m256 acc_row = _mm256_setzero_ps(); + __m256 acc_min_rows = _mm256_setzero_ps(); - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m128i row_scale_f16 = _mm_shuffle_epi32(_mm_maskload_epi32((int const*)(a_ptr[b].d), loadMask), 68); - const __m512 row_scale_f32 = GGML_F32Cx16_REPEAT_LOAD(row_scale_f16); + for (int64_t b = 0; b < nb; b++) { - // Multiply with appropiate scales and accumulate - acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); - acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); - acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); - acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); - } + // Load and convert to FP32 delta from block_q8_K + const __m256 row_scale_f32 = _mm256_set1_ps((a_ptr[b].d)); - // Store the accumulated values - for (int i = 0; i < 4; i++) { - _mm512_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } - if (anc != nc) { - xstart = anc/8; - y = 0; - } - #endif // __AVX512F__ + // Load the delta values for the 8 blocks interleaved in block_q2_Kx8 + // col_scale_f32 rearranged so as to multiply with appropriate quants + const __m256 col_scale_f32 = GGML_F32Cx8_REARRANGE_LOAD(b_ptr[b].d, deltamask); + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); - // Take group of four block_q8_0x4 structures at each pass of the loop and perform dot product operation + __m256i iacc_b = _mm256_setzero_si256(); + __m256i iacc_min_b = _mm256_setzero_si256(); - for (; y < anr / 4; y += 4) { - const block_q8_0x4 * a_ptrs[4]; + // Processes eight sub blocks from each Q2_K in each iteration + for(int sb = 0; sb < QK_K / 128; sb++) { - a_ptrs[0] = a_ptr_start + (y * nb); - for (int i = 0; i < 3; ++i) { - a_ptrs[i + 1] = a_ptrs[i] + nb; - } + // Load the eight block_q2_K for eight sub blocks quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 + const __m256i rhs_raw_vec_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_vec_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_vec_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_vec_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_vec_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_vec_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_vec_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_vec_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr[b].qs + 224 + sb * 256)); - // Take group of eight block_q4_0x8 structures at each pass of the loop and perform dot product operation - for (int64_t x = xstart; x < nc / 8; x++) { + // 2-bit -> 8-bit + // Values of the 0th,2nd,4th,6th sub blocks of eight block_q2_K structures for the sb loop + const __m256i rhs_vec_0123_00 = _mm256_and_si256(rhs_raw_vec_0123_0, m3b); //B00(0-7) B01(0-7) B02(0-7) B03(0-7) + const __m256i rhs_vec_0123_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 2), m3b); //B20(0-7) B21(0-7) B22(0-7) B23(0-7) + const __m256i rhs_vec_0123_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 4), m3b); //B40(0-7) B41(0-7) B42(0-7) B43(0-7) + const __m256i rhs_vec_0123_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_0, 6), m3b); //B60(0-7) B61(0-7) B62(0-7) B63(0-7) + + const __m256i rhs_vec_4567_00 = _mm256_and_si256(rhs_raw_vec_4567_0, m3b); //B04(0-7) B05(0-7) B06(0-7) B07(0-7) + const __m256i rhs_vec_4567_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 2), m3b); //B24(0-7) B25(0-7) B26(0-7) B27(0-7) + const __m256i rhs_vec_4567_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 4), m3b); //B44(0-7) B45(0-7) B46(0-7) B47(0-7) + const __m256i rhs_vec_4567_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_0, 6), m3b); //B64(0-7) B65(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_vec_0123_01 = _mm256_and_si256(rhs_raw_vec_0123_1, m3b); //B00(8-15) B01(8-15) B02(8-15) B03(8-15) + const __m256i rhs_vec_0123_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 2), m3b); //B20(8-15) B21(8-15) B22(8-15) B23(8-15) + const __m256i rhs_vec_0123_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 4), m3b); //B40(8-15) B41(8-15) B42(8-15) B43(8-15) + const __m256i rhs_vec_0123_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_1, 6), m3b); //B60(8-15) B61(8-15) B62(8-15) B63(8-15) + + const __m256i rhs_vec_4567_01 = _mm256_and_si256(rhs_raw_vec_4567_1, m3b); //B04(8-15) B05(8-15) B06(8-15) B07(8-15) + const __m256i rhs_vec_4567_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 2), m3b); //B24(8-15) B25(8-15) B26(8-15) B27(8-15) + const __m256i rhs_vec_4567_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 4), m3b); //B44(8-15) B45(8-15) B46(8-15) B47(8-15) + const __m256i rhs_vec_4567_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_1, 6), m3b); //B64(8-15) B65(8-15) B66(8-15) B67(8-15) + + // Values of the 1st,3rd,5th,7th sub blocks of eight block_q2_K structures for the sb loop + const __m256i rhs_vec_0123_10 = _mm256_and_si256(rhs_raw_vec_0123_2, m3b); //B10(0-7) B11(0-7) B12(0-7) B13(0-7) + const __m256i rhs_vec_0123_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 2), m3b); //B30(0-7) B31(0-7) B32(0-7) B33(0-7) + const __m256i rhs_vec_0123_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 4), m3b); //B50(0-7) B51(0-7) B52(0-7) B53(0-7) + const __m256i rhs_vec_0123_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_2, 6), m3b); //B70(0-7) B71(0-7) B72(0-7) B73(0-7) + + const __m256i rhs_vec_4567_10 = _mm256_and_si256(rhs_raw_vec_4567_2, m3b); //B14(0-7) B15(0-7) B16(0-7) B17(0-7) + const __m256i rhs_vec_4567_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 2), m3b); //B34(0-7) B35(0-7) B36(0-7) B37(0-7) + const __m256i rhs_vec_4567_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 4), m3b); //B54(0-7) B55(0-7) B56(0-7) B57(0-7) + const __m256i rhs_vec_4567_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_2, 6), m3b); //B74(0-7) B75(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_vec_0123_11 = _mm256_and_si256(rhs_raw_vec_0123_3, m3b); //B10(8-15) B11(8-15) B12(8-15) B13(8-15) + const __m256i rhs_vec_0123_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 2), m3b); //B30(8-15) B31(8-15) B32(8-15) B33(8-15) + const __m256i rhs_vec_0123_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 4), m3b); //B50(8-15) B51(8-15) B52(8-15) B53(8-15) + const __m256i rhs_vec_0123_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_0123_3, 6), m3b); //B70(8-15) B71(8-15) B72(8-15) B73(8-15) + + const __m256i rhs_vec_4567_11 = _mm256_and_si256(rhs_raw_vec_4567_3, m3b); //B14(8-15) B15(8-15) B16(8-15) B17(8-15) + const __m256i rhs_vec_4567_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 2), m3b); //B34(8-15) B35(8-15) B36(8-15) B37(8-15) + const __m256i rhs_vec_4567_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 4), m3b); //B54(8-15) B55(8-15) B56(8-15) B57(8-15) + const __m256i rhs_vec_4567_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_vec_4567_3, 6), m3b); //B74(8-15) B75(8-15) B76(8-15) B77(8-15) + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + // Scales of sub blocks in the sb loop + // Scales of the 0th sub block from each super block + __m128i scales_rearrange_0 = _mm_shuffle_epi8(scales_01, scalemask1); + __m256i scales_0 = _mm256_cvtepu8_epi16(scales_rearrange_0); - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); + // Scales of the 1st sub block from each super block + __m128i scales_rearrange_1 = _mm_shuffle_epi8(scales_01, scalemask2); + __m256i scales_1 = _mm256_cvtepu8_epi16(scales_rearrange_1); - // Master FP accumulators - __m256 acc_rows[16]; - for (int i = 0; i < 16; i++) { - acc_rows[i] = _mm256_setzero_ps(); - } + // Scales of the 2nd sub block from each super block + __m128i scales_rearrange_2 = _mm_shuffle_epi8(scales_23, scalemask1); + __m256i scales_2 = _mm256_cvtepu8_epi16(scales_rearrange_2); + + // Scales of the 3rd sub block from each super block + __m128i scales_rearrange_3 = _mm_shuffle_epi8(scales_23, scalemask2); + __m256i scales_3 = _mm256_cvtepu8_epi16(scales_rearrange_3); + + // Scales of the 4th sub block from each super block + __m128i scales_rearrange_4 = _mm_shuffle_epi8(scales_45, scalemask1); + __m256i scales_4 = _mm256_cvtepu8_epi16(scales_rearrange_4); + + // Scales of the 5th sub block from each super block + __m128i scales_rearrange_5 = _mm_shuffle_epi8(scales_45, scalemask2); + __m256i scales_5 = _mm256_cvtepu8_epi16(scales_rearrange_5); + + // Scales of the 6th sub block from each super block + __m128i scales_rearrange_6 = _mm_shuffle_epi8(scales_67, scalemask1); + __m256i scales_6 = _mm256_cvtepu8_epi16(scales_rearrange_6); + + // Scales of the 7th sub block from each super block + __m128i scales_rearrange_7 = _mm_shuffle_epi8(scales_67, scalemask2); + __m256i scales_7 = _mm256_cvtepu8_epi16(scales_rearrange_7); + + // Load the sub block values corresponding to sb in block_q8_K in batches of 16 bytes and replicate the same across 256 bit vector + __m256i lhs_vec_0 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + sb * 128))); + __m256i lhs_vec_1 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 16 + sb * 128))); + __m256i lhs_vec_2 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 32 + sb * 128))); + __m256i lhs_vec_3 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 48 + sb * 128))); + __m256i lhs_vec_4 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 64 + sb * 128))); + __m256i lhs_vec_5 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 80 + sb * 128))); + __m256i lhs_vec_6 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 96 + sb * 128))); + __m256i lhs_vec_7 = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i *)(a_ptr[b].qs + 112 + sb * 128))); + + lhs_vec_0 = _mm256_permute2f128_si256(lhs_vec_0, lhs_vec_0, 0); + lhs_vec_1 = _mm256_permute2f128_si256(lhs_vec_1, lhs_vec_1, 0); + lhs_vec_2 = _mm256_permute2f128_si256(lhs_vec_2, lhs_vec_2, 0); + lhs_vec_3 = _mm256_permute2f128_si256(lhs_vec_3, lhs_vec_3, 0); + lhs_vec_4 = _mm256_permute2f128_si256(lhs_vec_4, lhs_vec_4, 0); + lhs_vec_5 = _mm256_permute2f128_si256(lhs_vec_5, lhs_vec_5, 0); + lhs_vec_6 = _mm256_permute2f128_si256(lhs_vec_6, lhs_vec_6, 0); + lhs_vec_7 = _mm256_permute2f128_si256(lhs_vec_7, lhs_vec_7, 0); - for (int64_t b = 0; b < nb; b++) { - // Load the eight block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); + __m256i iacc_0 = _mm256_setzero_si256(); + __m256i iacc_1 = _mm256_setzero_si256(); + __m256i iacc_2 = _mm256_setzero_si256(); + __m256i iacc_3 = _mm256_setzero_si256(); + __m256i iacc_4 = _mm256_setzero_si256(); + __m256i iacc_5 = _mm256_setzero_si256(); + __m256i iacc_6 = _mm256_setzero_si256(); + __m256i iacc_7 = _mm256_setzero_si256(); - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + // Dot product done within 32 bit lanes and accumulated in the same vector + // First done for 0th sub block and then for seven (1st - 7th) other sub blocks processed for each sb (sb < QK_K/128 loop) // B0(0-3) B4(0-3) B1(0-3) B5(0-3) B2(0-3) B6(0-3) B3(0-3) B7(0-3) with A0(0-3) + // B0(4-7) B4(4-7) B1(4-7) B5(4-7) B2(4-7) B6(4-7) B3(4-7) B7(4-7) with A0(4-7) + // B0(8-11) B4(8-11) B1(8-11) B5(8-11) B2(8-11) B6(8-11) B3(8-11) B7(8-11) with A0(8-11) + // B0(12-15) B4(12-15) B1(12-15) B5(12-15) B2(12-15) B6(12-15) B3(12-15) B7(12-15) with A0(12-15) - // 4-bit -> 8-bit - Sign is maintained - const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) - const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_00 ,_mm256_shuffle_epi32(rhs_vec_4567_00, 177), 170), _mm256_shuffle_epi32(lhs_vec_0, 0))); + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_00, 177) ,rhs_vec_4567_00, 170), _mm256_shuffle_epi32(lhs_vec_0, 85))); - const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) - const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_01 ,_mm256_shuffle_epi32(rhs_vec_4567_01, 177), 170), _mm256_shuffle_epi32(lhs_vec_0, 170))); + iacc_0 = _mm256_add_epi16(iacc_0, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_01, 177) ,rhs_vec_4567_01, 170), _mm256_shuffle_epi32(lhs_vec_0, 255))); - const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) - const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) + iacc_0 = _mm256_madd_epi16(iacc_0, scales_0); - const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) - const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_10 ,_mm256_shuffle_epi32(rhs_vec_4567_10, 177), 170), _mm256_shuffle_epi32(lhs_vec_1, 0))); + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_10, 177) ,rhs_vec_4567_10, 170), _mm256_shuffle_epi32(lhs_vec_1, 85))); - // Shuffle pattern one - right side input - const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) - const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_11 ,_mm256_shuffle_epi32(rhs_vec_4567_11, 177), 170), _mm256_shuffle_epi32(lhs_vec_1, 170))); + iacc_1 = _mm256_add_epi16(iacc_1, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_11, 177) ,rhs_vec_4567_11, 170), _mm256_shuffle_epi32(lhs_vec_1, 255))); - const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) - const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) + iacc_1 = _mm256_madd_epi16(iacc_1, scales_1); - const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) - const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_20 ,_mm256_shuffle_epi32(rhs_vec_4567_20, 177), 170), _mm256_shuffle_epi32(lhs_vec_2, 0))); + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_20, 177) ,rhs_vec_4567_20, 170), _mm256_shuffle_epi32(lhs_vec_2, 85))); - const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) - const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_21 ,_mm256_shuffle_epi32(rhs_vec_4567_21, 177), 170), _mm256_shuffle_epi32(lhs_vec_2, 170))); + iacc_2 = _mm256_add_epi16(iacc_2, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_21, 177) ,rhs_vec_4567_21, 170), _mm256_shuffle_epi32(lhs_vec_2, 255))); - // Shuffle pattern two - right side input + iacc_2 = _mm256_madd_epi16(iacc_2, scales_2); - const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) - const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_30 ,_mm256_shuffle_epi32(rhs_vec_4567_30, 177), 170), _mm256_shuffle_epi32(lhs_vec_3, 0))); + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_30, 177) ,rhs_vec_4567_30, 170), _mm256_shuffle_epi32(lhs_vec_3, 85))); - const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) - const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_31 ,_mm256_shuffle_epi32(rhs_vec_4567_31, 177), 170), _mm256_shuffle_epi32(lhs_vec_3, 170))); + iacc_3 = _mm256_add_epi16(iacc_3, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_31, 177) ,rhs_vec_4567_31, 170), _mm256_shuffle_epi32(lhs_vec_3, 255))); - const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) - const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) + iacc_3 = _mm256_madd_epi16(iacc_3, scales_3); - const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) - const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_40 ,_mm256_shuffle_epi32(rhs_vec_4567_40, 177), 170), _mm256_shuffle_epi32(lhs_vec_4, 0))); + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_40, 177) ,rhs_vec_4567_40, 170), _mm256_shuffle_epi32(lhs_vec_4, 85))); - // Scale values - Load the wight scale values of block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_41 ,_mm256_shuffle_epi32(rhs_vec_4567_41, 177), 170), _mm256_shuffle_epi32(lhs_vec_4, 170))); + iacc_4 = _mm256_add_epi16(iacc_4, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_41, 177) ,rhs_vec_4567_41, 170), _mm256_shuffle_epi32(lhs_vec_4, 255))); - // Process LHS in groups of four - for (int rp = 0; rp < 4; rp++) { - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated into a 256 bit vector - __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs))); - __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); - __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); - __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 32))); - __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); - __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); - __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 64))); - __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); - __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); - __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptrs[rp][b].qs + 96))); - __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); - __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); + iacc_4 = _mm256_madd_epi16(iacc_4, scales_4); - // Shuffle pattern one - left side input - const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_50 ,_mm256_shuffle_epi32(rhs_vec_4567_50, 177), 170), _mm256_shuffle_epi32(lhs_vec_5, 0))); + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_50, 177) ,rhs_vec_4567_50, 170), _mm256_shuffle_epi32(lhs_vec_5, 85))); - const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_51 ,_mm256_shuffle_epi32(rhs_vec_4567_51, 177), 170), _mm256_shuffle_epi32(lhs_vec_5, 170))); + iacc_5 = _mm256_add_epi16(iacc_5, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_51, 177) ,rhs_vec_4567_51, 170), _mm256_shuffle_epi32(lhs_vec_5, 255))); - const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) + iacc_5 = _mm256_madd_epi16(iacc_5, scales_5); - const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_60 ,_mm256_shuffle_epi32(rhs_vec_4567_60, 177), 170), _mm256_shuffle_epi32(lhs_vec_6, 0))); + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_60, 177) ,rhs_vec_4567_60, 170), _mm256_shuffle_epi32(lhs_vec_6, 85))); - // Shuffle pattern two - left side input - const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_61 ,_mm256_shuffle_epi32(rhs_vec_4567_61, 177), 170), _mm256_shuffle_epi32(lhs_vec_6, 170))); + iacc_6 = _mm256_add_epi16(iacc_6, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_61, 177) ,rhs_vec_4567_61, 170), _mm256_shuffle_epi32(lhs_vec_6, 255))); - const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) + iacc_6 = _mm256_madd_epi16(iacc_6, scales_6); - const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_70 ,_mm256_shuffle_epi32(rhs_vec_4567_70, 177), 170), _mm256_shuffle_epi32(lhs_vec_7, 0))); + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_70, 177) ,rhs_vec_4567_70, 170), _mm256_shuffle_epi32(lhs_vec_7, 85))); - const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(rhs_vec_0123_71 ,_mm256_shuffle_epi32(rhs_vec_4567_71, 177), 170), _mm256_shuffle_epi32(lhs_vec_7, 170))); + iacc_7 = _mm256_add_epi16(iacc_7, _mm256_maddubs_epi16(_mm256_blend_epi32(_mm256_shuffle_epi32(rhs_vec_0123_71, 177) ,rhs_vec_4567_71, 170), _mm256_shuffle_epi32(lhs_vec_7, 255))); - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m256i zero = _mm256_setzero_si256(); - __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); - __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); + iacc_7 = _mm256_madd_epi16(iacc_7, scales_7); - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); + // Accumulate the iacc value for one sb + __m256i iacc_sb = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_0, iacc_1), _mm256_add_epi32(iacc_2, iacc_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_4, iacc_5), _mm256_add_epi32(iacc_6, iacc_7))); - // Straighten out to make 4 row vectors - __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); - __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); - __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); - __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + __m128i q8sums = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + sb * 8)); + __m256i q8s = _mm256_castsi128_si256(q8sums); + q8s= _mm256_permute2f128_si256(q8s, q8s, 0); + + // Broadcast the bsums of the two corresponding subblocks of q8_k + // Multiply-Add with corresponding mins of Q2_Kx8 with bsums + __m256i iacc_min_sb_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 0), mins_01); + __m256i iacc_min_sb_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 85), mins_23); + __m256i iacc_min_sb_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 170), mins_45); + __m256i iacc_min_sb_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(q8s, 255), mins_67); - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptrs[rp][b].d, loadMask); + __m256i iacc_min_sb = _mm256_add_epi32(_mm256_add_epi32(iacc_min_sb_01, iacc_min_sb_23), _mm256_add_epi32(iacc_min_sb_45,iacc_min_sb_67)); - // Multiply with appropiate scales and accumulate - acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); - acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); - acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); - acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); - } + // Accumulate for the complete block + iacc_b = _mm256_add_epi32(iacc_b, iacc_sb); + iacc_min_b = _mm256_add_epi32(iacc_min_b, iacc_min_sb); } - // Store the accumulated values - for (int i = 0; i < 16; i++) { - _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } + //Multiply-Add with scale values for complete super block + acc_row = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_b), _mm256_mul_ps(col_scale_f32, row_scale_f32), acc_row); + acc_min_rows = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_min_b), _mm256_mul_ps(col_dmin_f32, row_scale_f32), acc_min_rows); } + // Accumulated output values permuted so as to be stored in appropriate order post accumulation + acc_row = _mm256_permutevar8x32_ps(acc_row, finalpermutemask); + _mm256_storeu_ps(s + (y * nr + x * 8), _mm256_sub_ps(acc_row, acc_min_rows)); } + } +#else - // Take a block_q8_0x4 structures at each pass of the loop and perform dot product operation - for (; y < nr / 4; y ++) { - - const block_q8_0x4 * a_ptr = a_ptr_start + (y * nb); - - // Load the eight block_q4_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - for (int64_t x = xstart; x < nc / 8; x++) { - - const block_q4_0x8 * b_ptr = b_ptr_start + (x * b_nb); - - // Master FP accumulators - __m256 acc_rows[4]; - for (int i = 0; i < 4; i++) { - acc_rows[i] = _mm256_setzero_ps(); - } - - for (int64_t b = 0; b < nb; b++) { - // Load the eight block_q8_0 quantized values interleaved with each other in chunks of eight - B0,B1 ....B6,B7 - const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs)); - const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32)); - const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64)); - const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96)); - - // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of valuess - const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); - const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); - const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); - - // 4-bit -> 8-bit - Sign is maintained - const __m256i rhs_mat_0145_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_0, m4b)); //B0(0-7) B1(0-7) B4(0-7) B5(0-7) - const __m256i rhs_mat_2367_0 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_0, m4b)); //B2(0-7) B3(0-7) B6(0-7) B7(0-7) - - const __m256i rhs_mat_0145_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_0145_1, m4b)); //B0(8-15) B1(8-15) B4(8-15) B5(8-15) - const __m256i rhs_mat_2367_1 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(rhs_raw_mat_2367_1, m4b)); //B2(8-15) B3(8-15) B6(8-15) B7(8-15) - - const __m256i rhs_mat_0145_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m4b)); //B0(16-23) B1(16-23) B4(16-23) B5(16-23) - const __m256i rhs_mat_2367_2 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m4b)); //B2(16-23) B3(16-23) B6(16-23) B7(16-23) - - const __m256i rhs_mat_0145_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m4b)); //B0(24-31) B1(24-31) B4(24-31) B5(24-31) - const __m256i rhs_mat_2367_3 = _mm256_shuffle_epi8(signextendlut, _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m4b)); //B2(24-31) B3(24-31) B6(24-31) B7(24-31) - - // Shuffle pattern one - right side input - const __m256i rhs_mat_0145_0_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_0, 136); //B0(0-3) B1(0-3) B0(0-3) B1(0-3) B4(0-3) B5(0-3) B4(0-3) B5(0-3) - const __m256i rhs_mat_2367_0_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_0, 136); //B2(0-3) B3(0-3) B2(0-3) B3(0-3) B6(0-3) B7(0-3) B6(0-3) B7(0-3) - - const __m256i rhs_mat_0145_1_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_1, 136); //B0(8-11) B1(8-11) B0(8-11) B1(8-11) B4(8-11) B5(8-11) B4(8-11) B5(8-11) - const __m256i rhs_mat_2367_1_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_1, 136); //B2(8-11) B3(8-11) B2(8-11) B3(8-11) B6(8-11) B7(8-11) B6(8-11) B7(8-11) - - const __m256i rhs_mat_0145_2_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_2, 136); //B0(16-19) B1(16-19) B0(16-19) B1(16-19) B4(16-19) B5(16-19) B4(16-19) B5(16-19) - const __m256i rhs_mat_2367_2_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_2, 136); //B2(16-19) B3(16-19) B2(16-19) B3(16-19) B6(16-19) B7(16-19) B6(16-19) B7(16-19) - - const __m256i rhs_mat_0145_3_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_3, 136); //B0(24-27) B1(24-27) B0(24-27) B1(24-27) B4(24-27) B5(24-27) B4(24-27) B5(24-27) - const __m256i rhs_mat_2367_3_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_3, 136); //B2(24-27) B3(24-27) B2(24-27) B3(24-27) B6(24-27) B7(24-27) B6(24-27) B7(24-27) - - // Shuffle pattern two - right side input - - const __m256i rhs_mat_0145_0_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_0, 221); //B0(4-7) B1(4-7) B0(4-7) B1(4-7) B4(4-7) B5(4-7) B4(4-7) B5(4-7) - const __m256i rhs_mat_2367_0_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_0, 221); //B2(4-7) B3(4-7) B2(4-7) B3(4-7) B6(4-7) B7(4-7) B6(4-7) B7(4-7) - - const __m256i rhs_mat_0145_1_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_1, 221); //B0(12-15) B1(12-15) B0(12-15) B1(12-15) B4(12-15) B5(12-15) B4(12-15) B5(12-15) - const __m256i rhs_mat_2367_1_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_1, 221); //B2(12-15) B3(12-15) B2(12-15) B3(12-15) B6(12-15) B7(12-15) B6(12-15) B7(12-15) - - const __m256i rhs_mat_0145_2_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_2, 221); //B0(20-23) B1(20-23) B0(20-23) B1(20-23) B4(20-23) B5(20-23) B4(20-23) B5(20-23) - const __m256i rhs_mat_2367_2_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_2, 221); //B2(20-23) B3(20-23) B2(20-23) B3(20-23) B6(20-23) B7(20-23) B6(20-23) B7(20-23) - - const __m256i rhs_mat_0145_3_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_3, 221); //B0(28-31) B1(28-31) B0(28-31) B1(28-31) B4(28-31) B5(28-31) B4(28-31) B5(28-31) - const __m256i rhs_mat_2367_3_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_3, 221); //B2(28-31) B3(28-31) B2(28-31) B3(28-31) B6(28-31) B7(28-31) B6(28-31) B7(28-31) - - // Scale values - Load the wight scale values of block_q4_0x8 - const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); - - // Load the four block_q4_0 quantized values interleaved with each other in chunks of eight - A0,A1,A2,A3 - // Loaded as set of 128 bit vectors and repeated into a 256 bit vector - __m256i lhs_mat_0123_0 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs))); - __m256i lhs_mat_01_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 0); - __m256i lhs_mat_23_0 = _mm256_permute2f128_si256(lhs_mat_0123_0, lhs_mat_0123_0, 17); - __m256i lhs_mat_0123_1 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 32))); - __m256i lhs_mat_01_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 0); - __m256i lhs_mat_23_1 = _mm256_permute2f128_si256(lhs_mat_0123_1, lhs_mat_0123_1, 17); - __m256i lhs_mat_0123_2 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 64))); - __m256i lhs_mat_01_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 0); - __m256i lhs_mat_23_2 = _mm256_permute2f128_si256(lhs_mat_0123_2, lhs_mat_0123_2, 17); - __m256i lhs_mat_0123_3 = _mm256_loadu_si256((const __m256i *)((a_ptr[b].qs + 96))); - __m256i lhs_mat_01_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 0); - __m256i lhs_mat_23_3 = _mm256_permute2f128_si256(lhs_mat_0123_3, lhs_mat_0123_3, 17); - - // Shuffle pattern one - left side input - - const __m256i lhs_mat_01_0_sp1 = _mm256_shuffle_epi32(lhs_mat_01_0, 160); //A0(0-3) A0(0-3) A1(0-3) A1(0-3) A0(0-3) A0(0-3) A1(0-3) A1(0-3) - const __m256i lhs_mat_23_0_sp1 = _mm256_shuffle_epi32(lhs_mat_23_0, 160); //A2(0-3) A2(0-3) A3(0-3) A3(0-3) A2(0-3) A2(0-3) A3(0-3) A3(0-3) - - const __m256i lhs_mat_01_1_sp1 = _mm256_shuffle_epi32(lhs_mat_01_1, 160); //A0(8-11) A0(8-11) A1(8-11) A1(8-11) A0(8-11) A0(8-11) A1(8-11) A1(8-11) - const __m256i lhs_mat_23_1_sp1 = _mm256_shuffle_epi32(lhs_mat_23_1, 160); //A2(8-11) A2(8-11) A3(8-11) A3(8-11) A2(8-11) A2(8-11) A3(8-11) A3(8-11) - - const __m256i lhs_mat_01_2_sp1 = _mm256_shuffle_epi32(lhs_mat_01_2, 160); //A0(16-19) A0(16-19) A1(16-19) A1(16-19) A0(16-19) A0(16-19) A1(16-19) A1(16-19) - const __m256i lhs_mat_23_2_sp1 = _mm256_shuffle_epi32(lhs_mat_23_2, 160); //A2(16-19) A2(16-19) A3(16-19) A3(16-19) A2(16-19) A2(16-19) A3(16-19) A3(16-19) - - const __m256i lhs_mat_01_3_sp1 = _mm256_shuffle_epi32(lhs_mat_01_3, 160); //A0(24-27) A0(24-27) A1(24-27) A1(24-27) A0(24-27) A0(24-27) A1(24-27) A1(24-27) - const __m256i lhs_mat_23_3_sp1 = _mm256_shuffle_epi32(lhs_mat_23_3, 160); //A2(24-27) A2(24-27) A3(24-27) A3(24-27) A2(24-27) A2(24-27) A3(24-27) A3(24-27) - - // Shuffle pattern two - left side input - - const __m256i lhs_mat_01_0_sp2 = _mm256_shuffle_epi32(lhs_mat_01_0, 245); //A0(4-7) A0(4-7) A1(4-7) A1(4-7) A0(4-7) A0(4-7) A1(4-7) A1(4-7) - const __m256i lhs_mat_23_0_sp2 = _mm256_shuffle_epi32(lhs_mat_23_0, 245); //A2(4-7) A2(4-7) A3(4-7) A3(4-7) A2(4-7) A2(4-7) A3(4-7) A3(4-7) - - const __m256i lhs_mat_01_1_sp2 = _mm256_shuffle_epi32(lhs_mat_01_1, 245); //A0(12-15) A0(12-15) A1(12-15) A1(12-15) A0(12-15) A0(12-15) A1(12-15) A1(12-15) - const __m256i lhs_mat_23_1_sp2 = _mm256_shuffle_epi32(lhs_mat_23_1, 245); //A2(12-15) A2(12-15) A3(12-15) A3(12-15) A2(12-15) A2(12-15) A3(12-15) A3(12-15) - - const __m256i lhs_mat_01_2_sp2 = _mm256_shuffle_epi32(lhs_mat_01_2, 245); //A0(20-23) A0(20-23) A1(20-23) A1(20-23) A0(20-23) A0(20-23) A1(20-23) A1(20-23) - const __m256i lhs_mat_23_2_sp2 = _mm256_shuffle_epi32(lhs_mat_23_2, 245); //A2(20-23) A2(20-23) A3(20-23) A3(20-23) A2(20-23) A2(20-23) A3(20-23) A3(20-23) - - const __m256i lhs_mat_01_3_sp2 = _mm256_shuffle_epi32(lhs_mat_01_3, 245); //A0(28-31) A0(28-31) A1(28-31) A1(28-31) A0(28-31) A0(28-31) A1(28-31) A1(28-31) - const __m256i lhs_mat_23_3_sp2 = _mm256_shuffle_epi32(lhs_mat_23_3, 245); //A2(28-31) A2(28-31) A3(28-31) A3(28-31) A2(28-31) A2(28-31) A3(28-31) A3(28-31) - - // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane - // Resembles MMLAs into 2x2 matrices in ARM Version - const __m256i zero = _mm256_setzero_si256(); - __m256i iacc_mat_00_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_01_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_01_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_01_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_01_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_01_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_01_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_01_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_10_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_0145_3_sp1), lhs_mat_23_2_sp1, rhs_mat_0145_2_sp1), lhs_mat_23_1_sp1, rhs_mat_0145_1_sp1), lhs_mat_23_0_sp1, rhs_mat_0145_0_sp1); - __m256i iacc_mat_11_sp1 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp1, rhs_mat_2367_3_sp1), lhs_mat_23_2_sp1, rhs_mat_2367_2_sp1), lhs_mat_23_1_sp1, rhs_mat_2367_1_sp1), lhs_mat_23_0_sp1, rhs_mat_2367_0_sp1); - __m256i iacc_mat_00_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_01_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_01_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_01_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_01_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_01_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_01_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_01_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_01_0_sp2, rhs_mat_2367_0_sp2); - __m256i iacc_mat_10_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_0145_3_sp2), lhs_mat_23_2_sp2, rhs_mat_0145_2_sp2), lhs_mat_23_1_sp2, rhs_mat_0145_1_sp2), lhs_mat_23_0_sp2, rhs_mat_0145_0_sp2); - __m256i iacc_mat_11_sp2 = mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(mul_sum_i8_pairs_acc_int32x8(zero, lhs_mat_23_3_sp2, rhs_mat_2367_3_sp2), lhs_mat_23_2_sp2, rhs_mat_2367_2_sp2), lhs_mat_23_1_sp2, rhs_mat_2367_1_sp2), lhs_mat_23_0_sp2, rhs_mat_2367_0_sp2); - - // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block - __m256i iacc_mat_00 = _mm256_add_epi32(iacc_mat_00_sp1, iacc_mat_00_sp2); - __m256i iacc_mat_01 = _mm256_add_epi32(iacc_mat_01_sp1, iacc_mat_01_sp2); - __m256i iacc_mat_10 = _mm256_add_epi32(iacc_mat_10_sp1, iacc_mat_10_sp2); - __m256i iacc_mat_11 = _mm256_add_epi32(iacc_mat_11_sp1, iacc_mat_11_sp2); - + ggml_gemv_q2_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); - // Straighten out to make 4 row vectors - __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); - __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); - __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); - __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); +#endif +} - // Load the scale(d) values for all the 4 Q8_0 blocks and repeat it across lanes - const __m256 row_scale_f32 = GGML_F32Cx8_REPEAT_LOAD(a_ptr[b].d, loadMask); +void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) || defined(__AVX512F__) + { + // Lookup table to convert signed nibbles to signed bytes + __m256i signextendlut = _mm256_castsi128_si256(_mm_set_epi8(-1, -2, -3, -4, -5, -6, -7, -8, 7, 6, 5, 4, 3, 2, 1, 0)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); - // Multiply with appropiate scales and accumulate - acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); - acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); - acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); - acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); - } + gemm_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); - // Store the accumulated values - for (int i = 0; i < 4; i++) { - _mm256_storeu_ps((float *)(s + ((y * 4 + i) * bs + x * 8)), acc_rows[i]); - } - } - } return; } +#endif // defined(__AVX2__) || defined(__AVX512F__) -#endif // #if ! ((defined(_MSC_VER)) && ! defined(__clang__)) && defined(__aarch64__) - float sumf[4][8]; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; - } - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + - (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])) >> 4; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); - } - } - } - } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; - } - } - } + ggml_gemm_q4_0_8x8_q8_0_generic(n, s, bs, vx, vy, nr, nc); } void ggml_gemm_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { @@ -3216,70 +3401,2907 @@ void ggml_gemm_q4_K_8x8_q8_K(int n, floa } #else + UNUSED(kmask1); + UNUSED(kmask2); + UNUSED(kmask3); + ggml_gemm_q4_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); +#endif +} - float sumf[4][8]; - float sum_minf[4][8]; - uint32_t utmp[32]; - int sumi1; - int sumi2; - int sumi; - - for (int y = 0; y < nr / 4; y++) { - const block_q8_Kx4 * a_ptr = (const block_q8_Kx4 *) vy + (y * nb); - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_Kx8 * b_ptr = (const block_q4_Kx8 *) vx + (x * nb); - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumf[m][j] = 0.0; - sum_minf[m][j] = 0.0; - } +void ggml_gemm_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { +#if defined(__AVX2__) || defined(__AVX512F__) + { + __m256i signextendlut = _mm256_castsi128_si256(_mm_loadu_si128((const __m128i*)kvalues_iq4nl)); + signextendlut = _mm256_permute2f128_si256(signextendlut, signextendlut, 0); + + gemm_q4_b32_8x8_q8_0_lut_avx(n, s, bs, vx, vy, nr, nc, signextendlut); + + return; + } +#endif // defined(__AVX2__) || defined(__AVX512F__) + + ggml_gemm_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); +} + +void ggml_gemm_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert (n % qk == 0); + assert (nr % 4 == 0); + assert (nc % ncols_interleaved == 0); + + UNUSED(s); + UNUSED(bs); + UNUSED(vx); + UNUSED(vy); + UNUSED(nr); + UNUSED(nc); + UNUSED(nb); + UNUSED(ncols_interleaved); + UNUSED(blocklen); + +#if defined(__AVX2__) || defined(__AVX512F__) + const block_q2_Kx8 * b_ptr_start = (const block_q2_Kx8 * ) vx; + const block_q8_Kx4 * a_ptr_start = (const block_q8_Kx4 * ) vy; + int64_t b_nb = n / QK_K; + int64_t y = 0; + + // Permute mask used for easier vector processing at later stages + __m256i requiredOrder = _mm256_set_epi32(3, 2, 1, 0, 7, 6, 5, 4); + int64_t xstart = 0; + int anr = nr - nr % 16; // Used to align nr with boundary of 16 + + // Mask to convert 2 bit and 4 bit values into a bytes + const __m256i m3b = _mm256_set1_epi8(3); + const __m128i m4b_sse = _mm_set1_epi8(0xF); + + //Mask to get appropriate scales + __m128i scalesmask1_sse = _mm_set_epi8(14,14,12,12,10,10,8,8,6,6,4,4,2,2,0,0); + __m128i scalesmask2_sse = _mm_set_epi8(15,15,13,13,11,11,9,9,7,7,5,5,3,3,1,1); + + __m256i scalesmask1 = _mm256_castsi128_si256(scalesmask1_sse); + scalesmask1 = _mm256_permute2f128_si256(scalesmask1, scalesmask1, 0); + __m256i scalesmask2 = _mm256_castsi128_si256(scalesmask2_sse); + scalesmask2 = _mm256_permute2f128_si256(scalesmask2, scalesmask2, 0); + +#ifdef __AVX512F__ + + int anc = nc - nc % 16; // Used to align nc with boundary of 16 + + // Mask to mask out nibbles from packed bytes + const __m256i m4b = _mm256_set1_epi8(0x0F); + // Mask to mask out nibbles from packed bytes expanded to 512 bit length + const __m512i m3bexpanded = _mm512_set1_epi8(3); + //Take group of four block_q8_Kx4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_Kx4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_q2_Kx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_q2_Kx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm512_setzero_ps(); } - for (int l = 0; l < nb; l++) { - for (int sb = 0; sb < 8; sb++) { - memcpy(utmp + sb * 4, b_ptr[l].scales + sb * 12, 12); - utmp[sb * 4 + 3] = ((utmp[sb * 4 + 2] >> 4) & kmask2) | (((utmp[sb * 4 + 1] >> 6) & kmask3) << 4); - const uint32_t uaux_0 = utmp[sb * 4 + 1] & kmask1; - utmp[sb * 4 + 1] = (utmp[sb * 4 + 2] & kmask2) | (((utmp[sb * 4 + 0] >> 6) & kmask3) << 4); - utmp[sb * 4 + 2] = uaux_0; - utmp[sb * 4 + 0] &= kmask1; - } - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - uint8_t *scales_0 = (uint8_t*) utmp + (k / 4) * 32; - uint8_t *scales_1 = (uint8_t*) utmp + (k / 4) * 32 + 16; - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi1 = 0; - sumi2 = 0; - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4); - sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 256 + (k % 4) * 4 * blocklen + m * blocklen + i]); - sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 256 + (k % 4) * 4 * blocklen + m * blocklen + i + 128]); - sumi1 = sumi1 * scales_0[j]; - sumi2 = sumi2 * scales_1[j]; - sumi += sumi1 + sumi2; - } - sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d[m]; - } + + __m512 acc_min_rows[16]; + for (int i = 0; i < 16; i++) { + acc_min_rows[i] = _mm512_setzero_ps(); + } + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the sixteen scale values from two block_q2_kx8 structures + const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + + // dmin values - Load the sixteen dmin values from two block_q2_kx8 structures + const __m512 col_dmin_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].dmin, b_ptr_1[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + sb * 256)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_89AB_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_89AB_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + const __m256i rhs_raw_mat_89CD_2 = _mm256_blend_epi32(rhs_raw_mat_89AB_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_2, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_2, requiredOrder), rhs_raw_mat_CDEF_2, 240); + const __m256i rhs_raw_mat_89CD_3 = _mm256_blend_epi32(rhs_raw_mat_89AB_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_3, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_3, requiredOrder), rhs_raw_mat_CDEF_3, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + const __m512i rhs_raw_mat_014589CD_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_2), rhs_raw_mat_89CD_2, 1); + const __m512i rhs_raw_mat_2367ABEF_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_2), rhs_raw_mat_ABEF_2, 1); + const __m512i rhs_raw_mat_014589CD_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_3), rhs_raw_mat_89CD_3, 1); + const __m512i rhs_raw_mat_2367ABEF_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_3), rhs_raw_mat_ABEF_3, 1); + + //2-bit -> 8-bit + const __m512i rhs_mat_014589CD_00 = _mm512_and_si512(rhs_raw_mat_014589CD_0,m3bexpanded); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) B08(0-7) B09(0-7) B0C(0-7) B0D(0-7) + const __m512i rhs_mat_2367ABEF_00 = _mm512_and_si512(rhs_raw_mat_2367ABEF_0,m3bexpanded); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) B0A(0-7) B0B(0-7) B0E(0-7) B0F(0-7) + const __m512i rhs_mat_014589CD_01 = _mm512_and_si512(rhs_raw_mat_014589CD_1,m3bexpanded); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) B08(8-15) B09(8-15) B0C(8-15) B0D(8-15) + const __m512i rhs_mat_2367ABEF_01 = _mm512_and_si512(rhs_raw_mat_2367ABEF_1,m3bexpanded); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) B0A(8-15) B0B(8-15) B0E(8-15) B0F(8-15) + const __m512i rhs_mat_014589CD_10 = _mm512_and_si512(rhs_raw_mat_014589CD_2,m3bexpanded); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) B18(0-7) B19(0-7) B1C(0-7) B1D(0-7) + const __m512i rhs_mat_2367ABEF_10 = _mm512_and_si512(rhs_raw_mat_2367ABEF_2,m3bexpanded); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) B1A(0-7) B1B(0-7) B1E(0-7) B1F(0-7) + const __m512i rhs_mat_014589CD_11 = _mm512_and_si512(rhs_raw_mat_014589CD_3,m3bexpanded); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) B18(8-15) B19(8-15) B1C(8-15) B1D(8-15) + const __m512i rhs_mat_2367ABEF_11 = _mm512_and_si512(rhs_raw_mat_2367ABEF_3,m3bexpanded); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) B1A(8-15) B1B(8-15) B1E(8-15) B1F(8-15) + + const __m512i rhs_mat_014589CD_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 2), m3bexpanded); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) B28(0-7) B29(0-7) B2C(0-7) B2D(0-7) + const __m512i rhs_mat_2367ABEF_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 2), m3bexpanded); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) B2A(0-7) B2B(0-7) B2E(0-7) B2F(0-7) + + const __m512i rhs_mat_014589CD_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 2), m3bexpanded); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) B28(8-15) B29(8-15) B2C(8-15) B2D(8-15) + const __m512i rhs_mat_2367ABEF_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 2), m3bexpanded); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) B2A(8-15) B2B(8-15) B2E(8-15) B2F(8-15) + + const __m512i rhs_mat_014589CD_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 2), m3bexpanded); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) B38(0-7) B39(0-7) B3C(0-7) B3D(0-7) + const __m512i rhs_mat_2367ABEF_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 2), m3bexpanded); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) B3A(0-7) B3B(0-7) B3E(0-7) B3F(0-7) + + const __m512i rhs_mat_014589CD_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 2), m3bexpanded); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) B38(8-15) B39(8-15) B3C(8-15) B3D(8-15) + const __m512i rhs_mat_2367ABEF_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 2), m3bexpanded); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) B3A(8-15) B3B(8-15) B3E(8-15) B3F(8-15) + + const __m512i rhs_mat_014589CD_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m3bexpanded); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) B48(0-7) B49(0-7) B4C(0-7) B4D(0-7) + const __m512i rhs_mat_2367ABEF_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m3bexpanded); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) B4A(0-7) B4B(0-7) B4E(0-7) B4F(0-7) + + const __m512i rhs_mat_014589CD_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m3bexpanded); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) B48(8-15) B49(8-15) B4C(8-15) B4D(8-15) + const __m512i rhs_mat_2367ABEF_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m3bexpanded); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) B4A(8-15) B4B(8-15) B4E(8-15) B4F(8-15) + + const __m512i rhs_mat_014589CD_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 4), m3bexpanded); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) B58(0-7) B59(0-7) B5C(0-7) B5D(0-7) + const __m512i rhs_mat_2367ABEF_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 4), m3bexpanded); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) B5A(0-7) B5B(0-7) B5E(0-7) B5F(0-7) + + const __m512i rhs_mat_014589CD_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 4), m3bexpanded); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) B58(8-15) B59(8-15) B5C(8-15) B5D(8-15) + const __m512i rhs_mat_2367ABEF_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 4), m3bexpanded); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) B5A(8-15) B5B(8-15) B5E(8-15) B5F(8-15) + + const __m512i rhs_mat_014589CD_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 6), m3bexpanded); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) B68(0-7) B69(0-7) B6C(0-7) B6D(0-7) + const __m512i rhs_mat_2367ABEF_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 6), m3bexpanded); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) B6A(0-7) B6B(0-7) B6E(0-7) B6F(0-7) + + const __m512i rhs_mat_014589CD_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 6), m3bexpanded); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) B68(8-15) B69(8-15) B6C(8-15) B6D(8-15) + const __m512i rhs_mat_2367ABEF_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 6), m3bexpanded); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) B6A(8-15) B6B(8-15) B6E(8-15) B6F(8-15) + + const __m512i rhs_mat_014589CD_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 6), m3bexpanded); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) B78(0-7) B79(0-7) B7C(0-7) B7D(0-7) + const __m512i rhs_mat_2367ABEF_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 6), m3bexpanded); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) B7A(0-7) B7B(0-7) B7E(0-7) B7F(0-7) + + const __m512i rhs_mat_014589CD_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 6), m3bexpanded); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) B78(8-15) B79(8-15) B7C(8-15) B7D(8-15) + const __m512i rhs_mat_2367ABEF_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 6), m3bexpanded); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) B7A(8-15) B7B(8-15) B7E(8-15) B7F(8-15) + + const __m512i rhs_mat_014589CD_00_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) B08(0-3) B09(0-3) B08(0-3) B09(0-3) B0C(0-3) B0D(0-3) B0C(0-3) B0D(0-3) + const __m512i rhs_mat_2367ABEF_00_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) B0A(0-3) B0B(0-3) B0A(0-3) B0B(0-3) B0E(0-3) B0F(0-3) B0E(0-3) B0F(0-3) + + const __m512i rhs_mat_014589CD_01_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_01_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) B0A(8-11) B0B(8-11) B0A(8-11) B0B(8-11) B0E(8-11) B0F(8-11) B0E(8-11) B0F(8-11) + + const __m512i rhs_mat_014589CD_10_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) B18(0-3) B19(0-3) B18(0-3) B19(0-3) B1C(0-3) B1D(0-3) B1C(0-3) B1D(0-3) + const __m512i rhs_mat_2367ABEF_10_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) B1A(0-3) B1B(0-3) B1A(0-3) B1B(0-3) B1E(0-3) B1F(0-3) B1E(0-3) B1F(0-3) + + const __m512i rhs_mat_014589CD_11_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) B18(8-11) B19(8-11) B18(8-11) B19(8-11) B1C(8-11) B1D(8-11) B1C(8-11) B1D(8-11) + const __m512i rhs_mat_2367ABEF_11_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) B1A(8-11) B1B(8-11) B1A(8-11) B1B(8-11) B1E(8-11) B1F(8-11) B1E(8-11) B1F(8-11) + + const __m512i rhs_mat_014589CD_20_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) B28(0-3) B29(0-3) B28(0-3) B29(0-3) B2C(0-3) B2D(0-3) B2C(0-3) B2D(0-3) + const __m512i rhs_mat_2367ABEF_20_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) B2A(0-3) B2B(0-3) B2A(0-3) B2B(0-3) B2E(0-3) B2F(0-3) B2E(0-3) B2F(0-3) + + const __m512i rhs_mat_014589CD_21_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) B28(8-11) B29(8-11) B28(8-11) B29(8-11) B2C(8-11) B2D(8-11) B2C(8-11) B2D(8-11) + const __m512i rhs_mat_2367ABEF_21_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) B2A(8-11) B2B(8-11) B2A(8-11) B2B(8-11) B2E(8-11) B2F(8-11) B2E(8-11) B2F(8-11) + + const __m512i rhs_mat_014589CD_30_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)136); ///B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) B38(0-3) B39(0-3) B38(0-3) B39(0-3) B3C(0-3) B3D(0-3) B3C(0-3) B3D(0-3) + const __m512i rhs_mat_2367ABEF_30_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) B3A(0-3) B3B(0-3) B3A(0-3) B3B(0-3) B3E(0-3) B3F(0-3) B3E(0-3) B3F(0-3) + + const __m512i rhs_mat_014589CD_31_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11) B38(8-11) B39(8-11) B38(8-11) B39(8-11) B3C(8-11) B3D(8-11) B3C(8-11) B3D(8-11) + const __m512i rhs_mat_2367ABEF_31_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) B3A(8-11) B3B(8-11) B3A(8-11) B3B(8-11) B3E(8-11) B3F(8-11) B3E(8-11) B3F(8-11) + + const __m512i rhs_mat_014589CD_40_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) B48(0-3) B49(0-3) B48(0-3) B49(0-3) B4C(0-3) B4D(0-3) B4C(0-3) B4D(0-3) + const __m512i rhs_mat_2367ABEF_40_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) B4A(0-3) B4B(0-3) B4A(0-3) B4B(0-3) B4E(0-3) B4F(0-3) B4E(0-3) B4F(0-3) + + const __m512i rhs_mat_014589CD_41_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) B48(8-11) B49(8-11) B48(8-11) B49(8-11) B4C(8-11) B4D(8-11) B4C(8-11) B4D(8-11) + const __m512i rhs_mat_2367ABEF_41_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) B4A(8-11) B4B(8-11) B4A(8-11) B4B(8-11) B4E(8-11) B4F(8-11) B4E(8-11) B4F(8-11) + + const __m512i rhs_mat_014589CD_50_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) B58(0-3) B59(0-3) B58(0-3) B59(0-3) B5C(0-3) B5D(0-3) B5C(0-3) B5D(0-3) + const __m512i rhs_mat_2367ABEF_50_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) B5A(0-3) B5B(0-3) B5A(0-3) B5B(0-3) B5E(0-3) B5F(0-3) B5E(0-3) B5F(0-3) + + const __m512i rhs_mat_014589CD_51_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) B58(8-11) B59(8-11) B58(8-11) B59(8-11) B5C(8-11) B5D(8-11) B5C(8-11) B5D(8-11) + const __m512i rhs_mat_2367ABEF_51_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) B5A(8-11) B5B(8-11) B5A(8-11) B5B(8-11) B5E(8-11) B5F(8-11) B5E(8-11) B5F(8-11) + + const __m512i rhs_mat_014589CD_60_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) B68(0-3) B69(0-3) B68(0-3) B69(0-3) B6C(0-3) B6D(0-3) B6C(0-3) B6D(0-3) + const __m512i rhs_mat_2367ABEF_60_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) B6A(0-3) B6B(0-3) B6A(0-3) B6B(0-3) B6E(0-3) B6F(0-3) B6E(0-3) B6F(0-3) + + const __m512i rhs_mat_014589CD_61_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) B68(8-11) B69(8-11) B68(8-11) B69(8-11) B6C(8-11) B6D(8-11) B6C(8-11) B6D(8-11) + const __m512i rhs_mat_2367ABEF_61_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) B6A(8-11) B6B(8-11) B6A(8-11) B6B(8-11) B6E(8-11) B6F(8-11) B6E(8-11) B6F(8-11) + + const __m512i rhs_mat_014589CD_70_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) B78(0-3) B79(0-3) B78(0-3) B79(0-3) B7C(0-3) B7D(0-3) B7C(0-3) B7D(0-3) + const __m512i rhs_mat_2367ABEF_70_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) B7A(0-3) B7B(0-3) B7A(0-3) B7B(0-3) B7E(0-3) B7F(0-3) B7E(0-3) B7F(0-3) + + const __m512i rhs_mat_014589CD_71_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_71_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) B7A(8-11) B7B(8-11) B7A(8-11) B7B(8-11) B7E(8-11) B7F(8-11) B7E(8-11) B7F(8-11) + + const __m512i rhs_mat_014589CD_00_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) B08(4-7) B09(4-7) B08(4-7) B09(4-7) B0C(4-7) B0D(4-7) B0C(4-7) B0D(4-7) + const __m512i rhs_mat_2367ABEF_00_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) B0A(4-7) B0B(4-7) B0A(4-7) B0B(4-7) B0E(4-7) B0F(4-7) B0E(4-7) B0F(4-7) + + const __m512i rhs_mat_014589CD_01_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) B08(12-15) B09(12-15) B08(12-15) B09(12-15) B0C(12-15) B0D(12-15) B0C(12-15) B0D(12-15) + const __m512i rhs_mat_2367ABEF_01_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) B0A(12-15) B0B(12-15) B0A(12-15) B0B(12-15) B0E(12-15) B0F(12-15) B0E(12-15) B0F(12-15) + + const __m512i rhs_mat_014589CD_10_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) B18(4-7) B19(4-7) B18(4-7) B19(4-7) B1C(4-7) B1D(4-7) B1C(4-7) B1D(4-7) + const __m512i rhs_mat_2367ABEF_10_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) B1A(4-7) B1B(4-7) B1A(4-7) B1B(4-7) B1E(4-7) B1F(4-7) B1E(4-7) B1F(4-7) + + const __m512i rhs_mat_014589CD_11_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) B18(12-15) B19(12-15) B18(12-15) B19(12-15) B1C(12-15) B1D(12-15) B1C(12-15) B1D(12-15) + const __m512i rhs_mat_2367ABEF_11_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) B1A(12-15) B1B(12-15) B1A(12-15) B1B(12-15) B1E(12-15) B1F(12-15) B1E(12-15) B1F(12-15) + + const __m512i rhs_mat_014589CD_20_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) B28(4-7) B29(4-7) B28(4-7) B29(4-7) B2C(4-7) B2D(4-7) B2C(4-7) B2D(4-7) + const __m512i rhs_mat_2367ABEF_20_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) B2A(4-7) B2B(4-7) B2A(4-7) B2B(4-7) B2E(4-7) B2F(4-7) B2E(4-7) B2F(4-7) + + const __m512i rhs_mat_014589CD_21_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) B28(12-15) B29(12-15) B28(12-15) B29(12-15) B2C(12-15) B2D(12-15) B2C(12-15) B2D(12-15) + const __m512i rhs_mat_2367ABEF_21_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) B2A(12-15) B2B(12-15) B2A(12-15) B2B(12-15) B2E(12-15) B2F(12-15) B2E(12-15) B2F(12-15) + + const __m512i rhs_mat_014589CD_30_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) B38(4-7) B39(4-7) B38(4-7) B39(4-7) B3C(4-7) B3D(4-7) B3C(4-7) B3D(4-7) + const __m512i rhs_mat_2367ABEF_30_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) B3A(4-7) B3B(4-7) B3A(4-7) B3B(4-7) B3E(4-7) B3F(4-7) B3E(4-7) B3F(4-7) + + const __m512i rhs_mat_014589CD_31_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) B38(12-15) B39(12-15) B38(12-15) B39(12-15) B3C(12-15) B3D(12-15) B3C(12-15) B3D(12-15) + const __m512i rhs_mat_2367ABEF_31_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) B3A(12-15) B3B(12-15) B3A(12-15) B3B(12-15) B3E(12-15) B3F(12-15) B3E(12-15) B3F(12-15) + + const __m512i rhs_mat_014589CD_40_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) B48(4-7) B49(4-7) B48(4-7) B49(4-7) B4C(4-7) B4D(4-7) B4C(4-7) B4D(4-7) + const __m512i rhs_mat_2367ABEF_40_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) B4A(4-7) B4B(4-7) B4A(4-7) B4B(4-7) B4E(4-7) B4F(4-7) B4E(4-7) B4F(4-7) + + const __m512i rhs_mat_014589CD_41_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) B48(12-15) B49(12-15) B48(12-15) B49(12-15) B4C(12-15) B4D(12-15) B4C(12-15) B4D(12-15) + const __m512i rhs_mat_2367ABEF_41_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) B4A(12-15) B4B(12-15) B4A(12-15) B4B(12-15) B4E(12-15) B4F(12-15) B4E(12-15) B4F(12-15) + + const __m512i rhs_mat_014589CD_50_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) B58(4-7) B59(4-7) B58(4-7) B59(4-7) B5C(4-7) B5D(4-7) B5C(4-7) B5D(4-7) + const __m512i rhs_mat_2367ABEF_50_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) B5A(4-7) B5B(4-7) B5A(4-7) B5B(4-7) B5E(4-7) B5F(4-7) B5E(4-7) B5F(4-7) + + const __m512i rhs_mat_014589CD_51_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) B58(12-15) B59(12-15) B58(12-15) B59(12-15) B5C(12-15) B5D(12-15) B5C(12-15) B5D(12-15) + const __m512i rhs_mat_2367ABEF_51_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) B5A(12-15) B5B(12-15) B5A(12-15) B5B(12-15) B5E(12-15) B5F(12-15) B5E(12-15) B5F(12-15) + + const __m512i rhs_mat_014589CD_60_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) B68(4-7) B69(4-7) B68(4-7) B69(4-7) B6C(4-7) B6D(4-7) B6C(4-7) B6D(4-7) + const __m512i rhs_mat_2367ABEF_60_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) B6A(4-7) B6B(4-7) B6A(4-7) B6B(4-7) B6E(4-7) B6F(4-7) B6E(4-7) B6F(4-7) + + const __m512i rhs_mat_014589CD_61_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) B68(12-15) B69(12-15) B68(12-15) B69(12-15) B6C(12-15) B6D(12-15) B6C(12-15) B6D(12-15) + const __m512i rhs_mat_2367ABEF_61_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) B6A(12-15) B6B(12-15) B6A(12-15) B6B(12-15) B6E(12-15) B6F(12-15) B6E(12-15) B6F(12-15) + + const __m512i rhs_mat_014589CD_70_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) B78(4-7) B79(4-7) B78(4-7) B79(4-7) B7C(4-7) B7D(4-7) B7C(4-7) B7D(4-7) + const __m512i rhs_mat_2367ABEF_70_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) B7A(4-7) B7B(4-7) B7A(4-7) B7B(4-7) B7E(4-7) B7F(4-7) B7E(4-7) B7F(4-7) + + const __m512i rhs_mat_014589CD_71_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) B78(12-15) B79(12-15) B78(12-15) B79(12-15) B7C(12-15) B7D(12-15) B7C(12-15) B7D(12-15) + const __m512i rhs_mat_2367ABEF_71_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) B7A(12-15) B7B(12-15) B7A(12-15) B7B(12-15) B7E(12-15) B7F(12-15) B7E(12-15) B7F(12-15) + + //notation:superblock subblock + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + sb * 64)); + const __m128i mins_and_scales_23_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 48 + sb * 64)); + + const __m128i mins_and_scales_01_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + sb * 64)); + const __m128i mins_and_scales_23_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 48 + sb * 64)); + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m256i mins_and_scales_01 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_01_0), mins_and_scales_01_1, 1); + const __m256i mins_and_scales_23 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_23_0), mins_and_scales_23_1, 1); + const __m256i mins_and_scales_45 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_45_0), mins_and_scales_45_1, 1); + const __m256i mins_and_scales_67 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_67_0), mins_and_scales_67_1, 1); + + // Extract scales which is lower half from mins_and_scales + const __m256i scales_01 = _mm256_and_si256(mins_and_scales_01, m4b); + const __m256i scales_23 = _mm256_and_si256(mins_and_scales_23, m4b); + const __m256i scales_45 = _mm256_and_si256(mins_and_scales_45, m4b); + const __m256i scales_67 = _mm256_and_si256(mins_and_scales_67, m4b); + + // Extract mins which is upper half from mins_and_scales + const __m512i mins_01 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_01, 4), m4b)); + const __m512i mins_23 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_23, 4), m4b)); + const __m512i mins_45 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_45, 4), m4b)); + const __m512i mins_67 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_67, 4), m4b)); + + const __m512i scales_0 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01,scalesmask1)); + const __m512i scales_1 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01,scalesmask2)); + const __m512i scales_2 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23,scalesmask1)); + const __m512i scales_3 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23,scalesmask2)); + const __m512i scales_4 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45,scalesmask1)); + const __m512i scales_5 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45,scalesmask2)); + const __m512i scales_6 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67,scalesmask1)); + const __m512i scales_7 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67,scalesmask2)); + + const __m512i scale_014589CD_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)238); + + + for (int rp = 0; rp < 4; rp++) { + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated and stored into a 256 bit vector before again repeating into 512 bit vector + __m256i lhs_mat_ymm_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 512 * sb))); + __m256i lhs_mat_ymm_01_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 0); + __m256i lhs_mat_ymm_23_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 17); + __m256i lhs_mat_ymm_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 32 + 512 * sb))); + __m256i lhs_mat_ymm_01_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 0); + __m256i lhs_mat_ymm_23_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 17); + __m256i lhs_mat_ymm_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 64 + 512 * sb))); + __m256i lhs_mat_ymm_01_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 0); + __m256i lhs_mat_ymm_23_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 17); + __m256i lhs_mat_ymm_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 96 + 512 * sb))); + __m256i lhs_mat_ymm_01_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 0); + __m256i lhs_mat_ymm_23_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 17); + __m256i lhs_mat_ymm_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 128 + 512 * sb))); + __m256i lhs_mat_ymm_01_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 0); + __m256i lhs_mat_ymm_23_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 17); + __m256i lhs_mat_ymm_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 160 + 512 * sb))); + __m256i lhs_mat_ymm_01_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 0); + __m256i lhs_mat_ymm_23_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 17); + __m256i lhs_mat_ymm_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 192 + 512 * sb))); + __m256i lhs_mat_ymm_01_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 0); + __m256i lhs_mat_ymm_23_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 17); + __m256i lhs_mat_ymm_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 224 + 512 * sb))); + __m256i lhs_mat_ymm_01_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 0); + __m256i lhs_mat_ymm_23_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 17); + + __m256i lhs_mat_ymm_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 256 + 512 * sb))); + __m256i lhs_mat_ymm_01_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 0); + __m256i lhs_mat_ymm_23_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 17); + __m256i lhs_mat_ymm_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 288 + 512 * sb))); + __m256i lhs_mat_ymm_01_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 0); + __m256i lhs_mat_ymm_23_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 17); + __m256i lhs_mat_ymm_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 320 + 512 * sb))); + __m256i lhs_mat_ymm_01_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 0); + __m256i lhs_mat_ymm_23_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 17); + __m256i lhs_mat_ymm_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 352 + 512 * sb))); + __m256i lhs_mat_ymm_01_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 0); + __m256i lhs_mat_ymm_23_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 17); + __m256i lhs_mat_ymm_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 384 + 512 * sb))); + __m256i lhs_mat_ymm_01_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 0); + __m256i lhs_mat_ymm_23_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 17); + __m256i lhs_mat_ymm_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 416 + 512 * sb))); + __m256i lhs_mat_ymm_01_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 0); + __m256i lhs_mat_ymm_23_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 17); + __m256i lhs_mat_ymm_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 448 + 512 * sb))); + __m256i lhs_mat_ymm_01_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 0); + __m256i lhs_mat_ymm_23_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 17); + __m256i lhs_mat_ymm_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 480 + 512 * sb))); + __m256i lhs_mat_ymm_01_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 0); + __m256i lhs_mat_ymm_23_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 17); + + + __m512i lhs_mat_01_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_00), lhs_mat_ymm_01_00, 1); + __m512i lhs_mat_23_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_00), lhs_mat_ymm_23_00, 1); + __m512i lhs_mat_01_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_01), lhs_mat_ymm_01_01, 1); + __m512i lhs_mat_23_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_01), lhs_mat_ymm_23_01, 1); + + __m512i lhs_mat_01_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_10), lhs_mat_ymm_01_10, 1); + __m512i lhs_mat_23_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_10), lhs_mat_ymm_23_10, 1); + __m512i lhs_mat_01_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_11), lhs_mat_ymm_01_11, 1); + __m512i lhs_mat_23_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_11), lhs_mat_ymm_23_11, 1); + + __m512i lhs_mat_01_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_20), lhs_mat_ymm_01_20, 1); + __m512i lhs_mat_23_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_20), lhs_mat_ymm_23_20, 1); + __m512i lhs_mat_01_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_21), lhs_mat_ymm_01_21, 1); + __m512i lhs_mat_23_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_21), lhs_mat_ymm_23_21, 1); + + __m512i lhs_mat_01_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_30), lhs_mat_ymm_01_30, 1); + __m512i lhs_mat_23_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_30), lhs_mat_ymm_23_30, 1); + __m512i lhs_mat_01_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_31), lhs_mat_ymm_01_31, 1); + __m512i lhs_mat_23_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_31), lhs_mat_ymm_23_31, 1); + + __m512i lhs_mat_01_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_40), lhs_mat_ymm_01_40, 1); + __m512i lhs_mat_23_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_40), lhs_mat_ymm_23_40, 1); + __m512i lhs_mat_01_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_41), lhs_mat_ymm_01_41, 1); + __m512i lhs_mat_23_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_41), lhs_mat_ymm_23_41, 1); + + __m512i lhs_mat_01_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_50), lhs_mat_ymm_01_50, 1); + __m512i lhs_mat_23_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_50), lhs_mat_ymm_23_50, 1); + __m512i lhs_mat_01_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_51), lhs_mat_ymm_01_51, 1); + __m512i lhs_mat_23_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_51), lhs_mat_ymm_23_51, 1); + + __m512i lhs_mat_01_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_60), lhs_mat_ymm_01_60, 1); + __m512i lhs_mat_23_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_60), lhs_mat_ymm_23_60, 1); + __m512i lhs_mat_01_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_61), lhs_mat_ymm_01_61, 1); + __m512i lhs_mat_23_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_61), lhs_mat_ymm_23_61, 1); + + __m512i lhs_mat_01_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_70), lhs_mat_ymm_01_70, 1); + __m512i lhs_mat_23_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_70), lhs_mat_ymm_23_70, 1); + __m512i lhs_mat_01_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_71), lhs_mat_ymm_01_71, 1); + __m512i lhs_mat_23_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_71), lhs_mat_ymm_23_71, 1); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 24 + 32 * sb)); + + __m256i lhs_bsums_ymm_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m512i lhs_bsums_01_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_0123), lhs_bsums_ymm_01_0123, 1); + __m256i lhs_bsums_ymm_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m512i lhs_bsums_23_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_0123), lhs_bsums_ymm_23_0123, 1); __m256i lhs_bsums_ymm_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m512i lhs_bsums_01_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_4567), lhs_bsums_ymm_01_4567, 1); + __m256i lhs_bsums_ymm_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + __m512i lhs_bsums_23_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_4567), lhs_bsums_ymm_23_4567, 1); + + // Shuffle pattern one - left side input + const __m512i lhs_mat_01_00_sp1 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m512i lhs_mat_23_00_sp1 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)160); //A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) + + const __m512i lhs_mat_01_01_sp1 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m512i lhs_mat_23_01_sp1 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)160); //A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) + + const __m512i lhs_mat_01_10_sp1 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m512i lhs_mat_23_10_sp1 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)160); //A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) + + const __m512i lhs_mat_01_11_sp1 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m512i lhs_mat_23_11_sp1 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)160); //A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) + + const __m512i lhs_mat_01_20_sp1 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m512i lhs_mat_23_20_sp1 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)160); //A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) + + const __m512i lhs_mat_01_21_sp1 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m512i lhs_mat_23_21_sp1 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)160); //A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) + + const __m512i lhs_mat_01_30_sp1 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m512i lhs_mat_23_30_sp1 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)160); //A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) + + const __m512i lhs_mat_01_31_sp1 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m512i lhs_mat_23_31_sp1 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)160); //A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) + + const __m512i lhs_mat_01_40_sp1 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m512i lhs_mat_23_40_sp1 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)160); //A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) + + const __m512i lhs_mat_01_41_sp1 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m512i lhs_mat_23_41_sp1 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)160); //A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) + + const __m512i lhs_mat_01_50_sp1 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m512i lhs_mat_23_50_sp1 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)160); //A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) + + const __m512i lhs_mat_01_51_sp1 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m512i lhs_mat_23_51_sp1 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)160); //A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) + + const __m512i lhs_mat_01_60_sp1 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m512i lhs_mat_23_60_sp1 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)160); //A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) + + const __m512i lhs_mat_01_61_sp1 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m512i lhs_mat_23_61_sp1 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)160); //A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) + + const __m512i lhs_mat_01_70_sp1 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m512i lhs_mat_23_70_sp1 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)160); //A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) + + const __m512i lhs_mat_01_71_sp1 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m512i lhs_mat_23_71_sp1 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)160); //A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) + + const __m512i lhs_mat_01_00_sp2 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m512i lhs_mat_23_00_sp2 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)245); //A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) + + const __m512i lhs_mat_01_01_sp2 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m512i lhs_mat_23_01_sp2 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)245); //A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) + + const __m512i lhs_mat_01_10_sp2 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m512i lhs_mat_23_10_sp2 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)245); //A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) + + const __m512i lhs_mat_01_11_sp2 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m512i lhs_mat_23_11_sp2 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)245); //A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) + + const __m512i lhs_mat_01_20_sp2 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m512i lhs_mat_23_20_sp2 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)245); //A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) + + const __m512i lhs_mat_01_21_sp2 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m512i lhs_mat_23_21_sp2 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)245); //A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) + + const __m512i lhs_mat_01_30_sp2 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m512i lhs_mat_23_30_sp2 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)245); //A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) + + const __m512i lhs_mat_01_31_sp2 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m512i lhs_mat_23_31_sp2 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)245); //A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) + + const __m512i lhs_mat_01_40_sp2 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m512i lhs_mat_23_40_sp2 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)245); //A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) + + const __m512i lhs_mat_01_41_sp2 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m512i lhs_mat_23_41_sp2 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)245); //A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) + + const __m512i lhs_mat_01_50_sp2 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m512i lhs_mat_23_50_sp2 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)245); //A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) + + const __m512i lhs_mat_01_51_sp2 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m512i lhs_mat_23_51_sp2 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)245); //A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) + + const __m512i lhs_mat_01_60_sp2 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m512i lhs_mat_23_60_sp2 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)245); //A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) + + const __m512i lhs_mat_01_61_sp2 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m512i lhs_mat_23_61_sp2 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)245); //A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) + + const __m512i lhs_mat_01_70_sp2 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m512i lhs_mat_23_70_sp2 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)245); //A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) + + const __m512i lhs_mat_01_71_sp2 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m512i lhs_mat_23_71_sp2 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)245); //A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m512i iacc_mat_00_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_01_01_sp1)); + __m512i iacc_mat_01_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_01_01_sp1)); + + __m512i iacc_mat_10_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_23_01_sp1)); + __m512i iacc_mat_11_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_23_01_sp1)); + + __m512i iacc_mat_00_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_01_11_sp1)); + __m512i iacc_mat_01_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_01_11_sp1)); + + __m512i iacc_mat_10_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_23_11_sp1)); + __m512i iacc_mat_11_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_23_11_sp1)); + + __m512i iacc_mat_00_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_01_21_sp1)); + __m512i iacc_mat_01_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_01_21_sp1)); + + __m512i iacc_mat_10_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_23_21_sp1)); + __m512i iacc_mat_11_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_23_21_sp1)); + + __m512i iacc_mat_00_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_01_31_sp1)); + __m512i iacc_mat_01_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_01_31_sp1)); + + __m512i iacc_mat_10_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_23_31_sp1)); + __m512i iacc_mat_11_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_23_31_sp1)); + + __m512i iacc_mat_00_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_01_41_sp1)); + __m512i iacc_mat_01_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_01_41_sp1)); + + __m512i iacc_mat_10_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_23_41_sp1)); + __m512i iacc_mat_11_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_23_41_sp1)); + + __m512i iacc_mat_00_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_01_51_sp1)); + __m512i iacc_mat_01_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_01_51_sp1)); + + __m512i iacc_mat_10_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_23_51_sp1)); + __m512i iacc_mat_11_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_23_51_sp1)); + + __m512i iacc_mat_00_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_01_61_sp1)); + __m512i iacc_mat_01_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_01_61_sp1)); + + __m512i iacc_mat_10_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_23_61_sp1)); + __m512i iacc_mat_11_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_23_61_sp1)); + + __m512i iacc_mat_00_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_01_71_sp1)); + __m512i iacc_mat_01_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_01_71_sp1)); + + __m512i iacc_mat_10_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_23_71_sp1)); + __m512i iacc_mat_11_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_23_71_sp1)); + + + __m512i iacc_mat_00_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_01_01_sp2)); + __m512i iacc_mat_01_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_01_01_sp2)); + + __m512i iacc_mat_10_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_23_01_sp2)); + __m512i iacc_mat_11_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_23_01_sp2)); + + __m512i iacc_mat_00_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_01_11_sp2)); + __m512i iacc_mat_01_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_01_11_sp2)); + + __m512i iacc_mat_10_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_23_11_sp2)); + __m512i iacc_mat_11_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_23_11_sp2)); + + __m512i iacc_mat_00_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_01_21_sp2)); + __m512i iacc_mat_01_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_01_21_sp2)); + + __m512i iacc_mat_10_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_23_21_sp2)); + __m512i iacc_mat_11_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_23_21_sp2)); + + __m512i iacc_mat_00_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_01_31_sp2)); + __m512i iacc_mat_01_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_01_31_sp2)); + + __m512i iacc_mat_10_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_23_31_sp2)); + __m512i iacc_mat_11_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_23_31_sp2)); + + __m512i iacc_mat_00_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_01_41_sp2)); + __m512i iacc_mat_01_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_01_41_sp2)); + + __m512i iacc_mat_10_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_23_41_sp2)); + __m512i iacc_mat_11_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_23_41_sp2)); + + __m512i iacc_mat_00_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_01_51_sp2)); + __m512i iacc_mat_01_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_01_51_sp2)); + + __m512i iacc_mat_10_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_23_51_sp2)); + __m512i iacc_mat_11_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_23_51_sp2)); + + __m512i iacc_mat_00_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_01_61_sp2)); + __m512i iacc_mat_01_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_01_61_sp2)); + + __m512i iacc_mat_10_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_23_61_sp2)); + __m512i iacc_mat_11_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_23_61_sp2)); + + __m512i iacc_mat_00_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_01_71_sp2)); + __m512i iacc_mat_01_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_01_71_sp2)); + + __m512i iacc_mat_10_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_23_71_sp2)); + __m512i iacc_mat_11_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m512i iacc_mat_00_0 = _mm512_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m512i iacc_mat_01_0 = _mm512_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m512i iacc_mat_10_0 = _mm512_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m512i iacc_mat_11_0 = _mm512_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m512i iacc_mat_00_1 = _mm512_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m512i iacc_mat_01_1 = _mm512_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m512i iacc_mat_10_1 = _mm512_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m512i iacc_mat_11_1 = _mm512_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m512i iacc_mat_00_2 = _mm512_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m512i iacc_mat_01_2 = _mm512_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m512i iacc_mat_10_2 = _mm512_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m512i iacc_mat_11_2 = _mm512_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m512i iacc_mat_00_3 = _mm512_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m512i iacc_mat_01_3 = _mm512_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m512i iacc_mat_10_3 = _mm512_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m512i iacc_mat_11_3 = _mm512_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m512i iacc_mat_00_4 = _mm512_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m512i iacc_mat_01_4 = _mm512_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m512i iacc_mat_10_4 = _mm512_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m512i iacc_mat_11_4 = _mm512_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m512i iacc_mat_00_5 = _mm512_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m512i iacc_mat_01_5 = _mm512_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m512i iacc_mat_10_5 = _mm512_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m512i iacc_mat_11_5 = _mm512_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m512i iacc_mat_00_6 = _mm512_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m512i iacc_mat_01_6 = _mm512_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m512i iacc_mat_10_6 = _mm512_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m512i iacc_mat_11_6 = _mm512_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m512i iacc_mat_00_7 = _mm512_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m512i iacc_mat_01_7 = _mm512_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m512i iacc_mat_10_7 = _mm512_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m512i iacc_mat_11_7 = _mm512_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm512_madd_epi16(iacc_mat_00_0, scale_014589CD_0); + iacc_mat_01_0 = _mm512_madd_epi16(iacc_mat_01_0, scale_2367ABEF_0); + iacc_mat_10_0 = _mm512_madd_epi16(iacc_mat_10_0, scale_014589CD_0); + iacc_mat_11_0 = _mm512_madd_epi16(iacc_mat_11_0, scale_2367ABEF_0); + + iacc_mat_00_1 = _mm512_madd_epi16(iacc_mat_00_1, scale_014589CD_1); + iacc_mat_01_1 = _mm512_madd_epi16(iacc_mat_01_1, scale_2367ABEF_1); + iacc_mat_10_1 = _mm512_madd_epi16(iacc_mat_10_1, scale_014589CD_1); + iacc_mat_11_1 = _mm512_madd_epi16(iacc_mat_11_1, scale_2367ABEF_1); + + iacc_mat_00_2 = _mm512_madd_epi16(iacc_mat_00_2, scale_014589CD_2); + iacc_mat_01_2 = _mm512_madd_epi16(iacc_mat_01_2, scale_2367ABEF_2); + iacc_mat_10_2 = _mm512_madd_epi16(iacc_mat_10_2, scale_014589CD_2); + iacc_mat_11_2 = _mm512_madd_epi16(iacc_mat_11_2, scale_2367ABEF_2); + + iacc_mat_00_3 = _mm512_madd_epi16(iacc_mat_00_3, scale_014589CD_3); + iacc_mat_01_3 = _mm512_madd_epi16(iacc_mat_01_3, scale_2367ABEF_3); + iacc_mat_10_3 = _mm512_madd_epi16(iacc_mat_10_3, scale_014589CD_3); + iacc_mat_11_3 = _mm512_madd_epi16(iacc_mat_11_3, scale_2367ABEF_3); + + iacc_mat_00_4 = _mm512_madd_epi16(iacc_mat_00_4, scale_014589CD_4); + iacc_mat_01_4 = _mm512_madd_epi16(iacc_mat_01_4, scale_2367ABEF_4); + iacc_mat_10_4 = _mm512_madd_epi16(iacc_mat_10_4, scale_014589CD_4); + iacc_mat_11_4 = _mm512_madd_epi16(iacc_mat_11_4, scale_2367ABEF_4); + + iacc_mat_00_5 = _mm512_madd_epi16(iacc_mat_00_5, scale_014589CD_5); + iacc_mat_01_5 = _mm512_madd_epi16(iacc_mat_01_5, scale_2367ABEF_5); + iacc_mat_10_5 = _mm512_madd_epi16(iacc_mat_10_5, scale_014589CD_5); + iacc_mat_11_5 = _mm512_madd_epi16(iacc_mat_11_5, scale_2367ABEF_5); + + iacc_mat_00_6 = _mm512_madd_epi16(iacc_mat_00_6, scale_014589CD_6); + iacc_mat_01_6 = _mm512_madd_epi16(iacc_mat_01_6, scale_2367ABEF_6); + iacc_mat_10_6 = _mm512_madd_epi16(iacc_mat_10_6, scale_014589CD_6); + iacc_mat_11_6 = _mm512_madd_epi16(iacc_mat_11_6, scale_2367ABEF_6); + + iacc_mat_00_7 = _mm512_madd_epi16(iacc_mat_00_7, scale_014589CD_7); + iacc_mat_01_7 = _mm512_madd_epi16(iacc_mat_01_7, scale_2367ABEF_7); + iacc_mat_10_7 = _mm512_madd_epi16(iacc_mat_10_7, scale_014589CD_7); + iacc_mat_11_7 = _mm512_madd_epi16(iacc_mat_11_7, scale_2367ABEF_7); + + __m512i iacc_mat_00 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm512_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm512_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m512i iacc_mat_01 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm512_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm512_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m512i iacc_mat_10 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm512_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm512_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m512i iacc_mat_11 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm512_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm512_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptrs[rp][b].d); + const __m256 row_scale_f32_ymm = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + const __m512 row_scale_f32 = _mm512_insertf32x8(_mm512_castps256_ps512(row_scale_f32_ymm), row_scale_f32_ymm, 1); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m512i iacc_row_min_0_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_1_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)170), mins_01); + __m512i iacc_row_min_2_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_3_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)170), mins_01); + + __m512i iacc_row_min_0_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_1_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)255), mins_23); + __m512i iacc_row_min_2_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_3_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)255), mins_23); + + __m512i iacc_row_min_0_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_1_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)170), mins_45); + __m512i iacc_row_min_2_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_3_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)170), mins_45); + + __m512i iacc_row_min_0_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_1_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)255), mins_67); + __m512i iacc_row_min_2_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_3_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)255), mins_67); + + __m512i iacc_row_min_0 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm512_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m512i iacc_row_min_1 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm512_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m512i iacc_row_min_2 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm512_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m512i iacc_row_min_3 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm512_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[rp * 4] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_0), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[rp * 4]); + acc_min_rows[rp * 4 + 1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_1), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[rp * 4 + 1]); + acc_min_rows[rp * 4 + 2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_2), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[rp * 4 + 2]); + acc_min_rows[rp * 4 + 3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_3), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[rp * 4 + 3]); } } - for (int sb = 0; sb < 8; sb++) { - uint8_t *mins = (uint8_t*) utmp + 8 + sb * 16; - for(int m = 0; m < 4; m++) { - const int16_t *bsums = a_ptr[l].bsums + (sb * 8) + (m * 4) - ((sb % 2) * 6); - for(int j = 0; j < ncols_interleaved; j++) { - sum_minf[m][j] += mins[j] * (bsums[0] + bsums[1]) * GGML_CPU_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d[m]; - } + } + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm512_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm512_sub_ps(acc_rows[i], acc_min_rows[i])); + } + } + } + + for (; y < nr / 4; y ++) { + + const block_q8_Kx4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = 0; x < anc / 8; x += 2) { + + const block_q2_Kx8 * b_ptr_0 = b_ptr_start + ((x) * b_nb); + const block_q2_Kx8 * b_ptr_1 = b_ptr_start + ((x + 1) * b_nb); + + // Master FP accumulators + __m512 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm512_setzero_ps(); + } + + __m512 acc_min_rows[4]; + for (int i = 0; i < 4; i++) { + acc_min_rows[i] = _mm512_setzero_ps(); + } + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the sixteen scale values from two block_q2_kx8 structures + const __m512 col_scale_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].d, b_ptr_1[b].d); + + // dmin values - Load the sixteen dmin values from two block_q2_kx8 structures + const __m512 col_dmin_f32 = GGML_F32Cx8x2_LOAD(b_ptr_0[b].dmin, b_ptr_1[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_0[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_89AB_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + sb * 256)); + const __m256i rhs_raw_mat_CDEF_0 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_89AB_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_1 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_89AB_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_2 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_89AB_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_CDEF_3 = _mm256_loadu_si256((const __m256i * )(b_ptr_1[b].qs + 224 + sb * 256)); + + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + const __m256i rhs_raw_mat_89CD_0 = _mm256_blend_epi32(rhs_raw_mat_89AB_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_0, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_0, requiredOrder), rhs_raw_mat_CDEF_0, 240); + const __m256i rhs_raw_mat_89CD_1 = _mm256_blend_epi32(rhs_raw_mat_89AB_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_1, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_1, requiredOrder), rhs_raw_mat_CDEF_1, 240); + const __m256i rhs_raw_mat_89CD_2 = _mm256_blend_epi32(rhs_raw_mat_89AB_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_2, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_2, requiredOrder), rhs_raw_mat_CDEF_2, 240); + const __m256i rhs_raw_mat_89CD_3 = _mm256_blend_epi32(rhs_raw_mat_89AB_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_CDEF_3, requiredOrder), 240); + const __m256i rhs_raw_mat_ABEF_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_89AB_3, requiredOrder), rhs_raw_mat_CDEF_3, 240); + + const __m512i rhs_raw_mat_014589CD_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_0), rhs_raw_mat_89CD_0, 1); + const __m512i rhs_raw_mat_2367ABEF_0 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_0), rhs_raw_mat_ABEF_0, 1); + const __m512i rhs_raw_mat_014589CD_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_1), rhs_raw_mat_89CD_1, 1); + const __m512i rhs_raw_mat_2367ABEF_1 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_1), rhs_raw_mat_ABEF_1, 1); + + const __m512i rhs_raw_mat_014589CD_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_2), rhs_raw_mat_89CD_2, 1); + const __m512i rhs_raw_mat_2367ABEF_2 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_2), rhs_raw_mat_ABEF_2, 1); + const __m512i rhs_raw_mat_014589CD_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_0145_3), rhs_raw_mat_89CD_3, 1); + const __m512i rhs_raw_mat_2367ABEF_3 = _mm512_inserti32x8(_mm512_castsi256_si512(rhs_raw_mat_2367_3), rhs_raw_mat_ABEF_3, 1); + + //2-bit -> 8-bit + const __m512i rhs_mat_014589CD_00 = _mm512_and_si512(rhs_raw_mat_014589CD_0,m3bexpanded); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) B08(0-7) B09(0-7) B0C(0-7) B0D(0-7) + const __m512i rhs_mat_2367ABEF_00 = _mm512_and_si512(rhs_raw_mat_2367ABEF_0,m3bexpanded); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) B0A(0-7) B0B(0-7) B0E(0-7) B0F(0-7) + const __m512i rhs_mat_014589CD_01 = _mm512_and_si512(rhs_raw_mat_014589CD_1,m3bexpanded); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) B08(8-15) B09(8-15) B0C(8-15) B0D(8-15) + const __m512i rhs_mat_2367ABEF_01 = _mm512_and_si512(rhs_raw_mat_2367ABEF_1,m3bexpanded); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) B0A(8-15) B0B(8-15) B0E(8-15) B0F(8-15) + const __m512i rhs_mat_014589CD_10 = _mm512_and_si512(rhs_raw_mat_014589CD_2,m3bexpanded); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) B18(0-7) B19(0-7) B1C(0-7) B1D(0-7) + const __m512i rhs_mat_2367ABEF_10 = _mm512_and_si512(rhs_raw_mat_2367ABEF_2,m3bexpanded); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) B1A(0-7) B1B(0-7) B1E(0-7) B1F(0-7) + const __m512i rhs_mat_014589CD_11 = _mm512_and_si512(rhs_raw_mat_014589CD_3,m3bexpanded); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) B18(8-15) B19(8-15) B1C(8-15) B1D(8-15) + const __m512i rhs_mat_2367ABEF_11 = _mm512_and_si512(rhs_raw_mat_2367ABEF_3,m3bexpanded); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) B1A(8-15) B1B(8-15) B1E(8-15) B1F(8-15) + + const __m512i rhs_mat_014589CD_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 2), m3bexpanded); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) B28(0-7) B29(0-7) B2C(0-7) B2D(0-7) + const __m512i rhs_mat_2367ABEF_20 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 2), m3bexpanded); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) B2A(0-7) B2B(0-7) B2E(0-7) B2F(0-7) + + const __m512i rhs_mat_014589CD_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 2), m3bexpanded); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) B28(8-15) B29(8-15) B2C(8-15) B2D(8-15) + const __m512i rhs_mat_2367ABEF_21 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 2), m3bexpanded); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) B2A(8-15) B2B(8-15) B2E(8-15) B2F(8-15) + + const __m512i rhs_mat_014589CD_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 2), m3bexpanded); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) B38(0-7) B39(0-7) B3C(0-7) B3D(0-7) + const __m512i rhs_mat_2367ABEF_30 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 2), m3bexpanded); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) B3A(0-7) B3B(0-7) B3E(0-7) B3F(0-7) + + const __m512i rhs_mat_014589CD_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 2), m3bexpanded); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) B38(8-15) B39(8-15) B3C(8-15) B3D(8-15) + const __m512i rhs_mat_2367ABEF_31 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 2), m3bexpanded); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) B3A(8-15) B3B(8-15) B3E(8-15) B3F(8-15) + + const __m512i rhs_mat_014589CD_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 4), m3bexpanded); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) B48(0-7) B49(0-7) B4C(0-7) B4D(0-7) + const __m512i rhs_mat_2367ABEF_40 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 4), m3bexpanded); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) B4A(0-7) B4B(0-7) B4E(0-7) B4F(0-7) + + const __m512i rhs_mat_014589CD_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 4), m3bexpanded); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) B48(8-15) B49(8-15) B4C(8-15) B4D(8-15) + const __m512i rhs_mat_2367ABEF_41 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 4), m3bexpanded); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) B4A(8-15) B4B(8-15) B4E(8-15) B4F(8-15) + + const __m512i rhs_mat_014589CD_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 4), m3bexpanded); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) B58(0-7) B59(0-7) B5C(0-7) B5D(0-7) + const __m512i rhs_mat_2367ABEF_50 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 4), m3bexpanded); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) B5A(0-7) B5B(0-7) B5E(0-7) B5F(0-7) + + const __m512i rhs_mat_014589CD_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 4), m3bexpanded); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) B58(8-15) B59(8-15) B5C(8-15) B5D(8-15) + const __m512i rhs_mat_2367ABEF_51 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 4), m3bexpanded); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) B5A(8-15) B5B(8-15) B5E(8-15) B5F(8-15) + + const __m512i rhs_mat_014589CD_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_0, 6), m3bexpanded); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) B68(0-7) B69(0-7) B6C(0-7) B6D(0-7) + const __m512i rhs_mat_2367ABEF_60 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_0, 6), m3bexpanded); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) B6A(0-7) B6B(0-7) B6E(0-7) B6F(0-7) + + const __m512i rhs_mat_014589CD_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_1, 6), m3bexpanded); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) B68(8-15) B69(8-15) B6C(8-15) B6D(8-15) + const __m512i rhs_mat_2367ABEF_61 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_1, 6), m3bexpanded); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) B6A(8-15) B6B(8-15) B6E(8-15) B6F(8-15) + + const __m512i rhs_mat_014589CD_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_2, 6), m3bexpanded); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) B78(0-7) B79(0-7) B7C(0-7) B7D(0-7) + const __m512i rhs_mat_2367ABEF_70 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_2, 6), m3bexpanded); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) B7A(0-7) B7B(0-7) B7E(0-7) B7F(0-7) + + const __m512i rhs_mat_014589CD_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_014589CD_3, 6), m3bexpanded); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) B78(8-15) B79(8-15) B7C(8-15) B7D(8-15) + const __m512i rhs_mat_2367ABEF_71 = _mm512_and_si512(_mm512_srli_epi16(rhs_raw_mat_2367ABEF_3, 6), m3bexpanded); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) B7A(8-15) B7B(8-15) B7E(8-15) B7F(8-15) + + const __m512i rhs_mat_014589CD_00_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) B08(0-3) B09(0-3) B08(0-3) B09(0-3) B0C(0-3) B0D(0-3) B0C(0-3) B0D(0-3) + const __m512i rhs_mat_2367ABEF_00_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) B0A(0-3) B0B(0-3) B0A(0-3) B0B(0-3) B0E(0-3) B0F(0-3) B0E(0-3) B0F(0-3) + + const __m512i rhs_mat_014589CD_01_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_01_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) B0A(8-11) B0B(8-11) B0A(8-11) B0B(8-11) B0E(8-11) B0F(8-11) B0E(8-11) B0F(8-11) + + const __m512i rhs_mat_014589CD_10_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) B18(0-3) B19(0-3) B18(0-3) B19(0-3) B1C(0-3) B1D(0-3) B1C(0-3) B1D(0-3) + const __m512i rhs_mat_2367ABEF_10_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) B1A(0-3) B1B(0-3) B1A(0-3) B1B(0-3) B1E(0-3) B1F(0-3) B1E(0-3) B1F(0-3) + + const __m512i rhs_mat_014589CD_11_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) B18(8-11) B19(8-11) B18(8-11) B19(8-11) B1C(8-11) B1D(8-11) B1C(8-11) B1D(8-11) + const __m512i rhs_mat_2367ABEF_11_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) B1A(8-11) B1B(8-11) B1A(8-11) B1B(8-11) B1E(8-11) B1F(8-11) B1E(8-11) B1F(8-11) + + const __m512i rhs_mat_014589CD_20_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) B28(0-3) B29(0-3) B28(0-3) B29(0-3) B2C(0-3) B2D(0-3) B2C(0-3) B2D(0-3) + const __m512i rhs_mat_2367ABEF_20_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) B2A(0-3) B2B(0-3) B2A(0-3) B2B(0-3) B2E(0-3) B2F(0-3) B2E(0-3) B2F(0-3) + + const __m512i rhs_mat_014589CD_21_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) B28(8-11) B29(8-11) B28(8-11) B29(8-11) B2C(8-11) B2D(8-11) B2C(8-11) B2D(8-11) + const __m512i rhs_mat_2367ABEF_21_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) B2A(8-11) B2B(8-11) B2A(8-11) B2B(8-11) B2E(8-11) B2F(8-11) B2E(8-11) B2F(8-11) + const __m512i rhs_mat_014589CD_30_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)136); ///B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) B38(0-3) B39(0-3) B38(0-3) B39(0-3) B3C(0-3) B3D(0-3) B3C(0-3) B3D(0-3) + const __m512i rhs_mat_2367ABEF_30_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) B3A(0-3) B3B(0-3) B3A(0-3) B3B(0-3) B3E(0-3) B3F(0-3) B3E(0-3) B3F(0-3) + + const __m512i rhs_mat_014589CD_31_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11) B38(8-11) B39(8-11) B38(8-11) B39(8-11) B3C(8-11) B3D(8-11) B3C(8-11) B3D(8-11) + const __m512i rhs_mat_2367ABEF_31_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) B3A(8-11) B3B(8-11) B3A(8-11) B3B(8-11) B3E(8-11) B3F(8-11) B3E(8-11) B3F(8-11) + + const __m512i rhs_mat_014589CD_40_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) B48(0-3) B49(0-3) B48(0-3) B49(0-3) B4C(0-3) B4D(0-3) B4C(0-3) B4D(0-3) + const __m512i rhs_mat_2367ABEF_40_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) B4A(0-3) B4B(0-3) B4A(0-3) B4B(0-3) B4E(0-3) B4F(0-3) B4E(0-3) B4F(0-3) + + const __m512i rhs_mat_014589CD_41_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) B48(8-11) B49(8-11) B48(8-11) B49(8-11) B4C(8-11) B4D(8-11) B4C(8-11) B4D(8-11) + const __m512i rhs_mat_2367ABEF_41_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) B4A(8-11) B4B(8-11) B4A(8-11) B4B(8-11) B4E(8-11) B4F(8-11) B4E(8-11) B4F(8-11) + + const __m512i rhs_mat_014589CD_50_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) B58(0-3) B59(0-3) B58(0-3) B59(0-3) B5C(0-3) B5D(0-3) B5C(0-3) B5D(0-3) + const __m512i rhs_mat_2367ABEF_50_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) B5A(0-3) B5B(0-3) B5A(0-3) B5B(0-3) B5E(0-3) B5F(0-3) B5E(0-3) B5F(0-3) + + const __m512i rhs_mat_014589CD_51_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) B58(8-11) B59(8-11) B58(8-11) B59(8-11) B5C(8-11) B5D(8-11) B5C(8-11) B5D(8-11) + const __m512i rhs_mat_2367ABEF_51_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) B5A(8-11) B5B(8-11) B5A(8-11) B5B(8-11) B5E(8-11) B5F(8-11) B5E(8-11) B5F(8-11) + + const __m512i rhs_mat_014589CD_60_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) B68(0-3) B69(0-3) B68(0-3) B69(0-3) B6C(0-3) B6D(0-3) B6C(0-3) B6D(0-3) + const __m512i rhs_mat_2367ABEF_60_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) B6A(0-3) B6B(0-3) B6A(0-3) B6B(0-3) B6E(0-3) B6F(0-3) B6E(0-3) B6F(0-3) + + const __m512i rhs_mat_014589CD_61_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) B68(8-11) B69(8-11) B68(8-11) B69(8-11) B6C(8-11) B6D(8-11) B6C(8-11) B6D(8-11) + const __m512i rhs_mat_2367ABEF_61_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) B6A(8-11) B6B(8-11) B6A(8-11) B6B(8-11) B6E(8-11) B6F(8-11) B6E(8-11) B6F(8-11) + + const __m512i rhs_mat_014589CD_70_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) B78(0-3) B79(0-3) B78(0-3) B79(0-3) B7C(0-3) B7D(0-3) B7C(0-3) B7D(0-3) + const __m512i rhs_mat_2367ABEF_70_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) B7A(0-3) B7B(0-3) B7A(0-3) B7B(0-3) B7E(0-3) B7F(0-3) B7E(0-3) B7F(0-3) + + const __m512i rhs_mat_014589CD_71_sp1 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) B08(8-11) B09(8-11) B08(8-11) B09(8-11) B0C(8-11) B0D(8-11) B0C(8-11) B0D(8-11) + const __m512i rhs_mat_2367ABEF_71_sp1 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) B7A(8-11) B7B(8-11) B7A(8-11) B7B(8-11) B7E(8-11) B7F(8-11) B7E(8-11) B7F(8-11) + + const __m512i rhs_mat_014589CD_00_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_00, (_MM_PERM_ENUM)221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) B08(4-7) B09(4-7) B08(4-7) B09(4-7) B0C(4-7) B0D(4-7) B0C(4-7) B0D(4-7) + const __m512i rhs_mat_2367ABEF_00_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_00, (_MM_PERM_ENUM)221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) B0A(4-7) B0B(4-7) B0A(4-7) B0B(4-7) B0E(4-7) B0F(4-7) B0E(4-7) B0F(4-7) + + const __m512i rhs_mat_014589CD_01_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_01, (_MM_PERM_ENUM)221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) B08(12-15) B09(12-15) B08(12-15) B09(12-15) B0C(12-15) B0D(12-15) B0C(12-15) B0D(12-15) + const __m512i rhs_mat_2367ABEF_01_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_01, (_MM_PERM_ENUM)221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) B0A(12-15) B0B(12-15) B0A(12-15) B0B(12-15) B0E(12-15) B0F(12-15) B0E(12-15) B0F(12-15) + + const __m512i rhs_mat_014589CD_10_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_10, (_MM_PERM_ENUM)221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) B18(4-7) B19(4-7) B18(4-7) B19(4-7) B1C(4-7) B1D(4-7) B1C(4-7) B1D(4-7) + const __m512i rhs_mat_2367ABEF_10_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_10, (_MM_PERM_ENUM)221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) B1A(4-7) B1B(4-7) B1A(4-7) B1B(4-7) B1E(4-7) B1F(4-7) B1E(4-7) B1F(4-7) + + const __m512i rhs_mat_014589CD_11_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_11, (_MM_PERM_ENUM)221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) B18(12-15) B19(12-15) B18(12-15) B19(12-15) B1C(12-15) B1D(12-15) B1C(12-15) B1D(12-15) + const __m512i rhs_mat_2367ABEF_11_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_11, (_MM_PERM_ENUM)221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) B1A(12-15) B1B(12-15) B1A(12-15) B1B(12-15) B1E(12-15) B1F(12-15) B1E(12-15) B1F(12-15) + + const __m512i rhs_mat_014589CD_20_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_20, (_MM_PERM_ENUM)221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) B28(4-7) B29(4-7) B28(4-7) B29(4-7) B2C(4-7) B2D(4-7) B2C(4-7) B2D(4-7) + const __m512i rhs_mat_2367ABEF_20_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_20, (_MM_PERM_ENUM)221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) B2A(4-7) B2B(4-7) B2A(4-7) B2B(4-7) B2E(4-7) B2F(4-7) B2E(4-7) B2F(4-7) + + const __m512i rhs_mat_014589CD_21_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_21, (_MM_PERM_ENUM)221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) B28(12-15) B29(12-15) B28(12-15) B29(12-15) B2C(12-15) B2D(12-15) B2C(12-15) B2D(12-15) + const __m512i rhs_mat_2367ABEF_21_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_21, (_MM_PERM_ENUM)221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) B2A(12-15) B2B(12-15) B2A(12-15) B2B(12-15) B2E(12-15) B2F(12-15) B2E(12-15) B2F(12-15) + + const __m512i rhs_mat_014589CD_30_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_30, (_MM_PERM_ENUM)221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) B38(4-7) B39(4-7) B38(4-7) B39(4-7) B3C(4-7) B3D(4-7) B3C(4-7) B3D(4-7) + const __m512i rhs_mat_2367ABEF_30_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_30, (_MM_PERM_ENUM)221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) B3A(4-7) B3B(4-7) B3A(4-7) B3B(4-7) B3E(4-7) B3F(4-7) B3E(4-7) B3F(4-7) + + const __m512i rhs_mat_014589CD_31_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_31, (_MM_PERM_ENUM)221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) B38(12-15) B39(12-15) B38(12-15) B39(12-15) B3C(12-15) B3D(12-15) B3C(12-15) B3D(12-15) + const __m512i rhs_mat_2367ABEF_31_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_31, (_MM_PERM_ENUM)221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) B3A(12-15) B3B(12-15) B3A(12-15) B3B(12-15) B3E(12-15) B3F(12-15) B3E(12-15) B3F(12-15) + + const __m512i rhs_mat_014589CD_40_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_40, (_MM_PERM_ENUM)221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) B48(4-7) B49(4-7) B48(4-7) B49(4-7) B4C(4-7) B4D(4-7) B4C(4-7) B4D(4-7) + const __m512i rhs_mat_2367ABEF_40_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_40, (_MM_PERM_ENUM)221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) B4A(4-7) B4B(4-7) B4A(4-7) B4B(4-7) B4E(4-7) B4F(4-7) B4E(4-7) B4F(4-7) + + const __m512i rhs_mat_014589CD_41_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_41, (_MM_PERM_ENUM)221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) B48(12-15) B49(12-15) B48(12-15) B49(12-15) B4C(12-15) B4D(12-15) B4C(12-15) B4D(12-15) + const __m512i rhs_mat_2367ABEF_41_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_41, (_MM_PERM_ENUM)221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) B4A(12-15) B4B(12-15) B4A(12-15) B4B(12-15) B4E(12-15) B4F(12-15) B4E(12-15) B4F(12-15) + + const __m512i rhs_mat_014589CD_50_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_50, (_MM_PERM_ENUM)221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) B58(4-7) B59(4-7) B58(4-7) B59(4-7) B5C(4-7) B5D(4-7) B5C(4-7) B5D(4-7) + const __m512i rhs_mat_2367ABEF_50_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_50, (_MM_PERM_ENUM)221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) B5A(4-7) B5B(4-7) B5A(4-7) B5B(4-7) B5E(4-7) B5F(4-7) B5E(4-7) B5F(4-7) + + const __m512i rhs_mat_014589CD_51_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_51, (_MM_PERM_ENUM)221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) B58(12-15) B59(12-15) B58(12-15) B59(12-15) B5C(12-15) B5D(12-15) B5C(12-15) B5D(12-15) + const __m512i rhs_mat_2367ABEF_51_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_51, (_MM_PERM_ENUM)221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) B5A(12-15) B5B(12-15) B5A(12-15) B5B(12-15) B5E(12-15) B5F(12-15) B5E(12-15) B5F(12-15) + + const __m512i rhs_mat_014589CD_60_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_60, (_MM_PERM_ENUM)221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) B68(4-7) B69(4-7) B68(4-7) B69(4-7) B6C(4-7) B6D(4-7) B6C(4-7) B6D(4-7) + const __m512i rhs_mat_2367ABEF_60_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_60, (_MM_PERM_ENUM)221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) B6A(4-7) B6B(4-7) B6A(4-7) B6B(4-7) B6E(4-7) B6F(4-7) B6E(4-7) B6F(4-7) + + const __m512i rhs_mat_014589CD_61_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_61, (_MM_PERM_ENUM)221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) B68(12-15) B69(12-15) B68(12-15) B69(12-15) B6C(12-15) B6D(12-15) B6C(12-15) B6D(12-15) + const __m512i rhs_mat_2367ABEF_61_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_61, (_MM_PERM_ENUM)221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) B6A(12-15) B6B(12-15) B6A(12-15) B6B(12-15) B6E(12-15) B6F(12-15) B6E(12-15) B6F(12-15) + + const __m512i rhs_mat_014589CD_70_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_70, (_MM_PERM_ENUM)221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) B78(4-7) B79(4-7) B78(4-7) B79(4-7) B7C(4-7) B7D(4-7) B7C(4-7) B7D(4-7) + const __m512i rhs_mat_2367ABEF_70_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_70, (_MM_PERM_ENUM)221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) B7A(4-7) B7B(4-7) B7A(4-7) B7B(4-7) B7E(4-7) B7F(4-7) B7E(4-7) B7F(4-7) + + const __m512i rhs_mat_014589CD_71_sp2 = _mm512_shuffle_epi32(rhs_mat_014589CD_71, (_MM_PERM_ENUM)221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) B78(12-15) B79(12-15) B78(12-15) B79(12-15) B7C(12-15) B7D(12-15) B7C(12-15) B7D(12-15) + const __m512i rhs_mat_2367ABEF_71_sp2 = _mm512_shuffle_epi32(rhs_mat_2367ABEF_71, (_MM_PERM_ENUM)221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) B7A(12-15) B7B(12-15) B7A(12-15) B7B(12-15) B7E(12-15) B7F(12-15) B7E(12-15) B7F(12-15) + + //notation:superblock subblock + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + const __m128i mins_and_scales_01_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + sb * 64)); + const __m128i mins_and_scales_23_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_0 = _mm_loadu_si128((const __m128i *)(b_ptr_0[b].scales + 48 + sb * 64)); + + const __m128i mins_and_scales_01_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + sb * 64)); + const __m128i mins_and_scales_23_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67_1 = _mm_loadu_si128((const __m128i *)(b_ptr_1[b].scales + 48 + sb * 64)); + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m256i mins_and_scales_01 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_01_0), mins_and_scales_01_1, 1); + const __m256i mins_and_scales_23 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_23_0), mins_and_scales_23_1, 1); + const __m256i mins_and_scales_45 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_45_0), mins_and_scales_45_1, 1); + const __m256i mins_and_scales_67 = _mm256_insertf128_si256(_mm256_castsi128_si256(mins_and_scales_67_0), mins_and_scales_67_1, 1); + + // Extract scales which is lower half from mins_and_scales + const __m256i scales_01 = _mm256_and_si256(mins_and_scales_01, m4b); + const __m256i scales_23 = _mm256_and_si256(mins_and_scales_23, m4b); + const __m256i scales_45 = _mm256_and_si256(mins_and_scales_45, m4b); + const __m256i scales_67 = _mm256_and_si256(mins_and_scales_67, m4b); + + // Extract mins which is upper half from mins_and_scales + const __m512i mins_01 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_01, 4), m4b)); + const __m512i mins_23 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_23, 4), m4b)); + const __m512i mins_45 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_45, 4), m4b)); + const __m512i mins_67 = _mm512_cvtepu8_epi16(_mm256_and_si256(_mm256_srli_epi16(mins_and_scales_67, 4), m4b)); + + const __m512i scales_0 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01, scalesmask1)); + const __m512i scales_1 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_01, scalesmask2)); + const __m512i scales_2 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23, scalesmask1)); + const __m512i scales_3 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_23, scalesmask2)); + const __m512i scales_4 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45, scalesmask1)); + const __m512i scales_5 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_45, scalesmask2)); + const __m512i scales_6 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67, scalesmask1)); + const __m512i scales_7 = _mm512_cvtepu8_epi16(_mm256_shuffle_epi8(scales_67, scalesmask2)); + + const __m512i scale_014589CD_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_0 = _mm512_shuffle_epi32(scales_0, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_1 = _mm512_shuffle_epi32(scales_1, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_2 = _mm512_shuffle_epi32(scales_2, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_3 = _mm512_shuffle_epi32(scales_3, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_4 = _mm512_shuffle_epi32(scales_4, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_5 = _mm512_shuffle_epi32(scales_5, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_6 = _mm512_shuffle_epi32(scales_6, (_MM_PERM_ENUM)238); + + const __m512i scale_014589CD_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)68); + const __m512i scale_2367ABEF_7 = _mm512_shuffle_epi32(scales_7, (_MM_PERM_ENUM)238); + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_ymm_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 512 * sb))); + __m256i lhs_mat_ymm_01_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 0); + __m256i lhs_mat_ymm_23_00 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_00, lhs_mat_ymm_0123_00, 17); + __m256i lhs_mat_ymm_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 32 + 512 * sb))); + __m256i lhs_mat_ymm_01_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 0); + __m256i lhs_mat_ymm_23_01 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_01, lhs_mat_ymm_0123_01, 17); + __m256i lhs_mat_ymm_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 64 + 512 * sb))); + __m256i lhs_mat_ymm_01_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 0); + __m256i lhs_mat_ymm_23_10 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_10, lhs_mat_ymm_0123_10, 17); + __m256i lhs_mat_ymm_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 96 + 512 * sb))); + __m256i lhs_mat_ymm_01_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 0); + __m256i lhs_mat_ymm_23_11 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_11, lhs_mat_ymm_0123_11, 17); + __m256i lhs_mat_ymm_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 128 + 512 * sb))); + __m256i lhs_mat_ymm_01_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 0); + __m256i lhs_mat_ymm_23_20 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_20, lhs_mat_ymm_0123_20, 17); + __m256i lhs_mat_ymm_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 160 + 512 * sb))); + __m256i lhs_mat_ymm_01_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 0); + __m256i lhs_mat_ymm_23_21 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_21, lhs_mat_ymm_0123_21, 17); + __m256i lhs_mat_ymm_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 192 + 512 * sb))); + __m256i lhs_mat_ymm_01_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 0); + __m256i lhs_mat_ymm_23_30 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_30, lhs_mat_ymm_0123_30, 17); + __m256i lhs_mat_ymm_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 224 + 512 * sb))); + __m256i lhs_mat_ymm_01_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 0); + __m256i lhs_mat_ymm_23_31 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_31, lhs_mat_ymm_0123_31, 17); + + __m256i lhs_mat_ymm_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 256 + 512 * sb))); + __m256i lhs_mat_ymm_01_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 0); + __m256i lhs_mat_ymm_23_40 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_40, lhs_mat_ymm_0123_40, 17); + __m256i lhs_mat_ymm_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 288 + 512 * sb))); + __m256i lhs_mat_ymm_01_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 0); + __m256i lhs_mat_ymm_23_41 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_41, lhs_mat_ymm_0123_41, 17); + __m256i lhs_mat_ymm_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 320 + 512 * sb))); + __m256i lhs_mat_ymm_01_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 0); + __m256i lhs_mat_ymm_23_50 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_50, lhs_mat_ymm_0123_50, 17); + __m256i lhs_mat_ymm_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 352 + 512 * sb))); + __m256i lhs_mat_ymm_01_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 0); + __m256i lhs_mat_ymm_23_51 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_51, lhs_mat_ymm_0123_51, 17); + __m256i lhs_mat_ymm_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 384 + 512 * sb))); + __m256i lhs_mat_ymm_01_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 0); + __m256i lhs_mat_ymm_23_60 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_60, lhs_mat_ymm_0123_60, 17); + __m256i lhs_mat_ymm_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 416 + 512 * sb))); + __m256i lhs_mat_ymm_01_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 0); + __m256i lhs_mat_ymm_23_61 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_61, lhs_mat_ymm_0123_61, 17); + __m256i lhs_mat_ymm_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 448 + 512 * sb))); + __m256i lhs_mat_ymm_01_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 0); + __m256i lhs_mat_ymm_23_70 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_70, lhs_mat_ymm_0123_70, 17); + __m256i lhs_mat_ymm_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 480 + 512 * sb))); + __m256i lhs_mat_ymm_01_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 0); + __m256i lhs_mat_ymm_23_71 = _mm256_permute2f128_si256(lhs_mat_ymm_0123_71, lhs_mat_ymm_0123_71, 17); + + __m512i lhs_mat_01_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_00), lhs_mat_ymm_01_00, 1); + __m512i lhs_mat_23_00 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_00), lhs_mat_ymm_23_00, 1); + __m512i lhs_mat_01_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_01), lhs_mat_ymm_01_01, 1); + __m512i lhs_mat_23_01 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_01), lhs_mat_ymm_23_01, 1); + + __m512i lhs_mat_01_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_10), lhs_mat_ymm_01_10, 1); + __m512i lhs_mat_23_10 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_10), lhs_mat_ymm_23_10, 1); + __m512i lhs_mat_01_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_11), lhs_mat_ymm_01_11, 1); + __m512i lhs_mat_23_11 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_11), lhs_mat_ymm_23_11, 1); + + __m512i lhs_mat_01_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_20), lhs_mat_ymm_01_20, 1); + __m512i lhs_mat_23_20 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_20), lhs_mat_ymm_23_20, 1); + __m512i lhs_mat_01_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_21), lhs_mat_ymm_01_21, 1); + __m512i lhs_mat_23_21 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_21), lhs_mat_ymm_23_21, 1); + + __m512i lhs_mat_01_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_30), lhs_mat_ymm_01_30, 1); + __m512i lhs_mat_23_30 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_30), lhs_mat_ymm_23_30, 1); + __m512i lhs_mat_01_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_31), lhs_mat_ymm_01_31, 1); + __m512i lhs_mat_23_31 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_31), lhs_mat_ymm_23_31, 1); + + __m512i lhs_mat_01_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_40), lhs_mat_ymm_01_40, 1); + __m512i lhs_mat_23_40 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_40), lhs_mat_ymm_23_40, 1); + __m512i lhs_mat_01_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_41), lhs_mat_ymm_01_41, 1); + __m512i lhs_mat_23_41 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_41), lhs_mat_ymm_23_41, 1); + + __m512i lhs_mat_01_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_50), lhs_mat_ymm_01_50, 1); + __m512i lhs_mat_23_50 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_50), lhs_mat_ymm_23_50, 1); + __m512i lhs_mat_01_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_51), lhs_mat_ymm_01_51, 1); + __m512i lhs_mat_23_51 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_51), lhs_mat_ymm_23_51, 1); + + __m512i lhs_mat_01_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_60), lhs_mat_ymm_01_60, 1); + __m512i lhs_mat_23_60 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_60), lhs_mat_ymm_23_60, 1); + __m512i lhs_mat_01_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_61), lhs_mat_ymm_01_61, 1); + __m512i lhs_mat_23_61 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_61), lhs_mat_ymm_23_61, 1); + + __m512i lhs_mat_01_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_70), lhs_mat_ymm_01_70, 1); + __m512i lhs_mat_23_70 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_70), lhs_mat_ymm_23_70, 1); + __m512i lhs_mat_01_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_01_71), lhs_mat_ymm_01_71, 1); + __m512i lhs_mat_23_71 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_mat_ymm_23_71), lhs_mat_ymm_23_71, 1); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 24 + 32 * sb)); + + __m256i lhs_bsums_ymm_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m512i lhs_bsums_01_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_0123), lhs_bsums_ymm_01_0123, 1); + __m256i lhs_bsums_ymm_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m512i lhs_bsums_23_0123 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_0123), lhs_bsums_ymm_23_0123, 1); + __m256i lhs_bsums_ymm_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m512i lhs_bsums_01_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_01_4567), lhs_bsums_ymm_01_4567, 1); + __m256i lhs_bsums_ymm_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + __m512i lhs_bsums_23_4567 = _mm512_inserti32x8(_mm512_castsi256_si512(lhs_bsums_ymm_23_4567), lhs_bsums_ymm_23_4567, 1); + + // Shuffle pattern one - left side input + const __m512i lhs_mat_01_00_sp1 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m512i lhs_mat_23_00_sp1 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)160); //A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) A02(0-3) A02(0-3) A03(0-3) A03(0-3) + + const __m512i lhs_mat_01_01_sp1 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m512i lhs_mat_23_01_sp1 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)160); //A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) A02(8-11) A02(8-11) A03(8-11) A03(8-11) + + const __m512i lhs_mat_01_10_sp1 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m512i lhs_mat_23_10_sp1 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)160); //A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) A12(0-3) A12(0-3) A13(0-3) A13(0-3) + + const __m512i lhs_mat_01_11_sp1 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m512i lhs_mat_23_11_sp1 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)160); //A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) A12(8-11) A12(8-11) A13(8-11) A13(8-11) + + const __m512i lhs_mat_01_20_sp1 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m512i lhs_mat_23_20_sp1 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)160); //A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) A22(0-3) A22(0-3) A23(0-3) A23(0-3) + + const __m512i lhs_mat_01_21_sp1 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m512i lhs_mat_23_21_sp1 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)160); //A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) A22(8-11) A22(8-11) A23(8-11) A23(8-11) + + const __m512i lhs_mat_01_30_sp1 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m512i lhs_mat_23_30_sp1 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)160); //A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) A32(0-3) A32(0-3) A33(0-3) A33(0-3) + + const __m512i lhs_mat_01_31_sp1 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m512i lhs_mat_23_31_sp1 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)160); //A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) A32(8-11) A32(8-11) A33(8-11) A33(8-11) + + const __m512i lhs_mat_01_40_sp1 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m512i lhs_mat_23_40_sp1 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)160); //A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) A42(0-3) A42(0-3) A43(0-3) A43(0-3) + + const __m512i lhs_mat_01_41_sp1 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m512i lhs_mat_23_41_sp1 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)160); //A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) A42(8-11) A42(8-11) A43(8-11) A43(8-11) + + const __m512i lhs_mat_01_50_sp1 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m512i lhs_mat_23_50_sp1 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)160); //A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) A52(0-3) A52(0-3) A53(0-3) A53(0-3) + + const __m512i lhs_mat_01_51_sp1 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m512i lhs_mat_23_51_sp1 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)160); //A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) A52(8-11) A52(8-11) A53(8-11) A53(8-11) + + const __m512i lhs_mat_01_60_sp1 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m512i lhs_mat_23_60_sp1 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)160); //A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) A62(0-3) A62(0-3) A63(0-3) A63(0-3) + + const __m512i lhs_mat_01_61_sp1 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m512i lhs_mat_23_61_sp1 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)160); //A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) A62(8-11) A62(8-11) A63(8-11) A63(8-11) + + const __m512i lhs_mat_01_70_sp1 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m512i lhs_mat_23_70_sp1 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)160); //A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) A72(0-3) A72(0-3) A73(0-3) A73(0-3) + + const __m512i lhs_mat_01_71_sp1 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m512i lhs_mat_23_71_sp1 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)160); //A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) A72(8-11) A72(8-11) A73(8-11) A73(8-11) + + const __m512i lhs_mat_01_00_sp2 = _mm512_shuffle_epi32(lhs_mat_01_00, (_MM_PERM_ENUM)245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m512i lhs_mat_23_00_sp2 = _mm512_shuffle_epi32(lhs_mat_23_00, (_MM_PERM_ENUM)245); //A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) A02(4-7) A02(4-7) A03(4-7) A03(4-7) + + const __m512i lhs_mat_01_01_sp2 = _mm512_shuffle_epi32(lhs_mat_01_01, (_MM_PERM_ENUM)245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m512i lhs_mat_23_01_sp2 = _mm512_shuffle_epi32(lhs_mat_23_01, (_MM_PERM_ENUM)245); //A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) A02(12-15) A02(12-15) A03(12-15) A03(12-15) + + const __m512i lhs_mat_01_10_sp2 = _mm512_shuffle_epi32(lhs_mat_01_10, (_MM_PERM_ENUM)245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m512i lhs_mat_23_10_sp2 = _mm512_shuffle_epi32(lhs_mat_23_10, (_MM_PERM_ENUM)245); //A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) A12(4-7) A12(4-7) A13(4-7) A13(4-7) + + const __m512i lhs_mat_01_11_sp2 = _mm512_shuffle_epi32(lhs_mat_01_11, (_MM_PERM_ENUM)245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m512i lhs_mat_23_11_sp2 = _mm512_shuffle_epi32(lhs_mat_23_11, (_MM_PERM_ENUM)245); //A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) A12(12-15) A12(12-15) A13(12-15) A13(12-15) + + const __m512i lhs_mat_01_20_sp2 = _mm512_shuffle_epi32(lhs_mat_01_20, (_MM_PERM_ENUM)245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m512i lhs_mat_23_20_sp2 = _mm512_shuffle_epi32(lhs_mat_23_20, (_MM_PERM_ENUM)245); //A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) A22(4-7) A22(4-7) A23(4-7) A23(4-7) + + const __m512i lhs_mat_01_21_sp2 = _mm512_shuffle_epi32(lhs_mat_01_21, (_MM_PERM_ENUM)245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m512i lhs_mat_23_21_sp2 = _mm512_shuffle_epi32(lhs_mat_23_21, (_MM_PERM_ENUM)245); //A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) A22(12-15) A22(12-15) A23(12-15) A23(12-15) + + const __m512i lhs_mat_01_30_sp2 = _mm512_shuffle_epi32(lhs_mat_01_30, (_MM_PERM_ENUM)245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m512i lhs_mat_23_30_sp2 = _mm512_shuffle_epi32(lhs_mat_23_30, (_MM_PERM_ENUM)245); //A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) A32(4-7) A32(4-7) A33(4-7) A33(4-7) + + const __m512i lhs_mat_01_31_sp2 = _mm512_shuffle_epi32(lhs_mat_01_31, (_MM_PERM_ENUM)245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m512i lhs_mat_23_31_sp2 = _mm512_shuffle_epi32(lhs_mat_23_31, (_MM_PERM_ENUM)245); //A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) A32(12-15) A32(12-15) A33(12-15) A33(12-15) + + const __m512i lhs_mat_01_40_sp2 = _mm512_shuffle_epi32(lhs_mat_01_40, (_MM_PERM_ENUM)245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m512i lhs_mat_23_40_sp2 = _mm512_shuffle_epi32(lhs_mat_23_40, (_MM_PERM_ENUM)245); //A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) A42(4-7) A42(4-7) A43(4-7) A43(4-7) + + const __m512i lhs_mat_01_41_sp2 = _mm512_shuffle_epi32(lhs_mat_01_41, (_MM_PERM_ENUM)245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m512i lhs_mat_23_41_sp2 = _mm512_shuffle_epi32(lhs_mat_23_41, (_MM_PERM_ENUM)245); //A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) A42(12-15) A42(12-15) A43(12-15) A43(12-15) + + const __m512i lhs_mat_01_50_sp2 = _mm512_shuffle_epi32(lhs_mat_01_50, (_MM_PERM_ENUM)245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m512i lhs_mat_23_50_sp2 = _mm512_shuffle_epi32(lhs_mat_23_50, (_MM_PERM_ENUM)245); //A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) A52(4-7) A52(4-7) A53(4-7) A53(4-7) + + const __m512i lhs_mat_01_51_sp2 = _mm512_shuffle_epi32(lhs_mat_01_51, (_MM_PERM_ENUM)245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m512i lhs_mat_23_51_sp2 = _mm512_shuffle_epi32(lhs_mat_23_51, (_MM_PERM_ENUM)245); //A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) A52(12-15) A52(12-15) A53(12-15) A53(12-15) + + const __m512i lhs_mat_01_60_sp2 = _mm512_shuffle_epi32(lhs_mat_01_60, (_MM_PERM_ENUM)245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m512i lhs_mat_23_60_sp2 = _mm512_shuffle_epi32(lhs_mat_23_60, (_MM_PERM_ENUM)245); //A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) A62(4-7) A62(4-7) A63(4-7) A63(4-7) + + const __m512i lhs_mat_01_61_sp2 = _mm512_shuffle_epi32(lhs_mat_01_61, (_MM_PERM_ENUM)245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m512i lhs_mat_23_61_sp2 = _mm512_shuffle_epi32(lhs_mat_23_61, (_MM_PERM_ENUM)245); //A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) A62(12-15) A62(12-15) A63(12-15) A63(12-15) + + const __m512i lhs_mat_01_70_sp2 = _mm512_shuffle_epi32(lhs_mat_01_70, (_MM_PERM_ENUM)245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m512i lhs_mat_23_70_sp2 = _mm512_shuffle_epi32(lhs_mat_23_70, (_MM_PERM_ENUM)245); //A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) A72(4-7) A72(4-7) A73(4-7) A73(4-7) + + const __m512i lhs_mat_01_71_sp2 = _mm512_shuffle_epi32(lhs_mat_01_71, (_MM_PERM_ENUM)245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m512i lhs_mat_23_71_sp2 = _mm512_shuffle_epi32(lhs_mat_23_71, (_MM_PERM_ENUM)245); //A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) A72(12-15) A72(12-15) A73(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m512i iacc_mat_00_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_01_01_sp1)); + __m512i iacc_mat_01_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_01_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_01_01_sp1)); + + __m512i iacc_mat_10_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp1, lhs_mat_23_01_sp1)); + __m512i iacc_mat_11_0_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp1, lhs_mat_23_00_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp1, lhs_mat_23_01_sp1)); + + __m512i iacc_mat_00_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_01_11_sp1)); + __m512i iacc_mat_01_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_01_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_01_11_sp1)); + + __m512i iacc_mat_10_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp1, lhs_mat_23_11_sp1)); + __m512i iacc_mat_11_1_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp1, lhs_mat_23_10_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp1, lhs_mat_23_11_sp1)); + + __m512i iacc_mat_00_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_01_21_sp1)); + __m512i iacc_mat_01_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_01_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_01_21_sp1)); + + __m512i iacc_mat_10_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp1, lhs_mat_23_21_sp1)); + __m512i iacc_mat_11_2_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp1, lhs_mat_23_20_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp1, lhs_mat_23_21_sp1)); + + __m512i iacc_mat_00_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_01_31_sp1)); + __m512i iacc_mat_01_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_01_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_01_31_sp1)); + + __m512i iacc_mat_10_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp1, lhs_mat_23_31_sp1)); + __m512i iacc_mat_11_3_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp1, lhs_mat_23_30_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp1, lhs_mat_23_31_sp1)); + + __m512i iacc_mat_00_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_01_41_sp1)); + __m512i iacc_mat_01_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_01_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_01_41_sp1)); + + __m512i iacc_mat_10_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp1, lhs_mat_23_41_sp1)); + __m512i iacc_mat_11_4_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp1, lhs_mat_23_40_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp1, lhs_mat_23_41_sp1)); + + __m512i iacc_mat_00_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_01_51_sp1)); + __m512i iacc_mat_01_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_01_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_01_51_sp1)); + + __m512i iacc_mat_10_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp1, lhs_mat_23_51_sp1)); + __m512i iacc_mat_11_5_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp1, lhs_mat_23_50_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp1, lhs_mat_23_51_sp1)); + + __m512i iacc_mat_00_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_01_61_sp1)); + __m512i iacc_mat_01_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_01_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_01_61_sp1)); + + __m512i iacc_mat_10_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp1, lhs_mat_23_61_sp1)); + __m512i iacc_mat_11_6_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp1, lhs_mat_23_60_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp1, lhs_mat_23_61_sp1)); + + __m512i iacc_mat_00_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_01_71_sp1)); + __m512i iacc_mat_01_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_01_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_01_71_sp1)); + + __m512i iacc_mat_10_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp1, lhs_mat_23_71_sp1)); + __m512i iacc_mat_11_7_sp1 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp1, lhs_mat_23_70_sp1),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp1, lhs_mat_23_71_sp1)); + + + __m512i iacc_mat_00_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_01_01_sp2)); + __m512i iacc_mat_01_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_01_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_01_01_sp2)); + + __m512i iacc_mat_10_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_01_sp2, lhs_mat_23_01_sp2)); + __m512i iacc_mat_11_0_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_00_sp2, lhs_mat_23_00_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_01_sp2, lhs_mat_23_01_sp2)); + + __m512i iacc_mat_00_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_01_11_sp2)); + __m512i iacc_mat_01_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_01_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_01_11_sp2)); + + __m512i iacc_mat_10_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_11_sp2, lhs_mat_23_11_sp2)); + __m512i iacc_mat_11_1_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_10_sp2, lhs_mat_23_10_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_11_sp2, lhs_mat_23_11_sp2)); + + __m512i iacc_mat_00_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_01_21_sp2)); + __m512i iacc_mat_01_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_01_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_01_21_sp2)); + + __m512i iacc_mat_10_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_21_sp2, lhs_mat_23_21_sp2)); + __m512i iacc_mat_11_2_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_20_sp2, lhs_mat_23_20_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_21_sp2, lhs_mat_23_21_sp2)); + + __m512i iacc_mat_00_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_01_31_sp2)); + __m512i iacc_mat_01_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_01_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_01_31_sp2)); + + __m512i iacc_mat_10_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_31_sp2, lhs_mat_23_31_sp2)); + __m512i iacc_mat_11_3_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_30_sp2, lhs_mat_23_30_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_31_sp2, lhs_mat_23_31_sp2)); + + __m512i iacc_mat_00_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_01_41_sp2)); + __m512i iacc_mat_01_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_01_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_01_41_sp2)); + + __m512i iacc_mat_10_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_41_sp2, lhs_mat_23_41_sp2)); + __m512i iacc_mat_11_4_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_40_sp2, lhs_mat_23_40_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_41_sp2, lhs_mat_23_41_sp2)); + + __m512i iacc_mat_00_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_01_51_sp2)); + __m512i iacc_mat_01_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_01_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_01_51_sp2)); + + __m512i iacc_mat_10_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_51_sp2, lhs_mat_23_51_sp2)); + __m512i iacc_mat_11_5_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_50_sp2, lhs_mat_23_50_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_51_sp2, lhs_mat_23_51_sp2)); + + __m512i iacc_mat_00_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_01_61_sp2)); + __m512i iacc_mat_01_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_01_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_01_61_sp2)); + + __m512i iacc_mat_10_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_61_sp2, lhs_mat_23_61_sp2)); + __m512i iacc_mat_11_6_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_60_sp2, lhs_mat_23_60_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_61_sp2, lhs_mat_23_61_sp2)); + + __m512i iacc_mat_00_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_01_71_sp2)); + __m512i iacc_mat_01_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_01_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_01_71_sp2)); + + __m512i iacc_mat_10_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_014589CD_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_014589CD_71_sp2, lhs_mat_23_71_sp2)); + __m512i iacc_mat_11_7_sp2 = _mm512_add_epi16(_mm512_maddubs_epi16(rhs_mat_2367ABEF_70_sp2, lhs_mat_23_70_sp2),_mm512_maddubs_epi16(rhs_mat_2367ABEF_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m512i iacc_mat_00_0 = _mm512_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m512i iacc_mat_01_0 = _mm512_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m512i iacc_mat_10_0 = _mm512_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m512i iacc_mat_11_0 = _mm512_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m512i iacc_mat_00_1 = _mm512_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m512i iacc_mat_01_1 = _mm512_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m512i iacc_mat_10_1 = _mm512_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m512i iacc_mat_11_1 = _mm512_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m512i iacc_mat_00_2 = _mm512_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m512i iacc_mat_01_2 = _mm512_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m512i iacc_mat_10_2 = _mm512_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m512i iacc_mat_11_2 = _mm512_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m512i iacc_mat_00_3 = _mm512_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m512i iacc_mat_01_3 = _mm512_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m512i iacc_mat_10_3 = _mm512_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m512i iacc_mat_11_3 = _mm512_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m512i iacc_mat_00_4 = _mm512_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m512i iacc_mat_01_4 = _mm512_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m512i iacc_mat_10_4 = _mm512_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m512i iacc_mat_11_4 = _mm512_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m512i iacc_mat_00_5 = _mm512_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m512i iacc_mat_01_5 = _mm512_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m512i iacc_mat_10_5 = _mm512_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m512i iacc_mat_11_5 = _mm512_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m512i iacc_mat_00_6 = _mm512_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m512i iacc_mat_01_6 = _mm512_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m512i iacc_mat_10_6 = _mm512_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m512i iacc_mat_11_6 = _mm512_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m512i iacc_mat_00_7 = _mm512_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m512i iacc_mat_01_7 = _mm512_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m512i iacc_mat_10_7 = _mm512_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m512i iacc_mat_11_7 = _mm512_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm512_madd_epi16(iacc_mat_00_0, scale_014589CD_0); + iacc_mat_01_0 = _mm512_madd_epi16(iacc_mat_01_0, scale_2367ABEF_0); + iacc_mat_10_0 = _mm512_madd_epi16(iacc_mat_10_0, scale_014589CD_0); + iacc_mat_11_0 = _mm512_madd_epi16(iacc_mat_11_0, scale_2367ABEF_0); + + iacc_mat_00_1 = _mm512_madd_epi16(iacc_mat_00_1, scale_014589CD_1); + iacc_mat_01_1 = _mm512_madd_epi16(iacc_mat_01_1, scale_2367ABEF_1); + iacc_mat_10_1 = _mm512_madd_epi16(iacc_mat_10_1, scale_014589CD_1); + iacc_mat_11_1 = _mm512_madd_epi16(iacc_mat_11_1, scale_2367ABEF_1); + + iacc_mat_00_2 = _mm512_madd_epi16(iacc_mat_00_2, scale_014589CD_2); + iacc_mat_01_2 = _mm512_madd_epi16(iacc_mat_01_2, scale_2367ABEF_2); + iacc_mat_10_2 = _mm512_madd_epi16(iacc_mat_10_2, scale_014589CD_2); + iacc_mat_11_2 = _mm512_madd_epi16(iacc_mat_11_2, scale_2367ABEF_2); + + iacc_mat_00_3 = _mm512_madd_epi16(iacc_mat_00_3, scale_014589CD_3); + iacc_mat_01_3 = _mm512_madd_epi16(iacc_mat_01_3, scale_2367ABEF_3); + iacc_mat_10_3 = _mm512_madd_epi16(iacc_mat_10_3, scale_014589CD_3); + iacc_mat_11_3 = _mm512_madd_epi16(iacc_mat_11_3, scale_2367ABEF_3); + + iacc_mat_00_4 = _mm512_madd_epi16(iacc_mat_00_4, scale_014589CD_4); + iacc_mat_01_4 = _mm512_madd_epi16(iacc_mat_01_4, scale_2367ABEF_4); + iacc_mat_10_4 = _mm512_madd_epi16(iacc_mat_10_4, scale_014589CD_4); + iacc_mat_11_4 = _mm512_madd_epi16(iacc_mat_11_4, scale_2367ABEF_4); + + iacc_mat_00_5 = _mm512_madd_epi16(iacc_mat_00_5, scale_014589CD_5); + iacc_mat_01_5 = _mm512_madd_epi16(iacc_mat_01_5, scale_2367ABEF_5); + iacc_mat_10_5 = _mm512_madd_epi16(iacc_mat_10_5, scale_014589CD_5); + iacc_mat_11_5 = _mm512_madd_epi16(iacc_mat_11_5, scale_2367ABEF_5); + + iacc_mat_00_6 = _mm512_madd_epi16(iacc_mat_00_6, scale_014589CD_6); + iacc_mat_01_6 = _mm512_madd_epi16(iacc_mat_01_6, scale_2367ABEF_6); + iacc_mat_10_6 = _mm512_madd_epi16(iacc_mat_10_6, scale_014589CD_6); + iacc_mat_11_6 = _mm512_madd_epi16(iacc_mat_11_6, scale_2367ABEF_6); + + iacc_mat_00_7 = _mm512_madd_epi16(iacc_mat_00_7, scale_014589CD_7); + iacc_mat_01_7 = _mm512_madd_epi16(iacc_mat_01_7, scale_2367ABEF_7); + iacc_mat_10_7 = _mm512_madd_epi16(iacc_mat_10_7, scale_014589CD_7); + iacc_mat_11_7 = _mm512_madd_epi16(iacc_mat_11_7, scale_2367ABEF_7); + + __m512i iacc_mat_00 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm512_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm512_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m512i iacc_mat_01 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm512_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm512_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m512i iacc_mat_10 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm512_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm512_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m512i iacc_mat_11 = _mm512_add_epi32(_mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm512_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm512_add_epi32(_mm512_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm512_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m512i iacc_row_0 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_00, _mm512_shuffle_epi32(iacc_mat_01, (_MM_PERM_ENUM)78)); + __m512i iacc_row_1 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_00, (_MM_PERM_ENUM)78), iacc_mat_01); + __m512i iacc_row_2 = _mm512_mask_blend_epi32(0xCCCC, iacc_mat_10, _mm512_shuffle_epi32(iacc_mat_11, (_MM_PERM_ENUM)78)); + __m512i iacc_row_3 = _mm512_mask_blend_epi32(0xCCCC, _mm512_shuffle_epi32(iacc_mat_10, (_MM_PERM_ENUM)78), iacc_mat_11); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptr[b].d); + const __m256 row_scale_f32_ymm = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + const __m512 row_scale_f32 = _mm512_insertf32x8(_mm512_castps256_ps512(row_scale_f32_ymm), row_scale_f32_ymm, 1); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_0), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_1), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_2), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_3), _mm512_mul_ps(col_scale_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m512i iacc_row_min_0_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_1_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)170), mins_01); + __m512i iacc_row_min_2_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)0), mins_01); + __m512i iacc_row_min_3_01 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)170), mins_01); + + __m512i iacc_row_min_0_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_1_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_0123, (_MM_PERM_ENUM)255), mins_23); + __m512i iacc_row_min_2_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)85), mins_23); + __m512i iacc_row_min_3_23 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_0123, (_MM_PERM_ENUM)255), mins_23); + + __m512i iacc_row_min_0_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_1_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)170), mins_45); + __m512i iacc_row_min_2_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)0), mins_45); + __m512i iacc_row_min_3_45 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)170), mins_45); + + __m512i iacc_row_min_0_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_1_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_01_4567, (_MM_PERM_ENUM)255), mins_67); + __m512i iacc_row_min_2_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)85), mins_67); + __m512i iacc_row_min_3_67 = _mm512_madd_epi16(_mm512_shuffle_epi32(lhs_bsums_23_4567, (_MM_PERM_ENUM)255), mins_67); + + __m512i iacc_row_min_0 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm512_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m512i iacc_row_min_1 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm512_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m512i iacc_row_min_2 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm512_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m512i iacc_row_min_3 = _mm512_add_epi32(_mm512_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm512_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[0] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_0), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[0]); + acc_min_rows[1] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_1), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[1]); + acc_min_rows[2] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_2), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[2]); + acc_min_rows[3] = _mm512_fmadd_ps(_mm512_cvtepi32_ps(iacc_row_min_3), _mm512_mul_ps(col_dmin_f32, _mm512_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[3]); + } + } + // Store accumlated values + for (int i = 0; i < 4; i++) { + _mm512_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm512_sub_ps(acc_rows[i], acc_min_rows[i])); + } + } + } + + if (anc != nc) { + xstart = anc/8; + y = 0; + } + +#endif //AVX512F + + // Take group of four block_q8_Kx4 structures at each pass of the loop and perform dot product operation + for (; y < anr / 4; y += 4) { + + const block_q8_Kx4 * a_ptrs[4]; + + a_ptrs[0] = a_ptr_start + (y * nb); + for (int i = 0; i < 3; ++i) { + a_ptrs[i + 1] = a_ptrs[i] + nb; + } + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[16]; + for (int i = 0; i < 16; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + __m256 acc_min_rows[16]; + for (int i = 0; i < 16; i++) { + acc_min_rows[i] = _mm256_setzero_ps(); + } + + // For super block + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the eight scale values of block_q2_kx8 + const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + + // dmin values - Load the eight dmin values of block_q2_kx8 + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_K for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 224 + sb * 256)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + //superblock sub block which part of sub block + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + // 2-bit -> 8-bit + // First sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_00 = _mm256_and_si256(rhs_raw_mat_0145_0, m3b); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) + const __m256i rhs_mat_2367_00 = _mm256_and_si256(rhs_raw_mat_2367_0, m3b); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) + + const __m256i rhs_mat_0145_01 = _mm256_and_si256(rhs_raw_mat_0145_1, m3b); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) + const __m256i rhs_mat_2367_01 = _mm256_and_si256(rhs_raw_mat_2367_1, m3b); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) + + // Second sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_10 = _mm256_and_si256(rhs_raw_mat_0145_2, m3b); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) + const __m256i rhs_mat_2367_10 = _mm256_and_si256(rhs_raw_mat_2367_2, m3b); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) + + const __m256i rhs_mat_0145_11 = _mm256_and_si256(rhs_raw_mat_0145_3, m3b); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) + const __m256i rhs_mat_2367_11 = _mm256_and_si256(rhs_raw_mat_2367_3, m3b); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) + + // Third sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 2), m3b); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) + const __m256i rhs_mat_2367_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 2), m3b); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) + + const __m256i rhs_mat_0145_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 2), m3b); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) + const __m256i rhs_mat_2367_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 2), m3b); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) + + // Fourth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 2), m3b); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) + const __m256i rhs_mat_2367_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 2), m3b); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) + + const __m256i rhs_mat_0145_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 2), m3b); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) + const __m256i rhs_mat_2367_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 2), m3b); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) + + // Fifth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m3b); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) + const __m256i rhs_mat_2367_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m3b); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) + + const __m256i rhs_mat_0145_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m3b); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) + const __m256i rhs_mat_2367_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m3b); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) + + // Sixth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 4), m3b); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) + const __m256i rhs_mat_2367_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 4), m3b); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) + + const __m256i rhs_mat_0145_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 4), m3b); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) + const __m256i rhs_mat_2367_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 4), m3b); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) + + // Seventh sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 6), m3b); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) + const __m256i rhs_mat_2367_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 6), m3b); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_mat_0145_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 6), m3b); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) + const __m256i rhs_mat_2367_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 6), m3b); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) + + // Eighth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 6), m3b); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) + const __m256i rhs_mat_2367_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 6), m3b); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_mat_0145_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 6), m3b); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) + const __m256i rhs_mat_2367_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 6), m3b); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_00_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_00, 136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) + const __m256i rhs_mat_2367_00_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_00, 136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) + + const __m256i rhs_mat_0145_01_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_01, 136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) + const __m256i rhs_mat_2367_01_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_01, 136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) + + const __m256i rhs_mat_0145_10_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_10, 136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) + const __m256i rhs_mat_2367_10_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_10, 136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) + + const __m256i rhs_mat_0145_11_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_11, 136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) + const __m256i rhs_mat_2367_11_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_11, 136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) + + const __m256i rhs_mat_0145_20_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_20, 136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) + const __m256i rhs_mat_2367_20_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_20, 136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) + + const __m256i rhs_mat_0145_21_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_21, 136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) + const __m256i rhs_mat_2367_21_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_21, 136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) + + const __m256i rhs_mat_0145_30_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_30, 136); //B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) + const __m256i rhs_mat_2367_30_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_30, 136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) + + const __m256i rhs_mat_0145_31_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_31, 136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11 + const __m256i rhs_mat_2367_31_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_31, 136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) + + const __m256i rhs_mat_0145_40_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_40, 136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) + const __m256i rhs_mat_2367_40_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_40, 136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) + + const __m256i rhs_mat_0145_41_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_41, 136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) + const __m256i rhs_mat_2367_41_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_41, 136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) + + const __m256i rhs_mat_0145_50_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_50, 136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) + const __m256i rhs_mat_2367_50_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_50, 136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) + + const __m256i rhs_mat_0145_51_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_51, 136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) + const __m256i rhs_mat_2367_51_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_51, 136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) + + const __m256i rhs_mat_0145_60_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_60, 136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) + const __m256i rhs_mat_2367_60_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_60, 136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) + + const __m256i rhs_mat_0145_61_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_61, 136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) + const __m256i rhs_mat_2367_61_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_61, 136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) + + const __m256i rhs_mat_0145_70_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_70, 136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) + const __m256i rhs_mat_2367_70_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_70, 136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) + + const __m256i rhs_mat_0145_71_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_71, 136); //B70(8-11) B71(8-11) B70(8-11) B71(8-11) B74(8-11) B75(8-11) B74(8-11) B75(8-11) + const __m256i rhs_mat_2367_71_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_71, 136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) + + + // Shuffle pattern two - right side input + const __m256i rhs_mat_0145_00_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_00, 221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) + const __m256i rhs_mat_2367_00_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_00, 221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) + + const __m256i rhs_mat_0145_01_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_01, 221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) + const __m256i rhs_mat_2367_01_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_01, 221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) + + const __m256i rhs_mat_0145_10_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_10, 221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) + const __m256i rhs_mat_2367_10_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_10, 221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) + + const __m256i rhs_mat_0145_11_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_11, 221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) + const __m256i rhs_mat_2367_11_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_11, 221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) + + const __m256i rhs_mat_0145_20_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_20, 221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) + const __m256i rhs_mat_2367_20_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_20, 221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) + + const __m256i rhs_mat_0145_21_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_21, 221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) + const __m256i rhs_mat_2367_21_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_21, 221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) + + const __m256i rhs_mat_0145_30_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_30, 221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) + const __m256i rhs_mat_2367_30_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_30, 221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) + + const __m256i rhs_mat_0145_31_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_31, 221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) + const __m256i rhs_mat_2367_31_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_31, 221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) + + const __m256i rhs_mat_0145_40_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_40, 221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) + const __m256i rhs_mat_2367_40_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_40, 221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) + + const __m256i rhs_mat_0145_41_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_41, 221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) + const __m256i rhs_mat_2367_41_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_41, 221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) + + const __m256i rhs_mat_0145_50_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_50, 221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) + const __m256i rhs_mat_2367_50_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_50, 221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) + + const __m256i rhs_mat_0145_51_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_51, 221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) + const __m256i rhs_mat_2367_51_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_51, 221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) + + const __m256i rhs_mat_0145_60_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_60, 221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) + const __m256i rhs_mat_2367_60_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_60, 221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) + + const __m256i rhs_mat_0145_61_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_61, 221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) + const __m256i rhs_mat_2367_61_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_61, 221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) + + const __m256i rhs_mat_0145_70_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_70, 221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) + const __m256i rhs_mat_2367_70_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_70, 221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) + + const __m256i rhs_mat_0145_71_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_71, 221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) + const __m256i rhs_mat_2367_71_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_71, 221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + const __m256i scales_0 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask1_sse)); + const __m256i scales_1 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask2_sse)); + + const __m256i scales_2 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask1_sse)); + const __m256i scales_3 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask2_sse)); + + const __m256i scales_4 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask1_sse)); + const __m256i scales_5 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask2_sse)); + + const __m256i scales_6 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask1_sse)); + const __m256i scales_7 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask2_sse)); + + const __m256i scale_0145_0 = _mm256_shuffle_epi32(scales_0, 68); + const __m256i scale_2367_0 = _mm256_shuffle_epi32(scales_0, 238); + + const __m256i scale_0145_1 = _mm256_shuffle_epi32(scales_1, 68); + const __m256i scale_2367_1 = _mm256_shuffle_epi32(scales_1, 238); + + const __m256i scale_0145_2 = _mm256_shuffle_epi32(scales_2, 68); + const __m256i scale_2367_2 = _mm256_shuffle_epi32(scales_2, 238); + + const __m256i scale_0145_3 = _mm256_shuffle_epi32(scales_3, 68); + const __m256i scale_2367_3 = _mm256_shuffle_epi32(scales_3, 238); + + const __m256i scale_0145_4 = _mm256_shuffle_epi32(scales_4, 68); + const __m256i scale_2367_4 = _mm256_shuffle_epi32(scales_4, 238); + + const __m256i scale_0145_5 = _mm256_shuffle_epi32(scales_5, 68); + const __m256i scale_2367_5 = _mm256_shuffle_epi32(scales_5, 238); + + const __m256i scale_0145_6 = _mm256_shuffle_epi32(scales_6, 68); + const __m256i scale_2367_6 = _mm256_shuffle_epi32(scales_6, 238); + + const __m256i scale_0145_7 = _mm256_shuffle_epi32(scales_7, 68); + const __m256i scale_2367_7 = _mm256_shuffle_epi32(scales_7, 238); + + + for (int rp = 0; rp < 4; rp++) { + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 512 * sb))); + __m256i lhs_mat_01_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 0); + __m256i lhs_mat_23_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 17); + __m256i lhs_mat_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 32 + 512 * sb))); + __m256i lhs_mat_01_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 0); + __m256i lhs_mat_23_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 17); + __m256i lhs_mat_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 64 + 512 * sb))); + __m256i lhs_mat_01_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 0); + __m256i lhs_mat_23_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 17); + __m256i lhs_mat_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 96 + 512 * sb))); + __m256i lhs_mat_01_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 0); + __m256i lhs_mat_23_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 17); + __m256i lhs_mat_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 128 + 512 * sb))); + __m256i lhs_mat_01_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 0); + __m256i lhs_mat_23_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 17); + __m256i lhs_mat_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 160 + 512 * sb))); + __m256i lhs_mat_01_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 0); + __m256i lhs_mat_23_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 17); + __m256i lhs_mat_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 192 + 512 * sb))); + __m256i lhs_mat_01_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 0); + __m256i lhs_mat_23_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 17); + __m256i lhs_mat_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 224 + 512 * sb))); + __m256i lhs_mat_01_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 0); + __m256i lhs_mat_23_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 17); + + __m256i lhs_mat_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 256 + 512 * sb))); + __m256i lhs_mat_01_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 0); + __m256i lhs_mat_23_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 17); + __m256i lhs_mat_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 288 + 512 * sb))); + __m256i lhs_mat_01_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 0); + __m256i lhs_mat_23_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 17); + __m256i lhs_mat_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 320 + 512 * sb))); + __m256i lhs_mat_01_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 0); + __m256i lhs_mat_23_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 17); + __m256i lhs_mat_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 352 + 512 * sb))); + __m256i lhs_mat_01_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 0); + __m256i lhs_mat_23_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 17); + __m256i lhs_mat_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 384 + 512 * sb))); + __m256i lhs_mat_01_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 0); + __m256i lhs_mat_23_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 17); + __m256i lhs_mat_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 416 + 512 * sb))); + __m256i lhs_mat_01_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 0); + __m256i lhs_mat_23_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 17); + __m256i lhs_mat_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 448 + 512 * sb))); + __m256i lhs_mat_01_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 0); + __m256i lhs_mat_23_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 17); + __m256i lhs_mat_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptrs[rp][b].qs + 480 + 512 * sb))); + __m256i lhs_mat_01_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 0); + __m256i lhs_mat_23_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 17); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptrs[rp][b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptrs[rp][b].bsums + 24 + 32 * sb)); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_00_sp1 = _mm256_shuffle_epi32(lhs_mat_01_00, 160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m256i lhs_mat_23_00_sp1 = _mm256_shuffle_epi32(lhs_mat_23_00, 160); //A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) + + const __m256i lhs_mat_01_01_sp1 = _mm256_shuffle_epi32(lhs_mat_01_01, 160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m256i lhs_mat_23_01_sp1 = _mm256_shuffle_epi32(lhs_mat_23_01, 160); //A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) + + const __m256i lhs_mat_01_10_sp1 = _mm256_shuffle_epi32(lhs_mat_01_10, 160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m256i lhs_mat_23_10_sp1 = _mm256_shuffle_epi32(lhs_mat_23_10, 160); //A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) + + const __m256i lhs_mat_01_11_sp1 = _mm256_shuffle_epi32(lhs_mat_01_11, 160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m256i lhs_mat_23_11_sp1 = _mm256_shuffle_epi32(lhs_mat_23_11, 160); //A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) + + const __m256i lhs_mat_01_20_sp1 = _mm256_shuffle_epi32(lhs_mat_01_20, 160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m256i lhs_mat_23_20_sp1 = _mm256_shuffle_epi32(lhs_mat_23_20, 160); //A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) + + const __m256i lhs_mat_01_21_sp1 = _mm256_shuffle_epi32(lhs_mat_01_21, 160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m256i lhs_mat_23_21_sp1 = _mm256_shuffle_epi32(lhs_mat_23_21, 160); //A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) + + const __m256i lhs_mat_01_30_sp1 = _mm256_shuffle_epi32(lhs_mat_01_30, 160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m256i lhs_mat_23_30_sp1 = _mm256_shuffle_epi32(lhs_mat_23_30, 160); //A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) + + const __m256i lhs_mat_01_31_sp1 = _mm256_shuffle_epi32(lhs_mat_01_31, 160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m256i lhs_mat_23_31_sp1 = _mm256_shuffle_epi32(lhs_mat_23_31, 160); //A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) + + const __m256i lhs_mat_01_40_sp1 = _mm256_shuffle_epi32(lhs_mat_01_40, 160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m256i lhs_mat_23_40_sp1 = _mm256_shuffle_epi32(lhs_mat_23_40, 160); //A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) + + const __m256i lhs_mat_01_41_sp1 = _mm256_shuffle_epi32(lhs_mat_01_41, 160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m256i lhs_mat_23_41_sp1 = _mm256_shuffle_epi32(lhs_mat_23_41, 160); //A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) + + const __m256i lhs_mat_01_50_sp1 = _mm256_shuffle_epi32(lhs_mat_01_50, 160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m256i lhs_mat_23_50_sp1 = _mm256_shuffle_epi32(lhs_mat_23_50, 160); //A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) + + const __m256i lhs_mat_01_51_sp1 = _mm256_shuffle_epi32(lhs_mat_01_51, 160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m256i lhs_mat_23_51_sp1 = _mm256_shuffle_epi32(lhs_mat_23_51, 160); //A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) + + const __m256i lhs_mat_01_60_sp1 = _mm256_shuffle_epi32(lhs_mat_01_60, 160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m256i lhs_mat_23_60_sp1 = _mm256_shuffle_epi32(lhs_mat_23_60, 160); //A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) + + const __m256i lhs_mat_01_61_sp1 = _mm256_shuffle_epi32(lhs_mat_01_61, 160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m256i lhs_mat_23_61_sp1 = _mm256_shuffle_epi32(lhs_mat_23_61, 160); //A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) + + const __m256i lhs_mat_01_70_sp1 = _mm256_shuffle_epi32(lhs_mat_01_70, 160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m256i lhs_mat_23_70_sp1 = _mm256_shuffle_epi32(lhs_mat_23_70, 160); //A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) + + const __m256i lhs_mat_01_71_sp1 = _mm256_shuffle_epi32(lhs_mat_01_71, 160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m256i lhs_mat_23_71_sp1 = _mm256_shuffle_epi32(lhs_mat_23_71, 160); //A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) + + // Shuffle pattern two- left side input + const __m256i lhs_mat_01_00_sp2 = _mm256_shuffle_epi32(lhs_mat_01_00, 245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m256i lhs_mat_23_00_sp2 = _mm256_shuffle_epi32(lhs_mat_23_00, 245); //A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) + + const __m256i lhs_mat_01_01_sp2 = _mm256_shuffle_epi32(lhs_mat_01_01, 245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m256i lhs_mat_23_01_sp2 = _mm256_shuffle_epi32(lhs_mat_23_01, 245); //A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) + + const __m256i lhs_mat_01_10_sp2 = _mm256_shuffle_epi32(lhs_mat_01_10, 245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m256i lhs_mat_23_10_sp2 = _mm256_shuffle_epi32(lhs_mat_23_10, 245); //A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) + + const __m256i lhs_mat_01_11_sp2 = _mm256_shuffle_epi32(lhs_mat_01_11, 245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m256i lhs_mat_23_11_sp2 = _mm256_shuffle_epi32(lhs_mat_23_11, 245); //A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) + + const __m256i lhs_mat_01_20_sp2 = _mm256_shuffle_epi32(lhs_mat_01_20, 245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m256i lhs_mat_23_20_sp2 = _mm256_shuffle_epi32(lhs_mat_23_20, 245); //A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) + + const __m256i lhs_mat_01_21_sp2 = _mm256_shuffle_epi32(lhs_mat_01_21, 245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m256i lhs_mat_23_21_sp2 = _mm256_shuffle_epi32(lhs_mat_23_21, 245); //A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) + + const __m256i lhs_mat_01_30_sp2 = _mm256_shuffle_epi32(lhs_mat_01_30, 245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m256i lhs_mat_23_30_sp2 = _mm256_shuffle_epi32(lhs_mat_23_30, 245); //A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) + + const __m256i lhs_mat_01_31_sp2 = _mm256_shuffle_epi32(lhs_mat_01_31, 245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m256i lhs_mat_23_31_sp2 = _mm256_shuffle_epi32(lhs_mat_23_31, 245); //A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) + + const __m256i lhs_mat_01_40_sp2 = _mm256_shuffle_epi32(lhs_mat_01_40, 245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m256i lhs_mat_23_40_sp2 = _mm256_shuffle_epi32(lhs_mat_23_40, 245); //A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) + + const __m256i lhs_mat_01_41_sp2 = _mm256_shuffle_epi32(lhs_mat_01_41, 245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m256i lhs_mat_23_41_sp2 = _mm256_shuffle_epi32(lhs_mat_23_41, 245); //A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) + + const __m256i lhs_mat_01_50_sp2 = _mm256_shuffle_epi32(lhs_mat_01_50, 245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m256i lhs_mat_23_50_sp2 = _mm256_shuffle_epi32(lhs_mat_23_50, 245); //A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) + + const __m256i lhs_mat_01_51_sp2 = _mm256_shuffle_epi32(lhs_mat_01_51, 245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m256i lhs_mat_23_51_sp2 = _mm256_shuffle_epi32(lhs_mat_23_51, 245); //A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) + + const __m256i lhs_mat_01_60_sp2 = _mm256_shuffle_epi32(lhs_mat_01_60, 245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m256i lhs_mat_23_60_sp2 = _mm256_shuffle_epi32(lhs_mat_23_60, 245); //A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) + + const __m256i lhs_mat_01_61_sp2 = _mm256_shuffle_epi32(lhs_mat_01_61, 245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m256i lhs_mat_23_61_sp2 = _mm256_shuffle_epi32(lhs_mat_23_61, 245); //A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) + + const __m256i lhs_mat_01_70_sp2 = _mm256_shuffle_epi32(lhs_mat_01_70, 245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m256i lhs_mat_23_70_sp2 = _mm256_shuffle_epi32(lhs_mat_23_70, 245); //A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) + + const __m256i lhs_mat_01_71_sp2 = _mm256_shuffle_epi32(lhs_mat_01_71, 245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m256i lhs_mat_23_71_sp2 = _mm256_shuffle_epi32(lhs_mat_23_71, 245); //A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m256i iacc_mat_00_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_01_01_sp1)); + __m256i iacc_mat_01_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_01_01_sp1)); + + __m256i iacc_mat_10_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_23_01_sp1)); + __m256i iacc_mat_11_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_23_01_sp1)); + + __m256i iacc_mat_00_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_01_11_sp1)); + __m256i iacc_mat_01_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_01_11_sp1)); + + __m256i iacc_mat_10_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_23_11_sp1)); + __m256i iacc_mat_11_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_23_11_sp1)); + + __m256i iacc_mat_00_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_01_21_sp1)); + __m256i iacc_mat_01_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_01_21_sp1)); + + __m256i iacc_mat_10_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_23_21_sp1)); + __m256i iacc_mat_11_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_23_21_sp1)); + + __m256i iacc_mat_00_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_01_31_sp1)); + __m256i iacc_mat_01_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_01_31_sp1)); + + __m256i iacc_mat_10_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_23_31_sp1)); + __m256i iacc_mat_11_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_23_31_sp1)); + + __m256i iacc_mat_00_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_01_41_sp1)); + __m256i iacc_mat_01_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_01_41_sp1)); + + __m256i iacc_mat_10_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_23_41_sp1)); + __m256i iacc_mat_11_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_23_41_sp1)); + + __m256i iacc_mat_00_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_01_51_sp1)); + __m256i iacc_mat_01_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_01_51_sp1)); + + __m256i iacc_mat_10_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_23_51_sp1)); + __m256i iacc_mat_11_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_23_51_sp1)); + + __m256i iacc_mat_00_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_01_61_sp1)); + __m256i iacc_mat_01_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_01_61_sp1)); + + __m256i iacc_mat_10_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_23_61_sp1)); + __m256i iacc_mat_11_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_23_61_sp1)); + + __m256i iacc_mat_00_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_01_71_sp1)); + __m256i iacc_mat_01_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_01_71_sp1)); + + __m256i iacc_mat_10_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_23_71_sp1)); + __m256i iacc_mat_11_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_23_71_sp1)); + + + __m256i iacc_mat_00_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_01_01_sp2)); + __m256i iacc_mat_01_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_01_01_sp2)); + + __m256i iacc_mat_10_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_23_01_sp2)); + __m256i iacc_mat_11_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_23_01_sp2)); + + __m256i iacc_mat_00_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_01_11_sp2)); + __m256i iacc_mat_01_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_01_11_sp2)); + + __m256i iacc_mat_10_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_23_11_sp2)); + __m256i iacc_mat_11_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_23_11_sp2)); + + __m256i iacc_mat_00_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_01_21_sp2)); + __m256i iacc_mat_01_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_01_21_sp2)); + + __m256i iacc_mat_10_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_23_21_sp2)); + __m256i iacc_mat_11_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_23_21_sp2)); + + __m256i iacc_mat_00_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_01_31_sp2)); + __m256i iacc_mat_01_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_01_31_sp2)); + + __m256i iacc_mat_10_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_23_31_sp2)); + __m256i iacc_mat_11_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_23_31_sp2)); + + __m256i iacc_mat_00_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_01_41_sp2)); + __m256i iacc_mat_01_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_01_41_sp2)); + + __m256i iacc_mat_10_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_23_41_sp2)); + __m256i iacc_mat_11_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_23_41_sp2)); + + __m256i iacc_mat_00_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_01_51_sp2)); + __m256i iacc_mat_01_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_01_51_sp2)); + + __m256i iacc_mat_10_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_23_51_sp2)); + __m256i iacc_mat_11_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_23_51_sp2)); + + __m256i iacc_mat_00_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_01_61_sp2)); + __m256i iacc_mat_01_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_01_61_sp2)); + + __m256i iacc_mat_10_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_23_61_sp2)); + __m256i iacc_mat_11_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_23_61_sp2)); + + __m256i iacc_mat_00_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_01_71_sp2)); + __m256i iacc_mat_01_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_01_71_sp2)); + + __m256i iacc_mat_10_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_23_71_sp2)); + __m256i iacc_mat_11_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block + __m256i iacc_mat_00_0 = _mm256_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m256i iacc_mat_01_0 = _mm256_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m256i iacc_mat_10_0 = _mm256_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m256i iacc_mat_11_0 = _mm256_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m256i iacc_mat_00_1 = _mm256_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m256i iacc_mat_01_1 = _mm256_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m256i iacc_mat_10_1 = _mm256_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m256i iacc_mat_11_1 = _mm256_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m256i iacc_mat_00_2 = _mm256_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m256i iacc_mat_01_2 = _mm256_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m256i iacc_mat_10_2 = _mm256_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m256i iacc_mat_11_2 = _mm256_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m256i iacc_mat_00_3 = _mm256_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m256i iacc_mat_01_3 = _mm256_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m256i iacc_mat_10_3 = _mm256_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m256i iacc_mat_11_3 = _mm256_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m256i iacc_mat_00_4 = _mm256_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m256i iacc_mat_01_4 = _mm256_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m256i iacc_mat_10_4 = _mm256_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m256i iacc_mat_11_4 = _mm256_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m256i iacc_mat_00_5 = _mm256_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m256i iacc_mat_01_5 = _mm256_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m256i iacc_mat_10_5 = _mm256_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m256i iacc_mat_11_5 = _mm256_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m256i iacc_mat_00_6 = _mm256_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m256i iacc_mat_01_6 = _mm256_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m256i iacc_mat_10_6 = _mm256_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m256i iacc_mat_11_6 = _mm256_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m256i iacc_mat_00_7 = _mm256_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m256i iacc_mat_01_7 = _mm256_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m256i iacc_mat_10_7 = _mm256_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m256i iacc_mat_11_7 = _mm256_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm256_madd_epi16(iacc_mat_00_0, scale_0145_0); + iacc_mat_01_0 = _mm256_madd_epi16(iacc_mat_01_0, scale_2367_0); + iacc_mat_10_0 = _mm256_madd_epi16(iacc_mat_10_0, scale_0145_0); + iacc_mat_11_0 = _mm256_madd_epi16(iacc_mat_11_0, scale_2367_0); + + iacc_mat_00_1 = _mm256_madd_epi16(iacc_mat_00_1, scale_0145_1); + iacc_mat_01_1 = _mm256_madd_epi16(iacc_mat_01_1, scale_2367_1); + iacc_mat_10_1 = _mm256_madd_epi16(iacc_mat_10_1, scale_0145_1); + iacc_mat_11_1 = _mm256_madd_epi16(iacc_mat_11_1, scale_2367_1); + + iacc_mat_00_2 = _mm256_madd_epi16(iacc_mat_00_2, scale_0145_2); + iacc_mat_01_2 = _mm256_madd_epi16(iacc_mat_01_2, scale_2367_2); + iacc_mat_10_2 = _mm256_madd_epi16(iacc_mat_10_2, scale_0145_2); + iacc_mat_11_2 = _mm256_madd_epi16(iacc_mat_11_2, scale_2367_2); + + iacc_mat_00_3 = _mm256_madd_epi16(iacc_mat_00_3, scale_0145_3); + iacc_mat_01_3 = _mm256_madd_epi16(iacc_mat_01_3, scale_2367_3); + iacc_mat_10_3 = _mm256_madd_epi16(iacc_mat_10_3, scale_0145_3); + iacc_mat_11_3 = _mm256_madd_epi16(iacc_mat_11_3, scale_2367_3); + + iacc_mat_00_4 = _mm256_madd_epi16(iacc_mat_00_4, scale_0145_4); + iacc_mat_01_4 = _mm256_madd_epi16(iacc_mat_01_4, scale_2367_4); + iacc_mat_10_4 = _mm256_madd_epi16(iacc_mat_10_4, scale_0145_4); + iacc_mat_11_4 = _mm256_madd_epi16(iacc_mat_11_4, scale_2367_4); + + iacc_mat_00_5 = _mm256_madd_epi16(iacc_mat_00_5, scale_0145_5); + iacc_mat_01_5 = _mm256_madd_epi16(iacc_mat_01_5, scale_2367_5); + iacc_mat_10_5 = _mm256_madd_epi16(iacc_mat_10_5, scale_0145_5); + iacc_mat_11_5 = _mm256_madd_epi16(iacc_mat_11_5, scale_2367_5); + + iacc_mat_00_6 = _mm256_madd_epi16(iacc_mat_00_6, scale_0145_6); + iacc_mat_01_6 = _mm256_madd_epi16(iacc_mat_01_6, scale_2367_6); + iacc_mat_10_6 = _mm256_madd_epi16(iacc_mat_10_6, scale_0145_6); + iacc_mat_11_6 = _mm256_madd_epi16(iacc_mat_11_6, scale_2367_6); + + iacc_mat_00_7 = _mm256_madd_epi16(iacc_mat_00_7, scale_0145_7); + iacc_mat_01_7 = _mm256_madd_epi16(iacc_mat_01_7, scale_2367_7); + iacc_mat_10_7 = _mm256_madd_epi16(iacc_mat_10_7, scale_0145_7); + iacc_mat_11_7 = _mm256_madd_epi16(iacc_mat_11_7, scale_2367_7); + + __m256i iacc_mat_00 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm256_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm256_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m256i iacc_mat_01 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm256_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm256_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m256i iacc_mat_10 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm256_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm256_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m256i iacc_mat_11 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm256_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm256_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptrs[rp][b].d); + const __m256 row_scale_f32 = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[rp * 4]); + acc_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[rp * 4 + 1]); + acc_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[rp * 4 + 2]); + acc_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[rp * 4 + 3]); + + __m256i lhs_bsums_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m256i lhs_bsums_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m256i lhs_bsums_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m256i lhs_bsums_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m256i iacc_row_min_0_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 0), mins_01); + __m256i iacc_row_min_1_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 170), mins_01); + __m256i iacc_row_min_2_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 0), mins_01); + __m256i iacc_row_min_3_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 170), mins_01); + + __m256i iacc_row_min_0_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 85), mins_23); + __m256i iacc_row_min_1_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 255), mins_23); + __m256i iacc_row_min_2_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 85), mins_23); + __m256i iacc_row_min_3_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 255), mins_23); + + __m256i iacc_row_min_0_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 0), mins_45); + __m256i iacc_row_min_1_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 170), mins_45); + __m256i iacc_row_min_2_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 0), mins_45); + __m256i iacc_row_min_3_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 170), mins_45); + + __m256i iacc_row_min_0_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 85), mins_67); + __m256i iacc_row_min_1_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 255), mins_67); + __m256i iacc_row_min_2_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 85), mins_67); + __m256i iacc_row_min_3_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 255), mins_67); + + __m256i iacc_row_min_0 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm256_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m256i iacc_row_min_1 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm256_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m256i iacc_row_min_2 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm256_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m256i iacc_row_min_3 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm256_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[rp * 4] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_0), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[rp * 4]); + acc_min_rows[rp * 4 + 1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_1), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[rp * 4 + 1]); + acc_min_rows[rp * 4 + 2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_2), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[rp * 4 + 2]); + acc_min_rows[rp * 4 + 3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_3), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[rp * 4 + 3]); + } } } - for (int m = 0; m < 4; m++) { - for (int j = 0; j < ncols_interleaved; j++) { - s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j] - sum_minf[m][j]; + // Store the accumulated values + for (int i = 0; i < 16; i++) { + _mm256_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm256_sub_ps(acc_rows[i], acc_min_rows[i])); + + } + } + } + + for (; y < nr / 4; y ++) { + + const block_q8_Kx4 * a_ptr = a_ptr_start + (y * nb); + + // Take group of eight block_q2_kx8 structures at each pass of the loop and perform dot product operation + for (int64_t x = xstart; x < nc / 8; x++) { + + const block_q2_Kx8 * b_ptr = b_ptr_start + (x * b_nb); + + // Master FP accumulators + __m256 acc_rows[4]; + for (int i = 0; i < 4; i++) { + acc_rows[i] = _mm256_setzero_ps(); + } + + __m256 acc_min_rows[4]; + for (int i = 0; i < 4; i++) { + acc_min_rows[i] = _mm256_setzero_ps(); + } + + for (int64_t b = 0; b < nb; b++) { + // Delta values - Load the eight scale values of block_q2_kx8 + const __m256 col_scale_f32 = GGML_F32Cx8_LOAD(b_ptr[b].d); + + // dmin values - Load the eight dmin values of block_q2_kx8 + const __m256 col_dmin_f32 = GGML_F32Cx8_LOAD(b_ptr[b].dmin); + + // Loop to iterate over the sixteen sub blocks of a super block - eight sub blocks are processed per iteration + for (int sb = 0; sb < QK_K / 128; sb++) { + + // Load the eight block_q2_k for eight sub blocks quantized values interleaved with each other in chunks of eight bytes - B0,B1 ....B6,B7 + const __m256i rhs_raw_mat_0123_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + sb * 256)); + const __m256i rhs_raw_mat_4567_0 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 32 + sb * 256)); + const __m256i rhs_raw_mat_0123_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 64 + sb * 256)); + const __m256i rhs_raw_mat_4567_1 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 96 + sb * 256)); + const __m256i rhs_raw_mat_0123_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 128 + sb * 256)); + const __m256i rhs_raw_mat_4567_2 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 160 + sb * 256)); + const __m256i rhs_raw_mat_0123_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 192 + sb * 256)); + const __m256i rhs_raw_mat_4567_3 = _mm256_loadu_si256((const __m256i *)(b_ptr[b].qs + 224 + sb * 256)); + + // Save the values in the following vectors in the formats B0B1B4B5, B2B3B6B7 for further processing and storing of values + //superblock sub block which part of sub block + const __m256i rhs_raw_mat_0145_0 = _mm256_blend_epi32(rhs_raw_mat_0123_0, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_0, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_0 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_0, requiredOrder), rhs_raw_mat_4567_0, 240); + + const __m256i rhs_raw_mat_0145_1 = _mm256_blend_epi32(rhs_raw_mat_0123_1, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_1, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_1 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_1, requiredOrder), rhs_raw_mat_4567_1, 240); + + const __m256i rhs_raw_mat_0145_2 = _mm256_blend_epi32(rhs_raw_mat_0123_2, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_2, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_2 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_2, requiredOrder), rhs_raw_mat_4567_2, 240); + + const __m256i rhs_raw_mat_0145_3 = _mm256_blend_epi32(rhs_raw_mat_0123_3, _mm256_permutevar8x32_epi32(rhs_raw_mat_4567_3, requiredOrder), 240); + const __m256i rhs_raw_mat_2367_3 = _mm256_blend_epi32(_mm256_permutevar8x32_epi32(rhs_raw_mat_0123_3, requiredOrder), rhs_raw_mat_4567_3, 240); + + // 2-bit -> 8-bit + // First sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_00 = _mm256_and_si256(rhs_raw_mat_0145_0, m3b); //B00(0-7) B01(0-7) B04(0-7) B05(0-7) + const __m256i rhs_mat_2367_00 = _mm256_and_si256(rhs_raw_mat_2367_0, m3b); //B02(0-7) B03(0-7) B06(0-7) B07(0-7) + + const __m256i rhs_mat_0145_01 = _mm256_and_si256(rhs_raw_mat_0145_1, m3b); //B00(8-15) B01(8-15) B04(8-15) B05(8-15) + const __m256i rhs_mat_2367_01 = _mm256_and_si256(rhs_raw_mat_2367_1, m3b); //B02(8-15) B03(8-15) B06(8-15) B07(8-15) + + // Second sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_10 = _mm256_and_si256(rhs_raw_mat_0145_2, m3b); //B10(0-7) B11(0-7) B14(0-7) B15(0-7) + const __m256i rhs_mat_2367_10 = _mm256_and_si256(rhs_raw_mat_2367_2, m3b); //B12(0-7) B13(0-7) B16(0-7) B17(0-7) + + const __m256i rhs_mat_0145_11 = _mm256_and_si256(rhs_raw_mat_0145_3, m3b); //B10(8-15) B11(8-15) B14(8-15) B15(8-15) + const __m256i rhs_mat_2367_11 = _mm256_and_si256(rhs_raw_mat_2367_3, m3b); //B12(8-15) B13(8-15) B16(8-15) B17(8-15) + + // Third sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 2), m3b); //B20(0-7) B21(0-7) B24(0-7) B25(0-7) + const __m256i rhs_mat_2367_20 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 2), m3b); //B22(0-7) B23(0-7) B26(0-7) B27(0-7) + + const __m256i rhs_mat_0145_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 2), m3b); //B20(8-15) B21(8-15) B24(8-15) B25(8-15) + const __m256i rhs_mat_2367_21 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 2), m3b); //B22(8-15) B23(8-15) B26(8-15) B27(8-15) + + // Fourth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 2), m3b); //B30(0-7) B31(0-7) B34(0-7) B35(0-7) + const __m256i rhs_mat_2367_30 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 2), m3b); //B32(0-7) B33(0-7) B36(0-7) B37(0-7) + + const __m256i rhs_mat_0145_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 2), m3b); //B30(8-15) B31(8-15) B34(8-15) B35(8-15) + const __m256i rhs_mat_2367_31 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 2), m3b); //B32(8-15) B33(8-15) B36(8-15) B37(8-15) + + // Fifth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 4), m3b); //B40(0-7) B41(0-7) B44(0-7) B45(0-7) + const __m256i rhs_mat_2367_40 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 4), m3b); //B42(0-7) B43(0-7) B46(0-7) B47(0-7) + + const __m256i rhs_mat_0145_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 4), m3b); //B40(8-15) B41(8-15) B44(8-15) B45(8-15) + const __m256i rhs_mat_2367_41 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 4), m3b); //B42(8-15) B43(8-15) B46(8-15) B47(8-15) + + // Sixth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 4), m3b); //B50(0-7) B51(0-7) B54(0-7) B55(0-7) + const __m256i rhs_mat_2367_50 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 4), m3b); //B52(0-7) B53(0-7) B56(0-7) B57(0-7) + + const __m256i rhs_mat_0145_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 4), m3b); //B50(8-15) B51(8-15) B54(8-15) B55(8-15) + const __m256i rhs_mat_2367_51 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 4), m3b); //B52(8-15) B53(8-15) B56(8-15) B57(8-15) + + // Seventh sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_0, 6), m3b); //B60(0-7) B61(0-7) B64(0-7) B65(0-7) + const __m256i rhs_mat_2367_60 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_0, 6), m3b); //B62(0-7) B63(0-7) B66(0-7) B67(0-7) + + const __m256i rhs_mat_0145_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_1, 6), m3b); //B60(8-15) B61(8-15) B64(8-15) B65(8-15) + const __m256i rhs_mat_2367_61 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_1, 6), m3b); //B62(8-15) B63(8-15) B66(8-15) B67(8-15) + + // Eighth sub block of the eight sub blocks processed in the iteration + const __m256i rhs_mat_0145_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_2, 6), m3b); //B70(0-7) B71(0-7) B74(0-7) B75(0-7) + const __m256i rhs_mat_2367_70 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_2, 6), m3b); //B72(0-7) B73(0-7) B76(0-7) B77(0-7) + + const __m256i rhs_mat_0145_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_0145_3, 6), m3b); //B70(8-15) B71(8-15) B74(8-15) B75(8-15) + const __m256i rhs_mat_2367_71 = _mm256_and_si256(_mm256_srli_epi16(rhs_raw_mat_2367_3, 6), m3b); //B72(8-15) B73(8-15) B76(8-15) B77(8-15) + + // Shuffle pattern one - right side input + const __m256i rhs_mat_0145_00_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_00, 136); //B00(0-3) B01(0-3) B00(0-3) B01(0-3) B04(0-3) B05(0-3) B04(0-3) B05(0-3) + const __m256i rhs_mat_2367_00_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_00, 136); //B02(0-3) B03(0-3) B02(0-3) B03(0-3) B06(0-3) B07(0-3) B06(0-3) B07(0-3) + + const __m256i rhs_mat_0145_01_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_01, 136); //B00(8-11) B01(8-11) B00(8-11) B01(8-11) B04(8-11) B05(8-11) B04(8-11) B05(8-11) + const __m256i rhs_mat_2367_01_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_01, 136); //B02(8-11) B03(8-11) B02(8-11) B03(8-11) B06(8-11) B07(8-11) B06(8-11) B07(8-11) + + const __m256i rhs_mat_0145_10_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_10, 136); //B10(0-3) B11(0-3) B10(0-3) B11(0-3) B14(0-3) B15(0-3) B14(0-3) B15(0-3) + const __m256i rhs_mat_2367_10_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_10, 136); //B12(0-3) B13(0-3) B12(0-3) B13(0-3) B16(0-3) B17(0-3) B16(0-3) B17(0-3) + + const __m256i rhs_mat_0145_11_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_11, 136); //B10(8-11) B11(8-11) B10(8-11) B11(8-11) B14(8-11) B15(8-11) B14(8-11) B15(8-11) + const __m256i rhs_mat_2367_11_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_11, 136); //B12(8-11) B13(8-11) B12(8-11) B13(8-11) B16(8-11) B17(8-11) B16(8-11) B17(8-11) + + const __m256i rhs_mat_0145_20_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_20, 136); //B20(0-3) B21(0-3) B20(0-3) B21(0-3) B24(0-3) B25(0-3) B24(0-3) B25(0-3) + const __m256i rhs_mat_2367_20_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_20, 136); //B22(0-3) B23(0-3) B22(0-3) B23(0-3) B26(0-3) B27(0-3) B26(0-3) B27(0-3) + + const __m256i rhs_mat_0145_21_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_21, 136); //B20(8-11) B21(8-11) B20(8-11) B21(8-11) B24(8-11) B25(8-11) B24(8-11) B25(8-11) + const __m256i rhs_mat_2367_21_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_21, 136); //B22(8-11) B23(8-11) B22(8-11) B23(8-11) B26(8-11) B27(8-11) B26(8-11) B27(8-11) + + const __m256i rhs_mat_0145_30_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_30, 136); //B30(0-3) B31(0-3) B30(0-3) B31(0-3) B34(0-3) B35(0-3) B34(0-3) B35(0-3) + const __m256i rhs_mat_2367_30_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_30, 136); //B32(0-3) B33(0-3) B32(0-3) B33(0-3) B36(0-3) B37(0-3) B36(0-3) B37(0-3) + + const __m256i rhs_mat_0145_31_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_31, 136); //B30(8-11) B31(8-11) B30(8-11) B31(8-11) B34(8-11) B35(8-11) B34(8-11) B35(8-11 + const __m256i rhs_mat_2367_31_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_31, 136); //B32(8-11) B33(8-11) B32(8-11) B33(8-11) B36(8-11) B37(8-11) B36(8-11) B37(8-11) + + const __m256i rhs_mat_0145_40_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_40, 136); //B40(0-3) B41(0-3) B40(0-3) B41(0-3) B44(0-3) B45(0-3) B44(0-3) B45(0-3) + const __m256i rhs_mat_2367_40_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_40, 136); //B42(0-3) B43(0-3) B42(0-3) B43(0-3) B46(0-3) B47(0-3) B46(0-3) B47(0-3) + + const __m256i rhs_mat_0145_41_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_41, 136); //B40(8-11) B41(8-11) B40(8-11) B41(8-11) B44(8-11) B45(8-11) B44(8-11) B45(8-11) + const __m256i rhs_mat_2367_41_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_41, 136); //B42(8-11) B43(8-11) B42(8-11) B43(8-11) B46(8-11) B47(8-11) B46(8-11) B47(8-11) + + const __m256i rhs_mat_0145_50_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_50, 136); //B50(0-3) B51(0-3) B50(0-3) B51(0-3) B54(0-3) B55(0-3) B54(0-3) B55(0-3) + const __m256i rhs_mat_2367_50_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_50, 136); //B52(0-3) B53(0-3) B52(0-3) B53(0-3) B56(0-3) B57(0-3) B56(0-3) B57(0-3) + + const __m256i rhs_mat_0145_51_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_51, 136); //B50(8-11) B51(8-11) B50(8-11) B51(8-11) B54(8-11) B55(8-11) B54(8-11) B55(8-11) + const __m256i rhs_mat_2367_51_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_51, 136); //B52(8-11) B53(8-11) B52(8-11) B53(8-11) B56(8-11) B57(8-11) B56(8-11) B57(8-11) + + const __m256i rhs_mat_0145_60_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_60, 136); //B60(0-3) B61(0-3) B60(0-3) B61(0-3) B64(0-3) B65(0-3) B64(0-3) B65(0-3) + const __m256i rhs_mat_2367_60_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_60, 136); //B62(0-3) B63(0-3) B62(0-3) B63(0-3) B66(0-3) B67(0-3) B66(0-3) B67(0-3) + + const __m256i rhs_mat_0145_61_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_61, 136); //B60(8-11) B61(8-11) B60(8-11) B61(8-11) B64(8-11) B65(8-11) B64(8-11) B65(8-11) + const __m256i rhs_mat_2367_61_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_61, 136); //B62(8-11) B63(8-11) B62(8-11) B63(8-11) B66(8-11) B67(8-11) B66(8-11) B67(8-11) + + const __m256i rhs_mat_0145_70_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_70, 136); //B70(0-3) B71(0-3) B70(0-3) B71(0-3) B74(0-3) B75(0-3) B74(0-3) B75(0-3) + const __m256i rhs_mat_2367_70_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_70, 136); //B72(0-3) B73(0-3) B72(0-3) B73(0-3) B76(0-3) B77(0-3) B76(0-3) B77(0-3) + + const __m256i rhs_mat_0145_71_sp1 = _mm256_shuffle_epi32(rhs_mat_0145_71, 136); //B70(8-11) B71(8-11) B70(8-11) B71(8-11) B74(8-11) B75(8-11) B74(8-11) B75(8-11) + const __m256i rhs_mat_2367_71_sp1 = _mm256_shuffle_epi32(rhs_mat_2367_71, 136); //B72(8-11) B73(8-11) B72(8-11) B73(8-11) B76(8-11) B77(8-11) B76(8-11) B77(8-11) + + + // Shuffle pattern two - right side input + const __m256i rhs_mat_0145_00_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_00, 221); //B00(4-7) B01(4-7) B00(4-7) B01(4-7) B04(4-7) B05(4-7) B04(4-7) B05(4-7) + const __m256i rhs_mat_2367_00_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_00, 221); //B02(4-7) B03(4-7) B02(4-7) B03(4-7) B06(4-7) B07(4-7) B06(4-7) B07(4-7) + + const __m256i rhs_mat_0145_01_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_01, 221); //B00(12-15) B01(12-15) B00(12-15) B01(12-15) B04(12-15) B05(12-15) B04(12-15) B05(12-15) + const __m256i rhs_mat_2367_01_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_01, 221); //B02(12-15) B03(12-15) B02(12-15) B03(12-15) B06(12-15) B07(12-15) B06(12-15) B07(12-15) + + const __m256i rhs_mat_0145_10_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_10, 221); //B10(4-7) B11(4-7) B10(4-7) B11(4-7) B14(4-7) B15(4-7) B14(4-7) B15(4-7) + const __m256i rhs_mat_2367_10_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_10, 221); //B12(4-7) B13(4-7) B12(4-7) B13(4-7) B16(4-7) B17(4-7) B16(4-7) B17(4-7) + + const __m256i rhs_mat_0145_11_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_11, 221); //B10(12-15) B11(12-15) B10(12-15) B11(12-15) B14(12-15) B15(12-15) B14(12-15) B15(12-15) + const __m256i rhs_mat_2367_11_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_11, 221); //B12(12-15) B13(12-15) B12(12-15) B13(12-15) B16(12-15) B17(12-15) B16(12-15) B17(12-15) + + const __m256i rhs_mat_0145_20_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_20, 221); //B20(4-7) B21(4-7) B20(4-7) B21(4-7) B24(4-7) B25(4-7) B24(4-7) B25(4-7) + const __m256i rhs_mat_2367_20_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_20, 221); //B22(4-7) B23(4-7) B22(4-7) B23(4-7) B26(4-7) B27(4-7) B26(4-7) B27(4-7) + + const __m256i rhs_mat_0145_21_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_21, 221); //B20(12-15) B21(12-15) B20(12-15) B21(12-15) B24(12-15) B25(12-15) B24(12-15) B25(12-15) + const __m256i rhs_mat_2367_21_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_21, 221); //B22(12-15) B23(12-15) B22(12-15) B23(12-15) B26(12-15) B27(12-15) B26(12-15) B27(12-15) + + const __m256i rhs_mat_0145_30_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_30, 221); //B30(4-7) B31(4-7) B30(4-7) B31(4-7) B34(4-7) B35(4-7) B34(4-7) B35(4-7) + const __m256i rhs_mat_2367_30_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_30, 221); //B32(4-7) B33(4-7) B32(4-7) B33(4-7) B36(4-7) B37(4-7) B36(4-7) B37(4-7) + + const __m256i rhs_mat_0145_31_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_31, 221); //B30(12-15) B31(12-15) B30(12-15) B31(12-15) B34(12-15) B35(12-15) B34(12-15) B35(12-15) + const __m256i rhs_mat_2367_31_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_31, 221); //B32(12-15) B33(12-15) B32(12-15) B33(12-15) B36(12-15) B37(12-15) B36(12-15) B37(12-15) + + const __m256i rhs_mat_0145_40_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_40, 221); //B40(4-7) B41(4-7) B40(4-7) B41(4-7) B44(4-7) B45(4-7) B44(4-7) B45(4-7) + const __m256i rhs_mat_2367_40_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_40, 221); //B42(4-7) B43(4-7) B42(4-7) B43(4-7) B46(4-7) B47(4-7) B46(4-7) B47(4-7) + + const __m256i rhs_mat_0145_41_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_41, 221); //B40(12-15) B41(12-15) B40(12-15) B41(12-15) B44(12-15) B45(12-15) B44(12-15) B45(12-15) + const __m256i rhs_mat_2367_41_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_41, 221); //B42(12-15) B43(12-15) B42(12-15) B43(12-15) B46(12-15) B47(12-15) B46(12-15) B47(12-15) + + const __m256i rhs_mat_0145_50_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_50, 221); //B50(4-7) B51(4-7) B50(4-7) B51(4-7) B54(4-7) B55(4-7) B54(4-7) B55(4-7) + const __m256i rhs_mat_2367_50_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_50, 221); //B52(4-7) B53(4-7) B52(4-7) B53(4-7) B56(4-7) B57(4-7) B56(4-7) B57(4-7) + + const __m256i rhs_mat_0145_51_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_51, 221); //B50(12-15) B51(12-15) B50(12-15) B51(12-15) B54(12-15) B55(12-15) B54(12-15) B55(12-15) + const __m256i rhs_mat_2367_51_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_51, 221); //B52(12-15) B53(12-15) B52(12-15) B53(12-15) B56(12-15) B57(12-15) B56(12-15) B57(12-15) + + const __m256i rhs_mat_0145_60_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_60, 221); //B60(4-7) B61(4-7) B60(4-7) B61(4-7) B64(4-7) B65(4-7) B64(4-7) B65(4-7) + const __m256i rhs_mat_2367_60_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_60, 221); //B62(4-7) B63(4-7) B62(4-7) B63(4-7) B66(4-7) B67(4-7) B66(4-7) B67(4-7) + + const __m256i rhs_mat_0145_61_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_61, 221); //B60(12-15) B61(12-15) B60(12-15) B61(12-15) B64(12-15) B65(12-15) B64(12-15) B65(12-15) + const __m256i rhs_mat_2367_61_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_61, 221); //B62(12-15) B63(12-15) B62(12-15) B63(12-15) B66(12-15) B67(12-15) B66(12-15) B67(12-15) + + const __m256i rhs_mat_0145_70_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_70, 221); //B70(4-7) B71(4-7) B70(4-7) B71(4-7) B74(4-7) B75(4-7) B74(4-7) B75(4-7) + const __m256i rhs_mat_2367_70_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_70, 221); //B72(4-7) B73(4-7) B72(4-7) B73(4-7) B76(4-7) B77(4-7) B76(4-7) B77(4-7) + + const __m256i rhs_mat_0145_71_sp2 = _mm256_shuffle_epi32(rhs_mat_0145_71, 221); //B70(12-15) B71(12-15) B70(12-15) B71(12-15) B74(12-15) B75(12-15) B74(12-15) B75(12-15) + const __m256i rhs_mat_2367_71_sp2 = _mm256_shuffle_epi32(rhs_mat_2367_71, 221); //B72(12-15) B73(12-15) B72(12-15) B73(12-15) B76(12-15) B77(12-15) B76(12-15) B77(12-15) + + + //Scales and Mins of corresponding sub blocks from different Q2_K structures are stored together + //s00 m00 s01 m01 s10 m10 s11 m11 s20 m20 s21 m21 s30 m30 s31 m31 s40 m40 s41 m41 s50 m50 s51 m51 s60 m60 s61 m61 s70 m70 s71 m71 + + // Combine mins and scales for sub-blocks: 0-1, 2-3, 4-5, 6-7 in the sb loop + const __m128i mins_and_scales_01 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + sb * 64)); + const __m128i mins_and_scales_23 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 16 + sb * 64)); + const __m128i mins_and_scales_45 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 32 + sb * 64)); + const __m128i mins_and_scales_67 = _mm_loadu_si128((const __m128i *)(b_ptr[b].scales + 48 + sb * 64)); + + // Extract scales which is lower half from mins_and_scales + const __m128i scales_01 = _mm_and_si128(mins_and_scales_01, m4b_sse); + const __m128i scales_23 = _mm_and_si128(mins_and_scales_23, m4b_sse); + const __m128i scales_45 = _mm_and_si128(mins_and_scales_45, m4b_sse); + const __m128i scales_67 = _mm_and_si128(mins_and_scales_67, m4b_sse); + + // Extract mins which is upper half from mins_and_scales + const __m256i mins_01 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_01, 4), m4b_sse)); + const __m256i mins_23 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_23, 4), m4b_sse)); + const __m256i mins_45 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_45, 4), m4b_sse)); + const __m256i mins_67 = _mm256_cvtepu8_epi16(_mm_and_si128(_mm_srli_epi16(mins_and_scales_67, 4), m4b_sse)); + + const __m256i scales_0 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask1_sse)); + const __m256i scales_1 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_01, scalesmask2_sse)); + + const __m256i scales_2 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask1_sse)); + const __m256i scales_3 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_23, scalesmask2_sse)); + + const __m256i scales_4 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask1_sse)); + const __m256i scales_5 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_45, scalesmask2_sse)); + + const __m256i scales_6 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask1_sse)); + const __m256i scales_7 = _mm256_cvtepu8_epi16(_mm_shuffle_epi8(scales_67, scalesmask2_sse)); + + const __m256i scale_0145_0 = _mm256_shuffle_epi32(scales_0, 68); + const __m256i scale_2367_0 = _mm256_shuffle_epi32(scales_0, 238); + + const __m256i scale_0145_1 = _mm256_shuffle_epi32(scales_1, 68); + const __m256i scale_2367_1 = _mm256_shuffle_epi32(scales_1, 238); + + const __m256i scale_0145_2 = _mm256_shuffle_epi32(scales_2, 68); + const __m256i scale_2367_2 = _mm256_shuffle_epi32(scales_2, 238); + + const __m256i scale_0145_3 = _mm256_shuffle_epi32(scales_3, 68); + const __m256i scale_2367_3 = _mm256_shuffle_epi32(scales_3, 238); + + const __m256i scale_0145_4 = _mm256_shuffle_epi32(scales_4, 68); + const __m256i scale_2367_4 = _mm256_shuffle_epi32(scales_4, 238); + + const __m256i scale_0145_5 = _mm256_shuffle_epi32(scales_5, 68); + const __m256i scale_2367_5 = _mm256_shuffle_epi32(scales_5, 238); + + const __m256i scale_0145_6 = _mm256_shuffle_epi32(scales_6, 68); + const __m256i scale_2367_6 = _mm256_shuffle_epi32(scales_6, 238); + + const __m256i scale_0145_7 = _mm256_shuffle_epi32(scales_7, 68); + const __m256i scale_2367_7 = _mm256_shuffle_epi32(scales_7, 238); + + // Load the four block_q8_k quantized values interleaved with each other in chunks of eight bytes - A0,A1,A2,A3 + // Loaded as set of 128 bit vectors and repeated into a 256 bit vector + __m256i lhs_mat_0123_00 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 512 * sb))); + __m256i lhs_mat_01_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 0); + __m256i lhs_mat_23_00 = _mm256_permute2f128_si256(lhs_mat_0123_00, lhs_mat_0123_00, 17); + __m256i lhs_mat_0123_01 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 32 + 512 * sb))); + __m256i lhs_mat_01_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 0); + __m256i lhs_mat_23_01 = _mm256_permute2f128_si256(lhs_mat_0123_01, lhs_mat_0123_01, 17); + __m256i lhs_mat_0123_10 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 64 + 512 * sb))); + __m256i lhs_mat_01_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 0); + __m256i lhs_mat_23_10 = _mm256_permute2f128_si256(lhs_mat_0123_10, lhs_mat_0123_10, 17); + __m256i lhs_mat_0123_11 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 96 + 512 * sb))); + __m256i lhs_mat_01_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 0); + __m256i lhs_mat_23_11 = _mm256_permute2f128_si256(lhs_mat_0123_11, lhs_mat_0123_11, 17); + __m256i lhs_mat_0123_20 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 128 + 512 * sb))); + __m256i lhs_mat_01_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 0); + __m256i lhs_mat_23_20 = _mm256_permute2f128_si256(lhs_mat_0123_20, lhs_mat_0123_20, 17); + __m256i lhs_mat_0123_21 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 160 + 512 * sb))); + __m256i lhs_mat_01_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 0); + __m256i lhs_mat_23_21 = _mm256_permute2f128_si256(lhs_mat_0123_21, lhs_mat_0123_21, 17); + __m256i lhs_mat_0123_30 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 192 + 512 * sb))); + __m256i lhs_mat_01_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 0); + __m256i lhs_mat_23_30 = _mm256_permute2f128_si256(lhs_mat_0123_30, lhs_mat_0123_30, 17); + __m256i lhs_mat_0123_31 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 224 + 512 * sb))); + __m256i lhs_mat_01_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 0); + __m256i lhs_mat_23_31 = _mm256_permute2f128_si256(lhs_mat_0123_31, lhs_mat_0123_31, 17); + + __m256i lhs_mat_0123_40 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 256 + 512 * sb))); + __m256i lhs_mat_01_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 0); + __m256i lhs_mat_23_40 = _mm256_permute2f128_si256(lhs_mat_0123_40, lhs_mat_0123_40, 17); + __m256i lhs_mat_0123_41 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 288 + 512 * sb))); + __m256i lhs_mat_01_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 0); + __m256i lhs_mat_23_41 = _mm256_permute2f128_si256(lhs_mat_0123_41, lhs_mat_0123_41, 17); + __m256i lhs_mat_0123_50 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 320 + 512 * sb))); + __m256i lhs_mat_01_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 0); + __m256i lhs_mat_23_50 = _mm256_permute2f128_si256(lhs_mat_0123_50, lhs_mat_0123_50, 17); + __m256i lhs_mat_0123_51 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 352 + 512 * sb))); + __m256i lhs_mat_01_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 0); + __m256i lhs_mat_23_51 = _mm256_permute2f128_si256(lhs_mat_0123_51, lhs_mat_0123_51, 17); + __m256i lhs_mat_0123_60 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 384 + 512 * sb))); + __m256i lhs_mat_01_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 0); + __m256i lhs_mat_23_60 = _mm256_permute2f128_si256(lhs_mat_0123_60, lhs_mat_0123_60, 17); + __m256i lhs_mat_0123_61 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 416 + 512 * sb))); + __m256i lhs_mat_01_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 0); + __m256i lhs_mat_23_61 = _mm256_permute2f128_si256(lhs_mat_0123_61, lhs_mat_0123_61, 17); + __m256i lhs_mat_0123_70 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 448 + 512 * sb))); + __m256i lhs_mat_01_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 0); + __m256i lhs_mat_23_70 = _mm256_permute2f128_si256(lhs_mat_0123_70, lhs_mat_0123_70, 17); + __m256i lhs_mat_0123_71 = _mm256_loadu_si256((const __m256i * )((a_ptr[b].qs + 480 + 512 * sb))); + __m256i lhs_mat_01_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 0); + __m256i lhs_mat_23_71 = _mm256_permute2f128_si256(lhs_mat_0123_71, lhs_mat_0123_71, 17); + + // Bsums are loaded for the different Q8_K blocks + __m128i lhs_raw_bsums_01_0123 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 32 * sb))); + __m128i lhs_raw_bsums_23_0123 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 8 + 32 * sb)); + __m128i lhs_raw_bsums_01_4567 = _mm_loadu_si128((const __m128i *)((a_ptr[b].bsums + 16 + 32 * sb))); + __m128i lhs_raw_bsums_23_4567 = _mm_loadu_si128((const __m128i *)(a_ptr[b].bsums + 24 + 32 * sb)); + + // Shuffle pattern one - left side input + const __m256i lhs_mat_01_00_sp1 = _mm256_shuffle_epi32(lhs_mat_01_00, 160); //A00(0-3) A00(0-3) A01(0-3) A01(0-3) A00(0-3) A00(0-3) A01(0-3) A01(0-3) + const __m256i lhs_mat_23_00_sp1 = _mm256_shuffle_epi32(lhs_mat_23_00, 160); //A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) A02(0-3) A03(0-3) + + const __m256i lhs_mat_01_01_sp1 = _mm256_shuffle_epi32(lhs_mat_01_01, 160); //A00(8-11) A00(8-11) A01(8-11) A01(8-11) A00(8-11) A00(8-11) A01(8-11) A01(8-11) + const __m256i lhs_mat_23_01_sp1 = _mm256_shuffle_epi32(lhs_mat_23_01, 160); //A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) A02(8-11) A03(8-11) + + const __m256i lhs_mat_01_10_sp1 = _mm256_shuffle_epi32(lhs_mat_01_10, 160); //A10(0-3) A10(0-3) A11(0-3) A11(0-3) A10(0-3) A10(0-3) A11(0-3) A11(0-3) + const __m256i lhs_mat_23_10_sp1 = _mm256_shuffle_epi32(lhs_mat_23_10, 160); //A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) A12(0-3) A13(0-3) + + const __m256i lhs_mat_01_11_sp1 = _mm256_shuffle_epi32(lhs_mat_01_11, 160); //A10(8-11) A10(8-11) A11(8-11) A11(8-11) A10(8-11) A10(8-11) A11(8-11) A11(8-11) + const __m256i lhs_mat_23_11_sp1 = _mm256_shuffle_epi32(lhs_mat_23_11, 160); //A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) A12(8-11) A13(8-11) + + const __m256i lhs_mat_01_20_sp1 = _mm256_shuffle_epi32(lhs_mat_01_20, 160); //A20(0-3) A20(0-3) A21(0-3) A21(0-3) A20(0-3) A20(0-3) A21(0-3) A21(0-3) + const __m256i lhs_mat_23_20_sp1 = _mm256_shuffle_epi32(lhs_mat_23_20, 160); //A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) A22(0-3) A23(0-3) + + const __m256i lhs_mat_01_21_sp1 = _mm256_shuffle_epi32(lhs_mat_01_21, 160); //A20(8-11) A20(8-11) A21(8-11) A21(8-11) A20(8-11) A20(8-11) A21(8-11) A21(8-11) + const __m256i lhs_mat_23_21_sp1 = _mm256_shuffle_epi32(lhs_mat_23_21, 160); //A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) A22(8-11) A23(8-11) + + const __m256i lhs_mat_01_30_sp1 = _mm256_shuffle_epi32(lhs_mat_01_30, 160); //A30(0-3) A30(0-3) A31(0-3) A31(0-3) A30(0-3) A30(0-3) A31(0-3) A31(0-3) + const __m256i lhs_mat_23_30_sp1 = _mm256_shuffle_epi32(lhs_mat_23_30, 160); //A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) A32(0-3) A33(0-3) + + const __m256i lhs_mat_01_31_sp1 = _mm256_shuffle_epi32(lhs_mat_01_31, 160); //A30(8-11) A30(8-11) A31(8-11) A31(8-11) A30(8-11) A30(8-11) A31(8-11) A31(8-11) + const __m256i lhs_mat_23_31_sp1 = _mm256_shuffle_epi32(lhs_mat_23_31, 160); //A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) A32(8-11) A33(8-11) + + const __m256i lhs_mat_01_40_sp1 = _mm256_shuffle_epi32(lhs_mat_01_40, 160); //A40(0-3) A40(0-3) A41(0-3) A41(0-3) A40(0-3) A40(0-3) A41(0-3) A41(0-3) + const __m256i lhs_mat_23_40_sp1 = _mm256_shuffle_epi32(lhs_mat_23_40, 160); //A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) A42(0-3) A43(0-3) + + const __m256i lhs_mat_01_41_sp1 = _mm256_shuffle_epi32(lhs_mat_01_41, 160); //A40(8-11) A40(8-11) A41(8-11) A41(8-11) A40(8-11) A40(8-11) A41(8-11) A41(8-11) + const __m256i lhs_mat_23_41_sp1 = _mm256_shuffle_epi32(lhs_mat_23_41, 160); //A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) A42(8-11) A43(8-11) + + const __m256i lhs_mat_01_50_sp1 = _mm256_shuffle_epi32(lhs_mat_01_50, 160); //A50(0-3) A50(0-3) A51(0-3) A51(0-3) A50(0-3) A50(0-3) A51(0-3) A51(0-3) + const __m256i lhs_mat_23_50_sp1 = _mm256_shuffle_epi32(lhs_mat_23_50, 160); //A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) A52(0-3) A53(0-3) + + const __m256i lhs_mat_01_51_sp1 = _mm256_shuffle_epi32(lhs_mat_01_51, 160); //A50(8-11) A50(8-11) A51(8-11) A51(8-11) A50(8-11) A50(8-11) A51(8-11) A51(8-11) + const __m256i lhs_mat_23_51_sp1 = _mm256_shuffle_epi32(lhs_mat_23_51, 160); //A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) A52(8-11) A53(8-11) + + const __m256i lhs_mat_01_60_sp1 = _mm256_shuffle_epi32(lhs_mat_01_60, 160); //A60(0-3) A60(0-3) A61(0-3) A61(0-3) A60(0-3) A60(0-3) A61(0-3) A61(0-3) + const __m256i lhs_mat_23_60_sp1 = _mm256_shuffle_epi32(lhs_mat_23_60, 160); //A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) A62(0-3) A63(0-3) + + const __m256i lhs_mat_01_61_sp1 = _mm256_shuffle_epi32(lhs_mat_01_61, 160); //A60(8-11) A60(8-11) A61(8-11) A61(8-11) A60(8-11) A60(8-11) A61(8-11) A61(8-11) + const __m256i lhs_mat_23_61_sp1 = _mm256_shuffle_epi32(lhs_mat_23_61, 160); //A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) A62(8-11) A63(8-11) + + const __m256i lhs_mat_01_70_sp1 = _mm256_shuffle_epi32(lhs_mat_01_70, 160); //A70(0-3) A70(0-3) A71(0-3) A71(0-3) A70(0-3) A70(0-3) A71(0-3) A71(0-3) + const __m256i lhs_mat_23_70_sp1 = _mm256_shuffle_epi32(lhs_mat_23_70, 160); //A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) A72(0-3) A73(0-3) + + const __m256i lhs_mat_01_71_sp1 = _mm256_shuffle_epi32(lhs_mat_01_71, 160); //A70(8-11) A70(8-11) A71(8-11) A71(8-11) A70(8-11) A70(8-11) A71(8-11) A71(8-11) + const __m256i lhs_mat_23_71_sp1 = _mm256_shuffle_epi32(lhs_mat_23_71, 160); //A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) A72(8-11) A73(8-11) + + // Shuffle pattern two- left side input + const __m256i lhs_mat_01_00_sp2 = _mm256_shuffle_epi32(lhs_mat_01_00, 245); //A00(4-7) A00(4-7) A01(4-7) A01(4-7) A00(4-7) A00(4-7) A01(4-7) A01(4-7) + const __m256i lhs_mat_23_00_sp2 = _mm256_shuffle_epi32(lhs_mat_23_00, 245); //A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) A02(4-7) A03(4-7) + + const __m256i lhs_mat_01_01_sp2 = _mm256_shuffle_epi32(lhs_mat_01_01, 245); //A00(12-15) A00(12-15) A01(12-15) A01(12-15) A00(12-15) A00(12-15) A01(12-15) A01(12-15) + const __m256i lhs_mat_23_01_sp2 = _mm256_shuffle_epi32(lhs_mat_23_01, 245); //A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) A02(12-15) A03(12-15) + + const __m256i lhs_mat_01_10_sp2 = _mm256_shuffle_epi32(lhs_mat_01_10, 245); //A10(4-7) A10(4-7) A11(4-7) A11(4-7) A10(4-7) A10(4-7) A11(4-7) A11(4-7) + const __m256i lhs_mat_23_10_sp2 = _mm256_shuffle_epi32(lhs_mat_23_10, 245); //A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) A12(4-7) A13(4-7) + + const __m256i lhs_mat_01_11_sp2 = _mm256_shuffle_epi32(lhs_mat_01_11, 245); //A10(12-15) A10(12-15) A11(12-15) A11(12-15) A10(12-15) A10(12-15) A11(12-15) A11(12-15) + const __m256i lhs_mat_23_11_sp2 = _mm256_shuffle_epi32(lhs_mat_23_11, 245); //A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) A12(12-15) A13(12-15) + + const __m256i lhs_mat_01_20_sp2 = _mm256_shuffle_epi32(lhs_mat_01_20, 245); //A20(4-7) A20(4-7) A21(4-7) A21(4-7) A20(4-7) A20(4-7) A21(4-7) A21(4-7) + const __m256i lhs_mat_23_20_sp2 = _mm256_shuffle_epi32(lhs_mat_23_20, 245); //A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) A22(4-7) A23(4-7) + + const __m256i lhs_mat_01_21_sp2 = _mm256_shuffle_epi32(lhs_mat_01_21, 245); //A20(12-15) A20(12-15) A21(12-15) A21(12-15) A20(12-15) A20(12-15) A21(12-15) A21(12-15) + const __m256i lhs_mat_23_21_sp2 = _mm256_shuffle_epi32(lhs_mat_23_21, 245); //A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) A22(12-15) A23(12-15) + + const __m256i lhs_mat_01_30_sp2 = _mm256_shuffle_epi32(lhs_mat_01_30, 245); //A30(4-7) A30(4-7) A31(4-7) A31(4-7) A30(4-7) A30(4-7) A31(4-7) A31(4-7) + const __m256i lhs_mat_23_30_sp2 = _mm256_shuffle_epi32(lhs_mat_23_30, 245); //A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) A32(4-7) A33(4-7) + + const __m256i lhs_mat_01_31_sp2 = _mm256_shuffle_epi32(lhs_mat_01_31, 245); //A30(12-15) A30(12-15) A31(12-15) A31(12-15) A30(12-15) A30(12-15) A31(12-15) A31(12-15) + const __m256i lhs_mat_23_31_sp2 = _mm256_shuffle_epi32(lhs_mat_23_31, 245); //A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) A32(12-15) A33(12-15) + + const __m256i lhs_mat_01_40_sp2 = _mm256_shuffle_epi32(lhs_mat_01_40, 245); //A40(4-7) A40(4-7) A41(4-7) A41(4-7) A40(4-7) A40(4-7) A41(4-7) A41(4-7) + const __m256i lhs_mat_23_40_sp2 = _mm256_shuffle_epi32(lhs_mat_23_40, 245); //A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) A42(4-7) A43(4-7) + + const __m256i lhs_mat_01_41_sp2 = _mm256_shuffle_epi32(lhs_mat_01_41, 245); //A40(12-15) A40(12-15) A41(12-15) A41(12-15) A40(12-15) A40(12-15) A41(12-15) A41(12-15) + const __m256i lhs_mat_23_41_sp2 = _mm256_shuffle_epi32(lhs_mat_23_41, 245); //A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) A42(12-15) A43(12-15) + + const __m256i lhs_mat_01_50_sp2 = _mm256_shuffle_epi32(lhs_mat_01_50, 245); //A50(4-7) A50(4-7) A51(4-7) A51(4-7) A50(4-7) A50(4-7) A51(4-7) A51(4-7) + const __m256i lhs_mat_23_50_sp2 = _mm256_shuffle_epi32(lhs_mat_23_50, 245); //A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) A52(4-7) A53(4-7) + + const __m256i lhs_mat_01_51_sp2 = _mm256_shuffle_epi32(lhs_mat_01_51, 245); //A50(12-15) A50(12-15) A51(12-15) A51(12-15) A50(12-15) A50(12-15) A51(12-15) A51(12-15) + const __m256i lhs_mat_23_51_sp2 = _mm256_shuffle_epi32(lhs_mat_23_51, 245); //A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) A52(12-15) A53(12-15) + + const __m256i lhs_mat_01_60_sp2 = _mm256_shuffle_epi32(lhs_mat_01_60, 245); //A60(4-7) A60(4-7) A61(4-7) A61(4-7) A60(4-7) A60(4-7) A61(4-7) A61(4-7) + const __m256i lhs_mat_23_60_sp2 = _mm256_shuffle_epi32(lhs_mat_23_60, 245); //A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) A62(4-7) A63(4-7) + + const __m256i lhs_mat_01_61_sp2 = _mm256_shuffle_epi32(lhs_mat_01_61, 245); //A60(12-15) A60(12-15) A61(12-15) A61(12-15) A60(12-15) A60(12-15) A61(12-15) A61(12-15) + const __m256i lhs_mat_23_61_sp2 = _mm256_shuffle_epi32(lhs_mat_23_61, 245); //A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) A62(12-15) A63(12-15) + + const __m256i lhs_mat_01_70_sp2 = _mm256_shuffle_epi32(lhs_mat_01_70, 245); //A70(4-7) A70(4-7) A71(4-7) A71(4-7) A70(4-7) A70(4-7) A71(4-7) A71(4-7) + const __m256i lhs_mat_23_70_sp2 = _mm256_shuffle_epi32(lhs_mat_23_70, 245); //A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) A72(4-7) A73(4-7) + + const __m256i lhs_mat_01_71_sp2 = _mm256_shuffle_epi32(lhs_mat_01_71, 245); //A70(12-15) A70(12-15) A71(12-15) A71(12-15) A70(12-15) A70(12-15) A71(12-15) A71(12-15) + const __m256i lhs_mat_23_71_sp2 = _mm256_shuffle_epi32(lhs_mat_23_71, 245); //A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) A72(12-15) A73(12-15) + + // The values arranged in shuffle patterns are operated with dot product operation within 32 bit lane i.e corresponding bytes and multiplied and added into 32 bit integers within 32 bit lane + __m256i iacc_mat_00_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_01_01_sp1)); + __m256i iacc_mat_01_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_01_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_01_01_sp1)); + + __m256i iacc_mat_10_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_0145_01_sp1, lhs_mat_23_01_sp1)); + __m256i iacc_mat_11_0_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp1, lhs_mat_23_00_sp1),_mm256_maddubs_epi16(rhs_mat_2367_01_sp1, lhs_mat_23_01_sp1)); + + __m256i iacc_mat_00_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_01_11_sp1)); + __m256i iacc_mat_01_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_01_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_01_11_sp1)); + + __m256i iacc_mat_10_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_0145_11_sp1, lhs_mat_23_11_sp1)); + __m256i iacc_mat_11_1_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp1, lhs_mat_23_10_sp1),_mm256_maddubs_epi16(rhs_mat_2367_11_sp1, lhs_mat_23_11_sp1)); + + __m256i iacc_mat_00_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_01_21_sp1)); + __m256i iacc_mat_01_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_01_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_01_21_sp1)); + + __m256i iacc_mat_10_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_0145_21_sp1, lhs_mat_23_21_sp1)); + __m256i iacc_mat_11_2_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp1, lhs_mat_23_20_sp1),_mm256_maddubs_epi16(rhs_mat_2367_21_sp1, lhs_mat_23_21_sp1)); + + __m256i iacc_mat_00_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_01_31_sp1)); + __m256i iacc_mat_01_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_01_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_01_31_sp1)); + + __m256i iacc_mat_10_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_0145_31_sp1, lhs_mat_23_31_sp1)); + __m256i iacc_mat_11_3_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp1, lhs_mat_23_30_sp1),_mm256_maddubs_epi16(rhs_mat_2367_31_sp1, lhs_mat_23_31_sp1)); + + __m256i iacc_mat_00_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_01_41_sp1)); + __m256i iacc_mat_01_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_01_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_01_41_sp1)); + + __m256i iacc_mat_10_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_0145_41_sp1, lhs_mat_23_41_sp1)); + __m256i iacc_mat_11_4_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp1, lhs_mat_23_40_sp1),_mm256_maddubs_epi16(rhs_mat_2367_41_sp1, lhs_mat_23_41_sp1)); + + __m256i iacc_mat_00_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_01_51_sp1)); + __m256i iacc_mat_01_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_01_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_01_51_sp1)); + + __m256i iacc_mat_10_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_0145_51_sp1, lhs_mat_23_51_sp1)); + __m256i iacc_mat_11_5_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp1, lhs_mat_23_50_sp1),_mm256_maddubs_epi16(rhs_mat_2367_51_sp1, lhs_mat_23_51_sp1)); + + __m256i iacc_mat_00_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_01_61_sp1)); + __m256i iacc_mat_01_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_01_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_01_61_sp1)); + + __m256i iacc_mat_10_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_0145_61_sp1, lhs_mat_23_61_sp1)); + __m256i iacc_mat_11_6_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp1, lhs_mat_23_60_sp1),_mm256_maddubs_epi16(rhs_mat_2367_61_sp1, lhs_mat_23_61_sp1)); + + __m256i iacc_mat_00_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_01_71_sp1)); + __m256i iacc_mat_01_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_01_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_01_71_sp1)); + + __m256i iacc_mat_10_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_0145_71_sp1, lhs_mat_23_71_sp1)); + __m256i iacc_mat_11_7_sp1 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp1, lhs_mat_23_70_sp1),_mm256_maddubs_epi16(rhs_mat_2367_71_sp1, lhs_mat_23_71_sp1)); + + + __m256i iacc_mat_00_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_01_01_sp2)); + __m256i iacc_mat_01_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_01_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_01_01_sp2)); + + __m256i iacc_mat_10_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_0145_01_sp2, lhs_mat_23_01_sp2)); + __m256i iacc_mat_11_0_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_00_sp2, lhs_mat_23_00_sp2),_mm256_maddubs_epi16(rhs_mat_2367_01_sp2, lhs_mat_23_01_sp2)); + + __m256i iacc_mat_00_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_01_11_sp2)); + __m256i iacc_mat_01_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_01_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_01_11_sp2)); + + __m256i iacc_mat_10_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_0145_11_sp2, lhs_mat_23_11_sp2)); + __m256i iacc_mat_11_1_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_10_sp2, lhs_mat_23_10_sp2),_mm256_maddubs_epi16(rhs_mat_2367_11_sp2, lhs_mat_23_11_sp2)); + + __m256i iacc_mat_00_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_01_21_sp2)); + __m256i iacc_mat_01_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_01_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_01_21_sp2)); + + __m256i iacc_mat_10_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_0145_21_sp2, lhs_mat_23_21_sp2)); + __m256i iacc_mat_11_2_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_20_sp2, lhs_mat_23_20_sp2),_mm256_maddubs_epi16(rhs_mat_2367_21_sp2, lhs_mat_23_21_sp2)); + + __m256i iacc_mat_00_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_01_31_sp2)); + __m256i iacc_mat_01_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_01_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_01_31_sp2)); + + __m256i iacc_mat_10_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_0145_31_sp2, lhs_mat_23_31_sp2)); + __m256i iacc_mat_11_3_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_30_sp2, lhs_mat_23_30_sp2),_mm256_maddubs_epi16(rhs_mat_2367_31_sp2, lhs_mat_23_31_sp2)); + + __m256i iacc_mat_00_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_01_41_sp2)); + __m256i iacc_mat_01_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_01_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_01_41_sp2)); + + __m256i iacc_mat_10_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_0145_41_sp2, lhs_mat_23_41_sp2)); + __m256i iacc_mat_11_4_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_40_sp2, lhs_mat_23_40_sp2),_mm256_maddubs_epi16(rhs_mat_2367_41_sp2, lhs_mat_23_41_sp2)); + + __m256i iacc_mat_00_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_01_51_sp2)); + __m256i iacc_mat_01_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_01_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_01_51_sp2)); + + __m256i iacc_mat_10_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_0145_51_sp2, lhs_mat_23_51_sp2)); + __m256i iacc_mat_11_5_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_50_sp2, lhs_mat_23_50_sp2),_mm256_maddubs_epi16(rhs_mat_2367_51_sp2, lhs_mat_23_51_sp2)); + + __m256i iacc_mat_00_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_01_61_sp2)); + __m256i iacc_mat_01_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_01_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_01_61_sp2)); + + __m256i iacc_mat_10_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_0145_61_sp2, lhs_mat_23_61_sp2)); + __m256i iacc_mat_11_6_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_60_sp2, lhs_mat_23_60_sp2),_mm256_maddubs_epi16(rhs_mat_2367_61_sp2, lhs_mat_23_61_sp2)); + + __m256i iacc_mat_00_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_01_71_sp2)); + __m256i iacc_mat_01_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_01_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_01_71_sp2)); + + __m256i iacc_mat_10_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_0145_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_0145_71_sp2, lhs_mat_23_71_sp2)); + __m256i iacc_mat_11_7_sp2 = _mm256_add_epi16(_mm256_maddubs_epi16(rhs_mat_2367_70_sp2, lhs_mat_23_70_sp2),_mm256_maddubs_epi16(rhs_mat_2367_71_sp2, lhs_mat_23_71_sp2)); + + // Combine results from both shuffle patterns for each output block. + __m256i iacc_mat_00_0 = _mm256_add_epi16(iacc_mat_00_0_sp1, iacc_mat_00_0_sp2); + __m256i iacc_mat_01_0 = _mm256_add_epi16(iacc_mat_01_0_sp1, iacc_mat_01_0_sp2); + __m256i iacc_mat_10_0 = _mm256_add_epi16(iacc_mat_10_0_sp1, iacc_mat_10_0_sp2); + __m256i iacc_mat_11_0 = _mm256_add_epi16(iacc_mat_11_0_sp1, iacc_mat_11_0_sp2); + + __m256i iacc_mat_00_1 = _mm256_add_epi16(iacc_mat_00_1_sp1, iacc_mat_00_1_sp2); + __m256i iacc_mat_01_1 = _mm256_add_epi16(iacc_mat_01_1_sp1, iacc_mat_01_1_sp2); + __m256i iacc_mat_10_1 = _mm256_add_epi16(iacc_mat_10_1_sp1, iacc_mat_10_1_sp2); + __m256i iacc_mat_11_1 = _mm256_add_epi16(iacc_mat_11_1_sp1, iacc_mat_11_1_sp2); + + __m256i iacc_mat_00_2 = _mm256_add_epi16(iacc_mat_00_2_sp1, iacc_mat_00_2_sp2); + __m256i iacc_mat_01_2 = _mm256_add_epi16(iacc_mat_01_2_sp1, iacc_mat_01_2_sp2); + __m256i iacc_mat_10_2 = _mm256_add_epi16(iacc_mat_10_2_sp1, iacc_mat_10_2_sp2); + __m256i iacc_mat_11_2 = _mm256_add_epi16(iacc_mat_11_2_sp1, iacc_mat_11_2_sp2); + + __m256i iacc_mat_00_3 = _mm256_add_epi16(iacc_mat_00_3_sp1, iacc_mat_00_3_sp2); + __m256i iacc_mat_01_3 = _mm256_add_epi16(iacc_mat_01_3_sp1, iacc_mat_01_3_sp2); + __m256i iacc_mat_10_3 = _mm256_add_epi16(iacc_mat_10_3_sp1, iacc_mat_10_3_sp2); + __m256i iacc_mat_11_3 = _mm256_add_epi16(iacc_mat_11_3_sp1, iacc_mat_11_3_sp2); + + __m256i iacc_mat_00_4 = _mm256_add_epi16(iacc_mat_00_4_sp1, iacc_mat_00_4_sp2); + __m256i iacc_mat_01_4 = _mm256_add_epi16(iacc_mat_01_4_sp1, iacc_mat_01_4_sp2); + __m256i iacc_mat_10_4 = _mm256_add_epi16(iacc_mat_10_4_sp1, iacc_mat_10_4_sp2); + __m256i iacc_mat_11_4 = _mm256_add_epi16(iacc_mat_11_4_sp1, iacc_mat_11_4_sp2); + + __m256i iacc_mat_00_5 = _mm256_add_epi16(iacc_mat_00_5_sp1, iacc_mat_00_5_sp2); + __m256i iacc_mat_01_5 = _mm256_add_epi16(iacc_mat_01_5_sp1, iacc_mat_01_5_sp2); + __m256i iacc_mat_10_5 = _mm256_add_epi16(iacc_mat_10_5_sp1, iacc_mat_10_5_sp2); + __m256i iacc_mat_11_5 = _mm256_add_epi16(iacc_mat_11_5_sp1, iacc_mat_11_5_sp2); + + __m256i iacc_mat_00_6 = _mm256_add_epi16(iacc_mat_00_6_sp1, iacc_mat_00_6_sp2); + __m256i iacc_mat_01_6 = _mm256_add_epi16(iacc_mat_01_6_sp1, iacc_mat_01_6_sp2); + __m256i iacc_mat_10_6 = _mm256_add_epi16(iacc_mat_10_6_sp1, iacc_mat_10_6_sp2); + __m256i iacc_mat_11_6 = _mm256_add_epi16(iacc_mat_11_6_sp1, iacc_mat_11_6_sp2); + + __m256i iacc_mat_00_7 = _mm256_add_epi16(iacc_mat_00_7_sp1, iacc_mat_00_7_sp2); + __m256i iacc_mat_01_7 = _mm256_add_epi16(iacc_mat_01_7_sp1, iacc_mat_01_7_sp2); + __m256i iacc_mat_10_7 = _mm256_add_epi16(iacc_mat_10_7_sp1, iacc_mat_10_7_sp2); + __m256i iacc_mat_11_7 = _mm256_add_epi16(iacc_mat_11_7_sp1, iacc_mat_11_7_sp2); + + // Output of both shuffle patterns are added in order to sum dot product outputs of all 32 values in block + iacc_mat_00_0 = _mm256_madd_epi16(iacc_mat_00_0, scale_0145_0); + iacc_mat_01_0 = _mm256_madd_epi16(iacc_mat_01_0, scale_2367_0); + iacc_mat_10_0 = _mm256_madd_epi16(iacc_mat_10_0, scale_0145_0); + iacc_mat_11_0 = _mm256_madd_epi16(iacc_mat_11_0, scale_2367_0); + + iacc_mat_00_1 = _mm256_madd_epi16(iacc_mat_00_1, scale_0145_1); + iacc_mat_01_1 = _mm256_madd_epi16(iacc_mat_01_1, scale_2367_1); + iacc_mat_10_1 = _mm256_madd_epi16(iacc_mat_10_1, scale_0145_1); + iacc_mat_11_1 = _mm256_madd_epi16(iacc_mat_11_1, scale_2367_1); + + iacc_mat_00_2 = _mm256_madd_epi16(iacc_mat_00_2, scale_0145_2); + iacc_mat_01_2 = _mm256_madd_epi16(iacc_mat_01_2, scale_2367_2); + iacc_mat_10_2 = _mm256_madd_epi16(iacc_mat_10_2, scale_0145_2); + iacc_mat_11_2 = _mm256_madd_epi16(iacc_mat_11_2, scale_2367_2); + + iacc_mat_00_3 = _mm256_madd_epi16(iacc_mat_00_3, scale_0145_3); + iacc_mat_01_3 = _mm256_madd_epi16(iacc_mat_01_3, scale_2367_3); + iacc_mat_10_3 = _mm256_madd_epi16(iacc_mat_10_3, scale_0145_3); + iacc_mat_11_3 = _mm256_madd_epi16(iacc_mat_11_3, scale_2367_3); + + iacc_mat_00_4 = _mm256_madd_epi16(iacc_mat_00_4, scale_0145_4); + iacc_mat_01_4 = _mm256_madd_epi16(iacc_mat_01_4, scale_2367_4); + iacc_mat_10_4 = _mm256_madd_epi16(iacc_mat_10_4, scale_0145_4); + iacc_mat_11_4 = _mm256_madd_epi16(iacc_mat_11_4, scale_2367_4); + + iacc_mat_00_5 = _mm256_madd_epi16(iacc_mat_00_5, scale_0145_5); + iacc_mat_01_5 = _mm256_madd_epi16(iacc_mat_01_5, scale_2367_5); + iacc_mat_10_5 = _mm256_madd_epi16(iacc_mat_10_5, scale_0145_5); + iacc_mat_11_5 = _mm256_madd_epi16(iacc_mat_11_5, scale_2367_5); + + iacc_mat_00_6 = _mm256_madd_epi16(iacc_mat_00_6, scale_0145_6); + iacc_mat_01_6 = _mm256_madd_epi16(iacc_mat_01_6, scale_2367_6); + iacc_mat_10_6 = _mm256_madd_epi16(iacc_mat_10_6, scale_0145_6); + iacc_mat_11_6 = _mm256_madd_epi16(iacc_mat_11_6, scale_2367_6); + + iacc_mat_00_7 = _mm256_madd_epi16(iacc_mat_00_7, scale_0145_7); + iacc_mat_01_7 = _mm256_madd_epi16(iacc_mat_01_7, scale_2367_7); + iacc_mat_10_7 = _mm256_madd_epi16(iacc_mat_10_7, scale_0145_7); + iacc_mat_11_7 = _mm256_madd_epi16(iacc_mat_11_7, scale_2367_7); + + __m256i iacc_mat_00 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_0, iacc_mat_00_1), _mm256_add_epi32(iacc_mat_00_2, iacc_mat_00_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_00_4, iacc_mat_00_5), _mm256_add_epi32(iacc_mat_00_6, iacc_mat_00_7))); + __m256i iacc_mat_01 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_0, iacc_mat_01_1), _mm256_add_epi32(iacc_mat_01_2, iacc_mat_01_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_01_4, iacc_mat_01_5), _mm256_add_epi32(iacc_mat_01_6, iacc_mat_01_7))); + __m256i iacc_mat_10 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_0, iacc_mat_10_1), _mm256_add_epi32(iacc_mat_10_2, iacc_mat_10_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_10_4, iacc_mat_10_5), _mm256_add_epi32(iacc_mat_10_6, iacc_mat_10_7))); + __m256i iacc_mat_11 = _mm256_add_epi32(_mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_0, iacc_mat_11_1), _mm256_add_epi32(iacc_mat_11_2, iacc_mat_11_3)), _mm256_add_epi32(_mm256_add_epi32(iacc_mat_11_4, iacc_mat_11_5), _mm256_add_epi32(iacc_mat_11_6, iacc_mat_11_7))); + + // Straighten out to make 4 row vectors + __m256i iacc_row_0 = _mm256_blend_epi32(iacc_mat_00, _mm256_shuffle_epi32(iacc_mat_01, 78), 204); + __m256i iacc_row_1 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_00, 78), iacc_mat_01, 204); + __m256i iacc_row_2 = _mm256_blend_epi32(iacc_mat_10, _mm256_shuffle_epi32(iacc_mat_11, 78), 204); + __m256i iacc_row_3 = _mm256_blend_epi32(_mm256_shuffle_epi32(iacc_mat_10, 78), iacc_mat_11, 204); + + // Load the scale(d) values for all the 4 Q8_k blocks and repeat it across lanes + const __m128 row_scale_f32_sse = _mm_load_ps(a_ptr[b].d); + const __m256 row_scale_f32 = _mm256_set_m128(row_scale_f32_sse, row_scale_f32_sse); + + // Multiply with appropiate scales and accumulate (for both d and dmin) below + acc_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_0), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_rows[0]); + acc_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_1), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_rows[1]); + acc_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_2), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_rows[2]); + acc_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_3), _mm256_mul_ps(col_scale_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_rows[3]); + + __m256i lhs_bsums_01_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_0123), lhs_raw_bsums_01_0123, 1); + __m256i lhs_bsums_23_0123 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_0123), lhs_raw_bsums_23_0123, 1); + __m256i lhs_bsums_01_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_01_4567), lhs_raw_bsums_01_4567, 1); + __m256i lhs_bsums_23_4567 = _mm256_inserti128_si256(_mm256_castsi128_si256(lhs_raw_bsums_23_4567), lhs_raw_bsums_23_4567, 1); + + // Take two bsums from two Q8_Ks at a time and multiply with corresponding mins values from each Q2_K + __m256i iacc_row_min_0_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 0), mins_01); + __m256i iacc_row_min_1_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 170), mins_01); + __m256i iacc_row_min_2_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 0), mins_01); + __m256i iacc_row_min_3_01 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 170), mins_01); + + __m256i iacc_row_min_0_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 85), mins_23); + __m256i iacc_row_min_1_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_0123, 255), mins_23); + __m256i iacc_row_min_2_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 85), mins_23); + __m256i iacc_row_min_3_23 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_0123, 255), mins_23); + + __m256i iacc_row_min_0_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 0), mins_45); + __m256i iacc_row_min_1_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 170), mins_45); + __m256i iacc_row_min_2_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 0), mins_45); + __m256i iacc_row_min_3_45 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 170), mins_45); + + __m256i iacc_row_min_0_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 85), mins_67); + __m256i iacc_row_min_1_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_01_4567, 255), mins_67); + __m256i iacc_row_min_2_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 85), mins_67); + __m256i iacc_row_min_3_67 = _mm256_madd_epi16(_mm256_shuffle_epi32(lhs_bsums_23_4567, 255), mins_67); + + __m256i iacc_row_min_0 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_0_01, iacc_row_min_0_23), _mm256_add_epi32(iacc_row_min_0_45,iacc_row_min_0_67)); + __m256i iacc_row_min_1 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_1_01, iacc_row_min_1_23), _mm256_add_epi32(iacc_row_min_1_45,iacc_row_min_1_67)); + __m256i iacc_row_min_2 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_2_01, iacc_row_min_2_23), _mm256_add_epi32(iacc_row_min_2_45,iacc_row_min_2_67)); + __m256i iacc_row_min_3 = _mm256_add_epi32(_mm256_add_epi32(iacc_row_min_3_01, iacc_row_min_3_23), _mm256_add_epi32(iacc_row_min_3_45,iacc_row_min_3_67)); + + acc_min_rows[0] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_0), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 0)), acc_min_rows[0]); + acc_min_rows[1] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_1), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 85)), acc_min_rows[1]); + acc_min_rows[2] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_2), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 170)), acc_min_rows[2]); + acc_min_rows[3] = _mm256_fmadd_ps(_mm256_cvtepi32_ps(iacc_row_min_3), _mm256_mul_ps(col_dmin_f32, _mm256_shuffle_ps(row_scale_f32, row_scale_f32, 255)), acc_min_rows[3]); } } + // Store the accumulated values + for (int i = 0; i < 4; i++) { + _mm256_storeu_ps((float * )(s + ((y * 4 + i) * bs + x * 8)), _mm256_sub_ps(acc_rows[i], acc_min_rows[i])); + } } } +#else + + ggml_gemm_q2_K_8x8_q8_K_generic(n, s, bs, vx, vy, nr, nc); + + #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/arch-fallback.h 6641+dfsg-2/ggml/src/ggml-cpu/arch-fallback.h --- 5882+dfsg-2/ggml/src/ggml-cpu/arch-fallback.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/arch-fallback.h 2025-09-30 07:36:33.000000000 +0000 @@ -13,6 +13,7 @@ #define ggml_vec_dot_q5_0_q8_0_generic ggml_vec_dot_q5_0_q8_0 #define ggml_vec_dot_q5_1_q8_1_generic ggml_vec_dot_q5_1_q8_1 #define ggml_vec_dot_q8_0_q8_0_generic ggml_vec_dot_q8_0_q8_0 +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_q2_K_q8_K_generic ggml_vec_dot_q2_K_q8_K @@ -37,17 +38,25 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__aarch64__) || defined(__arm__) || defined(_M_ARM) || defined(_M_ARM64) // repack.cpp #define ggml_quantize_mat_q8_K_4x8_generic ggml_quantize_mat_q8_K_4x8 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #elif defined(__x86_64__) || defined(__i386__) || defined(_M_IX86) || defined(_M_X64) // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 @@ -72,18 +81,23 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__loongarch64) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -92,12 +106,16 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__riscv) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K @@ -112,6 +130,7 @@ #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K #define ggml_vec_dot_iq4_nl_q8_0_generic ggml_vec_dot_iq4_nl_q8_0 #define ggml_vec_dot_iq4_xs_q8_K_generic ggml_vec_dot_iq4_xs_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -119,16 +138,18 @@ #define ggml_gemv_q4_0_4x4_q8_0_generic ggml_gemv_q4_0_4x4_q8_0 #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__s390x__) // quants.c #define quantize_row_q8_K_generic quantize_row_q8_K -#define ggml_vec_dot_q5_0_q8_0_generic ggml_vec_dot_q5_0_q8_0 -#define ggml_vec_dot_q5_1_q8_1_generic ggml_vec_dot_q5_1_q8_1 #define ggml_vec_dot_tq1_0_q8_K_generic ggml_vec_dot_tq1_0_q8_K #define ggml_vec_dot_tq2_0_q8_K_generic ggml_vec_dot_tq2_0_q8_K #define ggml_vec_dot_q2_K_q8_K_generic ggml_vec_dot_q2_K_q8_K @@ -147,12 +168,16 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #elif defined(__wasm__) // quants.c #define ggml_vec_dot_q4_1_q8_1_generic ggml_vec_dot_q4_1_q8_1 @@ -167,6 +192,7 @@ #define ggml_vec_dot_iq1_m_q8_K_generic ggml_vec_dot_iq1_m_q8_K #define ggml_vec_dot_iq4_nl_q8_0_generic ggml_vec_dot_iq4_nl_q8_0 #define ggml_vec_dot_iq4_xs_q8_K_generic ggml_vec_dot_iq4_xs_q8_K +#define ggml_vec_dot_mxfp4_q8_0_generic ggml_vec_dot_mxfp4_q8_0 // repack.cpp #define ggml_quantize_mat_q8_0_4x4_generic ggml_quantize_mat_q8_0_4x4 #define ggml_quantize_mat_q8_0_4x8_generic ggml_quantize_mat_q8_0_4x8 @@ -175,10 +201,14 @@ #define ggml_gemv_q4_0_4x8_q8_0_generic ggml_gemv_q4_0_4x8_q8_0 #define ggml_gemv_q4_0_8x8_q8_0_generic ggml_gemv_q4_0_8x8_q8_0 #define ggml_gemv_q4_K_8x8_q8_K_generic ggml_gemv_q4_K_8x8_q8_K +#define ggml_gemv_q2_K_8x8_q8_K_generic ggml_gemv_q2_K_8x8_q8_K #define ggml_gemv_iq4_nl_4x4_q8_0_generic ggml_gemv_iq4_nl_4x4_q8_0 +#define ggml_gemv_iq4_nl_8x8_q8_0_generic ggml_gemv_iq4_nl_8x8_q8_0 #define ggml_gemm_q4_0_4x4_q8_0_generic ggml_gemm_q4_0_4x4_q8_0 #define ggml_gemm_q4_0_4x8_q8_0_generic ggml_gemm_q4_0_4x8_q8_0 #define ggml_gemm_q4_0_8x8_q8_0_generic ggml_gemm_q4_0_8x8_q8_0 #define ggml_gemm_q4_K_8x8_q8_K_generic ggml_gemm_q4_K_8x8_q8_K +#define ggml_gemm_q2_K_8x8_q8_K_generic ggml_gemm_q2_K_8x8_q8_K #define ggml_gemm_iq4_nl_4x4_q8_0_generic ggml_gemm_iq4_nl_4x4_q8_0 +#define ggml_gemm_iq4_nl_8x8_q8_0_generic ggml_gemm_iq4_nl_8x8_q8_0 #endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/common.h 6641+dfsg-2/ggml/src/ggml-cpu/common.h --- 5882+dfsg-2/ggml/src/ggml-cpu/common.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/common.h 2025-09-30 07:36:33.000000000 +0000 @@ -28,6 +28,14 @@ static inline float bf16_to_f32(ggml_bf1 return GGML_BF16_TO_FP32(x); } +static inline float i32_to_f32(int32_t x) { + return x; +} + +static inline int32_t f32_to_i32(float x) { + return x; +} + static inline float f32_to_f32(float x) { return x; } @@ -54,6 +62,12 @@ struct type_conversion_table +struct type_conversion_table { + static constexpr float (*to_f32)(int32_t) = i32_to_f32; + static constexpr int32_t (*from_f32)(float) = f32_to_i32; +}; + static std::pair get_thread_range(const struct ggml_compute_params * params, const struct ggml_tensor * src0) { const int64_t ith = params->ith; const int64_t nth = params->nth; diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu-impl.h 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu-impl.h --- 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu-impl.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu-impl.h 2025-09-30 07:36:33.000000000 +0000 @@ -68,12 +68,6 @@ struct ggml_compute_params { #endif // __VXE2__ #endif // __s390x__ && __VEC__ -#if defined(__s390x__) && defined(GGML_NNPA) -#ifndef __NNPA__ -#define __NNPA__ -#endif // __NNPA__ -#endif // __s390x__ && GGML_NNPA - #if defined(__ARM_FEATURE_SVE) #include #endif @@ -486,6 +480,19 @@ inline static int16x8_t vec_padd_s16(int return v_abo + v_abe; } +/** + * @see https://github.com/ggml-org/llama.cpp/pull/14037 + */ +inline static float vec_hsum_f32x4(float32x4_t v) { + float32x4_t v_temp = v + vec_reve(v); + return v_temp[0] + v_temp[1]; +} + +inline static int32_t vec_hsum_i32x4(int32x4_t v) { + int32x4_t v_temp = v + vec_reve(v); + return v_temp[0] + v_temp[1]; +} + inline static int32x4_t ggml_vec_dot(int32x4_t acc, int8x16_t a, int8x16_t b) { const int16x8_t p = vec_mule(a, b) + vec_mulo(a, b); return acc + (vec_unpackh(p) + vec_unpackl(p)); diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.c 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.c --- 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.c 2025-09-30 07:36:33.000000000 +0000 @@ -253,6 +253,12 @@ static const struct ggml_type_traits_cpu .vec_dot_type = GGML_TYPE_Q8_1, .nrows = 1, }, + [GGML_TYPE_MXFP4] = { + .from_float = quantize_row_mxfp4, + .vec_dot = ggml_vec_dot_mxfp4_q8_0, + .vec_dot_type = GGML_TYPE_Q8_0, + .nrows = 1, + }, [GGML_TYPE_Q2_K] = { .from_float = quantize_row_q2_K, .vec_dot = ggml_vec_dot_q2_K_q8_K, @@ -367,6 +373,9 @@ static const struct ggml_type_traits_cpu .vec_dot_type = GGML_TYPE_Q8_K, .nrows = 1, }, + [GGML_TYPE_I32] = { + .from_float = (ggml_from_float_t) ggml_cpu_fp32_to_i32, + }, }; const struct ggml_type_traits_cpu * ggml_get_type_traits_cpu(enum ggml_type type) { @@ -464,10 +473,10 @@ struct ggml_threadpool { struct ggml_compute_state { #ifndef GGML_USE_OPENMP ggml_thread_t thrd; - bool cpumask[GGML_MAX_N_THREADS]; int last_graph; bool pending; #endif + bool cpumask[GGML_MAX_N_THREADS]; struct ggml_threadpool * threadpool; int ith; }; @@ -1670,6 +1679,10 @@ static void ggml_compute_forward(struct { ggml_compute_forward_add(params, tensor); } break; + case GGML_OP_ADD_ID: + { + ggml_compute_forward_add_id(params, tensor); + } break; case GGML_OP_ADD1: { ggml_compute_forward_add1(params, tensor); @@ -1866,10 +1879,18 @@ static void ggml_compute_forward(struct { ggml_compute_forward_im2col_back_f32(params, tensor); } break; + case GGML_OP_IM2COL_3D: + { + ggml_compute_forward_im2col_3d(params, tensor); + } break; case GGML_OP_CONV_2D: { ggml_compute_forward_conv_2d(params, tensor); } break; + case GGML_OP_CONV_3D: + { + ggml_compute_forward_conv_3d(params, tensor); + } break; case GGML_OP_CONV_2D_DW: { ggml_compute_forward_conv_2d_dw(params, tensor); @@ -1924,7 +1945,7 @@ static void ggml_compute_forward(struct } break; case GGML_OP_FLASH_ATTN_EXT: { - ggml_compute_forward_flash_attn_ext(params, tensor->src[0], tensor->src[1], tensor->src[2], tensor->src[3], tensor); + ggml_compute_forward_flash_attn_ext(params, tensor); } break; case GGML_OP_FLASH_ATTN_BACK: { @@ -2012,6 +2033,11 @@ static void ggml_compute_forward(struct ggml_compute_forward_opt_step_adamw(params, tensor); } break; + case GGML_OP_OPT_STEP_SGD: + { + ggml_compute_forward_opt_step_sgd(params, tensor); + } + break; case GGML_OP_NONE: { // nop @@ -2111,6 +2137,7 @@ static int ggml_get_n_tasks(struct ggml_ case GGML_OP_DUP: case GGML_OP_CONT: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_ACC: { @@ -2172,6 +2199,7 @@ static int ggml_get_n_tasks(struct ggml_ case GGML_GLU_OP_REGLU: case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: { @@ -2234,7 +2262,9 @@ static int ggml_get_n_tasks(struct ggml_ } break; case GGML_OP_IM2COL: case GGML_OP_IM2COL_BACK: + case GGML_OP_IM2COL_3D: case GGML_OP_CONV_2D: + case GGML_OP_CONV_3D: case GGML_OP_CONV_2D_DW: case GGML_OP_CONV_TRANSPOSE_1D: case GGML_OP_CONV_TRANSPOSE_2D: @@ -2313,6 +2343,7 @@ static int ggml_get_n_tasks(struct ggml_ case GGML_OP_CROSS_ENTROPY_LOSS: case GGML_OP_CROSS_ENTROPY_LOSS_BACK: case GGML_OP_OPT_STEP_ADAMW: + case GGML_OP_OPT_STEP_SGD: { n_tasks = n_threads; } break; @@ -2668,11 +2699,15 @@ struct ggml_cplan ggml_graph_plan( if (ggml_is_quantized(node->type) || // F16 -> BF16 and BF16 -> F16 copies go through intermediate F32 (node->src[0]->type == GGML_TYPE_F16 && node->src[1] && node->src[1]->type == GGML_TYPE_BF16) || - (node->src[0]->type == GGML_TYPE_BF16 && node->src[1] && node->src[1]->type == GGML_TYPE_F16)) { + (node->src[0]->type == GGML_TYPE_BF16 && node->src[1] && node->src[1]->type == GGML_TYPE_F16) || + // conversion between F32 and I32 + (node->src[0]->type == GGML_TYPE_F32 && node->src[1] && node->src[1]->type == GGML_TYPE_I32) || + (node->src[0]->type == GGML_TYPE_I32 && node->src[1] && node->src[1]->type == GGML_TYPE_F32)) { cur = ggml_type_size(GGML_TYPE_F32) * node->ne[0] * n_tasks; } } break; case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: { if (ggml_is_quantized(node->src[0]->type)) { @@ -2754,6 +2789,7 @@ struct ggml_cplan ggml_graph_plan( } } break; case GGML_OP_CONV_2D: + case GGML_OP_CONV_3D: { cur = GGML_IM2COL_WORK_SIZE; } break; @@ -3045,7 +3081,14 @@ static struct ggml_threadpool * ggml_thr threadpool->workers = workers; -#ifndef GGML_USE_OPENMP +#ifdef GGML_USE_OPENMP + int32_t cpumask_iter = 0; + + // Compute CPU masks for each thread + for (int j = 0; j < tpp->n_threads; j++) { + ggml_thread_cpumask_next(tpp->cpumask, workers[j].cpumask, tpp->strict_cpu, &cpumask_iter); + } +#else // GGML_USE_OPENMP ggml_mutex_init(&threadpool->mutex); ggml_cond_init(&threadpool->cond); @@ -3118,7 +3161,14 @@ enum ggml_status ggml_graph_compute(stru atomic_store_explicit(&threadpool->n_threads_cur, n_threads, memory_order_relaxed); } - ggml_graph_compute_thread(&threadpool->workers[omp_get_thread_num()]); + // Apply thread CPU mask and priority + int ith = omp_get_thread_num(); + + ggml_thread_apply_priority(threadpool->prio); + if (ggml_thread_cpumask_is_valid(threadpool->workers[ith].cpumask)) { + ggml_thread_apply_affinity(threadpool->workers[ith].cpumask); + } + ggml_graph_compute_thread(&threadpool->workers[ith]); } } else { atomic_store_explicit(&threadpool->n_threads_cur, 1, memory_order_relaxed); @@ -3181,20 +3231,12 @@ void ggml_cpu_fp32_to_fp16(const float * __m128i y_vec = _mm_cvtps_ph(x_vec, _MM_FROUND_TO_NEAREST_INT); _mm_storel_epi64((__m128i *)(y + i), y_vec); } -#elif defined(__NNPA__) - for (; i + 7 < n; i += 8) { - float32x4_t v_xh = vec_xl(0, (const float *)(x + i + 0)); - float32x4_t v_xl = vec_xl(0, (const float *)(x + i + 4)); - uint16x8_t v_yd = vec_round_from_fp32(v_xh, v_xl, 0); - uint16x8_t v_y = vec_convert_to_fp16(v_yd, 0); - vec_xst(v_y, 0, (ggml_fp16_t *)(y + i)); - } - for (; i + 3 < n; i += 4) { - float32x4_t v_x = vec_xl(0, (const float *)(x + i)); - float32x4_t v_zero = vec_splats(0.0f); - uint16x8_t v_yd = vec_round_from_fp32(v_x, v_zero, 0); - uint16x8_t v_y = vec_convert_to_fp16(v_yd, 0); - vec_xst(v_y, 0, (ggml_fp16_t *)(y + i)); +#elif defined(__riscv_zvfh) + for (int vl; i < n; i += vl) { + vl = __riscv_vsetvl_e32m2(n - i); + vfloat32m2_t vx = __riscv_vle32_v_f32m2(&x[i], vl); + vfloat16m1_t vy = __riscv_vfncvt_f_f_w_f16m1(vx, vl); + __riscv_vse16_v_f16m1((_Float16 *)&y[i], vy, vl); } #endif for (; i < n; ++i) { @@ -3222,21 +3264,6 @@ void ggml_cpu_fp16_to_fp32(const ggml_fp __m128 y_vec = _mm_cvtph_ps(x_vec); _mm_storeu_ps(y + i, y_vec); } -#elif defined(__NNPA__) - for (; i + 7 < n; i += 8) { - uint16x8_t v_x = vec_xl(0, (const ggml_fp16_t *)(x + i)); - uint16x8_t v_yd = vec_convert_from_fp16(v_x, 0); - float32x4_t v_yh = vec_extend_to_fp32_hi(v_yd, 0); - float32x4_t v_yl = vec_extend_to_fp32_lo(v_yd, 0); - vec_xst(v_yh, 0, (float *)(y + i + 0)); - vec_xst(v_yl, 0, (float *)(y + i + 4)); - } - for (; i + 3 < n; i += 4) { - uint16x8_t v_x = vec_xl(0, (const ggml_fp16_t *)(x + i)); - uint16x8_t v_yd = vec_convert_from_fp16(v_x, 0); - float32x4_t v_yh = vec_extend_to_fp32_hi(v_yd, 0); - vec_xst(v_yh, 0, (float *)(y + i)); - } #endif for (; i < n; ++i) { @@ -3251,6 +3278,13 @@ void ggml_cpu_fp32_to_bf16(const float * } } +void ggml_cpu_fp32_to_i32(const float * x, int32_t * y, int64_t n) { + int64_t i = 0; + for (; i < n; ++i) { + y[i] = x[i]; + } +} + void ggml_cpu_bf16_to_fp32(const ggml_bf16_t * x, float * y, int64_t n) { int64_t i = 0; #if defined(__AVX2__) @@ -3437,14 +3471,6 @@ int ggml_cpu_has_vxe(void) { return 1; #else return 0; -#endif -} - -int ggml_cpu_has_nnpa(void) { -#if defined(GGML_NNPA) - return 1; -#else - return 0; #endif } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.cpp 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/ggml-cpu.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -18,6 +18,10 @@ # include "kleidiai/kleidiai.h" #endif +#ifdef GGML_USE_CPU_RISCV64_SPACEMIT +# include "spacemit/ime.h" +#endif + #if defined(_WIN32) # define WIN32_LEAN_AND_MEAN # ifndef NOMINMAX @@ -35,7 +39,7 @@ // ggml-backend interface -std::vector& ggml_backend_cpu_get_extra_buffers_type() { +std::vector & ggml_backend_cpu_get_extra_buffer_types() { static std::vector bufts = []() { std::vector bufts; @@ -45,6 +49,12 @@ std::vector& } #endif +#ifdef GGML_USE_CPU_RISCV64_SPACEMIT + if (ggml_backend_cpu_riscv64_spacemit_buffer_type()) { + bufts.push_back(ggml_backend_cpu_riscv64_spacemit_buffer_type()); + } +#endif + #ifdef GGML_USE_CPU_KLEIDIAI if (ggml_backend_cpu_kleidiai_buffer_type()) { bufts.push_back(ggml_backend_cpu_kleidiai_buffer_type()); @@ -57,8 +67,6 @@ std::vector& } #endif - bufts.push_back(NULL); - return bufts; }(); @@ -66,14 +74,20 @@ std::vector& } static ggml_backend_buffer_type_t * ggml_backend_cpu_device_get_extra_buffers_type(ggml_backend_dev_t device) { - return ggml_backend_cpu_get_extra_buffers_type().data(); + static std::vector extra_bufts = [] { + std::vector bufts = ggml_backend_cpu_get_extra_buffer_types(); + bufts.push_back(nullptr); + return bufts; + }(); + + return extra_bufts.data(); GGML_UNUSED(device); } static bool ggml_backend_cpu_is_extra_buffer_type(ggml_backend_buffer_type_t buft) { - for (auto * extra : ggml_backend_cpu_get_extra_buffers_type()) { - if (extra && extra == buft) { + for (auto * extra : ggml_backend_cpu_get_extra_buffer_types()) { + if (extra == buft) { return true; } } @@ -186,6 +200,7 @@ static const struct ggml_backend_i ggml_ /* .graph_compute = */ ggml_backend_cpu_graph_compute, /* .event_record = */ NULL, /* .event_wait = */ NULL, + /* .graph_optimize = */ NULL, }; static ggml_guid_t ggml_backend_cpu_guid(void) { @@ -210,10 +225,10 @@ ggml_backend_t ggml_backend_cpu_init(voi ctx->abort_callback_data = NULL; ggml_backend_t cpu_backend = new ggml_backend { - /* .guid = */ ggml_backend_cpu_guid(), - /* .interface = */ ggml_backend_cpu_i, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), - /* .context = */ ctx, + /* .guid = */ ggml_backend_cpu_guid(), + /* .iface = */ ggml_backend_cpu_i, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), + /* .context = */ ctx, }; if (cpu_backend == NULL) { @@ -344,8 +359,10 @@ static void ggml_backend_cpu_device_get_ long pages = sysconf(_SC_PHYS_PAGES); long page_size = sysconf(_SC_PAGE_SIZE); *total = pages * page_size; + + // "free" system memory is ill-defined, for practical purposes assume that all of it is free: *free = *total; -#endif +#endif // _WIN32 GGML_UNUSED(dev); } @@ -397,20 +414,13 @@ static bool ggml_backend_cpu_device_supp return true; } - // extra_buffer_op? - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { - if (extra) { - auto buf_extra = (ggml::cpu::extra_buffer_type*) extra->context; - if (buf_extra && buf_extra->supports_op(dev, op)) { - return true; - } - } - } - - // the other case need host buffer. - for (int i = 0; i < GGML_MAX_SRC; i++) { - if (op->src[i] && op->src[i]->buffer && !ggml_backend_buft_is_host(op->src[i]->buffer->buft)) { - return false; + // check extra buffer types + // note: only the first sources are checked for extra buffer types to reduce overhead, increase if necessary + for (int i = 0; i < 4; i++) { + if (op->src[i] && op->src[i]->buffer && + ggml_backend_cpu_is_extra_buffer_type(op->src[i]->buffer->buft)) { + auto * buf_extra = (ggml::cpu::extra_buffer_type *) op->src[i]->buffer->buft->context; + return buf_extra->supports_op(dev, op); } } @@ -579,9 +589,6 @@ static ggml_backend_feature * ggml_backe if (ggml_cpu_has_vxe()) { features.push_back({ "VXE", "1" }); } - if (ggml_cpu_has_nnpa()) { - features.push_back({ "NNPA", "1" }); - } if (ggml_cpu_has_wasm_simd()) { features.push_back({ "WASM_SIMD", "1" }); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.cpp 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -14,6 +14,7 @@ #include "kai_lhs_pack_bf16p2vlx2_f32_sme.h" #include "kai_lhs_quant_pack_qsi8d32p_f32.h" +#include "kai_lhs_quant_pack_qsi8d32p4x8sb_f32_neon.h" #include "kai_lhs_quant_pack_qsi8d32p_f32_neon.h" #include "kai_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme.h" @@ -22,9 +23,94 @@ #include "kai_common.h" +#include "simd-mappings.h" + #include "kernels.h" #define NELEMS(x) sizeof(x) / sizeof(*x) + +static const size_t INT4_PER_BYTE = 2; +static const size_t INT4_BITS = 4; +static const int Q4_0_ZERO_POINT = 8; +const size_t INT4_PER_UINT16 = 4; + +static void dequantize_row_qsi4c32pscalef16( + const void *packed_data, + int32_t row_idx, + int64_t nc, + float *out, + size_t nr_pack, + size_t packed_row_stride, + size_t kr, + size_t bl, + size_t num_bytes_multiplier +) { + size_t group_idx = row_idx / nr_pack; + size_t row_in_group = row_idx % nr_pack; + const uint8_t *packed_group = (const uint8_t *)packed_data + group_idx * packed_row_stride; + size_t num_blocks = nc / bl; + const uint8_t *block_ptr = packed_group; + + for (size_t b = 0; b < num_blocks; ++b) { + uint16_t scale_f16 = *((const uint16_t *)(block_ptr + row_in_group * num_bytes_multiplier)); + float scale = GGML_CPU_FP16_TO_FP32(scale_f16); + + const uint8_t *segment_ptr = block_ptr + nr_pack * num_bytes_multiplier; + size_t num_segments = bl / kr; + size_t num_bytes_per_segment = kr / INT4_PER_BYTE; + + for (size_t s = 0; s < num_segments; ++s) { + const uint8_t *seg_base = segment_ptr + s * nr_pack * num_bytes_per_segment; + const uint8_t *qbytes = seg_base + row_in_group * num_bytes_per_segment; + for (size_t k = 0; k < num_bytes_per_segment; ++k) { + uint8_t byte = qbytes[k] ^ 0x88; + int x0 = (byte & 0x0F) - Q4_0_ZERO_POINT; + int x1 = (byte >> INT4_BITS) - Q4_0_ZERO_POINT; + out[b * bl + s * num_bytes_per_segment + k] = x0 * scale; + out[b * bl + s * num_bytes_per_segment + k + bl/2] = x1 * scale; + } + } + block_ptr += nr_pack * num_bytes_multiplier + num_segments * nr_pack * num_bytes_per_segment; + } +} + +static void dequantize_row_qsi4c32ps1s0scalef16( + const void *packed_data, + int32_t row_idx, + int64_t k, + float *out, + size_t nr, + size_t packed_row_stride, + size_t kr, + size_t bl, + size_t num_bytes_multiplier +) { + const size_t num_blocks = k / bl; + const size_t bl4 = bl / INT4_PER_UINT16; + + size_t group_idx = row_idx / nr; + size_t row_in_group = row_idx % nr; + + const uint8_t *packed_group = (const uint8_t *)packed_data + group_idx * packed_row_stride; + const uint16_t *qdata = (const uint16_t *)packed_group; + const uint16_t *scales = (const uint16_t *)(packed_group + packed_row_stride - (nr * num_blocks * num_bytes_multiplier)); + + for (size_t block_idx = 0; block_idx < num_blocks; ++block_idx) { + uint16_t scale_f16 = scales[row_in_group + block_idx * nr]; + float scale = GGML_CPU_FP16_TO_FP32(scale_f16); + + for (size_t bl4_idx = 0; bl4_idx < bl4; ++bl4_idx) { + uint16_t q = qdata[(block_idx * bl4 + bl4_idx) * nr + row_in_group]; + + for (size_t qidx = 0; qidx < INT4_PER_UINT16; ++qidx) { + int v = ((q >> (qidx * 4)) & 0xF) - Q4_0_ZERO_POINT; + out[block_idx * bl + bl4_idx * INT4_BITS + qidx] = v * scale; + } + } + } + GGML_UNUSED(kr); +} + static ggml_kleidiai_kernels gemm_gemv_kernels[] = { #if defined(__ARM_FEATURE_SME) { @@ -42,6 +128,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1vlx4_qsi4c32p4vlx4_1vlx4vl_sme2_mopa, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1vlx4_qsi4c32p4vlx4_1vlx4vl_sme2_mopa, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32_neon, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32_neon, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32_neon, + /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32_neon, + }, /* SME GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4vlx4_1x4vl_sme2_sdot, @@ -56,15 +148,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4vlx4_1x4vl_sme2_sdot, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4vlx4_1x4vl_sme2_sdot, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32_neon, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32_neon, /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32_neon, /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32_neon, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32ps1s0scalef16_qsu4c32s16s0_neon, + /* .to_float = */ dequantize_row_qsi4c32ps1s0scalef16, }, /* .required_cpu = */ CPU_FEATURE_SME, /* .lhs_type = */ GGML_TYPE_F32, @@ -86,6 +180,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa, /* .run_kernel = */ kai_run_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_pack_bf16p2vlx2_f32_sme, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_pack_bf16p2vlx2_f32_sme, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_pack_bf16p2vlx2_f32_sme, + /* .pack_func = */ kai_run_lhs_pack_bf16p2vlx2_f32_sme, + }, /* SME GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa, @@ -100,15 +200,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa, /* .run_kernel = */ kai_run_matmul_clamp_f32_bf16p2vlx2_bf16p2vlx2_2vlx2vl_sme2_mopa, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_pack_bf16p2vlx2_f32_sme, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_pack_bf16p2vlx2_f32_sme, /* .packed_size = */ kai_get_lhs_packed_size_lhs_pack_bf16p2vlx2_f32_sme, /* .pack_func = */ kai_run_lhs_pack_bf16p2vlx2_f32_sme, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, - /* .pack_func = */ kai_run_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .packed_stride = */ NULL, + /* .pack_func = */ kai_run_rhs_pack_kxn_bf16p2vlx2b_f32_x32_sme, + /* .to_float = */ NULL, }, /* .required_cpu = */ CPU_FEATURE_SME, /* .lhs_type = */ GGML_TYPE_F32, @@ -133,6 +235,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p4x4_qsi4c32p4x4_16x4_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p4x4_qsi4c32p4x4_16x4_neon_dotprod, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, + /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, + }, /* DOTPROD GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, @@ -147,15 +255,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD, /* .lhs_type = */ GGML_TYPE_F32, @@ -179,6 +289,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p4x8_qsi4c32p4x8_16x4_neon_i8mm, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p4x8_qsi4c32p4x8_16x4_neon_i8mm, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + }, /* i8mm GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, @@ -193,15 +309,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD | CPU_FEATURE_I8MM, /* .lhs_type = */ GGML_TYPE_F32, @@ -226,6 +344,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p4x8_qsi4c32p4x8_16x4_neon_i8mm, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p4x8_qsi4c32p4x8_16x4_neon_i8mm, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p4x8sb_f32_neon, + }, /* i8mm GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, @@ -240,15 +364,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1x8_qsi4c32p4x8_1x4x32_neon_dotprod, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD | CPU_FEATURE_I8MM, /* .lhs_type = */ GGML_TYPE_F32, @@ -272,6 +398,12 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p4x4_qsi4c32p4x4_16x4_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p4x4_qsi4c32p4x4_16x4_neon_dotprod, }, + /* .gemm_lhs_info = */ { + /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, + /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, + /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, + /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, + }, /* DOTPROD GEMV */ /* .kern_info = */ { /* .get_m_step = */ kai_get_m_step_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, @@ -286,15 +418,17 @@ static ggml_kleidiai_kernels gemm_gemv_k /* .get_dst_size = */ kai_get_dst_size_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, /* .run_kernel = */ kai_run_matmul_clamp_f32_qsi8d32p1x4_qsi4c32p4x4_1x4_neon_dotprod, }, - /* .lhs_info = */ { + /* .gemv_lhs_info = */ { /* .get_offset = */ kai_get_lhs_offset_lhs_quant_pack_qsi8d32p_f32, /* .get_packed_offset = */ kai_get_lhs_packed_offset_lhs_quant_pack_qsi8d32p_f32, /* .packed_size = */ kai_get_lhs_packed_size_lhs_quant_pack_qsi8d32p_f32, /* .pack_func = */ kai_run_lhs_quant_pack_qsi8d32p_f32, }, /* .rhs_info = */ { - /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, - /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_size = */ kai_get_rhs_packed_size_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .packed_stride = */ kai_get_rhs_packed_stride_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .pack_func = */ kai_run_rhs_pack_nxk_qsi4c32pscalef16_qsu4c32s16s0, + /* .to_float = */ dequantize_row_qsi4c32pscalef16, }, /* .required_cpu = */ CPU_FEATURE_DOTPROD, /* .lhs_type = */ GGML_TYPE_F32, diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.h 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.h --- 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kernels.h 2025-09-30 07:36:33.000000000 +0000 @@ -71,18 +71,24 @@ struct rhs_packing_info { std::function, std::function > packed_size; + size_t (*packed_stride)(size_t k, size_t nr, size_t kr, size_t bl); std::variant< std::function, std::function > pack_func; + void (*to_float)(const void *packed_data, int32_t row_idx, int64_t nc, float *out, size_t nr_pack, size_t packed_row_stride, + size_t kr, size_t bl, size_t num_bytes_multiplier); }; struct ggml_kleidiai_kernels { kernel_info gemm; + lhs_packing_info gemm_lhs_info; + kernel_info gemv; - lhs_packing_info lhs_info; + lhs_packing_info gemv_lhs_info; + rhs_packing_info rhs_info; cpu_feature required_cpu; diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/kleidiai/kleidiai.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -40,6 +40,17 @@ struct ggml_kleidiai_context { ggml_kleidiai_kernels * kernels; } static ctx = { CPU_FEATURE_NONE, NULL }; +static const char* cpu_feature_to_string(cpu_feature f) { + switch (f) { + case CPU_FEATURE_NONE: return "NONE"; + case CPU_FEATURE_DOTPROD: return "DOTPROD"; + case CPU_FEATURE_I8MM: return "I8MM"; + case CPU_FEATURE_SVE: return "SVE"; + case CPU_FEATURE_SME: return "SME"; + default: return "UNKNOWN"; + } +} + static void init_kleidiai_context(void) { ggml_critical_section_start(); @@ -62,6 +73,11 @@ static void init_kleidiai_context(void) ctx.features |= ggml_cpu_has_sme() ? CPU_FEATURE_SME : CPU_FEATURE_NONE; } ctx.kernels = ggml_kleidiai_select_kernels_q4_0(ctx.features); +#ifndef NDEBUG + if (ctx.kernels) { + GGML_LOG_DEBUG("kleidiai: using kernel with CPU feature %s\n", cpu_feature_to_string(ctx.kernels->required_cpu)); + } +#endif } ggml_critical_section_end(); } @@ -71,15 +87,38 @@ static inline int64_t ggml_ne(const ggml return tensor->ne[dim]; } +template +constexpr bool variant_any_invocable_impl(std::index_sequence) { + using V = std::remove_reference_t; + return (std::is_invocable_r_v< + Ret, + std::variant_alternative_t, + Args...> || ...); +} + +template +constexpr bool variant_any_invocable_v = + variant_any_invocable_impl( + std::make_index_sequence< + std::variant_size_v>>{}); + template -static Ret variant_call(const Variant & var, Args&&... args) { - return std::visit([&](auto&& func) -> Ret { - if constexpr (std::is_invocable_r_v) { - return func(std::forward(args)...); - } else { - throw std::runtime_error("Invalid function type in variant_call"); - } - }, var); +static inline Ret variant_call(Variant && var, Args&&... args) { + static_assert(variant_any_invocable_v, Ret, Args...>, + "No alternative in Variant is invocable with the provided arguments and return type."); + + return std::visit( + [&](auto && f) -> Ret { + using F = std::decay_t; + if constexpr (std::is_invocable_r_v) { + return std::invoke(std::forward(f), std::forward(args)...); + } else { + GGML_ABORT("Invalid function type in variant_call"); + GGML_UNREACHABLE(); + } + }, + std::forward(var) + ); } namespace ggml::cpu::kleidiai { @@ -102,9 +141,14 @@ static void transpose_f32kxn_f16nxk(size class tensor_traits : public ggml::cpu::tensor_traits { bool work_size(int /* n_threads */, const struct ggml_tensor * op, size_t & size) override { + if (op->op != GGML_OP_MUL_MAT) { + return false; + } ggml_kleidiai_kernels *kernels = ggml_kleidiai_select_kernels(ctx.features, op); GGML_ASSERT(kernels); - kernel_info * kernel = op->src[1]->ne[1] == 1 ? &kernels->gemv : &kernels->gemm; + bool is_gemv = op->src[1]->ne[1] == 1; + kernel_info * kernel = is_gemv ? &kernels->gemv : &kernels->gemm; + lhs_packing_info * lhs_info = is_gemv ? &kernels->gemv_lhs_info : &kernels->gemm_lhs_info; size_t k = op->src[0]->ne[0]; size_t n = op->src[0]->ne[1]; @@ -115,9 +159,12 @@ class tensor_traits : public ggml::cpu:: size_t sr = kernel->get_sr(); if (kernels->rhs_type == GGML_TYPE_Q4_0) { - size = variant_call(kernels->lhs_info.packed_size, m, k, QK4_0, mr, kr, sr); + size = variant_call(lhs_info->packed_size, m, k, QK4_0, mr, kr, sr); } else if (kernels->rhs_type == GGML_TYPE_F16) { - size = variant_call(kernels->lhs_info.packed_size, m, k, mr, kr, sr) + + const int64_t lhs_batch_size0 = op->src[1]->ne[2]; + const int64_t rhs_batch_size0 = op->src[0]->ne[2]; + const int64_t r = lhs_batch_size0 / rhs_batch_size0; + size = variant_call(lhs_info->packed_size, m * r, k, mr, kr, sr) + variant_call(kernels->rhs_info.packed_size, n, k) + k * n * sizeof(float) + n * sizeof(float); } else { @@ -127,21 +174,22 @@ class tensor_traits : public ggml::cpu:: return true; } - bool compute_forward(struct ggml_compute_params * params, struct ggml_tensor * dst) override { if (dst->op == GGML_OP_MUL_MAT) { if (dst->src[0]->type == GGML_TYPE_Q4_0) { return compute_forward_q4_0(params, dst); } else if (dst->src[0]->type == GGML_TYPE_F16) { - return compute_forward_kv_cache(params, dst); + return compute_forward_fp16(params, dst); + } + } else if (dst->op == GGML_OP_GET_ROWS) { + if (dst->src[0]->type == GGML_TYPE_Q4_0) { + return compute_forward_get_rows(params, dst); } } return false; } - bool compute_forward_kv_cache(ggml_compute_params * params, struct ggml_tensor * dst) { - static std::atomic_flag first_to_arrive = ATOMIC_FLAG_INIT; - + bool compute_forward_fp16(ggml_compute_params * params, struct ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; @@ -150,7 +198,9 @@ class tensor_traits : public ggml::cpu:: ggml_kleidiai_kernels *kernels = ggml_kleidiai_select_kernels(ctx.features, dst); GGML_ASSERT(kernels); - kernel_info * kernel = src1->ne[1] == 1 ? &kernels->gemv : &kernels->gemm; + const bool is_gemv = src1->ne[1] == 1; + kernel_info * kernel = is_gemv ? &kernels->gemv : &kernels->gemm; + lhs_packing_info * lhs_info = is_gemv ? &kernels->gemv_lhs_info : &kernels->gemm_lhs_info; GGML_ASSERT(kernel); const int nth = params->nth; @@ -158,27 +208,30 @@ class tensor_traits : public ggml::cpu:: const int64_t lhs_batch_size0 = ne12; const int64_t rhs_batch_size0 = ne02; - const int64_t batch_size = rhs_batch_size0; + const int64_t batch_size = lhs_batch_size0; + GGML_ASSERT(rhs_batch_size0 > 0); + GGML_ASSERT(lhs_batch_size0 % rhs_batch_size0 == 0); const int64_t r = lhs_batch_size0 / rhs_batch_size0; - const int64_t m = ne11 * r; - const int64_t n = ne01; - const int64_t k = ne00; + const int64_t m_group = ne11; + const int64_t m = m_group; + const int64_t n = ne01; + const int64_t k = ne00; const size_t lhs_stride = src1->nb[1]; const size_t rhs_stride = src0->nb[1]; const size_t dst_stride = dst->nb[1]; - const int64_t mr = static_cast(kernel->get_mr()); - const int64_t nr = static_cast(kernel->get_nr()); - const int64_t kr = static_cast(kernel->get_kr()); - const int64_t sr = static_cast(kernel->get_sr()); - - const size_t lhs_packed_size = variant_call(kernels->lhs_info.packed_size, m, k, mr, kr, sr); - const size_t rhs_packed_size = variant_call(kernels->rhs_info.packed_size, n, k); - const size_t kxn_size = k * n * sizeof(float); - const size_t bias_size = n * sizeof(float); + const int64_t mr = (int64_t) kernel->get_mr(); + const int64_t nr = (int64_t) kernel->get_nr(); + const int64_t kr = (int64_t) kernel->get_kr(); + const int64_t sr = (int64_t) kernel->get_sr(); + + const size_t lhs_packed_size = variant_call(lhs_info->packed_size, (size_t)m, (size_t)k, (size_t)mr, (size_t)kr, (size_t)sr); + const size_t rhs_packed_size = variant_call(kernels->rhs_info.packed_size, (size_t)n, (size_t)k); + const size_t kxn_size = (size_t)k * (size_t)n * sizeof(float); + const size_t bias_size = (size_t)n * sizeof(float); const size_t wsize_required = lhs_packed_size + rhs_packed_size + kxn_size + bias_size; GGML_ASSERT(wsize_required <= params->wsize); @@ -189,79 +242,102 @@ class tensor_traits : public ggml::cpu:: uint8_t * bias = rhs_kxn + kxn_size; for (int64_t batch_idx = 0; batch_idx < batch_size; ++batch_idx) { - const uint8_t * lhs_batch = static_cast(src1->data) + batch_idx * m * lhs_stride; - const uint8_t * rhs_batch = static_cast(src0->data) + batch_idx * n * rhs_stride; - uint8_t * dst_batch = static_cast(dst->data) + batch_idx * m * dst_stride; + const int64_t rhs_batch_idx = batch_idx / r; + const uint8_t * rhs_batch_base = static_cast(src0->data) + rhs_batch_idx * src0->nb[2]; + uint8_t * dst_batch_base = static_cast(dst->data) + batch_idx * dst->nb[2]; - // LHS packing + // LHS packing (threaded over m, honoring mr alignment and KV groups) { const int64_t m_roundup_mr = kai_roundup(m, mr); const int64_t num_threads = KAI_MIN(m_roundup_mr / mr, nth); if (ith < num_threads) { - const int64_t num_m_per_thread0 = round_down(m_roundup_mr / num_threads, mr); + const int64_t num_m_per_thread0 = round_down((size_t)(m_roundup_mr / num_threads), (size_t)mr); const int64_t num_m_per_threadN_1 = m - (num_threads - 1) * num_m_per_thread0; - const int64_t m_start = ith * num_m_per_thread0; - const int64_t num_m_per_thread = (ith == num_threads - 1) ? num_m_per_threadN_1 : num_m_per_thread0; - - const size_t lhs_offset = variant_call(kernels->gemm.get_lhs_offset, m_start, lhs_stride); - const size_t lhs_packed_offset = variant_call(kernels->lhs_info.get_packed_offset, m_start, k, mr, kr, sr); - - const void * src_ptr = static_cast(lhs_batch) + lhs_offset; - void * dst_ptr = static_cast(lhs_packed) + lhs_packed_offset; + const int64_t m_start = ith * num_m_per_thread0; + const int64_t m_count = (ith == num_threads - 1) ? num_m_per_threadN_1 : num_m_per_thread0; - variant_call(kernels->lhs_info.pack_func, num_m_per_thread, k, mr, kr, sr, 0, src_ptr, lhs_stride, dst_ptr); + // Base packed offset (aligned) and per-row stride in bytes + const size_t base_packed_off = variant_call( + lhs_info->get_packed_offset, (size_t)m_start, (size_t)k, (size_t)mr, (size_t)kr, (size_t)sr); + const size_t next_block_off = variant_call( + lhs_info->get_packed_offset, (size_t)(m_start + mr), (size_t)k, (size_t)mr, (size_t)kr, (size_t)sr); + const size_t row_stride_bytes = (next_block_off - base_packed_off) / (size_t)mr; + + int64_t remaining = m_count; + int64_t cur = m_start; + + while (remaining > 0) { + const int64_t row_in_group = cur; + const int64_t avail = m_group - row_in_group; + const int64_t take = std::min(avail, remaining); + + const uint8_t * lhs_batch_base = static_cast(src1->data) + batch_idx * src1->nb[2]; + const void * src_ptr = lhs_batch_base + (size_t)row_in_group * lhs_stride; + const size_t dst_off = base_packed_off + (size_t)(cur - m_start) * row_stride_bytes; + void * dst_ptr = lhs_packed + dst_off; + + variant_call(lhs_info->pack_func, + (size_t)take, (size_t)k, (size_t)mr, (size_t)kr, (size_t)sr, + /*m_idx_start*/ 0, src_ptr, lhs_stride, dst_ptr); + + cur += take; + remaining -= take; + } } } - // RHS packing - if (first_to_arrive.test_and_set(std::memory_order_acquire) == false) { - // First thread to reach this point handles RHS packing - memset(bias, 0, n * sizeof(float)); - transpose_f32kxn_f16nxk(n, k, reinterpret_cast(rhs_kxn), - reinterpret_cast(rhs_batch), rhs_stride); - - variant_call(kernels->rhs_info.pack_func, 1, n, k, nr, kr, sr, n * sizeof(float), - rhs_kxn, bias, nullptr, rhs_packed, 0, nullptr); + // RHS packing (single thread), then synchronize + if (ith == 0) { + memset(bias, 0, (size_t)n * sizeof(float)); + transpose_f32kxn_f16nxk((size_t)n, (size_t)k, + reinterpret_cast(rhs_kxn), + reinterpret_cast(rhs_batch_base), + rhs_stride); + + variant_call(kernels->rhs_info.pack_func, + /*num_groups*/ 1, (size_t)n, (size_t)k, (size_t)nr, (size_t)kr, (size_t)sr, + /*rhs_stride (bytes)*/ (size_t)(n * sizeof(float)), + rhs_kxn, bias, nullptr, rhs_packed, /*extra_bytes*/ 0, /*params*/ nullptr); } ggml_barrier(params->threadpool); - first_to_arrive.clear(std::memory_order_release); - - // Perform the matmul + // Matmul (threaded over n) { - const int64_t m_to_process = m; - const int64_t m_start = 0; - - const int64_t n_step = static_cast(kernel->get_n_step()); - const int64_t num_threads = KAI_MIN(n / n_step, nth); + const int64_t n_step = (int64_t) kernel->get_n_step(); + int64_t num_threads_n = KAI_MIN(n / n_step, nth); + if (num_threads_n <= 0) { + num_threads_n = 1; + } - if (ith < num_threads) { - const int64_t num_n_per_thread0 = round_down(n / num_threads, n_step); - const int64_t num_n_per_threadN_1 = n - (num_threads - 1) * num_n_per_thread0; + if (ith < num_threads_n) { + const int64_t num_n_per_thread0 = round_down((size_t)(n / num_threads_n), (size_t)n_step); + const int64_t num_n_per_threadN_1 = n - (num_threads_n - 1) * num_n_per_thread0; const int64_t n_start = ith * num_n_per_thread0; - const int64_t n_to_process = (ith == num_threads - 1) ? num_n_per_threadN_1 : num_n_per_thread0; + const int64_t n_to_process = (ith == num_threads_n - 1) ? num_n_per_threadN_1 : num_n_per_thread0; - const size_t lhs_packed_offset = variant_call(kernel->get_lhs_offset, m_start, k); - const size_t rhs_packed_offset = variant_call(kernel->get_rhs_packed_offset, n_start, k); - const size_t dst_offset = kernel->get_dst_offset(m_start, n_start, dst_stride); + // LHS packed base at row 0 (consistent with packing above) + const size_t lhs_packed_offset0 = variant_call( + lhs_info->get_packed_offset, (size_t)0, (size_t)k, (size_t)mr, (size_t)kr, (size_t)sr); + const size_t rhs_packed_offset = variant_call(kernel->get_rhs_packed_offset, (size_t)n_start, (size_t)k); + const size_t dst_offset = kernel->get_dst_offset((size_t)0, (size_t)n_start, dst_stride); - const void * lhs_ptr = lhs_packed + lhs_packed_offset; + const void * lhs_ptr = lhs_packed + lhs_packed_offset0; const void * rhs_ptr = rhs_packed + rhs_packed_offset; - float * dst_ptr = reinterpret_cast(dst_batch + dst_offset); + float * dst_ptr = reinterpret_cast(dst_batch_base + dst_offset); - variant_call(kernel->run_kernel, m_to_process, n_to_process, k, lhs_ptr, rhs_ptr, dst_ptr, dst_stride, sizeof(float), -FLT_MAX, FLT_MAX); + variant_call(kernel->run_kernel, + (size_t)m, (size_t)n_to_process, (size_t)k, + lhs_ptr, rhs_ptr, + dst_ptr, dst_stride, sizeof(float), + -FLT_MAX, FLT_MAX); } } if (batch_idx != batch_size - 1) { - // This barrier is necessary when the batch size is larger than 1. While processing a batch, - // the work data buffer (params->wdata) is used as temporary storage which means that only - // a single batch can be processed at any given time. No barrier is needed for the last - // batch since GGML inserts a barrier between the execution of every operator. ggml_barrier(params->threadpool); } } @@ -270,6 +346,8 @@ class tensor_traits : public ggml::cpu:: } bool compute_forward_q4_0(struct ggml_compute_params * params, struct ggml_tensor * dst) { + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_Q4_0); + const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; @@ -278,13 +356,15 @@ class tensor_traits : public ggml::cpu:: ggml_kleidiai_kernels *kernels = ggml_kleidiai_select_kernels(ctx.features, dst); GGML_ASSERT(kernels); - kernel_info * kernel = src1->ne[1] == 1 ? &kernels->gemv : &kernels->gemm; - lhs_packing_info * lhs_info = &kernels->lhs_info; + bool is_gemv = src1->ne[1] == 1; + kernel_info * kernel = is_gemv ? &kernels->gemv : &kernels->gemm; + lhs_packing_info * lhs_info = is_gemv ? &kernels->gemv_lhs_info : &kernels->gemm_lhs_info; GGML_ASSERT(kernel); const int ith = params->ith; - const int nth = params->nth; + const int nth_raw = params->nth; + const int nth = nth_raw > 0 ? nth_raw : 1; const size_t k = ne00; const size_t m = ne11; @@ -302,9 +382,12 @@ class tensor_traits : public ggml::cpu:: const size_t num_n_per_thread = kai_roundup(kai_roundup(n, nth) / nth, n_step); const size_t n_start = ith * num_n_per_thread; - size_t n_to_process = num_n_per_thread; - if ((n_start + n_to_process) > n) { - n_to_process = n - n_start; + size_t n_to_process = 0; + if (n_start < n) { + n_to_process = num_n_per_thread; + if ((n_start + n_to_process) > n) { + n_to_process = n - n_start; + } } // Calculate number of columns to be processed per thread @@ -336,14 +419,57 @@ class tensor_traits : public ggml::cpu:: const void* lhs_ptr = (const void*)((const char *)lhs_packed + lhs_packed_offset); float *dst_ptr = reinterpret_cast(static_cast(dst->data) + dst_offset); - variant_call(kernel->run_kernel, m, n_to_process, k, QK4_0, lhs_ptr, rhs_ptr, dst_ptr, dst_stride, - sizeof(float), -FLT_MAX, FLT_MAX); + if (n_to_process > 0) { + variant_call(kernel->run_kernel, m, n_to_process, k, QK4_0, lhs_ptr, rhs_ptr, dst_ptr, dst_stride, + sizeof(float), -FLT_MAX, FLT_MAX); + } + + return true; + } + + bool compute_forward_get_rows(struct ggml_compute_params * params, struct ggml_tensor * dst) { + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_Q4_0); + GGML_ASSERT(ctx.kernels); + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + GGML_TENSOR_BINARY_OP_LOCALS + + rhs_packing_info * rhs_info = &ctx.kernels->rhs_info; + kernel_info * kernel = &ctx.kernels->gemm; + + const int64_t nc = ne00; + const int64_t nr = ggml_nelements(src1); + + const size_t block_rows = kernel->get_nr(); + const size_t kr = kernel->get_kr(); + + const size_t num_bytes_multiplier = sizeof(uint16_t); + const size_t packed_stride = rhs_info->packed_stride(nc, block_rows, kr, QK4_0); + + const int ith = params->ith; + const int nth = params->nth; + + const int dr = (nr + nth - 1) / nth; + const int ir0 = dr * ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int64_t i = ir0; i < ir1; ++i) { + GGML_ASSERT(src1->type == GGML_TYPE_I32); + int64_t row_idx = ((const int32_t *)src1->data)[i]; + GGML_ASSERT(row_idx >= 0 && row_idx < src0->ne[1]); + + float *out = (float *)((char *)dst->data + i * nb1); + rhs_info->to_float(src0->data, row_idx, nc, out, block_rows, packed_stride, kr, QK4_0, num_bytes_multiplier); + } return true; } public: int repack(struct ggml_tensor * tensor, const void * data, size_t data_size) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0); GGML_ASSERT(ctx.kernels); const size_t n = tensor->ne[1]; const size_t k = tensor->ne[0]; @@ -351,17 +477,12 @@ public: size_t kr = ctx.kernels->gemm.get_kr(); size_t sr = ctx.kernels->gemm.get_sr(); -#ifndef NDEBUG - const size_t repacked_size = variant_call(ctx.kernels->rhs_info.packed_size, n, k, nr, kr, QK4_0); - GGML_ASSERT(repacked_size <= data_size && "repacked size larger than the packed size!"); -#endif struct kai_rhs_pack_qs4cxs1s0_param params; params.lhs_zero_point = 1; params.rhs_zero_point = 8; variant_call(ctx.kernels->rhs_info.pack_func, 1, n, k, nr, kr, sr, QK4_0, (const uint8_t*)data, nullptr, tensor->data, 0, ¶ms); return 0; - GGML_UNUSED(data_size); } }; @@ -375,8 +496,8 @@ static ggml::cpu::tensor_traits * get_te static enum ggml_status ggml_backend_cpu_kleidiai_buffer_init_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor) { tensor->extra = (void *) ggml::cpu::kleidiai::get_tensor_traits(buffer, tensor); - GGML_UNUSED(buffer); return GGML_STATUS_SUCCESS; + GGML_UNUSED(buffer); } static void ggml_backend_cpu_kleidiai_buffer_set_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, @@ -418,10 +539,24 @@ static size_t ggml_backend_cpu_kleidiai_ GGML_UNUSED(buft); } +static size_t ggml_backend_cpu_kleidiai_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const struct ggml_tensor * tensor) { + GGML_ASSERT(tensor->type == GGML_TYPE_Q4_0); + GGML_ASSERT(ctx.kernels); + + const size_t n = tensor->ne[1]; + const size_t k = tensor->ne[0]; + const size_t nr = ctx.kernels->gemm.get_nr(); + const size_t kr = ctx.kernels->gemm.get_kr(); + + return variant_call(ctx.kernels->rhs_info.packed_size, n, k, nr, kr, QK4_0); + + GGML_UNUSED(buft); +} + namespace ggml::cpu::kleidiai { class extra_buffer_type : ggml::cpu::extra_buffer_type { bool supports_op(ggml_backend_dev_t, const struct ggml_tensor * op) override { - if (op->op == GGML_OP_MUL_MAT && + if ((op->op == GGML_OP_MUL_MAT || op->op == GGML_OP_GET_ROWS) && op->src[0]->type == GGML_TYPE_Q4_0 && op->src[0]->buffer && (ggml_n_dims(op->src[0]) == 2) && @@ -429,7 +564,7 @@ class extra_buffer_type : ggml::cpu::ext if (op->src[1]->buffer && !ggml_backend_buft_is_host(op->src[1]->buffer->buft)) { return false; } - if (op->src[1]->type == GGML_TYPE_F32 && + if ((op->src[1]->type == GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_I32) && ggml_ne(op->src[1], 2) == 1 && ggml_ne(op->src[1], 3) == 1) { return true; } @@ -438,17 +573,12 @@ class extra_buffer_type : ggml::cpu::ext } ggml::cpu::tensor_traits * get_tensor_traits(const struct ggml_tensor * op) override { - if (op->op == GGML_OP_MUL_MAT) { + if (op->op == GGML_OP_MUL_MAT || op->op == GGML_OP_GET_ROWS) { if (op->src[0]->buffer && op->src[0]->buffer->buft == ggml_backend_cpu_kleidiai_buffer_type()) { return (ggml::cpu::tensor_traits *) op->src[0]->extra; } - else if (ggml_kleidiai_select_kernels(ctx.features, op) && - op->src[0]->op == GGML_OP_VIEW && - (op->src[1]->op == GGML_OP_PERMUTE || op->src[1]->op == GGML_OP_SOFT_MAX) && - op->src[1]->ne[1] > 1) { - if ((op->src[0]->nb[0] != 2) || - (op->src[1]->nb[0] != 4) || - (op->src[0]->nb[1] * op->src[0]->ne[1] != op->src[0]->nb[2]) || + else if (ggml_kleidiai_select_kernels(ctx.features, op) && op->src[1]->ne[1] > 1) { + if ((op->src[0]->nb[1] * op->src[0]->ne[1] != op->src[0]->nb[2]) || (op->src[1]->nb[1] * op->src[1]->ne[1] != op->src[1]->nb[2])) { return nullptr; } @@ -469,7 +599,7 @@ ggml_backend_buffer_type_t ggml_backend_ /* .alloc_buffer = */ ggml_backend_cpu_kleidiai_buffer_type_alloc_buffer, /* .get_alignment = */ ggml_backend_cpu_kleidiai_buffer_type_get_alignment, /* .get_max_size = */ nullptr, // defaults to SIZE_MAX - /* .get_alloc_size = */ nullptr, // defaults to ggml_nbytes + /* .get_alloc_size = */ ggml_backend_cpu_kleidiai_buffer_type_get_alloc_size, /* .is_host = */ nullptr, }, /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/llamafile/sgemm.cpp 6641+dfsg-2/ggml/src/ggml-cpu/llamafile/sgemm.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/llamafile/sgemm.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/llamafile/sgemm.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -1541,7 +1541,7 @@ class tinyBLAS_BF16_PPC { } else if constexpr(RM == 8 && RN == 4) { KERNEL_8x4(ii,jj); } else { - static_assert(false, "RN/RM values not supported"); + assert(false && "RN/RM values not supported"); } } @@ -1573,13 +1573,13 @@ class tinyBLAS_BF16_PPC { const int nth; }; -template +template class tinyBLAS_Q0_PPC { public: tinyBLAS_Q0_PPC(int64_t k, const TA *A, int64_t lda, - const TB *B, int64_t ldb, - TC *C, int64_t ldc, + const block_q8_0 *B, int64_t ldb, + float *C, int64_t ldc, int ith, int nth) : A(A), B(B), C(C), k(k), lda(lda), ldb(ldb), ldc(ldc), ith(ith), nth(nth) { } @@ -1590,8 +1590,7 @@ class tinyBLAS_Q0_PPC { private: - template - inline void save_res(int ii, int jj, int idx, vector float* fin_res) { + inline void save_res(int ii, int jj, int idx, vector float* fin_res, int RM=4, int RN=4) { for (int I = 0; I < RM; I++) { for (int J = 0; J < RN; J++) { *((float*)(C+ii+((jj+J)*ldc)+I)) = *((float*)&fin_res[idx+I]+J); @@ -1611,29 +1610,67 @@ class tinyBLAS_Q0_PPC { fin_res[s_idx+i] = vec_madd(res[i], vs[s_idx+i], fin_res[s_idx+i]); } } - - template - void packNormalInt4(const TA* a, int64_t lda, int rows, int cols, VA* vec, std::array& comparray) { - int64_t i, j; - TA *aoffset = NULL; - VA *vecOffset = NULL; - TA *aoffset1 = NULL, *aoffset2 = NULL, *aoffset3 = NULL, *aoffset4 = NULL; - TA *aoffset5 = NULL, *aoffset6 = NULL, *aoffset7 = NULL, *aoffset8 = NULL; - VB c1[2] = {0}, c2[2] = {0}, c3[2] = {0}, c4[2] = {0}; - VB c5[2] = {0}, c6[2] = {0}, c7[2] = {0}, c8[2] = {0}; - VB t1, t2, t3, t4, t5, t6, t7, t8; + /* This function processes quantized data from block_q4_0 elements. + * First the we try to extract the two int4 values stored in single int8_t into two signed int8. + * And then we subtract each of the resultant element with 8, to convert signed int8 to unsigned int8. + * Also compute the rowsum which is required to compensate the above conversion. */ + inline void process_q4_elements(vector signed char (&c)[2], int* ca) { const vector signed char lowMask = vec_splats((signed char)0xF); const vector unsigned char v4 = vec_splats((unsigned char)0x4); const vector signed char v8 = vec_splats((signed char)0x8); - aoffset = const_cast(a); - vecOffset = vec; + vector signed int vsum = {0}; + vector signed int vsum2 = {0}; + c[0] = vec_and(c[1], lowMask); + c[1] = vec_sr(c[1], v4); + c[0] = vec_sub(c[0], v8); + c[1] = vec_sub(c[1], v8); + vsum = vec_sum4s(c[0], vsum); + vsum2 = vec_sum4s(c[1], vsum2); + vsum = vec_add(vsum, vsum2); + *(ca) = vsum[0] + vsum[1] + vsum[2] + vsum[3]; + } + + template + inline void vector_permute_store(V2 &s1, V2 &s2, V2 &s3, V2 &s4, V1 *vecOffset, bool flip) { vector unsigned char swiz1 = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; vector unsigned char swiz2 = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}; vector unsigned char swiz3 = {0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}; vector unsigned char swiz4 = {4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}; - vector signed int vsum = {0}; - vector signed int vsum2 = {0}; + V2 t1, t2, t3, t4, t5, t6, t7, t8; + vector unsigned char xor_vector; + uint8_t flip_vec = 0x80; + xor_vector = vec_splats(flip_vec); + t1 = vec_perm(s1, s2, swiz1); + t2 = vec_perm(s1, s2, swiz2); + t3 = vec_perm(s3, s4, swiz1); + t4 = vec_perm(s3, s4, swiz2); + t5 = vec_perm(t1, t3, swiz3); + t6 = vec_perm(t1, t3, swiz4); + t7 = vec_perm(t2, t4, swiz3); + t8 = vec_perm(t2, t4, swiz4); + if (flip == true) { + t5 = vec_xor(t5, xor_vector); + t6 = vec_xor(t6, xor_vector); + t7 = vec_xor(t7, xor_vector); + t8 = vec_xor(t8, xor_vector); + } + vec_xst(t5, 0, vecOffset); + vec_xst(t6, 0, vecOffset+16); + vec_xst(t7, 0, vecOffset+32); + vec_xst(t8, 0, vecOffset+48); + } + template + void packNormalInt4(const TA* a, int64_t lda, int rows, int cols, int8_t* vec, std::array& comparray) { + int64_t i, j; + TA *aoffset = NULL; + int8_t *vecOffset = NULL; + TA *aoffset1 = NULL, *aoffset2 = NULL, *aoffset3 = NULL, *aoffset4 = NULL; + TA *aoffset5 = NULL, *aoffset6 = NULL, *aoffset7 = NULL, *aoffset8 = NULL; + vector signed char c1[2] = {0}, c2[2] = {0}, c3[2] = {0}, c4[2] = {0}; + vector signed char c5[2] = {0}, c6[2] = {0}, c7[2] = {0}, c8[2] = {0}; + aoffset = const_cast(a); + vecOffset = vec; j = (rows >> 3); if (j > 0) { do { @@ -1646,159 +1683,30 @@ class tinyBLAS_Q0_PPC { aoffset7 = aoffset6 + lda; aoffset8 = aoffset7 + lda; aoffset += 8 * lda; - i = (cols >> 2); if (i > 0) { do { - c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); - c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); - c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); - c4[1] = reinterpret_cast(vec_xl(0, aoffset4->qs)); - c5[1] = reinterpret_cast(vec_xl(0, aoffset5->qs)); - c6[1] = reinterpret_cast(vec_xl(0, aoffset6->qs)); - c7[1] = reinterpret_cast(vec_xl(0, aoffset7->qs)); - c8[1] = reinterpret_cast(vec_xl(0, aoffset8->qs)); - - c1[0] = vec_and(c1[1], lowMask); - c1[1] = vec_sr(c1[1], v4); - c1[0] = vec_sub(c1[0], v8); - c1[1] = vec_sub(c1[1], v8); - vsum = vec_sum4s(c1[0], vsum); - vsum2 = vec_sum4s(c1[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[0] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c2[0] = vec_and(c2[1], lowMask); - c2[1] = vec_sr(c2[1], v4); - c2[0] = vec_sub(c2[0], v8); - c2[1] = vec_sub(c2[1], v8); - vsum = vec_sum4s(c2[0], vsum); - vsum2 = vec_sum4s(c2[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[1] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c3[0] = vec_and(c3[1], lowMask); - c3[1] = vec_sr(c3[1], v4); - c3[0] = vec_sub(c3[0], v8); - c3[1] = vec_sub(c3[1], v8); - vsum = vec_sum4s(c3[0], vsum); - vsum2 = vec_sum4s(c3[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[2] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c4[0] = vec_and(c4[1], lowMask); - c4[1] = vec_sr(c4[1], v4); - c4[0] = vec_sub(c4[0], v8); - c4[1] = vec_sub(c4[1], v8); - vsum = vec_sum4s(c4[0], vsum); - vsum2 = vec_sum4s(c4[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[3] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c5[0] = vec_and(c5[1], lowMask); - c5[1] = vec_sr(c5[1], v4); - c5[0] = vec_sub(c5[0], v8); - c5[1] = vec_sub(c5[1], v8); - vsum = vec_sum4s(c5[0], vsum); - vsum2 = vec_sum4s(c5[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[4] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c6[0] = vec_and(c6[1], lowMask); - c6[1] = vec_sr(c6[1], v4); - c6[0] = vec_sub(c6[0], v8); - c6[1] = vec_sub(c6[1], v8); - vsum = vec_sum4s(c6[0], vsum); - vsum2 = vec_sum4s(c6[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[5] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c7[0] = vec_and(c7[1], lowMask); - c7[1] = vec_sr(c7[1], v4); - c7[0] = vec_sub(c7[0], v8); - c7[1] = vec_sub(c7[1], v8); - vsum = vec_sum4s(c7[0], vsum); - vsum2 = vec_sum4s(c7[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[6] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c8[0] = vec_and(c8[1], lowMask); - c8[1] = vec_sr(c8[1], v4); - c8[0] = vec_sub(c8[0], v8); - c8[1] = vec_sub(c8[1], v8); - vsum = vec_sum4s(c8[0], vsum); - vsum2 = vec_sum4s(c8[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[7] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); - - t1 = vec_perm(c5[0], c6[0], swiz1); - t2 = vec_perm(c5[0], c6[0], swiz2); - t3 = vec_perm(c7[0], c8[0], swiz1); - t4 = vec_perm(c7[0], c8[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset+128); - vec_xst(t6, 0, vecOffset+144); - vec_xst(t7, 0, vecOffset+160); - vec_xst(t8, 0, vecOffset+176); - - t1 = vec_perm(c5[1], c6[1], swiz1); - t2 = vec_perm(c5[1], c6[1], swiz2); - t3 = vec_perm(c7[1], c8[1], swiz1); - t4 = vec_perm(c7[1], c8[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset+192); - vec_xst(t6, 0, vecOffset+208); - vec_xst(t7, 0, vecOffset+224); - vec_xst(t8, 0, vecOffset+240); - + c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); + c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); + c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); + c4[1] = reinterpret_cast(vec_xl(0, aoffset4->qs)); + c5[1] = reinterpret_cast(vec_xl(0, aoffset5->qs)); + c6[1] = reinterpret_cast(vec_xl(0, aoffset6->qs)); + c7[1] = reinterpret_cast(vec_xl(0, aoffset7->qs)); + c8[1] = reinterpret_cast(vec_xl(0, aoffset8->qs)); + + process_q4_elements(c1, &comparray[0]); + process_q4_elements(c2, &comparray[1]); + process_q4_elements(c3, &comparray[2]); + process_q4_elements(c4, &comparray[3]); + process_q4_elements(c5, &comparray[4]); + process_q4_elements(c6, &comparray[5]); + process_q4_elements(c7, &comparray[6]); + process_q4_elements(c8, &comparray[7]); + vector_permute_store(c1[0], c2[0], c3[0], c4[0], vecOffset, false); + vector_permute_store(c1[1], c2[1], c3[1], c4[1], vecOffset+64, false); + vector_permute_store(c5[0], c6[0], c7[0], c8[0], vecOffset+128, false); + vector_permute_store(c5[1], c6[1], c7[1], c8[1], vecOffset+192, false); aoffset1 += lda; aoffset2 += lda; aoffset3 += lda; @@ -1821,85 +1729,20 @@ class tinyBLAS_Q0_PPC { aoffset3 = aoffset2 + lda; aoffset4 = aoffset3 + lda; aoffset += 4 * lda; - i = (cols >> 2); if (i > 0) { do { - c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); - c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); - c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); - c4[1] = reinterpret_cast(vec_xl(0, aoffset4->qs)); - - c1[0] = vec_and(c1[1], lowMask); - c1[1] = vec_sr(c1[1], v4); - c1[0] = vec_sub(c1[0], v8); - c1[1] = vec_sub(c1[1], v8); - vsum = vec_sum4s(c1[0], vsum); - vsum2 = vec_sum4s(c1[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[0] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c2[0] = vec_and(c2[1], lowMask); - c2[1] = vec_sr(c2[1], v4); - c2[0] = vec_sub(c2[0], v8); - c2[1] = vec_sub(c2[1], v8); - vsum = vec_sum4s(c2[0], vsum); - vsum2 = vec_sum4s(c2[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[1] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c3[0] = vec_and(c3[1], lowMask); - c3[1] = vec_sr(c3[1], v4); - c3[0] = vec_sub(c3[0], v8); - c3[1] = vec_sub(c3[1], v8); - vsum = vec_sum4s(c3[0], vsum); - vsum2 = vec_sum4s(c3[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[2] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c4[0] = vec_and(c4[1], lowMask); - c4[1] = vec_sr(c4[1], v4); - c4[0] = vec_sub(c4[0], v8); - c4[1] = vec_sub(c4[1], v8); - vsum = vec_sum4s(c4[0], vsum); - vsum2 = vec_sum4s(c4[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[3] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats( 0); - - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); - + c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); + c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); + c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); + c4[1] = reinterpret_cast(vec_xl(0, aoffset4->qs)); + + process_q4_elements(c1, &comparray[0]); + process_q4_elements(c2, &comparray[1]); + process_q4_elements(c3, &comparray[2]); + process_q4_elements(c4, &comparray[3]); + vector_permute_store(c1[0], c2[0], c3[0], c4[0], vecOffset, false); + vector_permute_store(c1[1], c2[1], c3[1], c4[1], vecOffset+64, false); aoffset1 += lda; aoffset2 += lda; aoffset3 += lda; @@ -1918,80 +1761,17 @@ class tinyBLAS_Q0_PPC { if (i > 0) { do { switch(rows) { - case 3: c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); - case 2: c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); - case 1: c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); + case 3: c3[1] = reinterpret_cast(vec_xl(0, aoffset3->qs)); + case 2: c2[1] = reinterpret_cast(vec_xl(0, aoffset2->qs)); + case 1: c1[1] = reinterpret_cast(vec_xl(0, aoffset1->qs)); break; } - c1[0] = vec_and(c1[1], lowMask); - c1[1] = vec_sr(c1[1], v4); - c1[0] = vec_sub(c1[0], v8); - c1[1] = vec_sub(c1[1], v8); - vsum = vec_sum4s(c1[0], vsum); - vsum2 = vec_sum4s(c1[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[0] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c2[0] = vec_and(c2[1], lowMask); - c2[1] = vec_sr(c2[1], v4); - c2[0] = vec_sub(c2[0], v8); - c2[1] = vec_sub(c2[1], v8); - vsum = vec_sum4s(c2[0], vsum); - vsum2 = vec_sum4s(c2[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[1] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c3[0] = vec_and(c3[1], lowMask); - c3[1] = vec_sr(c3[1], v4); - c3[0] = vec_sub(c3[0], v8); - c3[1] = vec_sub(c3[1], v8); - vsum = vec_sum4s(c3[0], vsum); - vsum2 = vec_sum4s(c3[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[2] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - c4[0] = vec_and(c4[1], lowMask); - c4[1] = vec_sr(c4[1], v4); - c4[0] = vec_sub(c4[0], v8); - c4[1] = vec_sub(c4[1], v8); - vsum = vec_sum4s(c4[0], vsum); - vsum2 = vec_sum4s(c4[1], vsum2); - vsum = vec_add(vsum, vsum2); - comparray[3] = vsum[0] + vsum[1] + vsum[2] + vsum[3]; - vsum = vec_splats(0); - vsum2 = vec_splats(0); - - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); + process_q4_elements(c1, &comparray[0]); + process_q4_elements(c2, &comparray[1]); + process_q4_elements(c3, &comparray[2]); + process_q4_elements(c4, &comparray[3]); + vector_permute_store(c1[0], c2[0], c3[0], c4[0], vecOffset, false); + vector_permute_store(c1[1], c2[1], c3[1], c4[1], vecOffset+64, false); aoffset1 += lda; aoffset2 += lda; aoffset3 += lda; @@ -2001,146 +1781,40 @@ class tinyBLAS_Q0_PPC { } } } - template - void packNormal(const TB* a, int64_t lda, int rows, int cols, VA* vec, bool flip) { + void packNormal(const block_q8_0* a, int64_t lda, int rows, int cols, VA* vec, bool flip) { int64_t i, j; - TB *aoffset = NULL; + block_q8_0 *aoffset = NULL; VA *vecOffset = NULL; - TB *aoffset1 = NULL, *aoffset2 = NULL, *aoffset3 = NULL, *aoffset4 = NULL; - TB *aoffset5 = NULL, *aoffset6 = NULL, *aoffset7 = NULL, *aoffset8 = NULL; - __vector_pair C1, C2, C3, C4, C5, C6, C7, C8; - VB c1[2] = {0}, c2[2] = {0}, c3[2] = {0}, c4[2]={0}; - VB c5[2] = {0}, c6[2] = {0}, c7[2] = {0}, c8[2]={0}; - VB t1, t2, t3, t4, t5, t6, t7, t8; - vector unsigned char xor_vector; - uint8_t flip_vec = 0x80; - xor_vector = vec_splats(flip_vec); - vector unsigned char swiz1 = {0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23}; - vector unsigned char swiz2 = {8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31}; - vector unsigned char swiz3 = {0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}; - vector unsigned char swiz4 = {4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}; - - aoffset = const_cast(a); + block_q8_0* aoffsets[8]; + __vector_pair arr[8]; + VB c[8][2] = {0}; + VB c1[8] = {0}; VB c2[8] = {0}; + aoffset = const_cast(a); vecOffset = vec; j = (rows >> 3); if (j > 0) { do { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; - aoffset4 = aoffset3 + lda; - aoffset5 = aoffset4 + lda; - aoffset6 = aoffset5 + lda; - aoffset7 = aoffset6 + lda; - aoffset8 = aoffset7 + lda; + aoffsets[0] = aoffset; + for (int it = 1; it < 8; it++) + aoffsets[it] = aoffsets[it-1] + lda; aoffset += 8 * lda; i = (cols >> 3); if (i > 0) { do { - C1 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset1->qs); - C2 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset2->qs); - C3 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset3->qs); - C4 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset4->qs); - C5 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset5->qs); - C6 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset6->qs); - C7 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset7->qs); - C8 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset8->qs); - - __builtin_vsx_disassemble_pair(c1, &C1); - __builtin_vsx_disassemble_pair(c2, &C2); - __builtin_vsx_disassemble_pair(c3, &C3); - __builtin_vsx_disassemble_pair(c4, &C4); - __builtin_vsx_disassemble_pair(c5, &C5); - __builtin_vsx_disassemble_pair(c6, &C6); - __builtin_vsx_disassemble_pair(c7, &C7); - __builtin_vsx_disassemble_pair(c8, &C8); - - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); - } - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); + for (int it = 0; it < 8; it++) { + arr[it] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[it]->qs); + __builtin_vsx_disassemble_pair(c[it], &arr[it]); + c1[it] = c[it][0]; + c2[it] = c[it][1]; } - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); - - t1 = vec_perm(c5[0], c6[0], swiz1); - t2 = vec_perm(c5[0], c6[0], swiz2); - t3 = vec_perm(c7[0], c8[0], swiz1); - t4 = vec_perm(c7[0], c8[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); - } - vec_xst(t5, 0, vecOffset+128); - vec_xst(t6, 0, vecOffset+144); - vec_xst(t7, 0, vecOffset+160); - vec_xst(t8, 0, vecOffset+176); - - t1 = vec_perm(c5[1], c6[1], swiz1); - t2 = vec_perm(c5[1], c6[1], swiz2); - t3 = vec_perm(c7[1], c8[1], swiz1); - t4 = vec_perm(c7[1], c8[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); - } - vec_xst(t5, 0, vecOffset+192); - vec_xst(t6, 0, vecOffset+208); - vec_xst(t7, 0, vecOffset+224); - vec_xst(t8, 0, vecOffset+240); - - aoffset1 += lda; - aoffset2 += lda; - aoffset3 += lda; - aoffset4 += lda; - aoffset5 += lda; - aoffset6 += lda; - aoffset7 += lda; - aoffset8 += lda; + vector_permute_store(c1[0], c1[1], c1[2], c1[3], vecOffset, flip); + vector_permute_store(c2[0], c2[1], c2[2], c2[3], vecOffset+64, flip); + vector_permute_store(c1[4], c1[5], c1[6], c1[7], vecOffset+128, flip); + vector_permute_store(c2[4], c2[5], c2[6], c2[7], vecOffset+192, flip); + for (int it = 0; it < 8; it++) + aoffsets[it] += lda; vecOffset += 256; i--; } while(i > 0); @@ -2150,129 +1824,53 @@ class tinyBLAS_Q0_PPC { } if (rows & 4) { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; - aoffset4 = aoffset3 + lda; - aoffset += 4 * lda; - + aoffsets[0] = aoffset; + for (int it = 1; it < 4; it++ ) + aoffsets[it] = aoffsets[it-1] + lda; + aoffset += 4 * lda; i = (cols >> 3); if (i > 0) { do { - C1 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset1->qs); - C2 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset2->qs); - C3 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset3->qs); - C4 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset4->qs); - - __builtin_vsx_disassemble_pair(c1, &C1); - __builtin_vsx_disassemble_pair(c2, &C2); - __builtin_vsx_disassemble_pair(c3, &C3); - __builtin_vsx_disassemble_pair(c4, &C4); - - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); + for (int it = 0; it < 4; it++) { + arr[it] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[it]->qs); + __builtin_vsx_disassemble_pair(c[it], &arr[it]); + c1[it] = c[it][0]; + c2[it] = c[it][1]; } - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); + vector_permute_store(c1[0], c1[1], c1[2], c1[3], vecOffset, flip); + vector_permute_store(c2[0], c2[1], c2[2], c2[3], vecOffset+64, flip); + for (int it = 0; it < 4; it++) { + aoffsets[it] += lda; } - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); - - aoffset1 += lda; - aoffset2 += lda; - aoffset3 += lda; - aoffset4 += lda; vecOffset += 128; i--; } while(i > 0); } } + if (rows & 3) { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; + aoffsets[0] = aoffset; + for (int it = 1; it < 3; it++ ) + aoffsets[it] = aoffsets[it-1] + lda; i = (cols >> 3); if (i > 0) { do { switch(rows) { - case 3: C3 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset3->qs); - __builtin_vsx_disassemble_pair(c3, &C3); - case 2: C2 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset2->qs); - __builtin_vsx_disassemble_pair(c2, &C2); - case 1: C1 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset1->qs); - __builtin_vsx_disassemble_pair(c1, &C1); + case 3: arr[2] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[2]->qs); + __builtin_vsx_disassemble_pair(c[2], &arr[2]); + c1[2] = c[2][0]; c2[2] = c[2][1]; + case 2: arr[1] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[1]->qs); + __builtin_vsx_disassemble_pair(c[1], &arr[1]); + c1[1] = c[1][0]; c2[1] = c[1][1]; + case 1: arr[0] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[0]->qs); + __builtin_vsx_disassemble_pair(c[0], &arr[0]); + c1[0] = c[0][0]; c2[0] = c[0][1]; break; } - t1 = vec_perm(c1[0], c2[0], swiz1); - t2 = vec_perm(c1[0], c2[0], swiz2); - t3 = vec_perm(c3[0], c4[0], swiz1); - t4 = vec_perm(c3[0], c4[0], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); - } - vec_xst(t5, 0, vecOffset); - vec_xst(t6, 0, vecOffset+16); - vec_xst(t7, 0, vecOffset+32); - vec_xst(t8, 0, vecOffset+48); - - t1 = vec_perm(c1[1], c2[1], swiz1); - t2 = vec_perm(c1[1], c2[1], swiz2); - t3 = vec_perm(c3[1], c4[1], swiz1); - t4 = vec_perm(c3[1], c4[1], swiz2); - t5 = vec_perm(t1, t3, swiz3); - t6 = vec_perm(t1, t3, swiz4); - t7 = vec_perm(t2, t4, swiz3); - t8 = vec_perm(t2, t4, swiz4); - if (flip == true) { - t5 = vec_xor(t5, xor_vector); - t6 = vec_xor(t6, xor_vector); - t7 = vec_xor(t7, xor_vector); - t8 = vec_xor(t8, xor_vector); - } - vec_xst(t5, 0, vecOffset+64); - vec_xst(t6, 0, vecOffset+80); - vec_xst(t7, 0, vecOffset+96); - vec_xst(t8, 0, vecOffset+112); - - aoffset1 += lda; - aoffset2 += lda; - aoffset3 += lda; + vector_permute_store(c1[0], c1[1], c1[2], c1[3], vecOffset, flip); + vector_permute_store(c2[0], c2[1], c2[2], c2[3], vecOffset+64, flip); + for (int it = 0; it < 3; it++) + aoffsets[it] += lda; vecOffset += 128; i--; } while(i > 0); @@ -2281,159 +1879,42 @@ class tinyBLAS_Q0_PPC { } void mnpack(int64_t m0, int64_t m, int64_t n0, int64_t n) { - int64_t mc, nc, mp, np; - int m_rem = MIN(m - m0, 8); - int n_rem = MIN(n - n0, 8); - // TO-DO: KERNEL_16x8 and KERNEL_8x16 are having some performance - // issues. After resolving them, below code will be enabled. - /*if (m_rem >= 16 && n_rem >= 8) { - mc = 16; - nc = 8; - gemm<16,8>(m0, m, n0, n); - } else if(m_rem >= 8 && n_rem >= 16) { - mc = 8; - nc = 16; - gemm<8,16>(m0, m, n0, n); - }*/ + int m_rem = MIN(m - m0, 16); + int n_rem = MIN(n - n0, 16); + + int mc = 0, nc = 0; + if (m_rem >= 8 && n_rem >= 8) { - mc = 8; - nc = 8; - gemm<8,8>(m0, m, n0, n); + mc = 8; + nc = 8; + gemm<8, 8>(m0, m, n0, n); } else if (m_rem >= 4 && n_rem >= 8) { mc = 4; nc = 8; - gemm<4,8>(m0, m, n0, n); + gemm<4, 8>(m0, m, n0, n); } else if (m_rem >= 8 && n_rem >= 4) { mc = 8; nc = 4; - gemm<8,4>(m0, m, n0, n); + gemm<8, 4>(m0, m, n0, n); } else if (m_rem >= 4 && n_rem >= 4) { mc = 4; nc = 4; - gemm_small<4, 4>(m0, m, n0, n); - } else if ((m_rem < 4) && (n_rem > 4)) { - nc = 4; - switch(m_rem) { - case 1: - mc = 1; - gemm_small<1, 4>(m0, m, n0, n); - break; - case 2: - mc = 2; - gemm_small<2, 4>(m0, m, n0, n); - break; - case 3: - mc = 3; - gemm_small<3, 4>(m0, m, n0, n); - break; - default: - return; - } - } else if ((m_rem > 4) && (n_rem < 4)) { - mc = 4; - switch(n_rem) { - case 1: - nc = 1; - gemm_small<4, 1>(m0, m, n0, n); - break; - case 2: - nc = 2; - gemm_small<4, 2>(m0, m, n0, n); - break; - case 3: - nc = 3; - gemm_small<4, 3>(m0, m, n0, n); - break; - default: - return; - } + gemm_small(m0, m, n0, n, mc, nc); } else { - switch((m_rem << 4) | n_rem) { - case 0x43: - mc = 4; - nc = 3; - gemm_small<4, 3>(m0, m, n0, n); - break; - case 0x42: - mc = 4; - nc = 2; - gemm_small<4, 2>(m0, m, n0, n); - break; - case 0x41: - mc = 4; - nc = 1; - gemm_small<4, 1>(m0, m, n0, n); - break; - case 0x34: - mc = 3; - nc = 4; - gemm_small<3, 4>(m0, m, n0, n); - break; - case 0x33: - mc = 3; - nc = 3; - gemm_small<3, 3>(m0, m, n0, n); - break; - case 0x32: - mc = 3; - nc = 2; - gemm_small<3, 2>(m0, m, n0, n); - break; - case 0x31: - mc = 3; - nc = 1; - gemm_small<3, 1>(m0, m, n0, n); - break; - case 0x24: - mc = 2; - nc = 4; - gemm_small<2, 4>(m0, m, n0, n); - break; - case 0x23: - mc = 2; - nc = 3; - gemm_small<2, 3>(m0, m, n0, n); - break; - case 0x22: - mc = 2; - nc = 2; - gemm_small<2, 2>(m0, m, n0, n); - break; - case 0x21: - mc = 2; - nc = 1; - gemm_small<2, 1>(m0, m, n0, n); - break; - case 0x14: - mc = 1; - nc = 4; - gemm_small<1, 4>(m0, m, n0, n); - break; - case 0x13: - mc = 1; - nc = 3; - gemm_small<1, 3>(m0, m, n0, n); - break; - case 0x12: - mc = 1; - nc = 2; - gemm_small<1, 2>(m0, m, n0, n); - break; - case 0x11: - mc = 1; - nc = 1; - gemm_small<1, 1>(m0, m, n0, n); - break; - default: - return; - } + mc = (m_rem >= 4) ? 4 : m_rem; + nc = (n_rem >= 4) ? 4 : n_rem; + if (mc == 0 || nc == 0) + return; + gemm_small(m0, m, n0, n, mc, nc); } - mp = m0 + (m - m0) / mc * mc; - np = n0 + (n - n0) / nc * nc; + + int64_t mp = m0 + ((m - m0) / mc) * mc; + int64_t np = n0 + ((n - n0) / nc) * nc; mnpack(mp, m, n0, np); mnpack(m0, m, np, n); } + void KERNEL_4x8(int64_t ii, int64_t jj) { vec_t vec_A[8], vec_B[16] = {0}; acc_t acc_0, acc_1; @@ -2445,9 +1926,9 @@ class tinyBLAS_Q0_PPC { __builtin_mma_xxsetaccz(&acc_0); __builtin_mma_xxsetaccz(&acc_1); if (std::is_same_v) { - packNormalInt4((A+(ii*lda)+l), lda, 4, 4, (int8_t*)vec_A, comparray); + packNormalInt4<4>((A+(ii*lda)+l), lda, 4, 4, (int8_t*)vec_A, comparray); } else { - packNormal((const TB*)(A+(ii*lda)+l), lda, 4, 8, (int8_t*)vec_A, false); + packNormal((const block_q8_0*)(A+(ii*lda)+l), lda, 4, 8, (int8_t*)vec_A, false); } packNormal((B+(jj*ldb)+l), ldb, 8, 8, (uint8_t*)vec_B, true); for(int x = 0; x < 8; x++) { @@ -2475,8 +1956,8 @@ class tinyBLAS_Q0_PPC { compute<4>(&acc_0, 0, 0, comparray, vs, fin_res); compute<4>(&acc_1, 0, 4, comparray, vs, fin_res); } - save_res<4, 4>(ii, jj, 0, fin_res); - save_res<4, 4>(ii, jj+4, 4, fin_res); + save_res(ii, jj, 0, fin_res); + save_res(ii, jj+4, 4, fin_res); } void KERNEL_8x4(int64_t ii, int64_t jj) { @@ -2490,9 +1971,9 @@ class tinyBLAS_Q0_PPC { __builtin_mma_xxsetaccz(&acc_0); __builtin_mma_xxsetaccz(&acc_1); if (std::is_same_v) { - packNormalInt4((A+(ii*lda)+l), lda, 8, 4, (int8_t*)vec_A, comparray); + packNormalInt4<8>((A+(ii*lda)+l), lda, 8, 4, (int8_t*)vec_A, comparray); } else { - packNormal((const TB*)(A+(ii*lda)+l), lda, 8, 8, (int8_t*)vec_A, false); + packNormal((const block_q8_0*)(A+(ii*lda)+l), lda, 8, 8, (int8_t*)vec_A, false); } packNormal((B+(jj*ldb)+l), ldb, 4, 8, (uint8_t*)vec_B, true); for(int x = 0; x < 8; x++) { @@ -2519,8 +2000,8 @@ class tinyBLAS_Q0_PPC { compute<8>(&acc_0, 0, 0, comparray, vs, fin_res); compute<8>(&acc_1, 4, 4, comparray, vs, fin_res); } - save_res<4, 4>(ii, jj, 0, fin_res); - save_res<4, 4>(ii+4, jj, 4, fin_res); + save_res(ii, jj, 0, fin_res); + save_res(ii+4, jj, 4, fin_res); } void KERNEL_8x8(int64_t ii, int64_t jj) { @@ -2536,9 +2017,9 @@ class tinyBLAS_Q0_PPC { __builtin_mma_xxsetaccz(&acc_2); __builtin_mma_xxsetaccz(&acc_3); if (std::is_same_v) { - packNormalInt4((A+(ii*lda)+l), lda, 8, 4, (int8_t*)vec_A, comparray); + packNormalInt4<8>((A+(ii*lda)+l), lda, 8, 4, (int8_t*)vec_A, comparray); } else { - packNormal((const TB*)(A+(ii*lda)+l), lda, 8, 8, (int8_t*)vec_A, false); + packNormal((const block_q8_0*)(A+(ii*lda)+l), lda, 8, 8, (int8_t*)vec_A, false); } packNormal((B+(jj*ldb)+l), ldb, 8, 8, (uint8_t*)vec_B, true); for(int x = 0; x < 8; x++) { @@ -2570,14 +2051,13 @@ class tinyBLAS_Q0_PPC { compute<8>(&acc_2, 0, 8, comparray, vs, fin_res); compute<8>(&acc_3, 4, 12, comparray, vs, fin_res); } - save_res<4, 4>(ii, jj, 0, fin_res); - save_res<4, 4>(ii+4, jj, 4, fin_res); - save_res<4, 4>(ii, jj+4, 8, fin_res); - save_res<4, 4>(ii+4, jj+4, 12, fin_res); + save_res(ii, jj, 0, fin_res); + save_res(ii+4, jj, 4, fin_res); + save_res(ii, jj+4, 8, fin_res); + save_res(ii+4, jj+4, 12, fin_res); } - template - void gemm_small(int64_t m0, int64_t m, int64_t n0, int64_t n) { + void gemm_small(int64_t m0, int64_t m, int64_t n0, int64_t n, int RM, int RN) { int64_t ytiles = (m - m0) / RM; int64_t xtiles = (n - n0) / RN; int64_t tiles = xtiles * ytiles; @@ -2606,9 +2086,9 @@ class tinyBLAS_Q0_PPC { __builtin_prefetch((B+(jj*ldb)+(l+1))->qs, 0, 1); // prefetch one loop ahead __builtin_mma_xxsetaccz(&acc_0); if (isAblock_q4) { - packNormalInt4((A+(ii*lda)+l), lda, RM, 4, (int8_t*)vec_A, comparray); + packNormalInt4<4>((A+(ii*lda)+l), lda, RM, 4, (int8_t*)vec_A, comparray); } else { - packNormal((const TB*)(A+(ii*lda)+l), lda, RM, 8, (int8_t*)vec_A, false); + packNormal((const block_q8_0*)(A+(ii*lda)+l), lda, RM, 8, (int8_t*)vec_A, false); } packNormal((B+(jj*ldb)+l), ldb, RN, 8, (uint8_t*)vec_B, true); for(int x = 0; x < 8; x+=4) { @@ -2641,7 +2121,7 @@ class tinyBLAS_Q0_PPC { fin_res[i] = vec_madd(res[i], vs[i], fin_res[i]); } } - save_res(ii, jj, 0, fin_res); + save_res(ii, jj, 0, fin_res, RM, RN); } } @@ -2654,7 +2134,7 @@ class tinyBLAS_Q0_PPC { } else if constexpr(RM == 8 && RN == 8) { KERNEL_8x8(ii,jj); } else { - static_assert(false, "RN/RM values not supported"); + assert(false && "RN/RM values not supported"); } } @@ -2676,10 +2156,8 @@ class tinyBLAS_Q0_PPC { } const TA *const A; - const TB *const B; - TC *C; - TA *At; - TB *Bt; + const block_q8_0 *const B; + float *C; const int64_t k; const int64_t lda; const int64_t ldb; @@ -2688,266 +2166,183 @@ class tinyBLAS_Q0_PPC { const int nth; }; -template class tinyBLAS_PPC { public: tinyBLAS_PPC(int64_t k, - const TA *A, int64_t lda, - const TB *B, int64_t ldb, - TC *C, int64_t ldc, + const float * A, int64_t lda, + const float * B, int64_t ldb, + float * C, int64_t ldc, int ith, int nth) : A(A), B(B), C(C), k(k), lda(lda), ldb(ldb), ldc(ldc), ith(ith), nth(nth) { } void matmul(int64_t m, int64_t n) { - mnpack(0, m, 0, n); + int64_t mc = 256; int64_t nc = 256; int64_t kc = 256; + if (m % mc == 0 && n % nc == 0 && k % kc == 0) { + matmul_tiled(m, n, mc, nc, kc); + } else { + mnpack(0, m, 0, n); + } } private: - void (tinyBLAS_PPC::*kernel)(int64_t, int64_t); + inline void save_acc(acc_t * ACC, int64_t ii, int64_t jj) { + vec_t vec_C[4]; + __builtin_mma_disassemble_acc(vec_C, ACC); + for (int I = 0; I < 4; I++) { + for (int J = 0; J < 4; J++) { + *((float *)(C+ii+((jj+J)*ldc)+I)) = *((float *)&vec_C[I]+J); + } + } + } + + inline void add_save_acc(acc_t * ACC, int64_t ii, int64_t jj) { + vec_t vec_C[4]; + __builtin_mma_disassemble_acc(vec_C, ACC); + for (int I = 0; I < 4; I++) { + for (int J = 0; J < 4; J++) { + float * c_ptr = (float *)(C+ii+((jj+J)*ldc)+I); + *c_ptr += *((float *)&vec_C[I]+J); + } + } + } + + inline void vector_permute_store_4(vector float * src, float * vecOffset) { + vector float t1, t2, t3, t4, t5, t6, t7, t8; + t1 = vec_mergeh(src[0], src[1]); + t2 = vec_mergeh(src[2], src[3]); + t3 = vec_mergel(src[0], src[1]); + t4 = vec_mergel(src[2], src[3]); + + t5 = vec_xxpermdi(t1, t2, 0); + t6 = vec_xxpermdi(t1, t2, 3); + t7 = vec_xxpermdi(t3, t4, 0); + t8 = vec_xxpermdi(t3, t4, 3); - template - void packTranspose(const TA* a, int64_t lda, int rows, int cols, TA* vec) { + vec_xst(t5, 0, vecOffset); + vec_xst(t6, 0, vecOffset + 4); + vec_xst(t7, 0, vecOffset + 8); + vec_xst(t8, 0, vecOffset + 12); + } + + inline void vector_permute_store_8(vector float * src, float * vecOffset) { + vector float t1, t2, t3, t4, t5, t6, t7, t8; + t1 = vec_mergeh(src[0], src[1]); + t2 = vec_mergeh(src[2], src[3]); + t3 = vec_mergeh(src[4], src[5]); + t4 = vec_mergeh(src[6], src[7]); + + t5 = vec_xxpermdi(t1, t2, 0); + t6 = vec_xxpermdi(t3, t4, 0); + t7 = vec_xxpermdi(t1, t2, 3); + t8 = vec_xxpermdi(t3, t4, 3); + + vec_xst(t5, 0, vecOffset); + vec_xst(t6, 0, vecOffset + 4); + vec_xst(t7, 0, vecOffset + 8); + vec_xst(t8, 0, vecOffset + 12); + + t1 = vec_mergel(src[0], src[1]); + t2 = vec_mergel(src[2], src[3]); + t3 = vec_mergel(src[4], src[5]); + t4 = vec_mergel(src[6], src[7]); + + t5 = vec_xxpermdi(t1, t2, 0); + t6 = vec_xxpermdi(t3, t4, 0); + t7 = vec_xxpermdi(t1, t2, 3); + t8 = vec_xxpermdi(t3, t4, 3); + + vec_xst(t5, 0, vecOffset + 16); + vec_xst(t6, 0, vecOffset + 20); + vec_xst(t7, 0, vecOffset + 24); + vec_xst(t8, 0, vecOffset + 28); + } + + void packTranspose(const float * a, int64_t lda, int rows, int cols, float * vec) { int64_t i, j; - TA *aoffset = NULL, *boffset = NULL; - TA *aoffset1 = NULL, *aoffset2 = NULL, *aoffset3 = NULL, *aoffset4 = NULL; - TA *aoffset5 = NULL, *aoffset6 = NULL, *aoffset7 = NULL, *aoffset8 = NULL; - __vector_pair C1, C2, C3, C4, C5, C6, C7, C8; - VA c1[2] = {0}, c2[2] = {0}, c3[2] = {0}, c4[2] = {0}; - VA c5[2] = {0}, c6[2] = {0}, c7[2] = {0}, c8[2] = {0}; - VA t1, t2, t3, t4, t5, t6, t7, t8; - aoffset = const_cast(a); + float * aoffsets[8]; + float * aoffset = NULL, * boffset = NULL; + __vector_pair arr[8]; + vector float c[8][2] = {0}; + vector float c1[8] = {0}; + vector float c2[8] = {0}; + aoffset = const_cast(a); boffset = vec; j = (rows >> 3); if (j > 0) { - do { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; - aoffset4 = aoffset3 + lda; - aoffset5 = aoffset4 + lda; - aoffset6 = aoffset5 + lda; - aoffset7 = aoffset6 + lda; - aoffset8 = aoffset7 + lda; + aoffsets[0] = aoffset; + for (int it = 1; it < 8; it++) + aoffsets[it] = aoffsets[it-1] + lda; aoffset += 8 * lda; i = (cols >> 3); if (i > 0) { do { - C1 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset1); - C2 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset2); - C3 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset3); - C4 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset4); - C5 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset5); - C6 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset6); - C7 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset7); - C8 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset8); - __builtin_vsx_disassemble_pair(c1, &C1); - __builtin_vsx_disassemble_pair(c2, &C2); - __builtin_vsx_disassemble_pair(c3, &C3); - __builtin_vsx_disassemble_pair(c4, &C4); - __builtin_vsx_disassemble_pair(c5, &C5); - __builtin_vsx_disassemble_pair(c6, &C6); - __builtin_vsx_disassemble_pair(c7, &C7); - __builtin_vsx_disassemble_pair(c8, &C8); - - t1 = vec_mergeh(c1[0], c2[0]); - t2 = vec_mergeh(c3[0], c4[0]); - t3 = vec_mergeh(c5[0], c6[0]); - t4 = vec_mergeh(c7[0], c8[0]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset); - vec_xst(t6, 0, boffset+4); - vec_xst(t7, 0, boffset+8); - vec_xst(t8, 0, boffset+12); - - t1 = vec_mergel(c1[0], c2[0]); - t2 = vec_mergel(c3[0], c4[0]); - t3 = vec_mergel(c5[0], c6[0]); - t4 = vec_mergel(c7[0], c8[0]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset+16); - vec_xst(t6, 0, boffset+20); - vec_xst(t7, 0, boffset+24); - vec_xst(t8, 0, boffset+28); - - t1 = vec_mergeh(c1[1], c2[1]); - t2 = vec_mergeh(c3[1], c4[1]); - t3 = vec_mergeh(c5[1], c6[1]); - t4 = vec_mergeh(c7[1], c8[1]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset+32); - vec_xst(t6, 0, boffset+36); - vec_xst(t7, 0, boffset+40); - vec_xst(t8, 0, boffset+44); - - t1 = vec_mergel(c1[1], c2[1]); - t2 = vec_mergel(c3[1], c4[1]); - t3 = vec_mergel(c5[1], c6[1]); - t4 = vec_mergel(c7[1], c8[1]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset+48); - vec_xst(t6, 0, boffset+52); - vec_xst(t7, 0, boffset+56); - vec_xst(t8, 0, boffset+60); - - aoffset1 += 8*lda; - aoffset2 += 8*lda; - aoffset3 += 8*lda; - aoffset4 += 8*lda; + for (int it = 0; it < 8; it++) { + arr[it] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[it]); + __builtin_vsx_disassemble_pair(c[it], &arr[it]); + c1[it] = c[it][0]; + c2[it] = c[it][1]; + } + + vector_permute_store_8(c1, boffset); + vector_permute_store_8(c2, boffset + 32); boffset += 64; i--; + if (i > 0) { + for (int it = 0; it < 8; it++) { + aoffsets[it] = aoffsets[it] + 8; + } + } } while(i > 0); } if (cols & 4) { - c1[0] = vec_xl(0, aoffset1); - c2[0] = vec_xl(0, aoffset2); - c3[0] = vec_xl(0, aoffset3); - c4[0] = vec_xl(0, aoffset4); - c5[0] = vec_xl(0, aoffset5); - c6[0] = vec_xl(0, aoffset6); - c7[0] = vec_xl(0, aoffset7); - c8[0] = vec_xl(0, aoffset8); - - t1 = vec_mergeh(c1[0], c2[0]); - t2 = vec_mergeh(c3[0], c4[0]); - t3 = vec_mergeh(c5[0], c6[0]); - t4 = vec_mergeh(c7[0], c8[0]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset); - vec_xst(t6, 0, boffset+4); - vec_xst(t7, 0, boffset+8); - vec_xst(t8, 0, boffset+12); - - t1 = vec_mergel(c1[0], c2[0]); - t2 = vec_mergel(c3[0], c4[0]); - t3 = vec_mergel(c5[0], c6[0]); - t4 = vec_mergel(c7[0], c8[0]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t3, t4, 0); - t7 = vec_xxpermdi(t1, t2, 3); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset+16); - vec_xst(t6, 0, boffset+20); - vec_xst(t7, 0, boffset+24); - vec_xst(t8, 0, boffset+28); + for (int it = 0; it < 8 ; it++) + c1[it] = vec_xl(0, aoffsets[it]); + vector_permute_store_8(c1, boffset); } j--; } while(j > 0); } if (rows & 4) { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; - aoffset4 = aoffset3 + lda; + aoffsets[0] = aoffset; + for (int it = 1; it < 4; it++) + aoffsets[it] = aoffsets[it-1] + lda; aoffset += 4 * lda; i = (cols >> 3); if (i > 0) { do { - C1 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset1); - C2 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset2); - C3 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset3); - C4 = __builtin_vsx_lxvp(0, (__vector_pair*)aoffset4); - __builtin_vsx_disassemble_pair(c1, &C1); - __builtin_vsx_disassemble_pair(c2, &C2); - __builtin_vsx_disassemble_pair(c3, &C3); - __builtin_vsx_disassemble_pair(c4, &C4); - - t1 = vec_mergeh(c1[0], c2[0]); - t2 = vec_mergeh(c3[0], c4[0]); - t3 = vec_mergel(c1[0], c2[0]); - t4 = vec_mergel(c3[0], c4[0]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t1, t2, 3); - t7 = vec_xxpermdi(t3, t4, 0); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset); - vec_xst(t6, 0, boffset+4); - vec_xst(t7, 0, boffset+8); - vec_xst(t8, 0, boffset+12); - - t1 = vec_mergeh(c1[1], c2[1]); - t2 = vec_mergeh(c3[1], c4[1]); - t3 = vec_mergel(c1[1], c2[1]); - t4 = vec_mergel(c3[1], c4[1]); - t5 = vec_xxpermdi(t1, t2, 0); - t6 = vec_xxpermdi(t1, t2, 3); - t7 = vec_xxpermdi(t3, t4, 0); - t8 = vec_xxpermdi(t3, t4, 3); - vec_xst(t5, 0, boffset+16); - vec_xst(t6, 0, boffset+20); - vec_xst(t7, 0, boffset+24); - vec_xst(t8, 0, boffset+28); - - aoffset1 += 8*lda; - aoffset2 += 8*lda; - aoffset3 += 8*lda; - aoffset4 += 8*lda; + for (int it = 0; it < 4; it++) { + arr[it] = __builtin_vsx_lxvp(0, (__vector_pair*)aoffsets[it]); + __builtin_vsx_disassemble_pair(c[it], &arr[it]); + c1[it] = c[it][0]; + c2[it] = c[it][1]; + } + vector_permute_store_4(c1, boffset); + vector_permute_store_4(c2, boffset + 16); + for (int it = 0; it < 4; it++) + aoffsets[it] += 8 * lda; boffset += 32; i--; } while(i > 0); } if (cols & 4) { - c1[0] = vec_xl(0, aoffset1); - c2[0] = vec_xl(0, aoffset2); - c3[0] = vec_xl(0, aoffset3); - c4[0] = vec_xl(0, aoffset4); - - t1 = vec_mergeh(c1[0], c2[0]); - t2 = vec_mergeh(c3[0], c4[0]); - t3 = vec_xxpermdi(t1, t2, 0); - t4 = vec_xxpermdi(t1, t2, 3); - vec_xst(t3, 0, boffset); - vec_xst(t4, 0, boffset+4); - - t1 = vec_mergel(c1[0], c2[0]); - t2 = vec_mergel(c3[0], c4[0]); - t3 = vec_xxpermdi(t1, t2, 0); - t4 = vec_xxpermdi(t1, t2, 3); - vec_xst(t3, 0, boffset+8); - vec_xst(t4, 0, boffset+12); + for (int it = 0; it < 4; it++) + c1[it] = vec_xl(0, aoffsets[it]); + vector_permute_store_4(c1, boffset); } } if (rows & 3) { - aoffset1 = aoffset; - aoffset2 = aoffset1 + lda; - aoffset3 = aoffset2 + lda; + aoffsets[0] = aoffset; + for (int it = 1; it < 3; it++) + aoffsets[it] = aoffsets[it-1] + lda; if (cols & 4) { - c1[0] = vec_xl(0, aoffset1); - c2[0] = vec_xl(0, aoffset2); - c3[0] = vec_xl(0, aoffset3); - - t1 = vec_mergeh(c1[0], c2[0]); - t2 = vec_mergeh(c3[0], c4[0]); - t3 = vec_xxpermdi(t1, t2, 0); - t4 = vec_xxpermdi(t1, t2, 3); - vec_xst(t3, 0, boffset); - vec_xst(t4, 0, boffset+4); - - t1 = vec_mergel(c1[0], c2[0]); - t2 = vec_mergel(c3[0], c4[0]); - t3 = vec_xxpermdi(t1, t2, 0); - t4 = vec_xxpermdi(t1, t2, 3); - vec_xst(t3, 0, boffset+8); - vec_xst(t4, 0, boffset+12); + for (int it = 0; it < 3; it++) + c1[it] = vec_xl(0, aoffsets[it]); + vector_permute_store_4(c1, boffset); } } } @@ -2956,15 +2351,15 @@ class tinyBLAS_PPC { vec_t vec_A[4], vec_B[4], vec_C[4]; acc_t acc_0; __builtin_mma_xxsetaccz(&acc_0); - for (int l = 0; l < k; l+=4) { - packTranspose(A+(ii*lda)+l, lda, 4, 4, (TA*)vec_A); - packTranspose(B+(jj*ldb)+l, ldb, 4, 4, (TA*)vec_B); + for (int l = 0; l < k; l += 4) { + packTranspose(A + (ii * lda) + l, lda, 4, 4, (float *)vec_A); + packTranspose(B + (jj * ldb) + l, ldb, 4, 4, (float *)vec_B); __builtin_mma_xvf32gerpp(&acc_0, vec_A[0], vec_B[0]); __builtin_mma_xvf32gerpp(&acc_0, vec_A[1], vec_B[1]); __builtin_mma_xvf32gerpp(&acc_0, vec_A[2], vec_B[2]); __builtin_mma_xvf32gerpp(&acc_0, vec_A[3], vec_B[3]); } - SAVE_ACC(&acc_0, ii, jj); + save_acc(&acc_0, ii, jj); } void KERNEL_4x8(int64_t ii, int64_t jj) { @@ -2972,9 +2367,9 @@ class tinyBLAS_PPC { acc_t acc_0, acc_1; __builtin_mma_xxsetaccz(&acc_0); __builtin_mma_xxsetaccz(&acc_1); - for (int64_t l = 0; l < k; l+=4) { - packTranspose(A+(ii*lda)+l, lda, 4, 4, (TA*)vec_A); - packTranspose(B+(jj*ldb)+l, ldb, 8, 4, (TA*)vec_B); + for (int64_t l = 0; l < k; l += 4) { + packTranspose(A + (ii * lda) + l, lda, 4, 4, (float *)vec_A); + packTranspose(B + (jj * ldb) + l, ldb, 8, 4, (float *)vec_B); __builtin_mma_xvf32gerpp(&acc_0, vec_A[0], (vec_t)vec_B[0]); __builtin_mma_xvf32gerpp(&acc_1, vec_A[0], (vec_t)vec_B[1]); __builtin_mma_xvf32gerpp(&acc_0, vec_A[1], (vec_t)vec_B[2]); @@ -2984,8 +2379,8 @@ class tinyBLAS_PPC { __builtin_mma_xvf32gerpp(&acc_0, vec_A[3], (vec_t)vec_B[6]); __builtin_mma_xvf32gerpp(&acc_1, vec_A[3], (vec_t)vec_B[7]); } - SAVE_ACC(&acc_0, ii, jj); - SAVE_ACC(&acc_1, ii, jj+4); + save_acc(&acc_0, ii, jj); + save_acc(&acc_1, ii, jj + 4); } void KERNEL_8x4(int64_t ii, int64_t jj) { @@ -2993,9 +2388,9 @@ class tinyBLAS_PPC { acc_t acc_0, acc_1; __builtin_mma_xxsetaccz(&acc_0); __builtin_mma_xxsetaccz(&acc_1); - for (int64_t l = 0; l < k; l+=4) { - packTranspose(A+(ii*lda)+l, lda, 8, 4, (TA*)vec_A); - packTranspose(B+(jj*ldb)+l, ldb, 4, 4, (TA*)vec_B); + for (int64_t l = 0; l < k; l += 4) { + packTranspose(A + (ii * lda) + l, lda, 8, 4, (float *)vec_A); + packTranspose(B + (jj * ldb) + l, ldb, 4, 4, (float *)vec_B); __builtin_mma_xvf32gerpp(&acc_0, (vec_t)vec_A[0], vec_B[0]); __builtin_mma_xvf32gerpp(&acc_1, (vec_t)vec_A[1], vec_B[0]); __builtin_mma_xvf32gerpp(&acc_0, (vec_t)vec_A[2], vec_B[1]); @@ -3005,8 +2400,8 @@ class tinyBLAS_PPC { __builtin_mma_xvf32gerpp(&acc_0, (vec_t)vec_A[6], vec_B[3]); __builtin_mma_xvf32gerpp(&acc_1, (vec_t)vec_A[7], vec_B[3]); } - SAVE_ACC(&acc_0, ii, jj); - SAVE_ACC(&acc_1, ii+4, jj); + save_acc(&acc_0, ii, jj); + save_acc(&acc_1, ii + 4, jj); } void KERNEL_8x8(int64_t ii, int64_t jj) { @@ -3017,173 +2412,132 @@ class tinyBLAS_PPC { __builtin_mma_xxsetaccz(&acc_2); __builtin_mma_xxsetaccz(&acc_3); for (int l = 0; l < k; l+=8) { - packTranspose(A+(ii*lda)+l, lda, 8, 8, (TA*)vec_A); - packTranspose(B+(jj*ldb)+l, ldb, 8, 8, (TA*)vec_B); + packTranspose(A + (ii * lda) + l, lda, 8, 8, (float *)vec_A); + packTranspose(B + (jj * ldb) + l, ldb, 8, 8, (float *)vec_B); for(int x = 0; x < 16; x+=2) { __builtin_mma_xvf32gerpp(&acc_0, (vec_t)vec_A[x], vec_B[x]); - __builtin_mma_xvf32gerpp(&acc_1, (vec_t)vec_A[x], vec_B[x+1]); - __builtin_mma_xvf32gerpp(&acc_2, (vec_t)vec_A[x+1], vec_B[x]); - __builtin_mma_xvf32gerpp(&acc_3, (vec_t)vec_A[x+1], vec_B[x+1]); + __builtin_mma_xvf32gerpp(&acc_1, (vec_t)vec_A[x], vec_B[x + 1]); + __builtin_mma_xvf32gerpp(&acc_2, (vec_t)vec_A[x + 1], vec_B[x]); + __builtin_mma_xvf32gerpp(&acc_3, (vec_t)vec_A[x + 1], vec_B[x + 1]); + } + } + save_acc(&acc_0, ii, jj); + save_acc(&acc_1, ii, jj + 4); + save_acc(&acc_2, ii + 4, jj); + save_acc(&acc_3, ii + 4, jj + 4); + } + + inline void MMA_16x8(vec_t * vec_A0, vec_t * vec_A1, vec_t * vec_B, acc_t * acc) { + for (int x = 0; x < 16; x += 2) { + __builtin_mma_xvf32gerpp(&acc[0], vec_A0[x + 0], vec_B[x]); + __builtin_mma_xvf32gerpp(&acc[1], vec_A0[x + 0], vec_B[x + 1]); + __builtin_mma_xvf32gerpp(&acc[2], vec_A0[x + 1], vec_B[x]); + __builtin_mma_xvf32gerpp(&acc[3], vec_A0[x + 1], vec_B[x + 1]); + __builtin_mma_xvf32gerpp(&acc[4], vec_A1[x + 0], vec_B[x]); + __builtin_mma_xvf32gerpp(&acc[5], vec_A1[x + 0], vec_B[x + 1]); + __builtin_mma_xvf32gerpp(&acc[6], vec_A1[x + 1], vec_B[x]); + __builtin_mma_xvf32gerpp(&acc[7], vec_A1[x + 1], vec_B[x + 1]); + } + } + + void KERNEL(int64_t ii, int64_t jj, int64_t mc, int64_t nc, int64_t kc, vec_t * vec_A, vec_t * vec_B, int64_t kk) { + for (int64_t i = 0; i < mc; i += 16) { + int A_base_addr = (mc / 8) * (i / 8) * 16; + for (int64_t j = 0; j < nc; j += 8) { + int B_base_addr = (nc / 8) * (j / 8) * 16; + acc_t acc[8]; + vec_t A0_block[16]; vec_t A1_block[16]; + for (int x = 0; x < 8; x++) + __builtin_mma_xxsetaccz(&acc[x]); + for (int64_t l = 0; l < kc; l += 8) { + int A0_block_idx = A_base_addr + (l / 8) * 16; + int A1_block_idx = A0_block_idx + (mc / 8) * 16; + int B_block_idx = B_base_addr + (l / 8) * 16; + vec_t* A0_block = &vec_A[A0_block_idx]; + vec_t* A1_block = &vec_A[A1_block_idx]; + vec_t* B_block = &vec_B[B_block_idx]; + MMA_16x8(A0_block, A1_block, B_block, acc); + } + if (kk == 0) { + save_acc(&acc[0], ii + i, jj + j); + save_acc(&acc[1], ii + i, jj + j + 4); + save_acc(&acc[2], ii + i + 4, jj + j); + save_acc(&acc[3], ii + i + 4, jj + j + 4); + save_acc(&acc[4], ii + i + 8, jj + j); + save_acc(&acc[5], ii + i + 8, jj + j + 4); + save_acc(&acc[6], ii + i + 12, jj + j); + save_acc(&acc[7], ii + i + 12, jj + j + 4); + } else { + add_save_acc(&acc[0], ii + i, jj + j); + add_save_acc(&acc[1], ii + i, jj + j + 4); + add_save_acc(&acc[2], ii + i + 4, jj + j); + add_save_acc(&acc[3], ii + i + 4, jj + j + 4); + add_save_acc(&acc[4], ii + i + 8, jj + j); + add_save_acc(&acc[5], ii + i + 8, jj + j + 4); + add_save_acc(&acc[6], ii + i + 12, jj + j); + add_save_acc(&acc[7], ii + i + 12, jj + j + 4); + } + } + } + } + + void matmul_tiled(int64_t m , int64_t n, int64_t mc, int64_t nc, int64_t kc) { + int64_t ytiles = m / mc; + int64_t xtiles = n / nc; + int64_t tiles = xtiles * ytiles; + int64_t duty = (tiles + nth - 1) / nth; + int64_t start = duty * ith; + int64_t end = start + duty; + if (end > tiles) { + end = tiles; + } + for (int64_t job = start; job < end; ++job) { + int64_t ii = (job / xtiles) * mc; + int64_t jj = (job % xtiles) * nc; + for (int64_t kk = 0; kk < k; kk += kc) { + vec_t A_pack[kc * mc / 4]; + vec_t B_pack[kc * nc / 4]; + packTranspose(A + (ii * lda) + kk, lda, kc, mc, (float *)A_pack); + packTranspose(B + (jj * ldb) + kk, ldb, kc, nc, (float *)B_pack); + KERNEL(ii, jj, mc, nc, kc, A_pack, B_pack, kk); } } - SAVE_ACC(&acc_0, ii, jj); - SAVE_ACC(&acc_1, ii, jj+4); - SAVE_ACC(&acc_2, ii+4, jj); - SAVE_ACC(&acc_3, ii+4, jj+4); } void mnpack(int64_t m0, int64_t m, int64_t n0, int64_t n) { - int64_t mc, nc, mp, np; - int m_rem = MIN(m - m0, 16); - int n_rem = MIN(n - n0, 16); - if (m_rem >= 16 && n_rem >= 8) { - mc = 8; - nc = 8; - gemm<8,8>(m0, m, n0, n); - } else if(m_rem >= 8 && n_rem >= 16) { - mc = 8; - nc = 8; - gemm<8,8>(m0, m, n0, n); - } else if (m_rem >= 8 && n_rem >= 8) { + int m_rem = MIN(m - m0, 8); + int n_rem = MIN(n - n0, 8); + int mc = 0, nc = 0; + if (m_rem >= 8 && n_rem >= 8) { mc = 8; nc = 8; - gemm<8,8>(m0, m, n0, n); + gemm<8, 8>(m0, m, n0, n); } else if (m_rem >= 4 && n_rem >= 8) { mc = 4; nc = 8; - gemm<4,8>(m0, m, n0, n); + gemm<4, 8>(m0, m, n0, n); } else if (m_rem >= 8 && n_rem >= 4) { mc = 8; nc = 4; - gemm<8,4>(m0, m, n0, n); + gemm<8, 4>(m0, m, n0, n); } else if (m_rem >= 4 && n_rem >= 4) { mc = 4; nc = 4; - gemm<4,4>(m0, m, n0, n); - } else if ((m_rem < 4) && (n_rem > 4)) { - nc = 4; - switch(m_rem) { - case 1: - mc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 2: - mc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 3: - mc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - default: - return; - } - } else if ((m_rem > 4) && (n_rem < 4)) { - mc = 4; - switch(n_rem) { - case 1: - nc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 2: - nc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 3: - nc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - default: - return; - } + gemm<4, 4>(m0, m, n0, n); } else { - switch((m_rem << 4) | n_rem) { - case 0x43: - mc = 4; - nc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x42: - mc = 4; - nc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x41: - mc = 4; - nc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x34: - mc = 3; - nc = 4; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x33: - mc = 3; - nc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x32: - mc = 3; - nc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x31: - mc = 3; - nc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x24: - mc = 2; - nc = 4; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x23: - mc = 2; - nc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x22: - mc = 2; - nc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x21: - mc = 2; - nc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x14: - mc = 1; - nc = 4; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x13: - mc = 1; - nc = 3; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x12: - mc = 1; - nc = 2; - gemm_small(m0, m, n0, n, mc, nc); - break; - case 0x11: - mc = 1; - nc = 1; - gemm_small(m0, m, n0, n, mc, nc); - break; - default: - return; - } + mc = (m_rem >= 4) ? 4 : m_rem; + nc = (n_rem >= 4) ? 4 : n_rem; + if (mc == 0 || nc == 0) + return; + gemm_small(m0, m, n0, n, mc, nc); } - mp = m0 + (m - m0) / mc * mc; - np = n0 + (n - n0) / nc * nc; + int64_t mp = m0 + ((m - m0) / mc) * mc; + int64_t np = n0 + ((n - n0) / nc) * nc; mnpack(mp, m, n0, np); mnpack(m0, m, np, n); } - void gemm_small(int64_t m0, int64_t m, int64_t n0, int64_t n, int RM, int RN) { + void gemm_small(int64_t m0, int64_t m, int64_t n0, int64_t n, int RM, int RN) { int64_t ytiles = (m - m0) / RM; int64_t xtiles = (n - n0) / RN; int64_t tiles = xtiles * ytiles; @@ -3198,30 +2552,30 @@ class tinyBLAS_PPC { vec_t vec_C[4]; acc_t acc_0; __builtin_mma_xxsetaccz(&acc_0); - vec_t vec_A[4] {0}, vec_B[4] = {0}; - for (int l=0; l(A+(ii)*lda+l); - packTranspose(B+(jj*ldb)+l, ldb, RN, 4, (TA*)vec_B); + float * a = const_cast(A + (ii) * lda + l); + packTranspose(B + (jj * ldb) + l, ldb, RN, 4, (float *)vec_B); vec_A[0] = (vec_t)vec_xl(0,a); - vec_A[1] = (vec_t)vec_splats(*((TA*)&vec_A+1)); - vec_A[2] = (vec_t)vec_splats(*((TA*)&vec_A+2)); - vec_A[3] = (vec_t)vec_splats(*((TA*)&vec_A+3)); + vec_A[1] = (vec_t)vec_splats(*((float *)&vec_A+1)); + vec_A[2] = (vec_t)vec_splats(*((float *)&vec_A+2)); + vec_A[3] = (vec_t)vec_splats(*((float *)&vec_A+3)); } else if (RN == 1) { - packTranspose(A+(ii*lda)+l, lda, RM, 4, (TA*)vec_A); - TB* b = const_cast(B+(jj)*ldb+l); + packTranspose(A + (ii * lda) + l, lda, RM, 4, (float *)vec_A); + float * b = const_cast(B + (jj) * ldb + l); vec_B[0] = (vec_t)vec_xl(0,b); - vec_B[1] = (vec_t)vec_splats(*((TB*)&vec_B+1)); - vec_B[2] = (vec_t)vec_splats(*((TB*)&vec_B+2)); - vec_B[3] = (vec_t)vec_splats(*((TB*)&vec_B+3)); + vec_B[1] = (vec_t)vec_splats(*((float *)&vec_B+1)); + vec_B[2] = (vec_t)vec_splats(*((float *)&vec_B+2)); + vec_B[3] = (vec_t)vec_splats(*((float *)&vec_B+3)); } else { - packTranspose(A+(ii*lda)+l, lda, RM, 4, (TA*)vec_A); - packTranspose(B+(jj*ldb)+l, ldb, RN, 4, (TA*)vec_B); + packTranspose(A + (ii * lda) + l, lda, RM, 4, (float *)vec_A); + packTranspose(B + (jj * ldb) + l, ldb, RN, 4, (float *)vec_B); } __builtin_mma_xvf32gerpp(&acc_0, vec_A[0], vec_B[0]); __builtin_mma_xvf32gerpp(&acc_0, vec_A[1], vec_B[1]); @@ -3231,12 +2585,27 @@ class tinyBLAS_PPC { __builtin_mma_disassemble_acc(vec_C, &acc_0); for (int I = 0; I < RM; I++) { for (int J = 0; J < RN; J++) { - *((TC*)(C+ii+((jj+J)*ldc)+I)) = *((TC*)&vec_C[I]+J); + *((float *)(C+ii+((jj+J)*ldc)+I)) = *((float *)&vec_C[I]+J); } } } } + template + inline void kernel(int64_t ii, int64_t jj) { + if constexpr(RM == 4 && RN == 4) { + KERNEL_4x4(ii, jj); + } else if constexpr(RM == 4 && RN == 8) { + KERNEL_4x8(ii, jj); + } else if constexpr(RM == 8 && RN == 4) { + KERNEL_8x4(ii, jj); + } else if constexpr(RM == 8 && RN == 8) { + KERNEL_8x8(ii, jj); + } else { + static_assert(false, "RN/RM values not supported"); + } + } + template NOINLINE void gemm(int64_t m0, int64_t m, int64_t n0, int64_t n) { int64_t ytiles = (m - m0) / RM; @@ -3245,29 +2614,18 @@ class tinyBLAS_PPC { int64_t duty = (tiles + nth - 1) / nth; int64_t start = duty * ith; int64_t end = start + duty; - if (RM == 4 && RN == 4) { - kernel = &tinyBLAS_PPC::KERNEL_4x4; - } else if (RM == 4 && RN == 8) { - kernel = &tinyBLAS_PPC::KERNEL_4x8; - } else if (RM == 8 && RN == 4) { - kernel = &tinyBLAS_PPC::KERNEL_8x4; - } else if (RM == 8 && RN == 8) { - kernel = &tinyBLAS_PPC::KERNEL_8x8; - } if (end > tiles) end = tiles; for (int64_t job = start; job < end; ++job) { int64_t ii = m0 + job / xtiles * RM; int64_t jj = n0 + job % xtiles * RN; - (this->*kernel)(ii, jj); + kernel(ii, jj); } } - const TA *const A; - const TB *const B; - TC *C; - TA *At; - TB *Bt; + const float * const A; + const float * const B; + float * C; const int64_t k; const int64_t lda; const int64_t ldb; @@ -3366,7 +2724,7 @@ bool llamafile_sgemm(const struct ggml_c #elif defined(__MMA__) if (k % 8) return false; - tinyBLAS_PPC tb{ + tinyBLAS_PPC tb{ k, (const float *)A, lda, (const float *)B, ldb, (float *)C, ldc, @@ -3493,7 +2851,7 @@ bool llamafile_sgemm(const struct ggml_c return false; if (m < 8 && m != 4) return false; - tinyBLAS_Q0_PPC tb{ + tinyBLAS_Q0_PPC tb{ k, (const block_q8_0 *)A, lda, (const block_q8_0 *)B, ldb, (float *)C, ldc, @@ -3530,7 +2888,7 @@ bool llamafile_sgemm(const struct ggml_c return false; if (m < 8 && m != 4) return false; - tinyBLAS_Q0_PPC tb{ + tinyBLAS_Q0_PPC tb{ k, (const block_q4_0 *)A, lda, (const block_q8_0 *)B, ldb, (float *)C, ldc, diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/ops.cpp 6641+dfsg-2/ggml/src/ggml-cpu/ops.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/ops.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/ops.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -8,6 +8,7 @@ #include "vec.h" #include +#include // ggml_compute_forward_dup @@ -40,13 +41,15 @@ static void ggml_compute_forward_dup_sam } } -static void ggml_compute_forward_dup_f16( +template +static void ggml_compute_forward_dup_flt( const ggml_compute_params * params, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; GGML_ASSERT(ggml_nelements(dst) == ggml_nelements(src0)); + GGML_ASSERT(!ggml_is_quantized(src0->type) && !ggml_is_quantized(dst->type)); GGML_TENSOR_UNARY_OP_LOCALS @@ -61,6 +64,7 @@ static void ggml_compute_forward_dup_f16 const int ir0 = dr * ith; const int ir1 = MIN(ir0 + dr, nr); + // case: type & row size equal if (src0->type == dst->type && ne00 == ne0 && nb00 == ggml_type_size(src0->type) && nb0 == ggml_type_size(dst->type)) { @@ -79,11 +83,11 @@ static void ggml_compute_forward_dup_f16 return; } - // TODO: add more special-case implementations for tensor shapes/strides that can benefit from memcpy - + // case: dst tensor is contiguous if (ggml_is_contiguous(dst)) { - if (nb00 == sizeof(ggml_fp16_t)) { - if (dst->type == GGML_TYPE_F16) { + if (nb00 == sizeof(src_t)) { + if constexpr (std::is_same_v) { + // same type size_t id = 0; const size_t rs = ne00 * nb00; char * dst_ptr = (char *) dst->data; @@ -99,390 +103,46 @@ static void ggml_compute_forward_dup_f16 id += rs * (ne01 - ir1); } } - } else if (dst->type == GGML_TYPE_F32) { - size_t id = 0; - float * dst_ptr = (float *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const ggml_fp16_t * src0_ptr = (ggml_fp16_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - for (int i00 = 0; i00 < ne00; i00++) { - dst_ptr[id] = GGML_CPU_FP16_TO_FP32(src0_ptr[i00]); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (ggml_get_type_traits_cpu(dst->type)->from_float) { - ggml_from_float_t const quantize_row_q = ggml_get_type_traits_cpu(dst->type)->from_float; - float * src0_f32 = (float *) params->wdata + (ne00 + CACHE_LINE_SIZE_F32) * ith; - - size_t id = 0; - size_t rs = nb0 * (ne00 / ggml_blck_size(dst->type)); - char * dst_ptr = (char *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += rs * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const ggml_fp16_t * src0_ptr = (ggml_fp16_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - - for (int i00 = 0; i00 < ne00; i00++) { - src0_f32[i00] = GGML_CPU_FP16_TO_FP32(src0_ptr[i00]); - } - - quantize_row_q(src0_f32, dst_ptr + id, ne00); - id += rs; - } - id += rs * (ne01 - ir1); - } - } } else { - GGML_ABORT("fatal error"); // TODO: implement - } - } else { - //printf("%s: this is not optimal - fix me\n", __func__); - - if (dst->type == GGML_TYPE_F32) { - size_t id = 0; - float * dst_ptr = (float *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const ggml_fp16_t * src0_ptr = (ggml_fp16_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = GGML_CPU_FP16_TO_FP32(*src0_ptr); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_F16) { + // casting between non-quantized types size_t id = 0; - ggml_fp16_t * dst_ptr = (ggml_fp16_t *) dst->data; + dst_t * dst_ptr = (dst_t *) dst->data; for (int i03 = 0; i03 < ne03; i03++) { for (int i02 = 0; i02 < ne02; i02++) { id += ne00 * ir0; for (int i01 = ir0; i01 < ir1; i01++) { + const src_t * src0_ptr = (src_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); for (int i00 = 0; i00 < ne00; i00++) { - const ggml_fp16_t * src0_ptr = (ggml_fp16_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = *src0_ptr; + float tmp = type_conversion_table::to_f32(src0_ptr[i00]); + dst_ptr[id] = type_conversion_table::from_f32(tmp); id++; } } id += ne00 * (ne01 - ir1); } } - } else { - GGML_ABORT("fatal error"); // TODO: implement - } - } - return; - } - - // dst counters - int64_t i10 = 0; - int64_t i11 = 0; - int64_t i12 = 0; - int64_t i13 = 0; - - if (dst->type == GGML_TYPE_F16) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - - memcpy(dst_ptr, src0_ptr, sizeof(ggml_fp16_t)); - - if (++i10 == ne00) { - i10 = 0; - if (++i11 == ne01) { - i11 = 0; - if (++i12 == ne02) { - i12 = 0; - if (++i13 == ne03) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - } else if (dst->type == GGML_TYPE_F32) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - - *(float *) dst_ptr = GGML_CPU_FP16_TO_FP32(*(const ggml_fp16_t *) src0_ptr); - - if (++i10 == ne0) { - i10 = 0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - } else { - GGML_ABORT("fatal error"); // TODO: implement - } -} - -static void ggml_compute_forward_dup_bf16( - const ggml_compute_params * params, - ggml_tensor * dst) { - - const ggml_tensor * src0 = dst->src[0]; - - GGML_ASSERT(ggml_nelements(dst) == ggml_nelements(src0)); - - GGML_TENSOR_UNARY_OP_LOCALS - - const int ith = params->ith; // thread index - const int nth = params->nth; // number of threads - - // parallelize by rows - const int nr = ne01; - // number of rows per thread - const int dr = (nr + nth - 1) / nth; - // row range for this thread - const int ir0 = dr * ith; - const int ir1 = MIN(ir0 + dr, nr); - - if (src0->type == dst->type && - ne00 == ne0 && - nb00 == ggml_type_size(src0->type) && nb0 == ggml_type_size(dst->type)) { - // copy by rows - const size_t rs = ne00*nb00; - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - for (int64_t i01 = ir0; i01 < ir1; i01++) { - memcpy( - ((char *) dst->data + i01*nb1 + i02*nb2 + i03*nb3), - ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03), - rs); - } - } - } - return; - } - - // TODO: add more special-case implementations for tensor shapes/strides that can benefit from memcpy - - if (ggml_is_contiguous(dst)) { - if (nb00 == sizeof(ggml_bf16_t)) { - if (dst->type == GGML_TYPE_BF16) { - size_t id = 0; - const size_t rs = ne00 * nb00; - char * dst_ptr = (char *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += rs * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const char * src0_ptr = (char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03; - memcpy(dst_ptr + id, src0_ptr, rs); - id += rs; - } - id += rs * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_F16) { - size_t id = 0; - ggml_fp16_t * dst_ptr = (ggml_fp16_t *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - for (int i00 = 0; i00 < ne00; i00++) { - dst_ptr[id] = GGML_CPU_FP32_TO_FP16(GGML_BF16_TO_FP32(src0_ptr[i00])); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_F32) { - size_t id = 0; - float * dst_ptr = (float *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - for (int i00 = 0; i00 < ne00; i00++) { - dst_ptr[id] = GGML_BF16_TO_FP32(src0_ptr[i00]); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (ggml_get_type_traits_cpu(dst->type)->from_float) { - ggml_from_float_t const quantize_row_q = ggml_get_type_traits_cpu(dst->type)->from_float; - float * src0_f32 = (float *) params->wdata + (ne00 + CACHE_LINE_SIZE_F32) * ith; - - size_t id = 0; - size_t rs = nb0 * (ne00 / ggml_blck_size(dst->type)); - char * dst_ptr = (char *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += rs * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - - for (int i00 = 0; i00 < ne00; i00++) { - src0_f32[i00] = GGML_BF16_TO_FP32(src0_ptr[i00]); - } - - quantize_row_q(src0_f32, dst_ptr + id, ne00); - id += rs; - } - id += rs * (ne01 - ir1); - } - } - } else { - GGML_ABORT("fatal error"); // TODO: implement } } else { //printf("%s: this is not optimal - fix me\n", __func__); - if (dst->type == GGML_TYPE_F32) { - size_t id = 0; - float * dst_ptr = (float *) dst->data; + size_t id = 0; + dst_t * dst_ptr = (dst_t *) dst->data; - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = GGML_BF16_TO_FP32(*src0_ptr); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_BF16) { - size_t id = 0; - ggml_bf16_t * dst_ptr = (ggml_bf16_t *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = *src0_ptr; - id++; - } + for (int i03 = 0; i03 < ne03; i03++) { + for (int i02 = 0; i02 < ne02; i02++) { + id += ne00 * ir0; + for (int i01 = ir0; i01 < ir1; i01++) { + for (int i00 = 0; i00 < ne00; i00++) { + const src_t * src0_ptr = (src_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); + + float tmp = type_conversion_table::to_f32(*src0_ptr); + dst_ptr[id] = type_conversion_table::from_f32(tmp); + id++; } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_F16) { - size_t id = 0; - ggml_fp16_t * dst_ptr = (ggml_fp16_t *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const ggml_bf16_t * src0_ptr = (ggml_bf16_t *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = GGML_CPU_FP32_TO_FP16(GGML_BF16_TO_FP32(*src0_ptr)); - id++; - } - } - id += ne00 * (ne01 - ir1); } + id += ne00 * (ne01 - ir1); } - } else { - GGML_ABORT("fatal error"); // TODO: implement } } return; @@ -494,7 +154,7 @@ static void ggml_compute_forward_dup_bf1 int64_t i12 = 0; int64_t i13 = 0; - if (dst->type == GGML_TYPE_BF16) { + if constexpr (std::is_same_v) { for (int64_t i03 = 0; i03 < ne03; i03++) { for (int64_t i02 = 0; i02 < ne02; i02++) { i10 += ne00 * ir0; @@ -515,7 +175,7 @@ static void ggml_compute_forward_dup_bf1 const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - memcpy(dst_ptr, src0_ptr, sizeof(ggml_bf16_t)); + memcpy(dst_ptr, src0_ptr, sizeof(dst_t)); if (++i10 == ne00) { i10 = 0; @@ -546,59 +206,8 @@ static void ggml_compute_forward_dup_bf1 } } } - } else if (dst->type == GGML_TYPE_F16) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - - *(ggml_fp16_t *) dst_ptr = GGML_CPU_FP32_TO_FP16(GGML_BF16_TO_FP32(*(const ggml_bf16_t *) src0_ptr)); - if (++i10 == ne0) { - i10 = 0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - } else if (dst->type == GGML_TYPE_F32) { + } else { for (int64_t i03 = 0; i03 < ne03; i03++) { for (int64_t i02 = 0; i02 < ne02; i02++) { i10 += ne00 * ir0; @@ -619,7 +228,8 @@ static void ggml_compute_forward_dup_bf1 const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - *(float *) dst_ptr = GGML_BF16_TO_FP32(*(const ggml_bf16_t *) src0_ptr); + float tmp = type_conversion_table::to_f32(*(const src_t *) src0_ptr); + *(dst_t *) dst_ptr = type_conversion_table::from_f32(tmp); if (++i10 == ne0) { i10 = 0; @@ -650,18 +260,19 @@ static void ggml_compute_forward_dup_bf1 } } } - } else { - GGML_ABORT("fatal error"); // TODO: implement } } -static void ggml_compute_forward_dup_f32( + +template +static void ggml_compute_forward_dup_to_q( const ggml_compute_params * params, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; GGML_ASSERT(ggml_nelements(dst) == ggml_nelements(src0)); + GGML_ASSERT(!ggml_is_quantized(src0->type)); GGML_TENSOR_UNARY_OP_LOCALS @@ -676,278 +287,36 @@ static void ggml_compute_forward_dup_f32 const int ir0 = dr * ith; const int ir1 = MIN(ir0 + dr, nr); - if (src0->type == dst->type && - ne00 == ne0 && - nb00 == ggml_type_size(src0->type) && nb0 == ggml_type_size(dst->type)) { - // copy by rows - const size_t rs = ne00*nb00; - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - for (int64_t i01 = ir0; i01 < ir1; i01++) { - memcpy( - ((char *) dst->data + i01*nb1 + i02*nb2 + i03*nb3), - ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03), - rs); - } - } - } - return; - } - - if (ggml_is_contiguous(dst)) { - // TODO: simplify - if (nb00 == sizeof(float)) { - if (ggml_get_type_traits_cpu(dst->type)->from_float) { - ggml_from_float_t const from_float = ggml_get_type_traits_cpu(dst->type)->from_float; - - size_t id = 0; - size_t rs = nb0 * (ne00 / ggml_blck_size(dst->type)); - char * dst_ptr = (char *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += rs * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - const float * src0_ptr = (float *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - from_float(src0_ptr, dst_ptr + id, ne00); - id += rs; - } - id += rs * (ne01 - ir1); - } - } - } else { - GGML_ABORT("fatal error"); // TODO: implement - } - } else { - //printf("%s: this is not optimal - fix me\n", __func__); - - if (dst->type == GGML_TYPE_F32) { - size_t id = 0; - float * dst_ptr = (float *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const float * src0_ptr = (float *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = *src0_ptr; - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_F16) { - size_t id = 0; - ggml_fp16_t * dst_ptr = (ggml_fp16_t *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const float * src0_ptr = (float *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = GGML_CPU_FP32_TO_FP16(*src0_ptr); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else if (dst->type == GGML_TYPE_BF16) { - size_t id = 0; - ggml_bf16_t * dst_ptr = (ggml_bf16_t *) dst->data; - - for (int i03 = 0; i03 < ne03; i03++) { - for (int i02 = 0; i02 < ne02; i02++) { - id += ne00 * ir0; - for (int i01 = ir0; i01 < ir1; i01++) { - for (int i00 = 0; i00 < ne00; i00++) { - const float * src0_ptr = (float *) ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - - dst_ptr[id] = GGML_FP32_TO_BF16(*src0_ptr); - id++; - } - } - id += ne00 * (ne01 - ir1); - } - } - } else { - GGML_ABORT("fatal error"); // TODO: implement - } - } - - return; - } - - // dst counters - - int64_t i10 = 0; - int64_t i11 = 0; - int64_t i12 = 0; - int64_t i13 = 0; - - if (dst->type == GGML_TYPE_F32) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); + if (ggml_is_contiguous(dst) && + nb00 == sizeof(src_t) && + ggml_get_type_traits_cpu(dst->type)->from_float) { + // casting non-quantized types --> intermediate f32 --> quantized + ggml_from_float_t const quantize_row_q = ggml_get_type_traits_cpu(dst->type)->from_float; + float * src0_f32 = (float *) params->wdata + (ne00 + CACHE_LINE_SIZE_F32) * ith; - memcpy(dst_ptr, src0_ptr, sizeof(float)); - - if (++i10 == ne0) { - i10 = 0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - } else if (dst->type == GGML_TYPE_F16) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); + size_t id = 0; + size_t rs = nb0 * (ne00 / ggml_blck_size(dst->type)); + char * dst_ptr = (char *) dst->data; - *(ggml_fp16_t *) dst_ptr = GGML_CPU_FP32_TO_FP16(*(const float *) src0_ptr); + for (int i03 = 0; i03 < ne03; i03++) { + for (int i02 = 0; i02 < ne02; i02++) { + id += rs * ir0; + for (int i01 = ir0; i01 < ir1; i01++) { + const src_t * src0_ptr = (src_t *) ((char *) src0->data + i01*nb01 + i02*nb02 + i03*nb03); - if (++i10 == ne0) { - i10 = 0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - } else if (dst->type == GGML_TYPE_BF16) { - for (int64_t i03 = 0; i03 < ne03; i03++) { - for (int64_t i02 = 0; i02 < ne02; i02++) { - i10 += ne00 * ir0; - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } + for (int i00 = 0; i00 < ne00; i00++) { + src0_f32[i00] = type_conversion_table::to_f32(src0_ptr[i00]); } - } - for (int64_t i01 = ir0; i01 < ir1; i01++) { - for (int64_t i00 = 0; i00 < ne00; i00++) { - const char * src0_ptr = ((char *) src0->data + i00*nb00 + i01*nb01 + i02*nb02 + i03*nb03); - char * dst_ptr = ((char *) dst->data + i10*nb0 + i11*nb1 + i12*nb2 + i13*nb3); - *(ggml_bf16_t *) dst_ptr = GGML_FP32_TO_BF16(*(const float *) src0_ptr); - - if (++i10 == ne0) { - i10 = 0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } - } - } - } - i10 += ne00 * (ne01 - ir1); - while (i10 >= ne0) { - i10 -= ne0; - if (++i11 == ne1) { - i11 = 0; - if (++i12 == ne2) { - i12 = 0; - if (++i13 == ne3) { - i13 = 0; - } - } - } + quantize_row_q(src0_f32, dst_ptr + id, ne00); + id += rs; } + id += rs * (ne01 - ir1); } } } else { - GGML_ABORT("fatal error"); // TODO: implement + // printf("%s %s\n", ggml_type_name(src0->type), ggml_type_name(dst->type)); + GGML_ABORT("not implemented"); } } @@ -1101,7 +470,7 @@ static void ggml_compute_forward_dup_byt } } -static void ggml_compute_forward_dup_q( +static void ggml_compute_forward_dup_from_q( const ggml_compute_params * params, ggml_tensor * dst) { @@ -1166,20 +535,35 @@ void ggml_compute_forward_dup( switch (src0->type) { case GGML_TYPE_F16: { - ggml_compute_forward_dup_f16(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else ggml_compute_forward_dup_to_q(params, dst); } break; case GGML_TYPE_BF16: { - ggml_compute_forward_dup_bf16(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else ggml_compute_forward_dup_to_q(params, dst); } break; case GGML_TYPE_F32: { - ggml_compute_forward_dup_f32(params, dst); + /**/ if (dst->type == GGML_TYPE_F16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_BF16) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else if (dst->type == GGML_TYPE_I32) ggml_compute_forward_dup_flt(params, dst); + else ggml_compute_forward_dup_to_q(params, dst); + } break; + case GGML_TYPE_I32: + { + if (dst->type == GGML_TYPE_F32) ggml_compute_forward_dup_flt(params, dst); + else GGML_ABORT("not implemented"); } break; default: { if (ggml_is_quantized(src0->type) && dst->type == GGML_TYPE_F32) { - ggml_compute_forward_dup_q(params, dst); + ggml_compute_forward_dup_from_q(params, dst); break; } GGML_ABORT("fatal error"); @@ -1283,6 +667,7 @@ void ggml_compute_forward_add( case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -1309,6 +694,77 @@ void ggml_compute_forward_add( } } +// ggml_compute_forward_add_id + +static void ggml_compute_forward_add_id_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; + + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + + GGML_ASSERT(src0->nb[0] == sizeof(float)); + GGML_ASSERT(src1->nb[0] == sizeof(float)); + + const int ith = params->ith; + const int nth = params->nth; + + const int nr = ggml_nrows(src0); + + GGML_TENSOR_TERNARY_OP_LOCALS + + GGML_ASSERT( nb0 == sizeof(float)); + GGML_ASSERT(nb10 == sizeof(float)); + + // rows per thread + const int dr = (nr + nth - 1)/nth; + + // row range for this thread + const int ir0 = dr*ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int ir = ir0; ir < ir1; ++ir) { + // src0 indices + const int i3 = ir/(ne2*ne1); + const int i2 = (ir - i3*ne2*ne1)/ne1; + const int i1 = (ir - i3*ne2*ne1 - i2*ne1); + + // src1 indices + const int i11 = *(int32_t *) ((char *) src2->data + i1*nb20 + i2*nb21); + + GGML_ASSERT(i11 >= 0 && i11 < ne11); + + ggml_vec_add_f32(ne0, + (float *) ((char *) dst->data + i3*nb3 + i2*nb2 + i1*nb1 ), + (float *) ((char *) src0->data + i3*nb03 + i2*nb02 + i1*nb01), + (float *) ((char *) src1->data + i11*nb11)); + } +} + +void ggml_compute_forward_add_id( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_add_id_f32(params, dst); + } break; + default: + { + GGML_ABORT("unsupported type for ggml_compute_forward_add_id: %s", ggml_type_name(src0->type)); + } + } +} + // ggml_compute_forward_add1 static void ggml_compute_forward_add1_f32( @@ -1660,6 +1116,7 @@ void ggml_compute_forward_add1( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -1787,6 +1244,7 @@ void ggml_compute_forward_acc( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -3614,6 +3072,93 @@ static void ggml_compute_forward_swiglu( } } +// ggml_compute_forward_swiglu_oai + +static void ggml_compute_forward_swiglu_oai_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + char * src0_d = (char *) src0->data; + char * src1_d = (char *) (src1 ? src1->data : src0->data); + const size_t src0_o = src0->nb[1]; + const size_t src1_o = src1 ? src1->nb[1] : src0->nb[1]; + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(ggml_is_contiguous_1(dst)); + + if (src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src0->type == src1->type); + } + + const int ith = params->ith; + const int nth = params->nth; + + const int nc = src1 ? src0->ne[0] : src0->ne[0] / 2; + const int nr = ggml_nrows(src0); + + GGML_ASSERT(dst->ne[0] == nc); + GGML_ASSERT(ggml_nrows(dst) == nr); + + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + + // rows per thread + const int dr = (nr + nth - 1)/nth; + + // row range for this thread + const int ir0 = dr*ith; + const int ir1 = MIN(ir0 + dr, nr); + + for (int i1 = ir0; i1 < ir1; i1++) { + float * src0_p = (float *) (src0_d + i1*src0_o); + float * src1_p = (float *) (src1_d + i1*src1_o); + float * dst_p = (float *) ((char *) dst->data + i1*(dst->nb[1])); + + if (!src1) { + src0_p += swapped ? nc : 0; + src1_p += swapped ? 0 : nc; + } + + for (int k = 0; k < nc; k++) { + const float x = std::min(src0_p[k], limit); + const float y = std::clamp(src1_p[k], -limit, limit); + const float out_glu = x / (1.f + expf(alpha * (-x))); + dst_p[k] = out_glu * (y + 1.f); + } + +#ifndef NDEBUG + for (int k = 0; k < nc; k++) { + const float x = dst_p[k]; + GGML_UNUSED(x); + assert(!isnan(x)); + assert(!isinf(x)); + } +#endif + } +} + +static void ggml_compute_forward_swiglu_oai( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_swiglu_oai_f32(params, dst); + } break; + default: + { + GGML_ABORT("fatal error"); + } + } +} + // ggml_compute_forward_geglu_erf static void ggml_compute_forward_geglu_erf_f32( @@ -4015,6 +3560,9 @@ static void ggml_compute_forward_rms_nor const float scale = 1.0f/sqrtf(mean + eps); + // if you hit this, likely you got an inf somewhere earlier + assert(scale > 0.0f); + ggml_vec_scale_f32(ne00, y, scale); } } @@ -4596,6 +4144,7 @@ void ggml_compute_forward_out_prod( case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -4870,6 +4419,7 @@ void ggml_compute_forward_set( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -5131,6 +4681,7 @@ void ggml_compute_forward_get_rows( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -5188,6 +4739,7 @@ void ggml_compute_forward_get_rows( //} } +template static void ggml_compute_forward_set_rows_f32( const ggml_compute_params * params, ggml_tensor * dst) { @@ -5226,7 +4778,7 @@ static void ggml_compute_forward_set_row const int64_t i11 = i02%ne11; const int64_t i10 = i; - const int64_t i1 = *(int64_t *) ((char *) src1->data + i10*nb10 + i11*nb11 + i12*nb12); + const int64_t i1 = *(idx_t *) ((char *) src1->data + i10*nb10 + i11*nb11 + i12*nb12); GGML_ASSERT(i1 >= 0 && i1 < ne1); @@ -5243,11 +4795,18 @@ void ggml_compute_forward_set_rows( ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; switch (src0->type) { case GGML_TYPE_F32: { - ggml_compute_forward_set_rows_f32(params, dst); + if (src1->type == GGML_TYPE_I64) { + ggml_compute_forward_set_rows_f32(params, dst); + } else if (src1->type == GGML_TYPE_I32) { + ggml_compute_forward_set_rows_f32(params, dst); + } else { + GGML_ABORT("src1->type = %d (%s) not supported", src1->type, ggml_type_name(src1->type)); + } } break; default: { @@ -5520,6 +5079,7 @@ static void ggml_compute_forward_soft_ma const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; assert(ggml_is_contiguous(dst)); assert(ggml_are_same_shape(src0, dst)); @@ -5554,6 +5114,9 @@ static void ggml_compute_forward_soft_ma const bool use_f16 = (src1 && src1->type == GGML_TYPE_F16); + // sinks + const float * sk = src2 ? (float *)((char *) src2->data) : nullptr; + for (int64_t i03 = 0; i03 < ne03; i03++) { for (int64_t i02 = 0; i02 < ne02; i02++) { for (int64_t i01 = ith; i01 < ne01; i01 += nth) { @@ -5596,9 +5159,18 @@ static void ggml_compute_forward_soft_ma float max = -INFINITY; ggml_vec_max_f32(ne00, &max, wp); + // if we have sinks, make a correction as if they were included in the softmax + if (sk) { + max = MAX(max, sk[i02]); + } + ggml_float sum = ggml_vec_soft_max_f32(ne00, dp, wp, max); assert(sum > 0.0); + if (sk) { + sum += (ggml_float) expf(sk[i02] - max); + } + sum = 1.0/sum; ggml_vec_scale_f32(ne00, dp, sum); @@ -5833,6 +5405,7 @@ void ggml_compute_forward_clamp( case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: case GGML_TYPE_Q8_1: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -6845,6 +6418,209 @@ void ggml_compute_forward_im2col_back_f3 } } + +// ggml_compute_forward_im2col_3d_f16 +// src0: kernel [OC*IC, KD, KH, KW] +// src1: image [N*IC, ID, IH, IW] +// dst: result [N*OD, OH, OW, IC * KD * KH * KW] +static void ggml_compute_forward_im2col_3d_f16( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + GGML_ASSERT(src0->type == GGML_TYPE_F16); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F16); + + GGML_TENSOR_BINARY_OP_LOCALS; + + const int32_t s0 = ((const int32_t *)(dst->op_params))[0]; + const int32_t s1 = ((const int32_t *)(dst->op_params))[1]; + const int32_t s2 = ((const int32_t *)(dst->op_params))[2]; + const int32_t p0 = ((const int32_t *)(dst->op_params))[3]; + const int32_t p1 = ((const int32_t *)(dst->op_params))[4]; + const int32_t p2 = ((const int32_t *)(dst->op_params))[5]; + const int32_t d0 = ((const int32_t *)(dst->op_params))[6]; + const int32_t d1 = ((const int32_t *)(dst->op_params))[7]; + const int32_t d2 = ((const int32_t *)(dst->op_params))[8]; + const int32_t IC = ((const int32_t *)(dst->op_params))[9]; + + + const int ith = params->ith; + const int nth = params->nth; + + const int64_t N = ne13 / IC; + const int64_t ID = ne12; + const int64_t IH = ne11; + const int64_t IW = ne10; + + const int64_t OC = ne03 / IC; + GGML_UNUSED(OC); + const int64_t KD = ne02; + const int64_t KH = ne01; + const int64_t KW = ne00; + + const int64_t OD = ne3 / N; + const int64_t OH = ne2; + const int64_t OW = ne1; + const int64_t OH_OW = OH*OW; + const int64_t KD_KH_KW = KD*KH*KW; + const int64_t KH_KW = KH*KW; + const int64_t IC_KD_KH_KW = IC*KD*KH*KW; + + GGML_ASSERT(nb10 == sizeof(float)); + + // im2col: [N*IC, ID, IH, IW] => [N*OD, OH, OW, IC * KD * KH * KW] + { + ggml_fp16_t * const wdata = (ggml_fp16_t *) dst->data; + + for (int64_t in = 0; in < N; in++) { + for (int64_t iod = 0; iod < OD; iod++) { + for (int64_t ioh = 0; ioh < OH; ioh++) { + for (int64_t iow = 0; iow < OW; iow++) { + for (int64_t iic = ith; iic < IC; iic += nth) { + + // micro kernel + ggml_fp16_t * dst_data = wdata + (in*OD*OH_OW + iod*OH_OW + ioh*OW + iow)*IC_KD_KH_KW; // [IC, KD, KH, KW] + const float * const src_data = (const float *) ((const char *)src1->data + (in*IC + iic)*nb13); // [ID, IH, IW] + + for (int64_t ikd = 0; ikd < KD; ikd++) { + for (int64_t ikh = 0; ikh < KH; ikh++) { + for (int64_t ikw = 0; ikw < KW; ikw++) { + const int64_t iiw = iow*s0 + ikw*d0 - p0; + const int64_t iih = ioh*s1 + ikh*d1 - p1; + const int64_t iid = iod*s2 + ikd*d2 - p2; + + if (iid < 0 || iid >= ID || iih < 0 || iih >= IH || iiw < 0 || iiw >= IW || iid < 0 || iid >= ID) { + dst_data[iic*KD_KH_KW + ikd * KH_KW + ikh*KW + ikw] = 0; + } else { + const float * const s = (const float *) ((const char *)src_data + iid*nb12 + iih*nb11 + iiw*nb10); // [ID, IH, IW] + dst_data[iic*KD_KH_KW + ikd * KH_KW + ikh*KW + ikw] = GGML_CPU_FP32_TO_FP16(*s); + } + } + } + } + } + } + } + } + } + } +} + +// ggml_compute_forward_im2col_3d_f32 +// src0: kernel [OC*IC, KD, KH, KW] +// src1: image [N*IC, ID, IH, IW] +// dst: result [N*OD, OH, OW, IC * KD * KH * KW] +static void ggml_compute_forward_im2col_3d_f32( + const ggml_compute_params * params, + ggml_tensor * dst) { + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + GGML_TENSOR_BINARY_OP_LOCALS; + + const int32_t s0 = ((const int32_t *)(dst->op_params))[0]; + const int32_t s1 = ((const int32_t *)(dst->op_params))[1]; + const int32_t s2 = ((const int32_t *)(dst->op_params))[2]; + const int32_t p0 = ((const int32_t *)(dst->op_params))[3]; + const int32_t p1 = ((const int32_t *)(dst->op_params))[4]; + const int32_t p2 = ((const int32_t *)(dst->op_params))[5]; + const int32_t d0 = ((const int32_t *)(dst->op_params))[6]; + const int32_t d1 = ((const int32_t *)(dst->op_params))[7]; + const int32_t d2 = ((const int32_t *)(dst->op_params))[8]; + const int32_t IC = ((const int32_t *)(dst->op_params))[9]; + + + const int ith = params->ith; + const int nth = params->nth; + + const int64_t N = ne13 / IC; + const int64_t ID = ne12; + const int64_t IH = ne11; + const int64_t IW = ne10; + + const int64_t OC = ne03 / IC; + GGML_UNUSED(OC); + const int64_t KD = ne02; + const int64_t KH = ne01; + const int64_t KW = ne00; + + const int64_t OD = ne3 / N; + const int64_t OH = ne2; + const int64_t OW = ne1; + + const int64_t OH_OW = OH*OW; + const int64_t KD_KH_KW = KD*KH*KW; + const int64_t KH_KW = KH*KW; + const int64_t IC_KD_KH_KW = IC*KD*KH*KW; + + GGML_ASSERT(nb10 == sizeof(float)); + + // im2col: [N*IC, ID, IH, IW] => [N*OD, OH, OW, IC * KD * KH * KW] + { + float * const wdata = (float *) dst->data; + + for (int64_t in = 0; in < N; in++) { + for (int64_t iod = 0; iod < OD; iod++) { + for (int64_t ioh = 0; ioh < OH; ioh++) { + for (int64_t iow = 0; iow < OW; iow++) { + for (int64_t iic = ith; iic < IC; iic += nth) { + + // micro kernel + float * dst_data = wdata + (in*OD*OH_OW + iod*OH_OW + ioh*OW + iow)*IC_KD_KH_KW; // [IC, KD, KH, KW] + const float * const src_data = (const float *) ((const char *)src1->data + (in*IC + iic)*nb13); // [ID, IH, IW] + + for (int64_t ikd = 0; ikd < KD; ikd++) { + for (int64_t ikh = 0; ikh < KH; ikh++) { + for (int64_t ikw = 0; ikw < KW; ikw++) { + const int64_t iiw = iow*s0 + ikw*d0 - p0; + const int64_t iih = ioh*s1 + ikh*d1 - p1; + const int64_t iid = iod*s2 + ikd*d2 - p2; + + if (iid < 0 || iid >= ID || iih < 0 || iih >= IH || iiw < 0 || iiw >= IW || iid < 0 || iid >= ID) { + dst_data[iic*KD_KH_KW + ikd * KH_KW + ikh*KW + ikw] = 0; + } else { + const float * const s = (const float *) ((const char *)src_data + iid*nb12 + iih*nb11 + iiw*nb10); // [ID, IH, IW] + dst_data[iic*KD_KH_KW + ikd * KH_KW + ikh*KW + ikw] = *s; + } + } + } + } + } + } + } + } + } + } +} + + +void ggml_compute_forward_im2col_3d( + const ggml_compute_params * params, + ggml_tensor * dst) { + switch (dst->type) { + case GGML_TYPE_F16: + { + ggml_compute_forward_im2col_3d_f16(params, dst); + } break; + case GGML_TYPE_F32: + { + ggml_compute_forward_im2col_3d_f32(params, dst); + } break; + default: + { + GGML_ABORT("fatal error"); + } + } +} + static void ggml_call_mul_mat(ggml_type type, const ggml_compute_params * params, int64_t m, int64_t n, int64_t k, void * a, void * b, float * c) { const ggml_type_traits * traits = ggml_get_type_traits(type); @@ -7025,6 +6801,148 @@ void ggml_compute_forward_conv_2d( ggml_compute_forward_conv_2d_impl(params, src0, src1, dst, src0->type); } +// ggml_compute_forward_conv_3d + +static void ggml_compute_forward_conv_3d_impl(const ggml_compute_params * params, + const ggml_tensor * kernel, + const ggml_tensor * src, + ggml_tensor * dst, + ggml_type kernel_type) { + + GGML_ASSERT(ggml_is_contiguous(kernel)); + GGML_ASSERT(kernel_type == GGML_TYPE_F16 || kernel_type == GGML_TYPE_F32); + GGML_ASSERT(kernel->type == kernel_type); + + const ggml_type_traits * traits = ggml_get_type_traits(kernel_type); + + const int32_t s0 = dst->op_params[0]; + const int32_t s1 = dst->op_params[1]; + const int32_t s2 = dst->op_params[2]; + const int32_t p0 = dst->op_params[3]; + const int32_t p1 = dst->op_params[4]; + const int32_t p2 = dst->op_params[5]; + const int32_t d0 = dst->op_params[6]; + const int32_t d1 = dst->op_params[7]; + const int32_t d2 = dst->op_params[8]; + const int32_t c = dst->op_params[9]; + const int32_t n = dst->op_params[10]; + const int32_t oc = dst->op_params[11]; + + const int64_t src_w = src->ne[0]; + const int64_t src_h = src->ne[1]; + const int64_t src_d = src->ne[2]; + const int64_t knl_w = kernel->ne[0]; + const int64_t knl_h = kernel->ne[1]; + const int64_t knl_d = kernel->ne[2]; + const int64_t dst_w = dst->ne[0]; + const int64_t dst_h = dst->ne[1]; + const int64_t dst_d = dst->ne[2]; + + const float * src_data = (float *) src->data; + void * knl_data = kernel->data; + float * dst_data = (float *) dst->data; + + const int64_t knl_n_per_channel = knl_w * knl_h * knl_d; + const int64_t knl_n_total = knl_n_per_channel * c; + const int64_t patch_total = n * dst_w * dst_h * dst_d; + + const int64_t space_per_patch = knl_n_total * traits->type_size + oc * sizeof(float); + const int64_t batch_size = params->wsize / space_per_patch; + const int64_t patches_per_batch = batch_size > 8 ? (batch_size / 8) * 8 : batch_size; + const int64_t batch_n = (patch_total + patches_per_batch - 1) / patches_per_batch; + + GGML_ASSERT(patches_per_batch > 0 && batch_size >= 1); + + void * tmp = params->wdata; + + for (int64_t batch_i = 0; batch_i < batch_n; ++batch_i) { + const int64_t patch_start_batch = batch_i * patches_per_batch; + const int64_t patch_end_batch = std::min(patch_start_batch + patches_per_batch, patch_total); + const int64_t patch_n_in_batch = patch_end_batch - patch_start_batch; + + const int64_t patch_per_thread = (patch_n_in_batch + params->nth - 1) / params->nth; + const int64_t patch_start = patch_start_batch + params->ith * patch_per_thread; + const int64_t patch_end = std::min(patch_start + patch_per_thread, patch_end_batch); + + for (int64_t p = patch_start; p < patch_end; ++p) { + const int64_t p_in_batch = p % (dst_w * dst_h * dst_d); + const int64_t p_in_depth = p_in_batch % (dst_w * dst_h); + const int64_t batch_idx = p / (dst_w * dst_h * dst_d); + const int64_t dst_z = p_in_batch / (dst_w * dst_h); + const int64_t dst_y = p_in_depth / dst_w; + const int64_t dst_x = p_in_depth % dst_w; + + char * dst_row = (char *) tmp + (p % patches_per_batch) * knl_n_total * traits->type_size; + + for (int64_t ic = 0; ic < c; ++ic) { + for (int64_t kz = 0; kz < knl_d; ++kz) { + for (int64_t ky = 0; ky < knl_h; ++ky) { + for (int64_t kx = 0; kx < knl_w; ++kx) { + const int64_t sz = dst_z * s2 + kz * d2 - p2; + const int64_t sy = dst_y * s1 + ky * d1 - p1; + const int64_t sx = dst_x * s0 + kx * d0 - p0; + + int64_t dst_idx = ic * knl_n_per_channel + kz * (knl_h * knl_w) + ky * knl_w + kx; + + float src_val; + if (sz < 0 || sz >= src_d || sy < 0 || sy >= src_h || sx < 0 || sx >= src_w) { + src_val = 0.0f; + } else { + const int64_t cn_idx = batch_idx * c + ic; + const float * src_ptr = (const float *)((const char *)src_data + sx*src->nb[0] + sy*src->nb[1] + sz*src->nb[2] + cn_idx*src->nb[3]); + src_val = *src_ptr; + } + + char * element_ptr = dst_row + dst_idx * traits->type_size; + if (kernel_type == GGML_TYPE_F32) { + *(float *)element_ptr = src_val; + } else if (kernel_type == GGML_TYPE_F16) { + *(ggml_fp16_t *)element_ptr = GGML_CPU_FP32_TO_FP16(src_val); + } + } + } + } + } + } + + ggml_barrier(params->threadpool); + + float * gemm_output = (float *) ((char *) tmp + patches_per_batch * knl_n_total * traits->type_size); + ggml_call_mul_mat(kernel_type, params, patch_n_in_batch, oc, knl_n_total, tmp, knl_data, gemm_output); + + ggml_barrier(params->threadpool); + + const int64_t permute_per_thread = (patch_n_in_batch + params->nth - 1) / params->nth; + const int64_t permute_start = params->ith * permute_per_thread; + const int64_t permute_end = std::min(permute_start + permute_per_thread, patch_n_in_batch); + + for (int64_t i = permute_start; i < permute_end; ++i) { + const int64_t p = patch_start_batch + i; + const int64_t p_in_batch = p % (dst_w * dst_h * dst_d); + const int64_t p_in_depth = p_in_batch % (dst_w * dst_h); + const int64_t batch_idx = p / (dst_w * dst_h * dst_d); + const int64_t dst_z = p_in_batch / (dst_w * dst_h); + const int64_t dst_y = p_in_depth / dst_w; + const int64_t dst_x = p_in_depth % dst_w; + + for (int64_t ioc = 0; ioc < oc; ++ioc) { + const float value = gemm_output[i * oc + ioc]; + const int64_t ocn_idx = batch_idx * oc + ioc; + float * dst_ptr = (float *)((char *)dst_data + dst_x*dst->nb[0] + dst_y*dst->nb[1] + dst_z*dst->nb[2] + ocn_idx*dst->nb[3]); + *dst_ptr = value; + } + } + } +} + +void ggml_compute_forward_conv_3d( + const ggml_compute_params * params, + ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + ggml_compute_forward_conv_3d_impl(params, src0, src1, dst, src0->type); +} + // ggml_compute_forward_conv_transpose_2d void ggml_compute_forward_conv_transpose_2d( @@ -7690,6 +7608,15 @@ static void ggml_compute_forward_pad_f32 GGML_TENSOR_UNARY_OP_LOCALS float * dst_ptr = (float *) dst->data; + const int32_t lp0 = ggml_get_op_params_i32(dst, 0); + const int32_t rp0 = ggml_get_op_params_i32(dst, 1); + const int32_t lp1 = ggml_get_op_params_i32(dst, 2); + const int32_t rp1 = ggml_get_op_params_i32(dst, 3); + const int32_t lp2 = ggml_get_op_params_i32(dst, 4); + const int32_t rp2 = ggml_get_op_params_i32(dst, 5); + const int32_t lp3 = ggml_get_op_params_i32(dst, 6); + const int32_t rp3 = ggml_get_op_params_i32(dst, 7); + // TODO: optimize @@ -7698,10 +7625,12 @@ static void ggml_compute_forward_pad_f32 for (int64_t i0 = 0; i0 < ne0; ++i0) { for (int64_t i3 = 0; i3 < ne3; ++i3) { const int64_t dst_idx = i3*(ne0*ne1*ne2) + i2*(ne0*ne1) + i1*ne0 + i0; - - const float * src_ptr = (const float *)((char *) src0->data + i3*nb03 + i2*nb02 + i1*nb01 + i0*nb00); - - if (i0 < ne00 && i1 < ne01 && i2 < ne02 && i3 < ne03) { + if ((i0 >= lp0 && i0 < ne0 - rp0) \ + && (i1 >= lp1 && i1 < ne1 - rp1) \ + && (i2 >= lp2 && i2 < ne2 - rp2) \ + && (i3 >= lp3 && i3 < ne3 - rp3)) { + const int64_t src_idx = (i3 - lp3)*nb03 + (i2 - lp2)*nb02 + (i1 - lp1)*nb01 + (i0 - lp0)*nb00; + const float * src_ptr = (const float *)((char *) src0->data + src_idx); dst_ptr[dst_idx] = *src_ptr; } else { dst_ptr[dst_idx] = 0; @@ -7900,7 +7829,7 @@ static void ggml_compute_forward_timeste embed_data[j + half] = sinf(arg); } if (dim % 2 != 0 && ith == 0) { - embed_data[dim] = 0.f; + embed_data[2 * half] = 0.f; } } } @@ -7986,12 +7915,14 @@ void ggml_compute_forward_argsort( static void ggml_compute_forward_flash_attn_ext_f16( const ggml_compute_params * params, - const ggml_tensor * q, - const ggml_tensor * k, - const ggml_tensor * v, - const ggml_tensor * mask, ggml_tensor * dst) { + const ggml_tensor * q = dst->src[0]; + const ggml_tensor * k = dst->src[1]; + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + GGML_TENSOR_LOCALS(int64_t, neq, q, ne) GGML_TENSOR_LOCALS(size_t, nbq, q, nb) GGML_TENSOR_LOCALS(int64_t, nek, k, ne) @@ -8186,6 +8117,23 @@ static void ggml_compute_forward_flash_a } } + // sinks + if (sinks) { + const float s = ((float *)((char *) sinks->data))[h]; + + float ms = 1.0f; + float vs = 1.0f; + + if (s > M) { + ms = expf(M - s); + ggml_vec_scale_f32(DV, VKQ32, ms); + } else { + vs = expf(s - M); + } + + S = S*ms + vs; + } + // V /= S const float S_inv = 1.0f/S; ggml_vec_scale_f32(DV, VKQ32, S_inv); @@ -8205,17 +8153,13 @@ static void ggml_compute_forward_flash_a void ggml_compute_forward_flash_attn_ext( const ggml_compute_params * params, - const ggml_tensor * q, - const ggml_tensor * k, - const ggml_tensor * v, - const ggml_tensor * mask, ggml_tensor * dst) { switch (dst->op_params[3]) { case GGML_PREC_DEFAULT: case GGML_PREC_F32: { // uses F32 accumulators - ggml_compute_forward_flash_attn_ext_f16(params, q, k, v, mask, dst); + ggml_compute_forward_flash_attn_ext_f16(params, dst); } break; default: { @@ -8664,8 +8608,7 @@ static void ggml_compute_forward_ssm_sca GGML_ASSERT(src4->nb[0] == sizeof(float)); GGML_ASSERT(src5->nb[0] == sizeof(float)); GGML_ASSERT(src6->nb[0] == sizeof(int32_t)); - // allows optimizing the modulo since n_group should be a power of 2 - GGML_ASSERT((ng & -ng) == ng); + GGML_ASSERT(nh % ng == 0); // heads per thread const int dh = (nh + nth - 1)/nth; @@ -8696,6 +8639,7 @@ static void ggml_compute_forward_ssm_sca // ref: https://github.com/state-spaces/mamba/blob/62db608da60f6fc790b8ed9f4b3225e95ca15fde/mamba_ssm/ops/triton/softplus.py#L16 const float dt_soft_plus = dt[h] <= 20.0f ? log1pf(expf(dt[h])) : dt[h]; const float dA = expf(dt_soft_plus * A[h]); + const int g = h / (nh / ng); // repeat_interleave // dim for (int i1 = 0; i1 < nr; ++i1) { @@ -8718,8 +8662,8 @@ static void ggml_compute_forward_ssm_sca // TODO: maybe unroll more? for (int j = 0; j < 1; j++) { GGML_F32_VEC t0 = GGML_F32_VEC_LOAD(s0 + i + j*ggml_f32_epr + ii*nc); - GGML_F32_VEC t1 = GGML_F32_VEC_LOAD(B + i + j*ggml_f32_epr + (h & (ng - 1))*nc); - GGML_F32_VEC t2 = GGML_F32_VEC_LOAD(C + i + j*ggml_f32_epr + (h & (ng - 1))*nc); + GGML_F32_VEC t1 = GGML_F32_VEC_LOAD(B + i + j*ggml_f32_epr + g*nc); + GGML_F32_VEC t2 = GGML_F32_VEC_LOAD(C + i + j*ggml_f32_epr + g*nc); t0 = GGML_F32_VEC_MUL(t0, adA); t1 = GGML_F32_VEC_MUL(t1, axdt); @@ -8733,6 +8677,9 @@ static void ggml_compute_forward_ssm_sca } sumf = GGML_F32xt_REDUCE_ONE(sum); + #elif defined(__riscv_v_intrinsic) + // todo: RVV implementation + const int np = 0; #else const int np = (nc & ~(GGML_F32_STEP - 1)); @@ -8748,8 +8695,8 @@ static void ggml_compute_forward_ssm_sca for (int i = 0; i < np; i += GGML_F32_STEP) { for (int j = 0; j < GGML_F32_ARR; j++) { ax[j] = GGML_F32_VEC_LOAD(s0 + i + j*GGML_F32_EPR + ii*nc); - ay[j] = GGML_F32_VEC_LOAD(B + i + j*GGML_F32_EPR + (h & (ng - 1))*nc); - az[j] = GGML_F32_VEC_LOAD(C + i + j*GGML_F32_EPR + (h & (ng - 1))*nc); + ay[j] = GGML_F32_VEC_LOAD(B + i + j*GGML_F32_EPR + g*nc); + az[j] = GGML_F32_VEC_LOAD(C + i + j*GGML_F32_EPR + g*nc); ax[j] = GGML_F32_VEC_MUL(ax[j], adA); ay[j] = GGML_F32_VEC_MUL(ay[j], axdt); @@ -8771,7 +8718,7 @@ static void ggml_compute_forward_ssm_sca // d_state for (int i0 = np; i0 < nc; ++i0) { const int i = i0 + ii*nc; - const int ig = i0 + (h & (ng - 1))*nc; + const int ig = i0 + g*nc; // state = prev_state * dA + dB * x const float state = (s0[i] * dA) + (B[ig] * x_dt); // y = rowwise_dotprod(state, C) @@ -8788,6 +8735,7 @@ static void ggml_compute_forward_ssm_sca for (int h = ih0; h < ih1; ++h) { // ref: https://github.com/state-spaces/mamba/blob/62db608da60f6fc790b8ed9f4b3225e95ca15fde/mamba_ssm/ops/triton/softplus.py#L16 const float dt_soft_plus = dt[h] <= 20.0f ? log1pf(expf(dt[h])) : dt[h]; + const int g = h / (nh / ng); // repeat_interleave // dim for (int i1 = 0; i1 < nr; ++i1) { @@ -8802,8 +8750,8 @@ static void ggml_compute_forward_ssm_sca // TODO: what happens when (d_state % svcntw()) != 0? for (int64_t k = 0; k < nc; k += svcntw()) { svfloat32_t vA = GGML_F32_VEC_LOAD(&A[h*nc + k]); - svfloat32_t vB = GGML_F32_VEC_LOAD(&B[k + (h & (ng - 1))*nc]); - svfloat32_t vC = GGML_F32_VEC_LOAD(&C[k + (h & (ng - 1))*nc]); + svfloat32_t vB = GGML_F32_VEC_LOAD(&B[k + g*nc]); + svfloat32_t vC = GGML_F32_VEC_LOAD(&C[k + g*nc]); svfloat32_t vs0 = GGML_F32_VEC_LOAD(&s0[ii*nc + k]); svfloat32_t t1 = GGML_F32_VEC_MUL(vdt_soft_plus, vA); @@ -8823,7 +8771,7 @@ static void ggml_compute_forward_ssm_sca // d_state for (int i0 = 0; i0 < nc; ++i0) { const int i = i0 + ii*nc; - const int ig = i0 + (h & (ng - 1))*nc; + const int ig = i0 + g*nc; // state = prev_state * dA + dB * x const float state = (s0[i] * expf(dt_soft_plus * A[i0 + h*nc])) + (B[ig] * x_dt); // y = rowwise_dotprod(state, C) @@ -9077,6 +9025,10 @@ void ggml_compute_forward_glu( { ggml_compute_forward_swiglu(params, dst); } break; + case GGML_GLU_OP_SWIGLU_OAI: + { + ggml_compute_forward_swiglu_oai(params, dst); + } break; case GGML_GLU_OP_GEGLU_ERF: { ggml_compute_forward_geglu_erf(params, dst); @@ -9680,8 +9632,8 @@ static void ggml_compute_forward_rwkv_wk int64_t h_stride_2d = head_size * head_size; #if defined(GGML_SIMD) - #if defined(__ARM_FEATURE_SVE) - // scalar Route to scalar implementation //TODO: Write SVE code + #if defined(__ARM_FEATURE_SVE) || defined(__riscv_v_intrinsic) + // scalar Route to scalar implementation //TODO: Write SVE code and RVV code for (int64_t t = 0; t < T; t++) { int64_t t_offset = t * t_stride; int64_t state_offset = head_size * C * (t / (T / n_seqs)); @@ -10129,6 +10081,7 @@ static void ggml_compute_forward_opt_ste const int ir1 = MIN(ir0 + dr, nr); const float * adamw_params_ptr = ggml_get_data_f32(adamw_params); + const float alpha = adamw_params_ptr[0]; const float beta1 = adamw_params_ptr[1]; const float beta2 = adamw_params_ptr[2]; @@ -10136,7 +10089,7 @@ static void ggml_compute_forward_opt_ste const float wd = adamw_params_ptr[4]; const float beta1h = adamw_params_ptr[5]; const float beta2h = adamw_params_ptr[6]; - + const float keep = 1.f - alpha * wd; for (int ir = ir0; ir < ir1; ++ir) { const int64_t i03 = ir/(ne02*ne01); const int64_t i02 = (ir - i03*ne02*ne01)/ne01; @@ -10159,7 +10112,7 @@ static void ggml_compute_forward_opt_ste // The weight decay is applied independently of the Adam momenta m and v. // This is NOT equivalent to l2 regularization that adds w[i00]*w[i00] to the loss. // See: https://arxiv.org/pdf/1711.05101v3.pdf - w[i00] = w[i00]*(1.0f - alpha*wd) - alpha*mh/vh; + w[i00] = w[i00] * keep - alpha * mh / vh; } } } @@ -10181,3 +10134,63 @@ void ggml_compute_forward_opt_step_adamw } } } + +static void ggml_compute_forward_opt_step_sgd_f32(const ggml_compute_params * params, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src0_grad = dst->src[1]; + const ggml_tensor * sgd_params = dst->src[2]; + + GGML_ASSERT(ggml_are_same_shape(src0, src0_grad)); + GGML_ASSERT(ggml_nelements(sgd_params) == 2); + + const int ith = params->ith; + const int nth = params->nth; + + const int nr = ggml_nrows(src0); + + GGML_TENSOR_UNARY_OP_LOCALS + GGML_ASSERT(nb00 == sizeof(float)); + + // rows per thread + const int dr = (nr + nth - 1) / nth; + + // row range for this thread + const int ir0 = dr * ith; + const int ir1 = MIN(ir0 + dr, nr); + + // using adamw param subset we care about - alpha, wd - could have a separate struct + const float * sgd_params_ptr = ggml_get_data_f32(sgd_params); + const float alpha = sgd_params_ptr[0]; + const float keep = 1.f - alpha * sgd_params_ptr[1]; + + for (int ir = ir0; ir < ir1; ++ir) { + const int64_t i03 = ir / (ne02 * ne01); + const int64_t i02 = (ir - i03 * ne02 * ne01) / ne01; + const int64_t i01 = (ir - i03 * ne02 * ne01 - i02 * ne01); + + const size_t offset = i03 * nb03 + i02 * nb02 + i01 * nb01; + + float * w = (float *) ((char *) src0->data + offset); // weight + const float * g = (const float *) ((const char *) src0_grad->data + offset); // grad + + for (int i00 = 0; i00 < ne00; ++i00) { + w[i00] = w[i00] * keep - alpha * g[i00]; + } + } +} + +void ggml_compute_forward_opt_step_sgd(const ggml_compute_params * params, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + + switch (src0->type) { + case GGML_TYPE_F32: + { + ggml_compute_forward_opt_step_sgd_f32(params, dst); + } + break; + default: + { + GGML_ABORT("fatal error - sgd is F32 only"); + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/ops.h 6641+dfsg-2/ggml/src/ggml-cpu/ops.h --- 5882+dfsg-2/ggml/src/ggml-cpu/ops.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/ops.h 2025-09-30 07:36:33.000000000 +0000 @@ -29,6 +29,7 @@ extern "C" { void ggml_compute_forward_dup(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_add(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_add_id(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_add1(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_acc(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_sum(const struct ggml_compute_params * params, struct ggml_tensor * dst); @@ -68,7 +69,9 @@ void ggml_compute_forward_clamp(const st void ggml_compute_forward_conv_transpose_1d(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_im2col(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_im2col_back_f32(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_im2col_3d(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_conv_2d(const struct ggml_compute_params * params, struct ggml_tensor * dst); +void ggml_compute_forward_conv_3d(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_conv_transpose_2d(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_conv_2d_dw(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_pool_1d(const struct ggml_compute_params * params, struct ggml_tensor * dst); @@ -82,13 +85,7 @@ void ggml_compute_forward_arange(const s void ggml_compute_forward_timestep_embedding(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_argsort(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_leaky_relu(const struct ggml_compute_params * params, struct ggml_tensor * dst); -void ggml_compute_forward_flash_attn_ext( - const struct ggml_compute_params * params, - const struct ggml_tensor * q, - const struct ggml_tensor * k, - const struct ggml_tensor * v, - const struct ggml_tensor * mask, - struct ggml_tensor * dst); +void ggml_compute_forward_flash_attn_ext(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_flash_attn_back( const struct ggml_compute_params * params, const bool masked, @@ -112,7 +109,7 @@ void ggml_compute_forward_cross_entropy_ void ggml_compute_forward_cross_entropy_loss_back(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_opt_step_adamw(const struct ggml_compute_params * params, struct ggml_tensor * dst); void ggml_compute_forward_mul_mat(const struct ggml_compute_params * params, struct ggml_tensor * dst); - +void ggml_compute_forward_opt_step_sgd(const struct ggml_compute_params * params, struct ggml_tensor * dst); #ifdef __cplusplus } #endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/quants.c 6641+dfsg-2/ggml/src/ggml-cpu/quants.c --- 5882+dfsg-2/ggml/src/ggml-cpu/quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -46,6 +46,10 @@ void quantize_row_q8_1_generic(const flo quantize_row_q8_1_ref(x, y, k); } +void quantize_row_mxfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k) { + quantize_row_mxfp4_ref(x, y, k); +} + // // 2-6 bit quantization in super-blocks // @@ -181,6 +185,37 @@ void ggml_vec_dot_q4_1_q8_1_generic(int *s = sumf; } +void ggml_vec_dot_mxfp4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { + assert(nrc == 1); + UNUSED(nrc); + UNUSED(bx); + UNUSED(by); + UNUSED(bs); + assert(n % QK_MXFP4 == 0); + static_assert(QK_MXFP4 == QK8_0, "QK_MXFP4 and QK8_0 must be the same"); + + const block_mxfp4 * GGML_RESTRICT x = vx; + const block_q8_0 * GGML_RESTRICT y = vy; + + const int nb = n / QK_MXFP4; + + int ib = 0; + float sumf = 0; + + for (; ib < nb; ++ib) { + const float d = GGML_CPU_FP16_TO_FP32(y[ib].d)*GGML_E8M0_TO_FP32_HALF(x[ib].e); + + int sumi1 = 0; + int sumi2 = 0; + for (int j = 0; j < QK_MXFP4/2; ++j) { + sumi1 += y[ib].qs[j + 0] * kvalues_mxfp4[x[ib].qs[j] & 0xf]; + sumi2 += y[ib].qs[j + QK_MXFP4/2] * kvalues_mxfp4[x[ib].qs[j] >> 4]; + } + sumf += d * (sumi1 + sumi2); + } + *s = sumf; +} + void ggml_vec_dot_q5_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc) { const int qk = QK8_0; const int nb = n / qk; diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/quants.h 6641+dfsg-2/ggml/src/ggml-cpu/quants.h --- 5882+dfsg-2/ggml/src/ggml-cpu/quants.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/quants.h 2025-09-30 07:36:33.000000000 +0000 @@ -19,6 +19,8 @@ void quantize_row_q5_1(const float * GGM void quantize_row_q8_0(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q8_1(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); +void quantize_row_mxfp4(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); + void quantize_row_q2_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q3_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); void quantize_row_q4_K(const float * GGML_RESTRICT x, void * GGML_RESTRICT y, int64_t k); @@ -39,6 +41,8 @@ void ggml_vec_dot_q5_0_q8_0(int n, float void ggml_vec_dot_q5_1_q8_1(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q8_0_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); +void ggml_vec_dot_mxfp4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_q2_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q3_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_K_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); @@ -67,8 +71,12 @@ void ggml_vec_dot_q4_1_q8_1_generic(int void ggml_vec_dot_q5_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q5_1_q8_1_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q8_0_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + +void ggml_vec_dot_mxfp4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_tq1_0_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_tq2_0_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); + void ggml_vec_dot_q2_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q3_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); void ggml_vec_dot_q4_K_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, size_t bx, const void * GGML_RESTRICT vy, size_t by, int nrc); diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/repack.cpp 6641+dfsg-2/ggml/src/ggml-cpu/repack.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/repack.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/repack.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -14,7 +14,6 @@ #include #include #include -#include // for qsort #include // for GGML_ASSERT #include "repack.h" @@ -207,8 +206,9 @@ void ggml_gemv_q4_0_4x4_q8_0_generic(int const int ncols_interleaved = 4; const int blocklen = 4; - assert (n % qk == 0); - assert (nc % ncols_interleaved == 0); + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); UNUSED(s); UNUSED(bs); @@ -308,30 +308,28 @@ void ggml_gemv_q4_0_8x8_q8_0_generic(int UNUSED(ncols_interleaved); UNUSED(blocklen); - { - float sumf[8]; - int sumi; + float sumf[8]; + int sumi; - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_q4_0x8 * b_ptr = (const block_q4_0x8 *) vx + (x * nb); - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); - const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] << 4); + const int v1 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0xF0); + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])) >> 4; } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); } } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } } @@ -413,11 +411,11 @@ void ggml_gemv_q4_K_8x8_q8_K_generic(int } } -void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { - const int qk = QK8_0; +void ggml_gemv_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; const int nb = n / qk; - const int ncols_interleaved = 4; - const int blocklen = 4; + const int ncols_interleaved = 8; + const int blocklen = 8; assert (n % qk == 0); assert (nc % ncols_interleaved == 0); @@ -432,30 +430,136 @@ void ggml_gemv_iq4_nl_4x4_q8_0_generic(i UNUSED(ncols_interleaved); UNUSED(blocklen); - { - float sumf[4]; - int sumi; + float sumf[8]; + float sum_minf[8]; + int sumi1,sumi2,sumi3,sumi4; + int sumi; - const block_q8_0 * a_ptr = (const block_q8_0 *) vy; - for (int x = 0; x < nc / ncols_interleaved; x++) { - const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); + const block_q8_K * a_ptr = (const block_q8_K *)vy; + for(int x = 0; x < nc / ncols_interleaved; x++) { + const block_q2_Kx8 * b_ptr = (const block_q2_Kx8 *) vx + (x * nb); + for (int j = 0; j < ncols_interleaved; j++) { + sumf[j] = 0.0; + sum_minf[j] = 0.0; + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (4 * blocklen)); k++) { + const uint8_t *scales_0 = b_ptr[l].scales + (k / 4) * 64 ; + const uint8_t *scales_1 = b_ptr[l].scales + (k / 4) * 64 + 16; + const uint8_t *scales_2 = b_ptr[l].scales + (k / 4) * 64 + 32; + const uint8_t *scales_3 = b_ptr[l].scales + (k / 4) * 64 + 48; + for (int j = 0; j < ncols_interleaved; j++) { + sumi1 = 0; + sumi2 = 0; + sumi3 = 0; + sumi4 = 0; + sumi = 0; + int offset = ((k / 2) % 2) + j * 2; + for (int i = 0; i < blocklen; ++i){ + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 3); + const int v1 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 2 ) & 3); + const int v2 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4 ) & 3); + const int v3 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 6 ) & 3); + sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i]); + sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 32]); + sumi3 = (v2 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 64]); + sumi4 = (v3 * a_ptr[l].qs[(k >> 2) * 128 + (k % 4) * blocklen + i + 96]); + + sumi1 = sumi1 * (scales_0[offset] & 0xF); + sumi2 = sumi2 * (scales_1[offset] & 0xF); + sumi3 = sumi3 * (scales_2[offset] & 0xF); + sumi4 = sumi4 * (scales_3[offset] & 0xF); + sumi += sumi1 + sumi2 + sumi3 + sumi4; + } + sumf[j] += sumi * GGML_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d; + } + } + for(int sb = 0; sb < 8; sb++) { + const uint8_t *mins = b_ptr[l].scales + sb * 16; + for(int j = 0; j < ncols_interleaved; j++){ + sum_minf[j] += ((mins[j * 2] >> 4) * a_ptr[l].bsums[sb * 2] + (mins[(j * 2)+ 1] >> 4) * a_ptr[l].bsums[sb * 2 + 1]) * GGML_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d; + } + } + } + for (int j = 0; j < ncols_interleaved; j++) { + s[x * ncols_interleaved + j] = sumf[j] - sum_minf[j]; + } + } +} - for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; - for (int l = 0; l < nb; l++) { - for (int k = 0; k < (qk / (2 * blocklen)); k++) { - for (int j = 0; j < ncols_interleaved; j++) { - sumi = 0; - for (int i = 0; i < blocklen; ++i) { - const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; - const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; - sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); - } - sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); +void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 4; + const int blocklen = 4; + + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); + + UNUSED(bs); + UNUSED(nr); + + float sumf[4]; + int sumi; + + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx4 * b_ptr = (const block_iq4_nlx4 *) vx + (x * nb); + + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); } } - for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; + } +} + +void ggml_gemv_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert(nr == 1); + assert(n % qk == 0); + assert(nc % ncols_interleaved == 0); + + UNUSED(bs); + UNUSED(nr); + + float sumf[8]; + int sumi; + + const block_q8_0 * a_ptr = (const block_q8_0 *) vy; + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx8 * b_ptr = (const block_iq4_nlx8 *) vx + (x * nb); + + for (int j = 0; j < ncols_interleaved; j++) sumf[j] = 0.0; + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * blocklen + i]) + (v1 * a_ptr[l].qs[k * blocklen + i + qk / 2])); + } + sumf[j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d); + } + } + } + for (int j = 0; j < ncols_interleaved; j++) s[x * ncols_interleaved + j] = sumf[j]; } } @@ -712,6 +816,97 @@ void ggml_gemm_q4_K_8x8_q8_K_generic(int } } +void ggml_gemm_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK_K; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert (n % qk == 0); + assert (nr % 4 == 0); + assert (nc % ncols_interleaved == 0); + + UNUSED(s); + UNUSED(bs); + UNUSED(vx); + UNUSED(vy); + UNUSED(nr); + UNUSED(nc); + UNUSED(nb); + UNUSED(ncols_interleaved); + UNUSED(blocklen); + + float sumf[4][8]; + float sum_minf[4][8]; + int sumi1, sumi2, sumi3, sumi4; + int sumi; + + for (int y = 0; y < nr / 4; y++) { + const block_q8_Kx4 * a_ptr = (const block_q8_Kx4 *) vy + (y * nb); + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_q2_Kx8 * b_ptr = (const block_q2_Kx8 *) vx + (x * nb); + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumf[m][j] = 0.0; + sum_minf[m][j] = 0.0; + } + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (4 * blocklen)); k++) { + + const uint8_t *scales_0 = b_ptr[l].scales + (k / 4) * 64 ; + const uint8_t *scales_1 = b_ptr[l].scales + (k / 4) * 64 + 16; + const uint8_t *scales_2 = b_ptr[l].scales + (k / 4) * 64 + 32; + const uint8_t *scales_3 = b_ptr[l].scales + (k / 4) * 64 + 48; + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi1 = 0; + sumi2 = 0; + sumi3 = 0; + sumi4 = 0; + sumi = 0; + int offset = ((k / 2) % 2) + j * 2; + for (int i = 0; i < blocklen; ++i){ + const int v0 = (int8_t) (b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 3); + const int v1 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 2 ) & 3); + const int v2 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4 ) & 3); + const int v3 = (int8_t) ((b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 6 ) & 3); + sumi1 = (v0 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i]); + sumi2 = (v1 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 128]); + sumi3 = (v2 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 256]); + sumi4 = (v3 * a_ptr[l].qs[(k >> 2) * 512 + (k % 4) * 4 * blocklen + m * blocklen + i + 384]); + sumi1 = sumi1 * (scales_0[offset] & 0xF); + sumi2 = sumi2 * (scales_1[offset] & 0xF); + sumi3 = sumi3 * (scales_2[offset] & 0xF); + sumi4 = sumi4 * (scales_3[offset] & 0xF); + sumi += sumi1 + sumi2 + sumi3 + sumi4; + } + sumf[m][j] += sumi * GGML_FP16_TO_FP32(b_ptr[l].d[j]) * a_ptr[l].d[m]; + } + } + } + for(int sb = 0; sb < 8; sb++) { + const uint8_t *mins = b_ptr[l].scales + sb * 16; + for(int m = 0; m < 4; m++) { + const int16_t *bsums = a_ptr[l].bsums + (sb * 8) + (m * 4) - ((sb % 2) * 6); + for(int j = 0; j < ncols_interleaved; j++) { + int mins_prod = ((mins[j * 2] >> 4) * bsums[0] + (mins[(j * 2)+ 1] >> 4) * bsums[1]); + sum_minf[m][j] += (mins_prod) * GGML_FP16_TO_FP32(b_ptr[l].dmin[j]) * a_ptr[l].d[m]; + } + } + } + } + + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j] - sum_minf[m][j]; + } + } + } + } +} + + void ggml_gemm_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { const int qk = QK8_0; const int nb = n / qk; @@ -768,6 +963,50 @@ void ggml_gemm_iq4_nl_4x4_q8_0_generic(i } } +void ggml_gemm_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc) { + const int qk = QK8_0; + const int nb = n / qk; + const int ncols_interleaved = 8; + const int blocklen = 8; + + assert(n % qk == 0); + assert(nr % 4 == 0); + assert(nc % ncols_interleaved == 0); + + float sumf[4][8]; + int sumi; + + for (int y = 0; y < nr / 4; y++) { + const block_q8_0x4 * a_ptr = (const block_q8_0x4 *) vy + (y * nb); + for (int x = 0; x < nc / ncols_interleaved; x++) { + const block_iq4_nlx8 * b_ptr = (const block_iq4_nlx8 *) vx + (x * nb); + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) sumf[m][j] = 0.0; + } + for (int l = 0; l < nb; l++) { + for (int k = 0; k < (qk / (2 * blocklen)); k++) { + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) { + sumi = 0; + for (int i = 0; i < blocklen; ++i) { + const int v0 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] & 0x0F]; + const int v1 = kvalues_iq4nl[b_ptr[l].qs[k * ncols_interleaved * blocklen + j * blocklen + i] >> 4]; + sumi += ((v0 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i]) + + (v1 * a_ptr[l].qs[k * 4 * blocklen + m * blocklen + i + qk / 2 * 4])); + } + sumf[m][j] += sumi * GGML_CPU_FP16_TO_FP32(b_ptr[l].d[j]) * GGML_CPU_FP16_TO_FP32(a_ptr[l].d[m]); + } + } + } + } + for (int m = 0; m < 4; m++) { + for (int j = 0; j < ncols_interleaved; j++) + s[(y * 4 + m) * bs + x * ncols_interleaved + j] = sumf[m][j]; + } + } + } +} + } // extern "C" static block_q4_0x4 make_block_q4_0x4(block_q4_0 * in, unsigned int blck_size_interleave) { @@ -915,6 +1154,50 @@ static block_q4_Kx8 make_block_q4_Kx8(bl return out; } +static block_q2_Kx8 make_block_q2_Kx8(block_q2_K * in, unsigned int blck_size_interleave) { + block_q2_Kx8 out; + + // Delta(scale) and dmin values of the eight Q2_K structures are copied onto the output interleaved structure + for (int i = 0; i < 8; i++) { + out.d[i] = in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.d; + } + + for (int i = 0; i < 8; i++) { + out.dmin[i] = in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.dmin; + } + + const int end = QK_K * 2 / blck_size_interleave; + + // Interleave Q2_K quants by taking 8 bytes at a time + for (int i = 0; i < end; ++i) { + int src_id = i % 8; + int src_offset = (i / 8) * blck_size_interleave; + int dst_offset = i * blck_size_interleave; + + uint64_t elems; + memcpy(&elems, &in[src_id].qs[src_offset], sizeof(uint64_t)); + memcpy(&out.qs[dst_offset], &elems, sizeof(uint64_t)); + } + + // The below logic is designed so as to unpack and rearrange scales and mins values in Q2_K + // Currently the Q2_K structure has 16 scales and 16 mins packed in 16 bytes ( 4 bits for each value) + // The output Q2_Kx8 structure has 128 bytes for storing scales and mins + // Every 16 byte is packed such that it contains scales and mins for corresponding sub blocks from Q2_K structure + // For eg - First 16 bytes contains 16 scales and 16 mins - each of first and second sub blocks from different Q2_K structures + + for(int i = 0; i < 128; i++){ + + // Index for selecting which q2k super block + int src1 = (i % 16) / 2; + // Index for selecting scale + int src2 = ((i / 16) * 2) + (i % 2); + + out.scales[i] = in[src1].scales[src2]; + } + return out; + +} + static int repack_q4_0_to_q4_0_4_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_Q4_0); GGML_ASSERT(interleave_block == 4 || interleave_block == 8); @@ -976,6 +1259,37 @@ static int repack_q4_K_to_q4_K_8_bl(stru GGML_UNUSED(data_size); } +static int repack_q2_K_to_q2_K_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_Q2_K); + GGML_ASSERT(interleave_block == 8); + constexpr int nrows_interleaved = 8; + + block_q2_Kx8 * dst = (block_q2_Kx8*)t->data; + const block_q2_K * src = (const block_q2_K*) data; + block_q2_K dst_tmp[8]; + int nrow = ggml_nrows(t); + int nblocks = t->ne[0] / QK_K; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_q2_K)); + + if (t->ne[1] % nrows_interleaved != 0 || t->ne[0] % 8 != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++ ) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_q2_Kx8(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + static int repack_q4_0_to_q4_0_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_Q4_0); GGML_ASSERT(interleave_block == 8); @@ -1044,15 +1358,16 @@ static block_iq4_nlx4 make_block_iq4_nlx static int repack_iq4_nl_to_iq4_nl_4_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { GGML_ASSERT(t->type == GGML_TYPE_IQ4_NL); - //GGML_ASSERT(interleave_block == 4 || interleave_block == 8); GGML_ASSERT(interleave_block == 4); - block_iq4_nlx4 * dst = (block_iq4_nlx4 *)t->data; - const block_iq4_nl * src = (const block_iq4_nl *)data; + const block_iq4_nl * src = (const block_iq4_nl *)data; + block_iq4_nlx4 * dst = ( block_iq4_nlx4 *)t->data; + block_iq4_nl dst_tmp[4]; + int nrow = ggml_nrows(t); int nrows_interleaved = 4; - int nblocks = t->ne[0] / QK4_0; + int nblocks = t->ne[0] / QK4_NL; GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_iq4_nl)); @@ -1074,6 +1389,63 @@ static int repack_iq4_nl_to_iq4_nl_4_bl( GGML_UNUSED(data_size); } +static block_iq4_nlx8 make_block_iq4_nlx8(block_iq4_nl * in, unsigned int blck_size_interleave) { + block_iq4_nlx8 out; + + for (int i = 0; i < 8; i++) { + out.d[i] = in[i].d; + } + + const int end = QK4_NL * 4 / blck_size_interleave; + + if (blck_size_interleave == 8) { + for (int i = 0; i < end; ++i) { + int src_id = i % 8; + int src_offset = (i / 8) * blck_size_interleave; + int dst_offset = i * blck_size_interleave; + + memcpy(&out.qs[dst_offset], &in[src_id].qs[src_offset], sizeof(uint64_t)); + } + } else { + GGML_ASSERT(false); + } + + return out; +} + +static int repack_iq4_nl_to_iq4_nl_8_bl(struct ggml_tensor * t, int interleave_block, const void * GGML_RESTRICT data, size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_IQ4_NL); + GGML_ASSERT(interleave_block == 8); + + const block_iq4_nl * src = (const block_iq4_nl *)data; + block_iq4_nlx8 * dst = ( block_iq4_nlx8 *)t->data; + + block_iq4_nl dst_tmp[8]; + + int nrow = ggml_nrows(t); + int nrows_interleaved = 8; + int nblocks = t->ne[0] / QK4_NL; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_iq4_nl)); + + if (t->ne[1] % nrows_interleaved != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_iq4_nlx8(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + namespace ggml::cpu::repack { // repack template @@ -1096,6 +1468,10 @@ template <> int repack return repack_q4_K_to_q4_K_8_bl(t, 8, data, data_size); } +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_q2_K_to_q2_K_8_bl(t, 8, data, data_size); +} + template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { return repack_iq4_nl_to_iq4_nl_4_bl(t, 4, data, data_size); } @@ -1105,6 +1481,10 @@ template <> int repack int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_iq4_nl_to_iq4_nl_8_bl(t, 8, data, data_size); +} + // gemv template void gemv(int, float *, size_t, const void *, const void *, int, int); @@ -1125,10 +1505,18 @@ template <> void gemv void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemv_q2_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); +} + template <> void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { ggml_gemv_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); } +template <> void gemv(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemv_iq4_nl_8x8_q8_0(n, s, bs, vx, vy, nr, nc); +} + // gemm template void gemm(int, float *, size_t, const void *, const void *, int, int); @@ -1149,10 +1537,18 @@ template <> void gemm void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemm_q2_K_8x8_q8_K(n, s, bs, vx, vy, nr, nc); +} + template <> void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { ggml_gemm_iq4_nl_4x4_q8_0(n, s, bs, vx, vy, nr, nc); } +template <> void gemm(int n, float * s, size_t bs, const void * vx, const void * vy, int nr, int nc) { + ggml_gemm_iq4_nl_8x8_q8_0(n, s, bs, vx, vy, nr, nc); +} + class tensor_traits_base : public ggml::cpu::tensor_traits { public: virtual int repack(struct ggml_tensor * t, const void * data, size_t data_size) = 0; @@ -1422,8 +1818,12 @@ static const ggml::cpu::tensor_traits * static const ggml::cpu::repack::tensor_traits q4_0_8x8_q8_0; static const ggml::cpu::repack::tensor_traits q4_K_8x8_q8_K; + // instance for Q2 + static const ggml::cpu::repack::tensor_traits q2_K_8x8_q8_K; + // instance for IQ4 static const ggml::cpu::repack::tensor_traits iq4_nl_4x4_q8_0; + static const ggml::cpu::repack::tensor_traits iq4_nl_8x8_q8_0; if (cur->type == GGML_TYPE_Q4_0) { if (ggml_cpu_has_avx2() || (ggml_cpu_has_sve() && ggml_cpu_has_matmul_int8() && ggml_cpu_get_sve_cnt() == QK8_0)) { @@ -1447,7 +1847,18 @@ static const ggml::cpu::tensor_traits * return &q4_K_8x8_q8_K; } } + } else if (cur->type == GGML_TYPE_Q2_K) { + if (ggml_cpu_has_avx512()) { + if (cur->ne[1] % 8 == 0) { + return &q2_K_8x8_q8_K; + } + } } else if (cur->type == GGML_TYPE_IQ4_NL) { + if (ggml_cpu_has_avx2()) { + if (cur->ne[1] % 8 == 0) { + return &iq4_nl_8x8_q8_0; + } + } if (ggml_cpu_has_neon() && ggml_cpu_has_dotprod()) { if (cur->ne[1] % 4 == 0) { return &iq4_nl_4x4_q8_0; diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/repack.h 6641+dfsg-2/ggml/src/ggml-cpu/repack.h --- 5882+dfsg-2/ggml/src/ggml-cpu/repack.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/repack.h 2025-09-30 07:36:33.000000000 +0000 @@ -44,7 +44,14 @@ struct block_q4_Kx8 { }; static_assert(sizeof(block_q4_Kx8) == sizeof(ggml_half) * 16 + K_SCALE_SIZE * 8 + QK_K * 4, "wrong q4_K block size/padding"); +struct block_q2_Kx8 { + ggml_half d[8]; // super-block scale for quantized scales + ggml_half dmin[8]; // super-block scale for quantized mins + uint8_t scales[128]; // scales and mins, quantized with 4 bits + uint8_t qs[512]; // 2--bit quants +}; +static_assert(sizeof(block_q2_Kx8) == sizeof(ggml_half) * 16 + QK_K/2 + QK_K * 2, "wrong q2_K block size/padding"); struct block_q8_Kx4 { float d[4]; // delta int8_t qs[QK_K * 4]; // quants @@ -60,6 +67,13 @@ struct block_iq4_nlx4 { static_assert(sizeof(block_iq4_nlx4) == 4 * sizeof(ggml_half) + QK4_NL * 2, "wrong iq4_nlx4 block size/padding"); +struct block_iq4_nlx8 { + ggml_half d[8]; // deltas for 8 iq4_nl blocks + uint8_t qs[QK4_NL * 4]; // nibbles / quants for 8 iq4_nl blocks +}; + +static_assert(sizeof(block_iq4_nlx8) == 8 * sizeof(ggml_half) + QK4_NL * 4, "wrong iq4_nlx8 block size/padding"); + #if defined(__cplusplus) extern "C" { #endif @@ -71,12 +85,16 @@ void ggml_gemv_q4_0_4x4_q8_0(int n, floa void ggml_gemv_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_q2_K_8x8_q8_K(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_iq4_nl_4x4_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_iq4_nl_8x8_q8_0(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); // Native implementations void ggml_quantize_mat_q8_0_4x4_generic(const float * GGML_RESTRICT x, void * GGML_RESTRICT vy, int64_t k); @@ -86,12 +104,16 @@ void ggml_gemv_q4_0_4x4_q8_0_generic(int void ggml_gemv_q4_0_4x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_0_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemv_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemv_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_4x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_0_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_q4_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_q2_K_8x8_q8_K_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); void ggml_gemm_iq4_nl_4x4_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); +void ggml_gemm_iq4_nl_8x8_q8_0_generic(int n, float * GGML_RESTRICT s, size_t bs, const void * GGML_RESTRICT vx, const void * GGML_RESTRICT vy, int nr, int nc); #if defined(__cplusplus) } // extern "C" diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/simd-mappings.h 6641+dfsg-2/ggml/src/ggml-cpu/simd-mappings.h --- 5882+dfsg-2/ggml/src/ggml-cpu/simd-mappings.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/simd-mappings.h 2025-09-30 07:36:33.000000000 +0000 @@ -18,6 +18,10 @@ #include #endif +#if defined(__riscv_v_intrinsic) +#include +#endif + #ifdef __cplusplus extern "C" { #endif @@ -94,24 +98,15 @@ extern "C" { } #elif defined(__riscv) && defined(__riscv_zfhmin) static inline float riscv_compute_fp16_to_fp32(ggml_fp16_t h) { - float f; - __asm__( - "fmv.h.x %[f], %[h]\n\t" - "fcvt.s.h %[f], %[f]" - : [f] "=&f" (f) - : [h] "r" (h) - ); - return f; + _Float16 hf; + memcpy(&hf, &h, sizeof(ggml_fp16_t)); + return hf; } static inline ggml_fp16_t riscv_compute_fp32_to_fp16(float f) { ggml_fp16_t res; - __asm__( - "fcvt.h.s %[f], %[f]\n\t" - "fmv.x.h %[h], %[f]" - : [h] "=&r" (res) - : [f] "f" (f) - ); + _Float16 hf = (_Float16)f; + memcpy(&res, &hf, sizeof(ggml_fp16_t)); return res; } @@ -119,26 +114,6 @@ extern "C" { #define GGML_CPU_COMPUTE_FP32_TO_FP16(x) riscv_compute_fp32_to_fp16(x) #define GGML_CPU_FP16_TO_FP32(x) GGML_CPU_COMPUTE_FP16_TO_FP32(x) #define GGML_CPU_FP32_TO_FP16(x) GGML_CPU_COMPUTE_FP32_TO_FP16(x) -#elif defined(__NNPA__) - #define GGML_CPU_COMPUTE_FP16_TO_FP32(x) nnpa_compute_fp16_to_fp32(x) - #define GGML_CPU_COMPUTE_FP32_TO_FP16(x) nnpa_compute_fp32_to_fp16(x) - - #define GGML_CPU_FP16_TO_FP32(x) GGML_CPU_COMPUTE_FP16_TO_FP32(x) - #define GGML_CPU_FP32_TO_FP16(x) GGML_CPU_COMPUTE_FP32_TO_FP16(x) - - static inline float nnpa_compute_fp16_to_fp32(ggml_fp16_t h) { - uint16x8_t v_h = vec_splats(h); - uint16x8_t v_hd = vec_convert_from_fp16(v_h, 0); - return vec_extend_to_fp32_hi(v_hd, 0)[0]; - } - - static inline ggml_fp16_t nnpa_compute_fp32_to_fp16(float f) { - float32x4_t v_f = vec_splats(f); - float32x4_t v_zero = vec_splats(0.0f); - uint16x8_t v_hd = vec_round_from_fp32(v_f, v_zero, 0); - uint16x8_t v_h = vec_convert_to_fp16(v_hd, 0); - return vec_extract(v_h, 0); - } #endif // precomputed f32 table for f16 (256 KB) @@ -220,6 +195,47 @@ inline static float ggml_lookup_fp16_to_ #define GGML_F32_VEC_MUL GGML_F32xt_MUL #define GGML_F32_VEC_REDUCE GGML_F32xt_REDUCE +// F16 SVE +#define DEFAULT_PG32 svptrue_b32() +#define DEFAULT_PG16 svptrue_b16() + +#define GGML_F32Cxt svfloat16_t +#define GGML_F32Cxt_ZERO svdup_n_f16(0.0f) +#define GGML_F32Cxt_SET1(x) svdup_n_f16(x) +#define GGML_F32Cxt_LOAD(p) svld1_f16(DEFAULT_PG16, (const __fp16 *)(p)) +#define GGML_F32Cxt_STORE(dst_ptr, src_vec) svst1_f16(DEFAULT_PG16, (__fp16 *)(dst_ptr), (src_vec)) + +#define GGML_F32Cxt_FMA_IMPL(pg, a, b, c) svmad_f16_x(pg, b, c, a) +#define GGML_F32Cxt_FMA(...) GGML_F32Cxt_FMA_IMPL(DEFAULT_PG16, __VA_ARGS__) +#define GGML_F32Cxt_ADD_IMPL(pg, a, b) svadd_f16_x(pg, a, b) +#define GGML_F32Cxt_ADD(...) GGML_F32Cxt_ADD_IMPL(DEFAULT_PG16, __VA_ARGS__) +#define GGML_F32Cxt_MUL_IMPL(pg, a, b) svmul_f16_x(pg, a, b) +#define GGML_F32Cxt_MUL(...) GGML_F32Cxt_MUL_IMPL(DEFAULT_PG16, __VA_ARGS__) +#define GGML_F32Cxt_REDUCE GGML_F16xt_REDUCE_MIXED + +#define GGML_F16x_VEC GGML_F32Cxt +#define GGML_F16x_VEC_ZERO GGML_F32Cxt_ZERO +#define GGML_F16x_VEC_SET1 GGML_F32Cxt_SET1 +#define GGML_F16x_VEC_LOAD(p, i) GGML_F32Cxt_LOAD(p) +#define GGML_F16x_VEC_STORE(p, r, i) GGML_F32Cxt_STORE((__fp16 *)(p), r) +#define GGML_F16x_VEC_FMA GGML_F32Cxt_FMA +#define GGML_F16x_VEC_ADD GGML_F32Cxt_ADD +#define GGML_F16x_VEC_MUL GGML_F32Cxt_MUL +#define GGML_F16x_VEC_REDUCE GGML_F32Cxt_REDUCE + +#define GGML_F16xt_REDUCE_ONE_IMPL(pg, a) svaddv_f16(pg, a) +#define GGML_F16xt_REDUCE_ONE(...) GGML_F16xt_REDUCE_ONE_IMPL(DEFAULT_PG16, __VA_ARGS__) + +#define GGML_F16xt_REDUCE_MIXED_IMPL(pg16, res, sum1, sum2, sum3, sum4) \ +{ \ + sum1 = svadd_f16_x(pg16, sum1, sum2); \ + sum3 = svadd_f16_x(pg16, sum3, sum4); \ + sum1 = svadd_f16_x(pg16, sum1, sum3); \ + __fp16 sum_f16 = svaddv_f16(pg16, sum1); \ + (res) = (ggml_float) sum_f16; \ +} +#define GGML_F16xt_REDUCE_MIXED(...) GGML_F16xt_REDUCE_MIXED_IMPL(DEFAULT_PG16, __VA_ARGS__) + // F16 NEON #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) @@ -982,9 +998,9 @@ static inline void __lasx_f32cx8_store(g #define GGML_F32_EPR 4 #define GGML_F32x4 __m128 -#define GGML_F32x4_ZERO __lsx_vldi(0) -#define GGML_F32x4_SET1(x) __lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0) -#define GGML_F32x4_LOAD(x) __lsx_vld((x), 0) +#define GGML_F32x4_ZERO (__m128)__lsx_vldi(0) +#define GGML_F32x4_SET1(x) (__m128)__lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0) +#define GGML_F32x4_LOAD(x) (__m128)__lsx_vld((x), 0) #define GGML_F32x4_STORE(x, y) __lsx_vst(y, x, 0) #define GGML_F32x4_FMA(a, b, c) __lsx_vfmadd_s(b, c, a) #define GGML_F32x4_ADD __lsx_vfadd_s @@ -1006,7 +1022,7 @@ static inline void __lasx_f32cx8_store(g __m128i tmp = __lsx_vsrli_d((__m128i) x[0], 32); \ tmp = (__m128i) __lsx_vfadd_s((__m128) tmp, x[0]); \ tmp = __lsx_vpickev_w(__lsx_vldi(0), tmp); \ - const __m128 t0 = __lsx_vshuf4i_w(tmp, 0x88); \ + const __m128 t0 = (__m128)__lsx_vshuf4i_w(tmp, 0x88); \ tmp = __lsx_vsrli_d((__m128i) t0, 32); \ tmp = (__m128i) __lsx_vfadd_s((__m128) tmp, t0); \ tmp = __lsx_vpickev_w(__lsx_vldi(0), tmp); \ @@ -1036,7 +1052,7 @@ static inline __m128 __lsx_f16x4_load(co tmp[2] = GGML_CPU_FP16_TO_FP32(x[2]); tmp[3] = GGML_CPU_FP16_TO_FP32(x[3]); - return __lsx_vld(tmp, 0); + return (__m128)__lsx_vld(tmp, 0); } static inline void __lsx_f16x4_store(ggml_fp16_t * x, __m128 y) { @@ -1051,9 +1067,9 @@ static inline void __lsx_f16x4_store(ggm } #define GGML_F32Cx4 __m128 -#define GGML_F32Cx4_ZERO __lsx_vldi(0) -#define GGML_F32Cx4_SET1(x) __lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0) -#define GGML_F32Cx4_LOAD(x) __lsx_f16x4_load(x) +#define GGML_F32Cx4_ZERO (__m128)__lsx_vldi(0) +#define GGML_F32Cx4_SET1(x) (__m128)__lsx_vinsgr2vr_w(__lsx_vldi(0),(x), 0) +#define GGML_F32Cx4_LOAD(x) (__m128)__lsx_f16x4_load(x) #define GGML_F32Cx4_STORE(x, y) __lsx_f16x4_store(x, y) #define GGML_F32Cx4_FMA GGML_F32x4_FMA #define GGML_F32Cx4_ADD __lsx_vfadd_s @@ -1120,11 +1136,6 @@ static inline void __lsx_f16x4_store(ggm #define GGML_F16_EPR GGML_F32_EPR static inline float32x4_t __lzs_f16cx4_load(const ggml_fp16_t * x) { -#if defined(__NNPA__) - uint16x8_t v_x = vec_xl(0, (const ggml_fp16_t *)x); - uint16x8_t v_xd = vec_convert_from_fp16(v_x, 0); - return vec_extend_to_fp32_hi(v_xd, 0); -#else float tmp[4]; for (int i = 0; i < 4; i++) { @@ -1134,20 +1145,9 @@ static inline float32x4_t __lzs_f16cx4_l // note: keep type-cast here to prevent compiler bugs // see: https://github.com/ggml-org/llama.cpp/issues/12846 return vec_xl(0, (const float *)(tmp)); -#endif } static inline void __lzs_f16cx4_store(ggml_fp16_t * x, float32x4_t v_y) { -#if defined(__NNPA__) - float32x4_t v_zero = vec_splats(0.0f); - uint16x8_t v_xd = vec_round_from_fp32(v_y, v_zero, 0); - uint16x8_t v_x = vec_convert_to_fp16(v_xd, 0); - - x[0] = vec_extract(v_x, 0); - x[1] = vec_extract(v_x, 1); - x[2] = vec_extract(v_x, 2); - x[3] = vec_extract(v_x, 3); -#else float arr[4]; // note: keep type-cast here to prevent compiler bugs @@ -1157,7 +1157,6 @@ static inline void __lzs_f16cx4_store(gg for (int i = 0; i < 4; i++) { x[i] = GGML_CPU_FP32_TO_FP16(arr[i]); } -#endif } #define GGML_F16_VEC GGML_F32x4 @@ -1170,6 +1169,36 @@ static inline void __lzs_f16cx4_store(gg #define GGML_F16_VEC_MUL GGML_F32x4_MUL #define GGML_F16_VEC_REDUCE GGML_F32x4_REDUCE +#elif defined(__riscv_v_intrinsic) + +// compatible with vlen >= 128 + +#define GGML_SIMD + +// F32 + +#define GGML_F32_STEP 16 +#define GGML_F32_EPR 4 + +#define GGML_F32x4 vfloat32m1_t +#define GGML_F32x4_ZERO __riscv_vfmv_v_f_f32m1(0.0f, GGML_F32_EPR) +#define GGML_F32x4_SET1(x) __riscv_vfmv_v_f_f32m1(x, GGML_F32_EPR) +#define GGML_F32x4_LOAD(x) __riscv_vle32_v_f32m1(x, GGML_F32_EPR) +#define GGML_F32x4_STORE(b, v) __riscv_vse32_v_f32m1(b, v, GGML_F32_EPR) +#define GGML_F32x4_FMA(a, b, c) __riscv_vfmacc_vv_f32m1(a, b, c, GGML_F32_EPR) +#define GGML_F32x4_ADD(a, b) __riscv_vfadd_vv_f32m1(a, b, GGML_F32_EPR) +#define GGML_F32x4_MUL(a, b) __riscv_vfmul_vv_f32m1(a, b, GGML_F32_EPR) + +#define GGML_F32_VEC GGML_F32x4 +#define GGML_F32_VEC_ZERO GGML_F32x4_ZERO +#define GGML_F32_VEC_SET1 GGML_F32x4_SET1 +#define GGML_F32_VEC_LOAD GGML_F32x4_LOAD +#define GGML_F32_VEC_STORE GGML_F32x4_STORE +#define GGML_F32_VEC_FMA GGML_F32x4_FMA +#define GGML_F32_VEC_ADD GGML_F32x4_ADD +#define GGML_F32_VEC_MUL GGML_F32x4_MUL +#define GGML_F32_VEC_REDUCE GGML_F32x4_REDUCE + #endif // GGML_F32_ARR / GGML_F16_ARR diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.cpp 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,1024 @@ +#define GGML_COMMON_IMPL_CPP +#define GGML_COMMON_DECL_CPP + +#include "ime.h" + +#include "ggml-backend-impl.h" +#include "ggml-common.h" +#include "ggml-cpu.h" +#include "ime_kernels.h" +#include "traits.h" + +#include +#include +#include +#include // for GGML_ASSERT +#include +#include + +// clang-format off +#if defined(__riscv) + +#if !defined(__riscv_v) || !defined(__riscv_v_intrinsic) +#error "riscv v extension or v_intrinsic not enabled" +#else +#include +#endif + +#if !defined(__riscv_zfh) +#error "riscv zfh extension not enabled" +#endif + +#if defined(RISCV64_SPACEMIT_IME1) +#else +#error "RISCV64_SPACEMIT_IME1 not defined" +#endif + +#else + +#error "riscv not enabled in this build" + +#endif + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Woverlength-strings" +#pragma GCC diagnostic ignored "-Wcast-qual" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#if defined(RISCV64_SPACEMIT_IME1) +#define QGEMM_STRIDEN_THREAD_ALIGN 16 +#else +#define QGEMM_STRIDEN_THREAD_ALIGN 32 +#endif + +// clang-format on + +struct qnbitgemm_spacemit_ime_args { + const float * a_ptr = nullptr; + size_t lda = 0; + const std::byte * packed_quant_b_data = nullptr; + const float * quant_b_scale = nullptr; + const void * quant_b_zp = nullptr; + const float * quant_b_blksum = nullptr; + const float * bias = nullptr; + float * c_ptr = nullptr; + size_t ldc = 0; +}; + +constexpr size_t div_round_up(size_t up, size_t down) { + return (up + down - 1) / down; +} + +constexpr size_t q8_blk_size(size_t blk_len) { + const size_t blk_size = sizeof(float) + blk_len * sizeof(int8_t); + // Currently, the strictest alignment requirement of a block is for a float. + // Ensure contiguous blocks are suitably aligned. + assert(blk_size % alignof(float) == 0); + return blk_size; +} + +namespace ggml::cpu::riscv64_spacemit { + +const int num_ai_cores = std::thread::hardware_concurrency() / 2; + +} // namespace ggml::cpu::riscv64_spacemit + +static void sqnbitgemm_spacemit_ime_i8i4(const size_t blk_len, + const size_t gemm_k, + const qnbitgemm_spacemit_ime_args * gemm_args, + void * const per_gemm_ws, + const size_t m_start, + const size_t m_count, + const size_t n_start, + const size_t n_count) { + constexpr size_t scale_stride = sizeof(uint16_t); + constexpr size_t blk_bitwidth = 4; + + const size_t k_blks = div_round_up(gemm_k, blk_len); + + const size_t lda = k_blks * q8_blk_size(blk_len); + const size_t ldc = gemm_args->ldc; + const size_t ldb = k_blks * (blk_len * blk_bitwidth / 8); + const std::byte * quant_a_ptr = static_cast(per_gemm_ws) + m_start * lda; + + const size_t zero_point_stride = gemm_args->quant_b_zp != nullptr ? sizeof(uint8_t) : 0; + const size_t packed_b_stride = ldb + k_blks * (scale_stride + zero_point_stride); + const std::byte * packed_quant_b_data = gemm_args->packed_quant_b_data + n_start * packed_b_stride; + + float * c_ptr = gemm_args->c_ptr + m_start * ldc + n_start; + + size_t count_n = 0; + const size_t compute_block_count_n = m_count == 1 ? n_count : 16; + for (size_t n = 0; n < n_count; n += count_n) { + count_n = std::min(n_count - n, compute_block_count_n); + + const std::byte * a_row = quant_a_ptr; + const std::byte * b_col = packed_quant_b_data + n * packed_b_stride; + const std::byte * b_col_zp = (zero_point_stride != 0) ? b_col : nullptr; + float * c_blk = c_ptr + n; + + int32_t rows_remaining = m_count; + + while (rows_remaining > 0) { + const auto rows_handled = sqnbitgemm_spacemit_ime::ime1::gemm_kernel_i8i4( + blk_len, a_row, b_col, nullptr, b_col_zp, c_blk, rows_remaining, count_n, gemm_k, k_blks, ldc, nullptr, + scale_stride); + + c_blk += rows_handled * ldc; + a_row += rows_handled * lda; + + rows_remaining -= rows_handled; + } + } +} + +template constexpr int QK_0() { + if constexpr (K == 4) { + return QK4_0; + } + if constexpr (K == 8) { + return QK8_0; + } + return -1; +} + +template struct block { + ggml_half d[N]; // deltas for N qK_0 blocks + uint8_t qs[(QK_0() * N * K) / 8]; // quants for N qK_0 blocks +}; + +template struct block_with_zp { + ggml_half d[N]; // deltas for N qK_1 blocks + uint8_t zp[N]; // zero points for N qK_1 blocks + uint8_t qs[(QK_0() * N * K) / 8]; // quants for N qK_1 blocks +}; + +// control size +static_assert(sizeof(block<4, 16>) == 16 * sizeof(ggml_half) + QK4_0 * 8, "wrong block<4,16> size/padding"); +static_assert(sizeof(block_with_zp<4, 16>) == 16 * sizeof(ggml_half) + QK4_0 * 8 + 16 * sizeof(uint8_t), + "wrong block_with_zp<4,16> size/padding"); +static_assert(sizeof(block<8, 16>) == 16 * sizeof(ggml_half) + QK4_0 * 16, "wrong block<8,16> size/padding"); + +using block_q4_0x16 = block<4, 16>; +using block_q4_1x16 = block_with_zp<4, 16>; +using block_q8_0x16 = block<8, 16>; + +static block_q4_0x16 make_block_q4_0x16(block_q4_0 * in, unsigned int blck_size_interleave) { + block_q4_0x16 out; + GGML_ASSERT(QK4_0 / blck_size_interleave == 2); + + for (int i = 0; i < 16; i++) { + out.d[i] = in[i].d; + } + + for (int i = 0; i < 16; i++) { + // [0, 15], in.d & 0x0F + for (int j = 0; j < QK4_0 / 4; j++) { + //src [b0 b16] ......... [b8 b24] ......... [b15 b31] + //dst [b0 b8] ......... [b7 b15] + out.qs[i * QK4_0 / 4 + j] = (in[i].qs[j] & 0x0F) | ((in[i].qs[j + QK4_0 / 4] & 0x0F) << 4); + } + } + + for (int i = 0; i < 16; i++) { + // [16, 31], in.d & 0xF0 + for (int j = 0; j < QK4_0 / 4; j++) { + //src [b0 b16] ......... [b8 b24] ......... [b15 b31] + //dst [b16 b24] ......... [b23 b31] + out.qs[4 * QK4_0 + i * QK4_0 / 4 + j] = ((in[i].qs[j] & 0xF0) >> 4) | (in[i].qs[j + QK4_0 / 4] & 0xF0); + } + } + + return out; +} + +static block_q4_1x16 make_block_q4_1x16(block_q4_1 * in, unsigned int blck_size_interleave) { + block_q4_1x16 out; + GGML_ASSERT(QK4_1 / blck_size_interleave == 2); + + for (int i = 0; i < 16; i++) { + float d = GGML_FP16_TO_FP32(in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.d); + float m = GGML_FP16_TO_FP32(in[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.m); + float mid = -std::nearbyintf(m / d); + mid = std::min(15.0f, std::max(0.0f, mid)); + out.d[i] = GGML_FP32_TO_FP16(d); + out.zp[i] = static_cast(mid); + } + + for (int i = 0; i < 16; i++) { + // [0, 15], in.d & 0x0F + for (int j = 0; j < QK4_1 / 4; j++) { + //src [b0 b16] ......... [b8 b24] ......... [b15 b31] + //dst [b0 b8] ......... [b7 b15] + out.qs[i * QK4_1 / 4 + j] = (in[i].qs[j] & 0x0F) | ((in[i].qs[j + QK4_1 / 4] & 0x0F) << 4); + } + } + + for (int i = 0; i < 16; i++) { + // [16, 31], in.d & 0xF0 + for (int j = 0; j < QK4_1 / 4; j++) { + //src [b0 b16] ......... [b8 b24] ......... [b15 b31] + //dst [b16 b24] ......... [b23 b31] + out.qs[4 * QK4_1 + i * QK4_1 / 4 + j] = ((in[i].qs[j] & 0xF0) >> 4) | (in[i].qs[j + QK4_1 / 4] & 0xF0); + } + } + + return out; +} + +static int repack_q4_0_to_q4_0_16_bl(struct ggml_tensor * t, + int interleave_block, + const void * GGML_RESTRICT data, + size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_Q4_0); + GGML_ASSERT(interleave_block == 16); + + constexpr int nrows_interleaved = 16; + + block_q4_0x16 * dst = (block_q4_0x16 *) t->data; + const block_q4_0 * src = (const block_q4_0 *) data; + block_q4_0 dst_tmp[16]; + int nrow = ggml_nrows(t); + int nblocks = t->ne[0] / QK4_0; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_q4_0)); + + if (t->ne[1] % nrows_interleaved != 0 || t->ne[0] % QK4_0 != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_q4_0x16(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + +static int repack_q4_1_to_q4_1_16_bl(struct ggml_tensor * t, + int interleave_block, + const void * GGML_RESTRICT data, + size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_Q4_1); + GGML_ASSERT(interleave_block == 16); + + constexpr int nrows_interleaved = 16; + + block_q4_1x16 * dst = (block_q4_1x16 *) t->data; + const block_q4_1 * src = (const block_q4_1 *) data; + block_q4_1 dst_tmp[16]; + int nrow = ggml_nrows(t); + int nblocks = t->ne[0] / QK4_1; + + GGML_ASSERT(data_size == nrow * nblocks * sizeof(block_q4_1)); + + if (t->ne[1] % nrows_interleaved != 0 || t->ne[0] % QK4_1 != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int i = 0; i < nrows_interleaved; i++) { + dst_tmp[i] = src[x + i * nblocks]; + } + *dst++ = make_block_q4_1x16(dst_tmp, interleave_block); + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + +static inline void get_scale_min_k4(int j, + const uint8_t * GGML_RESTRICT q, + uint8_t * GGML_RESTRICT d, + uint8_t * GGML_RESTRICT m) { + if (j < 4) { + *d = q[j] & 63; + *m = q[j + 4] & 63; + } else { + *d = (q[j + 4] & 0xF) | ((q[j - 4] >> 6) << 4); + *m = (q[j + 4] >> 4) | ((q[j - 0] >> 6) << 4); + } +} + +static int repack_q4_k_to_q4_1_16_bl(struct ggml_tensor * t, + int interleave_block, + const void * GGML_RESTRICT data, + size_t data_size) { + GGML_ASSERT(t->type == GGML_TYPE_Q4_K); + GGML_ASSERT(interleave_block == 16); + GGML_ASSERT(QK_K / QK4_1 == 8); + + constexpr int nrows_interleaved = 16; + + block_q4_1x16 * dst = (block_q4_1x16 *) t->data; + const block_q4_K * src = (const block_q4_K *) data; + block_q4_1 dst_tmp[16]; + int nrow = ggml_nrows(t); + int nblocks = t->ne[0] / QK_K; + + if (t->ne[1] % nrows_interleaved != 0 || t->ne[0] % QK_K != 0) { + return -1; + } + + for (int b = 0; b < nrow; b += nrows_interleaved) { + for (int64_t x = 0; x < nblocks; x++) { + for (int j = 0; j < 8; j++) { + for (int i = 0; i < nrows_interleaved; i++) { + uint8_t sc, m; + const float d = GGML_FP16_TO_FP32(src[x + i * nblocks].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.d); + const float min = + GGML_FP16_TO_FP32(src[x + i * nblocks].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.dmin); + get_scale_min_k4(j, src[x + i * nblocks].scales, &sc, &m); + const float d1 = d * sc; + const float m1 = min * m; + + dst_tmp[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.d = GGML_FP32_TO_FP16(d1); + dst_tmp[i].GGML_COMMON_AGGR_U.GGML_COMMON_AGGR_S.m = GGML_FP32_TO_FP16(-m1); + // src -> [b0, b32] [b1, b33] ... [b31, b63] + // dst -> [b0, b16] [b1, b17] ... [b15, b31] [b32, b48] [b33, b49] ... [b47, b63] + const uint8_t * q = src[x + i * nblocks].qs + (j / 2) * QK4_1; + if (j % 2 == 0) { + for (int ii = 0; ii < 16; ii++) { + dst_tmp[i].qs[ii] = (q[ii] & 0x0F) | ((q[ii + 16] & 0x0F) << 4); + } + } else { + for (int ii = 0; ii < 16; ii++) { + dst_tmp[i].qs[ii] = ((q[ii] & 0xF0) >> 4) | (q[ii + 16] & 0xF0); + } + } + } + *dst++ = make_block_q4_1x16(dst_tmp, interleave_block); + } + } + src += nrows_interleaved * nblocks; + } + return 0; + + GGML_UNUSED(data_size); +} + +namespace ggml::cpu::riscv64_spacemit { + +template +int repack(struct ggml_tensor *, const void *, size_t); + +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_q4_0_to_q4_0_16_bl(t, 16, data, data_size); +} + +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_q4_1_to_q4_1_16_bl(t, 16, data, data_size); +} + +template <> int repack(struct ggml_tensor * t, const void * data, size_t data_size) { + return repack_q4_k_to_q4_1_16_bl(t, 16, data, data_size); +} + +class tensor_traits_base : public ggml::cpu::tensor_traits { + public: + virtual int repack(struct ggml_tensor * t, const void * data, size_t data_size) = 0; +}; + +template class tensor_traits : public tensor_traits_base { + bool work_size(int /* n_threads */, const struct ggml_tensor * op, size_t & size) override { + switch (op->op) { + case GGML_OP_MUL_MAT: + size = ggml_row_size(GGML_TYPE_Q8_0, ggml_nelements(op->src[1])) * 4; + size = ((size + QK4_0 - 1) / QK4_0) * (QK4_0 * sizeof(float) + sizeof(float)); + return true; + default: + // GGML_ABORT("fatal error"); + break; + } + return false; + } + + bool compute_forward(struct ggml_compute_params * params, struct ggml_tensor * op) override { + switch (op->op) { + case GGML_OP_MUL_MAT: + if (op->src[0]->type == GGML_TYPE_Q4_0 || // + op->src[0]->type == GGML_TYPE_Q4_1 || // + op->src[0]->type == GGML_TYPE_Q4_K) { + forward_mul_mat_q4(params, op); + return true; + } + default: + // GGML_ABORT("fatal error"); + break; + } + return false; + } + + void forward_mul_mat_q4(ggml_compute_params * params, ggml_tensor * op) { + const ggml_tensor * src0 = op->src[0]; + const ggml_tensor * src1 = op->src[1]; + ggml_tensor * dst = op; + + GGML_TENSOR_BINARY_OP_LOCALS + + int ith = params->ith; + int nth = params->nth; + + [[maybe_unused]] const enum ggml_type type = src0->type; + + void * w_data = (void *) src0->data; + const float * feature = (const float *) src1->data; + float * output = (float *) dst->data; + + const size_t batch_feature = ne12 * ne13; + [[maybe_unused]] const size_t batch_weight = ne02 * ne03; + const size_t gemm_m = ne11; + const size_t gemm_k = ne10; + const size_t gemm_n = ne01; + + GGML_ASSERT(batch_weight == 1); + + const size_t block_count_k = div_round_up(gemm_k, QK4_0); + const size_t per_gemm_workspace_size = gemm_m * block_count_k * q8_blk_size(QK4_0); + const size_t per_gemm_workspace_stride = + div_round_up(per_gemm_workspace_size, alignof(uint64_t)) * alignof(uint64_t); + const size_t gemm_workspace_size = batch_feature * per_gemm_workspace_stride; + const size_t desired_wsize = gemm_workspace_size + alignof(uint64_t) - 1; + + if (ith == 0 && params->wsize < desired_wsize) { + throw std::runtime_error("wsize less than desired_wsize"); + } + + std::vector qnbitgemm_args(batch_feature); + + for (size_t i = 0; i < batch_feature; i++) { + qnbitgemm_args[i].a_ptr = feature + gemm_m * gemm_k * i; + qnbitgemm_args[i].lda = gemm_k; + qnbitgemm_args[i].packed_quant_b_data = (const std::byte *) w_data; + qnbitgemm_args[i].quant_b_scale = nullptr; + + if constexpr (std::is_same_v) { + qnbitgemm_args[i].quant_b_zp = nullptr; + } else { + qnbitgemm_args[i].quant_b_zp = w_data; + } + + qnbitgemm_args[i].bias = nullptr; + qnbitgemm_args[i].c_ptr = output + gemm_m * gemm_n * i; + qnbitgemm_args[i].ldc = gemm_n; + } + + const uintptr_t ws_ptr = reinterpret_cast(params->wdata); + void * ws = reinterpret_cast((ws_ptr + alignof(uint64_t) - 1) & (~(alignof(uint64_t) - 1))); + const size_t quant_a_stride = block_count_k * q8_blk_size(QK4_0); + + { + constexpr size_t block_size_m = 4; + size_t per_gemm_block_count_m = div_round_up(gemm_m, block_size_m); + int32_t task_count = batch_feature * per_gemm_block_count_m; + int32_t task_per_thread = (task_count + nth - 1) / nth; + int32_t start = ith * task_per_thread; + int32_t end = std::min((ith + 1) * task_per_thread, task_count); + for (int32_t compute_idx = start; compute_idx < end; compute_idx++) { + int32_t gemm_idx = compute_idx / block_size_m; + int32_t m_idx = compute_idx % block_size_m * block_size_m; + const qnbitgemm_spacemit_ime_args & data = qnbitgemm_args[gemm_idx]; + int32_t rows_tobe_handled = (gemm_m - m_idx) > block_size_m ? block_size_m : (gemm_m - m_idx); + + if (rows_tobe_handled == block_size_m) { + const float * a_row_ptr = data.a_ptr + m_idx * data.lda; + std::byte * quant_a_row_ptr = + static_cast(ws) + gemm_idx * per_gemm_workspace_stride + m_idx * quant_a_stride; + sqnbitgemm_spacemit_ime::ime1::quantize_a_4row_i8(QK4_0, a_row_ptr, gemm_k, quant_a_row_ptr); + } else { + while (rows_tobe_handled) { + const float * a_row_ptr = data.a_ptr + m_idx * data.lda; + std::byte * quant_a_row_ptr = static_cast(ws) + + gemm_idx * per_gemm_workspace_stride + m_idx * quant_a_stride; + sqnbitgemm_spacemit_ime::ime1::quantize_a_row_i8(QK4_0, a_row_ptr, gemm_k, quant_a_row_ptr); + rows_tobe_handled -= 1; + m_idx += 1; + } + } + } + } + + ggml_barrier(params->threadpool); + + if (ith >= ggml::cpu::riscv64_spacemit::num_ai_cores) { + return; + } + nth = std::min(nth, int{ ggml::cpu::riscv64_spacemit::num_ai_cores }); + + size_t threads_per_gemm = nth / batch_feature; + constexpr size_t gemm_m_stride = 128; + size_t nc = gemm_n; + const size_t gemm_m_blocked = div_round_up(gemm_m, gemm_m_stride); + const size_t max_nc = div_round_up(gemm_n * gemm_m_blocked, threads_per_gemm); + if (max_nc < nc) { + nc = std::min(nc, div_round_up(max_nc, QGEMM_STRIDEN_THREAD_ALIGN) * QGEMM_STRIDEN_THREAD_ALIGN); + } + const size_t gemm_n_stride = nc; + const size_t thread_count_m = div_round_up(gemm_m, gemm_m_stride); + const size_t thread_count_n = div_round_up(gemm_n, gemm_n_stride); + threads_per_gemm = thread_count_m * thread_count_n; + + { + int task_count = batch_feature * threads_per_gemm; + int task_per_thread = (task_count + nth - 1) / nth; + int start = ith * task_per_thread; + int end = std::min((ith + 1) * task_per_thread, task_count); + for (int compute_idx = start; compute_idx < end; compute_idx++) { + const auto gemm_i = compute_idx / threads_per_gemm; + const auto blk_i = compute_idx % threads_per_gemm; + const auto * data = &qnbitgemm_args[gemm_i]; + + const auto tid_n = blk_i / thread_count_m; + const auto tid_m = blk_i % thread_count_m; + + const size_t m_start = tid_m * gemm_m_stride; + const size_t m_count = std::min(gemm_m - m_start, (size_t) gemm_m_stride); + + const size_t n_start = tid_n * gemm_n_stride; + const size_t n_count = std::min(gemm_n - n_start, (size_t) gemm_n_stride); + + void * per_gemm_ws = reinterpret_cast(ws) + gemm_i * per_gemm_workspace_stride; + + sqnbitgemm_spacemit_ime_i8i4(QK4_0, gemm_k, data, per_gemm_ws, m_start, m_count, n_start, n_count); + } + } + } + + int repack(struct ggml_tensor * t, const void * data, size_t data_size) override { + GGML_LOG_DEBUG("%s: repack tensor %s with %s_%dx%d\n", __func__, t->name, ggml_type_name(t->type), + (int) NB_COLS, (int) INTER_SIZE); + return ggml::cpu::riscv64_spacemit::repack(t, data, data_size); + } +}; + +class tensor_traits_common : public tensor_traits_base { + bool work_size(int /* n_threads */, const struct ggml_tensor * op, size_t & size) override { + switch (op->op) { + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + size = 0; + return true; + default: + // GGML_ABORT("fatal error"); + break; + } + return false; + } + + bool compute_forward(struct ggml_compute_params * params, struct ggml_tensor * op) override { + switch (op->op) { + case GGML_OP_NORM: + forward_norm_f32(params, op); + return true; + case GGML_OP_RMS_NORM: + forward_rms_norm_f32(params, op); + return true; + default: + // GGML_ABORT("fatal error"); + break; + } + return false; + } + + void forward_norm_f32(ggml_compute_params * params, ggml_tensor * op) { + const ggml_tensor * src0 = op->src[0]; + ggml_tensor * dst = op; + GGML_ASSERT(ggml_are_same_shape(src0, dst)); + GGML_ASSERT(src0->nb[0] == sizeof(float)); + + const int ith = params->ith; + const int nth = params->nth; + + GGML_TENSOR_UNARY_OP_LOCALS + + float epsilon; + memcpy(&epsilon, dst->op_params, sizeof(float)); + + GGML_ASSERT(epsilon > 0.0f); + + auto * input = (float *) src0->data; + auto * output = (float *) dst->data; + + const auto hidden_size = ne00; + const auto task_count = ne01 * ne02 * ne03; + const auto task_per_thread = (task_count + nth - 1) / nth; + + const auto task_begin = ith * task_per_thread; + const auto task_end = std::min((ith + 1) * task_per_thread, task_count); + + for (auto task_idx = task_begin; task_idx < task_end; task_idx++) { + auto offset = task_idx * hidden_size; + auto * p_input = const_cast(input + offset); + + auto * p_output = output + offset; + auto * p_temp_output = p_output; + auto * p_gamma_data = (const float *) nullptr; + auto * p_beta_data = (const float *) nullptr; + size_t gvl = __riscv_vsetvlmax_e32m4(); + vfloat32m4_t sum = __riscv_vfmv_v_f_f32m4(0.f, gvl); + vfloat32m4_t sum_sq = __riscv_vfmv_v_f_f32m4(0.f, gvl); + int64_t length = hidden_size; + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + // load data + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_input, gvl); + + sum = __riscv_vfadd_vv_f32m4(sum, src_data, gvl); + sum_sq = __riscv_vfmacc_vv_f32m4(sum_sq, src_data, src_data, gvl); + + __riscv_vse32_v_f32m4(p_temp_output, src_data, gvl); + + p_input += gvl; + p_temp_output += gvl; + length -= gvl; + } + + gvl = __riscv_vsetvlmax_e32m1(); + + float mean = 0.f; + vfloat32m1_t zero_v = __riscv_vfmv_v_f_f32m1(0.f, gvl); + vfloat32m1_t mean_v = + __riscv_vfadd_vv_f32m1(__riscv_vget_v_f32m4_f32m1(sum, 0), __riscv_vget_v_f32m4_f32m1(sum, 1), gvl); + mean_v = __riscv_vfadd_vv_f32m1(mean_v, __riscv_vget_v_f32m4_f32m1(sum, 2), gvl); + mean_v = __riscv_vfadd_vv_f32m1(mean_v, __riscv_vget_v_f32m4_f32m1(sum, 3), gvl); + mean_v = __riscv_vfredusum_vs_f32m1_f32m1(mean_v, zero_v, gvl); + mean = __riscv_vfmv_f_s_f32m1_f32(mean_v); + mean /= hidden_size; + + vfloat32m1_t mean_square_v = __riscv_vfadd_vv_f32m1(__riscv_vget_v_f32m4_f32m1(sum_sq, 0), + __riscv_vget_v_f32m4_f32m1(sum_sq, 1), gvl); + mean_square_v = __riscv_vfadd_vv_f32m1(mean_square_v, __riscv_vget_v_f32m4_f32m1(sum_sq, 2), gvl); + mean_square_v = __riscv_vfadd_vv_f32m1(mean_square_v, __riscv_vget_v_f32m4_f32m1(sum_sq, 3), gvl); + mean_square_v = __riscv_vfredusum_vs_f32m1_f32m1(mean_square_v, zero_v, gvl); + + float mean_square = __riscv_vfmv_f_s_f32m1_f32(mean_square_v); + mean_square /= hidden_size; + mean_square = sqrt(mean_square - mean * mean + epsilon); + + mean_square = 1.0f / mean_square; + length = hidden_size; + p_temp_output = p_output; + + if (p_gamma_data == nullptr && p_beta_data == nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + src_data = __riscv_vfsub_vf_f32m4(src_data, mean, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + length -= gvl; + } + } else if (p_beta_data == nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + vfloat32m4_t gamma_data_v = __riscv_vle32_v_f32m4(p_gamma_data, gvl); + src_data = __riscv_vfsub_vf_f32m4(src_data, mean, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + src_data = __riscv_vfmul_vv_f32m4(src_data, gamma_data_v, gvl); + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + p_gamma_data += gvl; + length -= gvl; + } + } else if (p_gamma_data != nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + vfloat32m4_t gamma_data_v = __riscv_vle32_v_f32m4(p_gamma_data, gvl); + src_data = __riscv_vfsub_vf_f32m4(src_data, mean, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + src_data = __riscv_vfmul_vv_f32m4(src_data, gamma_data_v, gvl); + vfloat32m4_t beta_data_v = __riscv_vle32_v_f32m4(p_beta_data, gvl); + src_data = __riscv_vfadd_vv_f32m4(src_data, beta_data_v, gvl); + p_beta_data += gvl; + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + p_gamma_data += gvl; + length -= gvl; + } + } + } + } + + void forward_rms_norm_f32(ggml_compute_params * params, ggml_tensor * op) { + const ggml_tensor * src0 = op->src[0]; + ggml_tensor * dst = op; + GGML_ASSERT(ggml_are_same_shape(src0, dst)); + GGML_ASSERT(src0->nb[0] == sizeof(float)); + + const int ith = params->ith; + const int nth = params->nth; + + GGML_TENSOR_UNARY_OP_LOCALS + + float epsilon; + memcpy(&epsilon, dst->op_params, sizeof(float)); + + GGML_ASSERT(epsilon > 0.0f); + + auto * input = (float *) src0->data; + auto * output = (float *) dst->data; + + const auto hidden_size = ne00; + const auto task_count = ne01 * ne02 * ne03; + const auto task_per_thread = (task_count + nth - 1) / nth; + + const auto task_begin = ith * task_per_thread; + const auto task_end = std::min((ith + 1) * task_per_thread, task_count); + + for (auto task_idx = task_begin; task_idx < task_end; task_idx++) { + auto offset = task_idx * hidden_size; + auto * p_input = const_cast(input + offset); + auto * p_output = output + offset; + auto * p_temp_output = p_output; + auto * p_gamma_data = (const float *) nullptr; + auto * p_beta_data = (const float *) nullptr; + + size_t gvl = __riscv_vsetvlmax_e32m4(); + // vfloat32m4_t sum = __riscv_vfmv_v_f_f32m4(0.f, gvl); + vfloat32m4_t sum_sq = __riscv_vfmv_v_f_f32m4(0.f, gvl); + int64_t length = hidden_size; + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + // load data + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_input, gvl); + + sum_sq = __riscv_vfmacc_vv_f32m4(sum_sq, src_data, src_data, gvl); + + __riscv_vse32_v_f32m4(p_temp_output, src_data, gvl); + + p_input += gvl; + p_temp_output += gvl; + length -= gvl; + } + + gvl = __riscv_vsetvlmax_e32m1(); + + // float mean = 0.f; + vfloat32m1_t zero_v = __riscv_vfmv_v_f_f32m1(0.f, gvl); + + vfloat32m1_t mean_square_v = __riscv_vfadd_vv_f32m1(__riscv_vget_v_f32m4_f32m1(sum_sq, 0), + __riscv_vget_v_f32m4_f32m1(sum_sq, 1), gvl); + mean_square_v = __riscv_vfadd_vv_f32m1(mean_square_v, __riscv_vget_v_f32m4_f32m1(sum_sq, 2), gvl); + mean_square_v = __riscv_vfadd_vv_f32m1(mean_square_v, __riscv_vget_v_f32m4_f32m1(sum_sq, 3), gvl); + mean_square_v = __riscv_vfredusum_vs_f32m1_f32m1(mean_square_v, zero_v, gvl); + + float mean_square = __riscv_vfmv_f_s_f32m1_f32(mean_square_v); + mean_square /= hidden_size; + + mean_square = sqrt(mean_square + epsilon); + + mean_square = 1.0f / mean_square; + length = hidden_size; + p_temp_output = p_output; + + if (p_gamma_data == nullptr && p_beta_data == nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + length -= gvl; + } + } else if (p_beta_data == nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + vfloat32m4_t gamma_data_v = __riscv_vle32_v_f32m4(p_gamma_data, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + src_data = __riscv_vfmul_vv_f32m4(src_data, gamma_data_v, gvl); + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + p_gamma_data += gvl; + length -= gvl; + } + } else if (p_gamma_data != nullptr) { + while (length > 0) { + gvl = __riscv_vsetvl_e32m4(length); + vfloat32m4_t src_data = __riscv_vle32_v_f32m4(p_temp_output, gvl); + vfloat32m4_t gamma_data_v = __riscv_vle32_v_f32m4(p_gamma_data, gvl); + src_data = __riscv_vfmul_vf_f32m4(src_data, mean_square, gvl); + src_data = __riscv_vfmul_vv_f32m4(src_data, gamma_data_v, gvl); + vfloat32m4_t beta_data_v = __riscv_vle32_v_f32m4(p_beta_data, gvl); + src_data = __riscv_vfadd_vv_f32m4(src_data, beta_data_v, gvl); + p_beta_data += gvl; + __riscv_vse32_v_f32m4(p_output, src_data, gvl); + p_temp_output += gvl; + p_output += gvl; + p_gamma_data += gvl; + length -= gvl; + } + } + } + } + + int repack(struct ggml_tensor * t, const void * data, size_t data_size) override { + memcpy(t->data, data, data_size); + return 0; + } +}; + +static const tensor_traits q4_0_16x8_q8_0; +static const tensor_traits q4_1_16x8_q8_0; +static const tensor_traits q4_k_16x8_q8_0; +static const tensor_traits_common rvv_impl; + +} // namespace ggml::cpu::riscv64_spacemit + +static const ggml::cpu::tensor_traits * ggml_riscv64_spacemit_get_optimal_repack_type(const struct ggml_tensor * cur) { + if (cur->type == GGML_TYPE_Q4_0) { + if (cur->ne[1] % 16 == 0) { + return &ggml::cpu::riscv64_spacemit::q4_0_16x8_q8_0; + } + } else if (cur->type == GGML_TYPE_Q4_1) { + if (cur->ne[1] % 16 == 0) { + return &ggml::cpu::riscv64_spacemit::q4_1_16x8_q8_0; + } + } else if (cur->type == GGML_TYPE_Q4_K) { + if (cur->ne[1] % 16 == 0) { + return &ggml::cpu::riscv64_spacemit::q4_k_16x8_q8_0; + } + } else if (cur->type == GGML_TYPE_F32) { + return &ggml::cpu::riscv64_spacemit::rvv_impl; + } + + return nullptr; +} + +static enum ggml_status ggml_backend_riscv64_spacemit_buffer_init_tensor(ggml_backend_buffer_t buffer, + struct ggml_tensor * tensor) { + tensor->extra = + (void *) const_cast(ggml_riscv64_spacemit_get_optimal_repack_type(tensor)); + + GGML_UNUSED(buffer); + + return GGML_STATUS_SUCCESS; +} + +static void ggml_backend_riscv64_spacemit_buffer_set_tensor(ggml_backend_buffer_t buffer, + struct ggml_tensor * tensor, + const void * data, + size_t offset, + size_t size) { + GGML_ASSERT(offset == 0); + GGML_ASSERT(size == ggml_nbytes(tensor)); + + auto tensor_traits = (ggml::cpu::riscv64_spacemit::tensor_traits_base *) tensor->extra; + if (tensor_traits) { + auto OK = tensor_traits->repack(tensor, data, size); + GGML_ASSERT(OK == 0); + } + + GGML_UNUSED(buffer); +} + +static const char * ggml_backend_cpu_riscv64_spacemit_buffer_type_get_name(ggml_backend_buffer_type_t buft) { + return "CPU_RISCV64_SPACEMIT"; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_t ggml_backend_cpu_riscv64_spacemit_buffer_type_alloc_buffer(ggml_backend_buffer_type_t buft, + size_t size) { + ggml_backend_buffer_t buffer = ggml_backend_buft_alloc_buffer(ggml_backend_cpu_buffer_type(), size); + + if (buffer == nullptr) { + return nullptr; + } + + buffer->buft = buft; + buffer->iface.init_tensor = ggml_backend_riscv64_spacemit_buffer_init_tensor; + buffer->iface.set_tensor = ggml_backend_riscv64_spacemit_buffer_set_tensor; + buffer->iface.get_tensor = nullptr; + buffer->iface.cpy_tensor = nullptr; + return buffer; +} + +static size_t ggml_backend_cpu_riscv64_spacemit_buffer_type_get_alignment(ggml_backend_buffer_type_t buft) { + return 64; + + GGML_UNUSED(buft); +} + +static size_t ggml_backend_cpu_riscv64_spacemit_nbytes(ggml_backend_buffer_type_t buft, + const struct ggml_tensor * tensor) { + for (int i = 0; i < GGML_MAX_DIMS; ++i) { + if (tensor->ne[i] <= 0) { + return 0; + } + } + + size_t nbytes; + const size_t blck_size = ggml_blck_size(tensor->type); + if (blck_size == 1) { + nbytes = ggml_type_size(tensor->type); + for (int i = 0; i < GGML_MAX_DIMS; ++i) { + nbytes += (tensor->ne[i] - 1) * tensor->nb[i]; + } + } else { + nbytes = tensor->ne[0] * tensor->nb[0] / blck_size; + if (tensor->type == GGML_TYPE_Q4_K) { + GGML_ASSERT(nbytes % sizeof(block_q4_K) == 0); + nbytes = (nbytes / sizeof(block_q4_K)) * sizeof(block_q4_1) * 8; + for (int i = 1; i < GGML_MAX_DIMS; ++i) { + nbytes += (tensor->ne[i] - 1) * (tensor->nb[i] / sizeof(block_q4_K)) * sizeof(block_q4_1) * 8; + } + } else { + for (int i = 1; i < GGML_MAX_DIMS; ++i) { + nbytes += (tensor->ne[i] - 1) * tensor->nb[i]; + } + } + } + + GGML_UNUSED(buft); + return nbytes; +} + +namespace ggml::cpu::riscv64_spacemit { + +class extra_buffer_type : ggml::cpu::extra_buffer_type { + bool supports_op(ggml_backend_dev_t, const struct ggml_tensor * op) override { + switch (op->op) { + case GGML_OP_MUL_MAT: + if (op->src[0]->buffer && (ggml_n_dims(op->src[0]) == 2) && + op->src[0]->buffer->buft == ggml_backend_cpu_riscv64_spacemit_buffer_type() && + ggml_riscv64_spacemit_get_optimal_repack_type(op->src[0])) { + if (op->src[1]->buffer && !ggml_backend_buft_is_host(op->src[1]->buffer->buft)) { + return false; + } + if (op->src[1]->type == GGML_TYPE_F32) { + return true; + } + } + break; + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + if (op->src[0]->type == GGML_TYPE_F32) { + return true; + } + break; + default: + // GGML_ABORT("fatal error"); + break; + } + return false; + } + + ggml::cpu::tensor_traits * get_tensor_traits(const struct ggml_tensor * op) override { + switch (op->op) { + case GGML_OP_MUL_MAT: + if (op->src[0]->buffer && op->src[0]->buffer->buft == ggml_backend_cpu_riscv64_spacemit_buffer_type()) { + return (ggml::cpu::tensor_traits *) op->src[0]->extra; + } + break; + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + return (ggml::cpu::tensor_traits *) (&ggml::cpu::riscv64_spacemit::rvv_impl); + default: + // GGML_ABORT("fatal error"); + break; + } + + return nullptr; + } +}; + +} // namespace ggml::cpu::riscv64_spacemit + +ggml_backend_buffer_type_t ggml_backend_cpu_riscv64_spacemit_buffer_type(void) { + static struct ggml_backend_buffer_type ggml_backend_cpu_buffer_type_riscv64_spacemit = { + /* .iface = */ + { + /* .get_name = */ ggml_backend_cpu_riscv64_spacemit_buffer_type_get_name, + /* .alloc_buffer = */ ggml_backend_cpu_riscv64_spacemit_buffer_type_alloc_buffer, + /* .get_alignment = */ ggml_backend_cpu_riscv64_spacemit_buffer_type_get_alignment, + /* .get_max_size = */ nullptr, + /* .get_alloc_size = */ ggml_backend_cpu_riscv64_spacemit_nbytes, + /* .is_host = */ nullptr, + }, + /* .device = */ + ggml_backend_reg_dev_get(ggml_backend_cpu_reg(), 0), + /* .context = */ + new ggml::cpu::riscv64_spacemit::extra_buffer_type(), + }; + + return &ggml_backend_cpu_buffer_type_riscv64_spacemit; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.h 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.h --- 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,13 @@ +#pragma once + +#include "ggml-alloc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +ggml_backend_buffer_type_t ggml_backend_cpu_riscv64_spacemit_buffer_type(void); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime1_kernels.cpp 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime1_kernels.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime1_kernels.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime1_kernels.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,3196 @@ +#include "ggml.h" +#include "ime_kernels.h" + +#include +#include + +// clang-format off +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Woverlength-strings" +#pragma GCC diagnostic ignored "-Wcast-qual" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif +// clang-format on +namespace sqnbitgemm_spacemit_ime { + +#define QUANTIZEM4ROW_KERNEL \ + "vmv.s.x v16, zero \n\t" \ + "vfabs.v v8, v0 \n\t" \ + "vfredmax.vs v16, v8, v16 \n\t" \ + "vfmv.f.s f10, v16 \n\t" \ + "fmul.s f10, f10, %[RMAXREC] \n\t" \ + "fsw f10, (a1) \n\t" \ + "fdiv.s f11, %[FONE], f10 \n\t" \ + "vfmul.vf v16, v0, f11 \n\t" \ + "vfcvt.x.f.v v16, v16 \n\t" \ + "vsetvli t0, zero, e16, mf2 \n\t" \ + "vnclip.wx v16, v16, zero \n\t" \ + "vnclip.wx v17, v17, zero \n\t" \ + "vnclip.wx v18, v18, zero \n\t" \ + "vnclip.wx v19, v19, zero \n\t" \ + "vnclip.wx v20, v20, zero \n\t" \ + "vnclip.wx v21, v21, zero \n\t" \ + "vnclip.wx v22, v22, zero \n\t" \ + "vnclip.wx v23, v23, zero \n\t" \ + "vsetvli t0, zero, e8, mf4 \n\t" \ + "vnclip.wx v24, v16, zero \n\t" \ + "vnclip.wx v25, v17, zero \n\t" \ + "vnclip.wx v26, v18, zero \n\t" \ + "vnclip.wx v27, v19, zero \n\t" \ + "vnclip.wx v28, v20, zero \n\t" \ + "vnclip.wx v29, v21, zero \n\t" \ + "vnclip.wx v30, v22, zero \n\t" \ + "vnclip.wx v31, v23, zero \n\t" + +#define QUANTIZEM4ROW_STORE \ + "addi t1, %[BlkLen], 0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v24, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v25, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v26, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v27, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v28, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v29, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v30, (s1) \n\t" \ + "addi s1, s1, 32 \n\t" \ + "sub t1, t1, t0 \n\t" \ + "vsetvli t0, t1, e8, mf4 \n\t" \ + "vse8.v v31, (s1) \n\t" + +namespace ime1 { +void quantize_a_4row_i8(size_t BlkLen, const float * A, size_t CountK, std::byte * QuantA) { + constexpr float range_max_reciprocal = 1.0f / ((1 << 7) - 1); + const float fone = 1.0f; + + if (BlkLen == 16 || BlkLen == 32 || BlkLen == 64) { + for (size_t row_index = 0; row_index < 4; ++row_index) { + const float * SRC = A + row_index * CountK; + std::byte * DST = QuantA + row_index * sizeof(float); + + const size_t offset = (4 - row_index) * 4 + row_index * 8; + const size_t stride = 4 * (sizeof(float) + BlkLen); + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "addi t2, %[CountK], 0 \n\t" + "addi a1, %[DST], 0 \n\t" + "blt t2, %[BlkLen], TAIL%= \n\t" + + "LOOP%=: \n\t" + "vsetvli t0, %[BlkLen], e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "sub t2, t2, t0 \n\t" + "slli t1, t0, 2 \n\t" + "add %[SRC], %[SRC], t1 \n\t" + "add s1, a1, %[OFFSET] \n\t" + + QUANTIZEM4ROW_KERNEL QUANTIZEM4ROW_STORE + + "add a1, a1, %[STRIDE] \n\t" + "bge t2, %[BlkLen], LOOP%= \n\t" + + "TAIL%=: \n\t" + "blez t2, QUIT%= \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "vsetvli t0, t2, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "add s1, a1, %[OFFSET] \n\t" + + QUANTIZEM4ROW_KERNEL + + "addi t3, %[BlkLen], 0 \n\t" + "addi s2, s1, 0 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vxor.vv v8, v8, v8 \n\t" + "SET_ZERO%=: \n\t" + "vse8.v v8, (s2) \n\t" + "addi s2, s2, 32 \n\t" + "addi t3, t3, -8 \n\t" + "bnez t3, SET_ZERO%= \n\t" + + QUANTIZEM4ROW_STORE + + "QUIT%=: \n\t" + : [SRC] "+r"(SRC) + : [DST] "r"(DST), [BlkLen] "r"(BlkLen), [OFFSET] "r"(offset), [STRIDE] "r"(stride), + [CountK] "r"(CountK), [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal) + : "cc", "t0", "t1", "t2", "t3", "a1", "s1", "s2", "f10", "f11"); + } + } else if (BlkLen == 128) { + for (size_t row_index = 0; row_index < 4; ++row_index) { + const float * SRC = A + row_index * CountK; + std::byte * DST = QuantA + row_index * sizeof(float); + + const size_t offset = (4 - row_index) * 4 + row_index * 8; + const size_t stride = 4 * (sizeof(float) + BlkLen); + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "li t6, 32 \n\t" + "addi t2, %[CountK], 0 \n\t" + "addi a1, %[DST], 0 \n\t" + "add s1, a1, %[OFFSET] \n\t" + "blt t2, %[BlkLen], TAIL%= \n\t" + + "LOOP%=: \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "addi t2, t2, -128 \n\t" + + "QUANTIZE%=: \n\t" + "add s1, a1, %[OFFSET] \n\t" + "vfabs.v v16, v0 \n\t" + "vfabs.v v24, v8 \n\t" + "vfmax.vv v16, v24, v16 \n\t" + "vfredmax.vs v24, v16, v24 \n\t" + "vfmv.f.s f10, v24 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (a1) \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vfmul.vf v16, v0, f11 \n\t" + "vfmul.vf v24, v8, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v20, v24, zero \n\t" + "vsetvli t0, zero, e8, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vsetvli t0, zero, e64, m4 \n\t" + "vsse64.v v16, (s1), t6 \n\t" + "add a1, a1, %[STRIDE] \n\t" + "bge t2, %[BlkLen], LOOP%= \n\t" + + "TAIL%=: \n\t" + "blez t2, QUIT%= \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vxor.vv v8, v8, v8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "vsetvli t0, t2, e32, m8 \n\t" + "sub t2, t2, t0 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vsetvli t0, t2, e32, m8 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "sub t2, t2, t2 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "jal x0, QUANTIZE%= \n\t" + + "QUIT%=: \n\t" + : [SRC] "+r"(SRC) + : [DST] "r"(DST), [BlkLen] "r"(BlkLen), [OFFSET] "r"(offset), [STRIDE] "r"(stride), + [CountK] "r"(CountK), [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal) + : "cc", "t0", "t1", "t2", "t6", "a1", "s1", "s2", "f10", "f11"); + } + } else if (BlkLen == 256) { + for (size_t row_index = 0; row_index < 4; ++row_index) { + const float * SRC = A + row_index * CountK; + std::byte * DST = QuantA + row_index * sizeof(float); + const size_t offset = (4 - row_index) * 4 + row_index * 8; + const size_t stride = 4 * (sizeof(float) + BlkLen); + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "li t6, 32 \n\t" + "addi t2, %[CountK], 0 \n\t" + "addi a1, %[DST], 0 \n\t" + "add s1, a1, %[OFFSET] \n\t" + "blt t2, %[BlkLen], TAIL%= \n\t" + + "LOOP%=: \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v16, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v24, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], -768 \n\t" + "addi t2, t2, -256 \n\t" + "vfabs.v v0, v0 \n\t" + "vfabs.v v8, v8 \n\t" + "vfabs.v v16, v16 \n\t" + "vfabs.v v24, v24 \n\t" + "vfmax.vv v8, v0, v8 \n\t" + "vfmax.vv v24, v24, v16 \n\t" + "vfmax.vv v8, v8, v24 \n\t" + "vfredmax.vs v24, v8, v24 \n\t" + "vfmv.f.s f10, v24 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v16, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v24, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + + "QUANTIZE%=: \n\t" + "add s1, a1, %[OFFSET] \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (a1) \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vfmul.vf v0, v0, f11 \n\t" + "vfmul.vf v8, v8, f11 \n\t" + "vfmul.vf v16, v16, f11 \n\t" + "vfmul.vf v24, v24, f11 \n\t" + "vfcvt.x.f.v v0, v0 \n\t" + "vfcvt.x.f.v v8, v8 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vnclip.wx v4, v8, zero \n\t" + "vnclip.wx v8, v16, zero \n\t" + "vnclip.wx v12, v24, zero \n\t" + "vsetvli t0, zero, e8, m4 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vnclip.wx v4, v8, zero \n\t" + "vsetvli t0, zero, e64, m8 \n\t" + "vsse64.v v0, (s1), t6 \n\t" + "add a1, a1, %[STRIDE] \n\t" + "bge t2, %[BlkLen], LOOP%= \n\t" + + "TAIL%=: \n\t" + "blez t2, QUIT%= \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vxor.vv v8, v8, v8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "addi t1, t2, 0 \n\t" + "vsetvli t0, t1, e32, m8 \n\t" + "sub t1, t1, t0 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vsetvli t0, t1, e32, m8 \n\t" + "sub t1, t1, t0 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vsetvli t0, t1, e32, m8 \n\t" + "sub t1, t1, t0 \n\t" + "vle32.v v16, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vsetvli t0, t1, e32, m8 \n\t" + "vle32.v v24, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], -768 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfabs.v v0, v0 \n\t" + "vfabs.v v8, v8 \n\t" + "vfabs.v v16, v16 \n\t" + "vfabs.v v24, v24 \n\t" + "vfmax.vv v8, v0, v8 \n\t" + "vfmax.vv v24, v16, v24 \n\t" + "vfmax.vv v8, v8, v24 \n\t" + "vfredmax.vs v24, v8, v24 \n\t" + "vfmv.f.s f10, v24 \n\t" + "add s1, a1, %[OFFSET] \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (a1) \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vsetvli t0, zero, e64, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vsse64.v v0, (s1), t6 \n\t" + + "TAIL_LOOP%=: \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vsetvli t0, t2, e32, m1 \n\t" + "sub t2, t2, t0 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 32 \n\t" + "vfmul.vf v1, v0, f11 \n\t" + "vfcvt.x.f.v v2, v1 \n\t" + "vsetvli t0, zero, e16, mf2 \n\t" + "vnclip.wx v3, v2, zero \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vnclip.wx v3, v3, zero \n\t" + "vse8.v v3, (s1) \n\t" + "addi s1, s1, 32 \n\t" + "bnez t2, TAIL_LOOP%= \n\t" + + "QUIT%=: \n\t" + : [SRC] "+r"(SRC) + : [DST] "r"(DST), [BlkLen] "r"(BlkLen), [OFFSET] "r"(offset), [STRIDE] "r"(stride), + [CountK] "r"(CountK), [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal) + : "cc", "t0", "t1", "t2", "t6", "a1", "s1", "s2", "f10", "f11"); + } + } +} + +void quantize_a_row_i8(size_t BlkLen, const float * A, size_t CountK, std::byte * QuantA) { + const float * SRC = A; + std::byte * DST = QuantA; + constexpr float range_max_reciprocal = 1.0f / ((1 << 7) - 1); + const float fone = 1.0f; + std::byte * QuantA_offset = QuantA + CountK + 4 * ((CountK + BlkLen - 1) / BlkLen); + size_t offset = (CountK + BlkLen - 1) / BlkLen * BlkLen - CountK; + + if (CountK <= BlkLen) { + float max_abs_A = 0.0f; + for (size_t k = 0; k < CountK; k++) { + max_abs_A = std::max(max_abs_A, fabsf(A[k])); + } + float scale_A = max_abs_A * range_max_reciprocal; + + ((float *) QuantA)[0] = scale_A; + + auto * QuantAData_offset = (int8_t *) (QuantA + sizeof(float)); + + for (size_t k = 0; k < CountK; k++) { + QuantAData_offset[k] = + (int8_t) std::clamp(roundf(A[k] / scale_A), (float) std::numeric_limits::lowest(), + (float) std::numeric_limits::max()); + } + for (size_t k = CountK; k < BlkLen; k++) { + QuantAData_offset[k] = 0; + } + + return; + } + + if (BlkLen != 32 || BlkLen != 64 || BlkLen != 128) { + __asm__ volatile( + "vsetvli t0, zero, e8, m8 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "LOOP%=: \n\t" + "vsetvli t0, %[CNT], e8, m8 \n\t" + "vse8.v v24, (%[DST]) \n\t" + "addi %[DST], %[DST], 128 \n\t" + "sub %[CNT], %[CNT], t0 \n\t" + "bnez %[CNT], LOOP%= \n\t" + : [DST] "+r"(QuantA_offset), [CNT] "+r"(offset) + : + : "cc", "t0"); + } + if (BlkLen == 16) { + float buffer[64] = { 0.0f }; + __asm__ volatile( + "addi t3, zero, 16*8 \n\t" + "addi t2, zero, 16 \n\t" + "blt %[K], t3, LOOP_K%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_MAIN%=: \n\t" + "vsetvli t1, zero, e32, m2 \n\t" + "addi %[K], %[K], -128 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v2, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v4, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v6, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v10, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v12, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "vle32.v v14, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "addi a1, %[BUFFER], 0 \n\t" + "vfabs.v v16, v0 \n\t" + "vfabs.v v18, v2 \n\t" + "vfabs.v v20, v4 \n\t" + "vfabs.v v22, v6 \n\t" + "vfabs.v v24, v8 \n\t" + "vfabs.v v26, v10 \n\t" + "vfabs.v v28, v12 \n\t" + "vfabs.v v30, v14 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vfmax.vv v18, v18, v19 \n\t" + "vfmax.vv v20, v20, v21 \n\t" + "vfmax.vv v22, v22, v23 \n\t" + "vfmax.vv v24, v24, v25 \n\t" + "vfmax.vv v26, v26, v27 \n\t" + "vfmax.vv v28, v28, v29 \n\t" + "vfmax.vv v30, v30, v31 \n\t" + "vse32.v v16, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v18, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v20, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v22, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v24, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v26, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v28, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vse32.v v30, (a1) \n\t" + "addi a1, %[BUFFER], 0 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f10, f3, f7 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f10, %[FONE], f10 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f11, f3, f7 \n\t" + "fmul.s f11, f11, %[RMAXREC] \n\t" + "fsw f11, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f11, %[FONE], f11 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f12, f3, f7 \n\t" + "fmul.s f12, f12, %[RMAXREC] \n\t" + "fsw f12, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f12, %[FONE], f12 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f13, f3, f7 \n\t" + "fmul.s f13, f13, %[RMAXREC] \n\t" + "fsw f13, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f13, %[FONE], f13 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f14, f3, f7 \n\t" + "fmul.s f14, f14, %[RMAXREC] \n\t" + "fsw f14, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f14, %[FONE], f14 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f15, f3, f7 \n\t" + "fmul.s f15, f15, %[RMAXREC] \n\t" + "fsw f15, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f15, %[FONE], f15 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f16, f3, f7 \n\t" + "fmul.s f16, f16, %[RMAXREC] \n\t" + "fsw f16, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "fdiv.s f16, %[FONE], f16 \n\t" + "flw f0, (a1) \n\t" + "flw f1, 4(a1) \n\t" + "flw f2, 8(a1) \n\t" + "flw f3, 12(a1) \n\t" + "flw f4, 16(a1) \n\t" + "flw f5, 20(a1) \n\t" + "flw f6, 24(a1) \n\t" + "flw f7, 28(a1) \n\t" + "addi a1, a1, 32 \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f17, f3, f7 \n\t" + "fmul.s f17, f17, %[RMAXREC] \n\t" + "fsw f17, (%[DST]) \n\t" + "addi %[DST], %[DST], -136 \n\t" + "fdiv.s f17, %[FONE], f17 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmul.vf v16, v0, f10 \n\t" + "vfmul.vf v18, v2, f11 \n\t" + "vfmul.vf v20, v4, f12 \n\t" + "vfmul.vf v22, v6, f13 \n\t" + "vfmul.vf v24, v8, f14 \n\t" + "vfmul.vf v26, v10, f15 \n\t" + "vfmul.vf v28, v12, f16 \n\t" + "vfmul.vf v30, v14, f17 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v18, v18 \n\t" + "vfcvt.x.f.v v20, v20 \n\t" + "vfcvt.x.f.v v22, v22 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vfcvt.x.f.v v26, v26 \n\t" + "vfcvt.x.f.v v28, v28 \n\t" + "vfcvt.x.f.v v30, v30 \n\t" + "vsetvli t0, zero, e16, m1 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v18, v18, zero \n\t" + "vnclip.wx v20, v20, zero \n\t" + "vnclip.wx v22, v22, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vnclip.wx v26, v26, zero \n\t" + "vnclip.wx v28, v28, zero \n\t" + "vnclip.wx v30, v30, zero \n\t" + "vsetvli t0, t1, e8, mf2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v18, v18, zero \n\t" + "vnclip.wx v20, v20, zero \n\t" + "vnclip.wx v22, v22, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vnclip.wx v26, v26, zero \n\t" + "vnclip.wx v28, v28, zero \n\t" + "vnclip.wx v30, v30, zero \n\t" + "vse8.v v16, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v18, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v20, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v22, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v24, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v26, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v28, (%[DST]) \n\t" + "addi %[DST], %[DST], 20 \n\t" + "vse8.v v30, (%[DST]) \n\t" + "addi %[DST], %[DST], 16 \n\t" + "bge %[K], t3, LOOP_MAIN%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_K%=: \n\t" + "vsetvli t1, %[K], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 64 \n\t" + "sub %[K], %[K], t1 \n\t" + "vfabs.v v16, v0 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vse32.v v16, (%[BUFFER]) \n\t" + "flw f0, (%[BUFFER]) \n\t" + "flw f1, 4(%[BUFFER]) \n\t" + "flw f2, 8(%[BUFFER]) \n\t" + "flw f3, 12(%[BUFFER]) \n\t" + "flw f4, 16(%[BUFFER]) \n\t" + "flw f5, 20(%[BUFFER]) \n\t" + "flw f6, 24(%[BUFFER]) \n\t" + "flw f7, 28(%[BUFFER]) \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f10, f3, f7 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (%[DST]) \n\t" + "addi %[DST], %[DST], 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmul.vf v16, v0, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vsetvli t0, zero, e16, m1 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vsetvli t0, t1, e8, mf2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vse8.v v16, (%[DST]) \n\t" + "addi %[DST], %[DST], 16 \n\t" + "bge %[K], t2, LOOP_K%= \n\t" + "TAIL%=: \n\t" + "blez %[K], END%= \n\t" + "vsetvli t0, t3, e32, m2 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "jal x0, LOOP_K%= \n\t" + "END%=: \n\t" + : [SRC] "+r"(SRC), [DST] "+r"(DST), [K] "+r"(CountK) + : [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal), [BUFFER] "r"(buffer) + : "cc", "t3", "t2", "t1", "t0", "a1", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f10", "f11", "f12", + "f13", "f14", "f15", "f16", "f17"); + } else if (BlkLen == 32) { + __asm__ volatile( + "addi t3, zero, 32*4 \n\t" + "addi t2, zero, 32 \n\t" + + "addi a1, %[SRC], 0 \n\t" + "addi a2, %[SRC], 128 \n\t" + "addi a3, %[SRC], 256 \n\t" + "addi a4, %[SRC], 384 \n\t" + + "addi s1, %[DST], 0 \n\t" + "addi s2, %[DST], 36 \n\t" + "addi s3, %[DST], 72 \n\t" + "addi s4, %[DST], 108 \n\t" + "blt %[K], t3, LOOP_K%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + + "LOOP_MAIN%=: \n\t" + "vsetvli t1, zero, e32, m4 \n\t" + "addi %[K], %[K], -128 \n\t" + "vle32.v v0, (a1) \n\t" + "addi a1, a1, 512 \n\t" + "vle32.v v4, (a2) \n\t" + "addi a2, a2, 512 \n\t" + "vle32.v v8, (a3) \n\t" + "addi a3, a3, 512 \n\t" + "vle32.v v12, (a4) \n\t" + "addi a4, a4, 512 \n\t" + "vfabs.v v16, v0 \n\t" + "vfabs.v v20, v4 \n\t" + "vfabs.v v24, v8 \n\t" + "vfabs.v v28, v12 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v16, v16, v18 \n\t" + "vfmax.vv v20, v20, v22 \n\t" + "vfmax.vv v24, v24, v26 \n\t" + "vfmax.vv v28, v28, v30 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vfmax.vv v20, v20, v21 \n\t" + "vfmax.vv v24, v24, v25 \n\t" + "vfmax.vv v28, v28, v29 \n\t" + + "vfredmax.vs v17, v16, v17 \n\t" + "vfredmax.vs v21, v20, v21 \n\t" + "vfredmax.vs v25, v24, v25 \n\t" + "vfredmax.vs v29, v28, v29 \n\t" + "vfmv.f.s f10, v17 \n\t" + "vfmv.f.s f11, v21 \n\t" + "vfmv.f.s f12, v25 \n\t" + "vfmv.f.s f13, v29 \n\t" + + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fmul.s f11, f11, %[RMAXREC] \n\t" + "fmul.s f12, f12, %[RMAXREC] \n\t" + "fmul.s f13, f13, %[RMAXREC] \n\t" + "fsw f10, (s1) \n\t" + "addi s1, s1, 4 \n\t" + + "fsw f11, (s2) \n\t" + "addi s2, s2, 4 \n\t" + "fsw f12, (s3) \n\t" + "addi s3, s3, 4 \n\t" + "fsw f13, (s4) \n\t" + "addi s4, s4, 4 \n\t" + "fdiv.s f10, %[FONE], f10 \n\t" + "fdiv.s f11, %[FONE], f11 \n\t" + "fdiv.s f12, %[FONE], f12 \n\t" + "fdiv.s f13, %[FONE], f13 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmul.vf v16, v0, f10 \n\t" + "vfmul.vf v20, v4, f11 \n\t" + "vfmul.vf v24, v8, f12 \n\t" + "vfmul.vf v28, v12, f13 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v20, v20 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vfcvt.x.f.v v28, v28 \n\t" + "vsetvli t0, zero, e16, m2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v20, v20, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vnclip.wx v28, v28, zero \n\t" + "vsetvli t0, t1, e8, m1 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v20, v20, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vnclip.wx v28, v28, zero \n\t" + "vse8.v v16, (s1) \n\t" + "addi s1, s1, 140 \n\t" + "vse8.v v20, (s2) \n\t" + "addi s2, s2, 140 \n\t" + "vse8.v v24, (s3) \n\t" + "addi s3, s3, 140 \n\t" + "vse8.v v28, (s4) \n\t" + "addi s4, s4, 140 \n\t" + "bge %[K], t3, LOOP_MAIN%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_K%=: \n\t" + "vsetvli t1, %[K], e32, m4 \n\t" + "vle32.v v0, (a1) \n\t" + "addi a1, a1, 128 \n\t" + "sub %[K], %[K], t1 \n\t" + "vfabs.v v16, v0 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v16, v16, v18 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vfredmax.vs v17, v16, v17 \n\t" + "vfmv.f.s f10, v17 \n\t" + + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (s1) \n\t" + "addi s1, s1, 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmul.vf v16, v0, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vsetvli t0, zero, e16, m2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vse8.v v16, (s1) \n\t" + "addi s1, s1, 32 \n\t" + "bge %[K], t2, LOOP_K%= \n\t" + "TAIL%=: \n\t" + "blez %[K], END%= \n\t" + "vsetvli t0, t3, e32, m4 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "jal x0, LOOP_K%= \n\t" + "END%=: \n\t" + : [K] "+r"(CountK) + : [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal), [SRC] "r"(SRC), [DST] "r"(DST) + : "cc", "t3", "t2", "t1", "t0", "a1", "a2", "a3", "a4", "s1", "s2", "s3", "s4", "f10", "f11", "f12", "f13"); + } else if (BlkLen == 64) { + __asm__ volatile( + "addi t3, zero, 64*2 \n\t" + "addi t2, zero, 64 \n\t" + "addi a1, %[SRC], 0 \n\t" + "addi a2, %[SRC], 256 \n\t" + "addi s1, %[DST], 0 \n\t" + "addi s2, %[DST], 68 \n\t" + "blt %[K], t3, LOOP_K%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_MAIN%=: \n\t" + "vsetvli t1, zero, e32, m8 \n\t" + "addi %[K], %[K], -128 \n\t" + "vle32.v v0, (a1) \n\t" + "addi a1, a1, 512 \n\t" + "vle32.v v8, (a2) \n\t" + "addi a2, a2, 512 \n\t" + "vfabs.v v16, v0 \n\t" + "vfabs.v v24, v8 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmax.vv v16, v16, v20 \n\t" + "vfmax.vv v24, v24, v28 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v16, v16, v18 \n\t" + "vfmax.vv v24, v24, v26 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vfmax.vv v24, v24, v25 \n\t" + "vfredmax.vs v17, v16, v17 \n\t" + "vfredmax.vs v25, v24, v25 \n\t" + "vfmv.f.s f10, v17 \n\t" + "vfmv.f.s f11, v25 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fmul.s f11, f11, %[RMAXREC] \n\t" + "fsw f10, (s1) \n\t" + "addi s1, s1, 4 \n\t" + "fsw f11, (s2) \n\t" + "addi s2, s2, 4 \n\t" + "fdiv.s f10, %[FONE], f10 \n\t" + "fdiv.s f11, %[FONE], f11 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfmul.vf v16, v0, f10 \n\t" + "vfmul.vf v24, v8, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vsetvli t0, t1, e8, m2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v24, v24, zero \n\t" + "vse8.v v16, (s1) \n\t" + "addi s1, s1, 132 \n\t" + "vse8.v v24, (s2) \n\t" + "addi s2, s2, 132 \n\t" + "bge %[K], t3, LOOP_MAIN%= \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_K%=: \n\t" + "vsetvli t1, %[K], e32, m8 \n\t" + "vle32.v v0, (a1) \n\t" + "addi a1, a1, 256 \n\t" + "sub %[K], %[K], t1 \n\t" + "vfabs.v v16, v0 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmax.vv v16, v16, v20 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v16, v16, v18 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v16, v16, v17 \n\t" + "vfredmax.vs v17, v16, v17 \n\t" + "vfmv.f.s f10, v17 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (s1) \n\t" + "addi s1, s1, 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfmul.vf v16, v0, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vsetvli t0, zero, e8, m2 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vse8.v v16, (s1) \n\t" + "addi s1, s1, 64 \n\t" + "bge %[K], t2, LOOP_K%= \n\t" + "TAIL%=: \n\t" + "blez %[K], END%= \n\t" + "vsetvli t0, t3, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "jal x0, LOOP_K%= \n\t" + "END%=: \n\t" + : [K] "+r"(CountK) + : [SRC] "r"(SRC), [DST] "r"(DST), [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal) + : "cc", "t3", "t2", "t1", "t0", "a1", "a2", "s1", "s2", "f10", "f11"); + } else if (BlkLen == 128) { + __asm__ volatile( + "addi t2, zero, 128 \n\t" + "addi a1, %[SRC], 0 \n\t" + "addi a2, %[SRC], 256 \n\t" + "blt %[K], t2, TAIL%= \n\t" + "LOOP_K%=: \n\t" + "vsetvli t1, zero, e32, m8 \n\t" + "vle32.v v0, (a1) \n\t" + "addi a1, a1, 512 \n\t" + "vle32.v v8, (a2) \n\t" + "addi a2, a2, 512 \n\t" + "sub %[K], %[K], t2 \n\t" + "QUANT%=: \n\t" + "vfabs.v v16, v0 \n\t" + "vfabs.v v24, v8 \n\t" + "vfmax.vv v24, v16, v24 \n\t" + "vsetvli t1, zero, e32, m4 \n\t" + "vfmax.vv v28, v24, v28 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v30, v28, v30 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v30, v30, v31 \n\t" + "vfredmax.vs v31, v30, v31 \n\t" + "vfmv.f.s f10, v31 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (%[DST]) \n\t" + "addi %[DST], %[DST], 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfmul.vf v16, v0, f11 \n\t" + "vfmul.vf v24, v8, f11 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vnclip.wx v20, v24, zero \n\t" + "vsetvli t0, zero, e8, m4 \n\t" + "vnclip.wx v16, v16, zero \n\t" + "vse8.v v16, (%[DST]) \n\t" + "addi %[DST], %[DST], 128 \n\t" + "bge %[K], t2, LOOP_K%= \n\t" + "TAIL%=: \n\t" + "blez %[K], END%= \n\t" + "vsetvli t1, zero, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vxor.vv v8, v8, v8 \n\t" + "vsetvli t0, %[K], e32, m8 \n\t" + "vle32.v v0, (a1) \n\t" + "sub %[K], %[K], t0 \n\t" + "vsetvli t0, %[K], e32, m8 \n\t" + "vle32.v v8, (a2) \n\t" + "sub %[K], %[K], t0 \n\t" + "vsetvli t1, zero, e32, m8 \n\t" + "jal x0, QUANT%= \n\t" + "END%=: \n\t" + + : [DST] "+r"(DST), [K] "+r"(CountK) + : [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal), [SRC] "r"(SRC) + : "cc", "t2", "t1", "t0", "a1", "a2", "f10", "f11"); + } else { + float buffer[8] = { 0.0f }; + size_t cnt = BlkLen / 256; + + __asm__ volatile( + "slli t3, %[BLK], 2 \n\t" + "blt %[K], %[BLK], LOOP_TAIL%= \n\t" + "LOOP_MAIN%=: \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vxor.vv v31, v31, v31 \n\t" + "vse32.v v31, (%[BUFFER]) \n\t" + "addi t6, %[CNT], 0 \n\t" + "LOOP_CMP%=: \n\t" + "addi t6, t6, -1 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v16, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v24, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vfabs.v v0, v0 \n\t" + "vfabs.v v8, v8 \n\t" + "vfabs.v v16, v16 \n\t" + "vfabs.v v24, v24 \n\t" + "vfmax.vv v8, v0, v8 \n\t" + "vfmax.vv v16, v16, v24 \n\t" + "vfmax.vv v0, v0, v16 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmax.vv v0, v0, v4 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v0, v0, v2 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v0, v0, v1 \n\t" + "vle32.v v30, (%[BUFFER]) \n\t" + "vfmax.vv v31, v30, v0 \n\t" + "vse32.v v31, (%[BUFFER]) \n\t" + "bnez t6, LOOP_CMP%= \n\t" + "sub %[SRC], %[SRC], t3 \n\t" + "addi t6, %[CNT], 0 \n\t" + "flw f0, (%[BUFFER]) \n\t" + "flw f1, 4(%[BUFFER]) \n\t" + "flw f2, 8(%[BUFFER]) \n\t" + "flw f3, 12(%[BUFFER]) \n\t" + "flw f4, 16(%[BUFFER]) \n\t" + "flw f5, 20(%[BUFFER]) \n\t" + "flw f6, 24(%[BUFFER]) \n\t" + "flw f7, 28(%[BUFFER]) \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f10, f3, f7 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (%[DST]) \n\t" + "addi %[DST], %[DST], 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "addi t6, %[CNT], 0 \n\t" + "LOOP_QUANT%=: \n\t" + "addi t6, t6, -1 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v8, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v16, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vle32.v v24, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfmul.vf v0, v0, f11 \n\t" + "vfmul.vf v8, v8, f11 \n\t" + "vfmul.vf v16, v16, f11 \n\t" + "vfmul.vf v24, v24, f11 \n\t" + "vfcvt.x.f.v v0, v0 \n\t" + "vfcvt.x.f.v v8, v8 \n\t" + "vfcvt.x.f.v v16, v16 \n\t" + "vfcvt.x.f.v v24, v24 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vnclip.wx v4, v8, zero \n\t" + "vnclip.wx v8, v16, zero \n\t" + "vnclip.wx v12, v24, zero \n\t" + "vsetvli t0, zero, e8, m4 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vnclip.wx v4, v8, zero \n\t" + "vse8.v v0, (%[DST]) \n\t" + "addi %[DST], %[DST], 128 \n\t" + "vse8.v v4, (%[DST]) \n\t" + "addi %[DST], %[DST], 128 \n\t" + "bnez t6, LOOP_QUANT%= \n\t" + "sub %[K], %[K], %[BLK] \n\t" + "bge %[K], %[BLK], LOOP_MAIN%= \n\t" + "blez %[K], END%= \n\t" + "LOOP_TAIL%=: \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vxor.vv v31, v31, v31 \n\t" + "vse32.v v31, (%[BUFFER]) \n\t" + "addi t6, %[K], 0 \n\t" + "addi s1, %[SRC], 0 \n\t" + "TAIL_CMP%=: \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vsetvli t0, t6, e32, m8 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi %[SRC], %[SRC], 256 \n\t" + "sub t6, t6, t0 \n\t" + "vfabs.v v0, v0 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vfmax.vv v0, v0, v4 \n\t" + "vsetvli t0, zero, e32, m2 \n\t" + "vfmax.vv v0, v0, v2 \n\t" + "vsetvli t0, zero, e32, m1 \n\t" + "vfmax.vv v0, v0, v1 \n\t" + "vle32.v v30, (%[BUFFER]) \n\t" + "vfmax.vv v31, v30, v0 \n\t" + "vse32.v v31, (%[BUFFER]) \n\t" + "bnez t6, TAIL_CMP%= \n\t" + "addi t6, %[K], 0 \n\t" + "flw f0, (%[BUFFER]) \n\t" + "flw f1, 4(%[BUFFER]) \n\t" + "flw f2, 8(%[BUFFER]) \n\t" + "flw f3, 12(%[BUFFER]) \n\t" + "flw f4, 16(%[BUFFER]) \n\t" + "flw f5, 20(%[BUFFER]) \n\t" + "flw f6, 24(%[BUFFER]) \n\t" + "flw f7, 28(%[BUFFER]) \n\t" + "fmax.s f1, f0, f1 \n\t" + "fmax.s f3, f2, f3 \n\t" + "fmax.s f5, f4, f5 \n\t" + "fmax.s f7, f6, f7 \n\t" + "fmax.s f3, f1, f3 \n\t" + "fmax.s f7, f5, f7 \n\t" + "fmax.s f10, f3, f7 \n\t" + "fmul.s f10, f10, %[RMAXREC] \n\t" + "fsw f10, (%[DST]) \n\t" + "addi %[DST], %[DST], 4 \n\t" + "fdiv.s f11, %[FONE], f10 \n\t" + "addi t6, %[K], 0 \n\t" + "TAIL_QUANT%=: \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v0, v0, v0 \n\t" + "vsetvli t1, t6, e32, m8 \n\t" + "vle32.v v0, (s1) \n\t" + "addi s1, s1, 256 \n\t" + "sub t6, t6, t1 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vfmul.vf v0, v0, f11 \n\t" + "vfcvt.x.f.v v0, v0 \n\t" + "vsetvli t0, zero, e16, m4 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vsetvli t0, t1, e8, m2 \n\t" + "vnclip.wx v0, v0, zero \n\t" + "vse8.v v0, (%[DST]) \n\t" + "addi %[DST], %[DST], 64 \n\t" + "bnez t6, TAIL_QUANT%= \n\t" + "END%=: \n\t" + : [SRC] "+r"(SRC), [DST] "+r"(DST), [K] "+r"(CountK) + : [FONE] "f"(fone), [RMAXREC] "f"(range_max_reciprocal), [BLK] "r"(BlkLen), [BUFFER] "r"(buffer), + [CNT] "r"(cnt) + : "cc", "t1", "t0", "t6", "s1", "f0", "f1", "f2", "f3", "f4", "f5", "f6"); + } +} + +} // namespace ime1 + +namespace { +#define SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 \ + "vmadot v16, v14, v0 \n\t" \ + "vmadot v18, v14, v1 \n\t" \ + "vmadot v20, v14, v2 \n\t" \ + "vmadot v22, v14, v3 \n\t" \ + "vmadot v16, v15, v4 \n\t" \ + "vmadot v18, v15, v5 \n\t" \ + "vmadot v20, v15, v6 \n\t" \ + "vmadot v22, v15, v7 \n\t" + +#define SQ4BIT_KERNEL_ACC_1X4X4 \ + "vfcvt.f.x.v v16, v16 \n\t" \ + "vfcvt.f.x.v v18, v18 \n\t" \ + "vfcvt.f.x.v v20, v20 \n\t" \ + "vfcvt.f.x.v v22, v22 \n\t" \ + "addi s2, s1, 16 \n\t" \ + "addi s3, s1, 32 \n\t" \ + "addi s4, s1, 48 \n\t" \ + "addi s6, s5, 12 \n\t" \ + "vfmacc.vv v28, v16, v24 \n\t" \ + "vfmacc.vv v29, v18, v25 \n\t" \ + "vfmacc.vv v30, v20, v26 \n\t" \ + "vfmacc.vv v31, v22, v27 \n\t" + +#define SQ4BIT_KERNEL_ACC_F16_1X4X4 \ + "vfcvt.f.x.v v16, v16 \n\t" \ + "vfcvt.f.x.v v18, v18 \n\t" \ + "vfcvt.f.x.v v20, v20 \n\t" \ + "vfcvt.f.x.v v22, v22 \n\t" \ + "addi s2, s1, 8 \n\t" \ + "addi s3, s1, 16 \n\t" \ + "addi s4, s1, 24 \n\t" \ + "addi s6, s5, 12 \n\t" \ + "vfmacc.vv v28, v16, v24 \n\t" \ + "vfmacc.vv v29, v18, v25 \n\t" \ + "vfmacc.vv v30, v20, v26 \n\t" \ + "vfmacc.vv v31, v22, v27 \n\t" + +#define SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 \ + "vle8.v v4, (s1) \n\t" \ + "addi s1, s1, 128 \n\t" \ + "vle8.v v5, (s2) \n\t" \ + "addi s2, s2, 128 \n\t" \ + "vle8.v v6, (s3) \n\t" \ + "addi s3, s3, 128 \n\t" \ + "vle8.v v7, (s4) \n\t" \ + "addi s4, s4, 128 \n\t" \ + "vsetvli t0, zero, e8, mf4 \n\t" \ + "vle8.v v14, (s5) \n\t" \ + "addi s5, s5, 16 \n\t" \ + "vle8.v v15, (s6) \n\t" \ + "addi s6, s6, 16 \n\t" \ + "addi t5, t5, -1 \n\t" \ + "vsetvli t0, zero, e8, m1 \n\t" \ + "vand.vi v0, v4, 15 \n\t" \ + "vand.vi v1, v5, 15 \n\t" \ + "vand.vi v2, v6, 15 \n\t" \ + "vand.vi v3, v7, 15 \n\t" \ + "vsrl.vi v4, v4, 4 \n\t" \ + "vsrl.vi v5, v5, 4 \n\t" \ + "vsrl.vi v6, v6, 4 \n\t" \ + "vsrl.vi v7, v7, 4 \n\t" + +#define SQ4BIT_KERNEL_LOAD_ZP_16X1 \ + "vsetvli t0, zero, e8, mf2 \n\t" \ + "vle8.v v1, (s7) \n\t" \ + "vsetvli t0, zero, e8, m1 \n\t" \ + "vrgather.vv v8, v1, v13 \n\t" \ + "vadd.vi v13, v13, 4 \n\t" \ + "vrgather.vv v9, v1, v13 \n\t" \ + "vadd.vi v13, v13, 4 \n\t" \ + "vrgather.vv v10, v1, v13 \n\t" \ + "vadd.vi v13, v13, 4 \n\t" \ + "vrgather.vv v11, v1, v13 \n\t" \ + "vadd.vi v13, v13, -12 \n\t" + +// using for M4Kernel +#define LOAD_B_16x8x2 \ + "vsetvli t0, zero, e8, m1 \n\t" \ + "vle8.v v6, (s1) \n\t" \ + "addi s1, s1, 32*4 \n\t" \ + "vle8.v v7, (s2) \n\t" \ + "addi s2, s2, 32*4 \n\t" \ + "vle8.v v8, (s3) \n\t" \ + "addi s3, s3, 32*4 \n\t" \ + "vle8.v v9, (s4) \n\t" \ + "addi s4, s4, 32*4 \n\t" \ + \ + "vand.vi v2, v6, 15 \n\t" \ + "vand.vi v3, v7, 15 \n\t" \ + "vand.vi v4, v8, 15 \n\t" \ + "vand.vi v5, v9, 15 \n\t" \ + \ + "vsrl.vi v6, v6, 4 \n\t" \ + "vsrl.vi v7, v7, 4 \n\t" \ + "vsrl.vi v8, v8, 4 \n\t" \ + "vsrl.vi v9, v9, 4 \n\t" + +// [s2|s5, s3, s4, s6] +#define LOAD_SCALE_4x16_FP16 \ + "addi s2, s5, -8 \n\t" \ + "addi s3, s5, 8 \n\t" \ + "addi s4, s5, 16 \n\t" \ + "addi s6, s5, 24 \n\t" \ + "li t1, 0xf0 \n\t" \ + "vmv.s.x v0, t1 \n\t" \ + "vsetvli t0, zero, e16, mf4 \n\t" \ + "vle16.v v9, (s5) \n\t" \ + "vle16.v v11, (s3) \n\t" \ + "vle16.v v13, (s4) \n\t" \ + "vle16.v v15, (s6) \n\t" \ + "vsetvli t0, zero, e16, mf2 \n\t" \ + "vle16.v v9, (s2), v0.t \n\t" \ + "vle16.v v11, (s5), v0.t \n\t" \ + "vle16.v v13, (s3), v0.t \n\t" \ + "vle16.v v15, (s4), v0.t \n\t" \ + "vfwcvt.f.f.v v8, v9 \n\t" \ + "vfwcvt.f.f.v v10, v11 \n\t" \ + "vfwcvt.f.f.v v12, v13 \n\t" \ + "vfwcvt.f.f.v v14, v15 \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + "vmv.v.v v9, v8 \n\t" \ + "vmv.v.v v11, v10 \n\t" \ + "vmv.v.v v13, v12 \n\t" \ + "vmv.v.v v15, v14 \n\t" \ + "li t1, 0xf0 \n\t" \ + "vmv.s.x v0, t1 \n\t" \ + "vsetvli t0, zero, e32, mf2 \n\t" \ + "vfmul.vf v8, v8, f1 \n\t" \ + "vfmul.vf v10, v10, f1 \n\t" \ + "vfmul.vf v12, v12, f1 \n\t" \ + "vfmul.vf v14, v14, f1 \n\t" \ + "vfmul.vf v9, v9, f3 \n\t" \ + "vfmul.vf v11, v11, f3 \n\t" \ + "vfmul.vf v13, v13, f3 \n\t" \ + "vfmul.vf v15, v15, f3 \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + "vfmul.vf v8, v8, f2, v0.t \n\t" \ + "vfmul.vf v10, v10, f2, v0.t \n\t" \ + "vfmul.vf v12, v12, f2, v0.t \n\t" \ + "vfmul.vf v14, v14, f2, v0.t \n\t" \ + "vfmul.vf v9, v9, f4, v0.t \n\t" \ + "vfmul.vf v11, v11, f4, v0.t \n\t" \ + "vfmul.vf v13, v13, f4, v0.t \n\t" \ + "vfmul.vf v15, v15, f4, v0.t \n\t" + +// [s2|s5, s3, s4, s6] +#define LOAD_SCALE_4x16 \ + "addi s2, s5, -16 \n\t" \ + "addi s3, s5, 16 \n\t" \ + "addi s4, s5, 32 \n\t" \ + "addi s6, s5, 48 \n\t" \ + "li t1, 0xf0 \n\t" \ + "vmv.s.x v0, t1 \n\t" \ + "vsetvli t0, zero, e32, mf2 \n\t" \ + "vle32.v v8, (s5) \n\t" \ + "vle32.v v10, (s3) \n\t" \ + "vle32.v v12, (s4) \n\t" \ + "vle32.v v14, (s6) \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + "vle32.v v8, (s2), v0.t \n\t" \ + "vle32.v v10, (s5), v0.t \n\t" \ + "vle32.v v12, (s3), v0.t \n\t" \ + "vle32.v v14, (s4), v0.t \n\t" \ + "vmv.v.v v9, v8 \n\t" \ + "vmv.v.v v11, v10 \n\t" \ + "vmv.v.v v13, v12 \n\t" \ + "vmv.v.v v15, v14 \n\t" \ + "vsetvli t0, zero, e32, mf2 \n\t" \ + "vfmul.vf v8, v8, f1 \n\t" \ + "vfmul.vf v10, v10, f1 \n\t" \ + "vfmul.vf v12, v12, f1 \n\t" \ + "vfmul.vf v14, v14, f1 \n\t" \ + "vfmul.vf v9, v9, f3 \n\t" \ + "vfmul.vf v11, v11, f3 \n\t" \ + "vfmul.vf v13, v13, f3 \n\t" \ + "vfmul.vf v15, v15, f3 \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + "vfmul.vf v8, v8, f2, v0.t \n\t" \ + "vfmul.vf v10, v10, f2, v0.t \n\t" \ + "vfmul.vf v12, v12, f2, v0.t \n\t" \ + "vfmul.vf v14, v14, f2, v0.t \n\t" \ + "vfmul.vf v9, v9, f4, v0.t \n\t" \ + "vfmul.vf v11, v11, f4, v0.t \n\t" \ + "vfmul.vf v13, v13, f4, v0.t \n\t" \ + "vfmul.vf v15, v15, f4, v0.t \n\t" + +//[s1| BIAS, s2, s3, s4] +#define LOAD_BIAS \ + "vsetvli t0, zero, e32, mf2 \n\t" \ + "li t1, 0xf0 \n\t" \ + "vmv.s.x v0, t1 \n\t" \ + "addi s1, %[BIAS], -16 \n\t" \ + "addi s2, %[BIAS], 16 \n\t" \ + "addi s3, %[BIAS], 32 \n\t" \ + "addi s4, %[BIAS], 48 \n\t" \ + \ + "vle32.v v24, (%[BIAS]) \n\t" \ + "vle32.v v26, (s2) \n\t" \ + "vle32.v v28, (s3) \n\t" \ + "vle32.v v30, (s4) \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + "vle32.v v24, (s1), v0.t \n\t" \ + "vle32.v v26, (%[BIAS]), v0.t \n\t" \ + "vle32.v v28, (s2), v0.t \n\t" \ + "vle32.v v30, (s3), v0.t \n\t" \ + "vmv.v.v v25, v24 \n\t" \ + "vmv.v.v v27, v26 \n\t" \ + "vmv.v.v v29, v28 \n\t" \ + "vmv.v.v v31, v30 \n\t" + +#define SQ4BIT_KERNEL_COMP_4x16x16 \ + "vmadot v16, v10, v2 \n\t" \ + "vmadot v18, v10, v3 \n\t" \ + "vmadot v20, v10, v4 \n\t" \ + "vmadot v22, v10, v5 \n\t" \ + "vmadot v16, v11, v6 \n\t" \ + "vmadot v18, v11, v7 \n\t" \ + "vmadot v20, v11, v8 \n\t" \ + "vmadot v22, v11, v9 \n\t" + +#define SAVE_RESULT_4x16 \ + "addi a1, %[C], 0 \n\t" \ + "add a2, %[C], %[LDC] \n\t" \ + "add a3, a2, %[LDC] \n\t" \ + "add a4, a3, %[LDC] \n\t" \ + "addi a2, a2, -16 \n\t" \ + "addi a4, a4, -16 \n\t" \ + "li t1, 0xf0 \n\t" \ + "vmv.s.x v0, t1 \n\t" \ + "vsetvli t0, zero, e32, mf2 \n\t" \ + \ + "vse32.v v24, (a1) \n\t" \ + "addi a1, a1, 16 \n\t" \ + "vse32.v v25, (a3) \n\t" \ + "addi a3, a3, 16 \n\t" \ + \ + "vse32.v v26, (a1) \n\t" \ + "addi a1, a1, 16 \n\t" \ + "vse32.v v27, (a3) \n\t" \ + "addi a3, a3, 16 \n\t" \ + \ + "vse32.v v28, (a1) \n\t" \ + "addi a1, a1, 16 \n\t" \ + "vse32.v v29, (a3) \n\t" \ + "addi a3, a3, 16 \n\t" \ + \ + "vse32.v v30, (a1) \n\t" \ + "vse32.v v31, (a3) \n\t" \ + "vsetvli t0, zero, e32, m1 \n\t" \ + \ + "vse32.v v24, (a2), v0.t \n\t" \ + "addi a2, a2, 16 \n\t" \ + "vse32.v v25, (a4), v0.t \n\t" \ + "addi a4, a4, 16 \n\t" \ + \ + "vse32.v v26, (a2), v0.t \n\t" \ + "addi a2, a2, 16 \n\t" \ + "vse32.v v27, (a4), v0.t \n\t" \ + "addi a4, a4, 16 \n\t" \ + \ + "vse32.v v28, (a2), v0.t \n\t" \ + "addi a2, a2, 16 \n\t" \ + "vse32.v v29, (a4), v0.t \n\t" \ + "addi a4, a4, 16 \n\t" \ + \ + "vse32.v v30, (a2), v0.t \n\t" \ + "vse32.v v31, (a4), v0.t \n\t" + +#define SQ4BIT_KERNEL_LOAD_ZP_16X1_v2 \ + "vsetvli t0, zero, e8, mf2 \n\t" \ + "vle8.v v11, (s6) \n\t" \ + "vsetvli t0, zero, e8, m1 \n\t" \ + "vrgather.vv v12, v11, v1 \n\t" \ + "vadd.vi v1, v1, 4 \n\t" \ + "vrgather.vv v13, v11, v1 \n\t" \ + "vadd.vi v1, v1, 4 \n\t" \ + "vrgather.vv v14, v11, v1 \n\t" \ + "vadd.vi v1, v1, 4 \n\t" \ + "vrgather.vv v15, v11, v1 \n\t" \ + "vadd.vi v1, v1, -12 \n\t" + +template +void SQ4BitGemmM4Kernel_CompInt8_ScaleFp16_Impl(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountN, + size_t BlockCountK, + const float * Bias, + const size_t ldc) { + GGML_UNUSED(QuantBScale); + GGML_UNUSED(QuantBZeroPoint); + size_t LDC = ldc * sizeof(float); + const size_t INNER = BlkLen / 16; + float tmp[4 * 16]; + + if constexpr (HasZeroPoint) { + for (size_t n = 0; n < CountN; n += 16) { + size_t NBLKS = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(uint8_t) + // zp + n * BlockCountK * sizeof(_Float16); // scale + float * CPtr = C + n; + if (NBLKS < 16) { + CPtr = tmp; + LDC = 16 * sizeof(float); + } + if (Bias != nullptr) { + const float * bias = Bias + n; + if (NBLKS < 16) { + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "vse32.v v0, (%[DST]) \n\t" + : + : [SRC] "r"(bias), [DST] "r"(tmp), [N] "r"(NBLKS) + : "cc", "t0"); + bias = tmp; + } + __asm__ volatile(LOAD_BIAS + + "addi t3, %[BlockCountK], 0 \n\t" + + "vsetvli t0, zero, e8, m1 \n\t" + "li s1, 24 \n\t" + "vmv.v.i v1, 3 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v1, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v1, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v1, 0 \n\t" + + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + + "BLOCK_COUNTK_LOOP%=: \n\t" + // scale offset + "addi s5, s1, 0 \n\t" + // zp offset + "addi s6, s1, 32 \n\t" + "addi s1, s6, 16 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1_v2 + + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vsub.vv v2, v2, v12 \n\t" + "vsub.vv v6, v6, v12 \n\t" + "vsub.vv v3, v3, v13 \n\t" + "vsub.vv v7, v7, v13 \n\t" + "vsub.vv v4, v4, v14 \n\t" + "vsub.vv v8, v8, v14 \n\t" + "vsub.vv v5, v5, v15 \n\t" + "vsub.vv v9, v9, v15 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16_FP16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr), [BIAS] "r"(bias) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", + "s2", "s3", "s4", "s5", "s6"); + + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "addi t3, %[BlockCountK], 0 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "li s1, 24 \n\t" + "vmv.v.i v1, 3 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v1, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v1, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v1, 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + // scale offset + "addi s5, s1, 0 \n\t" + // zp offset + "addi s6, s1, 32 \n\t" + "addi s1, s6, 16 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1_v2 + + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vsub.vv v2, v2, v12 \n\t" + "vsub.vv v6, v6, v12 \n\t" + "vsub.vv v3, v3, v13 \n\t" + "vsub.vv v7, v7, v13 \n\t" + "vsub.vv v4, v4, v14 \n\t" + "vsub.vv v8, v8, v14 \n\t" + "vsub.vv v5, v5, v15 \n\t" + "vsub.vv v9, v9, v15 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16_FP16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", "s2", "s3", + "s4", "s5", "s6"); + } + } + } else { + for (size_t n = 0; n < CountN; n += 16) { + size_t NBLKS = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(_Float16); // scale + float * CPtr = C + n; + if (NBLKS < 16) { + CPtr = tmp; + LDC = 16 * sizeof(float); + } + if (Bias != nullptr) { + const float * bias = Bias + n; + if (NBLKS < 16) { + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "vse32.v v0, (%[DST]) \n\t" + : + : [SRC] "r"(bias), [DST] "r"(tmp), [N] "r"(NBLKS) + : "cc", "t0"); + bias = tmp; + } + __asm__ volatile(LOAD_BIAS + + "addi t3, %[BlockCountK], 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + "addi s5, s1, 0 \n\t" + "addi s1, s5, 32 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vsetvli t0, zero, e8, m1 \n\t" + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + "vadd.vi v8, v8, -8 \n\t" + "vadd.vi v9, v9, -8 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16_FP16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr), [BIAS] "r"(bias) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", + "s2", "s3", "s4", "s5", "s6"); + + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "addi t3, %[BlockCountK], 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + "addi s5, s1, 0 \n\t" + "addi s1, s5, 32 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vsetvli t0, zero, e8, m1 \n\t" + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + "vadd.vi v8, v8, -8 \n\t" + "vadd.vi v9, v9, -8 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16_FP16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", "s2", "s3", + "s4", "s5", "s6"); + } + } + } + if (CountN % 16 != 0) { + // stroe output from tmp to C when NBLKS less than 16. + float * CPtr = C + CountN / 16 * 16; + const size_t N = CountN % 16; + LDC = ldc * sizeof(float); + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi s2, %[SRC], 64 \n\t" + "addi s3, %[SRC], 64*2 \n\t" + "addi s4, %[SRC], 64*3 \n\t" + "vle32.v v2, (s2) \n\t" + "vle32.v v4, (s3) \n\t" + "vle32.v v6, (s4) \n\t" + "add t2, %[DST], %[LDC] \n\t" + "add t3, t2, %[LDC] \n\t" + "add t4, t3, %[LDC] \n\t" + "vse32.v v0, (%[DST]) \n\t" + "vse32.v v2, (t2) \n\t" + "vse32.v v4, (t3) \n\t" + "vse32.v v6, (t4) \n\t" + : + : [N] "r"(N), [SRC] "r"(tmp), [DST] "r"(CPtr), [LDC] "r"(LDC) + : "cc", "t0", "t2", "t3", "t4", "s2", "s3", "s4"); + } +} + +template +void SQ4BitGemmM4Kernel_CompInt8_Impl(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountN, + size_t BlockCountK, + const float * Bias, + const size_t ldc) { + GGML_UNUSED(QuantBScale); + GGML_UNUSED(QuantBZeroPoint); + size_t LDC = ldc * sizeof(float); + const size_t INNER = BlkLen / 16; + float tmp[4 * 16]; + + if constexpr (HasZeroPoint) { + for (size_t n = 0; n < CountN; n += 16) { + size_t NBLKS = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(uint8_t) + // zp + n * BlockCountK * sizeof(float); // scale + float * CPtr = C + n; + if (NBLKS < 16) { + CPtr = tmp; + LDC = 16 * sizeof(float); + } + if (Bias != nullptr) { + const float * bias = Bias + n; + if (NBLKS < 16) { + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "vse32.v v0, (%[DST]) \n\t" + : + : [SRC] "r"(bias), [DST] "r"(tmp), [N] "r"(NBLKS) + : "cc", "t0"); + bias = tmp; + } + + __asm__ volatile(LOAD_BIAS + "addi t3, %[BlockCountK], 0 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "li s1, 24 \n\t" + "vmv.v.i v1, 3 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v1, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v1, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v1, 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + // scale offset + "addi s5, s1, 0 \n\t" + // zp offset + "addi s6, s1, 64 \n\t" + "addi s1, s6, 16 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1_v2 + + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vsub.vv v2, v2, v12 \n\t" + "vsub.vv v6, v6, v12 \n\t" + "vsub.vv v3, v3, v13 \n\t" + "vsub.vv v7, v7, v13 \n\t" + "vsub.vv v4, v4, v14 \n\t" + "vsub.vv v8, v8, v14 \n\t" + "vsub.vv v5, v5, v15 \n\t" + "vsub.vv v9, v9, v15 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr), [BIAS] "r"(bias) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", + "s2", "s3", "s4", "s5", "s6"); + + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "addi t3, %[BlockCountK], 0 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "li s1, 24 \n\t" + "vmv.v.i v1, 3 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v1, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v1, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v1, 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + // scale offset + "addi s5, s1, 0 \n\t" + // zp offset + "addi s6, s1, 64 \n\t" + "addi s1, s6, 16 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1_v2 + + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vsub.vv v2, v2, v12 \n\t" + "vsub.vv v6, v6, v12 \n\t" + "vsub.vv v3, v3, v13 \n\t" + "vsub.vv v7, v7, v13 \n\t" + "vsub.vv v4, v4, v14 \n\t" + "vsub.vv v8, v8, v14 \n\t" + "vsub.vv v5, v5, v15 \n\t" + "vsub.vv v9, v9, v15 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", "s2", "s3", + "s4", "s5", "s6"); + } + } + } else { + for (size_t n = 0; n < CountN; n += 16) { + size_t NBLKS = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(float); // scale + float * CPtr = C + n; + if (NBLKS < 16) { + CPtr = tmp; + LDC = 16 * sizeof(float); + } + if (Bias != nullptr) { + const float * bias = Bias + n; + if (NBLKS < 16) { + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "vse32.v v0, (%[DST]) \n\t" + : + : [SRC] "r"(bias), [DST] "r"(tmp), [N] "r"(NBLKS) + : "cc", "t0"); + bias = tmp; + } + __asm__ volatile(LOAD_BIAS + "addi t3, %[BlockCountK], 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + "addi s5, s1, 0 \n\t" + "addi s1, s5, 64 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vsetvli t0, zero, e8, m1 \n\t" + "vle8.v v10, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + "vadd.vi v8, v8, -8 \n\t" + "vadd.vi v9, v9, -8 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr), [BIAS] "r"(bias) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", + "s2", "s3", "s4", "s5", "s6"); + + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v24, v24, v24 \n\t" + "addi t3, %[BlockCountK], 0 \n\t" + "addi a1, %[A], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "BLOCK_COUNTK_LOOP%=: \n\t" + "addi s5, s1, 0 \n\t" + "addi s1, s5, 64 \n\t" + "addi s2, s1, 32 \n\t" + "addi s3, s1, 32*2 \n\t" + "addi s4, s1, 32*3 \n\t" + "vsetvli t0, zero, e32, m8 \n\t" + "vxor.vv v16, v16, v16 \n\t" + // load a scale + "flw f1, (a1) \n\t" + "flw f2, 4(a1) \n\t" + "flw f3, 8(a1) \n\t" + "flw f4, 12(a1) \n\t" + "addi a1, a1, 16 \n\t" + "addi t2, %[INNER], 0 \n\t" + "BLOCK_INNER_LOOP%=: \n\t" + + LOAD_B_16x8x2 + + "vsetvli t0, zero, e8, m1 \n\t" + "vle8.v v10, (a1) \n\t" + + "addi a1, a1, 32 \n\t" + "vle8.v v11, (a1) \n\t" + "addi a1, a1, 32 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + "vadd.vi v8, v8, -8 \n\t" + "vadd.vi v9, v9, -8 \n\t" + + SQ4BIT_KERNEL_COMP_4x16x16 + + "addi t2, t2, -1 \n\t" + "bnez t2, BLOCK_INNER_LOOP%= \n\t" + + LOAD_SCALE_4x16 + + "vsetvli t0, zero, e32, m8 \n\t" + "vfcvt.f.x.v v16, v16 \n\t" + "vfmacc.vv v24, v16, v8 \n\t" + "addi t3, t3, -1 \n\t" + "bnez t3, BLOCK_COUNTK_LOOP%= \n\t" + + "RESULT_SAVE%=: \n\t" + + SAVE_RESULT_4x16 + + : + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [LDC] "r"(LDC), + [BlockCountK] "r"(BlockCountK), [C] "r"(CPtr) + : "cc", "t0", "t1", "t2", "t3", "a1", "a2", "a3", "a4", "f1", "f2", "f3", "f4", "s1", "s2", "s3", + "s4", "s5", "s6"); + } + } + } + if (CountN % 16 != 0) { + // stroe output from tmp to C when NBLKS less than 16. + float * CPtr = C + CountN / 16 * 16; + const size_t N = CountN % 16; + LDC = ldc * sizeof(float); + __asm__ volatile( + "vsetvli t0, %[N], e32, m2 \n\t" + "vle32.v v0, (%[SRC]) \n\t" + "addi s2, %[SRC], 64 \n\t" + "addi s3, %[SRC], 64*2 \n\t" + "addi s4, %[SRC], 64*3 \n\t" + "vle32.v v2, (s2) \n\t" + "vle32.v v4, (s3) \n\t" + "vle32.v v6, (s4) \n\t" + "add t2, %[DST], %[LDC] \n\t" + "add t3, t2, %[LDC] \n\t" + "add t4, t3, %[LDC] \n\t" + "vse32.v v0, (%[DST]) \n\t" + "vse32.v v2, (t2) \n\t" + "vse32.v v4, (t3) \n\t" + "vse32.v v6, (t4) \n\t" + : + : [N] "r"(N), [SRC] "r"(tmp), [DST] "r"(CPtr), [LDC] "r"(LDC) + : "cc", "t0", "t2", "t3", "t4", "s2", "s3", "s4"); + } +} + +template +void SQ4BitGemmM1Kernel_CompInt8_ScaleFp16_Impl(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountN, + size_t BlockCountK, + const float * Bias) { + GGML_UNUSED(QuantBScale); + GGML_UNUSED(QuantBZeroPoint); + size_t INNER = BlkLen / 16; + + if constexpr (HasZeroPoint) { + for (size_t n = 0; n < CountN; n += 16) { + size_t nblks = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(uint8_t) + // zp + n * BlockCountK * sizeof(_Float16); // scale + float * CPtr = C + n; + size_t cnt = BlockCountK; + if (Bias != nullptr) { + const float * bias = Bias + n; + __asm__ volatile( + "addi t3, %[NBLKS], 0 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + + "vmv.v.i v13, 3 \n\t" + "li s1, 24 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v13, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v13, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v13, 0 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 8 \n\t" + "addi s3, %[B], 16 \n\t" + "addi s4, %[B], 24 \n\t" + // zp offset + "addi s7, %[B], 32 \n\t" + // a offset + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v28, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v29, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v30, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v31, (%[BIAS]) \n\t" + + "LOOP_K%=: \n\t" + "vsetvli t0, zero, e16, mf4 \n\t" + + "vle16.v v4, (s1) \n\t" + "addi s1, s1, 48 \n\t" + "vle16.v v5, (s2) \n\t" + "addi s2, s2, 72 \n\t" + "vle16.v v6, (s3) \n\t" + "addi s3, s3, 96 \n\t" + "vle16.v v7, (s4) \n\t" + "addi s4, s4, 120 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + "vfwcvt.f.f.v v8, v4 \n\t" + "vfwcvt.f.f.v v9, v5 \n\t" + "vfwcvt.f.f.v v10, v6 \n\t" + "vfwcvt.f.f.v v11, v7 \n\t" + + "vsetvli t0, zero, e32, mf2 \n\t" + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1 + + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vsub.vv v0, v0, v8 \n\t" + "vsub.vv v4, v4, v8 \n\t" + "vsub.vv v1, v1, v9 \n\t" + "vsub.vv v5, v5, v9 \n\t" + "vsub.vv v2, v2, v10 \n\t" + "vsub.vv v6, v6, v10 \n\t" + "vsub.vv v3, v3, v11 \n\t" + "vsub.vv v7, v7, v11 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_F16_1X4X4 + "addi s7, s1, 32 \n\t" + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks), [BIAS] "+r"(bias) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6", "s7"); + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v28, v28, v28 \n\t" + + "vsetvli t0, zero, e8, m1 \n\t" + "vmv.v.i v13, 3 \n\t" + "li s1, 24 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v13, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v13, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v13, 0 \n\t" + + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 8 \n\t" + "addi s3, %[B], 16 \n\t" + "addi s4, %[B], 24 \n\t" + + "addi s7, %[B], 32 \n\t" + + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "LOOP_K%=: \n\t" + "vsetvli t0, zero, e16, mf4 \n\t" + "vle16.v v4, (s1) \n\t" + "addi s1, s1, 48 \n\t" + "vle16.v v5, (s2) \n\t" + "addi s2, s2, 72 \n\t" + "vle16.v v6, (s3) \n\t" + "addi s3, s3, 96 \n\t" + "vle16.v v7, (s4) \n\t" + "addi s4, s4, 120 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "vfwcvt.f.f.v v8, v4 \n\t" + "vfwcvt.f.f.v v9, v5 \n\t" + "vfwcvt.f.f.v v10, v6 \n\t" + "vfwcvt.f.f.v v11, v7 \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1 + + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vsub.vv v0, v0, v8 \n\t" + "vsub.vv v4, v4, v8 \n\t" + "vsub.vv v1, v1, v9 \n\t" + "vsub.vv v5, v5, v9 \n\t" + "vsub.vv v2, v2, v10 \n\t" + "vsub.vv v6, v6, v10 \n\t" + "vsub.vv v3, v3, v11 \n\t" + "vsub.vv v7, v7, v11 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_F16_1X4X4 + "addi s7, s1, 32 \n\t" + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6", "s7"); + } + } + } else { + for (size_t n = 0; n < CountN; n += 16) { + size_t nblks = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(_Float16); // scale + float * CPtr = C + n; + size_t cnt = BlockCountK; + if (Bias != nullptr) { + const float * bias = Bias + n; + __asm__ volatile( + "addi t3, %[NBLKS], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 8 \n\t" + "addi s3, %[B], 16 \n\t" + "addi s4, %[B], 24 \n\t" + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v28, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v29, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v30, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v31, (%[BIAS]) \n\t" + + "LOOP_K%=: \n\t" + "vsetvli t0, zero, e16, mf4 \n\t" + + "vle16.v v4, (s1) \n\t" + "addi s1, s1, 32 \n\t" + "vle16.v v5, (s2) \n\t" + "addi s2, s2, 56 \n\t" + "vle16.v v6, (s3) \n\t" + "addi s3, s3, 80 \n\t" + "vle16.v v7, (s4) \n\t" + "addi s4, s4, 104 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + "vfwcvt.f.f.v v8, v4 \n\t" + "vfwcvt.f.f.v v9, v5 \n\t" + "vfwcvt.f.f.v v10, v6 \n\t" + "vfwcvt.f.f.v v11, v7 \n\t" + + "vsetvli t0, zero, e32, mf2 \n\t" + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vadd.vi v0, v0, -8 \n\t" + "vadd.vi v1, v1, -8 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_F16_1X4X4 + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks), [BIAS] "+r"(bias) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6"); + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v28, v28, v28 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 8 \n\t" + "addi s3, %[B], 16 \n\t" + "addi s4, %[B], 24 \n\t" + + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "LOOP_K%=: \n\t" + "vsetvli t0, zero, e16, mf4 \n\t" + "vle16.v v4, (s1) \n\t" + "addi s1, s1, 32 \n\t" + "vle16.v v5, (s2) \n\t" + "addi s2, s2, 56 \n\t" + "vle16.v v6, (s3) \n\t" + "addi s3, s3, 80 \n\t" + "vle16.v v7, (s4) \n\t" + "addi s4, s4, 104 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "vfwcvt.f.f.v v8, v4 \n\t" + "vfwcvt.f.f.v v9, v5 \n\t" + "vfwcvt.f.f.v v10, v6 \n\t" + "vfwcvt.f.f.v v11, v7 \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vadd.vi v0, v0, -8 \n\t" + "vadd.vi v1, v1, -8 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_F16_1X4X4 + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6"); + } + } + } +} + +template +void SQ4BitGemmM1Kernel_CompInt8_Impl(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountN, + size_t BlockCountK, + const float * Bias) { + GGML_UNUSED(QuantBScale); + GGML_UNUSED(QuantBZeroPoint); + const size_t INNER = BlkLen / 16; + if constexpr (HasZeroPoint) { + for (size_t n = 0; n < CountN; n += 16) { + size_t nblks = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(uint8_t) + // zp + n * BlockCountK * sizeof(float); // scale + float * CPtr = C + n; + size_t cnt = BlockCountK; + if (Bias != nullptr) { + const float * bias = Bias + n; + __asm__ volatile( + "addi t3, %[NBLKS], 0 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "vmv.v.i v13, 3 \n\t" + "li s1, 24 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v13, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v13, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v13, 0 \n\t" + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v28, v28, v28 \n\t" + + // scale offset, scale0.0, scale1.0, scale2.0, scale3.0....scale15.0 + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 16 \n\t" + "addi s3, %[B], 32 \n\t" + "addi s4, %[B], 48 \n\t" + // zp offset + "addi s7, %[B], 64 \n\t" + // a offset + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v28, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v29, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v30, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v31, (%[BIAS]) \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + "LOOP_K%=: \n\t" + + // load scale + "vle32.v v8, (s1) \n\t" + "addi s1, s1, 80 \n\t" + "vle32.v v9, (s2) \n\t" + "addi s2, s2, 96 \n\t" + "vle32.v v10, (s3) \n\t" + "addi s3, s3, 112 \n\t" + "vle32.v v11, (s4) \n\t" + "addi s4, s4, 128 \n\t" + + // load a scale + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + + // a scale * b scale + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1 + + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vsub.vv v0, v0, v8 \n\t" + "vsub.vv v4, v4, v8 \n\t" + "vsub.vv v1, v1, v9 \n\t" + "vsub.vv v5, v5, v9 \n\t" + "vsub.vv v2, v2, v10 \n\t" + "vsub.vv v6, v6, v10 \n\t" + "vsub.vv v3, v3, v11 \n\t" + "vsub.vv v7, v7, v11 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_1X4X4 + "addi s7, s1, 64 \n\t" + + "bnez %[CNT], LOOP_K%= \n\t" + + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks), [BIAS] "+r"(bias) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6", "s7"); + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v28, v28, v28 \n\t" + + "vsetvli t0, zero, e8, m1 \n\t" + "vmv.v.i v13, 3 \n\t" + "li s1, 24 \n\t" + "vsetvli t0, s1, e8, m1 \n\t" + "vmv.v.i v13, 2 \n\t" + "vsetvli t0, zero, e8, mf2 \n\t" + "vmv.v.i v13, 1 \n\t" + "vsetvli t0, zero, e8, mf4 \n\t" + "vmv.v.i v13, 0 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 16 \n\t" + "addi s3, %[B], 32 \n\t" + "addi s4, %[B], 48 \n\t" + + "addi s7, %[B], 64 \n\t" + + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + "LOOP_K%=: \n\t" + "vle32.v v8, (s1) \n\t" + "addi s1, s1, 80 \n\t" + "vle32.v v9, (s2) \n\t" + "addi s2, s2, 96 \n\t" + "vle32.v v10, (s3) \n\t" + "addi s3, s3, 112 \n\t" + "vle32.v v11, (s4) \n\t" + "addi s4, s4, 128 \n\t" + + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + + SQ4BIT_KERNEL_LOAD_ZP_16X1 + + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vsub.vv v0, v0, v8 \n\t" + "vsub.vv v4, v4, v8 \n\t" + "vsub.vv v1, v1, v9 \n\t" + "vsub.vv v5, v5, v9 \n\t" + "vsub.vv v2, v2, v10 \n\t" + "vsub.vv v6, v6, v10 \n\t" + "vsub.vv v3, v3, v11 \n\t" + "vsub.vv v7, v7, v11 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_1X4X4 + "addi s7, s1, 64 \n\t" + + "bnez %[CNT], LOOP_K%= \n\t" + + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6", "s7"); + } + } + } else { + for (size_t n = 0; n < CountN; n += 16) { + size_t nblks = (CountN - n) > 16 ? 16 : CountN - n; + std::byte * QuantBDataPtr = (std::byte *) QuantBData + // + n * BlockCountK * BlkLen / 2 + // b data + n * BlockCountK * sizeof(float); // scale + float * CPtr = C + n; + size_t cnt = BlockCountK; + if (Bias != nullptr) { + const float * bias = Bias + n; + __asm__ volatile( + "addi t3, %[NBLKS], 0 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 16 \n\t" + "addi s3, %[B], 32 \n\t" + "addi s4, %[B], 48 \n\t" + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v28, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v29, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v30, (%[BIAS]) \n\t" + "sub t3, t3, t0 \n\t" + "addi %[BIAS], %[BIAS], 16 \n\t" + "vsetvli t0, t3, e32, mf2 \n\t" + "vle32.v v31, (%[BIAS]) \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + "LOOP_K%=: \n\t" + "vle32.v v8, (s1) \n\t" + "addi s1, s1, 64 \n\t" + "vle32.v v9, (s2) \n\t" + "addi s2, s2, 80 \n\t" + "vle32.v v10, (s3) \n\t" + "addi s3, s3, 96 \n\t" + "vle32.v v11, (s4) \n\t" + "addi s4, s4, 112 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vadd.vi v0, v0, -8 \n\t" + "vadd.vi v1, v1, -8 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_1X4X4 + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks), [BIAS] "+r"(bias) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6"); + } else { + __asm__ volatile( + "vsetvli t0, zero, e32, m4 \n\t" + "vxor.vv v28, v28, v28 \n\t" + "addi s1, %[B], 0 \n\t" + "addi s2, %[B], 16 \n\t" + "addi s3, %[B], 32 \n\t" + "addi s4, %[B], 48 \n\t" + + "addi s5, %[A], 0 \n\t" + "addi s6, %[A], 12 \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + "LOOP_K%=: \n\t" + "vle32.v v8, (s1) \n\t" + "addi s1, s1, 64 \n\t" + "vle32.v v9, (s2) \n\t" + "addi s2, s2, 80 \n\t" + "vle32.v v10, (s3) \n\t" + "addi s3, s3, 96 \n\t" + "vle32.v v11, (s4) \n\t" + "addi s4, s4, 112 \n\t" + "flw f1, (s5) \n\t" + "addi s5, s5, 4 \n\t" + + "addi t5, %[INNER], 0 \n\t" + "vxor.vv v16, v16, v16 \n\t" + "vxor.vv v18, v18, v18 \n\t" + "vxor.vv v20, v20, v20 \n\t" + "vxor.vv v22, v22, v22 \n\t" + "vfmul.vf v24, v8, f1 \n\t" + "vfmul.vf v25, v9, f1 \n\t" + "vfmul.vf v26, v10, f1 \n\t" + "vfmul.vf v27, v11, f1 \n\t" + "addi %[CNT], %[CNT], -1 \n\t" + "vsetvli t0, zero, e8, m1 \n\t" + "LOOP_INNER%=: \n\t" + + SQ4BIT_KERNEL_LOAD_1x8x2_4X8X4 + + "vadd.vi v0, v0, -8 \n\t" + "vadd.vi v1, v1, -8 \n\t" + "vadd.vi v2, v2, -8 \n\t" + "vadd.vi v3, v3, -8 \n\t" + "vadd.vi v4, v4, -8 \n\t" + "vadd.vi v5, v5, -8 \n\t" + "vadd.vi v6, v6, -8 \n\t" + "vadd.vi v7, v7, -8 \n\t" + + SQ4BIT_KERNEL_COMP_1x8x2_4X8X4 + + "bnez t5, LOOP_INNER%= \n\t" + "vsetvli t0, zero, e32, mf2 \n\t" + + SQ4BIT_KERNEL_ACC_1X4X4 + + "bnez %[CNT], LOOP_K%= \n\t" + "addi t3, zero, 16 \n\t" + "addi s1, %[C], 16 \n\t" + "addi s2, %[C], 32 \n\t" + "addi s3, %[C], 48 \n\t" + "blt %[NBLKS], t3, ST_TAIL%= \n\t" + "vse32.v v28, (%[C]) \n\t" + "vse32.v v29, (s1) \n\t" + "vse32.v v30, (s2) \n\t" + "vse32.v v31, (s3) \n\t" + "jal x0, END%= \n\t" + + "ST_TAIL%=: \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v28, (%[C]) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v29, (s1) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v30, (s2) \n\t" + "vsetvli t0, %[NBLKS], e32, mf2 \n\t" + "sub %[NBLKS], %[NBLKS], t0 \n\t" + "vse32.v v31, (s3) \n\t" + "END%=: \n\t" + + : [CNT] "+r"(cnt), [NBLKS] "+r"(nblks) + : [INNER] "r"(INNER), [A] "r"(QuantA), [B] "r"(QuantBDataPtr), [C] "r"(CPtr) + : "cc", "t0", "t5", "t3", "f1", "s1", "s2", "s3", "s4", "s5", "s6"); + } + } + } +} + +template +inline void SQ4BitGemmM4Kernel_CompInt8_DispatchOnBlkLen(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountM, + size_t CountN, + size_t BlockStrideQuantB, + const float * Bias, + const size_t ldc, + const size_t scalestride) { + if (scalestride == 4) { + SQ4BitGemmM4Kernel_CompInt8_Impl(BlkLen, QuantA, QuantBData, QuantBScale, QuantBZeroPoint, C, + CountN, BlockStrideQuantB, Bias, ldc); + + } else if (scalestride == 2) { + SQ4BitGemmM4Kernel_CompInt8_ScaleFp16_Impl( + BlkLen, QuantA, QuantBData, QuantBScale, QuantBZeroPoint, C, CountN, BlockStrideQuantB, Bias, ldc); + } +} + +template +inline void SQ4BitGemmM1Kernel_CompInt8_DispatchOnBlkLen(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountM, + size_t CountN, + size_t BlockStrideQuantB, + const float * Bias, + const size_t ldc, + const size_t scalestride) { + if (scalestride == 4) { + SQ4BitGemmM1Kernel_CompInt8_Impl(BlkLen, QuantA, QuantBData, QuantBScale, QuantBZeroPoint, C, + CountN, BlockStrideQuantB, Bias); + } else if (scalestride == 2) { + SQ4BitGemmM1Kernel_CompInt8_ScaleFp16_Impl(BlkLen, QuantA, QuantBData, QuantBScale, + QuantBZeroPoint, C, CountN, BlockStrideQuantB, Bias); + } +} + +} // namespace + +namespace ime1 { +size_t gemm_kernel_i8i4(size_t BlkLen, + const std::byte * QuantA, + const std::byte * QuantBData, + const float * QuantBScale, + const std::byte * QuantBZeroPoint, + float * C, + size_t CountM, + size_t CountN, + size_t CountK, + size_t BlockCountK, + size_t ldc, + const float * Bias, + const size_t ScaleStride) { + GGML_UNUSED(CountM); + GGML_UNUSED(CountK); + GGML_UNUSED(ldc); + if (CountM >= 4) { + if (QuantBZeroPoint != nullptr) { + SQ4BitGemmM4Kernel_CompInt8_DispatchOnBlkLen(BlkLen, QuantA, QuantBData, QuantBScale, QuantBZeroPoint, + C, CountM, CountN, BlockCountK, Bias, ldc, ScaleStride); + } else { + SQ4BitGemmM4Kernel_CompInt8_DispatchOnBlkLen(BlkLen, QuantA, QuantBData, QuantBScale, + QuantBZeroPoint, C, CountM, CountN, BlockCountK, Bias, + ldc, ScaleStride); + } + return 4; + } else { + if (QuantBZeroPoint != nullptr) { + SQ4BitGemmM1Kernel_CompInt8_DispatchOnBlkLen(BlkLen, QuantA, QuantBData, QuantBScale, QuantBZeroPoint, + C, CountM, CountN, BlockCountK, Bias, ldc, ScaleStride); + } else { + SQ4BitGemmM1Kernel_CompInt8_DispatchOnBlkLen(BlkLen, QuantA, QuantBData, QuantBScale, + QuantBZeroPoint, C, CountM, CountN, BlockCountK, Bias, + ldc, ScaleStride); + } + return 1; + } +} +} // namespace ime1 +} // namespace sqnbitgemm_spacemit_ime diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime_kernels.h 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime_kernels.h --- 5882+dfsg-2/ggml/src/ggml-cpu/spacemit/ime_kernels.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/spacemit/ime_kernels.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,26 @@ +#pragma once + +#include + +namespace sqnbitgemm_spacemit_ime { +namespace ime1 { +size_t gemm_kernel_i8i4(size_t blk_len, + const std::byte * quant_a_ptr, + const std::byte * quant_b_data, + const float * quant_b_scale, + const std::byte * quant_b_zp, + float * c_ptr, + size_t count_m, + size_t count_n, + size_t count_k, + size_t block_count_k, + size_t ldc, + const float * bias, + const size_t scale_stride); + +void quantize_a_row_i8(size_t blk_len, const float * a_ptr, size_t count_k, std::byte * quant_a_ptr); + +void quantize_a_4row_i8(size_t blk_len, const float * a_ptr, size_t count_k, std::byte * quant_a_ptr); + +} // namespace ime1 +} // namespace sqnbitgemm_spacemit_ime diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/traits.cpp 6641+dfsg-2/ggml/src/ggml-cpu/traits.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/traits.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/traits.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -10,7 +10,7 @@ extra_buffer_type::~extra_buffer_type() } // namespace ggml::cpu bool ggml_cpu_extra_compute_forward(struct ggml_compute_params * params, struct ggml_tensor * op) { - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { + for (auto extra : ggml_backend_cpu_get_extra_buffer_types()) { if (extra && extra->context) { auto buf_extra = (ggml::cpu::extra_buffer_type *) extra->context; auto tensor_traits = buf_extra->get_tensor_traits(op); @@ -23,7 +23,7 @@ bool ggml_cpu_extra_compute_forward(stru } bool ggml_cpu_extra_work_size(int n_threads, const struct ggml_tensor * op, size_t * size) { - for (auto extra : ggml_backend_cpu_get_extra_buffers_type()) { + for (auto extra : ggml_backend_cpu_get_extra_buffer_types()) { if (extra && extra->context) { auto buf_extra = (ggml::cpu::extra_buffer_type *) extra->context; auto tensor_traits = buf_extra->get_tensor_traits(op); diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/traits.h 6641+dfsg-2/ggml/src/ggml-cpu/traits.h --- 5882+dfsg-2/ggml/src/ggml-cpu/traits.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/traits.h 2025-09-30 07:36:33.000000000 +0000 @@ -33,6 +33,6 @@ class extra_buffer_type { } // namespace ggml::cpu // implemented in ggml-cpu.cpp. -std::vector & ggml_backend_cpu_get_extra_buffers_type(); +std::vector & ggml_backend_cpu_get_extra_buffer_types(); #endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/vec.cpp 6641+dfsg-2/ggml/src/ggml-cpu/vec.cpp --- 5882+dfsg-2/ggml/src/ggml-cpu/vec.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/vec.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -84,6 +84,22 @@ void ggml_vec_dot_f32(int n, float * GGM } // reduce sum1,sum2 to sum1 GGML_F32_VEC_REDUCE(sumf, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8); + #elif defined(__riscv_v_intrinsic) + int vl = __riscv_vsetvlmax_e32m8(); + vfloat32m1_t vs = __riscv_vfmv_v_f_f32m1(0.0f, 1); + vfloat32m8_t vsum; + vfloat32m8_t ax; + vfloat32m8_t ay; + vsum = __riscv_vfmv_v_f_f32m8_tu(vsum, 0.0f, vl); + for (int i = 0; i < n; i += vl) { + vl = __riscv_vsetvl_e32m8(n - i); + ax = __riscv_vle32_v_f32m8_tu(ax, &x[i], vl); + ay = __riscv_vle32_v_f32m8_tu(ay, &y[i], vl); + vsum = __riscv_vfmacc_vv_f32m8_tu(vsum, ax, ay, vl); + } + vl = __riscv_vsetvlmax_e32m8(); + vs = __riscv_vfredusum_vs_f32m8_f32m1(vsum, vs, vl); + sumf += __riscv_vfmv_f_s_f32m1_f32(vs); #else const int np = (n & ~(GGML_F32_STEP - 1)); @@ -197,35 +213,125 @@ void ggml_vec_dot_f16(int n, float * GGM ggml_float sumf = 0.0; + #if defined(GGML_SIMD) - const int np = (n & ~(GGML_F16_STEP - 1)); + #if defined(__ARM_FEATURE_SVE) + const int sve_register_length = svcntb() * 8; //get vector length + const int ggml_f16_epr = sve_register_length / 16; // running when 16 + const int ggml_f16_step = 8 * ggml_f16_epr; // choose 8 SVE registers + + const int np= (n & ~(ggml_f16_step - 1)); + svfloat16_t sum1 = svdup_n_f16(0.0f); + svfloat16_t sum2 = svdup_n_f16(0.0f); + svfloat16_t sum3 = svdup_n_f16(0.0f); + svfloat16_t sum4 = svdup_n_f16(0.0f); + + svfloat16_t ax1, ax2, ax3, ax4, ax5, ax6, ax7, ax8; + svfloat16_t ay1, ay2, ay3, ay4, ay5, ay6, ay7, ay8; + for (int i = 0; i < np; i += ggml_f16_step) { + ax1 = GGML_F16x_VEC_LOAD(x + i + 0 * ggml_f16_epr, 0); + ay1 = GGML_F16x_VEC_LOAD(y + i + 0 * ggml_f16_epr, 0); + sum1 = GGML_F16x_VEC_FMA(sum1, ax1, ay1); + + ax2 = GGML_F16x_VEC_LOAD(x + i + 1 * ggml_f16_epr, 1); + ay2 = GGML_F16x_VEC_LOAD(y + i + 1 * ggml_f16_epr, 1); + sum2 = GGML_F16x_VEC_FMA(sum2, ax2, ay2); + + ax3 = GGML_F16x_VEC_LOAD(x + i + 2 * ggml_f16_epr, 2); + ay3 = GGML_F16x_VEC_LOAD(y + i + 2 * ggml_f16_epr, 2); + sum3 = GGML_F16x_VEC_FMA(sum3, ax3, ay3); + + ax4 = GGML_F16x_VEC_LOAD(x + i + 3 * ggml_f16_epr, 3); + ay4 = GGML_F16x_VEC_LOAD(y + i + 3 * ggml_f16_epr, 3); + sum4 = GGML_F16x_VEC_FMA(sum4, ax4, ay4); + + ax5 = GGML_F16x_VEC_LOAD(x + i + 4 * ggml_f16_epr, 4); + ay5 = GGML_F16x_VEC_LOAD(y + i + 4 * ggml_f16_epr, 4); + sum1 = GGML_F16x_VEC_FMA(sum1, ax5, ay5); + + ax6 = GGML_F16x_VEC_LOAD(x + i + 5 * ggml_f16_epr, 5); + ay6 = GGML_F16x_VEC_LOAD(y + i + 5 * ggml_f16_epr, 5); + sum2 = GGML_F16x_VEC_FMA(sum2, ax6, ay6); + + ax7 = GGML_F16x_VEC_LOAD(x + i + 6 * ggml_f16_epr, 6); + ay7 = GGML_F16x_VEC_LOAD(y + i + 6 * ggml_f16_epr, 6); + sum3 = GGML_F16x_VEC_FMA(sum3, ax7, ay7); + + ax8 = GGML_F16x_VEC_LOAD(x + i + 7 * ggml_f16_epr, 7); + ay8 = GGML_F16x_VEC_LOAD(y + i + 7 * ggml_f16_epr, 7); + sum4 = GGML_F16x_VEC_FMA(sum4, ax8, ay8); + } - GGML_F16_VEC sum[GGML_F16_ARR] = { GGML_F16_VEC_ZERO }; + const int np2 = (n & ~(ggml_f16_epr - 1)); // round down to multiple of 8 + for (int k = np; k < np2; k += ggml_f16_epr) { + svfloat16_t rx = GGML_F16x_VEC_LOAD(x + k, 0); + svfloat16_t ry = GGML_F16x_VEC_LOAD(y + k, 0); + sum1 = GGML_F16x_VEC_FMA(sum1, rx, ry); + } - GGML_F16_VEC ax[GGML_F16_ARR]; - GGML_F16_VEC ay[GGML_F16_ARR]; + if (np2 < n) { + svbool_t pg = svwhilelt_b16(np2, n); + svfloat16_t hx = svld1_f16(pg, (const __fp16 *)(x + np2)); + svfloat16_t hy = svld1_f16(pg, (const __fp16 *)(y + np2)); - for (int i = 0; i < np; i += GGML_F16_STEP) { - for (int j = 0; j < GGML_F16_ARR; j++) { - ax[j] = GGML_F16_VEC_LOAD(x + i + j*GGML_F16_EPR, j); - ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); + sum1 = svmad_f16_x(pg, hx, hy, sum1); + } + GGML_F16x_VEC_REDUCE(sumf, sum1, sum2, sum3, sum4); + #elif defined(__riscv_v_intrinsic) + #if defined(__riscv_zvfh) + int vl = __riscv_vsetvlmax_e32m2(); + vfloat32m1_t vs = __riscv_vfmv_v_f_f32m1(0.0f, 1); + vfloat32m2_t vsum; + vfloat16m1_t ax; + vfloat16m1_t ay; + vsum = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vmv_v_x_u32m2(0, vl)); + for (int i = 0; i < n; i += vl) { + vl = __riscv_vsetvl_e16m1(n - i); + ax = __riscv_vle16_v_f16m1_tu(ax, (const _Float16 *)&x[i], vl); + ay = __riscv_vle16_v_f16m1_tu(ay, (const _Float16 *)&y[i], vl); + vsum = __riscv_vfwmacc_vv_f32m2_tu(vsum, ax, ay, vl); + } + vl = __riscv_vsetvlmax_e32m1(); + vfloat32m1_t ac0 = __riscv_vfadd_vv_f32m1(__riscv_vget_v_f32m2_f32m1(vsum, 0), __riscv_vget_v_f32m2_f32m1(vsum, 1), vl); + vs = __riscv_vfredusum_vs_f32m1_f32m1(ac0, vs, vl); + sumf += __riscv_vfmv_f_s_f32m1_f32(vs); + #else + for (int i = 0; i < n; ++i) { + sumf += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[i])*GGML_CPU_FP16_TO_FP32(y[i])); + } + #endif // __riscv_zvfh + #else + const int np = (n & ~(GGML_F16_STEP - 1)); + + GGML_F16_VEC sum[GGML_F16_ARR] = { GGML_F16_VEC_ZERO }; + + GGML_F16_VEC ax[GGML_F16_ARR]; + GGML_F16_VEC ay[GGML_F16_ARR]; - sum[j] = GGML_F16_VEC_FMA(sum[j], ax[j], ay[j]); + for (int i = 0; i < np; i += GGML_F16_STEP) { + for (int j = 0; j < GGML_F16_ARR; j++) { + ax[j] = GGML_F16_VEC_LOAD(x + i + j*GGML_F16_EPR, j); + ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); + + sum[j] = GGML_F16_VEC_FMA(sum[j], ax[j], ay[j]); + } } - } - // reduce sum0..sum3 to sum0 - GGML_F16_VEC_REDUCE(sumf, sum); + // reduce sum0..sum3 to sum0 + GGML_F16_VEC_REDUCE(sumf, sum); - // leftovers - for (int i = np; i < n; ++i) { - sumf += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[i])*GGML_CPU_FP16_TO_FP32(y[i])); - } + // leftovers + for (int i = np; i < n; ++i) { + sumf += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[i])*GGML_CPU_FP16_TO_FP32(y[i])); + } + // if you hit this, you are likely running outside the FP range + assert(!isnan(sumf) && !isinf(sumf)); + #endif #else for (int i = 0; i < n; ++i) { sumf += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[i])*GGML_CPU_FP16_TO_FP32(y[i])); } -#endif +#endif // GGML_SIMD *s = sumf; } @@ -244,6 +350,12 @@ void ggml_vec_silu_f32(const int n, floa for (; i + 3 < n; i += 4) { _mm_storeu_ps(y + i, ggml_v_silu(_mm_loadu_ps(x + i))); } +#elif defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + const int vlen = svcntw(); + for (; i < n; i += vlen) { + const svbool_t pg = svwhilelt_b32_s32(i, n); + svst1_f32(pg, y + i, ggml_v_silu(pg, svld1_f32(pg, x + i))); + } #elif defined(__ARM_NEON) && defined(__aarch64__) for (; i + 3 < n; i += 4) { vst1q_f32(y + i, ggml_v_silu(vld1q_f32(x + i))); @@ -268,10 +380,24 @@ void ggml_vec_swiglu_f32(const int n, fl for (; i + 3 < n; i += 4) { _mm_storeu_ps(y + i, _mm_mul_ps(ggml_v_silu(_mm_loadu_ps(x + i)), _mm_loadu_ps(g + i))); } +#elif defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + const int vlen = svcntw(); + for (; i < n; i += vlen) { + const svbool_t pg = svwhilelt_b32_s32(i, n); + svst1_f32(pg, y + i, svmul_f32_x(pg, ggml_v_silu(pg, svld1_f32(pg, x + i)), svld1_f32(pg, g + i))); + } #elif defined(__ARM_NEON) && defined(__aarch64__) for (; i + 3 < n; i += 4) { vst1q_f32(y + i, vmulq_f32(ggml_v_silu(vld1q_f32(x + i)), vld1q_f32(g + i))); } +#elif defined(__riscv_v_intrinsic) + for (int vl; i < n; i += vl) { + vl = __riscv_vsetvl_e32m2(n - i); + vfloat32m2_t vx = __riscv_vle32_v_f32m2(&x[i], vl); + vfloat32m2_t vg = __riscv_vle32_v_f32m2(&g[i], vl); + vfloat32m2_t vy = __riscv_vfmul_vv_f32m2(ggml_v_silu_m2(vx, vl), vg, vl); + __riscv_vse32_v_f32m2(&y[i], vy, vl); + } #endif for (; i < n; ++i) { y[i] = ggml_silu_f32(x[i]) * g[i]; @@ -315,6 +441,15 @@ ggml_float ggml_vec_soft_max_f32(const i #endif sum += (ggml_float)_mm_cvtss_f32(val); } +#elif defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + const int vlen = svcntw(); + for (; i < n; i += vlen) { + const svbool_t pg = svwhilelt_b32_s32(i, n); + svfloat32_t val = ggml_v_expf(pg, svsub_f32_x(pg, svld1_f32(pg, x + i), + svdup_n_f32_x(pg, max))); + svst1_f32(pg, y + i, val); + sum += (ggml_float)svaddv_f32(pg, val); + } #elif defined(__ARM_NEON) && defined(__aarch64__) for (; i + 3 < n; i += 4) { float32x4_t val = ggml_v_expf(vsubq_f32(vld1q_f32(x + i), @@ -322,6 +457,15 @@ ggml_float ggml_vec_soft_max_f32(const i vst1q_f32(y + i, val); sum += (ggml_float)vaddvq_f32(val); } +#elif defined(__riscv_v_intrinsic) + vfloat64m1_t vsum = __riscv_vfmv_v_f_f64m1(0, 1); + for (int avl; i < n; i += avl) { + avl = __riscv_vsetvl_e32m2(n - i); + vfloat32m2_t val = ggml_v_expf_m2(__riscv_vfsub_vf_f32m2(__riscv_vle32_v_f32m2(&x[i], avl), max, avl), avl); + __riscv_vse32_v_f32m2(&y[i], val, avl); + vsum = __riscv_vfwredusum_vs_f32m2_f64m1(val, vsum, avl); + } + return (ggml_float)__riscv_vfmv_f_s_f64m1_f64(vsum); #endif for (; i < n; ++i) { float val = expf(x[i] - max); diff -pruN 5882+dfsg-2/ggml/src/ggml-cpu/vec.h 6641+dfsg-2/ggml/src/ggml-cpu/vec.h --- 5882+dfsg-2/ggml/src/ggml-cpu/vec.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cpu/vec.h 2025-09-30 07:36:33.000000000 +0000 @@ -55,7 +55,22 @@ inline static void ggml_vec_cpy_i32(cons inline static void ggml_vec_set_f16(const int n, ggml_fp16_t * x, const ggml_fp16_t v) { for (int i = 0; i < n; ++i) x[i] = v; } inline static void ggml_vec_set_bf16(const int n, ggml_bf16_t * x, const ggml_bf16_t v) { for (int i = 0; i < n; ++i) x[i] = v; } -inline static void ggml_vec_add_f32 (const int n, float * z, const float * x, const float * y) { for (int i = 0; i < n; ++i) z[i] = x[i] + y[i]; } + +inline static void ggml_vec_add_f32 (const int n, float * z, const float * x, const float * y) { + int i = 0; +#if defined(__AVX2__) + for (; i + 7 < n; i += 8) { + __m256 vx = _mm256_loadu_ps(x + i); + __m256 vy = _mm256_loadu_ps(y + i); + __m256 vz = _mm256_add_ps(vx, vy); + _mm256_storeu_ps(z + i, vz); + } +#endif + for (; i < n; ++i) { + z[i] = x[i] + y[i]; + } +} + inline static void ggml_vec_add_f16 (const int n, ggml_fp16_t * z, const ggml_fp16_t * x, const ggml_fp16_t * y) { for (int i = 0; i < n; ++i) { z[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(x[i]) + GGML_CPU_FP16_TO_FP32(y[i])); @@ -104,36 +119,149 @@ inline static void ggml_vec_dot_f16_unro } #if defined(GGML_SIMD) - const int np = (n & ~(GGML_F16_STEP - 1)); + #if defined(__ARM_FEATURE_SVE) + + const int sve_register_length = svcntb() * 8; + const int ggml_f16_epr = sve_register_length / 16; // running when 16 + const int ggml_f16_step = 8 * ggml_f16_epr; // choose 8 SVE registers + + const int np = (n & ~(ggml_f16_step - 1)); + + svfloat16_t sum_00 = svdup_n_f16(0.0f); + svfloat16_t sum_01 = svdup_n_f16(0.0f); + svfloat16_t sum_02 = svdup_n_f16(0.0f); + svfloat16_t sum_03 = svdup_n_f16(0.0f); + + svfloat16_t sum_10 = svdup_n_f16(0.0f); + svfloat16_t sum_11 = svdup_n_f16(0.0f); + svfloat16_t sum_12 = svdup_n_f16(0.0f); + svfloat16_t sum_13 = svdup_n_f16(0.0f); + + svfloat16_t ax1, ax2, ax3, ax4, ax5, ax6, ax7, ax8; + svfloat16_t ay1, ay2, ay3, ay4, ay5, ay6, ay7, ay8; + + for (int i = 0; i < np; i += ggml_f16_step) { + ay1 = GGML_F16x_VEC_LOAD(y + i + 0 * ggml_f16_epr, 0); // 8 elements + + ax1 = GGML_F16x_VEC_LOAD(x[0] + i + 0*ggml_f16_epr, 0); // 8 elemnst + sum_00 = GGML_F16x_VEC_FMA(sum_00, ax1, ay1); // sum_00 = sum_00+ax1*ay1 + ax1 = GGML_F16x_VEC_LOAD(x[1] + i + 0*ggml_f16_epr, 0); // 8 elements + sum_10 = GGML_F16x_VEC_FMA(sum_10, ax1, ay1); + + ay2 = GGML_F16x_VEC_LOAD(y + i + 1 * ggml_f16_epr, 1); // next 8 elements + + ax2 = GGML_F16x_VEC_LOAD(x[0] + i + 1*ggml_f16_epr, 1); // next 8 ekements + sum_01 = GGML_F16x_VEC_FMA(sum_01, ax2, ay2); + ax2 = GGML_F16x_VEC_LOAD(x[1] + i + 1*ggml_f16_epr, 1); + sum_11 = GGML_F16x_VEC_FMA(sum_11, ax2, ay2); + + ay3 = GGML_F16x_VEC_LOAD(y + i + 2 * ggml_f16_epr, 2); + + ax3 = GGML_F16x_VEC_LOAD(x[0] + i + 2*ggml_f16_epr, 2); + sum_02 = GGML_F16x_VEC_FMA(sum_02, ax3, ay3); + ax1 = GGML_F16x_VEC_LOAD(x[1] + i + 2*ggml_f16_epr, 2); + sum_12 = GGML_F16x_VEC_FMA(sum_12, ax3, ay3); + + ay4 = GGML_F16x_VEC_LOAD(y + i + 3 * ggml_f16_epr, 3); + + ax4 = GGML_F16x_VEC_LOAD(x[0] + i + 3*ggml_f16_epr, 3); + sum_03 = GGML_F16x_VEC_FMA(sum_03, ax4, ay4); + ax4 = GGML_F16x_VEC_LOAD(x[1] + i + 3*ggml_f16_epr, 3); + sum_13 = GGML_F16x_VEC_FMA(sum_13, ax4, ay4); + + ay5 = GGML_F16x_VEC_LOAD(y + i + 4 * ggml_f16_epr, 4); + + ax5 = GGML_F16x_VEC_LOAD(x[0] + i + 4*ggml_f16_epr, 4); + + sum_00 = GGML_F16x_VEC_FMA(sum_00, ax5, ay5); + ax5 = GGML_F16x_VEC_LOAD(x[1] + i + 4*ggml_f16_epr, 4); + sum_10 = GGML_F16x_VEC_FMA(sum_10, ax5, ay5); + + ay6 = GGML_F16x_VEC_LOAD(y + i + 5 * ggml_f16_epr, 5); + + ax6 = GGML_F16x_VEC_LOAD(x[0] + i + 5*ggml_f16_epr, 5); + + sum_01 = GGML_F16x_VEC_FMA(sum_01, ax6, ay6); + ax6 = GGML_F16x_VEC_LOAD(x[1] + i + 5*ggml_f16_epr, 5); + sum_11 = GGML_F16x_VEC_FMA(sum_11, ax6, ay6); + + ay7 = GGML_F16x_VEC_LOAD(y + i + 6 * ggml_f16_epr, 6); + + ax7 = GGML_F16x_VEC_LOAD(x[0] + i + 6*ggml_f16_epr, 6); + + sum_02 = GGML_F16x_VEC_FMA(sum_02, ax7, ay7); + ax7 = GGML_F16x_VEC_LOAD(x[1] + i + 6*ggml_f16_epr, 6); + sum_12 = GGML_F16x_VEC_FMA(sum_12, ax7, ay7); + + ay8 = GGML_F16x_VEC_LOAD(y + i + 7 * ggml_f16_epr, 7); + + ax8 = GGML_F16x_VEC_LOAD(x[0] + i + 7*ggml_f16_epr, 7); + + sum_03 = GGML_F16x_VEC_FMA(sum_03, ax8, ay8); + ax8 = GGML_F16x_VEC_LOAD(x[1] + i + 7*ggml_f16_epr, 7); + sum_13 = GGML_F16x_VEC_FMA(sum_13, ax8, ay8); + } + + const int np2 = (n & ~(ggml_f16_epr - 1)); + for (int k = np; k < np2; k += ggml_f16_epr) { + svfloat16_t ry = GGML_F16x_VEC_LOAD(y + k, 0); + + svfloat16_t rx = GGML_F16x_VEC_LOAD(x[0] + k, 0); + sum_00 = GGML_F16x_VEC_FMA(sum_00, rx, ry); + rx = GGML_F16x_VEC_LOAD(x[1] + k, 0); + sum_10 = GGML_F16x_VEC_FMA(sum_10, rx, ry); + } - GGML_F16_VEC sum[GGML_VEC_DOT_UNROLL][GGML_F16_ARR] = { { GGML_F16_VEC_ZERO } }; + if (np2 < n) { + svbool_t pg = svwhilelt_b16(np2, n); + svfloat16_t hx_0 = svld1_f16(pg, (const __fp16 *)(x[0] + np2)); + svfloat16_t hx_1 = svld1_f16(pg, (const __fp16 *)(x[1] + np2)); + svfloat16_t hy = svld1_f16(pg, (const __fp16 *)(y + np2)); + + sum_00 = svmad_f16_x(pg, hx_0, hy, sum_00); + sum_10 = svmad_f16_x(pg, hx_1, hy, sum_10); + } + GGML_F16x_VEC_REDUCE(sumf[0], sum_00, sum_01, sum_02, sum_03); + GGML_F16x_VEC_REDUCE(sumf[1], sum_10, sum_11, sum_12, sum_13); + #elif defined(__riscv_v_intrinsic) + // todo: RVV impl + for (int i = 0; i < n; ++i) { + for (int j = 0; j < GGML_VEC_DOT_UNROLL; ++j) { + sumf[j] += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[j][i])*GGML_CPU_FP16_TO_FP32(y[i])); + } + } + #else + const int np = (n & ~(GGML_F16_STEP - 1)); - GGML_F16_VEC ax[GGML_F16_ARR]; - GGML_F16_VEC ay[GGML_F16_ARR]; + GGML_F16_VEC sum[GGML_VEC_DOT_UNROLL][GGML_F16_ARR] = { { GGML_F16_VEC_ZERO } }; - for (int i = 0; i < np; i += GGML_F16_STEP) { - for (int j = 0; j < GGML_F16_ARR; j++) { - ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); + GGML_F16_VEC ax[GGML_F16_ARR]; + GGML_F16_VEC ay[GGML_F16_ARR]; - for (int k = 0; k < GGML_VEC_DOT_UNROLL; ++k) { - ax[j] = GGML_F16_VEC_LOAD(x[k] + i + j*GGML_F16_EPR, j); + for (int i = 0; i < np; i += GGML_F16_STEP) { + for (int j = 0; j < GGML_F16_ARR; j++) { + ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); - sum[k][j] = GGML_F16_VEC_FMA(sum[k][j], ax[j], ay[j]); + for (int k = 0; k < GGML_VEC_DOT_UNROLL; ++k) { + ax[j] = GGML_F16_VEC_LOAD(x[k] + i + j*GGML_F16_EPR, j); + + sum[k][j] = GGML_F16_VEC_FMA(sum[k][j], ax[j], ay[j]); + } } } - } - // reduce sum0..sum3 to sum0 - for (int k = 0; k < GGML_VEC_DOT_UNROLL; ++k) { - GGML_F16_VEC_REDUCE(sumf[k], sum[k]); - } + // reduce sum0..sum3 to sum0 + for (int k = 0; k < GGML_VEC_DOT_UNROLL; ++k) { + GGML_F16_VEC_REDUCE(sumf[k], sum[k]); + } - // leftovers - for (int i = np; i < n; ++i) { - for (int j = 0; j < GGML_VEC_DOT_UNROLL; ++j) { - sumf[j] += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[j][i])*GGML_CPU_FP16_TO_FP32(y[i])); + // leftovers + for (int i = np; i < n; ++i) { + for (int j = 0; j < GGML_VEC_DOT_UNROLL; ++j) { + sumf[j] += (ggml_float)(GGML_CPU_FP16_TO_FP32(x[j][i])*GGML_CPU_FP16_TO_FP32(y[i])); + } } - } + #endif #else for (int i = 0; i < n; ++i) { for (int j = 0; j < GGML_VEC_DOT_UNROLL; ++j) { @@ -228,6 +356,14 @@ inline static void ggml_vec_mad_f32(cons svst1_f32(pg, y + np2, ay1); } + #elif defined(__riscv_v_intrinsic) + for (int i = 0, avl; i < n; i += avl) { + avl = __riscv_vsetvl_e32m8(n - i); + vfloat32m8_t ax = __riscv_vle32_v_f32m8(&x[i], avl); + vfloat32m8_t ay = __riscv_vle32_v_f32m8(&y[i], avl); + vfloat32m8_t ny = __riscv_vfmadd_vf_f32m8(ax, v, ay, avl); + __riscv_vse32_v_f32m8(&y[i], ny, avl); + } #else const int np = (n & ~(GGML_F32_STEP - 1)); @@ -261,27 +397,112 @@ inline static void ggml_vec_mad_f32(cons inline static void ggml_vec_mad_f16(const int n, ggml_fp16_t * GGML_RESTRICT y, const ggml_fp16_t * GGML_RESTRICT x, const float v) { #if defined(GGML_SIMD) - const int np = (n & ~(GGML_F16_STEP - 1)); + #if defined(__ARM_FEATURE_SVE) + const int sve_register_length = svcntb() * 8; + const int ggml_f16_epr = sve_register_length / 16; + const int ggml_f16_step = 8 * ggml_f16_epr; + + GGML_F16x_VEC vx = GGML_F16x_VEC_SET1(v); + + const int np= (n & ~(ggml_f16_step - 1)); + + svfloat16_t ax1, ax2, ax3, ax4, ax5, ax6, ax7, ax8; + svfloat16_t ay1, ay2, ay3, ay4, ay5, ay6, ay7, ay8; + for (int i = 0; i < np; i += ggml_f16_step) { + ax1 = GGML_F16x_VEC_LOAD(x + i + 0 * ggml_f16_epr, 0); + ay1 = GGML_F16x_VEC_LOAD(y + i + 0 * ggml_f16_epr, 0); + ay1 = GGML_F16x_VEC_FMA(ay1, ax1, vx); + + GGML_F16x_VEC_STORE(y + i + 0 * ggml_f16_epr, ay1, 0); + + ax2 = GGML_F16x_VEC_LOAD(x + i + 1 * ggml_f16_epr, 1); + ay2 = GGML_F16x_VEC_LOAD(y + i + 1 * ggml_f16_epr, 1); + ay2 = GGML_F16x_VEC_FMA(ay2, ax2, vx); + + GGML_F16x_VEC_STORE(y + i + 1 * ggml_f16_epr, ay2, 1); + + ax3 = GGML_F16x_VEC_LOAD(x + i + 2 * ggml_f16_epr, 2); + ay3 = GGML_F16x_VEC_LOAD(y + i + 2 * ggml_f16_epr, 2); + ay3 = GGML_F16x_VEC_FMA(ay3, ax3, vx); + + GGML_F16x_VEC_STORE(y + i + 2 * ggml_f16_epr, ay3, 2); + + ax4 = GGML_F16x_VEC_LOAD(x + i + 3 * ggml_f16_epr, 3); + ay4 = GGML_F16x_VEC_LOAD(y + i + 3 * ggml_f16_epr, 3); + ay4 = GGML_F16x_VEC_FMA(ay4, ax4, vx); + + GGML_F16x_VEC_STORE(y + i + 3 * ggml_f16_epr, ay4, 3); + + ax5 = GGML_F16x_VEC_LOAD(x + i + 4 * ggml_f16_epr, 4); + ay5 = GGML_F16x_VEC_LOAD(y + i + 4 * ggml_f16_epr, 4); + ay5 = GGML_F16x_VEC_FMA(ay5, ax5, vx); + + GGML_F16x_VEC_STORE(y + i + 4 * ggml_f16_epr, ay5, 4); - GGML_F16_VEC vx = GGML_F16_VEC_SET1(v); + ax6 = GGML_F16x_VEC_LOAD(x + i + 5 * ggml_f16_epr, 5); + ay6 = GGML_F16x_VEC_LOAD(y + i + 5 * ggml_f16_epr, 5); + ay6 = GGML_F16x_VEC_FMA(ay6, ax6, vx); - GGML_F16_VEC ax[GGML_F16_ARR]; - GGML_F16_VEC ay[GGML_F16_ARR]; + GGML_F16x_VEC_STORE(y + i + 5 * ggml_f16_epr, ay6, 5); - for (int i = 0; i < np; i += GGML_F16_STEP) { - for (int j = 0; j < GGML_F16_ARR; j++) { - ax[j] = GGML_F16_VEC_LOAD(x + i + j*GGML_F16_EPR, j); - ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); - ay[j] = GGML_F16_VEC_FMA(ay[j], ax[j], vx); + ax7 = GGML_F16x_VEC_LOAD(x + i + 6 * ggml_f16_epr, 6); + ay7 = GGML_F16x_VEC_LOAD(y + i + 6 * ggml_f16_epr, 6); + ay7 = GGML_F16x_VEC_FMA(ay7, ax7, vx); - GGML_F16_VEC_STORE(y + i + j*GGML_F16_EPR, ay, j); + GGML_F16x_VEC_STORE(y + i + 6 * ggml_f16_epr, ay7, 6); + + ax8 = GGML_F16x_VEC_LOAD(x + i + 7 * ggml_f16_epr, 7); + ay8 = GGML_F16x_VEC_LOAD(y + i + 7 * ggml_f16_epr, 7); + ay8 = GGML_F16x_VEC_FMA(ay8, ax8, vx); + + GGML_F16x_VEC_STORE(y + i + 7 * ggml_f16_epr, ay8, 7); } - } + const int np2 = (n & ~(ggml_f16_epr - 1)); + for (int k = np; k < np2; k += ggml_f16_epr) { + svfloat16_t rx = GGML_F16x_VEC_LOAD(x + k, 0); + svfloat16_t ry = GGML_F16x_VEC_LOAD(y + k, 0); + ry = GGML_F16x_VEC_FMA(ry, rx, vx); - // leftovers - for (int i = np; i < n; ++i) { - y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i]) + GGML_CPU_FP16_TO_FP32(x[i])*v); - } + GGML_F16x_VEC_STORE(y + k, ry, 0); + } + + if (np2 < n) { + svbool_t pg = svwhilelt_b16(np2, n); + svfloat16_t hx = svld1_f16(pg, (const __fp16 *)(x + np2)); + svfloat16_t hy = svld1_f16(pg, (const __fp16 *)(y + np2)); + hy = svmad_f16_x(pg, hx, vx, hy); + svst1_f16(pg, (__fp16 *)(y + np2), hy); + } + + #elif defined(__riscv_v_intrinsic) + // todo: RVV impl + // scalar + for (int i = 0; i < n; ++i) { + y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i]) + GGML_CPU_FP16_TO_FP32(x[i])*v); + } + #else + const int np = (n & ~(GGML_F16_STEP - 1)); + + GGML_F16_VEC vx = GGML_F16_VEC_SET1(v); + + GGML_F16_VEC ax[GGML_F16_ARR]; + GGML_F16_VEC ay[GGML_F16_ARR]; + + for (int i = 0; i < np; i += GGML_F16_STEP) { + for (int j = 0; j < GGML_F16_ARR; j++) { + ax[j] = GGML_F16_VEC_LOAD(x + i + j*GGML_F16_EPR, j); + ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); + ay[j] = GGML_F16_VEC_FMA(ay[j], ax[j], vx); + + GGML_F16_VEC_STORE(y + i + j*GGML_F16_EPR, ay, j); + } + } + + // leftovers + for (int i = np; i < n; ++i) { + y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i]) + GGML_CPU_FP16_TO_FP32(x[i])*v); + } + #endif #else // scalar for (int i = 0; i < n; ++i) { @@ -309,6 +530,16 @@ inline static void ggml_vec_mad_f32_unro y[i] += x[k][i]*v[k][0]; } } + #elif defined(__riscv_v_intrinsic) + for (int i = 0, avl; i < n; i += avl) { + avl = __riscv_vsetvl_e32m8(n - i); + vfloat32m8_t ay = __riscv_vle32_v_f32m8(&y[i], avl); + for (int k = 0; k < GGML_VEC_MAD_UNROLL; k++) { + vfloat32m8_t ax = __riscv_vle32_v_f32m8(&x[k][i], avl); + ay = __riscv_vfmadd_vf_f32m8(ax, v[k][0], ay, avl); + } + __riscv_vse32_v_f32m8(&y[i], ay, avl); + } #else const int np = (n & ~(GGML_F32_STEP - 1)); @@ -360,6 +591,14 @@ inline static void ggml_vec_mad1_f32(con for (int i = 0; i < n; ++i) { y[i] = x[i]*s + b; } + #elif defined(__riscv_v_intrinsic) + for (int i = 0, avl; i < n; i += avl) { + avl = __riscv_vsetvl_e32m8(n - i); + vfloat32m8_t ax = __riscv_vle32_v_f32m8(&x[i], avl); + vfloat32m8_t vb = __riscv_vfmv_v_f_f32m8(b, avl); + vfloat32m8_t ny = __riscv_vfmadd_vf_f32m8(ax, s, vb, avl); + __riscv_vse32_v_f32m8(&y[i], ny, avl); + } #else const int np = (n & ~(GGML_F32_STEP - 1)); @@ -371,7 +610,7 @@ inline static void ggml_vec_mad1_f32(con for (int i = 0; i < np; i += GGML_F32_STEP) { for (int j = 0; j < GGML_F32_ARR; j++) { ay[j] = GGML_F32_VEC_LOAD(x + i + j*GGML_F32_EPR); - ay[j] = GGML_F32_VEC_FMA(ay[j], vs, vb); + ay[j] = GGML_F32_VEC_FMA(vb, ay[j], vs); GGML_F32_VEC_STORE(y + i + j*GGML_F32_EPR, ay[j]); } @@ -421,6 +660,13 @@ inline static void ggml_vec_scale_f32(co ay1 = svmul_f32_m(pg, ay1, vx); svst1_f32(pg, y + np, ay1); } + #elif defined(__riscv_v_intrinsic) + for (int i = 0, avl; i < n; i += avl) { + avl = __riscv_vsetvl_e32m8(n - i); + vfloat32m8_t ay = __riscv_vle32_v_f32m8(&y[i], avl); + vfloat32m8_t ny = __riscv_vfmul_vf_f32m8(ay, v, avl); + __riscv_vse32_v_f32m8(&y[i], ny, avl); + } #else const int np = (n & ~(GGML_F32_STEP - 1)); @@ -452,25 +698,59 @@ inline static void ggml_vec_scale_f32(co inline static void ggml_vec_scale_f16(const int n, ggml_fp16_t * y, const float v) { #if defined(GGML_SIMD) - const int np = (n & ~(GGML_F16_STEP - 1)); + #if defined(__ARM_FEATURE_SVE) + const int sve_register_length = svcntb() * 8; + const int ggml_f16_epr = sve_register_length / 16; + const int ggml_f16_step = 2 * ggml_f16_epr; + + GGML_F16x_VEC vx = GGML_F16x_VEC_SET1(v); + const int np = (n & ~(ggml_f16_step - 1)); + svfloat16_t ay1, ay2; + + for (int i = 0; i < np; i += ggml_f16_step) { + ay1 = GGML_F16x_VEC_LOAD(y + i + 0*ggml_f16_epr, 0); + ay1 = GGML_F16x_VEC_MUL(ay1, vx); + GGML_F16x_VEC_STORE(y + i + 0*ggml_f16_epr, ay1, 0); + + ay2 = GGML_F16x_VEC_LOAD(y + i + 1*ggml_f16_epr, 1); + ay2 = GGML_F16x_VEC_MUL(ay2, vx); + GGML_F16x_VEC_STORE(y + i + 1*ggml_f16_epr, ay2, 1); + } + // leftovers + // maximum number of leftover elements will be less that ggmlF_16x_epr. Apply predicated svmad on available elements only + if (np < n) { + svbool_t pg = svwhilelt_b16(np, n); + svfloat16_t hy = svld1_f16(pg, (__fp16 *)(y + np)); + svfloat16_t out = svmul_f16_m(pg, hy, vx); + svst1_f16(pg, (__fp16 *)(y + np), out); + } + #elif defined(__riscv_v_intrinsic) + // todo: RVV impl + // scalar + for (int i = 0; i < n; ++i) { + y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i])*v); + } + #else + const int np = (n & ~(GGML_F16_STEP - 1)); - GGML_F16_VEC vx = GGML_F16_VEC_SET1(v); + GGML_F16_VEC vx = GGML_F16_VEC_SET1(v); - GGML_F16_VEC ay[GGML_F16_ARR]; + GGML_F16_VEC ay[GGML_F16_ARR]; - for (int i = 0; i < np; i += GGML_F16_STEP) { - for (int j = 0; j < GGML_F16_ARR; j++) { - ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); - ay[j] = GGML_F16_VEC_MUL(ay[j], vx); + for (int i = 0; i < np; i += GGML_F16_STEP) { + for (int j = 0; j < GGML_F16_ARR; j++) { + ay[j] = GGML_F16_VEC_LOAD(y + i + j*GGML_F16_EPR, j); + ay[j] = GGML_F16_VEC_MUL(ay[j], vx); - GGML_F16_VEC_STORE(y + i + j*GGML_F16_EPR, ay, j); + GGML_F16_VEC_STORE(y + i + j*GGML_F16_EPR, ay, j); + } } - } - // leftovers - for (int i = np; i < n; ++i) { - y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i])*v); - } + // leftovers + for (int i = np; i < n; ++i) { + y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i])*v); + } + #endif #else // scalar for (int i = 0; i < n; ++i) { @@ -722,7 +1002,39 @@ https://github.com/openvinotoolkit/openv } #endif -#if defined(__ARM_NEON) && defined(__aarch64__) +#if defined(__ARM_FEATURE_SVE) && defined(__aarch64__) + +inline static svfloat32_t ggml_v_expf(svbool_t pg, svfloat32_t x) { + const svfloat32_t r = svdup_n_f32_x(pg, 0x1.8p23f); + const svfloat32_t z = svmla_n_f32_x(pg, r, x, 0x1.715476p+0f); + const svfloat32_t n = svsub_f32_x(pg, z, r); + const svfloat32_t b = svmls_n_f32_x(pg, svmls_n_f32_x(pg, x, n, 0x1.62e4p-1f), n, 0x1.7f7d1cp-20f); + const svuint32_t e = svlsl_n_u32_x(pg, svreinterpret_u32_f32(z), 23); + const svfloat32_t k = svreinterpret_f32_u32(svadd_u32_x(pg, e, svreinterpret_u32_f32(svdup_n_f32_x(pg, 1)))); + const svbool_t c = svacgt_n_f32(pg, n, 126); + const svfloat32_t u = svmul_f32_x(pg, b, b); + const svfloat32_t j = svmla_f32_x(pg, + svmul_n_f32_x(pg, b, 0x1.ffffecp-1f), + svmla_f32_x(pg, svmla_f32_x(pg, svdup_n_f32_x(pg, 0x1.fffdb6p-2f), svdup_n_f32_x(pg, 0x1.555e66p-3f), b), + svmla_f32_x(pg, svdup_n_f32_x(pg, 0x1.573e2ep-5f), svdup_n_f32_x(pg, 0x1.0e4020p-7f), b), u), u); + const svuint32_t d = svdup_n_u32_z(svcmple_n_f32(pg, n, 0.0), 0x82000000); + const svfloat32_t s1 = svreinterpret_f32_u32(svadd_n_u32_x(pg, d, 0x7f000000)); + const svfloat32_t s2 = svreinterpret_f32_u32(svsub_u32_x(pg, e, d)); + return svsel_f32(svacgt_f32(pg, n, svdup_n_f32_x(pg, 192)), svmul_f32_x(pg, s1, s1), + svsel_f32(c, svmul_f32_x(pg, svmla_f32_x(pg, s2, s2, j), s1), svmla_f32_x(pg, k, k, j))); +} + +// computes silu x/(1+exp(-x)) in single precision vector +inline static svfloat32_t ggml_v_silu(svbool_t pg, svfloat32_t x) { + const svfloat32_t one = svdup_n_f32_x(pg, 1.0f); + const svfloat32_t zero = svdup_n_f32_x(pg, 0.0f); + const svfloat32_t neg_x = svsub_f32_x(pg, zero, x); + const svfloat32_t exp_neg_x = ggml_v_expf(pg, neg_x); + const svfloat32_t one_plus_exp_neg_x = svadd_f32_x(pg, one, exp_neg_x); + return svdiv_f32_x(pg, x, one_plus_exp_neg_x); +} + +#elif defined(__ARM_NEON) && defined(__aarch64__) // adapted from arm limited optimized routine // the maximum error is 1.45358 plus 0.5 ulps @@ -913,7 +1225,59 @@ inline static __m128 ggml_v_silu(__m128 return _mm_div_ps(x, one_plus_exp_neg_x); } -#endif // __ARM_NEON / __AVX2__ / __SSE2__ +#elif defined(__riscv_v_intrinsic) + +// adapted from arm limited optimized routine +// the maximum error is 1.45358 plus 0.5 ulps +// numbers above 88.38 will flush to infinity +// numbers beneath -103.97 will flush to zero +inline static vfloat32m2_t ggml_v_expf_m2(vfloat32m2_t x, int vl) { + const vfloat32m2_t r = __riscv_vfmv_v_f_f32m2(0x1.8p23f, vl); +#ifdef __riscv_xtheadvector + // workaround for compiler bug (gcc 14.3.0: Error: unrecognized opcode `th.vmv1r.v v2,v4') + vfloat32m2_t z = __riscv_vfadd_vf_f32m2(r, 0.0f, vl); + z = __riscv_vfmacc_vf_f32m2(z, 0x1.715476p+0f, x, vl); +#else + const vfloat32m2_t z = __riscv_vfmacc_vf_f32m2(r, 0x1.715476p+0f, x, vl); +#endif + const vfloat32m2_t n = __riscv_vfsub_vv_f32m2(z, r, vl); + const vfloat32m2_t b = __riscv_vfnmsac_vf_f32m2(__riscv_vfnmsac_vf_f32m2(x, 0x1.62e4p-1f, n, vl), + 0x1.7f7d1cp-20f, n, vl); + const vuint32m2_t e = __riscv_vsll_vx_u32m2(__riscv_vreinterpret_v_f32m2_u32m2(z), 23, vl); + const vfloat32m2_t k = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vadd_vx_u32m2(e, 0x3f800000, vl)); // 1.0f + const vbool16_t c = __riscv_vmfgt_vf_f32m2_b16(__riscv_vfabs_v_f32m2(n, vl), 126.0f, vl); + const vfloat32m2_t u = __riscv_vfmul_vv_f32m2(b, b, vl); + const vfloat32m2_t j = __riscv_vfmacc_vv_f32m2( + __riscv_vfmul_vf_f32m2(b, 0x1.ffffecp-1f, vl), + __riscv_vfmacc_vv_f32m2( + __riscv_vfmacc_vf_f32m2(__riscv_vfmv_v_f_f32m2(0x1.fffdb6p-2f, vl), 0x1.555e66p-3f, b, vl), + __riscv_vfmacc_vf_f32m2(__riscv_vfmv_v_f_f32m2(0x1.573e2ep-5f, vl), 0x1.0e4020p-7f, b, vl), + u, vl), u, vl); + if (!__riscv_vcpop_m_b16(c, vl)) + return __riscv_vfmacc_vv_f32m2(k, j, k, vl); + const vbool16_t dm = __riscv_vmfle_vf_f32m2_b16(n, 0.0f, vl); + const vuint32m2_t d = __riscv_vmerge_vxm_u32m2(__riscv_vmv_v_x_u32m2(0, vl), 0x82000000, dm, vl); + const vfloat32m2_t s1 = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vadd_vx_u32m2(d, 0x7f000000, vl)); + const vfloat32m2_t s2 = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vsub_vv_u32m2(e, d, vl)); + const vfloat32m2_t r1 = __riscv_vmerge_vvm_f32m2( + __riscv_vfmacc_vv_f32m2(k, k, j, vl), + __riscv_vfmul_vv_f32m2(__riscv_vfmacc_vv_f32m2(s2, s2, j, vl), s1, vl), + c, vl); + return __riscv_vmerge_vvm_f32m2( + r1, __riscv_vfmul_vv_f32m2(s1, s1, vl), + __riscv_vmfgt_vf_f32m2_b16(__riscv_vfabs_v_f32m2(n, vl), 192.0f, vl), + vl); +} + +// computes silu x/(1+exp(-x)) in single precision vector +inline static vfloat32m2_t ggml_v_silu_m2(vfloat32m2_t x, int vl) { + const vfloat32m2_t neg_x = __riscv_vfneg_v_f32m2(x, vl); + const vfloat32m2_t exp_neg_x = ggml_v_expf_m2(neg_x, vl); + const vfloat32m2_t one_plus_exp_neg_x = __riscv_vfadd_vf_f32m2(exp_neg_x, 1.0f, vl); + return __riscv_vfdiv_vv_f32m2(x, one_plus_exp_neg_x, vl); +} + +#endif // __ARM_NEON / __AVX2__ / __SSE2__ / __riscv_v_intrinsic inline static void ggml_vec_silu_f16(const int n, ggml_fp16_t * y, const ggml_fp16_t * x) { for (int i = 0; i < n; ++i) { @@ -992,9 +1356,9 @@ void ggml_vec_swiglu_f32(const int n, fl inline static void ggml_vec_swiglu_f16(const int n, ggml_fp16_t * y, const ggml_fp16_t * x, const ggml_fp16_t * g) { for (int i = 0; i < n; ++i) { - float v = GGML_CPU_FP16_TO_FP32(x[i]); - float w = GGML_CPU_FP16_TO_FP32(g[i]); - y[i] = GGML_CPU_FP32_TO_FP16((v/(1.0f + expf(-v))) * w); + float xi = GGML_CPU_FP16_TO_FP32(x[i]); + float gi = GGML_CPU_FP16_TO_FP32(g[i]); + y[i] = GGML_CPU_FP32_TO_FP16((xi/(1.0f + expf(-xi))) * gi); } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-cuda/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-cuda/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -24,17 +24,15 @@ if (CUDAToolkit_FOUND) # for best performance and to also build real architectures for the most commonly used GPUs. if (GGML_NATIVE AND CUDAToolkit_VERSION VERSION_GREATER_EQUAL "11.6" AND CMAKE_VERSION VERSION_GREATER_EQUAL "3.24") set(CMAKE_CUDA_ARCHITECTURES "native") - elseif(GGML_CUDA_F16 OR GGML_CUDA_DMMV_F16) - if (CUDAToolkit_VERSION VERSION_GREATER_EQUAL "11.8") - set(CMAKE_CUDA_ARCHITECTURES "60-virtual;61-virtual;70-virtual;75-virtual;80-virtual;86-real;89-real") - else() - set(CMAKE_CUDA_ARCHITECTURES "60-virtual;61-virtual;70-virtual;75-virtual;80-virtual;86-real") - endif() else() + if (CUDAToolkit_VERSION VERSION_LESS "13") + list(APPEND CMAKE_CUDA_ARCHITECTURES 50-virtual 61-virtual 70-virtual) + endif () + + list(APPEND CMAKE_CUDA_ARCHITECTURES 75-virtual 80-virtual 86-real) + if (CUDAToolkit_VERSION VERSION_GREATER_EQUAL "11.8") - set(CMAKE_CUDA_ARCHITECTURES "50-virtual;61-virtual;70-virtual;75-virtual;80-virtual;86-real;89-real") - else() - set(CMAKE_CUDA_ARCHITECTURES "50-virtual;61-virtual;70-virtual;75-virtual;80-virtual;86-real") + list(APPEND CMAKE_CUDA_ARCHITECTURES 89-real) endif() endif() endif() @@ -50,6 +48,8 @@ if (CUDAToolkit_FOUND) list(APPEND GGML_SOURCES_CUDA ${SRCS}) file(GLOB SRCS "template-instances/mmq*.cu") list(APPEND GGML_SOURCES_CUDA ${SRCS}) + file(GLOB SRCS "template-instances/mmf*.cu") + list(APPEND GGML_SOURCES_CUDA ${SRCS}) if (GGML_CUDA_FA_ALL_QUANTS) file(GLOB SRCS "template-instances/fattn-vec*.cu") @@ -91,10 +91,6 @@ if (CUDAToolkit_FOUND) add_compile_definitions(GGML_CUDA_NO_FA) endif() - if (GGML_CUDA_F16 OR GGML_CUDA_DMMV_F16) - add_compile_definitions(GGML_CUDA_F16) - endif() - if (GGML_CUDA_NO_PEER_COPY) add_compile_definitions(GGML_CUDA_NO_PEER_COPY) endif() @@ -102,12 +98,16 @@ if (CUDAToolkit_FOUND) if (GGML_STATIC) if (WIN32) # As of 12.3.1 CUDA Toolkit for Windows does not offer a static cublas library - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas CUDA::cublasLt) + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas) else () - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas_static CUDA::cublasLt_static) + if (CUDAToolkit_VERSION VERSION_GREATER_EQUAL "10.1") + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas_static CUDA::cublasLt_static) + else() + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart_static CUDA::cublas_static) + endif() endif() else() - target_link_libraries(ggml-cuda PRIVATE CUDA::cudart CUDA::cublas CUDA::cublasLt) + target_link_libraries(ggml-cuda PRIVATE CUDA::cudart CUDA::cublas) endif() if (GGML_CUDA_NO_VMM) @@ -120,6 +120,10 @@ if (CUDAToolkit_FOUND) set(CUDA_FLAGS -use_fast_math -extended-lambda) + if (GGML_CUDA_DEBUG) + list(APPEND CUDA_FLAGS -lineinfo) + endif() + if (CUDAToolkit_VERSION VERSION_GREATER_EQUAL "12.8") # Options are: # - none (not recommended) diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/add-id.cu 6641+dfsg-2/ggml/src/ggml-cuda/add-id.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/add-id.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/add-id.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,58 @@ +#include "add-id.cuh" + +static __global__ void add_id_kernel( + const float * src0, const float * src1, const int32_t * src2, float * dst, + int64_t ne0, int64_t ne1, + size_t nb01, size_t nb02, + size_t nb11, + size_t nb21 + ) { + + const int64_t i1 = blockIdx.x; + const int64_t i2 = blockIdx.y; + + const int i11 = *(const int32_t *) ((const char *) src2 + i1*sizeof(int32_t) + i2*nb21); + + const size_t nb1 = ne0 * sizeof(float); + const size_t nb2 = ne1 * nb1; + + float * dst_row = (float *)((char *)dst + i1*nb1 + i2*nb2); + const float * src0_row = (const float *)((const char *)src0 + i1*nb01 + i2*nb02); + const float * src1_row = (const float *)((const char *)src1 + i11*nb11); + + for (int64_t i0 = threadIdx.x; i0 < ne0; i0 += blockDim.x) { + dst_row[i0] = src0_row[i0] + src1_row[i0]; + } +} + +void ggml_cuda_op_add_id(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; + + GGML_TENSOR_TERNARY_OP_LOCALS + + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + + GGML_ASSERT(nb00 == sizeof(float)); + GGML_ASSERT(nb10 == sizeof(float)); + GGML_ASSERT(nb20 == sizeof(int32_t)); + + const float * src0_d = (const float *)src0->data; + const float * src1_d = (const float *)src1->data; + const int32_t * src2_d = (const int32_t *)src2->data; + float * dst_d = (float *)dst->data; + + int threads = std::min((int)ne00, 768); // cols + dim3 blocks(ne01, ne02); // n_experts_used, n_tokens + add_id_kernel<<>>( + src0_d, src1_d, src2_d, dst_d, + ne0, ne1, + nb01, nb02, + nb11, + nb21 + ); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/add-id.cuh 6641+dfsg-2/ggml/src/ggml-cuda/add-id.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/add-id.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/add-id.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,3 @@ +#include "common.cuh" + +void ggml_cuda_op_add_id(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/binbcast.cu 6641+dfsg-2/ggml/src/ggml-cuda/binbcast.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/binbcast.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/binbcast.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,5 +1,6 @@ #include "binbcast.cuh" #include +#include static __device__ __forceinline__ float op_repeat(const float a, const float b) { return b; @@ -22,73 +23,295 @@ static __device__ __forceinline__ float return a / b; } -template -static __global__ void k_bin_bcast(const src0_t * src0, const src1_t * src1, dst_t * dst, - int ne0, int ne1, int ne2, int ne3, - int ne10, int ne11, int ne12, int ne13, - /*int s0, */ int s1, int s2, int s3, - /*int s00,*/ int s01, int s02, int s03, - /*int s10,*/ int s11, int s12, int s13) { - const int i0s = blockDim.x*blockIdx.x + threadIdx.x; - const int i1 = (blockDim.y*blockIdx.y + threadIdx.y); - const int i2 = (blockDim.z*blockIdx.z + threadIdx.z) / ne3; - const int i3 = (blockDim.z*blockIdx.z + threadIdx.z) % ne3; +template +static __global__ void k_bin_bcast(const src0_t * src0, + const src1_t * src1, + dst_t * dst, + const int ne0, + const int ne1, + const int ne2, + const uint3 ne3, + const uint3 ne10, + const uint3 ne11, + const uint3 ne12, + const uint3 ne13, + /*int s0, */ const int s1, + const int s2, + const int s3, + /*int s00,*/ const int s01, + const int s02, + const int s03, + /*int s10,*/ const int s11, + const int s12, + const int s13, + src1_ptrs... src1s) { + const uint32_t i0s = blockDim.x * blockIdx.x + threadIdx.x; + const uint32_t i1 = (blockDim.y * blockIdx.y + threadIdx.y); + const uint32_t i2 = fastdiv((blockDim.z * blockIdx.z + threadIdx.z), ne3); + const uint32_t i3 = (blockDim.z * blockIdx.z + threadIdx.z) - (i2 * ne3.z); - if (i0s >= ne0 || i1 >= ne1 || i2 >= ne2 || i3 >= ne3) { + if (i0s >= (uint32_t)ne0 || i1 >= (uint32_t)ne1 || i2 >= (uint32_t)ne2 || i3 >= ne3.z) { return; } - const int i11 = i1 % ne11; - const int i12 = i2 % ne12; - const int i13 = i3 % ne13; + const uint32_t i11 = fastmodulo(i1, ne11); + const uint32_t i12 = fastmodulo(i2, ne12); + const uint32_t i13 = fastmodulo(i3, ne13); const size_t i_src0 = i3*s03 + i2*s02 + i1*s01; const size_t i_src1 = i13*s13 + i12*s12 + i11*s11; const size_t i_dst = i3*s3 + i2*s2 + i1*s1; - const src0_t * src0_row = src0 + i_src0; - const src1_t * src1_row = src1 + i_src1; + const src0_t * src0_row = src0 ? (src0 + i_src0) : nullptr; dst_t * dst_row = dst + i_dst; - for (int i0 = i0s; i0 < ne0; i0 += blockDim.x*gridDim.x) { - const int i10 = i0 % ne10; - dst_row[i0] = (dst_t)bin_op(src0 ? (float)src0_row[i0] : 0.0f, (float)src1_row[i10]); + for (int i0 = i0s; i0 < ne0; i0 += blockDim.x * gridDim.x) { + const uint32_t i10 = fastmodulo(i0, ne10); + + float result = src0_row ? (float) src0_row[i0] : 0.0f; + if constexpr (sizeof...(src1_ptrs) > 0) { + result = (..., (result = bin_op(result, (float)src1s[i_src1 + i10]))); + } else { + result = bin_op(result, (float)src1[i_src1 + i10]); + } + + dst_row[i0] = (dst_t) result; } } -template -static __global__ void k_bin_bcast_unravel(const src0_t * src0, const src1_t * src1, dst_t * dst, - int ne0, int ne1, int ne2, int ne3, - int ne10, int ne11, int ne12, int ne13, - /*int s0, */ int s1, int s2, int s3, - /*int s00,*/ int s01, int s02, int s03, - /*int s10,*/ int s11, int s12, int s13) { - +template +static __global__ void k_bin_bcast_unravel(const src0_t * src0, + const src1_t * src1, + dst_t * dst, + const uint3 ne0, + const uint3 ne1, + const uint3 ne2, + const uint32_t ne3, + const uint3 prod_012, + const uint3 prod_01, + const uint3 ne10, + const uint3 ne11, + const uint3 ne12, + const uint3 ne13, + /*int s0, */ const int s1, + const int s2, + const int s3, + /*int s00,*/ const int s01, + const int s02, + const int s03, + /*int s10,*/ const int s11, + const int s12, + const int s13, + src1_ptrs... src1s) { const int i = blockDim.x*blockIdx.x + threadIdx.x; - const int i3 = i/(ne2*ne1*ne0); - const int i2 = (i/(ne1*ne0)) % ne2; - const int i1 = (i/ne0) % ne1; - const int i0 = i % ne0; + const uint32_t i3 = fastdiv(i, prod_012); + const uint32_t i2 = fastdiv(i - i3 * prod_012.z, prod_01); + const uint32_t i1 = fastdiv(i - i3 * prod_012.z - i2 * prod_01.z, ne0); + const uint32_t i0 = i - i3 * prod_012.z - i2 * prod_01.z - i1 * ne0.z; - if (i0 >= ne0 || i1 >= ne1 || i2 >= ne2 || i3 >= ne3) { + if (i0 >= ne0.z || i1 >= ne1.z || i2 >= ne2.z || i3 >= ne3) { return; } - const int i11 = i1 % ne11; - const int i12 = i2 % ne12; - const int i13 = i3 % ne13; + const int i11 = fastmodulo(i1, ne11); + const int i12 = fastmodulo(i2, ne12); + const int i13 = fastmodulo(i3, ne13); const size_t i_src0 = i3*s03 + i2*s02 + i1*s01; const size_t i_src1 = i13*s13 + i12*s12 + i11*s11; const size_t i_dst = i3*s3 + i2*s2 + i1*s1; - const src0_t * src0_row = src0 + i_src0; - const src1_t * src1_row = src1 + i_src1; + const src0_t * src0_row = src0 ? (src0 + i_src0) : nullptr; dst_t * dst_row = dst + i_dst; - const int i10 = i0 % ne10; - dst_row[i0] = (dst_t)bin_op(src0 ? (float)src0_row[i0] : 0.0f, (float)src1_row[i10]); + const int i10 = fastmodulo(i0, ne10); + + float result = src0_row ? (float) src0_row[i0] : 0.0f; + if constexpr (sizeof...(src1_ptrs) > 0) { + result = (..., (result = bin_op(result, (float)src1s[i_src1 + i10]))); + } else { + result = bin_op(result, (float)src1[i_src1 + i10]); + } + + dst_row[i0] = (dst_t) result; +} + +template +static void launch_bin_bcast_pack(const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, + const src0_t * src0_dd, const src1_t * src1_dd, dst_t * dst_dd, + cudaStream_t stream, std::index_sequence) { + GGML_TENSOR_BINARY_OP_LOCALS + + int nr0 = ne10 / ne0; + int nr1 = ne11 / ne1; + int nr2 = ne12 / ne2; + int nr3 = ne13 / ne3; + + int nr[4] = { nr0, nr1, nr2, nr3 }; + + int64_t cne[] = { ne0, ne1, ne2, ne3 }; + int64_t cne0[] = { ne00, ne01, ne02, ne03 }; + int64_t cne1[] = { ne10, ne11, ne12, ne13 }; + + size_t cnb[] = { nb0, nb1, nb2, nb3 }; + size_t cnb0[] = { nb00, nb01, nb02, nb03 }; + size_t cnb1[] = { nb10, nb11, nb12, nb13 }; + + auto collapse = [](int64_t cne[]) { + cne[0] *= cne[1]; + cne[1] = cne[2]; + cne[2] = cne[3]; + cne[3] = 1; + }; + + auto collapse_nb = [](size_t cnb[], const int64_t cne[]) { + cnb[1] *= cne[1]; + cnb[2] *= cne[2]; + cnb[3] *= cne[3]; + }; + + if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && ggml_is_contiguous(dst)) { + for (int i = 0; i < 4; i++) { + if (nr[i] != 1) { + break; + } + if (i > 0) { + collapse_nb(cnb, cne); + collapse_nb(cnb0, cne0); + collapse_nb(cnb1, cne1); + collapse(cne); + collapse(cne0); + collapse(cne1); + } + } + } + + { + int64_t ne0 = cne[0]; + int64_t ne1 = cne[1]; + int64_t ne2 = cne[2]; + int64_t ne3 = cne[3]; + + //int64_t ne00 = cne0[0]; GGML_UNUSED(ne00); + //int64_t ne01 = cne0[1]; GGML_UNUSED(ne01); + //int64_t ne02 = cne0[2]; GGML_UNUSED(ne02); + //int64_t ne03 = cne0[3]; GGML_UNUSED(ne03); + + size_t nb0 = cnb[0]; + size_t nb1 = cnb[1]; + size_t nb2 = cnb[2]; + size_t nb3 = cnb[3]; + + size_t nb00 = cnb0[0]; + size_t nb01 = cnb0[1]; + size_t nb02 = cnb0[2]; + size_t nb03 = cnb0[3]; + + size_t nb10 = cnb1[0]; + size_t nb11 = cnb1[1]; + size_t nb12 = cnb1[2]; + size_t nb13 = cnb1[3]; + + size_t s0 = nb0 / sizeof(dst_t); + size_t s1 = nb1 / sizeof(dst_t); + size_t s2 = nb2 / sizeof(dst_t); + size_t s3 = nb3 / sizeof(dst_t); + + size_t s10 = nb10 / sizeof(src1_t); + size_t s11 = nb11 / sizeof(src1_t); + size_t s12 = nb12 / sizeof(src1_t); + size_t s13 = nb13 / sizeof(src1_t); + + size_t s00 = nb00 / sizeof(src0_t); + size_t s01 = nb01 / sizeof(src0_t); + size_t s02 = nb02 / sizeof(src0_t); + size_t s03 = nb03 / sizeof(src0_t); + + GGML_ASSERT(nb0 % sizeof(dst_t) == 0); + GGML_ASSERT(nb1 % sizeof(dst_t) == 0); + GGML_ASSERT(nb2 % sizeof(dst_t) == 0); + GGML_ASSERT(nb3 % sizeof(dst_t) == 0); + + GGML_ASSERT(nb00 % sizeof(src0_t) == 0); + GGML_ASSERT(nb01 % sizeof(src0_t) == 0); + GGML_ASSERT(nb02 % sizeof(src0_t) == 0); + GGML_ASSERT(nb03 % sizeof(src0_t) == 0); + + GGML_ASSERT(nb10 % sizeof(src1_t) == 0); + GGML_ASSERT(nb11 % sizeof(src1_t) == 0); + GGML_ASSERT(nb12 % sizeof(src1_t) == 0); + GGML_ASSERT(nb13 % sizeof(src1_t) == 0); + + GGML_ASSERT(s0 == 1); + GGML_ASSERT(s00 == 1); + GGML_ASSERT(s10 == 1); + + const int block_size = 128; + + int64_t hne0 = std::max(ne0 / 2LL, 1LL); + + dim3 block_dims; + block_dims.x = std::min(hne0, block_size); + block_dims.y = std::min(ne1, block_size / block_dims.x); + block_dims.z = std::min(std::min(ne2 * ne3, block_size / block_dims.x / block_dims.y), 64U); + + dim3 block_nums((hne0 + block_dims.x - 1) / block_dims.x, (ne1 + block_dims.y - 1) / block_dims.y, + (ne2 * ne3 + block_dims.z - 1) / block_dims.z); + + const uint3 ne10 = init_fastdiv_values((uint32_t) cne1[0]); + const uint3 ne11 = init_fastdiv_values((uint32_t) cne1[1]); + const uint3 ne12 = init_fastdiv_values((uint32_t) cne1[2]); + const uint3 ne13 = init_fastdiv_values((uint32_t) cne1[3]); + + if (block_nums.z > 65535) { + int block_num = (ne0 * ne1 * ne2 * ne3 + block_size - 1) / block_size; + const uint3 prod_012 = init_fastdiv_values((uint32_t) (ne0 * ne1 * ne2)); + const uint3 prod_01 = init_fastdiv_values((uint32_t) (ne0 * ne1)); + const uint3 ne0_fastdiv = init_fastdiv_values((uint32_t) ne0); + const uint3 ne1_fastdiv = init_fastdiv_values((uint32_t) ne1); + const uint3 ne2_fastdiv = init_fastdiv_values((uint32_t) ne2); + + if constexpr (sizeof...(I) > 0) { + k_bin_bcast_unravel<<>>( + src0_dd, src1_dd, dst_dd, ne0_fastdiv, ne1_fastdiv, ne2_fastdiv, ne3, prod_012, prod_01, ne10, ne11, + ne12, ne13, + /* s0, */ s1, s2, s3, + /* s00,*/ s01, s02, s03, + /* s10,*/ s11, s12, s13, (const src1_t *) dst->src[I + 1]->data...); + } else { + k_bin_bcast_unravel + <<>>(src0_dd, src1_dd, dst_dd, ne0_fastdiv, ne1_fastdiv, + ne2_fastdiv, ne3, prod_012, prod_01, ne10, ne11, ne12, ne13, + /* s0, */ s1, s2, s3, + /* s00,*/ s01, s02, s03, + /* s10,*/ s11, s12, s13); + } + } else { + const uint3 ne3_fastdiv = init_fastdiv_values((uint32_t) ne3); + if constexpr (sizeof...(I) > 0) { + k_bin_bcast<<>>( + src0_dd, src1_dd, dst_dd, ne0, ne1, ne2, ne3_fastdiv, ne10, ne11, ne12, ne13, + /* s0, */ s1, s2, s3, + /* s00,*/ s01, s02, s03, + /* s10,*/ s11, s12, s13, (const src1_t *) dst->src[I + 1]->data...); + } else { + k_bin_bcast<<>>( + src0_dd, src1_dd, dst_dd, ne0, ne1, ne2, ne3_fastdiv, ne10, ne11, ne12, ne13, + /* s0, */ s1, s2, s3, + /* s00,*/ s01, s02, s03, + /* s10,*/ s11, s12, s13); + } + } + } } template @@ -120,160 +343,14 @@ static __global__ void k_repeat_back( dst[tid3*ne2*ne1*ne0 + tid2*ne1*ne0 + tid1*ne0 + tid0] = sum; } -template +template struct bin_bcast_cuda { template void operator()(const struct ggml_tensor * src0, const struct ggml_tensor * src1, struct ggml_tensor * dst, const src0_t * src0_dd, const src1_t * src1_dd, dst_t * dst_dd, cudaStream_t stream) { - - GGML_TENSOR_BINARY_OP_LOCALS - - int nr0 = ne10/ne0; - int nr1 = ne11/ne1; - int nr2 = ne12/ne2; - int nr3 = ne13/ne3; - - int nr[4] = { nr0, nr1, nr2, nr3 }; - - // collapse dimensions until first broadcast dimension - int64_t cne[] = {ne0, ne1, ne2, ne3}; - int64_t cne0[] = {ne00, ne01, ne02, ne03}; - int64_t cne1[] = {ne10, ne11, ne12, ne13}; - - size_t cnb[] = {nb0, nb1, nb2, nb3}; - size_t cnb0[] = {nb00, nb01, nb02, nb03}; - size_t cnb1[] = {nb10, nb11, nb12, nb13}; - - auto collapse = [](int64_t cne[]) { - cne[0] *= cne[1]; - cne[1] = cne[2]; - cne[2] = cne[3]; - cne[3] = 1; - }; - - auto collapse_nb = [](size_t cnb[], const int64_t cne[]) { - cnb[1] *= cne[1]; - cnb[2] *= cne[2]; - cnb[3] *= cne[3]; - }; - - if (ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && ggml_is_contiguous(dst)) { - for (int i = 0; i < 4; i++) { - if (nr[i] != 1) { - break; - } - if (i > 0) { - collapse_nb(cnb, cne); - collapse_nb(cnb0, cne0); - collapse_nb(cnb1, cne1); - collapse(cne); - collapse(cne0); - collapse(cne1); - } - } - } - - { - int64_t ne0 = cne[0]; - int64_t ne1 = cne[1]; - int64_t ne2 = cne[2]; - int64_t ne3 = cne[3]; - - //int64_t ne00 = cne0[0]; GGML_UNUSED(ne00); - //int64_t ne01 = cne0[1]; GGML_UNUSED(ne01); - //int64_t ne02 = cne0[2]; GGML_UNUSED(ne02); - //int64_t ne03 = cne0[3]; GGML_UNUSED(ne03); - - int64_t ne10 = cne1[0]; - int64_t ne11 = cne1[1]; - int64_t ne12 = cne1[2]; - int64_t ne13 = cne1[3]; - - size_t nb0 = cnb[0]; - size_t nb1 = cnb[1]; - size_t nb2 = cnb[2]; - size_t nb3 = cnb[3]; - - size_t nb00 = cnb0[0]; - size_t nb01 = cnb0[1]; - size_t nb02 = cnb0[2]; - size_t nb03 = cnb0[3]; - - size_t nb10 = cnb1[0]; - size_t nb11 = cnb1[1]; - size_t nb12 = cnb1[2]; - size_t nb13 = cnb1[3]; - - size_t s0 = nb0 / sizeof(dst_t); - size_t s1 = nb1 / sizeof(dst_t); - size_t s2 = nb2 / sizeof(dst_t); - size_t s3 = nb3 / sizeof(dst_t); - - size_t s10 = nb10 / sizeof(src1_t); - size_t s11 = nb11 / sizeof(src1_t); - size_t s12 = nb12 / sizeof(src1_t); - size_t s13 = nb13 / sizeof(src1_t); - - size_t s00 = nb00 / sizeof(src0_t); - size_t s01 = nb01 / sizeof(src0_t); - size_t s02 = nb02 / sizeof(src0_t); - size_t s03 = nb03 / sizeof(src0_t); - - GGML_ASSERT(nb0 % sizeof(dst_t) == 0); - GGML_ASSERT(nb1 % sizeof(dst_t) == 0); - GGML_ASSERT(nb2 % sizeof(dst_t) == 0); - GGML_ASSERT(nb3 % sizeof(dst_t) == 0); - - GGML_ASSERT(nb00 % sizeof(src0_t) == 0); - GGML_ASSERT(nb01 % sizeof(src0_t) == 0); - GGML_ASSERT(nb02 % sizeof(src0_t) == 0); - GGML_ASSERT(nb03 % sizeof(src0_t) == 0); - - GGML_ASSERT(nb10 % sizeof(src1_t) == 0); - GGML_ASSERT(nb11 % sizeof(src1_t) == 0); - GGML_ASSERT(nb12 % sizeof(src1_t) == 0); - GGML_ASSERT(nb13 % sizeof(src1_t) == 0); - - GGML_ASSERT(s0 == 1); - GGML_ASSERT(s00 == 1); - GGML_ASSERT(s10 == 1); - - const int block_size = 128; - - int64_t hne0 = std::max(ne0/2LL, 1LL); - - dim3 block_dims; - block_dims.x = std::min(hne0, block_size); - block_dims.y = std::min(ne1, block_size / block_dims.x); - block_dims.z = std::min(std::min(ne2*ne3, block_size / block_dims.x / block_dims.y), 64U); - - dim3 block_nums( - (hne0 + block_dims.x - 1) / block_dims.x, - (ne1 + block_dims.y - 1) / block_dims.y, - (ne2*ne3 + block_dims.z - 1) / block_dims.z - ); - - if (block_nums.z > 65535) { - // this is the maximum number of blocks in z dimension, fallback to 1D grid kernel - int block_num = (ne0*ne1*ne2*ne3 + block_size - 1) / block_size; - k_bin_bcast_unravel<<>>( - src0_dd, src1_dd, dst_dd, - ne0, ne1, ne2, ne3, - ne10, ne11, ne12, ne13, - /* s0, */ s1, s2, s3, - /* s00, */ s01, s02, s03, - /* s10, */ s11, s12, s13); - } else { - k_bin_bcast<<>>( - src0_dd, src1_dd, dst_dd, - ne0, ne1, ne2, ne3, - ne10, ne11, ne12, ne13, - /* s0, */ s1, s2, s3, - /* s00, */ s01, s02, s03, - /* s10, */ s11, s12, s13); - } - } + launch_bin_bcast_pack( + src0, src1, dst, src0_dd, src1_dd, dst_dd, stream, std::make_index_sequence{}); } }; @@ -312,7 +389,7 @@ static void ggml_cuda_op_bin_bcast( } void ggml_cuda_op_repeat(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - ggml_cuda_op_bin_bcast>(dst, dst->src[0], dst, nullptr, dst->src[0]->data, dst->data, ctx.stream()); + ggml_cuda_op_bin_bcast>(dst, dst->src[0], dst, nullptr, dst->src[0]->data, dst->data, ctx.stream()); } void ggml_cuda_op_add(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -331,6 +408,68 @@ void ggml_cuda_op_div(ggml_backend_cuda_ ggml_cuda_op_bin_bcast>(dst->src[0], dst->src[1], dst, dst->src[0]->data, dst->src[1]->data, dst->data, ctx.stream()); } +template +static void ggml_cuda_op_fused_binbcast_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + cudaStream_t stream = ctx.stream(); + + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + if (src0->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32) { + launch_bin_bcast_pack(src0, src1, dst, + (const float *) src0->data, (const float *) src1->data, (float *) dst->data, + stream, std::make_index_sequence{}); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F16) { + launch_bin_bcast_pack(src0, src1, dst, + (const half *) src0->data, (const half *) src1->data, (half *) dst->data, + stream, std::make_index_sequence{}); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F16) { + launch_bin_bcast_pack(src0, src1, dst, + (const half *) src0->data, (const float *) src1->data, (half *) dst->data, + stream, std::make_index_sequence{}); + } else if (src0->type == GGML_TYPE_F16 && dst->type == GGML_TYPE_F32) { + launch_bin_bcast_pack(src0, src1, dst, + (const half *) src0->data, (const float *) src1->data, (float *) dst->data, + stream, std::make_index_sequence{}); + } else { + fprintf(stderr, + "%s: unsupported types for fusion: dst: %s, src0: %s, src1: %s\n", + __func__, ggml_type_name(dst->type), ggml_type_name(src0->type), ggml_type_name(src1->type)); + GGML_ABORT("fatal error"); + } +} + + +void ggml_cuda_op_fused_add(ggml_backend_cuda_context & ctx, ggml_tensor * dst, int n_fuse) { + GGML_ASSERT(2 <= n_fuse && n_fuse <= 8); + + switch (n_fuse) { + case 2: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 3: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 4: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 5: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 6: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 7: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + case 8: + ggml_cuda_op_fused_binbcast_impl(ctx, dst); + break; + default: + GGML_ASSERT(false && "Unsupported n_fuse value"); + } +} + void ggml_cuda_op_repeat_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/binbcast.cuh 6641+dfsg-2/ggml/src/ggml-cuda/binbcast.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/binbcast.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/binbcast.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -7,3 +7,5 @@ void ggml_cuda_op_mul(ggml_backend_cuda_ void ggml_cuda_op_div(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_repeat_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst); + +void ggml_cuda_op_fused_add(ggml_backend_cuda_context & ctx, ggml_tensor * dst, int n_fuse); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/common.cuh 6641+dfsg-2/ggml/src/ggml-cuda/common.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/common.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/common.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -1,6 +1,7 @@ #pragma once #include "ggml.h" +#include "ggml-impl.h" #include "ggml-cuda.h" #include @@ -56,7 +57,7 @@ #define GGML_CUDA_CC_GCN4 (GGML_CUDA_CC_OFFSET_AMD + 0x803) // Tonga, Fiji, Polaris, minimum for fast fp16 #define GGML_CUDA_CC_VEGA (GGML_CUDA_CC_OFFSET_AMD + 0x900) // Vega56/64, minimum for fp16 dual issue #define GGML_CUDA_CC_VEGA20 (GGML_CUDA_CC_OFFSET_AMD + 0x906) // MI50/Radeon VII, minimum for dp4a -#define GGML_CUDA_CC_CDNA (GGML_CUDA_CC_OFFSET_AMD + 0x908) // MI100, minimum for MFMA, acc registers +#define GGML_CUDA_CC_CDNA1 (GGML_CUDA_CC_OFFSET_AMD + 0x908) // MI100, minimum for MFMA, acc registers #define GGML_CUDA_CC_CDNA2 (GGML_CUDA_CC_OFFSET_AMD + 0x910) // MI210, minimum acc register renameing #define GGML_CUDA_CC_CDNA3 (GGML_CUDA_CC_OFFSET_AMD + 0x942) // MI300 @@ -72,10 +73,15 @@ #define GGML_CUDA_CC_IS_RDNA2(cc) (cc >= GGML_CUDA_CC_RDNA2 && cc < GGML_CUDA_CC_RDNA3) #define GGML_CUDA_CC_IS_RDNA3(cc) (cc >= GGML_CUDA_CC_RDNA3 && cc < GGML_CUDA_CC_RDNA4) #define GGML_CUDA_CC_IS_RDNA4(cc) (cc >= GGML_CUDA_CC_RDNA4) -#define GGML_CUDA_CC_IS_GCN(cc) (cc > GGML_CUDA_CC_OFFSET_AMD && cc < GGML_CUDA_CC_CDNA) -#define GGML_CUDA_CC_IS_CDNA(cc) (cc >= GGML_CUDA_CC_CDNA && cc < GGML_CUDA_CC_RDNA1) +#define GGML_CUDA_CC_IS_GCN(cc) (cc > GGML_CUDA_CC_OFFSET_AMD && cc < GGML_CUDA_CC_CDNA1) +#define GGML_CUDA_CC_IS_CDNA(cc) (cc >= GGML_CUDA_CC_CDNA1 && cc < GGML_CUDA_CC_RDNA1) +#define GGML_CUDA_CC_IS_CDNA1(cc) (cc >= GGML_CUDA_CC_CDNA1 && cc < GGML_CUDA_CC_CDNA2) +#define GGML_CUDA_CC_IS_CDNA2(cc) (cc >= GGML_CUDA_CC_CDNA2 && cc < GGML_CUDA_CC_CDNA3) +#define GGML_CUDA_CC_IS_CDNA3(cc) (cc >= GGML_CUDA_CC_CDNA3 && cc < GGML_CUDA_CC_RDNA1) // Moore Threads +#define MUSART_HMASK 40300 // MUSA rc4.3, min. ver. for half2 -> uint mask comparisons + #define GGML_CUDA_CC_QY1 (GGML_CUDA_CC_OFFSET_MTHREADS + 0x210) // MTT S80, MTT S3000 #define GGML_CUDA_CC_QY2 (GGML_CUDA_CC_OFFSET_MTHREADS + 0x220) // MTT S4000 #define GGML_CUDA_CC_NG (GGML_CUDA_CC_OFFSET_MTHREADS + 0x310) // TBD @@ -85,6 +91,10 @@ #define GGML_CUDA_CC_IS_QY2(cc) (cc >= GGML_CUDA_CC_QY2 && cc < GGML_CUDA_CC_NG) #define GGML_CUDA_CC_IS_NG(cc) (cc >= GGML_CUDA_CC_NG) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +# define GGML_CUDA_USE_CUB +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 + #ifdef __CUDA_ARCH_LIST__ constexpr bool ggml_cuda_has_arch_impl(int) { return false; @@ -99,9 +109,9 @@ constexpr bool ggml_cuda_has_arch(const return ggml_cuda_has_arch_impl(arch, __CUDA_ARCH_LIST__); } -constexpr int ggml_cuda_highest_compiled_arch_impl(const int arch, const int cur) { +constexpr int ggml_cuda_highest_compiled_arch_impl(const int /*arch*/, const int cur) { if (cur == 0) { - GGML_ABORT("ggml was not compiled with any CUDA arch <= %d", arch); + return -1; } return cur; } @@ -175,7 +185,7 @@ static const char * cu_get_error_str(CUr #define CU_CHECK(err) CUDA_CHECK_GEN(err, CUDA_SUCCESS, cu_get_error_str) #endif -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) # define CUDA_SET_SHARED_MEMORY_LIMIT(kernel, nbytes) \ do { \ static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = { false }; \ @@ -190,7 +200,7 @@ static const char * cu_get_error_str(CUr do { \ GGML_UNUSED(nbytes); \ } while (0) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !(defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) #if CUDART_VERSION >= 11010 || defined(GGML_USE_MUSA) #define GGML_CUDA_ASSUME(x) __builtin_assume(x) @@ -198,21 +208,13 @@ static const char * cu_get_error_str(CUr #define GGML_CUDA_ASSUME(x) #endif // CUDART_VERSION >= 11010 -#ifdef GGML_CUDA_F16 -typedef half dfloat; // dequantize float -typedef half2 dfloat2; -#else -typedef float dfloat; // dequantize float -typedef float2 dfloat2; -#endif // GGML_CUDA_F16 - #if (!defined(GGML_USE_HIP) && !defined(GGML_CUDA_NO_VMM)) || (defined(GGML_USE_HIP) && !defined(GGML_HIP_NO_VMM)) #define GGML_USE_VMM #endif // (!defined(GGML_USE_HIP) && !defined(GGML_CUDA_NO_VMM)) || (defined(GGML_USE_HIP) && !defined(GGML_HIP_NO_VMM)) -#if (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL +#if defined(GGML_USE_HIP) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL #define FP16_AVAILABLE -#endif // (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL +#endif // defined(GGML_USE_HIP) || __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL #if defined(FP16_AVAILABLE) && __CUDA_ARCH__ != 610 #define FAST_FP16_AVAILABLE @@ -226,13 +228,21 @@ typedef float2 dfloat2; #define FP16_MMA_AVAILABLE #endif // defined(GGML_HIP_ROCWMMA_FATTN) && (defined(CDNA) || defined(RDNA3) || (defined(GGML_HIP_ROCWMMA_FATTN_GFX12) && defined(RDNA4))) -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING -#define NEW_MMA_AVAILABLE -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING +#if defined(GGML_USE_HIP) && defined(CDNA) && !defined(GGML_HIP_NO_MMQ_MFMA) +#define AMD_MFMA_AVAILABLE +#endif // defined(GGML_USE_HIP) && defined(CDNA) && !defined(GGML_HIP_NO_MMQ_MFMA) + +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING +#define TURING_MMA_AVAILABLE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_TURING + +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#define AMPERE_MMA_AVAILABLE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #define CP_ASYNC_AVAILABLE -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #if !defined(GGML_CUDA_NO_FA) && !(defined(GGML_USE_MUSA) && __MUSA_ARCH__ < 220) #define FLASH_ATTN_AVAILABLE @@ -254,7 +264,7 @@ static bool fast_fp16_hardware_available // Any FP16 tensor core instructions are available for ggml code. static bool fp16_mma_available(const int cc) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && !defined(GGML_HIP_ROCWMMA_FATTN) +#if defined(GGML_USE_HIP) && !defined(GGML_HIP_ROCWMMA_FATTN) return false; #else if ((GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) || @@ -270,7 +280,7 @@ static bool fp16_mma_available(const int } else { return false; } -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && !defined(GGML_HIP_ROCWMMA_FATTN) +#endif // defined(GGML_USE_HIP) && !defined(GGML_HIP_ROCWMMA_FATTN) } // To be used for feature selection of external libraries, e.g. cuBLAS. @@ -288,35 +298,61 @@ static bool fp32_mma_hardware_available( return GGML_CUDA_CC_IS_CDNA(cc); } +static bool amd_mfma_available(const int cc) { +#if !defined(GGML_HIP_NO_MMQ_MFMA) + return GGML_CUDA_CC_IS_CDNA(cc); +#else + return false; +#endif //!defined(GGML_HIP_NO_MMQ_MFMA) +} + // Volta technically had FP16 tensor cores but they work very differently compared to Turing and later. -static bool new_mma_available(const int cc) { +static bool turing_mma_available(const int cc) { return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_TURING; } +static bool ampere_mma_available(const int cc) { + return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; +} + static bool cp_async_available(const int cc) { - return cc < GGML_CUDA_CC_OFFSET_AMD && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; + return GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_AMPERE; } static constexpr __device__ int ggml_cuda_get_physical_warp_size() { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && (defined(__GFX9__) || defined(__GFX8__)) +#if defined(GGML_USE_HIP) && (defined(__GFX9__) || defined(__GFX8__)) return 64; #else return 32; -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) && (defined(__GFX9__) || defined(__GFX8__)) +#endif // defined(GGML_USE_HIP) && (defined(__GFX9__) || defined(__GFX8__)) +} + +// Maximum number of bytes that can be copied in a single instruction. +static constexpr __device__ int ggml_cuda_get_max_cpy_bytes() { +#ifdef GGML_USE_HIP + return 16; +#else +#if __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA + return 16; +#else + return 8; +#endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA +#endif // GGML_USE_HIP } + [[noreturn]] static __device__ void no_device_code( const char * file_name, const int line, const char * function_name, const int arch, const char * arch_list) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) printf("%s:%d: ERROR: HIP kernel %s has no device code compatible with HIP arch %d.\n", file_name, line, function_name, arch); GGML_UNUSED(arch_list); #else printf("%s:%d: ERROR: CUDA kernel %s has no device code compatible with CUDA arch %d. ggml-cuda.cu was compiled for: %s\n", file_name, line, function_name, arch, arch_list); -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) __trap(); GGML_UNUSED(no_device_code); // suppress unused function warning @@ -353,7 +389,7 @@ struct ggml_cuda_unroll<1> { template static __device__ __forceinline__ int warp_reduce_sum(int x) { -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE return __reduce_add_sync(0xffffffff, x); #else #pragma unroll @@ -361,7 +397,7 @@ static __device__ __forceinline__ int wa x += __shfl_xor_sync(0xffffffff, x, offset, width); } return x; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE } template @@ -398,24 +434,30 @@ static __device__ __forceinline__ half2 #endif // FP16_AVAILABLE } -// Row reduction kernel template - compute sum (norm=false) or mean (norm=true) -template -static __global__ void reduce_rows_f32(const float * x, float * dst, const int ncols) { - const int row = blockIdx.x; - const int col = threadIdx.x; - - float sum = 0.0f; - for (int i = col; i < ncols; i += blockDim.x) { - sum += x[row * ncols + i]; +template +static __device__ __forceinline__ int warp_reduce_all(int x) { + if (width == ggml_cuda_get_physical_warp_size()) { + return __all_sync(0xffffffff, x); + } else { +#pragma unroll + for (int offset = width/2; offset > 0; offset >>= 1) { + x = __shfl_xor_sync(0xffffffff, x, offset, width) && x; + } + return x; } +} - sum = warp_reduce_sum(sum); - - if (col != 0) { - return; +template +static __device__ __forceinline__ int warp_reduce_any(int x) { + if (width == ggml_cuda_get_physical_warp_size()) { + return __any_sync(0xffffffff, x); + } else { +#pragma unroll + for (int offset = width/2; offset > 0; offset >>= 1) { + x = __shfl_xor_sync(0xffffffff, x, offset, width) || x; + } + return x; } - - dst[row] = norm ? sum / ncols : sum; } template @@ -430,11 +472,11 @@ static __device__ __forceinline__ float static __device__ __forceinline__ half ggml_cuda_hmax(const half a, const half b) { #ifdef FP16_AVAILABLE -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && CUDART_VERSION < CUDART_HMAX +#if !defined(GGML_USE_HIP) && CUDART_VERSION < CUDART_HMAX return __float2half(fmaxf(__half2float(a), __half2float(b))); #else return __hmax(a, b); -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && CUDART_VERSION < CUDART_HMAX +#endif // !defined(GGML_USE_HIP) && CUDART_VERSION < CUDART_HMAX #else NO_DEVICE_CODE; @@ -444,25 +486,21 @@ static __device__ __forceinline__ half g } static __device__ __forceinline__ half2 ggml_cuda_hmax2(const half2 a, const half2 b) { -#if defined(GGML_USE_HIP) && HIP_VERSION >= 50700000 +#if defined(GGML_USE_HIP) return half2(__hmax(a.x, b.x), __hmax(a.y, b.y)); -#elif !defined(GGML_USE_HIP) && CUDART_VERSION >= CUDART_HMAX +#elif CUDART_VERSION >= CUDART_HMAX return __hmax2(a, b); -#elif !defined(GGML_USE_HIP) +#else half2 ret; reinterpret_cast(ret.x) = __float2half(fmaxf( __low2float(a), __low2float(b))); reinterpret_cast(ret.y) = __float2half(fmaxf(__high2float(a), __high2float(b))); return ret; -#else - GGML_UNUSED(a); - GGML_UNUSED(b); - NO_DEVICE_CODE; #endif } template static __device__ __forceinline__ half2 warp_reduce_max(half2 x) { -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || (defined(GGML_USE_HIP) && HIP_VERSION >= 50700000) +#if !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || defined(GGML_USE_HIP) #pragma unroll for (int offset = width/2; offset > 0; offset >>= 1) { x = ggml_cuda_hmax2(x, __shfl_xor_sync(0xffffffff, x, offset, width)); @@ -471,19 +509,20 @@ static __device__ __forceinline__ half2 #else GGML_UNUSED(x); NO_DEVICE_CODE; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || (defined(GGML_USE_HIP) && HIP_VERSION >= 50700000) +#endif // !defined(GGML_USE_HIP) && __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL || defined(GGML_USE_HIP) } -#if CUDART_VERSION < CUDART_HMASK +#if (defined(CUDART_VERSION) && CUDART_VERSION < CUDART_HMASK) || defined(GGML_USE_HIP) || \ + (defined(MUSART_VERSION) && MUSART_VERSION < MUSART_HMASK) static __device__ __forceinline__ uint32_t __hgt2_mask(const half2 a, const half2 b) { const uint32_t mask_low = 0x0000FFFF * (float( __low2half(a)) > float( __low2half(b))); const uint32_t mask_high = 0xFFFF0000 * (float(__high2half(a)) > float(__high2half(b))); return mask_low | mask_high; } -#endif // CUDART_VERSION < CUDART_HMASK +#endif // (defined(CUDART_VERSION) && CUDART_VERSION < CUDART_HMASK) || defined(GGML_USE_HIP) || (defined(MUSART_VERSION) && MUSART_VERSION < MUSART_HMASK) static __device__ __forceinline__ int ggml_cuda_dp4a(const int a, const int b, int c) { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) #if defined(CDNA) || defined(RDNA2) || defined(__gfx906__) c = __builtin_amdgcn_sdot4(a, b, c, false); #elif defined(RDNA3) || defined(RDNA4) @@ -509,7 +548,7 @@ static __device__ __forceinline__ int gg #endif return c; -#else // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#else // defined(GGML_USE_HIP) #if __CUDA_ARCH__ >= GGML_CUDA_CC_DP4A || defined(GGML_USE_MUSA) return __dp4a(a, b, c); @@ -519,10 +558,134 @@ static __device__ __forceinline__ int gg return c + a8[0]*b8[0] + a8[1]*b8[1] + a8[2]*b8[2] + a8[3]*b8[3]; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_DP4A || defined(GGML_USE_MUSA) -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) +} + +static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const float v, const float u) { + acc += v*u; +} + +static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const float2 v, const float2 u) { + acc += v.x*u.x; + acc += v.y*u.y; +} + +static __device__ __forceinline__ void ggml_cuda_mad(float & acc, const half2 v, const half2 u) { +#if defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4) || defined(__gfx906__) || defined(CDNA)) + asm volatile("v_dot2_f32_f16 %0, %1, %2, %0" : "+v"(acc) : "v"(v), "v"(u)); +#else +#ifdef FAST_FP16_AVAILABLE + const float2 tmp = __half22float2(v*u); + acc += tmp.x + tmp.y; +#else + const float2 tmpv = __half22float2(v); + const float2 tmpu = __half22float2(u); + acc += tmpv.x * tmpu.x; + acc += tmpv.y * tmpu.y; +#endif // FAST_FP16_AVAILABLE +#endif // defined(GGML_USE_HIP) && (defined(RDNA2) || defined(RDNA3) || defined(RDNA4) || defined(GCN5) || defined(CDNA)) +} + +static __device__ __forceinline__ void ggml_cuda_mad(half2 & acc, const half2 v, const half2 u) { +#ifdef FAST_FP16_AVAILABLE + acc += v*u; +#else + const float2 tmpv = __half22float2(v); + const float2 tmpu = __half22float2(u); + float2 tmpacc = __half22float2(acc); + tmpacc.x += tmpv.x * tmpu.x; + tmpacc.y += tmpv.y * tmpu.y; + acc = make_half2(tmpacc.x, tmpacc.y); +#endif // FAST_FP16_AVAILABLE +} + +// Aligned memory transfers of 8/16 bytes can be faster than 2 transfers with 4 bytes, especially on AMD. +template +static __device__ __forceinline__ void ggml_cuda_memcpy_1(void * __restrict__ dst, const void * __restrict__ src) { + if constexpr (alignment != 0) { + static_assert(nbytes % alignment == 0, "bad alignment"); + } + constexpr int nb_per_cpy = alignment == 0 ? nbytes : alignment; + +#pragma unroll + for (int i = 0; i < nbytes/nb_per_cpy; ++i) { + if constexpr (nb_per_cpy == 1) { + ((char *) dst)[i] = ((const char *) src)[i]; + } else if constexpr (nb_per_cpy == 2) { + ((short *) dst)[i] = ((const short *) src)[i]; + } else if constexpr (nb_per_cpy == 4) { + ((int *) dst)[i] = ((const int *) src)[i]; + } else if constexpr (nb_per_cpy == 8) { + ((int2 *) dst)[i] = ((const int2 *) src)[i]; + } else if constexpr (nb_per_cpy == 16) { + ((int4 *) dst)[i] = ((const int4 *) src)[i]; + } else { + static_assert(nbytes == 0 && nbytes == -1, "bad nbytes"); + } + } +} + +static __device__ __forceinline__ float ggml_cuda_e8m0_to_fp32(uint8_t x) { +#if CUDART_VERSION >= 12080 + const nv_bfloat16 e = __nv_cvt_e8m0_to_bf16raw(x); + return (float) e; +#else + uint32_t bits; + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint32_t) x << 23; + } + + float result; + memcpy(&result, &bits, sizeof(float)); + return result; +#endif // CUDART_VERSION >= 12050 +} + +// See https://gmplib.org/~tege/divcnst-pldi94.pdf figure 4.1. +// Precompute mp (m' in the paper) and L such that division +// can be computed using a multiply (high 32b of 64b result) +// and a shift: +// +// n/d = (mulhi(n, mp) + n) >> L; +static const uint3 init_fastdiv_values(uint32_t d) { + GGML_ASSERT(d != 0); + + // compute L = ceil(log2(d)); + uint32_t L = 0; + while (L < 32 && (uint32_t{ 1 } << L) < d) { + L++; + } + + uint32_t mp = (uint32_t) ((uint64_t{ 1 } << 32) * ((uint64_t{ 1 } << L) - d) / d + 1); + // pack divisor as well to reduce error surface + return make_uint3(mp, L, d); } -typedef void (*dequantize_kernel_t)(const void * vx, const int64_t ib, const int iqs, dfloat2 & v); +static __device__ __forceinline__ uint32_t fastdiv(uint32_t n, const uint3 fastdiv_values) { + // expects fastdiv_values to contain in + // fastdiv_values.z is unused and optimized away by the compiler. + // Compute high 32 bits of n * mp + const uint32_t hi = __umulhi(n, fastdiv_values.x); + // add n, apply bit shift + return (hi + n) >> fastdiv_values.y; +} + +static __device__ __forceinline__ uint32_t fastmodulo(uint32_t n, const uint3 fastdiv_values) { + // expects fastdiv_values to contain in (see init_fastdiv_values) + return n - fastdiv(n, fastdiv_values) * fastdiv_values.z; +} + +// Calculate both division and modulo at once, returns +static __device__ __forceinline__ uint2 fast_div_modulo(uint32_t n, const uint3 fastdiv_values) { + // expects fastdiv_values to contain in (see init_fastdiv_values) + const uint32_t div_val = fastdiv(n, fastdiv_values); + const uint32_t mod_val = n - div_val * fastdiv_values.z; + return make_uint2(div_val, mod_val); +} + +typedef void (*dequantize_kernel_t)(const void * vx, const int64_t ib, const int iqs, float2 & v); static __device__ __forceinline__ float get_alibi_slope( const float max_bias, const uint32_t h, const uint32_t n_head_log2, const float m0, const float m1 @@ -581,6 +744,13 @@ struct ggml_cuda_type_traits +struct ggml_cuda_type_traits { + static constexpr int qk = QK_MXFP4; + static constexpr int qr = QR_MXFP4; + static constexpr int qi = QI_MXFP4; +}; + +template<> struct ggml_cuda_type_traits { static constexpr int qk = QK_K; static constexpr int qr = QR2_K; @@ -765,7 +935,7 @@ struct ggml_tensor_extra_gpu { }; -#if (defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS)) +#if (defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS)) || defined(GGML_MUSA_GRAPHS) #define USE_CUDA_GRAPH #endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/conv-transpose-1d.cu 6641+dfsg-2/ggml/src/ggml-cuda/conv-transpose-1d.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/conv-transpose-1d.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/conv-transpose-1d.cu 2025-09-30 07:36:33.000000000 +0000 @@ -34,10 +34,7 @@ static __global__ void conv_transpose_1 } } dst[global_index] = accumulator; - GGML_UNUSED(p0); GGML_UNUSED(d0); GGML_UNUSED(src0_ne3); - GGML_UNUSED(src1_ne3); GGML_UNUSED(dst_ne3); - GGML_UNUSED(src1_ne1); GGML_UNUSED(dst_ne1); - GGML_UNUSED(src1_ne2); GGML_UNUSED(dst_ne2); + GGML_UNUSED_VARS(p0, d0, src0_ne3, src1_ne3, dst_ne3, src1_ne1, dst_ne1, src1_ne2, dst_ne2); } static void conv_transpose_1d_f32_f32_cuda( diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/conv2d.cu 6641+dfsg-2/ggml/src/ggml-cuda/conv2d.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/conv2d.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/conv2d.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,166 @@ +#include "conv2d.cuh" +#include "convert.cuh" + +struct conv_params { + const int64_t IW, IH; + const int64_t OW, OH; + const int64_t KW, KH; + const int64_t ST_X, ST_Y; + const int64_t PD_X, PD_Y; + const int64_t DL_X, DL_Y; + const int64_t IC, OC; + const int64_t B; + const int64_t TOTAL; +}; + +struct kernel_bounds { + int64_t y_min, y_max; + int64_t x_min, x_max; +}; + +__device__ __forceinline__ int64_t max64(int64_t a, int64_t b) { + return (a > b) ? a : b; +} + +__device__ __forceinline__ int64_t min64(int64_t a, int64_t b) { + return (a < b) ? a : b; +} + +__device__ __forceinline__ kernel_bounds calculate_kernel_bounds(int64_t out_x, int64_t out_y, const conv_params & P) { + kernel_bounds bounds; + bounds.y_min = max64(0, (P.PD_Y - out_y * P.ST_Y + P.DL_Y - 1) / P.DL_Y); + bounds.y_max = min64(P.KH, (P.IH + P.PD_Y - out_y * P.ST_Y + P.DL_Y - 1) / P.DL_Y); + bounds.x_min = max64(0, (P.PD_X - out_x * P.ST_X + P.DL_X - 1) / P.DL_X); + bounds.x_max = min64(P.KW, (P.IW + P.PD_X - out_x * P.ST_X + P.DL_X - 1) / P.DL_X); + return bounds; +} + +__device__ __forceinline__ int calculate_input_coord(int64_t out_coord, + int64_t kern_coord, + int64_t stride, + int64_t dilation, + int64_t padding) { + return out_coord * stride + kern_coord * dilation - padding; +} + +struct whcn_layout { + __device__ static int64_t input_index(int64_t n, int64_t c, int64_t y, int64_t x, const conv_params & P) { + return n * (P.IC * P.IW * P.IH) + c * P.IW * P.IH + y * P.IW + x; + } + + __device__ static int64_t kernel_index(int64_t c_out, int64_t c_in, int64_t ky, int64_t kx, const conv_params & P) { + return c_out * (P.IC * P.KH * P.KW) + c_in * (P.KH * P.KW) + ky * P.KW + kx; + } + + __device__ static int64_t output_index(int64_t n, int64_t c, int64_t y, int64_t x, const conv_params & P) { + return n * (P.OC * P.OW * P.OH) + c * P.OW * P.OH + y * P.OW + x; + } + + __device__ static void unpack_indices(int64_t global_idx, + const conv_params & P, + int64_t & n, + int64_t & c, + int64_t & out_y, + int64_t & out_x) { + out_x = global_idx % P.OW; + out_y = (global_idx / P.OW) % P.OH; + c = (global_idx / (P.OW * P.OH)) % P.OC; + n = global_idx / (P.OW * P.OH * P.OC); + } +}; + +template +static __global__ void conv2d_kernel(const float * __restrict__ input, + const T * __restrict__ kernel, + float * __restrict__ output, + const conv_params P) { + const int64_t global_idx = blockIdx.x * blockDim.x + threadIdx.x; + + if (global_idx >= P.TOTAL) { + return; + } + + int64_t n, c_out, out_y, out_x; + Layout::unpack_indices(global_idx, P, n, c_out, out_y, out_x); + + float acc = 0.0f; + + for (int64_t c_in = 0; c_in < P.IC; ++c_in) { + kernel_bounds bounds = calculate_kernel_bounds(out_x, out_y, P); + + for (int64_t ky = bounds.y_min; ky < bounds.y_max; ++ky) { + const int64_t in_y = calculate_input_coord(out_y, ky, P.ST_Y, P.DL_Y, P.PD_Y); + + for (int64_t kx = bounds.x_min; kx < bounds.x_max; ++kx) { + const int64_t in_x = calculate_input_coord(out_x, kx, P.ST_X, P.DL_X, P.PD_X); + + const float input_val = input[Layout::input_index(n, c_in, in_y, in_x, P)]; + const T kernel_val = kernel[Layout::kernel_index(c_out, c_in, ky, kx, P)]; + acc += (input_val * ggml_cuda_cast(kernel_val)); + } + } + } + + // [N, OC, OH, OW] + output[Layout::output_index(n, c_out, out_y, out_x, P)] = acc; +} + +template +static void conv2d_cuda(const float * X_D, const T * K_D, float * Y_D, const conv_params P, cudaStream_t st) { + const int blocks = (P.TOTAL + CUDA_CONV2D_BLOCK_SIZE - 1) / CUDA_CONV2D_BLOCK_SIZE; + conv2d_kernel<<>>(X_D, K_D, Y_D, P); +} + +static void conv2d_cuda_f16(const float * X_D, const half * K_D, float * Y_D, const conv_params P, cudaStream_t st) { + conv2d_cuda(X_D, K_D, Y_D, P, st); +} + +static void conv2d_cuda_f32(const float * X_D, const float * K_D, float * Y_D, const conv_params P, cudaStream_t st) { + conv2d_cuda(X_D, K_D, Y_D, P, st); +} + +void ggml_cuda_op_conv2d(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * kernel = dst->src[0]; + const ggml_tensor * input = dst->src[1]; + float * K_D = (float *) kernel->data; + const float * X_D = (const float *) input->data; + float * Y_D = (float *) dst->data; + + GGML_ASSERT(ggml_is_contiguous(kernel)); + GGML_ASSERT(kernel->type == GGML_TYPE_F16 || kernel->type == GGML_TYPE_F32); + + // same number of input channels + GGML_ASSERT(input->ne[2] == kernel->ne[2]); + + cudaStream_t st = ctx.stream(); + + const int32_t * p = (const int32_t *) dst->op_params; + const int ST_X = p[0]; // stride_x + const int ST_Y = p[1]; // stride_y + const int PD_X = p[2]; // padding_x + const int PD_Y = p[3]; // padding_y + const int DL_X = p[4]; // dilation_x + const int DL_Y = p[5]; // dilation_y + + // No cwhn + GGML_ASSERT(p[6] == false); + + const int IW = input->ne[0]; // input_w + const int IH = input->ne[1]; // input_h + const int OW = dst->ne[0]; // output_w + const int OH = dst->ne[1]; // output_h + const int KW = kernel->ne[0]; // kernel_w + const int KH = kernel->ne[1]; // kernel_h + const int IC = input->ne[2]; // input_channels + const int OC = kernel->ne[3]; // ouptut_chanles + const int B = input->ne[3]; // n_batches + + const int64_t total = B * OC * OH * OW; + conv_params params = { IW, IH, OW, OH, KW, KH, ST_X, ST_Y, PD_X, PD_Y, DL_X, DL_Y, IC, OC, B, total }; + + if (kernel->type == GGML_TYPE_F16) { + conv2d_cuda_f16(X_D, (half *) K_D, Y_D, params, st); + } else { + conv2d_cuda_f32(X_D, K_D, Y_D, params, st); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/conv2d.cuh 6641+dfsg-2/ggml/src/ggml-cuda/conv2d.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/conv2d.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/conv2d.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +#pragma once +#include "common.cuh" + +#define CUDA_CONV2D_BLOCK_SIZE 256 +void ggml_cuda_op_conv2d(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/convert.cu 6641+dfsg-2/ggml/src/ggml-cuda/convert.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/convert.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/convert.cu 2025-09-30 07:36:33.000000000 +0000 @@ -6,24 +6,33 @@ #define CUDA_Q8_0_NE_ALIGN 2048 template -static __global__ void dequantize_block(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k) { - const int64_t i = (int64_t)2*(blockDim.x*blockIdx.x + threadIdx.x); +static __global__ void dequantize_block(const void * __restrict__ vx, dst_t * __restrict__ y, + const int64_t ne00, const int64_t ne01, const int64_t ne02, + const int64_t s01, const int64_t s02, const int64_t s03) { + const int64_t i00 = 2 * (int64_t(blockDim.x)*blockIdx.x + threadIdx.x); - if (i >= k) { + if (i00 >= ne00) { return; } - const int64_t ib = i/qk; // block index - const int64_t iqs = (i%qk)/qr; // quant index - const int64_t iybs = i - i%qk; // y block start index + const int64_t i01 = blockIdx.y; + const int64_t i02 = blockIdx.z % ne02; + const int64_t i03 = blockIdx.z / ne02; + + const int64_t ibx0 = i03*s03 + i02*s02 + i01*s01; + + const int64_t ib = ibx0 + i00/qk; // block index + const int64_t iqs = (i00%qk)/qr; // quant index + const int64_t iybs = i00 - i00%qk; // y block start index const int64_t y_offset = qr == 1 ? 1 : qk/2; // dequantize - dfloat2 v; + float2 v; dequantize_kernel(vx, ib, iqs, v); - y[iybs + iqs + 0] = v.x; - y[iybs + iqs + y_offset] = v.y; + const int64_t iy0 = ((i03*ne02 + i02)*ne01 + i01)*ne00 + iybs + iqs; + y[iy0 + 0] = ggml_cuda_cast(v.x); + y[iy0 + y_offset] = ggml_cuda_cast(v.y); } template @@ -62,9 +71,7 @@ static __global__ void dequantize_block_ y2[iy/2 + threadIdx.x] = __hmul2(make_half2(qs.x, qs.y), __half2half2(d)); } #else - GGML_UNUSED(vx); - GGML_UNUSED(y); - GGML_UNUSED(k); + GGML_UNUSED_VARS(vx, y, k); NO_DEVICE_CODE; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_PASCAL } @@ -456,10 +463,36 @@ static __global__ void dequantize_block_ } } +template +static __global__ void dequantize_block_mxfp4(const void * __restrict__ vx, dst_t * __restrict__ yy) { + + const int64_t i = blockIdx.x; + const block_mxfp4 * x = (const block_mxfp4 *) vx + i*(QK_K/QK_MXFP4); + + const int64_t tid = threadIdx.x; + const int64_t il = tid/8; // 0...3 + const int64_t ib = tid%8; // 0...7 + dst_t * y = yy + i*QK_K + 32*ib + 4*il; + const uint8_t * q4 = x[ib].qs + 4*il; + const float d = ggml_cuda_e8m0_to_fp32(x[ib].e); + for (int j = 0; j < 4; ++j) { + y[j+ 0] = d * kvalues_mxfp4[q4[j] & 0xf]*0.5f; + y[j+16] = d * kvalues_mxfp4[q4[j] >> 4]*0.5f; + } +} + template -static void dequantize_block_cuda(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k, cudaStream_t stream) { - const int num_blocks = (k + 2*CUDA_DEQUANTIZE_BLOCK_SIZE - 1) / (2*CUDA_DEQUANTIZE_BLOCK_SIZE); - dequantize_block<<>>(vx, y, k); +static void dequantize_block_cuda(const void * vx, dst_t * y, + const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, + const int64_t s01, const int64_t s02, const int64_t s03, cudaStream_t stream) { + const dim3 num_blocks((ne00 + 2*CUDA_DEQUANTIZE_BLOCK_SIZE - 1) / (2*CUDA_DEQUANTIZE_BLOCK_SIZE), ne01, ne02*ne03); + dequantize_block<<>> + (vx, y, ne00, ne01, ne02, s01, s02, s03); +} + +template +static void dequantize_block_cont_cuda(const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t k, cudaStream_t stream) { + dequantize_block_cuda(vx, y, k, 1, 1, 1, k/qk, k/qk, k/qk, stream); } static void dequantize_block_q8_0_f16_cuda(const void * __restrict__ vx, half * __restrict__ y, const int64_t k, cudaStream_t stream) { @@ -571,6 +604,12 @@ static void dequantize_row_iq4_xs_cuda(c dequantize_block_iq4_xs<<>>(vx, y); } +template +static void dequantize_row_mxfp4_cuda(const void * vx, dst_t * y, const int64_t k, cudaStream_t stream) { + const int nb = (k + QK_K - 1) / QK_K; + dequantize_block_mxfp4<<>>(vx, y); +} + template static __global__ void convert_unary( const void * __restrict__ vx, dst_t * __restrict__ y, const int64_t ne00, const int64_t ne01, const int64_t ne02, @@ -589,7 +628,7 @@ static __global__ void convert_unary( const int64_t ix = i03*s03 + i02*s02 + i01*s01 + i00; const int64_t iy = ((i03*ne02 + i02)*ne01 + i01)*ne00 + i00; - y[iy] = float(x[ix]); + y[iy] = ggml_cuda_cast(x[ix]); } template @@ -624,14 +663,14 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggm case GGML_TYPE_Q4_1: return dequantize_row_q4_1_cuda; case GGML_TYPE_Q5_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q5_1: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q8_0: if (fp16_available(ggml_cuda_info().devices[ggml_cuda_get_device()].cc)) { return dequantize_block_q8_0_f16_cuda; } - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q2_K: return dequantize_row_q2_K_cuda; case GGML_TYPE_Q3_K: @@ -660,6 +699,8 @@ to_fp16_cuda_t ggml_get_to_fp16_cuda(ggm return dequantize_row_iq4_xs_cuda; case GGML_TYPE_IQ3_S: return dequantize_row_iq3_s_cuda; + case GGML_TYPE_MXFP4: + return dequantize_row_mxfp4_cuda; case GGML_TYPE_F32: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -676,11 +717,11 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggm case GGML_TYPE_Q4_1: return dequantize_row_q4_1_cuda; case GGML_TYPE_Q5_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q5_1: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q8_0: - return dequantize_block_cuda; + return dequantize_block_cont_cuda; case GGML_TYPE_Q2_K: return dequantize_row_q2_K_cuda; case GGML_TYPE_Q3_K: @@ -709,6 +750,8 @@ to_fp32_cuda_t ggml_get_to_fp32_cuda(ggm return dequantize_row_iq4_xs_cuda; case GGML_TYPE_IQ3_S: return dequantize_row_iq3_s_cuda; + case GGML_TYPE_MXFP4: + return dequantize_row_mxfp4_cuda; case GGML_TYPE_F16: return convert_unary_cont_cuda; case GGML_TYPE_BF16: @@ -722,6 +765,16 @@ to_fp16_nc_cuda_t ggml_get_to_fp16_nc_cu switch (type) { case GGML_TYPE_F32: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: @@ -733,6 +786,16 @@ to_bf16_nc_cuda_t ggml_get_to_bf16_nc_cu switch (type) { case GGML_TYPE_F32: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_F16: return convert_unary_cuda; default: @@ -744,6 +807,16 @@ to_fp32_nc_cuda_t ggml_get_to_fp32_nc_cu switch (type) { case GGML_TYPE_F16: return convert_unary_cuda; + case GGML_TYPE_Q4_0: + return dequantize_block_cuda; + case GGML_TYPE_Q4_1: + return dequantize_block_cuda; + case GGML_TYPE_Q5_0: + return dequantize_block_cuda; + case GGML_TYPE_Q5_1: + return dequantize_block_cuda; + case GGML_TYPE_Q8_0: + return dequantize_block_cuda; case GGML_TYPE_BF16: return convert_unary_cuda; default: diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/convert.cuh 6641+dfsg-2/ggml/src/ggml-cuda/convert.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/convert.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/convert.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -29,3 +29,18 @@ typedef to_t_nc_cuda_t to_b to_fp32_nc_cuda_t ggml_get_to_fp32_nc_cuda(ggml_type type); to_fp16_nc_cuda_t ggml_get_to_fp16_nc_cuda(ggml_type type); to_bf16_nc_cuda_t ggml_get_to_bf16_nc_cuda(ggml_type type); + +template + __host__ __device__ inline dst_t ggml_cuda_cast(src_t x) { + if constexpr (std::is_same_v) { + return x; + } else if constexpr(std::is_same_v) { + return __float2bfloat16(float(x)); + } else if constexpr(std::is_same_v) { + return __bfloat162float(x); + } else if constexpr(std::is_same_v) { + return int32_t(x); + } else { + return float(x); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/cpy-utils.cuh 6641+dfsg-2/ggml/src/ggml-cuda/cpy-utils.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/cpy-utils.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/cpy-utils.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,217 @@ +#pragma once + +#include "ggml-common.h" +#include "convert.cuh" + +static __device__ __forceinline__ int best_index_int8(int n, const int8_t * val, float x) { + if (x <= val[0]) return 0; + if (x >= val[n-1]) return n-1; + int ml = 0, mu = n-1; + while (mu-ml > 1) { + int mav = (ml+mu)/2; + if (x < val[mav]) mu = mav; else ml = mav; + } + return x - val[mu-1] < val[mu] - x ? mu-1 : mu; +} + +static __device__ void quantize_f32_q4_0_block(const float * __restrict__ x, block_q4_0 * __restrict__ y) { + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_0; ++j) { + const float v = x[j]; + if (amax < fabsf(v)) { + amax = fabsf(v); + vmax = v; + } + } + + const float d = vmax / -8; + const float id = d ? 1.0f/d : 0.0f; + + y->d = d; + + for (int j = 0; j < QK4_0/2; ++j) { + const float x0 = x[0 + j]*id; + const float x1 = x[QK4_0/2 + j]*id; + + const uint8_t xi0 = min(15, (int8_t)(x0 + 8.5f)); + const uint8_t xi1 = min(15, (int8_t)(x1 + 8.5f)); + + y->qs[j] = xi0; + y->qs[j] |= xi1 << 4; + } +} + +static __device__ void quantize_f32_q4_1_block(const float * __restrict__ x, block_q4_1 * __restrict__ y) { + float vmin = FLT_MAX; + float vmax = -FLT_MAX; + + for (int j = 0; j < QK4_1; ++j) { + const float v = x[j]; + if (v < vmin) vmin = v; + if (v > vmax) vmax = v; + } + + const float d = (vmax - vmin) / ((1 << 4) - 1); + const float id = d ? 1.0f/d : 0.0f; + + y->dm.x = d; + y->dm.y = vmin; + + for (int j = 0; j < QK4_1/2; ++j) { + const float x0 = (x[0 + j] - vmin)*id; + const float x1 = (x[QK4_1/2 + j] - vmin)*id; + + const uint8_t xi0 = min(15, (int8_t)(x0 + 0.5f)); + const uint8_t xi1 = min(15, (int8_t)(x1 + 0.5f)); + + y->qs[j] = xi0; + y->qs[j] |= xi1 << 4; + } +} + +static __device__ void quantize_f32_q5_0_block(const float * __restrict__ x, block_q5_0 * __restrict__ y) { + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK5_0; ++j) { + const float v = x[j]; + if (amax < fabsf(v)) { + amax = fabsf(v); + vmax = v; + } + } + + const float d = vmax / -16; + const float id = d ? 1.0f/d : 0.0f; + + y->d = d; + + uint32_t qh = 0; + for (int j = 0; j < QK5_0/2; ++j) { + const float x0 = x[0 + j]*id; + const float x1 = x[QK5_0/2 + j]*id; + + const uint8_t xi0 = min(31, (int8_t)(x0 + 16.5f)); + const uint8_t xi1 = min(31, (int8_t)(x1 + 16.5f)); + + y->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0/2); + } + memcpy(y->qh, &qh, sizeof(qh)); +} + +static __device__ void quantize_f32_q5_1_block(const float * __restrict__ x, block_q5_1 * __restrict__ y) { + float min = x[0]; + float max = x[0]; + + for (int j = 1; j < QK5_1; ++j) { + const float v = x[j]; + min = v < min ? v : min; + max = v > max ? v : max; + } + + const float d = (max - min) / 31; + const float id = d ? 1.0f/d : 0.0f; + + y->dm.x = d; + y->dm.y = min; + + uint32_t qh = 0; + for (int j = 0; j < QK5_1/2; ++j) { + const float x0 = (x[0 + j] - min)*id; + const float x1 = (x[QK5_1/2 + j] - min)*id; + + const uint8_t xi0 = (uint8_t)(x0 + 0.5f); + const uint8_t xi1 = (uint8_t)(x1 + 0.5f); + + y->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1/2); + } + memcpy(y->qh, &qh, sizeof(qh)); +} + +static __device__ void quantize_f32_q8_0_block(const float * __restrict__ x, block_q8_0 * __restrict__ y) { + float amax = 0.0f; // absolute max + + for (int j = 0; j < QK8_0; j++) { + const float v = x[j]; + amax = fmaxf(amax, fabsf(v)); + } + + const float d = amax / ((1 << 7) - 1); + const float id = d ? 1.0f/d : 0.0f; + + y->d = d; + + for (int j = 0; j < QK8_0; ++j) { + const float x0 = x[j]*id; + y->qs[j] = roundf(x0); + } +} + +static __device__ void quantize_f32_iq4_nl_block(const float * __restrict__ x, block_iq4_nl * __restrict__ y) { + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_NL; ++j) { + const float v = x[j]; + if (amax < fabsf(v)) { + amax = fabsf(v); + vmax = v; + } + } + + float d = vmax / kvalues_iq4nl[0]; + const float id = d ? 1.0f/d : 0.0f; + + float sumqx = 0, sumq2 = 0; + for (int j = 0; j < QK4_NL/2; ++j) { + const float x0 = x[0 + j]*id; + const float x1 = x[QK4_NL/2 + j]*id; + const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); + const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); + y->qs[j] = xi0 | (xi1 << 4); + const float v0 = kvalues_iq4nl[xi0]; + const float v1 = kvalues_iq4nl[xi1]; + const float w0 = x[0 + j]*x[0 + j]; + const float w1 = x[QK4_NL/2 + j]*x[QK4_NL/2 + j]; + sumqx += w0*v0*x[j] + w1*v1*x[QK4_NL/2 + j]; + sumq2 += w0*v0*v0 + w1*v1*v1; + } + + y->d = sumq2 > 0 ? sumqx/sumq2 : d; +} + +// Wrapper functions for cpy.cu compatibility +static __device__ void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { + quantize_f32_q4_0_block((const float *)cxi, (block_q4_0 *)cdsti); +} + +static __device__ void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { + quantize_f32_q4_1_block((const float *)cxi, (block_q4_1 *)cdsti); +} + +static __device__ void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { + quantize_f32_q5_0_block((const float *)cxi, (block_q5_0 *)cdsti); +} + +static __device__ void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { + quantize_f32_q5_1_block((const float *)cxi, (block_q5_1 *)cdsti); +} + +static __device__ void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { + quantize_f32_q8_0_block((const float *)cxi, (block_q8_0 *)cdsti); +} + +static __device__ void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { + quantize_f32_iq4_nl_block((const float *)cxi, (block_iq4_nl *)cdsti); +} + +template +static __device__ void cpy_1_flt(const char * cxi, char * cdsti) { + *(dst_t *) cdsti = ggml_cuda_cast(*(const src_t *) cxi); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/cpy.cu 6641+dfsg-2/ggml/src/ggml-cuda/cpy.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/cpy.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/cpy.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,51 +1,17 @@ #include "cpy.cuh" #include "dequantize.cuh" -#ifdef GGML_USE_MUSA +#include "cpy-utils.cuh" +#if defined(GGML_USE_MUSA) && defined(GGML_MUSA_MUDNN_COPY) #include "ggml-musa/mudnn.cuh" -#endif // GGML_USE_MUSA +#endif // GGML_USE_MUSA && GGML_MUSA_MUDNN_COPY typedef void (*cpy_kernel_t)(const char * cx, char * cdst); -static __device__ void cpy_1_f32_f32(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - float * dsti = (float *) cdsti; - - *dsti = *xi; -} - -static __device__ void cpy_1_f32_bf16(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - nv_bfloat16 * dsti = (nv_bfloat16 *) cdsti; - - *dsti = *xi; -} - -static __device__ void cpy_1_f32_f16(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - half * dsti = (half *) cdsti; - - *dsti = __float2half(*xi); -} - -static __device__ void cpy_1_f16_f16(const char * cxi, char * cdsti) { - const half * xi = (const half *) cxi; - half * dsti = (half *) cdsti; - - *dsti = *xi; -} - -static __device__ void cpy_1_f16_f32(const char * cxi, char * cdsti) { - const half * xi = (const half *) cxi; - float * dsti = (float *) cdsti; - - *dsti = *xi; -} - template -static __global__ void cpy_f32_f16(const char * cx, char * cdst_direct, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, - const int nb12, const int nb13, char ** cdst_indirect, int graph_cpynode_index) { +static __global__ void cpy_flt(const char * cx, char * cdst_direct, const int ne, + const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, + const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, + const int nb12, const int nb13, char ** cdst_indirect, int graph_cpynode_index) { const int64_t i = blockDim.x*blockIdx.x + threadIdx.x; if (i >= ne) { @@ -71,234 +37,31 @@ static __global__ void cpy_f32_f16(const cpy_1(cx + x_offset, cdst + dst_offset); } -static __device__ void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q8_0 * dsti = (block_q8_0 *) cdsti; - - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - const float v = xi[j]; - amax = fmaxf(amax, fabsf(v)); - } - - const float d = amax / ((1 << 7) - 1); - const float id = d ? 1.0f/d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK8_0; ++j) { - const float x0 = xi[j]*id; - - dsti->qs[j] = roundf(x0); - } -} - static __device__ void cpy_blck_q8_0_f32(const char * cxi, char * cdsti) { float * cdstf = (float *)(cdsti); #pragma unroll for (int j = 0; j < QK8_0; j += 2) { - dfloat2 dq; + float2 dq; dequantize_q8_0(cxi, 0, j, dq); *(cdstf + j) = dq.x; *(cdstf + j + 1) = dq.y; } } -static __device__ void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_0 * dsti = (block_q4_0 *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_0; ++j) { - const float v = xi[j]; - if (amax < fabsf(v)) { - amax = fabsf(v); - vmax = v; - } - } - - const float d = vmax / -8; - const float id = d ? 1.0f/d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK4_0/2; ++j) { - const float x0 = xi[0 + j]*id; - const float x1 = xi[QK4_0/2 + j]*id; - - const uint8_t xi0 = min(15, (int8_t)(x0 + 8.5f)); - const uint8_t xi1 = min(15, (int8_t)(x1 + 8.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static __device__ void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_1 * dsti = (block_q4_1 *) cdsti; - - float vmin = FLT_MAX; - float vmax = -FLT_MAX; - - for (int j = 0; j < QK4_1; ++j) { - const float v = xi[j]; - - if (v < vmin) vmin = v; - if (v > vmax) vmax = v; - } - - const float d = (vmax - vmin) / ((1 << 4) - 1); - const float id = d ? 1.0f/d : 0.0f; - - dsti->dm.x = d; - dsti->dm.y = vmin; - - for (int j = 0; j < QK4_1/2; ++j) { - const float x0 = (xi[0 + j] - vmin)*id; - const float x1 = (xi[QK4_1/2 + j] - vmin)*id; - - const uint8_t xi0 = min(15, (int8_t)(x0 + 0.5f)); - const uint8_t xi1 = min(15, (int8_t)(x1 + 0.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static __device__ void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_0 * dsti = (block_q5_0 *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK5_0; ++j) { - const float v = xi[j]; - if (amax < fabsf(v)) { - amax = fabsf(v); - vmax = v; - } - } - - const float d = vmax / -16; - const float id = d ? 1.0f/d : 0.0f; - - dsti->d = d; - - uint32_t qh = 0; - for (int j = 0; j < QK5_0/2; ++j) { - const float x0 = xi[0 + j]*id; - const float x1 = xi[QK5_0/2 + j]*id; - - const uint8_t xi0 = min(31, (int8_t)(x0 + 16.5f)); - const uint8_t xi1 = min(31, (int8_t)(x1 + 16.5f)); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0/2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - -static __device__ void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_1 * dsti = (block_q5_1 *) cdsti; - - float min = xi[0]; - float max = xi[0]; - - for (int j = 1; j < QK5_1; ++j) { - const float v = xi[j]; - min = v < min ? v : min; - max = v > max ? v : max; - } - - const float d = (max - min) / 31; - const float id = d ? 1.0f/d : 0.0f; - - dsti->dm.x = d; - dsti->dm.y = min; - - uint32_t qh = 0; - for (int j = 0; j < QK5_1/2; ++j) { - const float x0 = (xi[0 + j] - min)*id; - const float x1 = (xi[QK5_1/2 + j] - min)*id; - - const uint8_t xi0 = (uint8_t)(x0 + 0.5f); - const uint8_t xi1 = (uint8_t)(x1 + 0.5f); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1/2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - template static __device__ void cpy_blck_q_f32(const char * cxi, char * cdsti) { float * cdstf = (float *)(cdsti); #pragma unroll for (int j = 0; j < qk/2; j++) { - dfloat2 dq; + float2 dq; dequant(cxi, 0, j, dq); *(cdstf + j) = dq.x; *(cdstf + j + qk/2) = dq.y; } } -static __device__ __forceinline__ int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) return 0; - if (x >= val[n-1]) return n-1; - int ml = 0, mu = n-1; - while (mu-ml > 1) { - int mav = (ml+mu)/2; - if (x < val[mav]) mu = mav; else ml = mav; - } - return x - val[mu-1] < val[mu] - x ? mu-1 : mu; -} - -static __device__ void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_iq4_nl * dsti = (block_iq4_nl *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_NL; ++j) { - const float v = xi[j]; - if (amax < fabsf(v)) { - amax = fabsf(v); - vmax = v; - } - } - - float d = vmax / kvalues_iq4nl[0]; - const float id = d ? 1.0f/d : 0.0f; - - float sumqx = 0, sumq2 = 0; - for (int j = 0; j < QK4_NL/2; ++j) { - const float x0 = xi[0 + j]*id; - const float x1 = xi[QK4_NL/2 + j]*id; - const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); - const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); - dsti->qs[j] = xi0 | (xi1 << 4); - const float v0 = kvalues_iq4nl[xi0]; - const float v1 = kvalues_iq4nl[xi1]; - const float w0 = xi[0 + j]*xi[0 + j]; - const float w1 = xi[QK4_NL/2 + j]*xi[QK4_NL/2 + j]; - sumqx += w0*v0*xi[j] + w1*v1*xi[QK4_NL/2 + j]; - sumq2 += w0*v0*v0 + w1*v1*v1; - } - - dsti->d = sumq2 > 0 ? sumqx/sumq2 : d; -} - template static __global__ void cpy_f32_q(const char * cx, char * cdst_direct, const int ne, const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, @@ -358,7 +121,7 @@ static __global__ void cpy_q_f32(const c // Copy destination pointers to GPU to be available when pointer indirection is in use void ggml_cuda_cpy_dest_ptrs_copy(ggml_cuda_graph * cuda_graph, char ** host_dest_ptrs, const int host_dest_ptrs_size, cudaStream_t stream) { -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if (cuda_graph->dest_ptrs_size < host_dest_ptrs_size) { // (re-)allocate GPU memory for destination pointers CUDA_CHECK(cudaStreamSynchronize(stream)); if (cuda_graph->dest_ptrs_d != nullptr) { @@ -371,48 +134,18 @@ void ggml_cuda_cpy_dest_ptrs_copy(ggml_c CUDA_CHECK(cudaMemcpyAsync(cuda_graph->dest_ptrs_d, host_dest_ptrs, host_dest_ptrs_size*sizeof(char *), cudaMemcpyHostToDevice, stream)); cuda_graph->graph_cpynode_index = 0; // reset index #else - GGML_UNUSED(cuda_graph); GGML_UNUSED(host_dest_ptrs); - GGML_UNUSED(host_dest_ptrs_size); GGML_UNUSED(stream); + GGML_UNUSED_VARS(cuda_graph, host_dest_ptrs, host_dest_ptrs_size, stream); #endif } -static void ggml_cpy_f16_f32_cuda( +template +static void ggml_cpy_flt_cuda( const char * cx, char * cdst, const int ne, const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_f32_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_bf16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - -static void ggml_cpy_f32_f16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> + cpy_flt><<>> (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); } @@ -544,16 +277,6 @@ static void ggml_cpy_f32_iq4_nl_cuda( (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); } -static void ggml_cpy_f16_f16_cuda( - const char * cx, char * cdst, const int ne, - const int ne00, const int ne01, const int ne02, const int nb00, const int nb01, const int nb02, - const int nb03, const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, cudaStream_t stream, char ** cdst_indirect, int & graph_cpynode_index) { - - const int num_blocks = (ne + CUDA_CPY_BLOCK_SIZE - 1) / CUDA_CPY_BLOCK_SIZE; - cpy_f32_f16<<>> - (cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, cdst_indirect, graph_cpynode_index++); -} - void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, ggml_tensor * src1, bool disable_indirection_for_this_node) { const int64_t ne = ggml_nelements(src0); GGML_ASSERT(ne == ggml_nelements(src1)); @@ -590,7 +313,7 @@ void ggml_cuda_cpy(ggml_backend_cuda_con char ** dest_ptrs_d = nullptr; int graph_cpynode_index = -1; -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if(ctx.cuda_graph->use_cpy_indirection && !disable_indirection_for_this_node) { dest_ptrs_d = ctx.cuda_graph->dest_ptrs_d; graph_cpynode_index = ctx.cuda_graph->graph_cpynode_index; @@ -600,20 +323,20 @@ void ggml_cuda_cpy(ggml_backend_cuda_con #endif if (src0->type == src1->type && ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { GGML_ASSERT(ggml_nbytes(src0) == ggml_nbytes(src1)); -#ifdef GGML_USE_MUSA +#if defined(GGML_USE_MUSA) && defined(GGML_MUSA_MUDNN_COPY) if (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16) { CUDA_CHECK(mudnnMemcpyAsync(ctx, src1, src0)); } else -#endif // GGML_USE_MUSA +#endif // GGML_USE_MUSA && GGML_MUSA_MUDNN_COPY { CUDA_CHECK(cudaMemcpyAsync(src1_ddc, src0_ddc, ggml_nbytes(src0), cudaMemcpyDeviceToDevice, main_stream)); } } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { - ggml_cpy_f32_f32_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_BF16) { - ggml_cpy_f32_bf16_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F16) { - ggml_cpy_f32_f16_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_Q8_0) { ggml_cpy_f32_q8_0_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_Q8_0 && src1->type == GGML_TYPE_F32) { @@ -640,14 +363,26 @@ void ggml_cuda_cpy(ggml_backend_cuda_con } else if (src0->type == GGML_TYPE_Q5_1 && src1->type == GGML_TYPE_F32) { ggml_cpy_q5_1_f32_cuda(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { - ggml_cpy_f16_f16_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_BF16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { - ggml_cpy_f16_f32_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_BF16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F16) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F32) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_I32) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); + } else if (src0->type == GGML_TYPE_I32 && src1->type == GGML_TYPE_F32) { + ggml_cpy_flt_cuda (src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream, dest_ptrs_d, graph_cpynode_index); } else { GGML_ABORT("%s: unsupported type combination (%s to %s)\n", __func__, ggml_type_name(src0->type), ggml_type_name(src1->type)); } -#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) +#if defined(GGML_CUDA_USE_GRAPHS) || defined(GGML_HIP_GRAPHS) || defined(GGML_MUSA_GRAPHS) if(ctx.cuda_graph->use_cpy_indirection && !disable_indirection_for_this_node) { ctx.cuda_graph->graph_cpynode_index = graph_cpynode_index; } @@ -667,11 +402,11 @@ void* ggml_cuda_cpy_fn(const ggml_tensor if (src0->type == src1->type && ggml_is_contiguous(src0) && ggml_is_contiguous(src1)) { return nullptr; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_BF16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_Q8_0) { return (void*) cpy_f32_q; } else if (src0->type == GGML_TYPE_Q8_0 && src1->type == GGML_TYPE_F32) { @@ -695,9 +430,21 @@ void* ggml_cuda_cpy_fn(const ggml_tensor } else if (src0->type == GGML_TYPE_Q5_1 && src1->type == GGML_TYPE_F32) { return (void*) cpy_q_f32, QK5_1>; } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_BF16) { + return (void*) cpy_flt>; } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { - return (void*) cpy_f32_f16; + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F16) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_BF16) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_BF16 && src1->type == GGML_TYPE_F32) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_I32) { + return (void*) cpy_flt>; + } else if (src0->type == GGML_TYPE_I32 && src1->type == GGML_TYPE_F32) { + return (void*) cpy_flt>; } else { GGML_ABORT("%s: unsupported type combination (%s to %s)\n", __func__, ggml_type_name(src0->type), ggml_type_name(src1->type)); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/dequantize.cuh 6641+dfsg-2/ggml/src/ggml-cuda/dequantize.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/dequantize.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/dequantize.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -1,48 +1,37 @@ #include "common.cuh" -static __device__ __forceinline__ void dequantize_q4_0(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ +static __device__ __forceinline__ void dequantize_q4_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q4_0 * x = (const block_q4_0 *) vx; - const dfloat d = x[ib].d; + const float d = x[ib].d; const int vui = x[ib].qs[iqs]; v.x = vui & 0xF; v.y = vui >> 4; -#ifdef GGML_CUDA_F16 - v = __hsub2(v, {8.0f, 8.0f}); - v = __hmul2(v, {d, d}); -#else v.x = (v.x - 8.0f) * d; v.y = (v.y - 8.0f) * d; -#endif // GGML_CUDA_F16 } -static __device__ __forceinline__ void dequantize_q4_1(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ +static __device__ __forceinline__ void dequantize_q4_1(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q4_1 * x = (const block_q4_1 *) vx; - const dfloat d = __low2half(x[ib].dm); - const dfloat m = __high2half(x[ib].dm); + const float2 dm = __half22float2(x[ib].dm); const int vui = x[ib].qs[iqs]; v.x = vui & 0xF; v.y = vui >> 4; -#ifdef GGML_CUDA_F16 - v = __hmul2(v, {d, d}); - v = __hadd2(v, {m, m}); -#else - v.x = (v.x * d) + m; - v.y = (v.y * d) + m; -#endif // GGML_CUDA_F16 + v.x = (v.x * dm.x) + dm.y; + v.y = (v.y * dm.x) + dm.y; } -static __device__ __forceinline__ void dequantize_q5_0(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ +static __device__ __forceinline__ void dequantize_q5_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q5_0 * x = (const block_q5_0 *) vx; - const dfloat d = x[ib].d; + const float d = x[ib].d; uint32_t qh; memcpy(&qh, x[ib].qh, sizeof(qh)); @@ -53,20 +42,14 @@ static __device__ __forceinline__ void d v.x = ((x[ib].qs[iqs] & 0xf) | xh_0); v.y = ((x[ib].qs[iqs] >> 4) | xh_1); -#ifdef GGML_CUDA_F16 - v = __hsub2(v, {16.0f, 16.0f}); - v = __hmul2(v, {d, d}); -#else v.x = (v.x - 16.0f) * d; v.y = (v.y - 16.0f) * d; -#endif // GGML_CUDA_F16 } -static __device__ __forceinline__ void dequantize_q5_1(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ +static __device__ __forceinline__ void dequantize_q5_1(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q5_1 * x = (const block_q5_1 *) vx; - const dfloat d = __low2half(x[ib].dm); - const dfloat m = __high2half(x[ib].dm); + const float2 dm = __half22float2(x[ib].dm); uint32_t qh; memcpy(&qh, x[ib].qh, sizeof(qh)); @@ -77,27 +60,18 @@ static __device__ __forceinline__ void d v.x = ((x[ib].qs[iqs] & 0xf) | xh_0); v.y = ((x[ib].qs[iqs] >> 4) | xh_1); -#ifdef GGML_CUDA_F16 - v = __hmul2(v, {d, d}); - v = __hadd2(v, {m, m}); -#else - v.x = (v.x * d) + m; - v.y = (v.y * d) + m; -#endif // GGML_CUDA_F16 + v.x = (v.x * dm.x) + dm.y; + v.y = (v.y * dm.x) + dm.y; } -static __device__ __forceinline__ void dequantize_q8_0(const void * vx, const int64_t ib, const int iqs, dfloat2 & v){ +static __device__ __forceinline__ void dequantize_q8_0(const void * vx, const int64_t ib, const int iqs, float2 & v){ const block_q8_0 * x = (const block_q8_0 *) vx; - const dfloat d = x[ib].d; + const float d = x[ib].d; v.x = x[ib].qs[iqs + 0]; v.y = x[ib].qs[iqs + 1]; -#ifdef GGML_CUDA_F16 - v = __hmul2(v, {d, d}); -#else v.x *= d; v.y *= d; -#endif // GGML_CUDA_F16 } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-common.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-common.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-common.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-common.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -15,6 +15,8 @@ typedef void (* fattn_kernel_t)( const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -23,302 +25,238 @@ typedef void (* fattn_kernel_t)( const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3); + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33); -typedef half (*vec_dot_KQ_f16_t)( - const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8 , const void * __restrict__ Q_ds); -typedef float (*vec_dot_KQ_f32_t)( +typedef float (*vec_dot_KQ_t)( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8 , const void * __restrict__ Q_ds); -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_q4_0( +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_f16( + const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8 , const void * __restrict__ Q_ds_v) { + + const half2 * K_h2 = (const half2 *) K_c; + GGML_UNUSED(Q_q8); + GGML_UNUSED(Q_ds_v); + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + + float sum = 0.0f; + +#pragma unroll + for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += nthreads*cpy_ne) { + half2 tmp[cpy_ne]; + ggml_cuda_memcpy_1(tmp, K_h2 + k_KQ_0 + (threadIdx.x % nthreads)*cpy_ne); +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < cpy_ne; ++k_KQ_1) { +#ifdef FAST_FP16_AVAILABLE + ggml_cuda_mad(sum, tmp[k_KQ_1] , ((const half2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]); +#else + ggml_cuda_mad(sum, __half22float2(tmp[k_KQ_1]), ((const float2 *) Q_v)[k_KQ_0/nthreads + k_KQ_1]); +#endif // FP16_AVAILABLE + } + } + + return sum; +} + +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q4_0( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { const block_q4_0 * K_q4_0 = (const block_q4_0 *) K_c; GGML_UNUSED(Q_v); - T sum = 0.0f; + float sum = 0.0f; #pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += nthreads) { + const int k_KQ = k_KQ_0 + (nthreads == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads); const int ib = k_KQ / QI8_1; const int iqs4 = k_KQ % QI4_0; const int shift = k_KQ & (QI8_1/2); - const int v = (get_int_b2(K_q4_0[ib].qs, iqs4) >> shift) & 0x0F0F0F0F; - const int u = Q_q8[k_KQ_0/warp_size]; + int v; + ggml_cuda_memcpy_1(&v, K_q4_0[ib].qs + sizeof(int)*iqs4); + v = (v >> shift) & 0x0F0F0F0F; + const int u = Q_q8[k_KQ_0/nthreads]; const int sumi = ggml_cuda_dp4a(v, u, 0); -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - const half2 * Q_ds = (const half2 *) Q_ds_v; - - const half2 sum2 = __half2half2(K_q4_0[ib].d) * Q_ds[k_KQ_0/warp_size]; - sum += (T) (((half) sumi)*__low2half(sum2) - __high2half(sum2) /* *8/QI8_1 == 1 */); - } else -#endif // FP16_AVAILABLE - { - const float2 * Q_ds = (const float2 *) Q_ds_v; - - sum += (T) (__half2float(K_q4_0[ib].d) * (sumi*Q_ds[k_KQ_0/warp_size].x - (8/QI8_1)*Q_ds[k_KQ_0/warp_size].y)); - } + const float2 Q_ds = ((const float2 *) Q_ds_v)[k_KQ_0/nthreads]; + sum += __half2float(K_q4_0[ib].d) * (sumi*Q_ds.x - (8/QI8_1)*Q_ds.y); } return sum; } -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_q4_1( +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q4_1( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { const block_q4_1 * K_q4_1 = (const block_q4_1 *) K_c; GGML_UNUSED(Q_v); - T sum = 0.0f; + float sum = 0.0f; #pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += nthreads) { + const int k_KQ = k_KQ_0 + (nthreads == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads); const int ib = k_KQ / QI8_1; const int iqs4 = k_KQ % QI4_1; const int shift = k_KQ & (QI8_1/2); - const int v = (get_int_b4(K_q4_1[ib].qs, iqs4) >> shift) & 0x0F0F0F0F; - const int u = Q_q8[k_KQ_0/warp_size]; + int v; + ggml_cuda_memcpy_1(&v, K_q4_1[ib].qs + sizeof(int)*iqs4); + v = (v >> shift) & 0x0F0F0F0F; + const int u = Q_q8[k_KQ_0/nthreads]; const int sumi = ggml_cuda_dp4a(v, u, 0); -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - const half2 * Q_ds = (const half2 *) Q_ds_v; - - const half2 d4d8_m4s8 = K_q4_1[ib].dm * Q_ds[k_KQ_0/warp_size]; - const half2 sumid4d8_m4s8scaled = d4d8_m4s8 * make_half2(sumi, 1.0f/QI8_1); - sum += (T) (__low2half(sumid4d8_m4s8scaled) + __high2half(sumid4d8_m4s8scaled)); - } else -#endif // FP16_AVAILABLE - { - const float2 * Q_ds = (const float2 *) Q_ds_v; - - const float sumid4d8 = __low2float(K_q4_1[ib].dm)*Q_ds[k_KQ_0/warp_size].x * sumi; - const float m4s8scaled = __high2float(K_q4_1[ib].dm)*Q_ds[k_KQ_0/warp_size].y / QI8_1; + const float2 K_dm = __half22float2(K_q4_1[ib].dm); + const float2 Q_ds = ((const float2 *) Q_ds_v)[k_KQ_0/nthreads]; - sum += (T) (sumid4d8 + m4s8scaled); - } + sum += K_dm.x*Q_ds.x*sumi + K_dm.y*Q_ds.y/QI8_1; } return sum; } -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_q5_0( +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q5_0( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { const block_q5_0 * K_q5_0 = (const block_q5_0 *) K_c; GGML_UNUSED(Q_v); - T sum = 0.0f; + float sum = 0.0f; #pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += nthreads) { + const int k_KQ = k_KQ_0 + (nthreads == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads); const int ib = k_KQ / QI8_1; const int iqs4 = k_KQ % QI5_0; const int iqs8 = k_KQ % QI8_1; const int shift = k_KQ & (QI8_1/2); - int v = (get_int_b2(K_q5_0[ib].qs, iqs4) >> shift) & 0x0F0F0F0F; - const int vh = get_int_b2(K_q5_0[ib].qh, 0) >> (iqs8 * QI5_0); - v |= (vh << 4) & 0x00000010; // 0 -> 4 - v |= (vh << 11) & 0x00001000; // 1 -> 12 - v |= (vh << 18) & 0x00100000; // 2 -> 20 - v |= (vh << 25) & 0x10000000; // 3 -> 28 + int v; + ggml_cuda_memcpy_1(&v, K_q5_0[ib].qs + sizeof(int)*iqs4); + v = (v >> shift) & 0x0F0F0F0F; - const int u = Q_q8[k_KQ_0/warp_size]; + { + int vh; + ggml_cuda_memcpy_1(&vh, K_q5_0[ib].qh); + vh >>= iqs8 * QI5_0; - const int sumi = ggml_cuda_dp4a(v, u, 0); + v |= (vh << 4) & 0x00000010; // 0 -> 4 + v |= (vh << 11) & 0x00001000; // 1 -> 12 + v |= (vh << 18) & 0x00100000; // 2 -> 20 + v |= (vh << 25) & 0x10000000; // 3 -> 28 + } -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - const half2 * Q_ds = (const half2 *) Q_ds_v; + const int u = Q_q8[k_KQ_0/nthreads]; - const half2 sum2 = __half2half2(K_q5_0[ib].d) * Q_ds[k_KQ_0/warp_size]; - sum += (T) (((half) sumi)*__low2half(sum2) - __high2half(sum2)*__float2half(2.0f)) /* *16/QI8_1 == 2 */; - } else -#endif // FP16_AVAILABLE - { - const float2 * Q_ds = (const float2 *) Q_ds_v; + const int sumi = ggml_cuda_dp4a(v, u, 0); - sum += (T) (__half2float(K_q5_0[ib].d) * (sumi*Q_ds[k_KQ_0/warp_size].x - (16/QI8_1)*Q_ds[k_KQ_0/warp_size].y)); - } + const float2 Q_ds = ((const float2 *) Q_ds_v)[k_KQ_0/nthreads]; + + sum += __half2float(K_q5_0[ib].d) * (sumi*Q_ds.x - (16/QI8_1)*Q_ds.y); } return sum; } -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_q5_1( +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q5_1( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { const block_q5_1 * K_q5_1 = (const block_q5_1 *) K_c; GGML_UNUSED(Q_v); - T sum = 0.0f; + float sum = 0.0f; #pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += nthreads) { + const int k_KQ = k_KQ_0 + (nthreads == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads); const int ib = k_KQ / QI8_1; const int iqs4 = k_KQ % QI5_1; const int iqs8 = k_KQ % QI8_1; const int shift = k_KQ & (QI8_1/2); - int v = (get_int_b2(K_q5_1[ib].qs, iqs4) >> shift) & 0x0F0F0F0F; - const int vh = get_int_b2(K_q5_1[ib].qh, 0) >> (iqs8 * QI5_1); - v |= (vh << 4) & 0x00000010; // 0 -> 4 - v |= (vh << 11) & 0x00001000; // 1 -> 12 - v |= (vh << 18) & 0x00100000; // 2 -> 20 - v |= (vh << 25) & 0x10000000; // 3 -> 28 + int v; + ggml_cuda_memcpy_1(&v, K_q5_1[ib].qs + sizeof(int)*iqs4); + v = (v >> shift) & 0x0F0F0F0F; - const int u = Q_q8[k_KQ_0/warp_size]; + { + int vh; + ggml_cuda_memcpy_1(&vh, K_q5_1[ib].qh); + vh >>= iqs8 * QI5_0; - const int sumi = ggml_cuda_dp4a(v, u, 0); + v |= (vh << 4) & 0x00000010; // 0 -> 4 + v |= (vh << 11) & 0x00001000; // 1 -> 12 + v |= (vh << 18) & 0x00100000; // 2 -> 20 + v |= (vh << 25) & 0x10000000; // 3 -> 28 + } -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - const half2 * Q_ds = (const half2 *) Q_ds_v; + const int u = Q_q8[k_KQ_0/nthreads]; - const half2 d5d8_m5s8 = K_q5_1[ib].dm * Q_ds[k_KQ_0/warp_size]; - const half2 sumid5d8_m5s8scaled = d5d8_m5s8 * make_half2(sumi, 1.0f/QI8_1); - sum += (T) (__low2half(sumid5d8_m5s8scaled) + __high2half(sumid5d8_m5s8scaled)); - } else -#endif // FP16_AVAILABLE - { - const float2 * Q_ds = (const float2 *) Q_ds_v; + const int sumi = ggml_cuda_dp4a(v, u, 0); - const float sumid5d8 = __low2float(K_q5_1[ib].dm)*Q_ds[k_KQ_0/warp_size].x * sumi; - const float m5s8scaled = __high2float(K_q5_1[ib].dm)*Q_ds[k_KQ_0/warp_size].y / QI8_1; + const float2 K_dm = __half22float2(K_q5_1[ib].dm); + const float2 Q_ds = ((const float2 *) Q_ds_v)[k_KQ_0/nthreads]; - sum += (T) (sumid5d8 + m5s8scaled); - } + sum += K_dm.x*Q_ds.x*sumi + K_dm.y*Q_ds.y/QI8_1; } return sum; } -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_q8_0( +template +static __device__ __forceinline__ float vec_dot_fattn_vec_KQ_q8_0( const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8, const void * __restrict__ Q_ds_v) { const block_q8_0 * K_q8_0 = (const block_q8_0 *) K_c; GGML_UNUSED(Q_v); - T sum = 0.0f; + float sum = 0.0f; #pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + for (int k_KQ_0 = 0; k_KQ_0 < int(D/sizeof(int)); k_KQ_0 += nthreads) { + const int k_KQ = k_KQ_0 + (nthreads == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads); const int ib = k_KQ / QI8_0; const int iqs = k_KQ % QI8_0; - const int v = get_int_b2(K_q8_0[ib].qs, iqs); - - T Q_d; - if (std::is_same::value) { - const half2 * Q_ds = (const half2 *) Q_ds_v; - Q_d = __low2half(Q_ds[k_KQ_0/warp_size]); - } else { - const float2 * Q_ds = (const float2 *) Q_ds_v; - Q_d = Q_ds[k_KQ_0/warp_size].x; - } - - sum += vec_dot_q8_0_q8_1_impl(&v, &Q_q8[k_KQ_0/warp_size], K_q8_0[ib].d, Q_d); - } - - return sum; -} - -template -static __device__ __forceinline__ T vec_dot_fattn_vec_KQ_f16( - const char * __restrict__ K_c, const void * __restrict__ Q_v, const int * __restrict__ Q_q8 , const void * __restrict__ Q_ds_v) { - - const half2 * K_h2 = (const half2 *) K_c; - GGML_UNUSED(Q_q8); - GGML_UNUSED(Q_ds_v); - -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - const half2 * Q_h2 = (const half2 *) Q_v; - - half2 sum2 = make_half2(0.0f, 0.0f); - -#pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; - - const half2 K_ik = K_h2[k_KQ]; - sum2 += K_ik * Q_h2[k_KQ_0/warp_size]; - } - - return __low2half(sum2) + __high2half(sum2); - } -#endif // FP16_AVAILABLE - - const float2 * Q_f2 = (const float2 *) Q_v; - - float sum = 0.0f; + int v; + ggml_cuda_memcpy_1(&v, K_q8_0[ib].qs + 4*iqs); -#pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += warp_size) { - const int k_KQ = k_KQ_0 + threadIdx.x; + const float2 * Q_ds = (const float2 *) Q_ds_v; + const float Q_d = Q_ds[k_KQ_0/nthreads].x; - const half2 K_ik = K_h2[k_KQ]; - sum += __low2float(K_ik) * Q_f2[k_KQ_0/warp_size].x; - sum += __high2float(K_ik) * Q_f2[k_KQ_0/warp_size].y; + sum += vec_dot_q8_0_q8_1_impl(&v, &Q_q8[k_KQ_0/nthreads], K_q8_0[ib].d, Q_d); } return sum; } -template +template static __device__ __forceinline__ void quantize_q8_1_to_shared( const float * __restrict__ x, const float scale, int * __restrict__ yq32, void * __restrict__ yds) { float vals[sizeof(int)] = {0.0f}; #pragma unroll for (int l = 0; l < int(sizeof(int)); ++l) { - vals[l] = scale * x[4*threadIdx.x + l]; + vals[l] = (ni == WARP_SIZE || threadIdx.x < ni) ? scale * x[4*threadIdx.x + l] : 0.0f; } float amax = fabsf(vals[0]); @@ -346,7 +284,7 @@ static __device__ __forceinline__ void q } yq32[threadIdx.x] = q32; - if (threadIdx.x % QI8_1 == 0) { + if (threadIdx.x % QI8_1 == 0 && (ni == WARP_SIZE || threadIdx.x < ni)) { if (std::is_same::value) { ((half2 *) yds)[threadIdx.x/QI8_1] = make_half2(d, sum); } else { @@ -355,173 +293,335 @@ static __device__ __forceinline__ void q } } -typedef half (*dequantize_1_f16_t)(const void *, const int64_t); -typedef float (*dequantize_1_f32_t)(const void *, const int64_t); +typedef void (*dequantize_V_t)(const void *, void *, const int64_t); + +template +static __device__ __forceinline__ void dequantize_V_f16(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { + if constexpr (std::is_same_v) { + ggml_cuda_memcpy_1(dst, (const half *) vx + i0); + } else if constexpr (std::is_same_v) { + static_assert(ne % 2 == 0, "bad ne"); + half2 tmp[ne/2]; + ggml_cuda_memcpy_1(tmp, (const half *) vx + i0); + float2 * dst_f2 = (float2 *) dst; +#pragma unroll + for (int l = 0; l < ne/2; ++l) { + dst_f2[l] = __half22float2(tmp[l]); + } + } else { + static_assert(std::is_same_v, "unsupported type"); + } +} -template -static __device__ __forceinline__ T dequantize_1_q4_0(const void * __restrict__ vx, const int64_t i) { +template +static __device__ __forceinline__ void dequantize_V_q4_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { const block_q4_0 * x = (const block_q4_0 *) vx; - const int64_t ib = i / QK4_0; - const int iqs = i % (QK4_0/2); - const int shift = (i % QK4_0) / (QK4_0/2); - - const T d = x[ib].d; - const int q0 = x[ib].qs[iqs]; - const int q = ((q0 >> (4*shift)) & 0x0F) - 8; + const int64_t ib = i0 / QK4_0; + const int iqs = i0 % (QK4_0/2); + const int shift = (i0 % QK4_0) / (QK4_0/2); + + int q; + static_assert(ne == 2 || ne == 4, "bad ne"); + ggml_cuda_memcpy_1(&q, x[ib].qs + iqs); + q >>= 4*shift; + q &= 0x0F0F0F0F; + q = __vsubss4(q, 0x08080808); + + const int8_t * q8 = (const int8_t *) &q; #ifdef FP16_AVAILABLE - if (std::is_same::value) { - return ((half) d)*((half) q); - } + if constexpr (std::is_same_v) { + const half2 d = __half2half2(x[ib].d); + +#pragma unroll + for (int l0 = 0; l0 < ne; l0 += 2) { + ((half2 *) dst)[l0/2] = d * make_half2(q8[l0 + 0], q8[l0 + 1]); + } + } else #endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + const float d = x[ib].d; - return ((float) d)*((float) q); +#pragma unroll + for (int l = 0; l < ne; ++l) { + ((float *) dst)[l] = d * q8[l]; + } + } else { + static_assert(std::is_same_v, "bad type"); + } } -template -static __device__ __forceinline__ T dequantize_1_q4_1(const void * __restrict__ vx, const int64_t i) { +template +static __device__ __forceinline__ void dequantize_V_q4_1(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { const block_q4_1 * x = (const block_q4_1 *) vx; - const int64_t ib = i / QK4_1; - const int iqs = i % (QK4_1/2); - const int shift = (i % QK4_1) / (QK4_1/2); - - const half2 dm = x[ib].dm; - const int q0 = x[ib].qs[iqs]; - const int q = ((q0 >> (4*shift)) & 0x0F); + const int64_t ib = i0 / QK4_1; + const int iqs = i0 % (QK4_1/2); + const int shift = (i0 % QK4_1) / (QK4_1/2); + + int q; + static_assert(ne == 2 || ne == 4, "bad ne"); + ggml_cuda_memcpy_1(&q, x[ib].qs + iqs); + q >>= 4*shift; + q &= 0x0F0F0F0F; + + const int8_t * q8 = (const int8_t *) &q; #ifdef FP16_AVAILABLE - if (std::is_same::value) { - return __low2half(dm)*((half) q) + __high2half(dm); - } + if constexpr (std::is_same_v) { + const half2 dm = x[ib].dm; + const half2 d = __half2half2( __low2half(dm)); + const half2 m = __half2half2(__high2half(dm)); + +#pragma unroll + for (int l0 = 0; l0 < ne; l0 += 2) { + ((half2 *) dst)[l0/2] = d * make_half2(q8[l0 + 0], q8[l0 + 1]) + m; + } + } else #endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + const float2 dm = __half22float2(x[ib].dm); - return __low2float(dm)*((float) q) + __high2float(dm); +#pragma unroll + for (int l = 0; l < ne; ++l) { + ((float *) dst)[l] = dm.x * q8[l] + dm.y; + } + } else { + static_assert(std::is_same_v, "bad type"); + } } -template -static __device__ __forceinline__ T dequantize_1_q5_0(const void * __restrict__ vx, const int64_t i) { +template +static __device__ __forceinline__ void dequantize_V_q5_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { const block_q5_0 * x = (const block_q5_0 *) vx; - const int64_t ib = i / QK5_0; - const int idq = i % QK5_0; - const int iqs = i % (QK5_0/2); - const int shift = (i % QK5_0) / (QK5_0/2); - - const T d = x[ib].d; - const int ql0 = x[ib].qs[iqs]; - const int qh0 = get_int_b2(x[ib].qh, 0); - const int ql = ((ql0 >> (4*shift)) & 0x0F); - const int qh = ((qh0 >> idq) << 4) & 0x10; - const int q = (ql | qh) - 16; + const int64_t ib = i0 / QK5_0; + const int idq = i0 % QK5_0; + const int iqs = i0 % (QK5_0/2); + const int shift = (i0 % QK5_0) / (QK5_0/2); + + int q; + static_assert(ne == 2 || ne == 4, "bad ne"); + ggml_cuda_memcpy_1(&q, x[ib].qs + iqs); + q >>= 4*shift; + q &= 0x0F0F0F0F; -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - return ((half) d)*((half) q); + { + int qh; + ggml_cuda_memcpy_1(&qh, x[ib].qh); +#pragma unroll + for (int l = 0; l < ne; ++l) { + q |= ((qh >> (idq + l)) & 0x00000001) << (8*l + 4); + } } + + q = __vsubss4(q, 0x10101010); + + const int8_t * q8 = (const int8_t *) &q; + +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + const half2 d = __half2half2(x[ib].d); + +#pragma unroll + for (int l0 = 0; l0 < ne; l0 += 2) { + ((half2 *) dst)[l0/2] = d * make_half2(q8[l0 + 0], q8[l0 + 1]); + } + } else #endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + const float d = x[ib].d; - return ((float) d)*((float) q); +#pragma unroll + for (int l = 0; l < ne; ++l) { + ((float *) dst)[l] = d * q8[l]; + } + } else { + static_assert(std::is_same_v, "bad type"); + } } -template -static __device__ __forceinline__ T dequantize_1_q5_1(const void * __restrict__ vx, const int64_t i) { +template +static __device__ __forceinline__ void dequantize_V_q5_1(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { const block_q5_1 * x = (const block_q5_1 *) vx; - const int64_t ib = i / QK5_1; - const int idq = i % QK5_1; - const int iqs = i % (QK5_1/2); - const int shift = (i % QK5_1) / (QK5_1/2); - - const half2 dm = x[ib].dm; - const int ql0 = x[ib].qs[iqs]; - const int qh0 = get_int_b4(x[ib].qh, 0); - const int ql = ((ql0 >> (4*shift)) & 0x0F); - const int qh = ((qh0 >> idq) << 4) & 0x10; - const int q = (ql | qh); + const int64_t ib = i0 / QK5_1; + const int idq = i0 % QK5_1; + const int iqs = i0 % (QK5_1/2); + const int shift = (i0 % QK5_1) / (QK5_1/2); + + int q; + static_assert(ne == 2 || ne == 4, "bad ne"); + ggml_cuda_memcpy_1(&q, x[ib].qs + iqs); + q >>= 4*shift; + q &= 0x0F0F0F0F; -#ifdef FP16_AVAILABLE - if (std::is_same::value) { - return __low2half(dm)*((half) q) + __high2half(dm); + { + int qh; + ggml_cuda_memcpy_1(&qh, x[ib].qh); +#pragma unroll + for (int l = 0; l < ne; ++l) { + q |= ((qh >> (idq + l)) & 0x00000001) << (8*l + 4); + } } + + const int8_t * q8 = (const int8_t *) &q; + +#ifdef FP16_AVAILABLE + if constexpr (std::is_same_v) { + const half2 dm = x[ib].dm; + const half2 d = __half2half2( __low2half(dm)); + const half2 m = __half2half2(__high2half(dm)); + +#pragma unroll + for (int l0 = 0; l0 < ne; l0 += 2) { + ((half2 *) dst)[l0/2] = d * make_half2(q8[l0 + 0], q8[l0 + 1]) + m; + } + } else #endif // FP16_AVAILABLE + if constexpr (std::is_same_v) { + const float2 dm = __half22float2(x[ib].dm); - return __low2float(dm)*((float) q) + __high2float(dm); +#pragma unroll + for (int l = 0; l < ne; ++l) { + ((float *) dst)[l] = dm.x * q8[l] + dm.y; + } + } else { + static_assert(std::is_same_v, "bad type"); + } } -template -static __device__ __forceinline__ T dequantize_1_q8_0(const void * __restrict__ vx, const int64_t i) { +template +static __device__ __forceinline__ void dequantize_V_q8_0(const void * __restrict__ vx, void * __restrict__ dst, const int64_t i0) { const block_q8_0 * x = (const block_q8_0 *) vx; - const int64_t ib = i / QK8_0; - const int iqs = i % QK8_0; + const int64_t ib = i0 / QK8_0; + const int iqs = i0 % QK8_0; - const T d = x[ib].d; - const int q = x[ib].qs[iqs]; + static_assert(ne % 2 == 0, "bad ne"); + int8_t qs[ne]; + ggml_cuda_memcpy_1(qs, x[ib].qs + iqs); #ifdef FP16_AVAILABLE - if (std::is_same::value) { - return ((half) d)*((half) q); - } + if constexpr (std::is_same::value) { + const half2 d = __half2half2(x[ib].d); + +#pragma unroll + for (int l0 = 0; l0 < ne; l0 += 2) { + ((half2 *) dst)[l0/2] = d * make_half2(qs[l0 + 0], qs[l0 + 1]); + } + } else #endif // FP16_AVAILABLE + if constexpr (std::is_same::value) { + const float d = x[ib].d; - return ((float) d)*((float) q); +#pragma unroll + for (int l = 0; l < ne; ++l) { + ((float *) dst)[l] = d * qs[l]; + } + } else { + static_assert(std::is_same_v, "unsupported type"); + } } -template -static __device__ __forceinline__ T dequantize_1_f16(const void * __restrict__ vx, const int64_t i) { - const half * x = (const half *) vx; - - return x[i]; -} - -template -constexpr __device__ vec_dot_KQ_f16_t get_vec_dot_KQ_f16(ggml_type type_K) { - return type_K == GGML_TYPE_Q4_0 ? vec_dot_fattn_vec_KQ_q4_0 : - type_K == GGML_TYPE_Q4_1 ? vec_dot_fattn_vec_KQ_q4_1 : - type_K == GGML_TYPE_Q5_0 ? vec_dot_fattn_vec_KQ_q5_0 : - type_K == GGML_TYPE_Q5_1 ? vec_dot_fattn_vec_KQ_q5_1 : - type_K == GGML_TYPE_Q8_0 ? vec_dot_fattn_vec_KQ_q8_0 : - type_K == GGML_TYPE_F16 ? vec_dot_fattn_vec_KQ_f16 : - nullptr; -} - -template -constexpr __device__ vec_dot_KQ_f32_t get_vec_dot_KQ_f32(ggml_type type_K) { - return type_K == GGML_TYPE_Q4_0 ? vec_dot_fattn_vec_KQ_q4_0 : - type_K == GGML_TYPE_Q4_1 ? vec_dot_fattn_vec_KQ_q4_1 : - type_K == GGML_TYPE_Q5_0 ? vec_dot_fattn_vec_KQ_q5_0 : - type_K == GGML_TYPE_Q5_1 ? vec_dot_fattn_vec_KQ_q5_1 : - type_K == GGML_TYPE_Q8_0 ? vec_dot_fattn_vec_KQ_q8_0 : - type_K == GGML_TYPE_F16 ? vec_dot_fattn_vec_KQ_f16 : - nullptr; -} - -constexpr __device__ dequantize_1_f16_t get_dequantize_1_f16(ggml_type type_V) { - return type_V == GGML_TYPE_Q4_0 ? dequantize_1_q4_0 : - type_V == GGML_TYPE_Q4_1 ? dequantize_1_q4_1 : - type_V == GGML_TYPE_Q5_0 ? dequantize_1_q5_0 : - type_V == GGML_TYPE_Q5_1 ? dequantize_1_q5_1 : - type_V == GGML_TYPE_Q8_0 ? dequantize_1_q8_0 : - type_V == GGML_TYPE_F16 ? dequantize_1_f16 : - nullptr; -} - -constexpr __device__ dequantize_1_f32_t get_dequantize_1_f32(ggml_type type_V) { - return type_V == GGML_TYPE_Q4_0 ? dequantize_1_q4_0 : - type_V == GGML_TYPE_Q4_1 ? dequantize_1_q4_1 : - type_V == GGML_TYPE_Q5_0 ? dequantize_1_q5_0 : - type_V == GGML_TYPE_Q5_1 ? dequantize_1_q5_1 : - type_V == GGML_TYPE_Q8_0 ? dequantize_1_q8_0 : - type_V == GGML_TYPE_F16 ? dequantize_1_f16 : - nullptr; +template +constexpr __device__ vec_dot_KQ_t get_vec_dot_KQ() { + if constexpr (type_K == GGML_TYPE_F16) { + return vec_dot_fattn_vec_KQ_f16; + } else if constexpr (type_K == GGML_TYPE_Q4_0) { + return vec_dot_fattn_vec_KQ_q4_0; + } else if constexpr (type_K == GGML_TYPE_Q4_1) { + return vec_dot_fattn_vec_KQ_q4_1; + } else if constexpr (type_K == GGML_TYPE_Q5_0) { + return vec_dot_fattn_vec_KQ_q5_0; + } else if constexpr (type_K == GGML_TYPE_Q5_1) { + return vec_dot_fattn_vec_KQ_q5_1; + } else if constexpr (type_K == GGML_TYPE_Q8_0) { + return vec_dot_fattn_vec_KQ_q8_0; + } else { + static_assert(type_K == -1, "bad type"); + return nullptr; + } +} + +template +constexpr __device__ dequantize_V_t get_dequantize_V() { + if constexpr (type_V == GGML_TYPE_F16) { + return dequantize_V_f16; + } else if constexpr (type_V == GGML_TYPE_Q4_0) { + return dequantize_V_q4_0; + } else if constexpr (type_V == GGML_TYPE_Q4_1) { + return dequantize_V_q4_1; + } else if constexpr (type_V == GGML_TYPE_Q5_0) { + return dequantize_V_q5_0; + } else if constexpr (type_V == GGML_TYPE_Q5_1) { + return dequantize_V_q5_1; + } else if constexpr (type_V == GGML_TYPE_Q8_0) { + return dequantize_V_q8_0; + } else { + static_assert(type_V == -1, "bad type"); + return nullptr; + } +} + +template +__launch_bounds__(FATTN_KQ_STRIDE/2, 1) +static __global__ void flash_attn_mask_to_KV_max( + const half2 * __restrict__ mask, int * __restrict__ KV_max, const int ne30, const int s31, const int s33) { + const int ne31 = gridDim.x; + const int tid = threadIdx.x; + const int sequence = blockIdx.y; + const int jt = blockIdx.x; + + mask += sequence*s33 + jt*ncols1*s31; + + __shared__ int buf_iw[WARP_SIZE]; + if (tid < WARP_SIZE) { + buf_iw[tid] = 1; + } + __syncthreads(); + + int KV_max_sj = (ne30 - 1) * FATTN_KQ_STRIDE; + for (; KV_max_sj >= 0; KV_max_sj -= FATTN_KQ_STRIDE) { + int all_inf = 1; + +#pragma unroll + for (int j = 0; j < ncols1; ++j) { + const float2 tmp = __half22float2(mask[j*s31 + KV_max_sj/2 + tid]); + all_inf = all_inf && int(isinf(tmp.x)) && int(isinf(tmp.y)); + } + + all_inf = warp_reduce_all(all_inf); + if (tid % WARP_SIZE == 0) { + buf_iw[tid / WARP_SIZE] = all_inf; + } + __syncthreads(); + all_inf = buf_iw[tid % WARP_SIZE]; + __syncthreads(); + all_inf = warp_reduce_all(all_inf); + + if (!all_inf) { + break; + } + } + + // If the break in the loop was not triggered, KV_max_sj is now -FATTN_KQ_STRIDE. + // If the break was triggered it's the lower edge of the tile with the first non-masked values. + // In either case, walk back the decrementation by FATTN_KQ_STRIDE. + KV_max_sj += FATTN_KQ_STRIDE; + + if (threadIdx.x != 0) { + return; + } + + KV_max[sequence*ne31 + jt] = KV_max_sj; } template // D == head size __launch_bounds__(D, 1) static __global__ void flash_attn_stream_k_fixup( - float * __restrict__ dst, const float2 * __restrict__ dst_fixup, const int ne01, const int ne02, const int ne11) { + float * __restrict__ dst, const float2 * __restrict__ dst_fixup, const int ne01, const int ne02, const int ne03, const int ne11) { constexpr int ncols = ncols1*ncols2; const int bidx0 = blockIdx.x; @@ -535,8 +635,8 @@ static __global__ void flash_attn_stream const int iter_k = ne11 / FATTN_KQ_STRIDE; const int iter_j = (ne01 + (ncols1 - 1)) / ncols1; - const int kbc0 = (bidx0 + 0)*iter_k*iter_j*(ne02/ncols2) / gridDim.x; - const int kbc0_stop = (bidx0 + 1)*iter_k*iter_j*(ne02/ncols2) / gridDim.x; + const int kbc0 = (bidx0 + 0)*(iter_k*iter_j*(ne02/ncols2)*ne03) / gridDim.x; + const int kbc0_stop = (bidx0 + 1)*(iter_k*iter_j*(ne02/ncols2)*ne03) / gridDim.x; const bool did_not_have_any_data = kbc0 == kbc0_stop; const bool wrote_beginning_of_tile = kbc0 % iter_k == 0; @@ -545,14 +645,15 @@ static __global__ void flash_attn_stream return; } - const int channel = kbc0 / (iter_k*iter_j); - const int jt = (kbc0 - channel*iter_k*iter_j) / iter_k; + const int sequence = kbc0 / (iter_k*iter_j*(ne02/ncols2)); + const int head = (kbc0 - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); + const int jt = (kbc0 - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*head) / iter_k; // j index of current tile. if (jt*ncols1 + j >= ne01) { return; } - dst += jt*ne02*(ncols1*D) + channel*(ncols2*D) + (j*ne02 + c)*D + tid; + dst += sequence*ne02*ne01*D + jt*ne02*(ncols1*D) + head*(ncols2*D) + (j*ne02 + c)*D + tid; // Load the partial result that needs a fixup: float dst_val = 0.0f; @@ -571,7 +672,7 @@ static __global__ void flash_attn_stream int bidx = bidx0 - 1; int kbc_stop = kbc0; while(true) { - const int kbc = bidx*iter_k*iter_j*(ne02/ncols2) / gridDim.x; + const int kbc = bidx*(iter_k*iter_j*(ne02/ncols2)*ne03) / gridDim.x; if (kbc == kbc_stop) { // Did not have any data. bidx--; kbc_stop = kbc; @@ -609,24 +710,37 @@ static __global__ void flash_attn_stream } template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) __launch_bounds__(D, 1) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) static __global__ void flash_attn_combine_results( const float * __restrict__ VKQ_parts, const float2 * __restrict__ VKQ_meta, float * __restrict__ dst, const int parallel_blocks) { - VKQ_parts += parallel_blocks*D * gridDim.z*blockIdx.x; - VKQ_meta += parallel_blocks * gridDim.z*blockIdx.x; - dst += D * gridDim.z*blockIdx.x; + // Dimension 0: threadIdx.x + // Dimension 1: blockIdx.x + // Dimension 2: blockIdx.y + // Dimension 3: blockIdx.z + // Memory layout is permuted with [0, 2, 1, 3] + + const int ne01 = gridDim.x; + const int ne02 = gridDim.y; + + const int col = blockIdx.x; + const int head = blockIdx.y; + const int sequence = blockIdx.z; + + const int j_dst_unrolled = (sequence*ne01 + col)*ne02 + head; + + VKQ_parts += j_dst_unrolled * parallel_blocks*D; + VKQ_meta += j_dst_unrolled * parallel_blocks; + dst += j_dst_unrolled * D; const int tid = threadIdx.x; __builtin_assume(tid < D); extern __shared__ float2 meta[]; for (int i = tid; i < 2*parallel_blocks; i += D) { - ((float *) meta)[i] = ((const float *)VKQ_meta) [blockIdx.z*(2*parallel_blocks) + i]; + ((float *) meta)[i] = ((const float *)VKQ_meta) [i]; } __syncthreads(); @@ -639,38 +753,13 @@ static __global__ void flash_attn_combin float VKQ_numerator = 0.0f; float VKQ_denominator = 0.0f; for (int l = 0; l < parallel_blocks; ++l) { - const float diff = meta[l].x - kqmax; - float KQ_max_scale = expf(diff); - const uint32_t ftz_mask = 0xFFFFFFFF * (diff > SOFTMAX_FTZ_THRESHOLD); - *((uint32_t *) &KQ_max_scale) &= ftz_mask; + const float KQ_max_scale = expf(meta[l].x - kqmax); - VKQ_numerator += KQ_max_scale * VKQ_parts[l*gridDim.z*D + blockIdx.z*D + tid]; + VKQ_numerator += KQ_max_scale * VKQ_parts[l*D + tid]; VKQ_denominator += KQ_max_scale * meta[l].y; } - dst[blockIdx.z*D + tid] = VKQ_numerator / VKQ_denominator; -} - -[[noreturn]] -static void on_no_fattn_vec_case(const int D) { - if (D == 64) { - fprintf(stderr, "Unsupported KV type combination for head_size 64.\n"); - fprintf(stderr, "By default only f16 KV cache is supported.\n"); - fprintf(stderr, "Compile with GGML_CUDA_FA_ALL_QUANTS for V cache quantization support.\n"); - GGML_ABORT("fatal error"); - } else if (D == 128) { - fprintf(stderr, "Unsupported KV type combination for head_size 128.\n"); - fprintf(stderr, "Supported combinations:\n"); - fprintf(stderr, " - K == q4_0, V == q4_0, 4.50 BPV\n"); - fprintf(stderr, " - K == q8_0, V == q8_0, 8.50 BPV\n"); - fprintf(stderr, " - K == f16, V == f16, 16.00 BPV\n"); - fprintf(stderr, "Compile with GGML_CUDA_FA_ALL_QUANTS for all combinations of q4_0, q4_1, q5_0, q5_1, q8_0, and f16.\n"); - GGML_ABORT("fatal error"); - } else { - fprintf(stderr, "Unsupported KV type combination for head_size %d.\n", D); - fprintf(stderr, "Only f16 is supported.\n"); - GGML_ABORT("fatal error"); - } + dst[tid] = VKQ_numerator / VKQ_denominator; } template @@ -688,7 +777,8 @@ void launch_fattn( GGML_ASSERT(V || is_mla); - const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; ggml_tensor * KQV = dst; @@ -705,8 +795,6 @@ void launch_fattn( GGML_ASSERT(K->ne[1] % FATTN_KQ_STRIDE == 0 && "Incorrect KV cache padding."); - GGML_ASSERT(Q->ne[3] == 1); - ggml_cuda_pool & pool = ctx.pool(); cudaStream_t main_stream = ctx.stream(); const int id = ggml_cuda_get_device(); @@ -715,6 +803,7 @@ void launch_fattn( ggml_cuda_pool_alloc K_f16(pool); ggml_cuda_pool_alloc V_f16(pool); + ggml_cuda_pool_alloc KV_max(pool); ggml_cuda_pool_alloc dst_tmp(pool); ggml_cuda_pool_alloc dst_tmp_meta(pool); @@ -729,43 +818,86 @@ void launch_fattn( size_t nb23 = V ? V->nb[3] : nb13; if (need_f16_K && K->type != GGML_TYPE_F16) { - GGML_ASSERT(ggml_is_contiguously_allocated(K)); - K_f16.alloc(ggml_nelements(K)); - to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(K->type); - to_fp16(K_data, K_f16.ptr, ggml_nelements(K), main_stream); - K_data = (char *) K_f16.ptr; - const size_t bs = ggml_blck_size(K->type); const size_t ts = ggml_type_size(K->type); - nb11 = nb11*bs*sizeof(half)/ts; - nb12 = nb12*bs*sizeof(half)/ts; - nb13 = nb13*bs*sizeof(half)/ts; + K_f16.alloc(ggml_nelements(K)); + if (ggml_is_contiguously_allocated(K)) { + to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(K->type); + to_fp16(K_data, K_f16.ptr, ggml_nelements(K), main_stream); + + nb11 = nb11*bs*sizeof(half)/ts; + nb12 = nb12*bs*sizeof(half)/ts; + nb13 = nb13*bs*sizeof(half)/ts; + } else { + GGML_ASSERT(K->nb[0] == ts); + to_fp16_nc_cuda_t to_fp16 = ggml_get_to_fp16_nc_cuda(K->type); + const int64_t s01 = nb11 / ts; + const int64_t s02 = nb12 / ts; + const int64_t s03 = nb13 / ts; + to_fp16(K_data, K_f16.ptr, K->ne[0], K->ne[1], K->ne[2], K->ne[3], s01, s02, s03, main_stream); + + nb11 = K->ne[0] * sizeof(half); + nb12 = K->ne[1] * nb11; + nb13 = K->ne[2] * nb12; + } + K_data = (char *) K_f16.ptr; } if (V && need_f16_V && V->type != GGML_TYPE_F16) { - GGML_ASSERT(ggml_is_contiguously_allocated(V)); - V_f16.alloc(ggml_nelements(V)); - to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(V->type); - to_fp16(V_data, V_f16.ptr, ggml_nelements(V), main_stream); - V_data = (char *) V_f16.ptr; - const size_t bs = ggml_blck_size(V->type); const size_t ts = ggml_type_size(V->type); - nb21 = nb21*bs*sizeof(half)/ts; - nb22 = nb22*bs*sizeof(half)/ts; - nb23 = nb23*bs*sizeof(half)/ts; + V_f16.alloc(ggml_nelements(V)); + if (ggml_is_contiguously_allocated(V)) { + to_fp16_cuda_t to_fp16 = ggml_get_to_fp16_cuda(V->type); + to_fp16(V_data, V_f16.ptr, ggml_nelements(V), main_stream); + V_data = (char *) V_f16.ptr; + + nb21 = nb21*bs*sizeof(half)/ts; + nb22 = nb22*bs*sizeof(half)/ts; + nb23 = nb23*bs*sizeof(half)/ts; + } else { + GGML_ASSERT(V->nb[0] == ts); + to_fp16_nc_cuda_t to_fp16 = ggml_get_to_fp16_nc_cuda(V->type); + const int64_t s01 = nb21 / ts; + const int64_t s02 = nb22 / ts; + const int64_t s03 = nb23 / ts; + to_fp16(V_data, V_f16.ptr, V->ne[0], V->ne[1], V->ne[2], V->ne[3], s01, s02, s03, main_stream); + + nb21 = V->ne[0] * sizeof(half); + nb22 = V->ne[1] * nb21; + nb23 = V->ne[2] * nb22; + } + V_data = (char *) V_f16.ptr; } - int parallel_blocks = 1; - const int ntiles_x = ((Q->ne[1] + ncols1 - 1) / ncols1); const int ntiles_total = ntiles_x * (Q->ne[2] / ncols2) * Q->ne[3]; + // Optional optimization where the mask is scanned to determine whether part of the calculation can be skipped. + // Only worth the overhead if there is at lease one FATTN_KQ_STRIDE x FATTN_KQ_STRIDE square to be skipped or + // multiple sequences of possibly different lengths. + if (mask && (Q->ne[1] >= 1024 || Q->ne[3] > 1)) { + const int s31 = mask->nb[1] / sizeof(half2); + const int s33 = mask->nb[3] / sizeof(half2); + + const dim3 blocks_num_KV_max(ntiles_x, Q->ne[3], 1); + const dim3 block_dim_KV_max(FATTN_KQ_STRIDE/2, 1, 1); + + const int ne_KV_max = blocks_num_KV_max.x*blocks_num_KV_max.y; + const int iter_k = K->ne[1] / FATTN_KQ_STRIDE; + + KV_max.alloc(ne_KV_max); + flash_attn_mask_to_KV_max<<>> + ((const half2 *) mask->data, KV_max.ptr, iter_k, s31, s33); + CUDA_CHECK(cudaGetLastError()); + } + const dim3 block_dim(warp_size, nwarps, 1); int max_blocks_per_sm = 1; // Max. number of active blocks limited by occupancy. CUDA_CHECK(cudaOccupancyMaxActiveBlocksPerMultiprocessor(&max_blocks_per_sm, fattn_kernel, block_dim.x * block_dim.y * block_dim.z, nbytes_shared)); + int parallel_blocks = max_blocks_per_sm; dim3 blocks_num; if (stream_k) { @@ -787,9 +919,6 @@ void launch_fattn( GGML_ASSERT(K->ne[1] % KQ_row_granularity == 0); const int ntiles_KQ = K->ne[1] / KQ_row_granularity; // Max. number of parallel blocks limited by tensor size. - // parallel_blocks should be at least large enough to achieve max. occupancy for a single wave: - parallel_blocks = std::max((nsm * max_blocks_per_sm) / ntiles_total, 1); - // parallel_blocks must not be larger than what the tensor size allows: parallel_blocks = std::min(parallel_blocks, ntiles_KQ); @@ -804,7 +933,7 @@ void launch_fattn( const int efficiency_percent = 100 * nblocks_total / (nwaves*blocks_per_wave); // Stop trying configurations with more waves if we already have good efficiency to avoid excessive overhead. - if (efficiency_percent_best >= 90 && nwaves > nwaves_best) { + if (efficiency_percent_best >= 95 && nwaves > nwaves_best) { break; } @@ -849,16 +978,15 @@ void launch_fattn( K_data, V_data, mask ? ((const char *) mask->data) : nullptr, + sinks ? ((const char *) sinks->data) : nullptr, + KV_max.ptr, !stream_k && parallel_blocks > 1 ? dst_tmp.ptr : (float *) KQV->data, dst_tmp_meta.ptr, scale, max_bias, m0, m1, n_head_log2, logit_softcap, - Q->ne[0], Q->ne[1], Q->ne[2], Q->ne[3], - K->ne[0], K->ne[1], K->ne[2], K->ne[3], - mask ? mask->ne[1] : 0, mask ? mask->ne[2] : 0, - mask ? mask->nb[1] : 0, mask ? mask->nb[2] : 0, - Q->nb[1], Q->nb[2], Q->nb[3], - nb11, nb12, nb13, + Q->ne[0], Q->ne[1], Q->ne[2], Q->ne[3], Q->nb[1], Q->nb[2], Q->nb[3], + K->ne[0], K->ne[1], K->ne[2], K->ne[3], nb11, nb12, nb13, nb21, nb22, nb23, - KQV->ne[0], KQV->ne[1], KQV->ne[2], KQV->ne[3] + mask ? mask->ne[1] : 0, mask ? mask->ne[2] : 0, mask ? mask->ne[3] : 0, + mask ? mask->nb[1] : 0, mask ? mask->nb[2] : 0, mask ? mask->nb[3] : 0 ); CUDA_CHECK(cudaGetLastError()); @@ -869,11 +997,11 @@ void launch_fattn( flash_attn_stream_k_fixup <<>> - ((float *) KQV->data, dst_tmp_meta.ptr, Q->ne[1], Q->ne[2], K->ne[1]); + ((float *) KQV->data, dst_tmp_meta.ptr, Q->ne[1], Q->ne[2], Q->ne[3], K->ne[1]); } } else if (parallel_blocks > 1) { const dim3 block_dim_combine(DV, 1, 1); - const dim3 blocks_num_combine(Q->ne[1], 1, blocks_num.z); + const dim3 blocks_num_combine(Q->ne[1], Q->ne[2], Q->ne[3]); const size_t nbytes_shared_combine = parallel_blocks*sizeof(float2); flash_attn_combine_results diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-mma-f16.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-mma-f16.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-mma-f16.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-mma-f16.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -392,7 +392,8 @@ static __device__ __forceinline__ void f } } -template +template static __device__ __forceinline__ void flash_attn_ext_f16_iter( const float2 * const __restrict__ Q_f2, const half2 * const __restrict__ K_h2, @@ -408,7 +409,6 @@ static __device__ __forceinline__ void f const int stride_K, const int stride_V, const int stride_mask, - const int jt, half2 * const __restrict__ tile_Q, half2 * const __restrict__ tile_K, half2 * const __restrict__ tile_V, @@ -418,7 +418,7 @@ static __device__ __forceinline__ void f float * const __restrict__ KQ_max, float * const __restrict__ KQ_rowsum, const int kb0) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE typedef fattn_mma_f16_config c; #ifdef CP_ASYNC_AVAILABLE @@ -455,7 +455,7 @@ static __device__ __forceinline__ void f cp_async_wait_all(); __syncthreads(); flash_attn_ext_f16_load_tile - (V_h2 + k_VKQ_0*stride_V, tile_V, nbatch_V2, stride_V); + (V_h2 + int64_t(k_VKQ_0)*stride_V, tile_V, nbatch_V2, stride_V); } else { constexpr bool use_cp_async = nstages == 1; if (ncols2 > 1 || mask_h2) { @@ -471,7 +471,7 @@ static __device__ __forceinline__ void f if (nstages <= 1) { constexpr bool use_cp_async = nstages == 1; flash_attn_ext_f16_load_tile - (K_h2 + k_VKQ_0*stride_K + k0_start, tile_K, k0_diff, stride_K); + (K_h2 + int64_t(k_VKQ_0)*stride_K + k0_start, tile_K, k0_diff, stride_K); if (use_cp_async) { cp_async_wait_all(); } @@ -715,7 +715,7 @@ static __device__ __forceinline__ void f (mask_h2 + (k_VKQ_0 + c::nbatch_fa)/2, tile_mask, stride_mask); } flash_attn_ext_f16_load_tile - (K_h2 + (k_VKQ_0 + c::nbatch_fa)*stride_K, tile_K, nbatch_K2, stride_K); + (K_h2 + int64_t(k_VKQ_0 + c::nbatch_fa)*stride_K, tile_K, nbatch_K2, stride_K); } } @@ -732,7 +732,7 @@ static __device__ __forceinline__ void f if (nstages <= 1 && i0_start < reusable_cutoff) { constexpr bool use_cp_async = nstages == 1; flash_attn_ext_f16_load_tile - (V_h2 + k_VKQ_0*stride_V + i0_start/2, tile_V, i0_diff/2, stride_V); + (V_h2 + int64_t(k_VKQ_0)*stride_V + i0_start/2, tile_V, i0_diff/2, stride_V); if (use_cp_async) { cp_async_wait_all(); } @@ -767,17 +767,13 @@ static __device__ __forceinline__ void f } } #else - GGML_UNUSED(Q_f2); GGML_UNUSED(K_h2); GGML_UNUSED(V_h2); - GGML_UNUSED(mask_h2); GGML_UNUSED(dstk); GGML_UNUSED(dstk_fixup); - GGML_UNUSED(scale); GGML_UNUSED(slope); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(stride_K); GGML_UNUSED(stride_V); - GGML_UNUSED(stride_mask); GGML_UNUSED(jt); GGML_UNUSED(tile_K); - GGML_UNUSED(stride_mask); GGML_UNUSED(jt); GGML_UNUSED(tile_K); - GGML_UNUSED(tile_V); GGML_UNUSED(tile_mask); GGML_UNUSED(Q_B); - GGML_UNUSED(VKQ_C); GGML_UNUSED(KQ_max); GGML_UNUSED(KQ_rowsum); - GGML_UNUSED(kb0); GGML_UNUSED(tile_Q); + GGML_UNUSED_VARS(Q_f2, K_h2, V_h2, mask_h2, dstk, dstk_fixup, + scale, slope, logit_softcap, ne01, ne02, + stride_K, stride_V, stride_mask, + tile_Q, tile_K, tile_V, tile_mask, + Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template @@ -786,6 +782,7 @@ static __device__ __forceinline__ void f const half2 * const __restrict__ K_h2, const half2 * const __restrict__ V_h2, const half2 * const __restrict__ mask_h2, + const float * const __restrict__ sinks_f, float2 * const __restrict__ dstk, float2 * const __restrict__ dstk_fixup, const float scale, @@ -801,7 +798,7 @@ static __device__ __forceinline__ void f const int jt, const int kb0_start, const int kb0_stop) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE //In this kernel Q, K, V are matrices while i, j, k are matrix indices. typedef fattn_mma_f16_config c; @@ -920,21 +917,22 @@ static __device__ __forceinline__ void f (mask_h2 + kb0_start*c::nbatch_fa/2, tile_mask, stride_mask); } flash_attn_ext_f16_load_tile - (K_h2 + kb0_start*c::nbatch_fa*stride_K, tile_K, nbatch_K2, stride_K); + (K_h2 + int64_t(kb0_start)*c::nbatch_fa*stride_K, tile_K, nbatch_K2, stride_K); } // Iterate over ne11 == previous tokens: - for (int kb0 = kb0_start; kb0 < kb0_stop-1; ++kb0) { + int kb0 = kb0_start; + for (; kb0 < kb0_stop-1; ++kb0) { constexpr bool last_iter = false; flash_attn_ext_f16_iter (Q_f2, K_h2, V_h2, mask_h2, dstk, dstk_fixup, scale, slope, logit_softcap, - ne01, ne02, stride_K, stride_V, stride_mask, jt, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); + ne01, ne02, stride_K, stride_V, stride_mask, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); } { // kb0_start is always < kb0_stop so the last iter can be executed unconditionally. constexpr bool last_iter = true; flash_attn_ext_f16_iter (Q_f2, K_h2, V_h2, mask_h2, dstk, dstk_fixup, scale, slope, logit_softcap, - ne01, ne02, stride_K, stride_V, stride_mask, jt, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0_stop-1); + ne01, ne02, stride_K, stride_V, stride_mask, tile_Q, tile_K, tile_V, tile_mask, Q_B, VKQ_C, KQ_max, KQ_rowsum, kb0); } // With multi-stage loading there is no __syncthreads at the end of the iter, @@ -957,6 +955,52 @@ static __device__ __forceinline__ void f } } + // If attention sinks are used, potentially re-scale if KQ_max is small. + // Also add the sink as a value to KQ_rowsum, this is done after synchonization of KQ_rowsum + // so it's being done unconditionally for every thread. + if (!is_fixup && (np == 1 || threadIdx.y % np == 0) && sinks_f) { + float KQ_max_scale[cols_per_thread]; +#pragma unroll + for (int col = 0; col < cols_per_thread; ++col) { + static_assert(ntiles == 1 || ntiles == 2, "ntiles > 2 not implemented"); + const int jc = ntiles == 1 ? 2*tile_C_VKQ::get_j(col/2) + col % 2 : tile_C_VKQ_16::get_i(col); + const float sink = sinks_f[jc % ncols2]; + + const float KQ_max_new = fmaxf(KQ_max[col], sink); + const float KQ_max_diff = KQ_max[col] - KQ_max_new; + KQ_max_scale[col] = expf(KQ_max_diff); + KQ_max[col] = KQ_max_new; + + *((uint32_t *) &KQ_max_scale[col]) *= KQ_max_diff >= SOFTMAX_FTZ_THRESHOLD; + + const float KQ_max_add = expf(sink - KQ_max_new); + KQ_rowsum[col] = KQ_max_scale[col]*KQ_rowsum[col] + KQ_max_add; + } + + if (ntiles == 1) { + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale[0], KQ_max_scale[1]); +#pragma unroll + for (int i = 0; i < DV/tile_C_VKQ::I; ++i) { +#pragma unroll + for (int l = 0; l < tile_C_VKQ::ne; ++l) { + VKQ_C[i].x[l] *= KQ_max_scale_h2; + } + } + } else { +#pragma unroll + for (int col = 0; col < cols_per_thread; ++col) { + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale[col], KQ_max_scale[col]); +#pragma unroll + for (int i = 0; i < DV/tile_C_VKQ_16::J; ++i) { +#pragma unroll + for (int l0 = 0; l0 < tile_C_VKQ_16::ne; l0 += 2) { + VKQ_C_16[i*ntiles/2 + col/2].x[l0 + col % 2] *= KQ_max_scale_h2; + } + } + } + } + } + // Combine VKQ accumulator values if np > 1. // It's also faster to do small writes to shared memory, then large write to VRAM than to do small writes to VRAM. // So also write VKQ accumulators to shared memory in column-major format if np == 1. @@ -1189,14 +1233,12 @@ static __device__ __forceinline__ void f } } #else - GGML_UNUSED(Q_f2); GGML_UNUSED(K_h2); GGML_UNUSED(V_h2); - GGML_UNUSED(mask_h2); GGML_UNUSED(dstk); GGML_UNUSED(dstk_fixup); - GGML_UNUSED(scale); GGML_UNUSED(slope); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(stride_Q1); - GGML_UNUSED(stride_Q2); GGML_UNUSED(stride_K); GGML_UNUSED(stride_V); GGML_UNUSED(stride_mask); - GGML_UNUSED(jt); GGML_UNUSED(kb0_start); GGML_UNUSED(kb0_stop); + GGML_UNUSED_VARS(Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dstk_fixup, + scale, slope, logit_softcap, ne01, ne02, + stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, + jt, kb0_start, kb0_stop); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template @@ -1206,6 +1248,8 @@ static __global__ void flash_attn_ext_f1 const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -1214,32 +1258,14 @@ static __global__ void flash_attn_ext_f1 const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#if defined(FLASH_ATTN_AVAILABLE) && defined(NEW_MMA_AVAILABLE) + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { +#if defined(FLASH_ATTN_AVAILABLE) && defined(TURING_MMA_AVAILABLE) // Skip unused kernel variants for faster compilation: if (use_logit_softcap && !(DKQ == 128 || DKQ == 256)) { @@ -1274,8 +1300,8 @@ static __global__ void flash_attn_ext_f1 constexpr int kb_niter = FATTN_KQ_STRIDE / c::nbatch_fa; // Number of kernel iterations per assigned KQ slice. // kbc == k block continuous, current index in continuous ijk space. - int kbc = (blockIdx.x + 0)*iter_k*iter_j*(ne02/ncols2) / gridDim.x; - const int kbc_stop = (blockIdx.x + 1)*iter_k*iter_j*(ne02/ncols2) / gridDim.x; + int kbc = (blockIdx.x + 0)*(iter_k*iter_j*(ne02/ncols2)*ne03) / gridDim.x; + const int kbc_stop = (blockIdx.x + 1)*(iter_k*iter_j*(ne02/ncols2)*ne03) / gridDim.x; // If the seams of 2 CUDA blocks fall within an output tile their results need to be combined. // For this we need to track both the block that starts the tile (needs_fixup) and the block that finishes the tile (is_fixup). @@ -1284,33 +1310,42 @@ static __global__ void flash_attn_ext_f1 // kb0 == k start index when in the output tile. int kb0_start = kbc % iter_k; int kb0_stop = min(iter_k, kb0_start + kbc_stop - kbc); + while (kbc < kbc_stop && kb0_stop == iter_k) { - const int channel = kbc / (iter_k*iter_j); - const int jt = (kbc - channel*iter_k*iter_j) / iter_k; // j index of current tile. + const int sequence = kbc / (iter_k*iter_j*(ne02/ncols2)); + const int zt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); // head in units of ncols2 + const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*zt) / iter_k; // j index of current tile. + + const int head0 = zt * ncols2; - const float2 * Q_f2 = (const float2 *) (Q + nb02* channel*ncols2); - const half2 * K_h2 = (const half2 *) (K + nb12*(channel*ncols2 / gqa_ratio)); + const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02* head0); + const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head0 / gqa_ratio)); const half2 * mask_h2 = ncols2 == 1 && !mask ? nullptr : - (const half2 *) (mask + nb32*(channel % ne32) + nb31*jt*ncols1); - float2 * dstk = ((float2 *) dst) + channel*(ncols2 * DV/2); + (const half2 *) (mask + nb33*(sequence % ne33) + nb31*jt*ncols1); + float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head0) * (DV/2); - const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb22*(channel*ncols2 / gqa_ratio)); + const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head0 / gqa_ratio)); + const float * sinks_f = sinks ? (const float *) sinks + head0 : nullptr; - const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, channel, n_head_log2, m0, m1) : 1.0f; + const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head0, n_head_log2, m0, m1) : 1.0f; const int kb0_start_kernel = kb0_start * kb_niter; - const int kb0_stop_kernel = kb0_stop * kb_niter; + int kb0_stop_kernel = kb0_stop * kb_niter; + + if (KV_max) { + kb0_stop_kernel = min(kb0_stop_kernel, KV_max[sequence*iter_j + jt] / c::nbatch_fa); + } constexpr bool is_fixup = false; // All but (potentially) the last iterations write their data to dst rather than the fixup buffer. if (kb0_start == 0) { constexpr bool needs_fixup = false; // CUDA block is working on an entire tile. flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); } else { constexpr bool needs_fixup = true; // CUDA block is working on the beginning of a tile. flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); } @@ -1325,40 +1360,47 @@ static __global__ void flash_attn_ext_f1 return; } - const int channel = kbc / (iter_k*iter_j); - const int jt = (kbc - channel*iter_k*iter_j) / iter_k; // j index of current tile. + const int sequence = kbc / (iter_k*iter_j*(ne02/ncols2)); + const int zt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence) / (iter_k*iter_j); // head in units of ncols2 + const int jt = (kbc - iter_k*iter_j*(ne02/ncols2)*sequence - iter_k*iter_j*zt) / iter_k; // j index of current tile. + + const int head0 = zt * ncols2; - const float2 * Q_f2 = (const float2 *) (Q + nb02* channel*ncols2); - const half2 * K_h2 = (const half2 *) (K + nb12*(channel*ncols2 / gqa_ratio)); + const float2 * Q_f2 = (const float2 *) (Q + nb03*sequence + nb02* head0); + const half2 * K_h2 = (const half2 *) (K + nb13*sequence + nb12*(head0 / gqa_ratio)); const half2 * mask_h2 = ncols2 == 1 && !mask ? nullptr : - (const half2 *) (mask + nb32*(channel % ne32) + nb31*jt*ncols1); - float2 * dstk = ((float2 *) dst) + channel*(ncols2 * DV/2); + (const half2 *) (mask + nb33*(sequence % ne33) + nb31*jt*ncols1); + float2 * dstk = ((float2 *) dst) + (sequence*ne01*ne02 + head0) * (DV/2); - const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb22*(channel*ncols2 / gqa_ratio)); + const half2 * V_h2 = mla ? K_h2 + (DKQ/2 - DV/2) : (const half2 *) (V + nb23*sequence + nb22*(head0 / gqa_ratio)); + const float * sinks_f = sinks ? (const float *) sinks + head0 : nullptr; - const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, channel, n_head_log2, m0, m1) : 1.0f; + const float slope = ncols2 == 1 ? get_alibi_slope(max_bias, head0, n_head_log2, m0, m1) : 1.0f; const int kb0_start_kernel = kb0_start * kb_niter; - const int kb0_stop_kernel = kb0_stop * kb_niter; + int kb0_stop_kernel = kb0_stop * kb_niter; + + if (KV_max) { + kb0_stop_kernel = min(kb0_stop_kernel, KV_max[sequence*iter_j + jt] / c::nbatch_fa); + } constexpr bool is_fixup = true; // Last index writes its data to fixup buffer to avoid data races with other blocks. constexpr bool needs_fixup = false; flash_attn_ext_f16_process_tile - (Q_f2, K_h2, V_h2, mask_h2, dstk, dst_meta, scale, slope, logit_softcap, + (Q_f2, K_h2, V_h2, mask_h2, sinks_f, dstk, dst_meta, scale, slope, logit_softcap, ne01, ne02, stride_Q1, stride_Q2, stride_K, stride_V, stride_mask, jt, kb0_start_kernel, kb0_stop_kernel); #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); GGML_UNUSED(ne00); - GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); GGML_UNUSED(ne10); - GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); - GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); GGML_UNUSED(nb21); - GGML_UNUSED(nb22); GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); NO_DEVICE_CODE; -#endif // defined(FLASH_ATTN_AVAILABLE) && defined(NEW_MMA_AVAILABLE) +#endif // defined(FLASH_ATTN_AVAILABLE) && defined(TURING_MMA_AVAILABLE) } template @@ -1408,24 +1450,24 @@ void ggml_cuda_flash_attn_ext_mma_f16_ca constexpr bool use_logit_softcap = false; fattn_kernel = flash_attn_ext_f16; -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = {false}; if (!shared_memory_limit_raised[id]) { CUDA_CHECK(cudaFuncSetAttribute(fattn_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, nbytes_shared_total)); shared_memory_limit_raised[id] = true; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) } else { constexpr bool use_logit_softcap = true; fattn_kernel = flash_attn_ext_f16; -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) static bool shared_memory_limit_raised[GGML_CUDA_MAX_DEVICES] = {false}; if (!shared_memory_limit_raised[id]) { CUDA_CHECK(cudaFuncSetAttribute(fattn_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, nbytes_shared_total)); shared_memory_limit_raised[id] = true; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && !defined(GGML_USE_MUSA) +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) } launch_fattn diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,359 +0,0 @@ -#include "common.cuh" -#include "fattn-common.cuh" -#include "fattn-tile-f16.cuh" - -#define FATTN_KQ_STRIDE_TILE_F16 64 - -template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) -__launch_bounds__(nwarps*WARP_SIZE, 2) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) -static __global__ void flash_attn_tile_ext_f16( - const char * __restrict__ Q, - const char * __restrict__ K, - const char * __restrict__ V, - const char * __restrict__ mask, - float * __restrict__ dst, - float2 * __restrict__ dst_meta, - const float scale, - const float max_bias, - const float m0, - const float m1, - const uint32_t n_head_log2, - const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#if defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) - - // Skip unused kernel variants for faster compilation: -#ifdef FP16_MMA_AVAILABLE - NO_DEVICE_CODE; - return; -#endif // FP16_MMA_AVAILABLE - if (use_logit_softcap && !(D == 128 || D == 256)) { - NO_DEVICE_CODE; - return; - } - - //In this kernel Q, K, V are matrices while i, j, k are matrix indices. - - const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. - - const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float2 * Q_f2 = (const float2 *) (Q + nb02* blockIdx.z + nb01*ic0); - const half2 * K_h2 = (const half2 *) (K + nb12*(blockIdx.z / gqa_ratio)); - const half2 * V_h2 = (const half2 *) (V + nb12*(blockIdx.z / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb32*(blockIdx.z % ne32) + nb31*ic0); - - const int stride_KV2 = nb11 / sizeof(half2); - - const float slopef = get_alibi_slope(max_bias, blockIdx.z, n_head_log2, m0, m1); - const half slopeh = __float2half(slopef); - - static_assert(D % (2*WARP_SIZE) == 0, "D not divisible by 2*WARP_SIZE == 64."); - - __shared__ half KQ[ncols*FATTN_KQ_STRIDE_TILE_F16]; - half2 * KQ2 = (half2 *) KQ; - - __shared__ half2 KV_tmp[FATTN_KQ_STRIDE_TILE_F16][D/2 + 1]; // Pad D to avoid memory bank conflicts. - - half kqmax[ncols/nwarps]; -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - kqmax[j0/nwarps] = -HALF_MAX_HALF; - } - half2 kqsum[ncols/nwarps] = {{0.0f, 0.0f}}; - - half2 VKQ[ncols/nwarps][(D/2)/WARP_SIZE] = {{{0.0f, 0.0f}}}; - - // Convert Q to half2 and store in registers: - __shared__ half2 Q_h2[ncols][D/2]; -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const float2 tmp = ic0 + j < ne01 ? Q_f2[j*(nb01/sizeof(float2)) + i] : make_float2(0.0f, 0.0f); - Q_h2[j][i] = make_half2(scale, scale) * make_half2(tmp.x, tmp.y); - } - } - - __syncthreads(); - - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F16; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F16) { - // Calculate KQ tile and keep track of new maximum KQ values: - - half kqmax_new[ncols/nwarps]; -#pragma unroll - for (int j = 0; j < ncols/nwarps; ++j) { - kqmax_new[j] = kqmax[j]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F16; i_KQ_0 += nwarps) { - const int i_KQ = i_KQ_0 + threadIdx.y; - -#pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < D/2; k_KQ_0 += WARP_SIZE) { - const int k_KQ = k_KQ_0 + threadIdx.x; - - KV_tmp[i_KQ][k_KQ] = K_h2[(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ]; - } - } - - __syncthreads(); - - half2 sum2[FATTN_KQ_STRIDE_TILE_F16/WARP_SIZE][ncols/nwarps] = {{{0.0f, 0.0f}}}; - -#pragma unroll - for (int k_KQ = 0; k_KQ < D/2; ++k_KQ) { - half2 K_k[FATTN_KQ_STRIDE_TILE_F16/WARP_SIZE]; - half2 Q_k[ncols/nwarps]; - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F16; i_KQ_0 += WARP_SIZE) { - const int i_KQ = i_KQ_0 + threadIdx.x; - - K_k[i_KQ_0/WARP_SIZE] = KV_tmp[i_KQ][k_KQ]; - } -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - const int j_KQ = j_KQ_0 + threadIdx.y; - - Q_k[j_KQ_0/nwarps] = Q_h2[j_KQ][k_KQ]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F16; i_KQ_0 += WARP_SIZE) { -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - sum2[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps] += K_k[i_KQ_0/WARP_SIZE]*Q_k[j_KQ_0/nwarps]; - } - } - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F16; i_KQ_0 += WARP_SIZE) { - const int i_KQ = i_KQ_0 + threadIdx.x; - -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - const int j_KQ = j_KQ_0 + threadIdx.y; - - half sum; - if (use_logit_softcap) { - const float2 tmp = __half22float2(sum2[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]); - sum = logit_softcap * tanhf(tmp.x + tmp.y); - } else { - sum = __low2half(sum2[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]) + __high2half(sum2[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]); - } - sum += mask ? slopeh*maskh[j_KQ*ne11 + k_VKQ_0 + i_KQ] : __float2half(0.0f); - - kqmax_new[j_KQ_0/nwarps] = ggml_cuda_hmax(kqmax_new[j_KQ_0/nwarps], sum); - - KQ[j_KQ*FATTN_KQ_STRIDE_TILE_F16 + i_KQ] = sum; - } - } - - __syncthreads(); - -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - kqmax_new[j0/nwarps] = warp_reduce_max(kqmax_new[j0/nwarps]); - const half2 KQ_max_scale = __half2half2(hexp(kqmax[j0/nwarps] - kqmax_new[j0/nwarps])); - kqmax[j0/nwarps] = kqmax_new[j0/nwarps]; - -#pragma unroll - for (int i0 = 0; i0 < FATTN_KQ_STRIDE_TILE_F16/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const half2 diff = KQ2[j*(FATTN_KQ_STRIDE_TILE_F16/2) + i] - __half2half2(kqmax[j0/nwarps]); - const half2 val = h2exp(diff); - kqsum[j0/nwarps] = kqsum[j0/nwarps]*KQ_max_scale + val; - KQ2[j*(FATTN_KQ_STRIDE_TILE_F16/2) + i] = val; - } - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - VKQ[j0/nwarps][i0/WARP_SIZE] *= KQ_max_scale; - } - } - - __syncthreads(); - -#pragma unroll - for (int k0 = 0; k0 < FATTN_KQ_STRIDE_TILE_F16; k0 += nwarps) { - const int k = k0 + threadIdx.y; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - KV_tmp[k][i] = V_h2[(k_VKQ_0 + k)*stride_KV2 + i]; - } - } - - __syncthreads(); - -#pragma unroll - for (int k0 = 0; k0 < FATTN_KQ_STRIDE_TILE_F16; k0 += 2) { - half2 V_k[(D/2)/WARP_SIZE][2]; - half2 KQ_k[ncols/nwarps]; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - V_k[i0/WARP_SIZE][0] = KV_tmp[k0 + 0][i]; - V_k[i0/WARP_SIZE][1] = KV_tmp[k0 + 1][i]; - } -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - KQ_k[j0/nwarps] = KQ2[j*(FATTN_KQ_STRIDE_TILE_F16/2) + k0/2]; - } - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - VKQ[j0/nwarps][i0/WARP_SIZE] += V_k[i0/WARP_SIZE][0]* __low2half2(KQ_k[j0/nwarps]); - VKQ[j0/nwarps][i0/WARP_SIZE] += V_k[i0/WARP_SIZE][1]*__high2half2(KQ_k[j0/nwarps]); - } - } - } - - __syncthreads(); - } - -#pragma unroll - for (int j_VKQ_0 = 0; j_VKQ_0 < ncols; j_VKQ_0 += nwarps) { - const int j_VKQ = j_VKQ_0 + threadIdx.y; - - if (ic0 + j_VKQ >= ne01) { - return; - } - - half kqsum_j = __low2half(kqsum[j_VKQ_0/nwarps]) + __high2half(kqsum[j_VKQ_0/nwarps]); - kqsum_j = warp_reduce_sum((float)kqsum_j); - -#pragma unroll - for (int i00 = 0; i00 < D; i00 += 2*WARP_SIZE) { - const int i0 = i00 + 2*threadIdx.x; - - half2 dst_val = VKQ[j_VKQ_0/nwarps][i0/(2*WARP_SIZE)]; - if (gridDim.y == 1) { - dst_val /= __half2half2(kqsum_j); - } - const int j_dst = (ic0 + j_VKQ)*gridDim.y + blockIdx.y; - dst[j_dst*D*gridDim.z + D*blockIdx.z + i0 + 0] = __low2float(dst_val); - dst[j_dst*D*gridDim.z + D*blockIdx.z + i0 + 1] = __high2float(dst_val); - } - - if (gridDim.y != 1 && threadIdx.x == 0) { - dst_meta[((ic0 + j_VKQ)*gridDim.z + blockIdx.z) * gridDim.y + blockIdx.y] = make_float2(kqmax[j_VKQ_0/nwarps], kqsum_j); - } - } -#else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; -#endif // defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) -} - -template -void launch_fattn_tile_f16_64_128(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * Q = dst->src[0]; - switch (Q->ne[0]) { - case 64: { - constexpr int D = 64; - constexpr int nwarps = 8; - constexpr size_t nbytes_shared = 0; - fattn_kernel_t fattn_kernel = flash_attn_tile_ext_f16; - launch_fattn - (ctx, dst, fattn_kernel, nwarps, nbytes_shared, FATTN_KQ_STRIDE_TILE_F16, true, true, false); - } break; - case 128: { - constexpr int D = 128; - constexpr int nwarps = 8; - constexpr size_t nbytes_shared = 0; - fattn_kernel_t fattn_kernel = flash_attn_tile_ext_f16; - launch_fattn - (ctx, dst, fattn_kernel, nwarps, nbytes_shared, FATTN_KQ_STRIDE_TILE_F16, true, true, false); - } break; - default: { - GGML_ABORT("FlashAttention without tensor cores only supports head sizes 64 and 128."); - } break; - } -} - -void ggml_cuda_flash_attn_ext_tile_f16(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - - const int32_t precision = KQV->op_params[3]; - GGML_ASSERT(precision == GGML_PREC_DEFAULT); - - float logit_softcap; - memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); - - if (Q->ne[1] <= 16) { - constexpr int cols_per_block = 16; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - launch_fattn_tile_f16_64_128(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - launch_fattn_tile_f16_64_128(ctx, dst); - } - return; - } - - constexpr int cols_per_block = 32; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - launch_fattn_tile_f16_64_128(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - launch_fattn_tile_f16_64_128(ctx, dst); - } -} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f16.cuh 1970-01-01 00:00:00.000000000 +0000 @@ -1,3 +0,0 @@ -#include "common.cuh" - -void ggml_cuda_flash_attn_ext_tile_f16(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cu 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,367 +0,0 @@ -#include "common.cuh" -#include "fattn-common.cuh" -#include "fattn-tile-f32.cuh" - -#define FATTN_KQ_STRIDE_TILE_F32 32 - -template // D == head size -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) -__launch_bounds__(nwarps*WARP_SIZE, 2) -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) -static __global__ void flash_attn_tile_ext_f32( - const char * __restrict__ Q, - const char * __restrict__ K, - const char * __restrict__ V, - const char * __restrict__ mask, - float * __restrict__ dst, - float2 * __restrict__ dst_meta, - const float scale, - const float max_bias, - const float m0, - const float m1, - const uint32_t n_head_log2, - const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#ifdef FLASH_ATTN_AVAILABLE - - // Skip unused kernel variants for faster compilation: -#ifdef FP16_MMA_AVAILABLE - NO_DEVICE_CODE; - return; -#endif // FP16_MMA_AVAILABLE - if (use_logit_softcap && !(D == 128 || D == 256)) { - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; - return; - } - - // In this kernel Q, K, V are matrices while i, j, k are matrix indices. - - const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. - - const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float2 * Q_f2 = (const float2 *) (Q + nb02* blockIdx.z + nb01*ic0); - const half2 * K_h2 = (const half2 *) (K + nb12*(blockIdx.z / gqa_ratio)); - const half2 * V_h2 = (const half2 *) (V + nb12*(blockIdx.z / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb32*(blockIdx.z % ne32) + nb31*ic0); - - const int stride_KV2 = nb11 / sizeof(half2); - - const float slope = get_alibi_slope(max_bias, blockIdx.z, n_head_log2, m0, m1); - - static_assert(D % (2*WARP_SIZE) == 0, "D not divisible by 2*WARP_SIZE == 64."); - - __shared__ float KQ[ncols*FATTN_KQ_STRIDE_TILE_F32]; - - __shared__ float KV_tmp[FATTN_KQ_STRIDE_TILE_F32][D + 1]; // Pad D to avoid memory bank conflicts. - float2 * KV_tmp2 = (float2 *) KV_tmp; - - float kqmax[ncols/nwarps]; -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - kqmax[j0/nwarps] = -FLT_MAX/2.0f; - } - float kqsum[ncols/nwarps] = {0.0f}; - - float2 VKQ[ncols/nwarps][(D/2)/WARP_SIZE] = {{{0.0f, 0.0f}}}; - - // Convert Q to half2 and store in registers: - __shared__ float Q_f[ncols][D]; -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - -#pragma unroll - for (int i0 = 0; i0 < D; i0 += 2*WARP_SIZE) { - float2 tmp = ic0 + j < ne01 ? Q_f2[j*(nb01/sizeof(float2)) + i0/2 + threadIdx.x] : make_float2(0.0f, 0.0f); - Q_f[j][i0 + 0*WARP_SIZE + threadIdx.x] = tmp.x * scale; - Q_f[j][i0 + 1*WARP_SIZE + threadIdx.x] = tmp.y * scale; - } - } - - __syncthreads(); - - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE_TILE_F32; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE_TILE_F32) { - // Calculate KQ tile and keep track of new maximum KQ values: - - float kqmax_new[ncols/nwarps]; -#pragma unroll - for (int j = 0; j < ncols/nwarps; ++j) { - kqmax_new[j] = kqmax[j]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F32; i_KQ_0 += nwarps) { - const int i_KQ = i_KQ_0 + threadIdx.y; - -#pragma unroll - for (int k_KQ_0 = 0; k_KQ_0 < D; k_KQ_0 += 2*WARP_SIZE) { - const half2 tmp = K_h2[(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ_0/2 + threadIdx.x]; - KV_tmp[i_KQ][k_KQ_0 + 0*WARP_SIZE + threadIdx.x] = __low2float(tmp); - KV_tmp[i_KQ][k_KQ_0 + 1*WARP_SIZE + threadIdx.x] = __high2float(tmp); - } - } - - __syncthreads(); - - float sum[FATTN_KQ_STRIDE_TILE_F32/WARP_SIZE][ncols/nwarps] = {{0.0f}}; - -#pragma unroll - for (int k_KQ = 0; k_KQ < D; ++k_KQ) { - float K_k[FATTN_KQ_STRIDE_TILE_F32/WARP_SIZE]; - float Q_k[ncols/nwarps]; - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F32; i_KQ_0 += WARP_SIZE) { - const int i_KQ = i_KQ_0 + threadIdx.x; - - K_k[i_KQ_0/WARP_SIZE] = KV_tmp[i_KQ][k_KQ]; - } -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - const int j_KQ = j_KQ_0 + threadIdx.y; - - Q_k[j_KQ_0/nwarps] = Q_f[j_KQ][k_KQ]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F32; i_KQ_0 += WARP_SIZE) { -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps] += K_k[i_KQ_0/WARP_SIZE] * Q_k[j_KQ_0/nwarps]; - } - } - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE_TILE_F32; i_KQ_0 += WARP_SIZE) { - const int i_KQ = i_KQ_0 + threadIdx.x; - -#pragma unroll - for (int j_KQ_0 = 0; j_KQ_0 < ncols; j_KQ_0 += nwarps) { - const int j_KQ = j_KQ_0 + threadIdx.y; - - if (use_logit_softcap) { - sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps] = logit_softcap * tanhf(sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]); - } - - sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps] += mask ? slope*__half2float(maskh[j_KQ*ne11 + k_VKQ_0 + i_KQ]) : 0.0f; - - kqmax_new[j_KQ_0/nwarps] = fmaxf(kqmax_new[j_KQ_0/nwarps], sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]); - - KQ[j_KQ*FATTN_KQ_STRIDE_TILE_F32 + i_KQ] = sum[i_KQ_0/WARP_SIZE][j_KQ_0/nwarps]; - } - } - - __syncthreads(); - -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - kqmax_new[j0/nwarps] = warp_reduce_max(kqmax_new[j0/nwarps]); - const float KQ_max_scale = expf(kqmax[j0/nwarps] - kqmax_new[j0/nwarps]); - kqmax[j0/nwarps] = kqmax_new[j0/nwarps]; - - float kqsum_add = 0.0f; -#pragma unroll - for (int i0 = 0; i0 < FATTN_KQ_STRIDE_TILE_F32; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const float diff = KQ[j*FATTN_KQ_STRIDE_TILE_F32 + i] - kqmax[j0/nwarps]; - const float val = expf(diff); - kqsum_add += val; - KQ[j*FATTN_KQ_STRIDE_TILE_F32 + i] = val; - } - kqsum[j0/nwarps] = kqsum[j0/nwarps]*KQ_max_scale + kqsum_add; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - VKQ[j0/nwarps][i0/WARP_SIZE].x *= KQ_max_scale; - VKQ[j0/nwarps][i0/WARP_SIZE].y *= KQ_max_scale; - } - } - - __syncthreads(); - -#pragma unroll - for (int k0 = 0; k0 < FATTN_KQ_STRIDE_TILE_F32; k0 += nwarps) { - const int k = k0 + threadIdx.y; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - KV_tmp2[k*(D/2) + i].x = __low2float(V_h2[(k_VKQ_0 + k)*stride_KV2 + i]); - KV_tmp2[k*(D/2) + i].y = __high2float(V_h2[(k_VKQ_0 + k)*stride_KV2 + i]); - } - } - - __syncthreads(); - -#pragma unroll - for (int k = 0; k < FATTN_KQ_STRIDE_TILE_F32; ++k) { - float2 V_k[(D/2)/WARP_SIZE]; - float KQ_k[ncols/nwarps]; - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - V_k[i0/WARP_SIZE] = KV_tmp2[k*(D/2) + i]; - } -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - KQ_k[j0/nwarps] = KQ[j*FATTN_KQ_STRIDE_TILE_F32 + k]; - } - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - VKQ[j0/nwarps][i0/WARP_SIZE].x += V_k[i0/WARP_SIZE].x*KQ_k[j0/nwarps]; - VKQ[j0/nwarps][i0/WARP_SIZE].y += V_k[i0/WARP_SIZE].y*KQ_k[j0/nwarps]; - } - } - } - - __syncthreads(); - } - -#pragma unroll - for (int j_VKQ_0 = 0; j_VKQ_0 < ncols; j_VKQ_0 += nwarps) { - const int j_VKQ = j_VKQ_0 + threadIdx.y; - - if (ic0 + j_VKQ >= ne01) { - return; - } - - float kqsum_j = kqsum[j_VKQ_0/nwarps]; - kqsum_j = warp_reduce_sum(kqsum_j); - -#pragma unroll - for (int i00 = 0; i00 < D; i00 += 2*WARP_SIZE) { - const int i0 = i00 + 2*threadIdx.x; - - float2 dst_val = VKQ[j_VKQ_0/nwarps][i0/(2*WARP_SIZE)]; - if (gridDim.y == 1) { - dst_val.x /= kqsum_j; - dst_val.y /= kqsum_j; - } - const int j_dst = (ic0 + j_VKQ)*gridDim.y + blockIdx.y; - dst[j_dst*D*gridDim.z + D*blockIdx.z + i0 + 0] = dst_val.x; - dst[j_dst*D*gridDim.z + D*blockIdx.z + i0 + 1] = dst_val.y; - } - - if (gridDim.y != 1 && threadIdx.x == 0) { - dst_meta[((ic0 + j_VKQ)*gridDim.z + blockIdx.z) * gridDim.y + blockIdx.y] = make_float2(kqmax[j_VKQ_0/nwarps], kqsum_j); - } - } -#else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); - GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); - GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); - GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); - GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); - GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; -#endif // FLASH_ATTN_AVAILABLE -} - -template -void launch_fattn_tile_f32_64_128(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * Q = dst->src[0]; - switch (Q->ne[0]) { - case 64: { - constexpr int D = 64; - constexpr int nwarps = 8; - constexpr size_t nbytes_shared = 0; - fattn_kernel_t fattn_kernel = flash_attn_tile_ext_f32; - launch_fattn - (ctx, dst, fattn_kernel, nwarps, nbytes_shared, FATTN_KQ_STRIDE_TILE_F32, true, true, false); - } break; - case 128: { - constexpr int D = 128; - constexpr int nwarps = 8; - constexpr size_t nbytes_shared = 0; - fattn_kernel_t fattn_kernel = flash_attn_tile_ext_f32; - launch_fattn - (ctx, dst, fattn_kernel, nwarps, nbytes_shared, FATTN_KQ_STRIDE_TILE_F32, true, true, false); - } break; - default: { - GGML_ABORT("FlashAttention without tensor cores only supports head sizes 64 and 128."); - } break; - } -} - -void ggml_cuda_flash_attn_ext_tile_f32(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - - float logit_softcap; - memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); - - if (Q->ne[1] <= 16) { - constexpr int cols_per_block = 16; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - launch_fattn_tile_f32_64_128(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - launch_fattn_tile_f32_64_128(ctx, dst); - } - return; - } - - constexpr int cols_per_block = 32; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - launch_fattn_tile_f32_64_128(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - launch_fattn_tile_f32_64_128(ctx, dst); - } -} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile-f32.cuh 1970-01-01 00:00:00.000000000 +0000 @@ -1,3 +0,0 @@ -#include "common.cuh" - -void ggml_cuda_flash_attn_ext_tile_f32(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cu 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,755 @@ +#include "common.cuh" +#include "fattn-common.cuh" +#include "fattn-tile.cuh" + +// kq_stride == number of KQ rows to process per iteration +// kq_nbatch == number of K columns to load in parallel for KQ calculation + +static int fattn_tile_get_kq_stride_host(const int D, const int ncols, const int cc, const int warp_size) { + if (GGML_CUDA_CC_IS_AMD(cc)) { + if (GGML_CUDA_CC_IS_RDNA(cc)) { + switch (D) { + case 64: + return 128; + case 128: + case 256: + return ncols <= 16 ? 128 : 64; + default: + GGML_ABORT("fatal error"); + return -1; + } + } + switch (D) { + case 64: + return ncols == 32 ? 128 : 64; + case 128: + return ncols == 32 ? 64 : 32; + case 256: + return 32; + default: + GGML_ABORT("fatal error"); + return -1; + } + } + if (fast_fp16_available(cc)) { + switch (D) { + case 64: + case 128: + case 256: + return ncols <= 16 ? 128 : 64; + default: + GGML_ABORT("fatal error"); + return -1; + } + } + switch (D) { + case 64: + return ncols <= 16 ? 128 : 64; + case 128: + return ncols <= 16 ? 64 : 32; + case 256: + return 32; + default: + GGML_ABORT("fatal error"); + return -1; + } + GGML_UNUSED(warp_size); +} + +static constexpr __device__ int fattn_tile_get_kq_stride_device(int D, int ncols, int warp_size) { +#ifdef GGML_USE_HIP +#ifdef RDNA + switch (D) { + case 64: + return 128; + case 128: + case 256: + return ncols <= 16 ? 128 : 64; + default: + return -1; + } +#else + switch (D) { + case 64: + return ncols == 32 ? 128 : 64; + case 128: + return ncols == 32 ? 64 : 32; + case 256: + return 32; + default: + return -1; + } +#endif // RDNA +#else +#ifdef FAST_FP16_AVAILABLE + switch (D) { + case 64: + case 128: + case 256: + return ncols <= 16 ? 128 : 64; + default: + return -1; + } +#else + switch (D) { + case 64: + return ncols <= 16 ? 128 : 64; + case 128: + return ncols <= 16 ? 64 : 32; + case 256: + return 32; + default: + return -1; + } +#endif // FAST_FP16_AVAILABLE +#endif // GGML_USE_HIP + GGML_UNUSED_VARS(ncols, warp_size); +} + +static constexpr __device__ int fattn_tile_get_kq_nbatch_device(int D, int ncols, int warp_size) { +#ifdef GGML_USE_HIP + switch (D) { + case 64: + return 64; + case 128: + case 256: + return 128; + default: + return -1; + } +#else +#ifdef FAST_FP16_AVAILABLE + switch (D) { + case 64: + return 64; + case 128: + case 256: + return 128; + default: + return -1; + } +#else + switch (D) { + case 64: + return 64; + case 128: + return 128; + case 256: + return ncols <= 16 ? 128 : 64; + default: + return -1; + } +#endif // FAST_FP16_AVAILABLE +#endif // GGML_USE_HIP + GGML_UNUSED_VARS(ncols, warp_size); +} + +static int fattn_tile_get_nthreads_host(const int cc, const int ncols) { + return 256; + GGML_UNUSED_VARS(cc, ncols); +} + +static constexpr __device__ int fattn_tile_get_nthreads_device(int ncols) { + return 256; + GGML_UNUSED(ncols); +} + +static constexpr __device__ int fattn_tile_get_occupancy_device(int ncols) { +#ifdef RDNA + return 3; +#else + return ncols <= 16 ? 3 : 2; +#endif // RDNA + GGML_UNUSED(ncols); +} + +template // D == head size +__launch_bounds__(fattn_tile_get_nthreads_device(ncols), fattn_tile_get_occupancy_device(ncols)) +static __global__ void flash_attn_tile( + const char * __restrict__ Q, + const char * __restrict__ K, + const char * __restrict__ V, + const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, + float * __restrict__ dst, + float2 * __restrict__ dst_meta, + const float scale, + const float max_bias, + const float m0, + const float m1, + const uint32_t n_head_log2, + const float logit_softcap, + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { +#ifdef FLASH_ATTN_AVAILABLE + + // Skip unused kernel variants for faster compilation: +#ifdef FP16_MMA_AVAILABLE + NO_DEVICE_CODE; + return; +#endif // FP16_MMA_AVAILABLE + + if (use_logit_softcap && !(D == 128 || D == 256)) { + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); + NO_DEVICE_CODE; + return; + } + + constexpr int warp_size = 32; + constexpr int nwarps = fattn_tile_get_nthreads_device(ncols) / warp_size; + constexpr int kq_stride = fattn_tile_get_kq_stride_device(D, ncols, warp_size); + static_assert(kq_stride % warp_size == 0, "kq_stride not divisable by warp_size."); + constexpr int kq_nbatch = fattn_tile_get_kq_nbatch_device(D, ncols, warp_size); + static_assert(kq_nbatch % (2*warp_size) == 0, "bad kq_nbatch"); + + // In this kernel Q, K, V are matrices while i, j, k are matrix indices. + + const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. + + const int sequence = blockIdx.z / ne02; + const int head = blockIdx.z - sequence*ne02; + const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. + const float * Q_f = (const float *) (Q + nb03* sequence + nb02* head + nb01*ic0); + const half2 * K_h2 = (const half2 *) (K + nb13* sequence + nb12*(head / gqa_ratio)); + const half2 * V_h2 = (const half2 *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const float * sinksf = (const float *) (sinks); + + const int stride_KV2 = nb11 / sizeof(half2); + + const float slope = get_alibi_slope(max_bias, head, n_head_log2, m0, m1); + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + + constexpr int cpw = ncols/nwarps; // cols per warp + + // softmax_iter_j == number of KQ columns for which to calculate softmax in parallel. + // KQ is originall 2D but uses a Z-shaped memory pattern for larger reads/writes. +#ifdef FAST_FP16_AVAILABLE + constexpr int softmax_iter_j = cpw < 2*cpy_ne ? cpw : 2*cpy_ne; + + __shared__ half KQ[ncols/softmax_iter_j][kq_stride][softmax_iter_j]; + __shared__ half2 Q_tmp[ncols][D/2]; + __shared__ half2 KV_tmp[kq_stride * (kq_nbatch/2 + cpy_ne)]; // Padded to avoid memory bank conflicts. + half2 VKQ[cpw][D/(2*warp_size)] = {{{0.0f, 0.0f}}}; +#else + constexpr int softmax_iter_j = cpw < 1*cpy_ne ? cpw : 1*cpy_ne; + + __shared__ float KQ[ncols/softmax_iter_j][kq_stride][softmax_iter_j]; + __shared__ float Q_tmp[ncols][D]; + __shared__ float KV_tmp[kq_stride * (kq_nbatch + cpy_ne)]; // Padded to avoid memory bank conflicts. + float2 VKQ[cpw][D/(2*warp_size)] = {{{0.0f, 0.0f}}}; +#endif // FAST_FP16_AVAILABLE + static_assert(cpw % softmax_iter_j == 0, "bad softmax_iter_j"); + + float KQ_max[cpw]; +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + KQ_max[j0/nwarps] = -FLT_MAX/2.0f; + } + float KQ_sum[cpw] = {0.0f}; + + // Load Q data, convert to FP16 if fast. +#pragma unroll + for (int j0 = 0; j0 < cpw; ++j0) { + const int j = j0 + threadIdx.y*cpw; + + constexpr int cpy_ne_D = cpy_ne < D/warp_size ? cpy_ne : D/warp_size; + +#pragma unroll + for (int i0 = 0; i0 < D; i0 += warp_size*cpy_ne_D) { + float tmp_f[cpy_ne_D] = {0.0f}; + if (ic0 + j < ne01) { + ggml_cuda_memcpy_1(tmp_f, &Q_f[j*(nb01/sizeof(float)) + i0 + threadIdx.x*cpy_ne_D]); + } + +#pragma unroll + for (int i1 = 0; i1 < cpy_ne_D; ++i1) { + tmp_f[i1] *= scale; + } + +#ifdef FAST_FP16_AVAILABLE + half2 tmp_h2[cpy_ne_D/2]; +#pragma unroll + for (int i1 = 0; i1 < cpy_ne_D; i1 += 2) { + tmp_h2[i1/2] = make_half2(tmp_f[i1 + 0], tmp_f[i1 + 1]); + } + ggml_cuda_memcpy_1(&Q_tmp[j][i0/2 + threadIdx.x*(cpy_ne_D/2)], tmp_h2); +#else + ggml_cuda_memcpy_1 (&Q_tmp[j][i0 + threadIdx.x* cpy_ne_D], tmp_f); +#endif // FAST_FP16_AVAILABLE + } + } + + __syncthreads(); + + // Main loop over KV cache: + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + for (int k_VKQ_0 = blockIdx.y*kq_stride; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*kq_stride) { + // Calculate KQ tile and keep track of new maximum KQ values: + + float KQ_max_new[cpw]; +#pragma unroll + for (int j = 0; j < cpw; ++j) { + KQ_max_new[j] = KQ_max[j]; + } + + float KQ_acc[kq_stride/warp_size][cpw] = {{0.0f}}; // Accumulators for KQ matrix multiplication. + + // KQ = K @ Q matrix multiplication: +#pragma unroll + for (int k_KQ_0 = 0; k_KQ_0 < D; k_KQ_0 += kq_nbatch) { +#pragma unroll + for (int i_KQ_0 = 0; i_KQ_0 < kq_stride; i_KQ_0 += nwarps) { + const int i_KQ = i_KQ_0 + threadIdx.y; + +#ifdef FAST_FP16_AVAILABLE + constexpr int cpy_ne_kqnb = cpy_ne < kq_nbatch/(2*warp_size) ? cpy_ne : kq_nbatch/(2*warp_size); +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < kq_nbatch/2; k_KQ_1 += warp_size*cpy_ne_kqnb) { + ggml_cuda_memcpy_1( + &KV_tmp[i_KQ*(kq_nbatch/2 + cpy_ne) + k_KQ_1 + threadIdx.x*cpy_ne_kqnb], + &K_h2[int64_t(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ_0/2 + k_KQ_1 + threadIdx.x*cpy_ne_kqnb]); + } +#else + constexpr int cpy_ne_kqnb = cpy_ne < kq_nbatch/warp_size ? cpy_ne : kq_nbatch/warp_size; +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < kq_nbatch; k_KQ_1 += warp_size*cpy_ne_kqnb) { + half2 tmp_h2[cpy_ne_kqnb/2]; + ggml_cuda_memcpy_1( + tmp_h2, &K_h2[int64_t(k_VKQ_0 + i_KQ)*stride_KV2 + k_KQ_0/2 + k_KQ_1/2 + threadIdx.x*(cpy_ne_kqnb/2)]); + + float2 tmp_f2[cpy_ne_kqnb/2]; +#pragma unroll + for (int k_KQ_2 = 0; k_KQ_2 < cpy_ne_kqnb/2; ++k_KQ_2) { + tmp_f2[k_KQ_2] = __half22float2(tmp_h2[k_KQ_2]); + } + ggml_cuda_memcpy_1( + &KV_tmp[i_KQ*(kq_nbatch + cpy_ne) + k_KQ_1 + threadIdx.x*cpy_ne_kqnb], tmp_f2); + } +#endif // FAST_FP16_AVAILABLE + } + + __syncthreads(); + +#ifdef FAST_FP16_AVAILABLE +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < kq_nbatch/2; k_KQ_1 += cpy_ne) { + half2 K_k[kq_stride/warp_size][cpy_ne]; + half2 Q_k[cpw][cpy_ne]; +#else +#pragma unroll + for (int k_KQ_1 = 0; k_KQ_1 < kq_nbatch; k_KQ_1 += cpy_ne) { + float K_k[kq_stride/warp_size][cpy_ne]; + float Q_k[cpw][cpy_ne]; +#endif // FAST_FP16_AVAILABLE + +#pragma unroll + for (int i_KQ_0 = 0; i_KQ_0 < kq_stride; i_KQ_0 += warp_size) { + const int i_KQ = i_KQ_0 + threadIdx.x; + +#ifdef FAST_FP16_AVAILABLE + ggml_cuda_memcpy_1(&K_k[i_KQ_0/warp_size], &KV_tmp[i_KQ*(kq_nbatch/2 + cpy_ne) + k_KQ_1]); +#else + ggml_cuda_memcpy_1(&K_k[i_KQ_0/warp_size], &KV_tmp[i_KQ*(kq_nbatch + cpy_ne) + k_KQ_1]); +#endif // FAST_FP16_AVAILABLE + } +#pragma unroll + for (int j_KQ_0 = 0; j_KQ_0 < cpw; ++j_KQ_0) { + const int j_KQ = j_KQ_0 + threadIdx.y*cpw; + +#ifdef FAST_FP16_AVAILABLE + ggml_cuda_memcpy_1(&Q_k[j_KQ_0], &Q_tmp[j_KQ][k_KQ_0/2 + k_KQ_1]); +#else + ggml_cuda_memcpy_1(&Q_k[j_KQ_0], &Q_tmp[j_KQ][k_KQ_0 + k_KQ_1]); +#endif // FAST_FP16_AVAILABLE + } + +#pragma unroll + for (int i_KQ_0 = 0; i_KQ_0 < kq_stride; i_KQ_0 += warp_size) { +#pragma unroll + for (int j_KQ_0 = 0; j_KQ_0 < cpw; ++j_KQ_0) { +#pragma unroll + for (int k = 0; k < cpy_ne; ++k) { + ggml_cuda_mad(KQ_acc[i_KQ_0/warp_size][j_KQ_0], K_k[i_KQ_0/warp_size][k], Q_k[j_KQ_0][k]); + } + } + } + } + + if (k_KQ_0 + kq_nbatch < D) { + __syncthreads(); // Sync not needed on last iteration. + } + } + + // Apply logit softcap, mask, update KQ_max: +#pragma unroll + for (int i_KQ_0 = 0; i_KQ_0 < kq_stride; i_KQ_0 += warp_size) { + const int i_KQ = i_KQ_0 + threadIdx.x; + +#pragma unroll + for (int j_KQ_0 = 0; j_KQ_0 < cpw; ++j_KQ_0) { + const int j_KQ = j_KQ_0 + threadIdx.y*cpw; + + if (use_logit_softcap) { + KQ_acc[i_KQ_0/warp_size][j_KQ_0] = logit_softcap * tanhf(KQ_acc[i_KQ_0/warp_size][j_KQ_0]); + } + + KQ_acc[i_KQ_0/warp_size][j_KQ_0] += mask ? slope*__half2float(maskh[j_KQ*ne11 + k_VKQ_0 + i_KQ]) : 0.0f; + + KQ_max_new[j_KQ_0] = fmaxf(KQ_max_new[j_KQ_0], KQ_acc[i_KQ_0/warp_size][j_KQ_0]); + } + } + + __syncthreads(); + + // Calculate KQ softmax, write to shared KQ buffer, re-scale VKQ accumulators: +#pragma unroll + for (int j0 = 0; j0 < cpw; j0 += softmax_iter_j) { +#ifdef FAST_FP16_AVAILABLE + half tmp[kq_stride/warp_size][softmax_iter_j]; +#else + float tmp[kq_stride/warp_size][softmax_iter_j]; +#endif // FAST_FP16_AVAILABLE + +#pragma unroll + for (int j1 = 0; j1 < softmax_iter_j; ++j1) { + KQ_max_new[j0+j1] = warp_reduce_max(KQ_max_new[j0+j1]); + const float KQ_max_scale = expf(KQ_max[j0+j1] - KQ_max_new[j0+j1]); + KQ_max[j0+j1] = KQ_max_new[j0+j1]; + + float KQ_sum_add = 0.0f; +#pragma unroll + for (int i0 = 0; i0 < kq_stride; i0 += warp_size) { + const float val = expf(KQ_acc[i0/warp_size][j0+j1] - KQ_max[j0+j1]); + KQ_sum_add += val; + tmp[i0/warp_size][j1] = val; + } + KQ_sum[j0+j1] = KQ_sum[j0+j1]*KQ_max_scale + KQ_sum_add; + +#ifdef FAST_FP16_AVAILABLE + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + VKQ[j0+j1][i0/warp_size] *= KQ_max_scale_h2; + } +#else +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + VKQ[j0+j1][i0/warp_size].x *= KQ_max_scale; + VKQ[j0+j1][i0/warp_size].y *= KQ_max_scale; + } +#endif // FAST_FP16_AVAILABLE + } + +#pragma unroll + for (int i0 = 0; i0 < kq_stride; i0 += warp_size) { + const int i = i0 + threadIdx.x; + + ggml_cuda_memcpy_1( + KQ[j0/softmax_iter_j + threadIdx.y*(cpw/softmax_iter_j)][i], tmp[i0/warp_size]); + } + } + + // VKQ = V @ KQ matrix multiplication: + constexpr int V_cols_per_iter = kq_stride*kq_nbatch / D; // Number of V columns that fit in SRAM for K. + static_assert(kq_stride % V_cols_per_iter == 0, "bad V_cols_per_iter"); +#pragma unroll + for (int k0 = 0; k0 < kq_stride; k0 += V_cols_per_iter) { +#pragma unroll + for (int k1 = 0; k1 < V_cols_per_iter; k1 += nwarps) { + const int k_tile = k1 + threadIdx.y; + +#ifdef FAST_FP16_AVAILABLE + constexpr int cpy_ne_D = cpy_ne < D/(2*warp_size) ? cpy_ne : D/(2*warp_size); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size*cpy_ne_D) { + ggml_cuda_memcpy_1( + &KV_tmp[k_tile*(D/2) + i0 + threadIdx.x*cpy_ne_D], + &V_h2[int64_t(k_VKQ_0 + k0 + k_tile)*stride_KV2 + i0 + threadIdx.x*cpy_ne_D]); + } +#else + constexpr int cpy_ne_D = cpy_ne < D/warp_size ? cpy_ne : D/warp_size; +#pragma unroll + for (int i0 = 0; i0 < D; i0 += warp_size*cpy_ne_D) { + half2 tmp_h2[cpy_ne_D/2]; + ggml_cuda_memcpy_1( + tmp_h2, &V_h2[int64_t(k_VKQ_0 + k0 + k_tile)*stride_KV2 + i0/2 + threadIdx.x*(cpy_ne_D/2)]); + + float2 tmp_f2[cpy_ne_D/2]; +#pragma unroll + for (int i1 = 0; i1 < cpy_ne_D/2; ++i1) { + tmp_f2[i1] = __half22float2(tmp_h2[i1]); + } + ggml_cuda_memcpy_1( + &KV_tmp[k_tile*D + i0 + threadIdx.x*cpy_ne_D], tmp_f2); + } +#endif // FAST_FP16_AVAILABLE + } + + __syncthreads(); + +#ifdef FAST_FP16_AVAILABLE +#pragma unroll + for (int k1 = 0; k1 < V_cols_per_iter; ++k1) { + half2 V_k[(D/2)/warp_size]; + half2 KQ_k[cpw]; + + constexpr int cpy_ne_D = cpy_ne/2 < (D/2)/warp_size ? cpy_ne/2 : (D/2)/warp_size; +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size*cpy_ne_D) { + ggml_cuda_memcpy_1(&V_k[i0/warp_size], &KV_tmp[k1*(D/2) + i0 + threadIdx.x*cpy_ne_D]); + } +#pragma unroll + for (int j0 = 0; j0 < cpw; j0 += softmax_iter_j) { + const int j = j0/softmax_iter_j + threadIdx.y*(cpw/softmax_iter_j); + + half tmp[softmax_iter_j]; + ggml_cuda_memcpy_1( + &tmp, KQ[j][k0 + k1]); +#pragma unroll + for (int j1 = 0; j1 < softmax_iter_j; ++j1) { + KQ_k[j0+j1] = __half2half2(tmp[j1]); + } + } + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { +#pragma unroll + for (int j0 = 0; j0 < cpw; ++j0) { + VKQ[j0][i0/warp_size] += V_k[i0/warp_size]*KQ_k[j0]; + } + } + } +#else +#pragma unroll + for (int k1 = 0; k1 < V_cols_per_iter; ++k1) { + float2 V_k[(D/2)/warp_size]; + float KQ_k[cpw]; + + constexpr int cpy_ne_D = cpy_ne < D/warp_size ? cpy_ne : D/warp_size; +#pragma unroll + for (int i0 = 0; i0 < D; i0 += warp_size*cpy_ne_D) { + ggml_cuda_memcpy_1(&V_k[i0/(2*warp_size)], &KV_tmp[k1*D + i0 + threadIdx.x*cpy_ne_D]); + } +#pragma unroll + for (int j0 = 0; j0 < cpw; j0 += softmax_iter_j) { + const int j = j0/softmax_iter_j + threadIdx.y*(cpw/softmax_iter_j); + + ggml_cuda_memcpy_1( + &KQ_k[j0], KQ[j][k0 + k1]); + } + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { +#pragma unroll + for (int j0 = 0; j0 < cpw; ++j0) { + VKQ[j0][i0/warp_size].x += V_k[i0/warp_size].x*KQ_k[j0]; + VKQ[j0][i0/warp_size].y += V_k[i0/warp_size].y*KQ_k[j0]; + } + } + } +#endif // FAST_FP16_AVAILABLE + + __syncthreads(); + } + } + + + // Attention sink: adjust running max and sum once per head + if (sinksf && blockIdx.y == 0) { + const float sink = sinksf[head]; + +#pragma unroll + for (int j0 = 0; j0 < cpw; ++j0) { + float KQ_max_new_j = fmaxf(KQ_max[j0], sink); + KQ_max_new_j = warp_reduce_max(KQ_max_new_j); + + const float KQ_max_scale = expf(KQ_max[j0] - KQ_max_new_j); + KQ_max[j0] = KQ_max_new_j; + + const float val = expf(sink - KQ_max[j0]); + KQ_sum[j0] = KQ_sum[j0] * KQ_max_scale; + if (threadIdx.x == 0) { + KQ_sum[j0] += val; + } + +#ifdef FAST_FP16_AVAILABLE + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + VKQ[j0][i0/warp_size] *= KQ_max_scale_h2; + } +#else +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + VKQ[j0][i0/warp_size].x *= KQ_max_scale; + VKQ[j0][i0/warp_size].y *= KQ_max_scale; + } +#endif // FAST_FP16_AVAILABLE + } + } + +#pragma unroll + for (int j_VKQ_0 = 0; j_VKQ_0 < cpw; ++j_VKQ_0) { + KQ_sum[j_VKQ_0] = warp_reduce_sum(KQ_sum[j_VKQ_0]); + } + if (gridDim.y == 1) { +#pragma unroll + for (int j_VKQ_0 = 0; j_VKQ_0 < cpw; ++j_VKQ_0) { +#ifdef FAST_FP16_AVAILABLE + const half2 KQ_sum_j_inv = make_half2(1.0f/KQ_sum[j_VKQ_0], 1.0f/KQ_sum[j_VKQ_0]); +#pragma unroll + for (int i = 0; i < (D/2)/warp_size; ++i) { + VKQ[j_VKQ_0][i] *= KQ_sum_j_inv; + } +#else + const float KQ_sum_j_inv = 1.0f/KQ_sum[j_VKQ_0]; +#pragma unroll + for (int i = 0; i < (D/2)/warp_size; ++i) { + VKQ[j_VKQ_0][i].x *= KQ_sum_j_inv; + VKQ[j_VKQ_0][i].y *= KQ_sum_j_inv; + } +#endif // FAST_FP16_AVAILABLE + } + } + + // Write back results: +#pragma unroll + for (int j_VKQ_0 = 0; j_VKQ_0 < cpw; ++j_VKQ_0) { + const int j_VKQ = j_VKQ_0 + threadIdx.y*cpw; + + if (ic0 + j_VKQ >= ne01) { + return; + } + + const int j_dst_unrolled = ((sequence*ne01 + ic0 + j_VKQ)*ne02 + head)*gridDim.y + blockIdx.y; + +#ifdef FAST_FP16_AVAILABLE + constexpr int cpy_ne_D = cpy_ne/2 < (D/2)/warp_size ? cpy_ne/2 : (D/2)/warp_size; +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size*cpy_ne_D) { + float2 tmp[cpy_ne_D]; +#pragma unroll + for (int i1 = 0; i1 < cpy_ne_D; ++i1) { + tmp[i1] = __half22float2(VKQ[j_VKQ_0][i0/warp_size + i1]); + } + ggml_cuda_memcpy_1(&dst[j_dst_unrolled*D + 2*i0 + threadIdx.x*(2*cpy_ne_D)], tmp); + } +#else + constexpr int cpy_ne_D = cpy_ne < D/warp_size ? cpy_ne : D/warp_size; +#pragma unroll + for (int i0 = 0; i0 < D; i0 += warp_size*cpy_ne_D) { + ggml_cuda_memcpy_1( + &dst[j_dst_unrolled*D + i0 + threadIdx.x*cpy_ne_D], &VKQ[j_VKQ_0][i0/(2*warp_size)]); + } +#endif // FAST_FP16_AVAILABLE + + if (gridDim.y != 1 && threadIdx.x == 0) { + dst_meta[j_dst_unrolled] = make_float2(KQ_max[j_VKQ_0], KQ_sum[j_VKQ_0]); + } + } +#else + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); + NO_DEVICE_CODE; +#endif // FLASH_ATTN_AVAILABLE +} + +template +static void launch_fattn_tile_switch_ncols(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * Q = dst->src[0]; + + const int id = ggml_cuda_get_device(); + const int cc = ggml_cuda_info().devices[id].cc; + const int warp_size = 32; + + constexpr size_t nbytes_shared = 0; + +#ifdef GGML_USE_HIP + if constexpr (D <= 128) { + if (Q->ne[1] > 32) { + constexpr int cols_per_block = 64; + const int nwarps = fattn_tile_get_nthreads_host(cc, cols_per_block) / warp_size; + fattn_kernel_t fattn_kernel = flash_attn_tile; + const int kq_stride = fattn_tile_get_kq_stride_host(D, cols_per_block, cc, warp_size); + launch_fattn + (ctx, dst, fattn_kernel, nwarps, nbytes_shared, kq_stride, true, true, false, warp_size); + return; + } + } +#endif // GGML_USE_HIP + + if (Q->ne[1] > 16) { + constexpr int cols_per_block = 32; + const int nwarps = fattn_tile_get_nthreads_host(cc, cols_per_block) / warp_size; + fattn_kernel_t fattn_kernel = flash_attn_tile; + const int kq_stride = fattn_tile_get_kq_stride_host(D, cols_per_block, cc, warp_size); + launch_fattn + (ctx, dst, fattn_kernel, nwarps, nbytes_shared, kq_stride, true, true, false, warp_size); + return; + } + + constexpr int cols_per_block = 16; + const int nwarps = fattn_tile_get_nthreads_host(cc, cols_per_block) / warp_size; + fattn_kernel_t fattn_kernel = flash_attn_tile; + const int kq_stride = fattn_tile_get_kq_stride_host(D, cols_per_block, cc, warp_size); + launch_fattn + (ctx, dst, fattn_kernel, nwarps, nbytes_shared, kq_stride, true, true, false, warp_size); +} + +template +static void launch_fattn_tile_switch_head_size(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * Q = dst->src[0]; + switch (Q->ne[0]) { + case 64: { + launch_fattn_tile_switch_ncols< 64, use_logit_softcap>(ctx, dst); + } break; + case 128: { + launch_fattn_tile_switch_ncols<128, use_logit_softcap>(ctx, dst); + } break; + case 256: { + launch_fattn_tile_switch_ncols<256, use_logit_softcap>(ctx, dst); + } break; + default: { + GGML_ABORT("Unsupported head size"); + } break; + } +} + +void ggml_cuda_flash_attn_ext_tile(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * KQV = dst; + + float logit_softcap; + memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); + + if (logit_softcap == 0.0f) { + constexpr bool use_logit_softcap = false; + launch_fattn_tile_switch_head_size(ctx, dst); + } else { + constexpr bool use_logit_softcap = true; + launch_fattn_tile_switch_head_size(ctx, dst); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-tile.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,3 @@ +#include "common.cuh" + +void ggml_cuda_flash_attn_ext_tile(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f16.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f16.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f16.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f16.cuh 1970-01-01 00:00:00.000000000 +0000 @@ -1,484 +0,0 @@ -#include "common.cuh" -#include "fattn-common.cuh" - -template // D == head size -#ifndef GGML_USE_HIP -__launch_bounds__(D, 1) -#endif // GGML_USE_HIP -static __global__ void flash_attn_vec_ext_f16( - const char * __restrict__ Q, - const char * __restrict__ K, - const char * __restrict__ V, - const char * __restrict__ mask, - float * __restrict__ dst, - float2 * __restrict__ dst_meta, - const float scale, - const float max_bias, - const float m0, - const float m1, - const uint32_t n_head_log2, - const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#if defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) - - // Skip unused kernel variants for faster compilation: - if (use_logit_softcap && !(D == 128 || D == 256)) { - NO_DEVICE_CODE; - return; - } -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) - if (ncols > 1) { - NO_DEVICE_CODE; - return; - } -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) - - //In this kernel Q, K, V are matrices while i, j, k are matrix indices. - - constexpr vec_dot_KQ_f16_t vec_dot_KQ = get_vec_dot_KQ_f16(type_K); - constexpr bool Q_q8_1 = type_K != GGML_TYPE_F16; - constexpr dequantize_1_f16_t dequantize_1_v = get_dequantize_1_f16(type_V); - - const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. - - const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - Q += nb02* blockIdx.z + nb01*ic0; - K += nb12*(blockIdx.z / gqa_ratio); - V += nb22*(blockIdx.z / gqa_ratio); - - const half * maskh = (const half *) (mask + nb32*(blockIdx.z % ne32) + nb31*ic0); - - const float slopef = get_alibi_slope(max_bias, blockIdx.z, n_head_log2, m0, m1); - const half slopeh = __float2half(slopef); - - static_assert(D % (2*WARP_SIZE) == 0, "D not divisible by 2*WARP_SIZE == 64."); - constexpr int nwarps = D / WARP_SIZE; - const int tid = WARP_SIZE*threadIdx.y + threadIdx.x; - __builtin_assume(tid < D); - - __shared__ half KQ[ncols*D]; - half2 * KQ2 = (half2 *) KQ; - - half kqmax[ncols]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqmax[j] = -HALF_MAX_HALF; - } - half kqsum[ncols] = {0.0f}; - - __shared__ half kqmax_shared[ncols][WARP_SIZE]; - __shared__ half kqsum_shared[ncols][WARP_SIZE]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - if (threadIdx.y == 0) { - kqmax_shared[j][threadIdx.x] = -HALF_MAX_HALF; - kqsum_shared[j][threadIdx.x] = 0.0f; - } - } - - __shared__ half maskh_shared[ncols*D]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - maskh_shared[j*D + tid] = 0.0f; - } - - __syncthreads(); - - // Convert Q to half2 (f16 K) or q8_1 (quantized K) and store in registers: - half2 Q_h2[ncols][D/(2*WARP_SIZE)]; - int Q_i32[ncols][D/(sizeof(int)*QK8_1) == 0 ? 1 : D/(sizeof(int)*QK8_1)]; - half2 Q_ds[ncols][D/QK8_1 == 0 ? 1 : D/QK8_1]; - if (Q_q8_1) { -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - if (j0 + nwarps > ncols && j >= ncols) { - break; - } - - // Reuse KQ as temporary storage for converting Q to q8_1: - int * tmp_q_i32 = (int *) &KQ[j*D]; - half2 * tmp_q_ds = (half2 *) (tmp_q_i32 + D/sizeof(int)); - - // Set memory to zero if out of bounds: - if (ncols > 2 && ic0 + j >= ne01) { -#pragma unroll - for (int i0 = 0; i0 < D/sizeof(int); i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - tmp_q_i32[i] = 0; - } - if (threadIdx.x < D/QK8_1) { - tmp_q_ds[threadIdx.x] = make_half2(0.0f, 0.0f); - } - continue; - } - - const float * Q_f = (const float *) (Q + j*nb01); -#pragma unroll - for (int i0 = 0; i0 < D/sizeof(int); i0 += WARP_SIZE) { - quantize_q8_1_to_shared(Q_f + 4*i0, scale, tmp_q_i32, tmp_q_ds); - } - } - - __syncthreads(); - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - int * tmp_q_i32 = (int *) &KQ[j*D]; - half2 * tmp_q_ds = (half2 *) (tmp_q_i32 + D/sizeof(int)); - -#pragma unroll - for (int i0 = 0; i0 < D/sizeof(int); i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - Q_i32[j][i0/WARP_SIZE] = tmp_q_i32[i]; - Q_ds[j][i0/WARP_SIZE] = tmp_q_ds[i/QI8_1]; - } - } - - __syncthreads(); - } else { -#pragma unroll - for (int j = 0; j < ncols; ++j) { - const float2 * Q_f2_j = (const float2 *) (Q + j*nb01); - -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const float2 tmp = ncols <= 2 || ic0 + j < ne01 ? Q_f2_j[i] : make_float2(0.0f, 0.0f); - Q_h2[j][i0/WARP_SIZE] = make_half2(scale, scale) * make_half2(tmp.x, tmp.y); - } - } - } - - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - KQ[j*D + tid] = -HALF_MAX_HALF; - } - __syncthreads(); - - half2 VKQ[ncols] = {{0.0f, 0.0f}}; - - for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*D) { - // Calculate KQ tile and keep track of new maximum KQ values: - - if (mask) { -#pragma unroll - for (int j = 0; j < ncols; ++j) { - maskh_shared[j*D + tid] = slopeh*maskh[j*ne11 + k_VKQ_0 + tid]; - } - - __syncthreads(); - - // When using multiple parallel sequences in llama.cpp, some KV slices can be fully masked out. - // In such cases, skip the KV slice. - // On AMD __all_sync would not work correctly because it assumes a warp size of 64. -#ifndef GGML_USE_HIP - bool skip = true; -#pragma unroll - for (int j = 0; j < ncols; ++j) { -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - const float2 tmp = __half22float2(((const half2 *) maskh_shared)[j*(D/2) + i]); - skip = skip && isinf(tmp.x) && isinf(tmp.y); - } - } - if (__all_sync(0xFFFFFFFF, skip)) { - __syncthreads(); - continue; - } -#endif // GGML_USE_HIP - } - - // For unknown reasons using a half array of size 1 for kqmax_new causes a performance regression, - // see https://github.com/ggerganov/llama.cpp/pull/7061 . - // Therefore this variable is defined twice but only used once (so that the compiler can optimize out the unused variable). - half kqmax_new = kqmax[0]; - half kqmax_new_arr[ncols]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqmax_new_arr[j] = kqmax[j]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < D; i_KQ_0 += nwarps) { - const int i_KQ = i_KQ_0 + threadIdx.y; - - if ((i_KQ_0 + nwarps > D && i_KQ >= D) || (FATTN_KQ_STRIDE % D != 0 && k_VKQ_0 + i_KQ >= ne11)) { - break; - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - half sum = vec_dot_KQ(K + (k_VKQ_0 + i_KQ)*nb11, Q_h2[j], Q_i32[j], Q_ds[j]); - sum = warp_reduce_sum((float)sum); - - if (use_logit_softcap) { - sum = logit_softcap*tanhf(sum); - } - - sum += maskh_shared[j*D + i_KQ]; - - if (ncols == 1) { - kqmax_new = ggml_cuda_hmax(kqmax_new, sum); - } else { - kqmax_new_arr[j] = ggml_cuda_hmax(kqmax_new_arr[j], sum); - } - - if (threadIdx.x == 0) { - KQ[j*D + i_KQ] = sum; - } - } - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - half kqmax_new_j = ncols == 1 ? kqmax_new : kqmax_new_arr[j]; - - if (threadIdx.x == 0) { - kqmax_shared[j][threadIdx.y] = kqmax_new_j; - } - } - - __syncthreads(); - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - half kqmax_new_j = kqmax_shared[j][threadIdx.x]; - kqmax_new_j = warp_reduce_max(kqmax_new_j); - - const half KQ_max_scale = hexp(kqmax[j] - kqmax_new_j); - kqmax[j] = kqmax_new_j; - - const half val = hexp(KQ[j*D + tid] - kqmax[j]); - kqsum[j] = kqsum[j]*KQ_max_scale + val; - KQ[j*D + tid] = val; - - VKQ[j] *= __half2half2(KQ_max_scale); - } - - __syncthreads(); - -#pragma unroll - for (int k0 = 0; k0 < D; k0 += 2) { - if (FATTN_KQ_STRIDE % D != 0 && k_VKQ_0 + k0 >= ne11) { - break; - } - - half2 V_k; - reinterpret_cast(V_k.x) = dequantize_1_v(V + (k_VKQ_0 + k0 + 0)*nb21, tid); - reinterpret_cast(V_k.y) = dequantize_1_v(V + (k_VKQ_0 + k0 + 1)*nb21, tid); -#pragma unroll - for (int j = 0; j < ncols; ++j) { - VKQ[j] += V_k*KQ2[j*(D/2) + k0/2]; - } - } - - __syncthreads(); - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqsum[j] = warp_reduce_sum((float)kqsum[j]); - if (threadIdx.x == 0) { - kqsum_shared[j][threadIdx.y] = kqsum[j]; - } - } - - __syncthreads(); - -#pragma unroll - for (int j_VKQ = 0; j_VKQ < ncols; ++j_VKQ) { - if (ncols > 2 && ic0 + j_VKQ >= ne01) { - break; - } - - kqsum[j_VKQ] = kqsum_shared[j_VKQ][threadIdx.x]; - kqsum[j_VKQ] = warp_reduce_sum((float)kqsum[j_VKQ]); - - half dst_val = (__low2half(VKQ[j_VKQ]) + __high2half(VKQ[j_VKQ])); - if (gridDim.y == 1) { - dst_val /= kqsum[j_VKQ]; - } - const int j_dst = (ic0 + j_VKQ)*gridDim.y + blockIdx.y; - dst[j_dst*D*gridDim.z + D*blockIdx.z + tid] = dst_val; - } - - if (gridDim.y != 1 && tid < ncols && (ncols <= 2 || ic0 + tid < ne01)) { - dst_meta[((ic0 + tid)*gridDim.z + blockIdx.z) * gridDim.y + blockIdx.y] = make_float2(kqmax[tid], kqsum[tid]); - } -#else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; -#endif // defined(FLASH_ATTN_AVAILABLE) && defined(FP16_AVAILABLE) -} - -template -void ggml_cuda_flash_attn_ext_vec_f16_case_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - constexpr int nwarps = D/WARP_SIZE; - fattn_kernel_t fattn_kernel = flash_attn_vec_ext_f16; - constexpr bool need_f16_K = D != 128; - constexpr bool need_f16_V = D != 128 && D != 64; - constexpr size_t nbytes_shared = 0; - launch_fattn(ctx, dst, fattn_kernel, nwarps, nbytes_shared, D, need_f16_K, need_f16_V, false); -} - -template -void ggml_cuda_flash_attn_ext_vec_f16_case(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - const ggml_tensor * K = dst->src[1]; - const ggml_tensor * V = dst->src[2]; - - const int32_t precision = KQV->op_params[3]; - GGML_ASSERT(precision == GGML_PREC_DEFAULT); - - GGML_ASSERT(K->type == type_K); - GGML_ASSERT(V->type == type_V); - - float logit_softcap; - memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); - - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; - - if (Q->ne[1] == 1 || GGML_CUDA_CC_IS_NVIDIA(cc)) { - constexpr int cols_per_block = 1; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } - return; - } - - if (Q->ne[1] == 2) { - constexpr int cols_per_block = 2; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } - return; - } - - if (Q->ne[1] <= 4) { - constexpr int cols_per_block = 4; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } - return; - } - - constexpr int cols_per_block = 8; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f16_case_impl(ctx, dst); - } -} - -#define DECL_FATTN_VEC_F16_CASE(D, type_K, type_V) \ - template void ggml_cuda_flash_attn_ext_vec_f16_case \ - (ggml_backend_cuda_context & ctx, ggml_tensor * dst) \ - -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0); - -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16); - -extern DECL_FATTN_VEC_F16_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f32.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f32.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f32.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec-f32.cuh 1970-01-01 00:00:00.000000000 +0000 @@ -1,477 +0,0 @@ -#include "common.cuh" -#include "fattn-common.cuh" - -template // D == head size -#ifndef GGML_USE_HIP -__launch_bounds__(D, 1) -#endif // GGML_USE_HIP -static __global__ void flash_attn_vec_ext_f32( - const char * __restrict__ Q, - const char * __restrict__ K, - const char * __restrict__ V, - const char * __restrict__ mask, - float * __restrict__ dst, - float2 * __restrict__ dst_meta, - const float scale, - const float max_bias, - const float m0, - const float m1, - const uint32_t n_head_log2, - const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { -#ifdef FLASH_ATTN_AVAILABLE - - // Skip unused kernel variants for faster compilation: - if (use_logit_softcap && !(D == 128 || D == 256)) { - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); - GGML_UNUSED(ne03); GGML_UNUSED(ne10); GGML_UNUSED(ne11); - GGML_UNUSED(ne12); GGML_UNUSED(ne13); GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); - GGML_UNUSED(nb13); GGML_UNUSED(nb21); GGML_UNUSED(nb22); - GGML_UNUSED(nb23); GGML_UNUSED(ne0); GGML_UNUSED(ne1); - GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; - return; - } -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) - if (ncols > 1) { - NO_DEVICE_CODE; - return; - } -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) - - //In this kernel Q, K, V are matrices while i, j, k are matrix indices. - - constexpr vec_dot_KQ_f32_t vec_dot_KQ = get_vec_dot_KQ_f32(type_K); - constexpr bool Q_q8_1 = type_K != GGML_TYPE_F16; - constexpr dequantize_1_f32_t dequantize_1_v = get_dequantize_1_f32(type_V); - - const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. - - const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - Q += nb02* blockIdx.z + nb01*ic0; - K += nb12*(blockIdx.z / gqa_ratio); - V += nb22*(blockIdx.z / gqa_ratio); // K and V have same shape - - const half * maskh = (const half *) (mask + nb32*(blockIdx.z % ne32) + nb31*ic0); - - const float slope = get_alibi_slope(max_bias, blockIdx.z, n_head_log2, m0, m1); - - static_assert(D % (2*WARP_SIZE) == 0, "D not divisible by 2*WARP_SIZE == 64."); - constexpr int nwarps = D / WARP_SIZE; - const int tid = WARP_SIZE*threadIdx.y + threadIdx.x; - __builtin_assume(tid < D); - - __shared__ float KQ[ncols*D]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - KQ[j*D + tid] = -FLT_MAX/2.0f; - } - - float kqmax[ncols]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqmax[j] = -FLT_MAX/2.0f; - } - float kqsum[ncols] = {0.0f}; - - __shared__ float kqmax_shared[ncols][WARP_SIZE]; - __shared__ float kqsum_shared[ncols][WARP_SIZE]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - if (threadIdx.y == 0) { - kqmax_shared[j][threadIdx.x] = -FLT_MAX/2.0f; - kqsum_shared[j][threadIdx.x] = 0.0f; - } - } - - __shared__ float maskf_shared[ncols*D]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - maskf_shared[j*D + tid] = 0.0f; - } - - __syncthreads(); - - // Convert Q to float2 (f16 K) or q8_1 (quantized K) and store in registers: - float2 Q_f2[ncols][D/(2*WARP_SIZE)]; - int Q_i32[ncols][D/(sizeof(int)*QK8_1) == 0 ? 1 : D >= D/(sizeof(int)*QK8_1)]; - float2 Q_ds[ncols][D/QK8_1 == 0 ? 1 : D/QK8_1]; - if (Q_q8_1) { -#pragma unroll - for (int j0 = 0; j0 < ncols; j0 += nwarps) { - const int j = j0 + threadIdx.y; - - if (j0 + nwarps > ncols && j >= ncols) { - break; - } - - // Reuse KQ as temporary storage for converting Q to q8_1: - int * tmp_q_i32 = (int *) &KQ[j*D]; - float2 * tmp_q_ds = (float2 *) (tmp_q_i32 + D/sizeof(int)); - - // Set memory to zero if out of bounds: - if (ncols > 2 && ic0 + j >= ne01) { -#pragma unroll - for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - tmp_q_i32[i] = 0; - } - if (threadIdx.x < D/QK8_1) { - tmp_q_ds[threadIdx.x] = make_float2(0.0f, 0.0f); - } - continue; - } - - const float * Q_f = (const float *) (Q + j*nb01); -#pragma unroll - for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += WARP_SIZE) { - quantize_q8_1_to_shared(Q_f + 4*i0, scale, tmp_q_i32, tmp_q_ds); - } - } - - __syncthreads(); - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - int * tmp_q_i32 = (int *) &KQ[j*D]; - float2 * tmp_q_ds = (float2 *) (tmp_q_i32 + D/sizeof(int)); - -#pragma unroll - for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - Q_i32[j][i0/WARP_SIZE] = tmp_q_i32[i]; - Q_ds[j][i0/WARP_SIZE] = tmp_q_ds[i/QI8_1]; - } - } - - __syncthreads(); - } else { -#pragma unroll - for (int j = 0; j < ncols; ++j) { - const float2 * Q_f2_j = (const float2 *) (Q + j*nb01); -#pragma unroll - for (int i0 = 0; i0 < D/2; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - Q_f2[j][i0/WARP_SIZE] = ncols <= 2 || ic0 + j < ne01 ? Q_f2_j[i] : make_float2(0.0f, 0.0f); - Q_f2[j][i0/WARP_SIZE].x *= scale; - Q_f2[j][i0/WARP_SIZE].y *= scale; - } - } - } - - float VKQ[ncols] = {0.0f}; - - for (int k_VKQ_0 = blockIdx.y*D; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*D) { - // Calculate KQ tile and keep track of new maximum KQ values: - - if (mask) { -#pragma unroll - for (int j = 0; j < ncols; ++j) { - maskf_shared[j*D + tid] = slope*__half2float(maskh[j*ne11 + k_VKQ_0 + tid]); - } - - __syncthreads(); - - // When using multiple parallel sequences in llama.cpp, some KV slices can be fully masked out. - // In such cases, skip the KV slice. - // On AMD __all_sync would not work correctly because it assumes a warp size of 64. -#ifndef GGML_USE_HIP - bool skip = true; -#pragma unroll - for (int j = 0; j < ncols; ++j) { -#pragma unroll - for (int i0 = 0; i0 < D; i0 += WARP_SIZE) { - const int i = i0 + threadIdx.x; - - skip = skip && isinf(maskf_shared[j*D + i]); - } - } - if (__all_sync(0xFFFFFFFF, skip)) { - __syncthreads(); - continue; - } -#endif // GGML_USE_HIP - } - - float kqmax_new_arr[ncols]; -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqmax_new_arr[j] = kqmax[j]; - } - -#pragma unroll - for (int i_KQ_0 = 0; i_KQ_0 < D; i_KQ_0 += nwarps) { - const int i_KQ = i_KQ_0 + threadIdx.y; - - if ((i_KQ_0 + nwarps > D && i_KQ >= D) || (FATTN_KQ_STRIDE % D != 0 && k_VKQ_0 + i_KQ >= ne11)) { - break; - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - float sum = vec_dot_KQ(K + (k_VKQ_0 + i_KQ)*nb11, Q_f2[j], Q_i32[j], Q_ds[j]); - sum = warp_reduce_sum(sum); - - if (use_logit_softcap) { - sum = logit_softcap*tanhf(sum); - } - - sum += maskf_shared[j*D + i_KQ]; - - kqmax_new_arr[j] = fmaxf(kqmax_new_arr[j], sum); - - if (threadIdx.x == 0) { - KQ[j*D + i_KQ] = sum; - } - } - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - float kqmax_new_j = kqmax_new_arr[j]; - - if (threadIdx.x == 0) { - kqmax_shared[j][threadIdx.y] = kqmax_new_j; - } - } - - __syncthreads(); - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - float kqmax_new_j = kqmax_shared[j][threadIdx.x]; - kqmax_new_j = warp_reduce_max(kqmax_new_j); - - const float KQ_max_scale = expf(kqmax[j] - kqmax_new_j); - kqmax[j] = kqmax_new_j; - - const float val = expf(KQ[j*D + tid] - kqmax[j]); - kqsum[j] = kqsum[j]*KQ_max_scale + val; - KQ[j*D + tid] = val; - - VKQ[j] *= KQ_max_scale; - } - - __syncthreads(); - -#pragma unroll - for (int k = 0; k < D; ++k) { - if (FATTN_KQ_STRIDE % D != 0 && k_VKQ_0 + k >= ne11) { - break; - } - - const float V_ki = dequantize_1_v(V + (k_VKQ_0 + k)*nb21, tid); -#pragma unroll - for (int j = 0; j < ncols; ++j) { - VKQ[j] += V_ki*KQ[j*D + k]; - } - } - - __syncthreads(); - } - -#pragma unroll - for (int j = 0; j < ncols; ++j) { - kqsum[j] = warp_reduce_sum(kqsum[j]); - if (threadIdx.x == 0) { - kqsum_shared[j][threadIdx.y] = kqsum[j]; - } - } - - __syncthreads(); - -#pragma unroll - for (int j_VKQ = 0; j_VKQ < ncols; ++j_VKQ) { - if (ncols > 2 && ic0 + j_VKQ >= ne01) { - break; - } - - kqsum[j_VKQ] = kqsum_shared[j_VKQ][threadIdx.x]; - kqsum[j_VKQ] = warp_reduce_sum(kqsum[j_VKQ]); - - float dst_val = VKQ[j_VKQ]; - if (gridDim.y == 1) { - dst_val /= kqsum[j_VKQ]; - } - const int j_dst = (ic0 + j_VKQ)*gridDim.y + blockIdx.y; - dst[j_dst*D*gridDim.z + D*blockIdx.z + tid] = dst_val; - } - - if (gridDim.y != 1 && tid < ncols && (ncols <= 2 || ic0 + tid < ne01)) { - dst_meta[((ic0 + tid)*gridDim.z + blockIdx.z) * gridDim.y + blockIdx.y] = make_float2(kqmax[tid], kqsum[tid]); - } -#else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); - GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); - GGML_UNUSED(ne31); GGML_UNUSED(ne32); - GGML_UNUSED(nb31); GGML_UNUSED(nb32); - GGML_UNUSED(nb01); GGML_UNUSED(nb02); GGML_UNUSED(nb03); - GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); - GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); - NO_DEVICE_CODE; -#endif // FLASH_ATTN_AVAILABLE -} - -template -void ggml_cuda_flash_attn_ext_vec_f32_case_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - constexpr int nwarps = D/WARP_SIZE; - fattn_kernel_t fattn_kernel = flash_attn_vec_ext_f32; - constexpr bool need_f16_K = D != 128; - constexpr bool need_f16_V = D != 128 && D != 64; - constexpr size_t nbytes_shared = 0; - launch_fattn(ctx, dst, fattn_kernel, nwarps, nbytes_shared, D, need_f16_K, need_f16_V, false); -} - -template -void ggml_cuda_flash_attn_ext_vec_f32_case(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - const ggml_tensor * K = dst->src[1]; - const ggml_tensor * V = dst->src[2]; - - GGML_ASSERT(K->type == type_K); - GGML_ASSERT(V->type == type_V); - - float logit_softcap; - memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); - - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; - - if (Q->ne[1] == 1 || GGML_CUDA_CC_IS_NVIDIA(cc)) { - constexpr int cols_per_block = 1; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } - return; - } - - if (Q->ne[1] == 2) { - constexpr int cols_per_block = 2; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } - return; - } - - if (Q->ne[1] <= 4) { - constexpr int cols_per_block = 4; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } - return; - } - - constexpr int cols_per_block = 8; - if (logit_softcap == 0.0f) { - constexpr bool use_logit_softcap = false; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } else { - constexpr bool use_logit_softcap = true; - ggml_cuda_flash_attn_ext_vec_f32_case_impl(ctx, dst); - } -} - -#define DECL_FATTN_VEC_F32_CASE(D, type_K, type_V) \ - template void ggml_cuda_flash_attn_ext_vec_f32_case \ - (ggml_backend_cuda_context & ctx, ggml_tensor * dst) \ - -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0); - -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16); -extern DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16); - -extern DECL_FATTN_VEC_F32_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-vec.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-vec.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,593 @@ +#include "common.cuh" +#include "fattn-common.cuh" + +static int ggml_cuda_fattn_vec_get_nthreads_host(const int cc) { + return 128; + GGML_UNUSED(cc); +} + +static constexpr __device__ int ggml_cuda_fattn_vec_get_nthreads_device() { + return 128; +} + +// Currenlty llvm with the amdgcn target dose not support unrolling loops +// that contain a break that can not be resolved at compile time. +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpass-failed" +#endif // __clang__ +template // D == head size +__launch_bounds__(ggml_cuda_fattn_vec_get_nthreads_device(), 1) +static __global__ void flash_attn_ext_vec( + const char * __restrict__ Q, + const char * __restrict__ K, + const char * __restrict__ V, + const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, + float * __restrict__ dst, + float2 * __restrict__ dst_meta, + const float scale, + const float max_bias, + const float m0, + const float m1, + const uint32_t n_head_log2, + const float logit_softcap, + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { +#ifdef FLASH_ATTN_AVAILABLE + + // Skip unused kernel variants for faster compilation: + if (use_logit_softcap && !(D == 128 || D == 256)) { + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); + NO_DEVICE_CODE; + return; + } + + //In this kernel Q, K, V are matrices while i, j, k are matrix indices. + + constexpr int cpy_nb = ggml_cuda_get_max_cpy_bytes(); + constexpr int cpy_ne = cpy_nb / 4; + +#ifdef GGML_USE_HIP +#ifdef RDNA + constexpr int nthreads_KQ_q = 2; +#else + constexpr int nthreads_KQ_q = 4; +#endif // RDNA + constexpr int nthreads_V_q = (D/4 < 32 ? D/4 : 32); +#else + constexpr int nthreads_KQ_q = (D/4 < 32 ? D/4 : 32); + constexpr int nthreads_V_q = (D/4 < 32 ? D/4 : 32); +#endif // GGML_USE_HIP + + constexpr int nthreads = ggml_cuda_fattn_vec_get_nthreads_device(); + constexpr int nthreads_KQ = type_K == GGML_TYPE_F16 ? 128 / cpy_nb : nthreads_KQ_q; + constexpr int nthreads_V = type_V == GGML_TYPE_F16 ? 128 / cpy_nb : nthreads_V_q; + + static_assert(WARP_SIZE % nthreads_KQ == 0, "bad nthreads_K"); + static_assert(WARP_SIZE % nthreads_V == 0, "bad nthreads_V"); + + constexpr int V_rows_per_thread = type_V == GGML_TYPE_F16 ? 2*cpy_ne : 4; + constexpr int V_cols_per_iter = WARP_SIZE / nthreads_V; + + constexpr vec_dot_KQ_t vec_dot_KQ = get_vec_dot_KQ(); + constexpr bool Q_q8_1 = type_K != GGML_TYPE_F16; +#ifdef FAST_FP16_AVAILABLE + constexpr dequantize_V_t dequantize_V = get_dequantize_V(); +#else + constexpr dequantize_V_t dequantize_V = get_dequantize_V(); +#endif // FAST_FP16_AVAILABLE + + const int ic0 = blockIdx.x * ncols; // Index of the Q/QKV column to work on. + + const int sequence = blockIdx.z / ne02; + const int head = blockIdx.z - sequence*ne02; + const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. + Q += nb03*sequence + nb02* head + nb01*ic0; + K += nb13*sequence + nb12*(head / gqa_ratio); + V += nb23*sequence + nb22*(head / gqa_ratio); + + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + + const float slope = get_alibi_slope(max_bias, head, n_head_log2, m0, m1); + + static_assert(D % (2*WARP_SIZE) == 0, "D not divisible by 2*WARP_SIZE == 64."); + constexpr int nwarps = nthreads / WARP_SIZE; + const int tid = WARP_SIZE*threadIdx.y + threadIdx.x; + __builtin_assume(tid < nthreads); + + constexpr int ne_KQ = ncols*D; + constexpr int ne_combine = nwarps*V_cols_per_iter*D; +#ifdef FAST_FP16_AVAILABLE + half2 VKQ[ncols][(D/2)/nthreads_V] = {{{0.0f, 0.0f}}}; + __shared__ half KQ[ne_KQ > ne_combine ? ne_KQ : ne_combine]; +#else + float2 VKQ[ncols][(D/2)/nthreads_V] = {{{0.0f, 0.0f}}}; + __shared__ float KQ[ne_KQ > ne_combine ? ne_KQ : ne_combine]; +#endif // FAST_FP16_AVAILABLE + + float KQ_max[ncols]; + float KQ_sum[ncols]; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + KQ_max[j] = -FLT_MAX/2.0f; + KQ_sum[j] = 0.0f; + } + + // Convert Q to float2 (f16 K) or q8_1 (quantized K) and store in registers: +#ifdef FAST_FP16_AVAILABLE + half2 Q_reg[ncols][(D/2)/nthreads_KQ]; // Will be initialized completely. +#else + float2 Q_reg[ncols][(D/2)/nthreads_KQ] = {{{0.0f, 0.0f}}}; // May be only partially initialized. +#endif // FAST_FP16_AVAILABLE + int Q_i32[ncols][1 > D/(sizeof(int)*nthreads_KQ) ? 1 : D/(sizeof(int)*nthreads_KQ)]; + float2 Q_ds[ncols][1 > D/(sizeof(int)*nthreads_KQ) ? 1 : D/(sizeof(int)*nthreads_KQ)]; + if constexpr (Q_q8_1) { +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (j0 + nwarps > ncols && j >= ncols) { + break; + } + + // Reuse KQ as temporary storage for converting Q to q8_1: + int * tmp_q_i32 = (int *) &KQ[j*D]; + float2 * tmp_q_ds = (float2 *) (tmp_q_i32 + D/sizeof(int)); + + // Set memory to zero if out of bounds: + if (ncols > 1 && ic0 + j >= ne01) { +#pragma unroll + for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += WARP_SIZE) { + const int i = i0 + threadIdx.x; + + if (i0 + WARP_SIZE <= D/sizeof(int) || i < D/sizeof(int)) { + tmp_q_i32[i] = 0; + } + } + if (threadIdx.x < D/QK8_1) { + tmp_q_ds[threadIdx.x] = make_float2(0.0f, 0.0f); + } + } else { + const float * Q_f = (const float *) (Q + j*nb01); + constexpr int nthreads_quantize = D/sizeof(int) < WARP_SIZE ? D/sizeof(int) : WARP_SIZE; +#pragma unroll + for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += nthreads_quantize) { + quantize_q8_1_to_shared + (Q_f + i0*sizeof(int), scale, tmp_q_i32 + i0, tmp_q_ds + i0/QI8_1); + } + } + } + + __syncthreads(); + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + int * tmp_q_i32 = (int *) &KQ[j*D]; + float2 * tmp_q_ds = (float2 *) (tmp_q_i32 + D/sizeof(int)); + +#pragma unroll + for (int i0 = 0; i0 < int(D/sizeof(int)); i0 += nthreads_KQ) { + const int i = i0 + (nthreads_KQ == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_KQ); + + Q_i32[j][i0/nthreads_KQ] = tmp_q_i32[i]; + Q_ds[j][i0/nthreads_KQ] = tmp_q_ds[i/QI8_1]; + } + } + + __syncthreads(); + } else { +#ifdef FAST_FP16_AVAILABLE + const half2 scale_h2 = make_half2(scale, scale); +#pragma unroll + for (int j = 0; j < ncols; ++j) { + const float2 * Q_j = (const float2 *) (Q + j*nb01); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += nthreads_KQ*cpy_ne) { + const int i = i0 + (nthreads_KQ == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_KQ)*cpy_ne; + + float2 tmp[cpy_ne] = {{0.0f, 0.0f}}; + if (ncols == 1 || ic0 + j < ne01) { + ggml_cuda_memcpy_1(tmp, &Q_j[i]); + ggml_cuda_memcpy_1(tmp + cpy_ne/2, &Q_j[i + cpy_ne/2]); + } +#pragma unroll + for (int i1 = 0; i1 < cpy_ne; ++i1) { + Q_reg[j][i0/nthreads_KQ + i1] = make_half2(tmp[i1].x, tmp[i1].y); + } + } +#pragma unroll + for (int k = 0; k < (D/2)/nthreads_KQ; ++k) { + Q_reg[j][k] *= scale_h2; + } + } +#else +#pragma unroll + for (int j = 0; j < ncols; ++j) { + const float2 * Q_j = (const float2 *) (Q + j*nb01); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += nthreads_KQ*cpy_ne) { + const int i = i0 + (nthreads_KQ == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_KQ)*cpy_ne; + if (ncols == 1 || ic0 + j < ne01) { + ggml_cuda_memcpy_1(&Q_reg[j][i0/nthreads_KQ], &Q_j[i]); + ggml_cuda_memcpy_1(&Q_reg[j][i0/nthreads_KQ + cpy_ne/2], &Q_j[i + cpy_ne/2]); + } + } +#pragma unroll + for (int k = 0; k < (D/2)/nthreads_KQ; ++k) { + Q_reg[j][k].x *= scale; + Q_reg[j][k].y *= scale; + } + } +#endif // FAST_FP16_AVAILABLE + } + + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + K += blockIdx.y*nthreads * nb11; + V += blockIdx.y*nthreads * nb21; + maskh += blockIdx.y*nthreads; + for (int k_VKQ_0 = blockIdx.y*nthreads; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*nthreads, + // Increment pointers after each loop: + K += gridDim.y*nthreads*nb11, V += gridDim.y*nthreads*nb21, maskh += gridDim.y*nthreads) { + + // Calculate KQ tile and keep track of new maximum KQ values: + float KQ_reg[ncols]; // KQ in registers. + + float KQ_max_new[ncols]; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + KQ_max_new[j] = KQ_max[j]; + } + +#pragma unroll + for (int i_KQ_0 = 0; i_KQ_0 < nthreads_KQ; ++i_KQ_0) { + const int i_KQ = threadIdx.y*WARP_SIZE + (nthreads_KQ == WARP_SIZE ? 0 : (threadIdx.x & ~(nthreads_KQ-1))) + i_KQ_0; + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + float sum = vec_dot_KQ(K + i_KQ*nb11, Q_reg[j], Q_i32[j], Q_ds[j]); + sum = warp_reduce_sum(sum); + + if (use_logit_softcap) { + sum = logit_softcap*tanhf(sum); + } + + if (mask) { + sum += slope*__half2float(maskh[j*ne11 + i_KQ]); + } + + KQ_max_new[j] = fmaxf(KQ_max_new[j], sum); + + if ((nthreads_KQ == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_KQ) == i_KQ_0) { + KQ_reg[j] = sum; + } + } + } + +#pragma unroll + for (int j = 0; j < ncols; ++j) { +#pragma unroll + for (int offset = nthreads_KQ; offset < WARP_SIZE; offset <<= 1) { + KQ_max_new[j] = fmaxf(KQ_max_new[j], __shfl_xor_sync(0xFFFFFFFF, KQ_max_new[j], offset, WARP_SIZE)); + } + const float KQ_max_scale = expf(KQ_max[j] - KQ_max_new[j]); + KQ_max[j] = KQ_max_new[j]; + + KQ_reg[j] = expf(KQ_reg[j] - KQ_max[j]); + KQ_sum[j] = KQ_sum[j]*KQ_max_scale + KQ_reg[j]; + KQ[j*nthreads + tid] = KQ_reg[j]; + +#ifdef FAST_FP16_AVAILABLE + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j][i_VKQ_0/nthreads_V] *= KQ_max_scale_h2; + } +#else +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j][i_VKQ_0/nthreads_V].x *= KQ_max_scale; + VKQ[j][i_VKQ_0/nthreads_V].y *= KQ_max_scale; + } +#endif // FAST_FP16_AVAILABLE + } + +#ifndef GGML_USE_HIP + __syncwarp(); +#endif // GGML_USE_HIP + +#pragma unroll + for (int k0 = 0; k0 < WARP_SIZE; k0 += V_cols_per_iter) { + const int k = threadIdx.y*WARP_SIZE + k0 + (nthreads_V == WARP_SIZE ? 0 : threadIdx.x / nthreads_V); + +#ifdef FAST_FP16_AVAILABLE + half2 KQ_k[ncols]; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + KQ_k[j] = __half2half2(KQ[j*nthreads + k]); + } +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { + half2 tmp[V_rows_per_thread/2]; + dequantize_V(V + k*nb21, tmp, + 2*i_VKQ_0 + (nthreads_V == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_V)*V_rows_per_thread); +#pragma unroll + for (int i_VKQ_1 = 0; i_VKQ_1 < V_rows_per_thread/2; ++i_VKQ_1) { +#pragma unroll + for (int j = 0; j < ncols; ++j) { + VKQ[j][i_VKQ_0/nthreads_V + i_VKQ_1] += tmp[i_VKQ_1]*KQ_k[j]; + } + } + } +#else + float KQ_k[ncols]; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + KQ_k[j] = KQ[j*nthreads + k]; + } +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { + float2 tmp[V_rows_per_thread/2]; + dequantize_V(V + k*nb21, tmp, + 2*i_VKQ_0 + (nthreads_V == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_V)*V_rows_per_thread); +#pragma unroll + for (int i_VKQ_1 = 0; i_VKQ_1 < V_rows_per_thread/2; ++i_VKQ_1) { +#pragma unroll + for (int j = 0; j < ncols; ++j) { + VKQ[j][i_VKQ_0/nthreads_V + i_VKQ_1].x += tmp[i_VKQ_1].x*KQ_k[j]; + VKQ[j][i_VKQ_0/nthreads_V + i_VKQ_1].y += tmp[i_VKQ_1].y*KQ_k[j]; + } + } + } +#endif // FAST_FP16_AVAILABLE + } + } + + if (sinks && blockIdx.y == 0) { + const float sink = ((const float *) sinks)[head]; + +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (j0 + nwarps > ncols && j >= ncols) { + break; + } + + const float kqmax_new_j = fmaxf(sink, KQ_max[j]); + const float KQ_max_scale = expf(KQ_max[j] - kqmax_new_j); + KQ_max[j] = kqmax_new_j; + + KQ_sum[j] = KQ_sum[j]*KQ_max_scale + (threadIdx.x == 0 ? expf(sink - KQ_max[j]) : 0.0f); + +#ifdef FAST_FP16_AVAILABLE + const half2 KQ_max_scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j][i_VKQ_0/nthreads_V] *= KQ_max_scale_h2; + } +#else +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j][i_VKQ_0/nthreads_V].x *= KQ_max_scale; + VKQ[j][i_VKQ_0/nthreads_V].y *= KQ_max_scale; + } +#endif // FAST_FP16_AVAILABLE + } + } + + __shared__ float KQ_max_shared[ncols][WARP_SIZE]; + __shared__ float KQ_sum_shared[ncols][WARP_SIZE]; +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (threadIdx.y == 0) { + KQ_max_shared[j][threadIdx.x] = -FLT_MAX/2.0f; + KQ_sum_shared[j][threadIdx.x] = 0.0f; + } + } + + __syncthreads(); + +#pragma unroll + for (int j = 0; j < ncols; ++j) { + if (threadIdx.x == 0) { + KQ_max_shared[j][threadIdx.y] = KQ_max[j]; + } + } + __syncthreads(); + +#pragma unroll + for (int j_VKQ = 0; j_VKQ < ncols; ++j_VKQ) { + if (ncols > 1 && ic0 + j_VKQ >= ne01) { + break; + } + + float kqmax_new = KQ_max_shared[j_VKQ][threadIdx.x]; + kqmax_new = warp_reduce_max(kqmax_new); + const float kqmax_scale = expf(KQ_max[j_VKQ] - kqmax_new); + KQ_max[j_VKQ] = kqmax_new; + +#ifdef FAST_FP16_AVAILABLE + half2 * VKQ_tmp = (half2 *) KQ + threadIdx.y*(V_cols_per_iter*D/2) + + (nthreads_V == WARP_SIZE ? 0 : threadIdx.x / nthreads_V)*(D/2); + + const half2 kqmax_scale_h2 = make_half2(kqmax_scale, kqmax_scale); +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j_VKQ][i_VKQ_0/nthreads_V] *= kqmax_scale_h2; + } +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { + const int i_VKQ = i_VKQ_0 + (nthreads_V == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_V)*(V_rows_per_thread/2); + + ggml_cuda_memcpy_1(VKQ_tmp + i_VKQ, &VKQ[j_VKQ][i_VKQ_0/nthreads_V]); + } +#else + float2 * VKQ_tmp = (float2 *) KQ + threadIdx.y*(V_cols_per_iter*D/2) + + (nthreads_V == WARP_SIZE ? 0 : threadIdx.x / nthreads_V)*(D/2); + +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V) { + VKQ[j_VKQ][i_VKQ_0/nthreads_V].x *= kqmax_scale; + VKQ[j_VKQ][i_VKQ_0/nthreads_V].y *= kqmax_scale; + } +#pragma unroll + for (int i_VKQ_0 = 0; i_VKQ_0 < D/2; i_VKQ_0 += nthreads_V*V_rows_per_thread/2) { + const int i_VKQ = i_VKQ_0 + (nthreads_V == WARP_SIZE ? threadIdx.x : threadIdx.x % nthreads_V)*(V_rows_per_thread/2); + + ggml_cuda_memcpy_1(VKQ_tmp + i_VKQ, &VKQ[j_VKQ][i_VKQ_0/nthreads_V]); + ggml_cuda_memcpy_1(VKQ_tmp + i_VKQ + V_rows_per_thread/4, &VKQ[j_VKQ][i_VKQ_0/nthreads_V + V_rows_per_thread/4]); + } +#endif // FAST_FP16_AVAILABLE + + KQ_sum[j_VKQ] *= kqmax_scale; + KQ_sum[j_VKQ] = warp_reduce_sum(KQ_sum[j_VKQ]); + if (threadIdx.x == 0) { + KQ_sum_shared[j_VKQ][threadIdx.y] = KQ_sum[j_VKQ]; + } + + __syncthreads(); + + if (nthreads <= D || tid < D) { + KQ_sum[j_VKQ] = KQ_sum_shared[j_VKQ][threadIdx.x]; + KQ_sum[j_VKQ] = warp_reduce_sum(KQ_sum[j_VKQ]); + +#pragma unroll + for (int i0 = 0; i0 < D; i0 += nthreads) { + float dst_val = 0; +#pragma unroll + for (int w = 0; w < nwarps; ++w) { +#pragma unroll + for (int v = 0; v < V_cols_per_iter; ++v) { + dst_val += float(KQ[w*V_cols_per_iter*D + v*D + i0 + tid]); + } + } + if (gridDim.y == 1) { + dst_val /= KQ_sum[j_VKQ]; + } + dst[(((sequence*ne01 + ic0 + j_VKQ)*ne02 + head)*gridDim.y + blockIdx.y)*D + i0 + tid] = dst_val; + } + } + + if (j_VKQ < ncols-1) { + __syncthreads(); + } + + } + + if (gridDim.y != 1 && tid < ncols && (ncols == 1 || ic0 + tid < ne01)) { + dst_meta[((sequence*ne01 + ic0 + tid)*ne02 + head)*gridDim.y + blockIdx.y] = make_float2(KQ_max[tid], KQ_sum[tid]); + } +#else + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); + NO_DEVICE_CODE; +#endif // FLASH_ATTN_AVAILABLE +} +#ifdef __clang__ +#pragma clang diagnostic pop +#endif // __clang__ + +template +void ggml_cuda_flash_attn_ext_vec_case_impl(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + + const int nthreads = ggml_cuda_fattn_vec_get_nthreads_host(cc); + const int nwarps = nthreads / WARP_SIZE; + fattn_kernel_t fattn_kernel = flash_attn_ext_vec; + constexpr bool need_f16_K = false; + constexpr bool need_f16_V = false; + constexpr size_t nbytes_shared = 0; + launch_fattn(ctx, dst, fattn_kernel, nwarps, nbytes_shared, D, need_f16_K, need_f16_V, false); +} + +template +void ggml_cuda_flash_attn_ext_vec_case(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * KQV = dst; + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + + GGML_ASSERT(K->type == type_K); + GGML_ASSERT(V->type == type_V); + + float logit_softcap; + memcpy(&logit_softcap, (const float *) KQV->op_params + 2, sizeof(float)); + + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + + if (Q->ne[1] == 1) { + constexpr int cols_per_block = 1; + if (logit_softcap == 0.0f) { + constexpr bool use_logit_softcap = false; + ggml_cuda_flash_attn_ext_vec_case_impl(ctx, dst); + } else { + constexpr bool use_logit_softcap = true; + ggml_cuda_flash_attn_ext_vec_case_impl(ctx, dst); + } + return; + } + + constexpr int cols_per_block = 2; + if (logit_softcap == 0.0f) { + constexpr bool use_logit_softcap = false; + ggml_cuda_flash_attn_ext_vec_case_impl(ctx, dst); + } else { + constexpr bool use_logit_softcap = true; + ggml_cuda_flash_attn_ext_vec_case_impl(ctx, dst); + } +} + +#define DECL_FATTN_VEC_CASE(D, type_K, type_V) \ + template void ggml_cuda_flash_attn_ext_vec_case \ + (ggml_backend_cuda_context & ctx, ggml_tensor * dst) \ + +#define EXTERN_DECL_FATTN_VEC_CASES(D, type_K) \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_F16); \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_Q4_0); \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_Q4_1); \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_Q5_0); \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_Q5_1); \ + extern DECL_FATTN_VEC_CASE(D, type_K, GGML_TYPE_Q8_0); \ + +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_F16) +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_Q4_0) +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_Q4_1) +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_Q5_0) +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_Q5_1) +EXTERN_DECL_FATTN_VEC_CASES( 64, GGML_TYPE_Q8_0) + +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_F16) +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_Q4_0) +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_Q4_1) +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_Q5_0) +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_Q5_1) +EXTERN_DECL_FATTN_VEC_CASES(128, GGML_TYPE_Q8_0) + +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_F16) +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q4_0) +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q4_1) +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q5_0) +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q5_1) +EXTERN_DECL_FATTN_VEC_CASES(256, GGML_TYPE_Q8_0) diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn-wmma-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/fattn-wmma-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn-wmma-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn-wmma-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -7,7 +7,7 @@ #include "fattn-wmma-f16.cuh" #ifdef FP16_MMA_AVAILABLE -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) #include #ifdef GGML_USE_MUSA namespace wmma = mtmusa::wmma; @@ -15,10 +15,9 @@ namespace wmma = mtmusa::wmma; namespace wmma = nvcuda::wmma; #endif // GGML_USE_MUSA #elif defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE) -#undef HIP_ENABLE_WARP_SYNC_BUILTINS // conflicts with rocWMMA headers #include namespace wmma = rocwmma; -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) #endif // FP16_MMA_AVAILABLE // D == head size, VKQ_stride == num VKQ rows calculated in parallel: @@ -29,6 +28,8 @@ static __global__ void flash_attn_ext_f1 const char * __restrict__ K, const char * __restrict__ V, const char * __restrict__ mask, + const char * __restrict__ sinks, + const int * __restrict__ KV_max, float * __restrict__ dst, float2 * __restrict__ dst_meta, const float scale, @@ -37,31 +38,13 @@ static __global__ void flash_attn_ext_f1 const float m1, const uint32_t n_head_log2, const float logit_softcap, - const int ne00, - const int ne01, - const int ne02, - const int ne03, - const int ne10, - const int ne11, - const int ne12, - const int ne13, - const int ne31, - const int ne32, - const int nb31, - const int nb32, - const int nb01, - const int nb02, - const int nb03, - const int nb11, - const int nb12, - const int nb13, - const int nb21, - const int nb22, - const int nb23, - const int ne0, - const int ne1, - const int ne2, - const int ne3) { + const int32_t ne00, const int32_t ne01, const int32_t ne02, const int32_t ne03, + const int32_t nb01, const int32_t nb02, const int32_t nb03, + const int32_t ne10, const int32_t ne11, const int32_t ne12, const int32_t ne13, + const int32_t nb11, const int32_t nb12, const int64_t nb13, + const int32_t nb21, const int32_t nb22, const int64_t nb23, + const int32_t ne31, const int32_t ne32, const int32_t ne33, + const int32_t nb31, const int32_t nb32, const int64_t nb33) { #if defined(FLASH_ATTN_AVAILABLE) && (__CUDA_ARCH__ == GGML_CUDA_CC_VOLTA || (defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE))) // Skip unused kernel variants for faster compilation: if (use_logit_softcap && !(D == 128 || D == 256)) { @@ -95,17 +78,20 @@ static __global__ void flash_attn_ext_f1 constexpr int kqs_padded = FATTN_KQ_STRIDE + 8; constexpr int kqar = sizeof(KQ_acc_t)/sizeof(half); + const int sequence = blockIdx.z / ne02; + const int head = blockIdx.z - sequence*ne02; const int gqa_ratio = ne02 / ne12; // With grouped query attention there are > 1 Q matrices per K, V matrix. - const float * Q_f = (const float *) (Q + nb02* blockIdx.z + nb01*ic0); - const half * K_h = (const half *) (K + nb12*(blockIdx.z / gqa_ratio)); - const half * V_h = (const half *) (V + nb12*(blockIdx.z / gqa_ratio)); // K and V have same shape - const half * maskh = (const half *) (mask + nb32*(blockIdx.z % ne32) + nb31*ic0); - const half2 * mask2 = (const half2 *) maskh; + const float * Q_f = (const float *) (Q + nb03* sequence + nb02* head + nb01*ic0); + const half * K_h = (const half *) (K + nb13* sequence + nb12*(head / gqa_ratio)); + const half * V_h = (const half *) (V + nb13* sequence + nb12*(head / gqa_ratio)); // K and V have same shape + const half * maskh = (const half *) (mask + nb33*(sequence % ne33) + nb31*ic0); + const half2 * mask2 = (const half2 *) maskh; + const float * sinksf = (const float *) sinks; const int stride_Q = nb01 / sizeof(float); const int stride_KV = nb11 / sizeof(half); - const float slopef = get_alibi_slope(max_bias, blockIdx.z, n_head_log2, m0, m1); + const float slopef = get_alibi_slope(max_bias, head, n_head_log2, m0, m1); const half slopeh = __float2half(slopef); const half2 slope2 = make_half2(slopef, slopef); @@ -181,7 +167,8 @@ static __global__ void flash_attn_ext_f1 __syncthreads(); // Iterate over ne11 == previous tokens: - for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE; k_VKQ_0 < ne11; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE) { + const int k_VKQ_max = KV_max ? KV_max[sequence*gridDim.x + blockIdx.x] : ne11; + for (int k_VKQ_0 = blockIdx.y*FATTN_KQ_STRIDE; k_VKQ_0 < k_VKQ_max; k_VKQ_0 += gridDim.y*FATTN_KQ_STRIDE) { // Calculate tile of KQ: #pragma unroll for (int i_KQ_0 = 0; i_KQ_0 < FATTN_KQ_STRIDE; i_KQ_0 += KQ_stride_tc) { @@ -193,7 +180,7 @@ static __global__ void flash_attn_ext_f1 #pragma unroll for (int k_KQ_0 = 0; k_KQ_0 < D; k_KQ_0 += 16) { frag_a_K K_a; - wmma::load_matrix_sync(K_a, K_h + (k_VKQ_0 + i_KQ_0 + frag_m*threadIdx.y)*stride_KV + k_KQ_0, stride_KV); + wmma::load_matrix_sync(K_a, K_h + int64_t(k_VKQ_0 + i_KQ_0 + frag_m*threadIdx.y)*stride_KV + k_KQ_0, stride_KV); #pragma unroll for (int j = 0; j < ncols/frag_n; ++j) { wmma::mma_sync(KQ_c[j], K_a, Q_b[k_KQ_0/16][j], KQ_c[j]); @@ -340,7 +327,7 @@ static __global__ void flash_attn_ext_f1 const int k = k0 + (threadIdx.y % VKQ_ratio)*16; frag_a_V v_a; - wmma::load_matrix_sync(v_a, V_h + (k_VKQ_0 + k)*stride_KV + i_VKQ_0 + frag_m*(threadIdx.y/VKQ_ratio), stride_KV); + wmma::load_matrix_sync(v_a, V_h + int64_t(k_VKQ_0 + k)*stride_KV + i_VKQ_0 + frag_m*(threadIdx.y/VKQ_ratio), stride_KV); #pragma unroll for (int j = 0; j < ncols/frag_n; ++j) { wmma::mma_sync(VKQ_c[i_VKQ_0/VKQ_stride][j], v_a, KQ_b[k0/(VKQ_ratio*16)][j], VKQ_c[i_VKQ_0/VKQ_stride][j]); @@ -394,13 +381,59 @@ static __global__ void flash_attn_ext_f1 __syncthreads(); } + // Apply attention sinks + if (sinksf && blockIdx.y == 0) { + const float sinkf = sinksf[head]; + const half sinkh = __float2half(sinkf); + +#pragma unroll + for (int j0 = 0; j0 < ncols; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (std::is_same::value) { + float kqmax_new = fmaxf(KQ_max_f[j0/nwarps], sinkf); + + const float KQ_max_scale = expf(KQ_max_f[j0/nwarps] - kqmax_new); + KQ_max_f[j0/nwarps] = kqmax_new; + + KQ_rowsum_f[j0/nwarps] = KQ_rowsum_f[j0/nwarps] * KQ_max_scale + expf(sinkf - KQ_max_f[j0/nwarps]); + + const half2 scale_h2 = make_half2(KQ_max_scale, KQ_max_scale); +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + const int i = i0 + threadIdx.x; + if (i0 + warp_size > D/2 && i >= D/2) break; + VKQ2[j*(D_padded/2) + i] *= scale_h2; + } + } else { + half kqmax_old = __low2half(KQ_max_h2[j0/nwarps]); + half kqmax_new = fmaxf(kqmax_old, sinkh); + KQ_max_h2[j0/nwarps] = __half2half2(kqmax_new); + + const half KQ_max_scale_h = hexp(kqmax_old - kqmax_new); + const half2 KQ_max_scale = __half2half2(KQ_max_scale_h); + + KQ_rowsum_h2[j0/nwarps] = KQ_rowsum_h2[j0/nwarps] * KQ_max_scale; + const half val = hexp(sinkh - kqmax_new); + KQ_rowsum_h2[j0/nwarps].x = __hadd(KQ_rowsum_h2[j0/nwarps].x, val); + +#pragma unroll + for (int i0 = 0; i0 < D/2; i0 += warp_size) { + const int i = i0 + threadIdx.x; + if (i0 + warp_size > D/2 && i >= D/2) break; + VKQ2[j*(D_padded/2) + i] *= KQ_max_scale; + } + } + } + + __syncthreads(); + } #pragma unroll for (int j0 = 0; j0 < ncols; j0 += nwarps) { const int j_VKQ = j0 + threadIdx.y; if (ic0 + j_VKQ >= ne01) { return; } - const int j_dst = (ic0 + j_VKQ)*gridDim.y + blockIdx.y; float KQ_rowsum_j; if (std::is_same::value) { @@ -409,6 +442,8 @@ static __global__ void flash_attn_ext_f1 KQ_rowsum_j = __low2float(KQ_rowsum_h2[j0/nwarps]) + __high2float(KQ_rowsum_h2[j0/nwarps]); } + const int j_dst_unrolled = ((sequence*ne01 + ic0 + j_VKQ)*ne02 + head)*gridDim.y + blockIdx.y; + #pragma unroll for (int i0 = 0; i0 < D; i0 += warp_size) { const int i = i0 + threadIdx.x; @@ -419,7 +454,7 @@ static __global__ void flash_attn_ext_f1 if (gridDim.y == 1) { dst_val /= KQ_rowsum_j; } - dst[j_dst*gridDim.z*D + blockIdx.z*D + i] = dst_val; + dst[j_dst_unrolled*D + i] = dst_val; } if (gridDim.y == 1 || threadIdx.x != 0) { @@ -433,19 +468,18 @@ static __global__ void flash_attn_ext_f1 dst_meta_val.x = __low2float(KQ_max_h2[j0/nwarps]); } dst_meta_val.y = KQ_rowsum_j; - dst_meta[((ic0 + j_VKQ)*gridDim.z + blockIdx.z) * gridDim.y + blockIdx.y] = dst_meta_val; + dst_meta[j_dst_unrolled] = dst_meta_val; } #else - GGML_UNUSED(Q); GGML_UNUSED(K); GGML_UNUSED(V); GGML_UNUSED(mask); - GGML_UNUSED(dst); GGML_UNUSED(dst_meta); GGML_UNUSED(scale); - GGML_UNUSED(max_bias); GGML_UNUSED(m0); GGML_UNUSED(m1); - GGML_UNUSED(n_head_log2); GGML_UNUSED(logit_softcap); - GGML_UNUSED(ne00); GGML_UNUSED(ne01); GGML_UNUSED(ne02); GGML_UNUSED(ne03); - GGML_UNUSED(ne10); GGML_UNUSED(ne11); GGML_UNUSED(ne12); GGML_UNUSED(ne13); - GGML_UNUSED(ne31); GGML_UNUSED(ne32); GGML_UNUSED(nb31); GGML_UNUSED(nb32); GGML_UNUSED(nb01); GGML_UNUSED(nb02); - GGML_UNUSED(nb03); GGML_UNUSED(nb11); GGML_UNUSED(nb12); GGML_UNUSED(nb13); - GGML_UNUSED(nb21); GGML_UNUSED(nb22); GGML_UNUSED(nb23); - GGML_UNUSED(ne0); GGML_UNUSED(ne1); GGML_UNUSED(ne2); GGML_UNUSED(ne3); + GGML_UNUSED_VARS(Q, K, V, mask, sinks, KV_max, dst, dst_meta, scale, + max_bias, m0, m1, n_head_log2, logit_softcap, + ne00, ne01, ne02, ne03, + nb01, nb02, nb03, + ne10, ne11, ne12, ne13, + nb11, nb12, nb13, + nb21, nb22, nb23, + ne31, ne32, ne33, + nb31, nb32, nb33); NO_DEVICE_CODE; #endif // defined(FLASH_ATTN_AVAILABLE) && (__CUDA_ARCH__ == GGML_CUDA_CC_VOLTA || (defined(GGML_HIP_ROCWMMA_FATTN) && defined(FP16_MMA_AVAILABLE))) } @@ -561,7 +595,7 @@ void ggml_cuda_flash_attn_ext_wmma_f16(g return; } -#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#if !defined(GGML_USE_HIP) if (Q->ne[1] <= 8 && Q->ne[0] % warp_size == 0) { constexpr int cols_per_block = 8; switch (Q->ne[0]) { @@ -583,7 +617,7 @@ void ggml_cuda_flash_attn_ext_wmma_f16(g } return; } -#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) +#endif // !defined(GGML_USE_HIP) if (Q->ne[1] <= 32) { constexpr int cols_per_block = 16; diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn.cu 6641+dfsg-2/ggml/src/ggml-cuda/fattn.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,10 +1,8 @@ #include "common.cuh" #include "fattn-common.cuh" #include "fattn-mma-f16.cuh" -#include "fattn-tile-f16.cuh" -#include "fattn-tile-f32.cuh" -#include "fattn-vec-f16.cuh" -#include "fattn-vec-f32.cuh" +#include "fattn-tile.cuh" +#include "fattn-vec.cuh" #include "fattn-wmma-f16.cuh" #include "fattn.cuh" @@ -118,229 +116,218 @@ static void ggml_cuda_flash_attn_ext_mma } } -#define FATTN_VEC_F16_CASE(D, type_K, type_V) \ - if (Q->ne[0] == (D) && K->type == (type_K) && V->type == (type_V)) { \ - ggml_cuda_flash_attn_ext_vec_f16_case(ctx, dst); \ - return; \ - } \ +#define FATTN_VEC_CASE(D, type_K, type_V) \ + if (Q->ne[0] == (D) && K->type == (type_K) && V->type == (type_V)) { \ + ggml_cuda_flash_attn_ext_vec_case(ctx, dst); \ + return; \ + } \ + +#define FATTN_VEC_CASES_ALL_D(type_K, type_V) \ + FATTN_VEC_CASE( 64, type_K, type_V) \ + FATTN_VEC_CASE(128, type_K, type_V) \ + FATTN_VEC_CASE(256, type_K, type_V) \ -static void ggml_cuda_flash_attn_ext_vec_f16(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { +static void ggml_cuda_flash_attn_ext_vec(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { ggml_tensor * Q = dst->src[0]; ggml_tensor * K = dst->src[1]; ggml_tensor * V = dst->src[2]; #ifdef GGML_CUDA_FA_ALL_QUANTS - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16 ) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16) - - FATTN_VEC_F16_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_F16) + + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q4_0) + + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q4_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q4_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q4_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q4_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q4_1) + + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q5_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q5_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q5_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q5_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q5_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q5_0) + + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q5_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q5_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q5_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q5_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q5_1) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q5_1) + + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_1, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_0, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q5_1, GGML_TYPE_Q8_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) #else - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) - - FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) - - FATTN_VEC_F16_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16) - FATTN_VEC_F16_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_F16, GGML_TYPE_F16) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) + FATTN_VEC_CASES_ALL_D(GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) #endif // GGML_CUDA_FA_ALL_QUANTS - on_no_fattn_vec_case(Q->ne[0]); + GGML_ABORT("fatal error"); } -#define FATTN_VEC_F32_CASE(D, type_K, type_V) \ - if (Q->ne[0] == (D) && K->type == (type_K) && V->type == (type_V)) { \ - ggml_cuda_flash_attn_ext_vec_f32_case(ctx, dst); \ - return; \ - } \ +// Best FlashAttention kernel for a specific GPU: +enum best_fattn_kernel { + BEST_FATTN_KERNEL_NONE = 0, + BEST_FATTN_KERNEL_TILE = 200, + BEST_FATTN_KERNEL_VEC = 100, + BEST_FATTN_KERNEL_WMMA_F16 = 300, + BEST_FATTN_KERNEL_MMA_F16 = 400, +}; + +static best_fattn_kernel ggml_cuda_get_best_fattn_kernel(const int device, const ggml_tensor * dst) { +#ifndef FLASH_ATTN_AVAILABLE + GGML_UNUSED(device); GGML_UNUSED(dst); + return BEST_FATTN_KERNEL_NONE; +#endif// FLASH_ATTN_AVAILABLE + + const ggml_tensor * Q = dst->src[0]; + const ggml_tensor * K = dst->src[1]; + const ggml_tensor * V = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; -static void ggml_cuda_flash_attn_ext_vec_f32(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - ggml_tensor * Q = dst->src[0]; - ggml_tensor * K = dst->src[1]; - ggml_tensor * V = dst->src[2]; + const int gqa_ratio = Q->ne[2] / K->ne[2]; + GGML_ASSERT(Q->ne[2] % K->ne[2] == 0); -#ifdef GGML_CUDA_FA_ALL_QUANTS - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0) - - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16) + const int cc = ggml_cuda_info().devices[device].cc; - FATTN_VEC_F32_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16) -#else - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0) + switch (K->ne[0]) { + case 64: + case 128: + case 256: + if (V->ne[0] != K->ne[0]) { + return BEST_FATTN_KERNEL_NONE; + } + break; + case 80: + case 96: + case 112: + if (V->ne[0] != K->ne[0]) { + return BEST_FATTN_KERNEL_NONE; + } + if (!fp16_mma_available(cc) && !turing_mma_available(cc)) { + return BEST_FATTN_KERNEL_NONE; + } + break; + case 576: + if (V->ne[0] != 512) { + return BEST_FATTN_KERNEL_NONE; + } + if (!turing_mma_available(cc) || gqa_ratio % 16 != 0) { + return BEST_FATTN_KERNEL_NONE; + } + break; + default: + return BEST_FATTN_KERNEL_NONE; + } - FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0) +#ifndef GGML_CUDA_FA_ALL_QUANTS + if (K->type != V->type) { + return BEST_FATTN_KERNEL_NONE; + } +#endif // GGML_CUDA_FA_ALL_QUANTS - FATTN_VEC_F32_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16) - FATTN_VEC_F32_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16) + switch (K->type) { + case GGML_TYPE_F16: + break; + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: +#ifndef GGML_CUDA_FA_ALL_QUANTS + return BEST_FATTN_KERNEL_NONE; #endif // GGML_CUDA_FA_ALL_QUANTS + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q8_0: + break; + default: + return BEST_FATTN_KERNEL_NONE; + } - on_no_fattn_vec_case(Q->ne[0]); -} + if (mask && mask->ne[2] != 1) { + return BEST_FATTN_KERNEL_NONE; + } -void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * KQV = dst; - const ggml_tensor * Q = dst->src[0]; - const ggml_tensor * K = dst->src[1]; - const ggml_tensor * V = dst->src[2]; - const ggml_tensor * mask = dst->src[3]; + const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % 64 == 0; - ggml_cuda_set_device(ctx.device); - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; - const int warp_size = ggml_cuda_info().devices[ggml_cuda_get_device()].warp_size; - const enum ggml_prec prec = ggml_flash_attn_ext_get_prec(KQV); + // If Turing tensor cores available, use them except for some cases with batch size 1: + if (turing_mma_available(cc)) { + best_fattn_kernel best = BEST_FATTN_KERNEL_MMA_F16; - if (GGML_CUDA_CC_IS_AMD(cc)) { -#if defined(GGML_HIP_ROCWMMA_FATTN) - if (fp16_mma_available(cc)) { - ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); - return; + if (can_use_vector_kernel) { + if (K->type == GGML_TYPE_F16 && V->type == GGML_TYPE_F16) { + if (cc >= GGML_CUDA_CC_ADA_LOVELACE && Q->ne[1] == 1 && Q->ne[3] == 1 && !(gqa_ratio > 4 && K->ne[1] >= 8192)) { + best = BEST_FATTN_KERNEL_VEC; + } + } else { + if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { + if (Q->ne[1] <= 2) { + best = BEST_FATTN_KERNEL_VEC; + } + } else { + if (Q->ne[1] == 1) { + best = BEST_FATTN_KERNEL_VEC; + } + } + } + if ((gqa_ratio % 2 != 0 || !mask) && Q->ne[1] == 1) { + best = BEST_FATTN_KERNEL_VEC; // GQA-specific optimizations in the mma kernel do not apply. + } } -#endif // defined(GGML_HIP_ROCWMMA_FATTN) - // On AMD the tile kernels perform poorly, use the vec kernel instead: - if (prec == GGML_PREC_DEFAULT && fast_fp16_available(cc)) { - ggml_cuda_flash_attn_ext_vec_f16(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_vec_f32(ctx, dst); - } - return; + return best; } - if (!fast_fp16_available(cc)) { - if (Q->ne[1] <= 8 || Q->ne[0] == 256) { - ggml_cuda_flash_attn_ext_vec_f32(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_tile_f32(ctx, dst); - } - return; + // Use kernels specialized for small batch sizes if possible: + if (Q->ne[1] <= 8 && can_use_vector_kernel) { + return BEST_FATTN_KERNEL_VEC; } - if (!fp16_mma_available(cc)) { - if (prec == GGML_PREC_DEFAULT) { - if (Q->ne[1] <= 8 || Q->ne[0] == 256) { - ggml_cuda_flash_attn_ext_vec_f16(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_tile_f16(ctx, dst); - } - } else { - if (Q->ne[1] <= 8 || Q->ne[0] == 256) { - ggml_cuda_flash_attn_ext_vec_f32(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_tile_f32(ctx, dst); - } - } - return; + // For large batch sizes, use the WMMA kernel if possible: + if (fp16_mma_available(cc)) { + return BEST_FATTN_KERNEL_WMMA_F16; } - const bool gqa_opt_applies = ((Q->ne[2] / K->ne[2]) % 2 == 0) && mask; // The mma-based kernels have GQA-specific optimizations - const bool mma_needs_data_conversion = K->type != GGML_TYPE_F16 || V->type != GGML_TYPE_F16; - const bool mma_faster_for_bs1 = new_mma_available(cc) && gqa_opt_applies && cc < GGML_CUDA_CC_ADA_LOVELACE && !mma_needs_data_conversion; - const bool can_use_vector_kernel = Q->ne[0] <= 256 && Q->ne[0] % (2*warp_size) == 0; - if (Q->ne[1] == 1 && can_use_vector_kernel && !mma_faster_for_bs1) { - if (prec == GGML_PREC_DEFAULT) { - ggml_cuda_flash_attn_ext_vec_f16(ctx, dst); - } else { - ggml_cuda_flash_attn_ext_vec_f32(ctx, dst); - } - return; - } + // If there is no suitable kernel for tensor cores or small batch sizes, use the generic kernel for large batch sizes: + return BEST_FATTN_KERNEL_TILE; +} - // The MMA implementation needs Turing or newer, use the old WMMA code for Volta: - if (fp16_mma_available(cc) && !new_mma_available(cc)) { - ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); - return; +void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + ggml_cuda_set_device(ctx.device); + switch (ggml_cuda_get_best_fattn_kernel(ggml_cuda_get_device(), dst)) { + case BEST_FATTN_KERNEL_NONE: + GGML_ABORT("fatal error"); + case BEST_FATTN_KERNEL_TILE: + ggml_cuda_flash_attn_ext_tile(ctx, dst); + break; + case BEST_FATTN_KERNEL_VEC: + ggml_cuda_flash_attn_ext_vec(ctx, dst); + break; + case BEST_FATTN_KERNEL_WMMA_F16: + ggml_cuda_flash_attn_ext_wmma_f16(ctx, dst); + break; + case BEST_FATTN_KERNEL_MMA_F16: + ggml_cuda_flash_attn_ext_mma_f16(ctx, dst); + break; } +} - ggml_cuda_flash_attn_ext_mma_f16(ctx, dst); +bool ggml_cuda_flash_attn_ext_supported(int device, const ggml_tensor * dst) { + return ggml_cuda_get_best_fattn_kernel(device, dst) != BEST_FATTN_KERNEL_NONE; } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/fattn.cuh 6641+dfsg-2/ggml/src/ggml-cuda/fattn.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/fattn.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/fattn.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -1,3 +1,5 @@ #include "common.cuh" void ggml_cuda_flash_attn_ext(ggml_backend_cuda_context & ctx, ggml_tensor * dst); + +bool ggml_cuda_flash_attn_ext_supported(int device, const ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/getrows.cu 6641+dfsg-2/ggml/src/ggml-cuda/getrows.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/getrows.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/getrows.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,68 +1,71 @@ #include "getrows.cuh" #include "dequantize.cuh" +#include "convert.cuh" template static __global__ void k_get_rows( const void * __restrict__ src0, const int32_t * __restrict__ src1, dst_t * __restrict__ dst, const int64_t ne00, /*const int64_t ne01, const int64_t ne02, const int64_t ne03,*/ - /*const int64_t ne10, const int64_t ne11,*/ const int64_t ne12, /*const int64_t ne13,*/ + /*const int64_t ne10,*/ const int64_t ne11, const int64_t ne12, /*const int64_t ne13,*/ /*const size_t s0,*/ const size_t s1, const size_t s2, const size_t s3, /*const size_t nb00,*/ const size_t nb01, const size_t nb02, const size_t nb03, const size_t s10, const size_t s11, const size_t s12/*, const size_t s13*/) { - // The x and y dimensions of the grid are swapped because the maximum allowed grid size for x is higher. - const int i00 = (blockIdx.y * blockDim.x + threadIdx.x)*2; - const int i10 = blockIdx.x; - const int i11 = blockIdx.z / ne12; - const int i12 = blockIdx.z % ne12; + for (int64_t z = blockIdx.z; z < ne11*ne12; z += gridDim.z) { + for (int64_t i00 = 2*(blockIdx.y*blockDim.x + threadIdx.x); i00 < ne00; i00 += gridDim.y*blockDim.x) { + // The x and y dimensions of the grid are swapped because the maximum allowed grid size for x is higher. + const int i10 = blockIdx.x; + const int i11 = z / ne12; // TODO fastdiv + const int i12 = z % ne12; + + const int i01 = src1[i10*s10 + i11*s11 + i12*s12]; + + dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; + const void * src0_row = (const char *) src0 + i01*nb01 + i11*nb02 + i12*nb03; + + const int ib = i00/qk; // block index + const int iqs = (i00%qk)/qr; // quant index + const int iybs = i00 - i00%qk; // dst block start index + const int y_offset = qr == 1 ? 1 : qk/2; + + // dequantize + float2 v; + dequantize_kernel(src0_row, ib, iqs, v); - if (i00 >= ne00) { - return; + dst_row[iybs + iqs + 0] = ggml_cuda_cast(v.x); + dst_row[iybs + iqs + y_offset] = ggml_cuda_cast(v.y); + } } - - const int i01 = src1[i10*s10 + i11*s11 + i12*s12]; - - dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; - const void * src0_row = (const char *) src0 + i01*nb01 + i11*nb02 + i12*nb03; - - const int ib = i00/qk; // block index - const int iqs = (i00%qk)/qr; // quant index - const int iybs = i00 - i00%qk; // dst block start index - const int y_offset = qr == 1 ? 1 : qk/2; - - // dequantize - dfloat2 v; - dequantize_kernel(src0_row, ib, iqs, v); - - dst_row[iybs + iqs + 0] = float(v.x); - dst_row[iybs + iqs + y_offset] = float(v.y); } template static __global__ void k_get_rows_float( const src0_t * __restrict__ src0, const int32_t * __restrict__ src1, dst_t * __restrict__ dst, const int64_t ne00, /*const int64_t ne01, const int64_t ne02, const int64_t ne03,*/ - /*const int64_t ne10, const int64_t ne11,*/ const int64_t ne12, /*const int64_t ne13,*/ + /*const int64_t ne10,*/ const int64_t ne11, const int64_t ne12, /*const int64_t ne13,*/ /*const size_t s0,*/ const size_t s1, const size_t s2, const size_t s3, /*const size_t nb00,*/ const size_t nb01, const size_t nb02, const size_t nb03, const size_t s10, const size_t s11, const size_t s12/*, const size_t s13*/) { - // The x and y dimensions of the grid are swapped because the maximum allowed grid size for x is higher. - const int i00 = blockIdx.y * blockDim.x + threadIdx.x; - const int i10 = blockIdx.x; - const int i11 = blockIdx.z / ne12; - const int i12 = blockIdx.z % ne12; + for (int64_t z = blockIdx.z; z < ne11*ne12; z += gridDim.z) { + for (int64_t i00 = blockIdx.y*blockDim.x + threadIdx.x; i00 < ne00; i00 += gridDim.y*blockDim.x) { + // The x and y dimensions of the grid are swapped because the maximum allowed grid size for x is higher. + const int i10 = blockIdx.x; + const int i11 = z / ne12; // TODO fastdiv + const int i12 = z % ne12; + + if (i00 >= ne00) { + return; + } - if (i00 >= ne00) { - return; - } - - const int i01 = src1[i10*s10 + i11*s11 + i12*s12]; + const int i01 = src1[i10*s10 + i11*s11 + i12*s12]; - dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; - const src0_t * src0_row = (const src0_t *)((const char *) src0 + i01*nb01 + i11*nb02 + i12*nb03); + dst_t * dst_row = dst + i10*s1 + i11*s2 + i12*s3; + const src0_t * src0_row = (const src0_t *)((const char *) src0 + i01*nb01 + i11*nb02 + i12*nb03); - dst_row[i00] = float(src0_row[i00]); + dst_row[i00] = ggml_cuda_cast(src0_row[i00]); + } + } } template @@ -97,7 +100,7 @@ static void get_rows_cuda_q( cudaStream_t stream) { const dim3 block_dims(CUDA_GET_ROWS_BLOCK_SIZE, 1, 1); const int block_num_y = (ne00 + 2*CUDA_GET_ROWS_BLOCK_SIZE - 1) / (2*CUDA_GET_ROWS_BLOCK_SIZE); - const dim3 block_nums(ne10, block_num_y, ne11*ne12); + const dim3 block_nums(ne10, MIN(block_num_y, UINT16_MAX), MIN(ne11*ne12, UINT16_MAX)); // strides in elements // const size_t s0 = nb0 / sizeof(dst_t); @@ -115,7 +118,7 @@ static void get_rows_cuda_q( k_get_rows<<>>( src0_d, src1_d, dst_d, ne00, /*ne01, ne02, ne03,*/ - /*ne10, ne11,*/ ne12, /*ne13,*/ + /*ne10,*/ ne11, ne12, /*ne13,*/ /* s0,*/ s1, s2, s3, /* nb00,*/ nb01, nb02, nb03, s10, s11, s12/*, s13*/); @@ -130,7 +133,7 @@ static void get_rows_cuda_float( cudaStream_t stream) { const dim3 block_dims(CUDA_GET_ROWS_BLOCK_SIZE, 1, 1); const int block_num_y = (ne00 + CUDA_GET_ROWS_BLOCK_SIZE - 1) / CUDA_GET_ROWS_BLOCK_SIZE; - const dim3 block_nums(ne10, block_num_y, ne11*ne12); + const dim3 block_nums(ne10, MIN(block_num_y, UINT16_MAX), MIN(ne11*ne12, UINT16_MAX)); // strides in elements // const size_t s0 = nb0 / sizeof(dst_t); @@ -146,7 +149,7 @@ static void get_rows_cuda_float( k_get_rows_float<<>>( src0_d, src1_d, dst_d, ne00, /*ne01, ne02, ne03,*/ - /*ne10, ne11,*/ ne12, /*ne13,*/ + /*ne10,*/ ne11, ne12, /*ne13,*/ /* s0,*/ s1, s2, s3, /* nb00,*/ nb01, nb02, nb03, s10, s11, s12/*, s13*/); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/ggml-cuda.cu 6641+dfsg-2/ggml/src/ggml-cuda/ggml-cuda.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/ggml-cuda.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/ggml-cuda.cu 2025-09-30 07:36:33.000000000 +0000 @@ -4,6 +4,7 @@ #include "ggml-cuda/common.cuh" #include "ggml-cuda/acc.cuh" +#include "ggml-cuda/add-id.cuh" #include "ggml-cuda/arange.cuh" #include "ggml-cuda/argmax.cuh" #include "ggml-cuda/argsort.cuh" @@ -11,6 +12,7 @@ #include "ggml-cuda/clamp.cuh" #include "ggml-cuda/concat.cuh" #include "ggml-cuda/conv-transpose-1d.cuh" +#include "ggml-cuda/conv2d.cuh" #include "ggml-cuda/conv2d-dw.cuh" #include "ggml-cuda/conv2d-transpose.cuh" #include "ggml-cuda/convert.cuh" @@ -21,17 +23,21 @@ #include "ggml-cuda/fattn.cuh" #include "ggml-cuda/getrows.cuh" #include "ggml-cuda/im2col.cuh" +#include "ggml-cuda/mmf.cuh" #include "ggml-cuda/mmq.cuh" -#include "ggml-cuda/mmv.cuh" +#include "ggml-cuda/mmvf.cuh" #include "ggml-cuda/mmvq.cuh" #include "ggml-cuda/norm.cuh" #include "ggml-cuda/opt-step-adamw.cuh" +#include "ggml-cuda/opt-step-sgd.cuh" #include "ggml-cuda/out-prod.cuh" #include "ggml-cuda/pad.cuh" #include "ggml-cuda/pool2d.cuh" #include "ggml-cuda/quantize.cuh" #include "ggml-cuda/rope.cuh" +#include "ggml-cuda/roll.cuh" #include "ggml-cuda/scale.cuh" +#include "ggml-cuda/softcap.cuh" #include "ggml-cuda/softmax.cuh" #include "ggml-cuda/ssm-conv.cuh" #include "ggml-cuda/ssm-scan.cuh" @@ -39,11 +45,13 @@ #include "ggml-cuda/sumrows.cuh" #include "ggml-cuda/mean.cuh" #include "ggml-cuda/tsembd.cuh" +#include "ggml-cuda/topk-moe.cuh" #include "ggml-cuda/unary.cuh" #include "ggml-cuda/upscale.cuh" #include "ggml-cuda/wkv.cuh" #include "ggml-cuda/gla.cuh" #include "ggml-cuda/set-rows.cuh" +#include "ggml-cuda/pad_reflect_1d.cuh" #include "ggml.h" #include @@ -55,6 +63,7 @@ #include #include #include +#include #include #include #include @@ -125,7 +134,7 @@ static cudaError_t ggml_cuda_device_mall return err; } -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) static int ggml_cuda_parse_id(char devName[]) { // A list of possible Target IDs can be found under the rocclr/clr repo in device.cpp // these values are not stable so this is susceptible to breakage @@ -172,33 +181,9 @@ static int ggml_cuda_parse_id(char devNa archNum += archMinor; return archNum; } -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) static ggml_cuda_device_info ggml_cuda_init() { -#ifdef __HIP_PLATFORM_AMD__ - // Workaround for a rocBLAS bug when using multiple graphics cards: - // https://github.com/ROCmSoftwarePlatform/rocBLAS/issues/1346 - { - int major_version = 0; - size_t version_length = 0; - if (rocblas_get_version_string_size(&version_length) == rocblas_status_success) { - std::vector version(version_length+1, '\0'); - if (rocblas_get_version_string(version.data(), version.size()) == rocblas_status_success) { - version.resize(::strlen(version.data())); - int parsed_value = 0; - if (std::from_chars(version.data(), version.data() + version.size(), parsed_value).ec == std::errc()) { - major_version = parsed_value; - } - } - } - if (major_version < 4) { - GGML_LOG_DEBUG(GGML_CUDA_NAME " calling rocblas_initialize as a workaround for a rocBLAS bug\n"); - rocblas_initialize(); - CUDA_CHECK(cudaDeviceSynchronize()); - } - } -#endif - ggml_cuda_device_info info = {}; cudaError_t err = cudaGetDeviceCount(&info.device_count); @@ -221,6 +206,8 @@ static ggml_cuda_device_info ggml_cuda_i GGML_LOG_INFO("%s: GGML_CUDA_FORCE_CUBLAS: no\n", __func__); #endif // GGML_CUDA_FORCE_CUBLAS GGML_LOG_INFO("%s: found %d " GGML_CUDA_NAME " devices:\n", __func__, info.device_count); + + std::vector> turing_devices_without_mma; for (int id = 0; id < info.device_count; ++id) { int device_vmm = 0; @@ -248,7 +235,7 @@ static ggml_cuda_device_info ggml_cuda_i info.devices[id].nsm = prop.multiProcessorCount; info.devices[id].smpb = prop.sharedMemPerBlock; info.devices[id].warp_size = prop.warpSize; -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) info.devices[id].smpbo = prop.sharedMemPerBlock; info.devices[id].cc = ggml_cuda_parse_id(prop.gcnArchName); @@ -278,7 +265,25 @@ static ggml_cuda_device_info ggml_cuda_i info.devices[id].cc = 100*prop.major + 10*prop.minor; GGML_LOG_INFO(" Device %d: %s, compute capability %d.%d, VMM: %s\n", id, prop.name, prop.major, prop.minor, device_vmm ? "yes" : "no"); -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) + std::string device_name(prop.name); + if (device_name == "NVIDIA GeForce MX450") { + turing_devices_without_mma.push_back({ id, device_name }); + } else if (device_name == "NVIDIA GeForce MX550") { + turing_devices_without_mma.push_back({ id, device_name }); + } else if (device_name.substr(0, 21) == "NVIDIA GeForce GTX 16") { + turing_devices_without_mma.push_back({ id, device_name }); + } +#endif // defined(GGML_USE_HIP) + } + + if (ggml_cuda_highest_compiled_arch(GGML_CUDA_CC_TURING) >= GGML_CUDA_CC_TURING && !turing_devices_without_mma.empty()) { + GGML_LOG_INFO("The following devices will have suboptimal performance due to a lack of tensor cores:\n"); + for (size_t device_pos = 0; device_pos < turing_devices_without_mma.size(); device_pos++) { + GGML_LOG_INFO( + " Device %d: %s\n", turing_devices_without_mma[device_pos].first, turing_devices_without_mma[device_pos].second.c_str()); + } + GGML_LOG_INFO( + "Consider compiling with CMAKE_CUDA_ARCHITECTURES=61-virtual;80-virtual and DGGML_CUDA_FORCE_MMQ to force the use of the Pascal code for Turing.\n"); } for (int id = 0; id < info.device_count; ++id) { @@ -1346,9 +1351,7 @@ static void ggml_cuda_op_mul_mat_cublas( &beta, dst_dd_i, ldc)); } - GGML_UNUSED(dst); - GGML_UNUSED(src1_ddq_i); - GGML_UNUSED(src1_padded_row_size); + GGML_UNUSED_VARS(dst, src1_ddq_i, src1_padded_row_size); } static void ggml_cuda_set_peer_access(const int n_tokens, int main_device) { @@ -1849,6 +1852,9 @@ static void ggml_cuda_mul_mat_batched_cu ggml_cuda_pool_alloc src0_alloc(ctx.pool()); ggml_cuda_pool_alloc src1_alloc(ctx.pool()); + bool is_src0_cont_2 = ggml_is_contiguous_2(src0); + bool is_src1_cont_2 = ggml_is_contiguous_2(src1); + // Handle src0 src0_ptr = (const cuda_t *) src0->data; @@ -1867,6 +1873,8 @@ static void ggml_cuda_mul_mat_batched_cu s11 = ne10; s12 = ne11*s11; s13 = ne12*s12; + + is_src1_cont_2 = true; } // Setup destination buffer @@ -1915,15 +1923,19 @@ static void ggml_cuda_mul_mat_batched_cu const int64_t r2 = ne12/ne02; const int64_t r3 = ne13/ne03; - if (r2 == 1 && r3 == 1 && ggml_is_contiguous_2(src0) && ggml_is_contiguous_2(src1)) { + if (r2 == 1 && r3 == 1 && is_src0_cont_2 && is_src1_cont_2) { + // with a [0, 2, 1, 3] perm. and ne02==1 the matrix strides need to be determined from dim 3: + const int64_t sma = ne02 == 1 ? nb03/nb00 : nb02/nb00; + const int64_t smb = ne12 == 1 ? s13 : s12; + // there is no broadcast and src0, src1 are contiguous across dims 2, 3 // use cublasGemmStridedBatchedEx CUBLAS_CHECK( cublasGemmStridedBatchedEx(ctx.cublas_handle(), CUBLAS_OP_T, CUBLAS_OP_N, ne01, ne11, ne10, - alpha, src0_ptr, cu_data_type_a, nb01/nb00, nb02/nb00, // strideA - src1_ptr, cu_data_type_b, s11, s12, // strideB - beta, dst_t, cu_data_type, ne0, ne1*ne0, // strideC + alpha, src0_ptr, cu_data_type_a, nb01/nb00, sma, // strideA + src1_ptr, cu_data_type_b, s11, smb, // strideB + beta, dst_t, cu_data_type, ne0, ne1*ne0, // strideC ne12*ne13, cu_compute_type, CUBLAS_GEMM_DEFAULT_TENSOR_OP)); @@ -1995,7 +2007,9 @@ static void ggml_cuda_mul_mat(ggml_backe const bool bad_padding_clear = ggml_backend_buffer_get_usage(src0->buffer) == GGML_BACKEND_BUFFER_USAGE_COMPUTE && ggml_nbytes(src0) != ggml_backend_buffer_get_alloc_size(src0->buffer, src0) && src0->view_src; - bool use_mul_mat_vec = (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_BF16) + bool use_mul_mat_vec_f = (src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_BF16) + && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; + bool use_mul_mat_f = !ggml_is_quantized(src0->type) && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32; bool use_mul_mat_vec_q = ggml_is_quantized(src0->type) && !bad_padding_clear && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 @@ -2015,14 +2029,18 @@ static void ggml_cuda_mul_mat(ggml_backe } const int cc = ggml_cuda_info().devices[id].cc; + const int warp_size = ggml_cuda_info().devices[id].warp_size; use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]); - use_mul_mat_vec = use_mul_mat_vec && ggml_cuda_should_use_mmv(src0->type, cc, src0->ne, src1->ne[1]); + use_mul_mat_f = use_mul_mat_f && ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src1->ne[1], /*mul_mat_id=*/false); + use_mul_mat_vec_f = use_mul_mat_vec_f && ggml_cuda_should_use_mmvf(src0->type, cc, src0->ne, src1->ne[1]); any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_hardware_available(cc); } } else { const int cc = ggml_cuda_info().devices[ctx.device].cc; + const int warp_size = ggml_cuda_info().devices[ctx.device].warp_size; use_mul_mat_q = use_mul_mat_q && ggml_cuda_should_use_mmq(src0->type, cc, src1->ne[1]); - use_mul_mat_vec = use_mul_mat_vec && ggml_cuda_should_use_mmv(src0->type, cc, src0->ne, src1->ne[1]); + use_mul_mat_f = use_mul_mat_f && ggml_cuda_should_use_mmf(src0->type, cc, warp_size, src0->ne, src1->ne[1], /*mul_mat_id=*/false); + use_mul_mat_vec_f = use_mul_mat_vec_f && ggml_cuda_should_use_mmvf(src0->type, cc, src0->ne, src1->ne[1]); any_gpus_with_slow_fp16 = any_gpus_with_slow_fp16 || !fast_fp16_hardware_available(cc); } @@ -2035,15 +2053,17 @@ static void ggml_cuda_mul_mat(ggml_backe //printf("src1 is contiguous %d, transposed %d, type = %s, name = %s\n", ggml_is_contiguous(src1), ggml_is_transposed(src1), ggml_type_name(src1->type), src1->name); //TODO update for generic tensor parallelism - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; bool use_batched_cublas_f16 = src0->type == GGML_TYPE_F16 && (src1->type == GGML_TYPE_F16 || !any_gpus_with_slow_fp16); bool use_batched_cublas_bf16 = src0->type == GGML_TYPE_BF16 && bf16_mma_hardware_available(cc); bool use_batched_cublas_f32 = src0->type == GGML_TYPE_F32; - if (!split && use_mul_mat_vec) { + if (!split && use_mul_mat_vec_f) { // the custom F16 vector kernel can be used over batched cuBLAS GEMM // but this is only faster for GPUs without tensor cores or with a thin src0 matrix (particularly KQV in attention) - ggml_cuda_mul_mat_vec(ctx, src0, src1, nullptr, dst); + ggml_cuda_mul_mat_vec_f(ctx, src0, src1, nullptr, dst); + } else if (!split && use_mul_mat_f) { + ggml_cuda_mul_mat_f(ctx, src0, src1, nullptr, dst); } else if (!split && use_mul_mat_vec_q) { ggml_cuda_mul_mat_vec_q(ctx, src0, src1, nullptr, dst); } else if (!split && use_mul_mat_q) { @@ -2052,8 +2072,8 @@ static void ggml_cuda_mul_mat(ggml_backe && !ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1->ne[2]*src1->ne[3] > 1) { // general KQ + KQV multi-batch without FlashAttention ggml_cuda_mul_mat_batched_cublas(ctx, src0, src1, dst); - } else if (use_mul_mat_vec) { - ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec, nullptr); + } else if (use_mul_mat_vec_f) { + ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_f, nullptr); } else if (use_mul_mat_vec_q) { ggml_cuda_op_mul_mat(ctx, src0, src1, dst, ggml_cuda_op_mul_mat_vec_q, quantize_row_q8_1_cuda); } else if (use_mul_mat_q) { @@ -2081,7 +2101,7 @@ static void ggml_cuda_mul_mat_id(ggml_ba if (ggml_is_quantized(src0->type)) { ggml_cuda_mul_mat_vec_q(ctx, src0, src1, ids, dst); } else { - ggml_cuda_mul_mat_vec(ctx, src0, src1, ids, dst); + ggml_cuda_mul_mat_vec_f(ctx, src0, src1, ids, dst); } return; } @@ -2090,6 +2110,11 @@ static void ggml_cuda_mul_mat_id(ggml_ba ggml_cuda_mul_mat_q(ctx, src0, src1, ids, dst); return; } + + if (ggml_cuda_should_use_mmf(src0->type, cc, WARP_SIZE, src0->ne, src1->ne[2], /*mul_mat_id=*/true)) { + ggml_cuda_mul_mat_f(ctx, src0, src1, ids, dst); + return; + } } cudaStream_t stream = ctx.stream(); @@ -2247,6 +2272,9 @@ static bool ggml_cuda_compute_forward(gg case GGML_OP_ADD1: // TODO: more efficient implementation ggml_cuda_op_add(ctx, dst); break; + case GGML_OP_ADD_ID: + ggml_cuda_op_add_id(ctx, dst); + break; case GGML_OP_SUB: ggml_cuda_op_sub(ctx, dst); break; @@ -2303,6 +2331,9 @@ static bool ggml_cuda_compute_forward(gg case GGML_UNARY_OP_EXP: ggml_cuda_op_exp(ctx, dst); break; + case GGML_UNARY_OP_ELU: + ggml_cuda_op_elu(ctx, dst); + break; default: return false; } @@ -2318,6 +2349,9 @@ static bool ggml_cuda_compute_forward(gg case GGML_GLU_OP_SWIGLU: ggml_cuda_op_swiglu(ctx, dst); break; + case GGML_GLU_OP_SWIGLU_OAI: + ggml_cuda_op_swiglu_oai(ctx, dst); + break; case GGML_GLU_OP_GEGLU_ERF: ggml_cuda_op_geglu_erf(ctx, dst); break; @@ -2346,6 +2380,9 @@ static bool ggml_cuda_compute_forward(gg case GGML_OP_PAD: ggml_cuda_op_pad(ctx, dst); break; + case GGML_OP_PAD_REFLECT_1D: + ggml_cuda_op_pad_reflect_1d(ctx, dst); + break; case GGML_OP_ARANGE: ggml_cuda_op_arange(ctx, dst); break; @@ -2415,9 +2452,18 @@ static bool ggml_cuda_compute_forward(gg case GGML_OP_ROPE_BACK: ggml_cuda_op_rope_back(ctx, dst); break; + case GGML_OP_ROLL: + ggml_cuda_op_roll(ctx, dst); + break; case GGML_OP_IM2COL: ggml_cuda_op_im2col(ctx, dst); break; + case GGML_OP_IM2COL_3D: + ggml_cuda_op_im2col_3d(ctx, dst); + break; + case GGML_OP_CONV_2D: + ggml_cuda_op_conv2d(ctx, dst); + break; case GGML_OP_CONV_2D_DW: ggml_cuda_op_conv2d_dw(ctx, dst); break; @@ -2469,6 +2515,9 @@ static bool ggml_cuda_compute_forward(gg case GGML_OP_OPT_STEP_ADAMW: ggml_cuda_opt_step_adamw(ctx, dst); break; + case GGML_OP_OPT_STEP_SGD: + ggml_cuda_opt_step_sgd(ctx, dst); + break; default: return false; } @@ -2587,6 +2636,12 @@ static bool check_node_graph_compatibili // Loop over nodes in GGML graph to obtain info needed for CUDA graph cuda_ctx->cuda_graph->cpy_dest_ptrs.clear(); + const std::string gemma3n_per_layer_proj_src0_name = "inp_per_layer_selected"; + const std::string gemma3n_per_layer_proj_src1_name = "per_layer_proj"; + const std::string ffn_moe_gate_bias_prefix = "ffn_moe_gate_biased"; + const std::string ffn_moe_up_bias_prefix = "ffn_moe_up_biased"; + const std::string ffn_moe_down_bias_prefix = "ffn_moe_down_biased"; + for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2608,9 +2663,18 @@ static bool check_node_graph_compatibili #endif } - if (node->op == GGML_OP_ADD && node->src[1] && node->src[1]->ne[1] > 1) { - // disable CUDA graphs for batch size > 1 for now. - // Changes in batch size or context size can cause changes to the grid size of some kernels. + if (node->op == GGML_OP_ADD && + node->src[1] && node->src[1]->ne[1] > 1 && + (node->src[0] ? node->src[0]->name != gemma3n_per_layer_proj_src0_name : true) && + (node->src[1] ? node->src[1]->name != gemma3n_per_layer_proj_src1_name : true) && + strncmp(node->name, ffn_moe_gate_bias_prefix.c_str(), ffn_moe_gate_bias_prefix.size()) != 0 && + strncmp(node->name, ffn_moe_up_bias_prefix.c_str(), ffn_moe_up_bias_prefix.size()) != 0 && + strncmp(node->name, ffn_moe_down_bias_prefix.c_str(), ffn_moe_down_bias_prefix.size()) != 0) { + // disable CUDA graphs for batch size > 1 for now while excluding the matrix-matrix addition as part of Gemma3n's `project_per_layer_input` operation + // by means of matching node names. See + // https://github.com/ggml-org/llama.cpp/blob/f9a31eea06a859e34cecb88b4d020c7f03d86cc4/src/llama-model.cpp#L10199-L10241 and + // https://github.com/huggingface/transformers/blob/bda75b4011239d065de84aa3e744b67ebfa7b245/src/transformers/models/gemma3n/modeling_gemma3n.py#L1773, + // Generally, changes in batch size or context size can cause changes to the grid size of some kernels. use_cuda_graph = false; #ifndef NDEBUG GGML_LOG_DEBUG("%s: disabling CUDA graphs due to batch size > 1 [%s] [%ld %ld %ld %ld]\n", __func__, node->name, node->ne[0], node->ne[1], node->ne[2], node->ne[3]); @@ -2756,6 +2820,120 @@ static void update_cuda_graph_executable } #endif +static bool ggml_cuda_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops, std::initializer_list unary_ops) { +#ifndef NDEBUG + const size_t num_unary = std::count(ops.begin(), ops.end(), GGML_OP_UNARY); + GGML_ASSERT(unary_ops.size() == num_unary); +#endif + + //TODO: remove special case once ggml_can_fuse can handle empty nodes + std::initializer_list topk_moe_ops = ggml_cuda_topk_moe_ops(false); + std::initializer_list topk_moe_ops_with_norm = ggml_cuda_topk_moe_ops(true); + + if (ops.size() == topk_moe_ops_with_norm.size() && std::equal(ops.begin(), ops.end(), topk_moe_ops_with_norm.begin())) { + + if (node_idx + topk_moe_ops_with_norm.size() > (size_t)cgraph->n_nodes) { + return false; + } + + for (size_t i = 0; i < topk_moe_ops_with_norm.size(); i++) { + if (cgraph->nodes[node_idx + i]->op != topk_moe_ops_with_norm.begin()[i]) return false; + } + ggml_tensor * softmax = cgraph->nodes[node_idx]; + ggml_tensor * weights = cgraph->nodes[node_idx+8]; + + if (ggml_cuda_should_use_topk_moe(softmax, weights)) { + return true; + } + } + + if (ops.size() == topk_moe_ops.size() && std::equal(ops.begin(), ops.end(), topk_moe_ops.begin())) { + + if (node_idx + topk_moe_ops.size() > (size_t)cgraph->n_nodes) { + return false; + } + + for (size_t i = 0; i < topk_moe_ops.size(); i++) { + if (cgraph->nodes[node_idx + i]->op != topk_moe_ops.begin()[i]) return false; + } + + ggml_tensor * softmax = cgraph->nodes[node_idx]; + ggml_tensor * weights = cgraph->nodes[node_idx+4]; + if (ggml_cuda_should_use_topk_moe(softmax, weights)) { + return true; + } + } + + if (!ggml_can_fuse(cgraph, node_idx, ops)) { + return false; + } + + if ((ops.size() == 2 || ops.size() == 3) && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = nullptr; + + if (ops.size() == 3 && ops.begin()[2] == GGML_OP_ADD) { + add = cgraph->nodes[node_idx+2]; + } + + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); + + //rms norm only supports F32 + if (mul->src[0]->type != GGML_TYPE_F32 || + mul->src[1]->type != GGML_TYPE_F32 || + mul->type != GGML_TYPE_F32) { + return false; + } + + if (add && (add->src[0]->type != GGML_TYPE_F32 || + add->src[1]->type != GGML_TYPE_F32 || + add->type != GGML_TYPE_F32) ) { + return false; + } + + //if rms norm is the B operand, then we don't handle broadcast + if (rms_norm == mul->src[1] && !ggml_are_same_shape(mul->src[0], rms_norm->src[1])) { + return false; + } + + //rms_norm kernel assumes contigous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { + return false; + } + + if (add && (!ggml_is_contiguous(add->src[0]) || !ggml_is_contiguous_rows(add->src[1]))) { + return false; + } + + return true; + } + + if (ops.size() == 3 && ops.begin()[0] == GGML_OP_SCALE && ops.begin()[1] == GGML_OP_UNARY && ops.begin()[2] == GGML_OP_SCALE + && unary_ops.size() == 1 && unary_ops.begin()[0] == GGML_UNARY_OP_TANH) { + const ggml_tensor *scale = cgraph->nodes[node_idx]; + const ggml_tensor *tanh = cgraph->nodes[node_idx+1]; + const ggml_tensor *scale2 = cgraph->nodes[node_idx+2]; + + GGML_ASSERT(scale->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(scale->type == GGML_TYPE_F32); + + if (ggml_get_unary_op(tanh) != GGML_UNARY_OP_TANH) { + return false; + } + + // Check for bias + if (ggml_get_op_params_f32(scale, 1) != 0.0f || ggml_get_op_params_f32(scale2, 1) != 0.0f) { + return false; + } + + return true; + } + + return false; +} + static void evaluate_and_capture_cuda_graph(ggml_backend_cuda_context * cuda_ctx, ggml_cgraph * cgraph, bool & graph_evaluated_or_captured, bool & use_cuda_graph, bool & cuda_graph_update_required) { // flag used to determine whether it is an integrated_gpu @@ -2765,6 +2943,7 @@ static void evaluate_and_capture_cuda_gr // Only perform the graph execution if CUDA graphs are not enabled, or we are capturing the graph. // With the use of CUDA graphs, the execution will be performed by the graph launch. if (!use_cuda_graph || cuda_graph_update_required) { + for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2772,6 +2951,75 @@ static void evaluate_and_capture_cuda_gr continue; } + static bool disable_fusion = (getenv("GGML_CUDA_DISABLE_FUSION") != nullptr); + if (!disable_fusion) { + + if (ggml_cuda_can_fuse(cgraph, i, ggml_cuda_topk_moe_ops(/*with norm*/ true), {})) { + ggml_tensor * weights = cgraph->nodes[i+8]; + ggml_tensor * selected_experts = cgraph->nodes[i+3]; + ggml_cuda_op_topk_moe(*cuda_ctx, node, weights, selected_experts, /*with norm*/ true); + i += 8; + continue; + } + + if (ggml_cuda_can_fuse(cgraph, i, ggml_cuda_topk_moe_ops(/*with norm*/ false), {})) { + ggml_tensor * weights = cgraph->nodes[i+4]; + ggml_tensor * selected_experts = cgraph->nodes[i+3]; + ggml_cuda_op_topk_moe(*cuda_ctx, node, weights, selected_experts, /*with norm*/ false); + i += 4; + continue; + } + + if (node->op == GGML_OP_ADD) { + int n_fuse = 0; + ggml_op ops[8]; + std::fill(ops, ops + 8, GGML_OP_ADD); + + for (; n_fuse <= 6; ++n_fuse){ + if (!ggml_can_fuse(cgraph, i + n_fuse, ops + n_fuse, 2)) { + break; + } + if (cgraph->nodes[i + n_fuse] != cgraph->nodes[i + n_fuse + 1]->src[0]) { + break; + } + if (!ggml_are_same_layout(cgraph->nodes[i + n_fuse]->src[1], cgraph->nodes[i + n_fuse + 1]->src[1])) { + break; + } + } + + n_fuse++; + + if (n_fuse > 1) { + for (int j = 0; j < n_fuse - 1; ++j) { + node->src[j + 2] = cgraph->nodes[i + j + 1]->src[1]; + } + cgraph->nodes[i + n_fuse - 1]->data = node->data; + ggml_cuda_op_fused_add(*cuda_ctx, node, n_fuse); + i += n_fuse - 1; + + continue; + } + } + + + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL, GGML_OP_ADD}, {})) { + ggml_cuda_op_rms_norm_fused_add(*cuda_ctx, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL}, {})) { + ggml_cuda_op_rms_norm_fused(*cuda_ctx, node, cgraph->nodes[i+1]); + i++; + continue; + } + + if (ggml_cuda_can_fuse(cgraph, i, { GGML_OP_SCALE, GGML_OP_UNARY, GGML_OP_SCALE }, { GGML_UNARY_OP_TANH })) { + i += 2; + ggml_cuda_op_softcap(*cuda_ctx, cgraph->nodes[i], node); + continue; + } + } #ifndef NDEBUG assert(node->buffer->buft == ggml_backend_cuda_buffer_type(cuda_ctx->device)); for (int j = 0; j < GGML_MAX_SRC; j++) { @@ -2947,6 +3195,7 @@ static const ggml_backend_i ggml_backend /* .graph_compute = */ ggml_backend_cuda_graph_compute, /* .event_record = */ ggml_backend_cuda_event_record, /* .event_wait = */ ggml_backend_cuda_event_wait, + /* .graph_optimize = */ NULL, }; static ggml_guid_t ggml_backend_cuda_guid() { @@ -2979,7 +3228,7 @@ bool ggml_backend_cuda_register_host_buf return false; } -#if CUDART_VERSION >= 11010 || defined(GGML_USE_MUSA) +#if CUDART_VERSION >= 11010 || defined(GGML_USE_MUSA) || defined(GGML_USE_HIP) cudaError_t err = cudaHostRegister(buffer, size, cudaHostRegisterPortable | cudaHostRegisterReadOnly); if (err != cudaSuccess) { // clear the error @@ -3016,6 +3265,7 @@ struct ggml_backend_cuda_device_context int device; std::string name; std::string description; + std::string pci_bus_id; }; static const char * ggml_backend_cuda_device_get_name(ggml_backend_dev_t dev) { @@ -3040,9 +3290,12 @@ static enum ggml_backend_dev_type ggml_b } static void ggml_backend_cuda_device_get_props(ggml_backend_dev_t dev, ggml_backend_dev_props * props) { + ggml_backend_cuda_device_context * ctx = (ggml_backend_cuda_device_context *)dev->context; + props->name = ggml_backend_cuda_device_get_name(dev); props->description = ggml_backend_cuda_device_get_description(dev); props->type = ggml_backend_cuda_device_get_type(dev); + props->device_id = ctx->pci_bus_id.empty() ? nullptr : ctx->pci_bus_id.c_str(); ggml_backend_cuda_device_get_memory(dev, &props->memory_free, &props->memory_total); bool host_buffer = getenv("GGML_CUDA_NO_PINNED") == nullptr; @@ -3116,6 +3369,7 @@ static bool ggml_backend_cuda_device_sup case GGML_UNARY_OP_GELU_QUICK: case GGML_UNARY_OP_TANH: case GGML_UNARY_OP_EXP: + case GGML_UNARY_OP_ELU: return ggml_is_contiguous(op->src[0]); default: return false; @@ -3126,6 +3380,7 @@ static bool ggml_backend_cuda_device_sup case GGML_GLU_OP_REGLU: case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: return ggml_is_contiguous_1(op->src[0]); @@ -3176,6 +3431,7 @@ static bool ggml_backend_cuda_device_sup case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -3222,21 +3478,19 @@ static bool ggml_backend_cuda_device_sup } break; case GGML_OP_SET_ROWS: { - return (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16) && + return (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_BF16 || + op->type == GGML_TYPE_Q4_0 || op->type == GGML_TYPE_Q4_1 || op->type == GGML_TYPE_Q5_0 || + op->type == GGML_TYPE_Q5_1 || op->type == GGML_TYPE_Q8_0 || op->type == GGML_TYPE_IQ4_NL) && op->src[0]->type == GGML_TYPE_F32 && - op->src[1]->type == GGML_TYPE_I64; + (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); } break; case GGML_OP_CPY: { ggml_type src0_type = op->src[0]->type; ggml_type src1_type = op->src[1]->type; - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_F32) { - return true; - } - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_BF16) { - return true; - } - if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_F16) { + if ((src0_type == GGML_TYPE_F32 || src0_type == GGML_TYPE_BF16 || src0_type == GGML_TYPE_F16) && + (src1_type == GGML_TYPE_F32 || src1_type == GGML_TYPE_BF16 || src1_type == GGML_TYPE_F16) + ) { return true; } if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_Q8_0) { @@ -3272,10 +3526,10 @@ static bool ggml_backend_cuda_device_sup if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_IQ4_NL) { return true; } - if (src0_type == GGML_TYPE_F16 && src1_type == GGML_TYPE_F16) { + if (src0_type == GGML_TYPE_F32 && src1_type == GGML_TYPE_I32) { return true; } - if (src0_type == GGML_TYPE_F16 && src1_type == GGML_TYPE_F32) { + if (src0_type == GGML_TYPE_I32 && src1_type == GGML_TYPE_F32) { return true; } if (src0_type == src1_type && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1])) { @@ -3330,6 +3584,7 @@ static bool ggml_backend_cuda_device_sup case GGML_OP_PERMUTE: case GGML_OP_TRANSPOSE: case GGML_OP_ADD: + case GGML_OP_ADD_ID: case GGML_OP_ADD1: case GGML_OP_SUB: case GGML_OP_MUL: @@ -3358,7 +3613,7 @@ static bool ggml_backend_cuda_device_sup return op->src[0]->ne[1] % 128 == 0; } case GGML_OP_CONT: - return op->src[0]->type != GGML_TYPE_BF16; + return true; case GGML_OP_DIAG_MASK_INF: return true; case GGML_OP_SOFT_MAX: @@ -3368,24 +3623,34 @@ static bool ggml_backend_cuda_device_sup memcpy(&max_bias, (const float *) op->op_params + 1, sizeof(float)); return max_bias == 0.0f; } + case GGML_OP_ROLL: + if(op->src[0]->type == GGML_TYPE_F32) { + return true; + } + return false; case GGML_OP_ROPE: case GGML_OP_ROPE_BACK: { return op->src[0]->nb[0] == ggml_type_size(op->src[0]->type) && ggml_is_contiguous_2(op->src[0]); } case GGML_OP_IM2COL: + case GGML_OP_IM2COL_3D: + case GGML_OP_CONV_2D: case GGML_OP_CONV_2D_DW: case GGML_OP_CONV_TRANSPOSE_2D: case GGML_OP_POOL_2D: case GGML_OP_SUM: - case GGML_OP_SUM_ROWS: - case GGML_OP_MEAN: - case GGML_OP_ARGSORT: case GGML_OP_ACC: return true; + case GGML_OP_ARGSORT: + // TODO: Support arbitrary column width + return op->src[0]->ne[0] <= 1024; + case GGML_OP_SUM_ROWS: + case GGML_OP_MEAN: case GGML_OP_GROUP_NORM: + case GGML_OP_PAD: return ggml_is_contiguous(op->src[0]); case GGML_OP_UPSCALE: - case GGML_OP_PAD: + case GGML_OP_PAD_REFLECT_1D: case GGML_OP_ARANGE: case GGML_OP_TIMESTEP_EMBEDDING: case GGML_OP_LEAKY_RELU: @@ -3393,45 +3658,12 @@ static bool ggml_backend_cuda_device_sup case GGML_OP_GATED_LINEAR_ATTN: case GGML_OP_RWKV_WKV7: return true; - case GGML_OP_FLASH_ATTN_EXT: { -#ifndef FLASH_ATTN_AVAILABLE - return false; -#endif // FLASH_ATTN_AVAILABLE - if (op->src[1]->ne[0] != op->src[2]->ne[0]) { - const int cc = ggml_cuda_info().devices[dev_ctx->device].cc; - if (!new_mma_available(cc)) { - return false; - } - const int gqa_ratio = op->src[0]->ne[2] / op->src[1]->ne[2]; - return op->src[1]->ne[0] == 576 && op->src[2]->ne[0] == 512 && op->src[3] && gqa_ratio % 16 == 0; - } - if (op->src[0]->ne[0] == 192) { - return false; - } - // TODO: support broadcast - // note: this was initially implemented in https://github.com/ggml-org/llama.cpp/pull/14500, but - // the interface of ggml_flash_attn_ext() changed in https://github.com/ggml-org/llama.cpp/pull/14505 - if (op->src[0]->ne[3] != 1) { - return false; - } - if (op->src[1]->type == GGML_TYPE_BF16 || op->src[2]->type == GGML_TYPE_BF16) { - return false; - } - if (op->src[0]->ne[0] == 64 && op->src[1]->type == GGML_TYPE_F16) { - return true; - } - if (op->src[0]->ne[0] == 128) { - return true; - } - if (op->src[0]->ne[0] == 256 && op->src[1]->type == GGML_TYPE_F16 && op->src[2]->type == GGML_TYPE_F16) { - return true; - } - return fp16_mma_available(ggml_cuda_info().devices[dev_ctx->device].cc) && - op->src[1]->type == GGML_TYPE_F16 && op->src[2]->type == GGML_TYPE_F16; - } + case GGML_OP_FLASH_ATTN_EXT: + return ggml_cuda_flash_attn_ext_supported(dev_ctx->device, op); case GGML_OP_CROSS_ENTROPY_LOSS: case GGML_OP_CROSS_ENTROPY_LOSS_BACK: case GGML_OP_OPT_STEP_ADAMW: + case GGML_OP_OPT_STEP_SGD: return true; default: return false; @@ -3563,10 +3795,6 @@ static ggml_backend_feature * ggml_backe features.push_back({ "NO_PEER_COPY", "1" }); #endif - #ifdef GGML_CUDA_F16 - features.push_back({ "F16", "1" }); - #endif - #ifdef GGML_CUDA_USE_GRAPHS features.push_back({ "USE_GRAPHS", "1" }); #endif @@ -3637,6 +3865,10 @@ ggml_backend_reg_t ggml_backend_cuda_reg CUDA_CHECK(cudaGetDeviceProperties(&prop, i)); dev_ctx->description = prop.name; + char pci_bus_id[16] = {}; + snprintf(pci_bus_id, sizeof(pci_bus_id), "%04x:%02x:%02x.0", prop.pciDomainID, prop.pciBusID, prop.pciDeviceID); + dev_ctx->pci_bus_id = pci_bus_id; + ggml_backend_dev_t dev = new ggml_backend_device { /* .iface = */ ggml_backend_cuda_device_interface, /* .reg = */ ®, @@ -3671,10 +3903,10 @@ ggml_backend_t ggml_backend_cuda_init(in } ggml_backend_t cuda_backend = new ggml_backend { - /* .guid = */ ggml_backend_cuda_guid(), - /* .interface = */ ggml_backend_cuda_interface, - /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cuda_reg(), device), - /* .context = */ ctx, + /* .guid = */ ggml_backend_cuda_guid(), + /* .iface = */ ggml_backend_cuda_interface, + /* .device = */ ggml_backend_reg_dev_get(ggml_backend_cuda_reg(), device), + /* .context = */ ctx, }; return cuda_backend; diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/im2col.cu 6641+dfsg-2/ggml/src/ggml-cuda/im2col.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/im2col.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/im2col.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,65 +1,76 @@ #include "im2col.cuh" +#define MAX_GRIDDIM_Z 65535 + template static __global__ void im2col_kernel( - const float * x, T * dst, int64_t batch_offset, - int64_t offset_delta, int64_t IC, int64_t IW, int64_t IH, int64_t OH, int64_t OW, int64_t KW, int64_t KH, int64_t pelements, int64_t CHW, + const float * x, T * dst, + int64_t IC, int64_t IW, int64_t IH, int64_t OH, int64_t OW, int64_t KW, int64_t KH, + int64_t IC_IH_IW, int64_t IH_IW, int64_t N_OH, int64_t KH_KW, int64_t IC_KH_KW, int s0, int s1, int p0, int p1, int d0, int d1) { const int64_t i = threadIdx.x + blockIdx.x * blockDim.x; - if (i >= pelements) { + if (i >= IC_KH_KW) { return; } - const int64_t ksize = OW * (KH > 1 ? KW : 1); - const int64_t kx = i / ksize; - const int64_t kd = kx * ksize; - const int64_t ky = (i - kd) / OW; - const int64_t ix = i % OW; - - const int64_t oh = blockIdx.y; - const int64_t batch = blockIdx.z / IC; - const int64_t ic = blockIdx.z % IC; - - const int64_t iiw = ix * s0 + kx * d0 - p0; - const int64_t iih = oh * s1 + ky * d1 - p1; - - const int64_t offset_dst = - ((batch * OH + oh) * OW + ix) * CHW + - (ic * (KW * KH) + ky * KW + kx); - - if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW) { - dst[offset_dst] = 0.0f; - } else { - const int64_t offset_src = ic * offset_delta + batch * batch_offset; - dst[offset_dst] = x[offset_src + iih * IW + iiw]; + const int64_t iic = i / (KH_KW); + const int64_t rem = i - iic * KH_KW; + const int64_t ikh = rem / KW; + const int64_t ikw = rem - ikh * KW; + + const int64_t iow = blockIdx.y; + for (int64_t iz = blockIdx.z; iz < N_OH; iz+=MAX_GRIDDIM_Z) { + const int64_t in = iz / OH; + const int64_t ioh = iz - in * OH; + + const int64_t iiw = iow * s0 + ikw * d0 - p0; + const int64_t iih = ioh * s1 + ikh * d1 - p1; + + const int64_t offset_dst = + ((in * OH + ioh) * OW + iow) * IC_KH_KW + iic * KH_KW + ikh * KW + ikw; + + if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW) { + dst[offset_dst] = 0.0f; + } else { + const int64_t offset_src = iic * IC_IH_IW + in * IH_IW; + dst[offset_dst] = x[offset_src + iih * IW + iiw]; + } } + + GGML_UNUSED(IC); + GGML_UNUSED(KH); } +// im2col: [N, IC, IH, IW] => [N, OH, OW, IC*KH*KW] template static void im2col_cuda(const float * x, T* dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - const int parallel_elements = OW * KW * KH; - const int num_blocks = (parallel_elements + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE; - dim3 block_nums(num_blocks, OH, batch * IC); - im2col_kernel<<>>(x, dst, batch_offset, offset_delta, IC, IW, IH, OH, OW, KW, KH, parallel_elements, (IC * KH * KW), s0, s1, p0, p1, d0, d1); + const int64_t IC_KH_KW = IC * KH * KW; + const int64_t num_blocks = (IC_KH_KW + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE; + const int64_t N_OH = N * OH; + const int64_t KH_KW = KW*KH; + dim3 block_nums(num_blocks, OW, MIN(N_OH, MAX_GRIDDIM_Z)); + im2col_kernel<<>>(x, dst, IC, IW, IH, OH, OW, KW, KH, + IC_IH_IW, IH_IW, N_OH, KH_KW, IC_KH_KW, + s0, s1, p0, p1, d0, d1); } static void im2col_cuda_f16(const float * x, half * dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, offset_delta, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } static void im2col_cuda_f32(const float * x, float * dst, int64_t IW, int64_t IH, int64_t OW, int64_t OH, int64_t KW, int64_t KH, int64_t IC, - int64_t batch, int64_t batch_offset, int64_t offset_delta, + int64_t N, int64_t IC_IH_IW, int64_t IH_IW, int s0,int s1,int p0,int p1,int d0,int d1, cudaStream_t stream) { - im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, offset_delta, s0, s1, p0, p1, d0, d1, stream); + im2col_cuda(x, dst, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); } void ggml_cuda_op_im2col(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -91,13 +102,163 @@ void ggml_cuda_op_im2col(ggml_backend_cu const int64_t OH = is_2D ? dst->ne[2] : 1; const int64_t OW = dst->ne[1]; - const size_t delta_offset = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32 - const int64_t batch = src1->ne[is_2D ? 3 : 2]; - const size_t batch_offset = src1->nb[is_2D ? 3 : 2] / 4; // nb is byte offset, src is type float32 + const int64_t IC_IH_IW = src1->nb[is_2D ? 2 : 1] / 4; // nb is byte offset, src is type float32 + const int64_t N = src1->ne[is_2D ? 3 : 2]; + const int64_t IH_IW = src1->nb[is_2D ? 3 : 2] / 4; // nb is byte offset, src is type float32 + + if(dst->type == GGML_TYPE_F16) { + im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); + } else { + im2col_cuda_f32(src1_d, (float *) dst_d, IW, IH, OW, OH, KW, KH, IC, N, IC_IH_IW, IH_IW, s0, s1, p0, p1, d0, d1, stream); + } +} + +// [N*IC, ID, IH, IW] => [N*OD, OH, OW, IC * KD * KH * KW] +template +static __global__ void im2col_3d_kernel( + const float * src, T * dst, + int64_t N, int64_t IC, int64_t ID, int64_t IH, int64_t IW, int64_t OC, + int64_t KD, int64_t KH, int64_t KW, int64_t OD, int64_t OH, int64_t OW, + int64_t OH_OW, int64_t KD_KH_KW, int64_t ID_IH_IW, int64_t KH_KW, int64_t IH_IW, int64_t IC_ID_IH_IW, + int64_t IC_KD_KH_KW, int64_t OW_KD_KH_KW, int64_t OD_OH_OW_IC_KD_KH_KW, int64_t OH_OW_IC_KD_KH_KW, + int64_t OW_IC_KD_KH_KW, int64_t N_OD_OH, int64_t OD_OH, + int64_t stride_q, int64_t stride_z, int64_t stride_y, int64_t stride_x, + int s0, int s1, int s2, int p0, int p1, int p2, int d0, int d1, int d2) { + const int64_t i = threadIdx.x + blockIdx.x * blockDim.x; + if (i >= IC_KD_KH_KW) { + return; + } + GGML_UNUSED(N); GGML_UNUSED(OC); GGML_UNUSED(OH_OW); GGML_UNUSED(OD); GGML_UNUSED(OW); GGML_UNUSED(KD); GGML_UNUSED(KH); + GGML_UNUSED(ID_IH_IW); GGML_UNUSED(IH_IW); GGML_UNUSED(IC_ID_IH_IW); GGML_UNUSED(OW_KD_KH_KW); + + const int64_t iic = i / KD_KH_KW; + const int64_t ikd = (i - iic * KD_KH_KW) / KH_KW; + const int64_t ikh = (i - iic * KD_KH_KW - ikd * KH_KW) / KW; + const int64_t ikw = i % KW; + + const int64_t iow = blockIdx.y; + for (int64_t iz = blockIdx.z; iz < N_OD_OH; iz+=MAX_GRIDDIM_Z) { + const int64_t in = iz / OD_OH; + const int64_t iod = (iz - in*OD_OH) / OH; + const int64_t ioh = iz % OH; + + const int64_t iiw = iow * s0 + ikw * d0 - p0; + const int64_t iih = ioh * s1 + ikh * d1 - p1; + const int64_t iid = iod * s2 + ikd * d2 - p2; + + const int64_t offset_dst = in*OD_OH_OW_IC_KD_KH_KW + iod*OH_OW_IC_KD_KH_KW + ioh*OW_IC_KD_KH_KW + iow*IC_KD_KH_KW + iic*KD_KH_KW + ikd * KH_KW + ikh*KW + ikw; + + if (iih < 0 || iih >= IH || iiw < 0 || iiw >= IW || iid < 0 || iid >= ID) { + dst[offset_dst] = 0.0f; + } else { + const int64_t offset_src = ((in * IC + iic) * stride_q) + (iid * stride_z) + (iih * stride_y) + (iiw * stride_x); + dst[offset_dst] = src[offset_src]; + } + } +} + +// [N*IC, ID, IH, IW] => [N*OD, OH, OW, IC * KD * KH * KW] +template +static void im2col_3d_cuda(const float * src, T* dst, + int64_t N, int64_t IC, int64_t ID, int64_t IH, int64_t IW, int64_t OC, + int64_t KD, int64_t KH, int64_t KW, int64_t OD, int64_t OH, int64_t OW, + int64_t stride_q, int64_t stride_z, int64_t stride_y, int64_t stride_x, + int s0, int s1, int s2, int p0, int p1, int p2, int d0, int d1, int d2, cudaStream_t stream) { + const int64_t OH_OW = OH*OW; + const int64_t KD_KH_KW = KD*KH*KW; + const int64_t ID_IH_IW = ID*IH*IW; + const int64_t KH_KW = KH*KW; + const int64_t IH_IW = IH*IW; + const int64_t IC_KD_KH_KW = IC*KD*KH*KW; + const int64_t OW_KD_KH_KW = OW*KD*KH*KW; + const int64_t N_OD_OH = N*OD*OH; + const int64_t OD_OH = OD*OH; + const int64_t IC_ID_IH_IW = IC*ID*IH*IW; + const int64_t OD_OH_OW_IC_KD_KH_KW = OD*OH*OW*IC*KD*KH*KW; + const int64_t OH_OW_IC_KD_KH_KW = OH*OW*IC*KD*KH*KW; + const int64_t OW_IC_KD_KH_KW = OW*IC*KD*KH*KW; + const int64_t num_blocks = (IC_KD_KH_KW + CUDA_IM2COL_BLOCK_SIZE - 1) / CUDA_IM2COL_BLOCK_SIZE; + dim3 block_nums(num_blocks, OW, MIN(N_OD_OH, MAX_GRIDDIM_Z)); + im2col_3d_kernel<<>>(src, dst, N, IC, ID, IH, IW, OC, KD, KH, KW, OD, OH, OW, + OH_OW, KD_KH_KW, ID_IH_IW, KH_KW, IH_IW, IC_ID_IH_IW, + IC_KD_KH_KW, OW_KD_KH_KW, OD_OH_OW_IC_KD_KH_KW, + OH_OW_IC_KD_KH_KW, OW_IC_KD_KH_KW, N_OD_OH, OD_OH, + stride_q, stride_z, stride_y, stride_x, + s0, s1, s2, p0, p1, p2, d0, d1, d2); +} + +static void im2col_3d_cuda_f16(const float * src, half * dst, + int64_t N, int64_t IC, int64_t ID, int64_t IH, int64_t IW, int64_t OC, + int64_t KD, int64_t KH, int64_t KW, int64_t OD, int64_t OH, int64_t OW, + int64_t stride_q, int64_t stride_z, int64_t stride_y, int64_t stride_x, + int s0, int s1, int s2, int p0, int p1, int p2, int d0, int d1, int d2, cudaStream_t stream) { + + im2col_3d_cuda(src, dst, N, IC, ID, IH, IW, OC, KD, KH, KW, OD, OH, OW, + stride_q, stride_z, stride_y, stride_x, + s0, s1, s2, p0, p1, p2, d0, d1, d2, stream); +} + +static void im2col_3d_cuda_f32(const float * src, float * dst, + int64_t N, int64_t IC, int64_t ID, int64_t IH, int64_t IW, int64_t OC, + int64_t KD, int64_t KH, int64_t KW, int64_t OD, int64_t OH, int64_t OW, + int64_t stride_q, int64_t stride_z, int64_t stride_y, int64_t stride_x, + int s0, int s1, int s2, int p0, int p1, int p2, int d0, int d1, int d2, cudaStream_t stream) { + + im2col_3d_cuda(src, dst, N, IC, ID, IH, IW, OC, KD, KH, KW, OD, OH, OW, + stride_q, stride_z, stride_y, stride_x, + s0, s1, s2, p0, p1, p2, d0, d1, d2, stream); +} + +void ggml_cuda_op_im2col_3d(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + const float * src1_d = (const float *)src1->data; + float * dst_d = (float *)dst->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F16 || dst->type == GGML_TYPE_F32); + + GGML_TENSOR_BINARY_OP_LOCALS + + const int32_t s0 = ((const int32_t *)(dst->op_params))[0]; + const int32_t s1 = ((const int32_t *)(dst->op_params))[1]; + const int32_t s2 = ((const int32_t *)(dst->op_params))[2]; + const int32_t p0 = ((const int32_t *)(dst->op_params))[3]; + const int32_t p1 = ((const int32_t *)(dst->op_params))[4]; + const int32_t p2 = ((const int32_t *)(dst->op_params))[5]; + const int32_t d0 = ((const int32_t *)(dst->op_params))[6]; + const int32_t d1 = ((const int32_t *)(dst->op_params))[7]; + const int32_t d2 = ((const int32_t *)(dst->op_params))[8]; + const int32_t IC = ((const int32_t *)(dst->op_params))[9]; + + const int64_t N = ne13 / IC; + const int64_t ID = ne12; + const int64_t IH = ne11; + const int64_t IW = ne10; + + const int64_t OC = ne03 / IC; + const int64_t KD = ne02; + const int64_t KH = ne01; + const int64_t KW = ne00; + + const int64_t OD = ne3 / N; + const int64_t OH = ne2; + const int64_t OW = ne1; + + const size_t es = ggml_element_size(src1); + const int64_t stride_x = src1->nb[0] / es; + const int64_t stride_y = src1->nb[1] / es; + const int64_t stride_z = src1->nb[2] / es; + const int64_t stride_q = src1->nb[3] / es; if(dst->type == GGML_TYPE_F16) { - im2col_cuda_f16(src1_d, (half *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream); + im2col_3d_cuda_f16(src1_d, (half *) dst_d, N, IC, ID, IH, IW, OC, KD, KH, KW, OD, OH, OW, + stride_q, stride_z, stride_y, stride_x, + s0, s1, s2, p0, p1, p2, d0, d1, d2, stream); } else { - im2col_cuda_f32(src1_d, (float *) dst_d, IW, IH, OW, OH, KW, KH, IC, batch, batch_offset, delta_offset, s0, s1, p0, p1, d0, d1, stream); + im2col_3d_cuda_f32(src1_d, (float *) dst_d, N, IC, ID, IH, IW, OC, KD, KH, KW, OD, OH, OW, + stride_q, stride_z, stride_y, stride_x, + s0, s1, s2, p0, p1, p2, d0, d1, d2, stream); } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/im2col.cuh 6641+dfsg-2/ggml/src/ggml-cuda/im2col.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/im2col.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/im2col.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -3,3 +3,4 @@ #define CUDA_IM2COL_BLOCK_SIZE 256 void ggml_cuda_op_im2col(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_im2col_3d(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mean.cu 6641+dfsg-2/ggml/src/ggml-cuda/mean.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mean.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mean.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,4 +1,14 @@ #include "mean.cuh" +#include "reduce_rows.cuh" + +#ifdef GGML_CUDA_USE_CUB +#include +using namespace cub; +#endif // GGML_CUDA_USE_CUB + +template __global__ void divide_by_count(T * result, size_t count) { + *result /= static_cast(count); +} void ggml_cuda_op_mean(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; @@ -13,7 +23,51 @@ void ggml_cuda_op_mean(ggml_backend_cuda const int64_t ncols = src0->ne[0]; const int64_t nrows = ggml_nrows(src0); - const dim3 block_dims(WARP_SIZE, 1, 1); +// Special case for reducing vectors +#ifdef GGML_CUDA_USE_CUB +#ifdef USE_CUDA_GRAPH + cudaStreamCaptureStatus iscapturing; + CUDA_CHECK(cudaStreamIsCapturing(stream, &iscapturing)); +#endif // USE_CUDA_GRAPH + if ((nrows == 1) && +#ifdef USE_CUDA_GRAPH + // CUDA_GRAPHS_DISABLED + ((ncols > 65536) && + ((ctx.cuda_graph->instance == nullptr) && (iscapturing == cudaStreamCaptureStatusNone) || + ctx.cuda_graph->disable_due_to_gpu_arch || ctx.cuda_graph->disable_due_to_too_many_updates || + ctx.cuda_graph->disable_due_to_failed_graph_capture)) || + // CUDA_GRAPHS ENABLED + ((ncols > 32768) && + !((ctx.cuda_graph->instance == nullptr) && (iscapturing == cudaStreamCaptureStatusNone) || + ctx.cuda_graph->disable_due_to_gpu_arch || ctx.cuda_graph->disable_due_to_too_many_updates || + ctx.cuda_graph->disable_due_to_failed_graph_capture))) { +#else + (ncols > 65536)) { +#endif // USE_CUDA_GRAPH + // Single row - use device-wide reduction + size_t tmp_size = 0; + ggml_cuda_pool & pool = ctx.pool(); + + DeviceReduce::Sum(nullptr, tmp_size, src0_d, dst_d, ncols, stream); + + ggml_cuda_pool_alloc tmp_alloc(pool, tmp_size); + DeviceReduce::Sum(tmp_alloc.ptr, tmp_size, src0_d, dst_d, ncols, stream); + + // Divide by ncols + divide_by_count<<<1, 1, 0, stream>>>(dst_d, ncols); + return; + } +#endif // GGML_CUDA_USE_CUB + const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(src0_d, dst_d, ncols); + + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; + if ((nrows / nsm) < 2) { + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } else { + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mma.cuh 6641+dfsg-2/ggml/src/ggml-cuda/mma.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/mma.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mma.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -1,3 +1,4 @@ +#pragma once // This file contains primitives that expose the tensor core PTX instructions for CUDA code. // The primitives can be used in a similar way as the nvcuda::wmma interface but with a well-defined memory layout. // The documentation for the PTX instructions can be found under: @@ -12,7 +13,8 @@ // The methods get_i and get_j can be used to get the physical 32 bit index of the lth element of a thread within a tile. // All matrix tiles have ne physical 32 bit elements per warp. // -// As described in the documentation, all pointers for load_ldmatrix must be to shared memory and aligned to 16 bytes. +// As described in the PTX documentation, all pointers for load_ldmatrix must be to shared memory and aligned to 16 bytes. +// The API in this file also assumes that the pointers for load_generic are aligned to 16 bytes, unaligned pointers are considered undefined behavior. #include "common.cuh" @@ -22,13 +24,13 @@ static __device__ __forceinline__ int ggml_cuda_movmatrix(const int x) { int ret = 0; -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE asm("movmatrix.sync.aligned.m8n8.trans.b16 %0, %1;" : "=r"(ret) : "r"(x)); #else GGML_UNUSED(x); NO_DEVICE_CODE; -#endif // defined(NEW_MMA_AVAILABLE) +#endif // defined(TURING_MMA_AVAILABLE) return ret; } @@ -66,7 +68,44 @@ namespace ggml_cuda_mma { struct tile { static constexpr int I = I_; static constexpr int J = J_; - static constexpr int ne = I * J / WARP_SIZE; + +#if defined(GGML_USE_HIP) + static constexpr int ne = I * J / 64; + T x[ne] = {0}; + + static __device__ __forceinline__ int get_i(const int l) { + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> + return threadIdx.x % 16; + } else if constexpr (I == 16 && J == 8) { + return threadIdx.x % 16; + } else if constexpr (I == 32 && J == 4) { + return threadIdx.x % 32; + } else if constexpr (I == 16 && J == 16) { + return 4 * (threadIdx.x / 16) + l; + } else if constexpr (I == 32 && J == 32) { + return 4 * (threadIdx.x / 32) + 8 * (l / 4) + (l % 4); + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + + static __device__ __forceinline__ int get_j(const int l) { + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> + return (2 * ((threadIdx.x / 16) % 2) + l); + } else if constexpr (I == 16 && J == 8) { + return 2 * (threadIdx.x / 16) + l; + } else if constexpr (I == 32 && J == 4) { + return 2 * (threadIdx.x / 32) + l; + } else if constexpr (I == 16 && J == 16) { + return threadIdx.x % 16; + } else if constexpr (I == 32 && J == 32) { + return threadIdx.x % 32; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } +#else + static constexpr int ne = I * J / 32; T x[ne] = {0}; static __device__ __forceinline__ int get_i(const int l) { @@ -94,6 +133,7 @@ namespace ggml_cuda_mma { static_assert(I == -1 && J == -1, "template specialization not implemented"); } } +#endif // defined(GGML_USE_HIP) }; template @@ -128,6 +168,38 @@ namespace ggml_cuda_mma { } }; + template + struct tile { + static constexpr int I = I_; + static constexpr int J = J_; + static constexpr int ne = I * J / WARP_SIZE; + nv_bfloat162 x[ne] = {{0.0f, 0.0f}}; + + static __device__ __forceinline__ int get_i(const int l) { + if constexpr (I == 8 && J == 8) { + return threadIdx.x / 4; + } else if constexpr (I == 16 && J == 4) { + return l * 8 + threadIdx.x / 4; + } else if constexpr (I == 16 && J == 8) { + return (l % 2) * 8 + threadIdx.x / 4; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + + static __device__ __forceinline__ int get_j(const int l) { + if constexpr (I == 8 && J == 8) { + return l * 4 + threadIdx.x % 4; + } else if constexpr (I == 16 && J == 4) { + return threadIdx.x % 4; + } else if constexpr (I == 16 && J == 8) { + return (l / 2) * 4 + threadIdx.x % 4; + } else { + static_assert(I == -1 && J == -1, "template specialization not implemented"); + } + } + }; + template static __device__ __forceinline__ tile get_half2(const tile & tile_float) { tile ret; @@ -148,16 +220,29 @@ namespace ggml_cuda_mma { template static __device__ __forceinline__ void load_generic(tile & t, const T * __restrict__ xs0, const int stride) { +#if defined(AMD_MFMA_AVAILABLE) + if constexpr (I == 64 && J == 2) { // Special tile size to load <16, 4> as <16, 8> +#pragma unroll + for (int l = 0; l < t.ne; ++l) { + t.x[l] = xs0[t.get_i(l)*stride + t.get_j(l)]; + } + } else { + int64_t * xi = (int64_t *) t.x; + const int64_t * xs = (int64_t *) ((const int *) xs0 + (threadIdx.x % t.I) * stride + 2 * (threadIdx.x / t.I)); + xi[0] = xs[0]; + } +#else #pragma unroll for (int l = 0; l < t.ne; ++l) { t.x[l] = xs0[t.get_i(l)*stride + t.get_j(l)]; } +#endif // defined(AMD_MFMA_AVAILABLE) } template static __device__ __forceinline__ void load_ldmatrix( tile<8, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int *) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + ((threadIdx.x / t.I) * (t.J / 2)) % t.J; asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];" @@ -165,13 +250,13 @@ namespace ggml_cuda_mma { : "l"(xs)); #else load_generic(t, xs0, stride); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix( tile<16, 4, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int *) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride; asm volatile("ldmatrix.sync.aligned.m8n8.x2.b16 {%0, %1}, [%2];" @@ -180,13 +265,13 @@ namespace ggml_cuda_mma { #else load_generic(xs0, stride); GGML_UNUSED(t); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix( tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#if defined(TURING_MMA_AVAILABLE) int * xi = (int * ) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2); asm volatile("ldmatrix.sync.aligned.m8n8.x4.b16 {%0, %1, %2, %3}, [%4];" @@ -194,29 +279,27 @@ namespace ggml_cuda_mma { : "l"(xs)); #else load_generic(t, xs0, stride); -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } template static __device__ __forceinline__ void load_ldmatrix_trans( tile<16, 8, T> & t, const T * __restrict__ xs0, const int stride) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE int * xi = (int * ) t.x; const int * xs = (const int *) xs0 + (threadIdx.x % t.I) * stride + (threadIdx.x / t.I) * (t.J / 2); asm volatile("ldmatrix.sync.aligned.m8n8.x4.trans.b16 {%0, %1, %2, %3}, [%4];" : "=r"(xi[0]), "=r"(xi[2]), "=r"(xi[1]), "=r"(xi[3]) : "l"(xs)); #else - GGML_UNUSED(t); - GGML_UNUSED(xs0); - GGML_UNUSED(stride); + GGML_UNUSED_VARS(t, xs0, stride); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, int> & D, const tile<16, 4, int> & A, const tile<8, 4, int> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE #if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE asm("mma.sync.aligned.m16n8k16.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5}, {%6}, {%0, %1, %2, %3};" : "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3]) @@ -231,16 +314,14 @@ namespace ggml_cuda_mma { : "r"(A.x[1]), "r"(B.x[0])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, int> & D, const tile<16, 8, int> & A, const tile<8, 8, int> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE #if __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE asm("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" : "+r"(D.x[0]), "+r"(D.x[1]), "+r"(D.x[2]), "+r"(D.x[3]) @@ -261,16 +342,14 @@ namespace ggml_cuda_mma { : "r"(A.x[3]), "r"(B.x[1])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 4, half2> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -288,16 +367,14 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[1])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // TURING_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, half2> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -324,16 +401,29 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[3])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); + NO_DEVICE_CODE; +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 8, float> & D, const tile<16, 8, float> & A, const tile<8, 8, float> & B) { +#ifdef AMPERE_MMA_AVAILABLE + const int * Axi = (const int *) A.x; + const int * Bxi = (const int *) B.x; + int * Dxi = (int *) D.x; + asm("mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" + : "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3]) + : "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1])); +#else + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMPERE_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 8, float> & D, const tile<16, 8, half2> & A, const tile<8, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -351,16 +441,29 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[1])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); + NO_DEVICE_CODE; +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 8, float> & D, const tile<16, 8, nv_bfloat162> & A, const tile<8, 8, nv_bfloat162> & B) { +#ifdef AMPERE_MMA_AVAILABLE + const int * Axi = (const int *) A.x; + const int * Bxi = (const int *) B.x; + int * Dxi = (int *) D.x; + asm("mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};" + : "+r"(Dxi[0]), "+r"(Dxi[1]), "+r"(Dxi[2]), "+r"(Dxi[3]) + : "r"(Axi[0]), "r"(Axi[1]), "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[0]), "r"(Bxi[1])); +#else + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMPERE_MMA_AVAILABLE } static __device__ __forceinline__ void mma( tile<16, 16, float> & D, const tile<16, 8, half2> & A, const tile<16, 8, half2> & B) { -#ifdef NEW_MMA_AVAILABLE +#ifdef TURING_MMA_AVAILABLE const int * Axi = (const int *) A.x; const int * Bxi = (const int *) B.x; int * Dxi = (int *) D.x; @@ -387,10 +490,60 @@ namespace ggml_cuda_mma { : "r"(Axi[2]), "r"(Axi[3]), "r"(Bxi[3])); #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_AMPERE #else - GGML_UNUSED(D); - GGML_UNUSED(A); - GGML_UNUSED(B); + GGML_UNUSED_VARS(D, A, B); + NO_DEVICE_CODE; +#endif // TURING_MMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<16, 16, int> & D, const tile<16, 8, int> & A, const tile<16, 8, int> & B) { +#if defined(AMD_MFMA_AVAILABLE) + using int32x4_t = __attribute__((__vector_size__(4 * sizeof(int)))) int; + int32x4_t * acc = (int32x4_t *) D.x; +#if defined(CDNA3) + acc[0] = __builtin_amdgcn_mfma_i32_16x16x32_i8(((int64_t *) A.x)[0], + ((int64_t *) B.x)[0], + acc[0], + 0, 0, 0); +#elif defined(CDNA2) || defined(CDNA) + acc[0] = __builtin_amdgcn_mfma_i32_16x16x16i8(A.x[0], + B.x[0], + acc[0], + 0, 0, 0); + acc[0] = __builtin_amdgcn_mfma_i32_16x16x16i8(A.x[1], + B.x[1], + acc[0], + 0, 0, 0); +#endif // defined(CDNA3) +#else + GGML_UNUSED_VARS(D, A, B); + NO_DEVICE_CODE; +#endif // AMD_MFMA_AVAILABLE + } + + static __device__ __forceinline__ void mma( + tile<32, 32, int> & D, const tile<32, 4, int> & A, const tile<32, 4, int> & B) { +#if defined(AMD_MFMA_AVAILABLE) + using int32x16_t = __attribute__((__vector_size__(16 * sizeof(int)))) int; + int32x16_t * acc = (int32x16_t *) D.x; +#if defined(CDNA3) + acc[0] = __builtin_amdgcn_mfma_i32_32x32x16_i8(((int64_t *) A.x)[0], + ((int64_t *) B.x)[0], + acc[0], + 0, 0, 0); +#elif defined(CDNA2) || defined(CDNA) + acc[0] = __builtin_amdgcn_mfma_i32_32x32x8i8(A.x[0], + B.x[0], + acc[0], + 0, 0, 0); + acc[0] = __builtin_amdgcn_mfma_i32_32x32x8i8(A.x[1], + B.x[1], + acc[0], + 0, 0, 0); +#endif // defined(CDNA3) +#else + GGML_UNUSED_VARS(D, A, B); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmf.cu 6641+dfsg-2/ggml/src/ggml-cuda/mmf.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mmf.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmf.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,123 @@ +#include "ggml.h" +#include "mmf.cuh" + +void ggml_cuda_mul_mat_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { + GGML_ASSERT( src1->type == GGML_TYPE_F32); + GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + + GGML_TENSOR_BINARY_OP_LOCALS; + + const size_t ts_src0 = ggml_type_size(src0->type); + const size_t ts_src1 = ggml_type_size(src1->type); + const size_t ts_dst = ggml_type_size(dst->type); + + GGML_ASSERT(ne13 == ne3); + + GGML_ASSERT( nb00 == ts_src0); + GGML_ASSERT( nb10 == ts_src1); + GGML_ASSERT(!ids || ids->nb[0] == ggml_type_size(ids->type)); + GGML_ASSERT( nb0 == ts_dst); + + const float * src1_d = (const float *) src1->data; + const int32_t * ids_d = ids ? (const int32_t *) ids->data : nullptr; + float * dst_d = (float *) dst->data; + + const int64_t s01 = src0->nb[1] / ts_src0; + const int64_t s11 = src1->nb[1] / ts_src1; + const int64_t s1 = dst->nb[1] / ts_dst; + const int64_t s02 = src0->nb[2] / ts_src0; + const int64_t s12 = src1->nb[2] / ts_src1; + const int64_t s2 = dst->nb[2] / ts_dst; + const int64_t s03 = src0->nb[3] / ts_src0; + const int64_t s13 = src1->nb[3] / ts_src1; + const int64_t s3 = dst->nb[3] / ts_dst; + + const int64_t ids_s0 = ids ? ids->nb[0] / ggml_type_size(ids->type) : 0; + const int64_t ids_s1 = ids ? ids->nb[1] / ggml_type_size(ids->type) : 0; + + // For MUL_MAT_ID the memory layout is different than for MUL_MAT: + const int64_t ncols_dst = ids ? ne2 : ne1; + const int64_t nchannels_dst = ids ? ne1 : ne2; + + const int64_t stride_col_dst = ids ? s2 : s1; + const int64_t stride_col_y = ids ? s12 : s11; + const int64_t stride_channel_dst = ids ? s1 : s2; + + int64_t stride_channel_y = ids ? s11 : s12; + int64_t nchannels_y = ids ? ne11 : ne12; + + //mul_mat_id: handle broadcast + if (ids && nchannels_y == 1) { + stride_channel_y = 0; + nchannels_y = ids->ne[0]; + } + + switch (src0->type) { + case GGML_TYPE_F32: { + const float * src0_d = (const float *) src0->data; + constexpr int vals_per_T = 1; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, stride_col_y/vals_per_T, stride_col_dst, + ids_s0, ids_s1, ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + case GGML_TYPE_F16: { + const half2 * src0_d = (const half2 *) src0->data; + constexpr int vals_per_T = 2; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, stride_col_y/vals_per_T, stride_col_dst, + ids_s0, ids_s1, ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + case GGML_TYPE_BF16: { + const nv_bfloat162 * src0_d = (const nv_bfloat162 *) src0->data; + constexpr int vals_per_T = 2; + mul_mat_f_switch_cols_per_block( + src0_d, src1_d, ids_d, dst_d, ne00/vals_per_T, ne01, ncols_dst, s01/vals_per_T, stride_col_y/vals_per_T, stride_col_dst, + ids_s0, ids_s1, ne02, nchannels_y, nchannels_dst, s02/vals_per_T, stride_channel_y, stride_channel_dst, + ne03, ne3, s03/vals_per_T, s13, s3, ctx.stream()); + } break; + default: + GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); + } +} + +bool ggml_cuda_should_use_mmf(enum ggml_type type, int cc, int warp_size, const int64_t * src0_ne, const int src1_ncols, bool mul_mat_id) { + + if (ggml_is_quantized(type)) { + return false; + } + + if (src0_ne[0] % (warp_size * (4/ggml_type_size(type))) != 0) { + return false; + } + if (src0_ne[1] % MMF_ROWS_PER_BLOCK != 0) { + return false; + } + + if (mul_mat_id) { + if (type == GGML_TYPE_F32 && src1_ncols > 32) { + return false; + } + if ((type == GGML_TYPE_F16 || type == GGML_TYPE_BF16) && src1_ncols > 64) { + return false; + } + } else { + if (src1_ncols > 16) { + return false; + } + } + + switch (type) { + case GGML_TYPE_F32: + return ampere_mma_available(cc); + case GGML_TYPE_F16: + return turing_mma_available(cc); + case GGML_TYPE_BF16: + return ampere_mma_available(cc); + default: + return false; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmf.cuh 6641+dfsg-2/ggml/src/ggml-cuda/mmf.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/mmf.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmf.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,496 @@ +#pragma once + +#include "mma.cuh" +#include "common.cuh" + +using namespace ggml_cuda_mma; + +#define MMF_ROWS_PER_BLOCK 32 + +void ggml_cuda_mul_mat_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); + +bool ggml_cuda_should_use_mmf(enum ggml_type type, int cc, int warp_size, const int64_t * scr0_ne, const int src1_ncols, bool mul_mat_id); + +template +__launch_bounds__(ggml_cuda_get_physical_warp_size()*nwarps, 1) +static __global__ void mul_mat_f( + const T * __restrict__ x, const float * __restrict__ y, const int32_t * __restrict__ ids, float * __restrict__ dst, + const int ncols, const int ncols_dst_total, const int nchannels_dst, const int stride_row, const int stride_col_y, const int stride_col_dst, + const int stride_col_id, const int stride_row_id, + const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, + const int sample_ratio, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) + typedef tile<16, 8, T> tile_A; + typedef tile< 8, 8, T> tile_B; + typedef tile<16, 8, float> tile_C; + + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int tile_k_padded = warp_size + 4; + constexpr int ntA = rows_per_block / tile_A::I; + constexpr int ntB = (cols_per_block + tile_B::I - 1) / tile_B::I; + + const int row0 = blockIdx.x * rows_per_block; + + int expert_idx = 0; + int col_base = 0; + + const int channel_dst = has_ids ? 0 : blockIdx.y; + + if constexpr (has_ids) { + // experts + tiles of ncols_dst are packed in the y dimension + int col_tiles = (ncols_dst_total + cols_per_block - 1) / cols_per_block; + const int nchannels_x = gridDim.y / col_tiles; + const int tile_idx = blockIdx.y / nchannels_x; + expert_idx = blockIdx.y - tile_idx * nchannels_x; + col_base = tile_idx * cols_per_block; + } + + const int channel_x = has_ids ? expert_idx : (channel_dst / channel_ratio); + const int channel_y = channel_dst; + const int sample_dst = blockIdx.z; + const int sample_x = sample_dst / sample_ratio; + const int sample_y = sample_dst; + + x += int64_t(sample_x) *stride_sample_x + channel_x *stride_channel_x + row0*stride_row ; + y += int64_t(sample_y) *stride_sample_y + (has_ids ? 0 : channel_y *stride_channel_y); + dst += int64_t(sample_dst)*stride_sample_dst + (has_ids ? 0 : channel_dst*stride_channel_dst); + + if constexpr (has_ids) { + constexpr int y_stride_scale = std::is_same_v ? 1 : 2; + const int64_t col_offset = col_base; + y += col_offset * stride_col_y * y_stride_scale; + dst += col_offset * stride_col_dst; + ids += col_offset * stride_row_id; + } + + const float2 * y2 = (const float2 *) y; + + extern __shared__ char data_mmv[]; + + char * shmem_base = data_mmv; + int * slot_map = (int *) shmem_base; + char * compute_base = has_ids ? (shmem_base + GGML_PAD(cols_per_block, 16) * sizeof(int)) : shmem_base; + + tile_C C[ntA][ntB]; + + T * tile_xy = (T *) compute_base + threadIdx.y*(tile_A::I * tile_k_padded); + + if constexpr (has_ids) { + int found = 0; + + for (int j0 = 0; j0 < cols_per_block; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (threadIdx.x == 0) { + slot_map[j] = -1; + } + + if (col_base + j >= ncols_dst_total) { + continue; + } + + const int32_t * __restrict__ id_row = ids + j*stride_row_id; + + for (int k = threadIdx.x; k < nchannels_dst; k += warp_size) { + int match = id_row[k*stride_col_id] == expert_idx; + + if (match) { + slot_map[j] = k; + found = 1; + break; + } + } + } + + if (!__syncthreads_or(found)) { + return; + } + } + + + for (int col = threadIdx.y*warp_size + threadIdx.x; col < ncols; col += nwarps*warp_size) { + tile_A A[ntA][warp_size / tile_A::J]; +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { +#pragma unroll + for (int i = 0; i < tile_A::I; ++i) { + tile_xy[i*tile_k_padded + threadIdx.x] = x[(itA*tile_A::I + i)*stride_row + col]; + } +#pragma unroll + for (int k0 = 0; k0 < warp_size; k0 += tile_A::J) { + load_ldmatrix(A[itA][k0/tile_A::J], tile_xy + k0, tile_k_padded); + } + } + +#pragma unroll + for (int itB = 0; itB < ntB; ++itB) { + if constexpr (std::is_same_v) { +#pragma unroll + for (int j0 = 0; j0 < tile_B::I; ++j0) { + const int j = j0 + itB*tile_B::I; + + if constexpr (!has_ids) { + tile_xy[j0*tile_k_padded + threadIdx.x] = j < cols_per_block ? y[j*stride_col_y + col] : 0.0f; + } else { + const bool valid = j < cols_per_block && (col_base + j) < ncols_dst_total && slot_map[j] >= 0; + tile_xy[j0*tile_k_padded + threadIdx.x] = valid ? y[slot_map[j]*stride_channel_y + j*stride_col_y + col] : 0.0f; + } + } + } else if constexpr (std::is_same_v || std::is_same_v) { +#pragma unroll + for (int j0 = 0; j0 < tile_B::I; ++j0) { + const int j = j0 + itB*tile_B::I; + + if constexpr (!has_ids) { + const float2 tmp = j < cols_per_block ? y2[j*stride_col_y + col] : make_float2(0.0f, 0.0f); + tile_xy[j0*tile_k_padded + threadIdx.x] = {tmp.x, tmp.y}; + } else { + const bool valid = j < cols_per_block && (col_base + j) < ncols_dst_total && slot_map[j] >= 0; + float2 tmp = valid ? *(const float2*) &y[slot_map[j]*stride_channel_y + 2*(j*stride_col_y + col)] : make_float2(0.0f, 0.0f); + tile_xy[j0*tile_k_padded + threadIdx.x] = {tmp.x, tmp.y}; + } + } + } else { + static_assert(std::is_same_v, "unsupported type"); + } +#pragma unroll + for (int k0 = 0; k0 < warp_size; k0 += tile_B::J) { + tile_B B; + load_ldmatrix(B, tile_xy + k0, tile_k_padded); +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { + mma(C[itA][itB], A[itA][k0/tile_B::J], B); + } + } + } + } + + float * buf_iw = (float *) compute_base; + constexpr int kiw = nwarps*rows_per_block + 4; + + if (nwarps > 1) { + __syncthreads(); + } +#pragma unroll + for (int itB = 0; itB < ntB; ++itB) { +#pragma unroll + for (int itA = 0; itA < ntA; ++itA) { +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = threadIdx.y*rows_per_block + itA*tile_C::I + tile_C::get_i(l); + const int j = itB*tile_C::J + tile_C::get_j(l); + buf_iw[j*kiw + i] = C[itA][itB].x[l]; + } + } + } + + if (nwarps > 1) { + __syncthreads(); + } + +#pragma unroll + for (int j0 = 0; j0 < cols_per_block; j0 += nwarps) { + const int j = j0 + threadIdx.y; + + if (j0 + nwarps > cols_per_block && j >= cols_per_block) { + return; + } + + float sum = 0.0f; + static_assert(rows_per_block == warp_size, "need loop/check"); +#pragma unroll + for (int i0 = 0; i0 < nwarps*rows_per_block; i0 += rows_per_block) { + const int i = i0 + threadIdx.x; + + sum += buf_iw[j*kiw + i]; + } + + if constexpr (!has_ids) { + dst[j*stride_col_dst + row0 + threadIdx.x] = sum; + } else { + const int slot = (j < cols_per_block) ? slot_map[j] : -1; + if (slot >= 0 && (col_base + j) < ncols_dst_total) { + dst[slot*stride_channel_dst + j*stride_col_dst + row0 + threadIdx.x] = sum; + } + } + } +#else + GGML_UNUSED_VARS(x, y, ids, dst, + ncols, ncols_dst_total, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + NO_DEVICE_CODE; +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +} + +template +static inline void mul_mat_f_switch_ids( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols_x, const int64_t ncols_dst, const int64_t nchannels_dst, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t stride_col_id, const int64_t stride_row_id, + const int64_t channel_ratio, const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, + const int64_t sample_ratio, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + const dim3 & block_nums, const dim3 & block_dims, const int nbytes_shared_total, cudaStream_t stream) { + if (ids) { + const int64_t col_tiles = (ncols_dst + cols_per_block - 1) / cols_per_block; + dim3 block_nums_ids = block_nums; + block_nums_ids.y *= col_tiles; + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } else { + mul_mat_f<<>> + (x, y, ids, dst, ncols_x, cols_per_block, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } +} + +template +void mul_mat_f_cuda( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols_x, const int64_t nrows_x, const int64_t ncols_dst, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t stride_col_id, const int64_t stride_row_id, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + typedef tile<16, 8, T> tile_A; + typedef tile< 8, 8, T> tile_B; + + GGML_ASSERT(ncols_x % 2 == 0); + GGML_ASSERT(stride_row % 2 == 0); + GGML_ASSERT(stride_col_y % 2 == 0); + GGML_ASSERT(ids || nchannels_dst % nchannels_x == 0); + GGML_ASSERT( nsamples_dst % nsamples_x == 0); + const int64_t channel_ratio = nchannels_dst / nchannels_x; + const int64_t sample_ratio = nsamples_dst / nsamples_x; + + const int device = ggml_cuda_get_device(); + const int warp_size = ggml_cuda_info().devices[device].warp_size; + + int64_t nwarps_best = 1; + int64_t niter_best = (ncols_x + warp_size*2 - 1) / (warp_size*2); + int64_t max_block_size = 256; + for (int64_t nwarps = 2; nwarps <= max_block_size/warp_size; nwarps++) { + const int64_t niter = (ncols_x + nwarps*warp_size*2 - 1) / (nwarps*warp_size*2); + if (niter < niter_best) { + niter_best = niter; + nwarps_best = nwarps; + } + } + + constexpr int rows_per_block = MMF_ROWS_PER_BLOCK; + const int nbytes_shared_iter = nwarps_best * tile_A::I * (warp_size + 4) * 4; + const int nbytes_shared_combine = GGML_PAD(cols_per_block, tile_B::I) * (nwarps_best*rows_per_block + 4) * 4; + const int nbytes_shared = std::max(nbytes_shared_iter, nbytes_shared_combine); + const int nbytes_slotmap = ids ? GGML_PAD(cols_per_block, 16) * sizeof(int) : 0; + const int nbytes_shared_total = nbytes_shared + nbytes_slotmap; + const int64_t grid_y = ids ? nchannels_x : nchannels_dst; // per expert when ids present + + const dim3 block_nums(nrows_x/rows_per_block, grid_y, nsamples_dst); + const dim3 block_dims(warp_size, nwarps_best, 1); + + switch (nwarps_best) { + case 1: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 2: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 3: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 4: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 5: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 6: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 7: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + case 8: { + mul_mat_f_switch_ids( + x, y, ids, dst, ncols_x, ncols_dst, nchannels_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst, block_nums, block_dims, nbytes_shared_total, stream); + } break; + default: { + GGML_ABORT("fatal error"); + } break; + } + + GGML_UNUSED_VARS(nchannels_y); +} + +template +static void mul_mat_f_switch_cols_per_block( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols_x, const int64_t nrows_x, const int64_t ncols_dst, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t stride_col_id, const int stride_row_id, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + + const int ncols_case = (ids && ncols_dst > 16) ? 16 : ncols_dst; + + GGML_ASSERT(ids || ncols_dst <= 16); + + switch (ncols_case) { + case 1: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 2: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 3: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 4: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 5: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 6: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 7: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 8: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 9: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 10: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 11: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 12: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 13: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 14: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 15: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + case 16: { + mul_mat_f_cuda(x, y, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row, stride_col_y, stride_col_dst, + stride_col_id, stride_row_id, nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + } break; + default: { + GGML_ABORT("fatal error"); + } break; + } +} + +#define DECL_MMF_CASE_HELPER(T, ncols_dst) \ + template void mul_mat_f_cuda( \ + const T * x, const float * y, const int32_t * ids, float * dst, \ + const int64_t ncols_x, const int64_t nrows_x, int64_t ncols_dst_total, const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, \ + const int64_t stride_col_id, const int64_t stride_row_id, \ + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, \ + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x,\ + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, \ + cudaStream_t stream); + +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) +#define DECL_MMF_CASE_EXTERN(ncols_dst) \ + extern DECL_MMF_CASE_HELPER(float, ncols_dst) \ + extern DECL_MMF_CASE_HELPER(half2, ncols_dst) \ + extern DECL_MMF_CASE_HELPER(nv_bfloat162, ncols_dst) + +#define DECL_MMF_CASE(ncols_dst) \ + DECL_MMF_CASE_HELPER(float, ncols_dst) \ + DECL_MMF_CASE_HELPER(half2, ncols_dst) \ + DECL_MMF_CASE_HELPER(nv_bfloat162, ncols_dst) + +DECL_MMF_CASE_EXTERN(1); +DECL_MMF_CASE_EXTERN(2); +DECL_MMF_CASE_EXTERN(3); +DECL_MMF_CASE_EXTERN(4); +DECL_MMF_CASE_EXTERN(5); +DECL_MMF_CASE_EXTERN(6); +DECL_MMF_CASE_EXTERN(7); +DECL_MMF_CASE_EXTERN(8); +DECL_MMF_CASE_EXTERN(9); +DECL_MMF_CASE_EXTERN(10); +DECL_MMF_CASE_EXTERN(11); +DECL_MMF_CASE_EXTERN(12); +DECL_MMF_CASE_EXTERN(13); +DECL_MMF_CASE_EXTERN(14); +DECL_MMF_CASE_EXTERN(15); +DECL_MMF_CASE_EXTERN(16); +#else +#define DECL_MMF_CASE(ncols_dst) +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmq.cu 6641+dfsg-2/ggml/src/ggml-cuda/mmq.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mmq.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmq.cu 2025-09-30 07:36:33.000000000 +0000 @@ -3,6 +3,140 @@ #include +// To reduce shared memory use, store "it" and "iex_used" with 22/10 bits each. +struct mmq_ids_helper_store { + uint32_t data; + + __device__ mmq_ids_helper_store(const uint32_t it, const uint32_t iex_used) { + data = (it & 0x003FFFFF) | (iex_used << 22); + } + + __device__ uint32_t it() const { + return data & 0x003FFFFF; + } + + __device__ uint32_t iex_used() const { + return data >> 22; + } +}; +static_assert(sizeof(mmq_ids_helper_store) == 4, "unexpected size for mmq_ids_helper_store"); + +// Helper function for mul_mat_id, converts ids to a more convenient format. +// ids_src1 describes how to permute the flattened column indices of src1 in order to get a compact src1 tensor sorted by expert. +// ids_dst describes the same mapping but for the dst tensor. +// The upper and lower bounds for the ith expert in the compact src1 tensor are stored in expert_bounds[i:i+1]. +template +__launch_bounds__(ggml_cuda_get_physical_warp_size(), 1) +static __global__ void mmq_ids_helper( + const int32_t * __restrict__ ids, int32_t * __restrict__ ids_src1, int32_t * __restrict__ ids_dst, int32_t * __restrict__ expert_bounds, + const int n_tokens, const int n_expert_used_var, const int nchannels_y, const int si1, const int sis1) { + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + const int n_expert_used = n_expert_used_template == 0 ? n_expert_used_var : n_expert_used_template; + const int expert = blockIdx.x; + + extern __shared__ char data_mmq_ids_helper[]; + mmq_ids_helper_store * store = (mmq_ids_helper_store *) data_mmq_ids_helper; + + int nex_prev = 0; // Number of columns for experts with a lower index. + int it_compact = 0; // Running index for the compact slice of this expert. + + if constexpr (n_expert_used_template == 0) { + // Generic implementation: + for (int it = 0; it < n_tokens; ++it) { + int iex_used = -1; // The index at which the expert is used, if any. + for (int iex = threadIdx.x; iex < n_expert_used; iex += warp_size) { + const int expert_used = ids[it*si1 + iex]; + nex_prev += expert_used < expert; + if (expert_used == expert) { + iex_used = iex; + } + } + + if (iex_used != -1) { + store[it_compact] = mmq_ids_helper_store(it, iex_used); + } + + if (warp_reduce_any(iex_used != -1)) { + it_compact++; + } + } + } else { + // Implementation optimized for specific numbers of experts used: + static_assert(n_expert_used == 6 || warp_size % n_expert_used == 0, "bad n_expert_used"); + const int neu_padded = n_expert_used == 6 ? 8 : n_expert_used; // Padded to next higher power of 2. + for (int it0 = 0; it0 < n_tokens; it0 += warp_size/neu_padded) { + const int it = it0 + threadIdx.x / neu_padded; + + const int iex = threadIdx.x % neu_padded; // The index at which the expert is used, if any. + const int expert_used = (neu_padded == n_expert_used || iex < n_expert_used) && it < n_tokens ? + ids[it*si1 + iex] : INT_MAX; + const int iex_used = expert_used == expert ? iex : -1; + nex_prev += expert_used < expert; + + // Whether the threads at this token position have used the expert: + const int it_compact_add_self = warp_reduce_any(iex_used != -1); + + // Do a scan over threads at lower token positions in warp to get the correct index for writing data: + int it_compact_add_lower = 0; +#pragma unroll + for (int offset = neu_padded; offset < warp_size; offset += neu_padded) { + const int tmp = __shfl_up_sync(0xFFFFFFFF, it_compact_add_self, offset, warp_size); + if (threadIdx.x >= static_cast(offset)) { + it_compact_add_lower += tmp; + } + } + + if (iex_used != -1) { + store[it_compact + it_compact_add_lower] = mmq_ids_helper_store(it, iex_used); + } + + // The thread with the highest index in the warp always has the sum over the whole warp, use it to increment all threads: + it_compact += __shfl_sync(0xFFFFFFFF, it_compact_add_lower + it_compact_add_self, warp_size - 1, warp_size); + } + } + nex_prev = warp_reduce_sum(nex_prev); + + for (int itc = threadIdx.x; itc < it_compact; itc += warp_size) { + const mmq_ids_helper_store store_it = store[itc]; + const int it = store_it.it(); + const int iex_used = store_it.iex_used(); + ids_src1[nex_prev + itc] = it*sis1 + iex_used % nchannels_y; + ids_dst [nex_prev + itc] = it*n_expert_used + iex_used; + } + + if (threadIdx.x != 0) { + return; + } + + expert_bounds[expert] = nex_prev; + + if (expert < static_cast(gridDim.x) - 1) { + return; + } + + expert_bounds[gridDim.x] = nex_prev + it_compact; +} + +template +static void launch_mmq_ids_helper( + const int32_t * __restrict__ ids, int32_t * __restrict__ ids_src1, int32_t * __restrict__ ids_dst, int32_t * __restrict__ expert_bounds, + const int n_experts, const int n_tokens, const int n_expert_used_var, const int nchannels_y, const int si1, const int sis1, cudaStream_t stream) { + GGML_ASSERT(n_tokens < (1 << 22) && "too few bits in mmq_ids_helper_store"); + GGML_ASSERT(n_expert_used_var < (1 << 10) && "too few bits in mmq_ids_helper_store"); + + const int id = ggml_cuda_get_device(); + const int warp_size = ggml_cuda_info().devices[id].warp_size; + const size_t smpbo = ggml_cuda_info().devices[id].smpbo; + CUDA_SET_SHARED_MEMORY_LIMIT(mmq_ids_helper, smpbo); + + const dim3 num_blocks(n_experts, 1, 1); + const dim3 block_size(warp_size, 1, 1); + const size_t nbytes_shared = n_tokens*sizeof(mmq_ids_helper_store); + GGML_ASSERT(nbytes_shared <= smpbo); + mmq_ids_helper<<>> + (ids, ids_src1, ids_dst, expert_bounds, n_tokens, n_expert_used_var, nchannels_y, si1, sis1); +} + static void ggml_cuda_mul_mat_q_switch_type(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { switch (args.type_x) { case GGML_TYPE_Q4_0: @@ -20,6 +154,9 @@ static void ggml_cuda_mul_mat_q_switch_t case GGML_TYPE_Q8_0: mul_mat_q_case(ctx, args, stream); break; + case GGML_TYPE_MXFP4: + mul_mat_q_case(ctx, args, stream); + break; case GGML_TYPE_Q2_K: mul_mat_q_case(ctx, args, stream); break; @@ -109,7 +246,8 @@ void ggml_cuda_mul_mat_q( const int64_t s03 = src0->nb[3] / ts_src0; const int64_t s3 = dst->nb[3] / ts_dst; - const bool use_stream_k = GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA; + const bool use_stream_k = (GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) + || GGML_CUDA_CC_IS_CDNA(cc); if (!ids) { const size_t nbytes_src1_q8_1 = ne13*ne12 * ne11*ne10_padded * sizeof(block_q8_1)/QK8_1 + @@ -133,7 +271,7 @@ void ggml_cuda_mul_mat_q( ne00, ne01, ne1, s01, ne11, s1, ne02, ne12, s02, s12, s2, ne03, ne13, s03, s13, s3, - use_stream_k}; + use_stream_k, ne1}; ggml_cuda_mul_mat_q_switch_type(ctx, args, stream); return; } @@ -144,54 +282,50 @@ void ggml_cuda_mul_mat_q( const int64_t n_expert_used = ids->ne[0]; const int64_t ne_get_rows = ne12 * n_expert_used; + GGML_ASSERT(ne1 == n_expert_used); - std::vector ids_host(ggml_nbytes(ids)); - std::vector ids_src1_host; - ids_src1_host.reserve(ne_get_rows); - std::vector ids_dst_host; - ids_dst_host.reserve(ne_get_rows); - std::vector tokens_per_expert_host(ne02); - std::vector expert_bounds_host(ne02 + 1); - ggml_cuda_pool_alloc ids_buf_dev(ctx.pool()); - - CUDA_CHECK(cudaMemcpyAsync(ids_host.data(), ids->data, ggml_nbytes(ids), cudaMemcpyDeviceToHost, stream)); - CUDA_CHECK(cudaStreamSynchronize(stream)); - - for (int64_t i02 = 0; i02 < ne02; ++i02) { // expert matrices - for (int64_t i12 = 0; i12 < ne12; ++i12) { // tokens - for (int64_t iex = 0; iex < n_expert_used; ++iex) { - const int32_t expert_to_use = *(const int32_t *)(ids_host.data() + i12*ids->nb[1] + iex*ids->nb[0]); - assert(expert_to_use >= 0 && expert_to_use < ne02); - if (expert_to_use == i02) { - ids_src1_host.push_back(i12*(nb12/nb11) + iex % ne11); - ids_dst_host.push_back(i12*ne1 + iex); - tokens_per_expert_host[i02]++; - break; - } - } + ggml_cuda_pool_alloc ids_src1(ctx.pool(), ne_get_rows); + ggml_cuda_pool_alloc ids_dst(ctx.pool(), ne_get_rows); + ggml_cuda_pool_alloc expert_bounds(ctx.pool(), ne02 + 1); + + { + GGML_ASSERT(ids->nb[0] == ggml_element_size(ids)); + const int si1 = ids->nb[1] / ggml_element_size(ids); + const int sis1 = nb12 / nb11; + + switch (n_expert_used) { + case 2: + launch_mmq_ids_helper< 2> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + case 4: + launch_mmq_ids_helper< 4> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + case 6: + launch_mmq_ids_helper< 6> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + case 8: + launch_mmq_ids_helper< 8> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + case 16: + launch_mmq_ids_helper<16> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + case 32: + launch_mmq_ids_helper<32> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; + default: + launch_mmq_ids_helper< 0> ((const int32_t *) ids->data, ids_src1.get(), ids_dst.get(), expert_bounds.get(), + ne02, ne12, n_expert_used, ne11, si1, sis1, stream); + break; } + CUDA_CHECK(cudaGetLastError()); } - int32_t cumsum = 0; - for (int64_t i = 0; i < ne02; ++i) { - expert_bounds_host[i] = cumsum; - cumsum += tokens_per_expert_host[i]; - } - expert_bounds_host[ne02] = cumsum; - - std::vector ids_buf_host; - ids_buf_host.reserve(ids_src1_host.size() + ids_dst_host.size() + expert_bounds_host.size()); - ids_buf_host.insert(ids_buf_host.end(), ids_src1_host.begin(), ids_src1_host.end()); - ids_buf_host.insert(ids_buf_host.end(), ids_dst_host.begin(), ids_dst_host.end()); - ids_buf_host.insert(ids_buf_host.end(), expert_bounds_host.begin(), expert_bounds_host.end()); - ids_buf_dev.alloc(ids_buf_host.size() + get_mmq_x_max_host(cc)); // Expert bounds are padded on device. - CUDA_CHECK(cudaMemcpyAsync(ids_buf_dev.ptr, ids_buf_host.data(), ids_buf_host.size()*sizeof(int32_t), cudaMemcpyHostToDevice, stream)); - CUDA_CHECK(cudaStreamSynchronize(stream)); - - const int32_t * ids_src1_dev = ids_buf_dev.ptr; - const int32_t * ids_dst_dev = ids_src1_dev + ids_src1_host.size(); - const int32_t * expert_bounds_dev = ids_dst_dev + ids_dst_host.size(); - const size_t nbytes_src1_q8_1 = ne12*n_expert_used*ne10_padded * sizeof(block_q8_1)/QK8_1 + get_mmq_x_max_host(cc)*sizeof(block_q8_1_mmq); ggml_cuda_pool_alloc src1_q8_1(ctx.pool(), nbytes_src1_q8_1); @@ -204,7 +338,7 @@ void ggml_cuda_mul_mat_q( const int64_t s11 = src1->nb[1] / ts_src1; const int64_t s12 = src1->nb[2] / ts_src1; const int64_t s13 = src1->nb[2] / ts_src1; - quantize_mmq_q8_1_cuda(src1_d, ids_src1_dev, src1_q8_1.get(), src0->type, + quantize_mmq_q8_1_cuda(src1_d, ids_src1.get(), src1_q8_1.get(), src0->type, ne10, s11, s12, s13, ne10_padded, ne11_flat, ne12_flat, ne13_flat, stream); CUDA_CHECK(cudaGetLastError()); } @@ -214,11 +348,11 @@ void ggml_cuda_mul_mat_q( // Note that ne02 is used instead of ne12 because the number of y channels determines the z dimension of the CUDA grid. const mmq_args args = { - src0_d, src0->type, (const int *) src1_q8_1.ptr, ids_dst_dev, expert_bounds_dev, dst_d, + src0_d, src0->type, (const int *) src1_q8_1.get(), ids_dst.get(), expert_bounds.get(), dst_d, ne00, ne01, ne_get_rows, s01, ne_get_rows, s1, ne02, ne02, s02, s12, s2, ne03, ne13, s03, s13, s3, - use_stream_k}; + use_stream_k, ne12}; ggml_cuda_mul_mat_q_switch_type(ctx, args, stream); } @@ -250,21 +384,19 @@ void ggml_cuda_op_mul_mat_q( // The stream-k decomposition is only faster for recent NVIDIA GPUs. // Also its fixup needs to allocate a temporary buffer in the memory pool. // There are multiple parallel CUDA streams for src1_ncols != ne11 which would introduce a race condition for this buffer. - const bool use_stream_k = GGML_CUDA_CC_IS_NVIDIA(cc) && - ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA && src1_ncols == ne11; + const bool use_stream_k = ((GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA) + || GGML_CUDA_CC_IS_CDNA(cc)) + && src1_ncols == ne11; const mmq_args args = { src0_dd_i, src0->type, (const int *) src1_ddq_i, nullptr, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride01, ne11, nrows_dst, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, - use_stream_k}; + use_stream_k, src1_ncols}; ggml_cuda_mul_mat_q_switch_type(ctx, args, stream); - GGML_UNUSED(src1); - GGML_UNUSED(dst); - GGML_UNUSED(src1_ddf_i); - GGML_UNUSED(src1_padded_row_size); + GGML_UNUSED_VARS(src1, dst, src1_ddf_i, src1_padded_row_size); } bool ggml_cuda_should_use_mmq(enum ggml_type type, int cc, int64_t ne11) { @@ -280,6 +412,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_ case GGML_TYPE_Q5_0: case GGML_TYPE_Q5_1: case GGML_TYPE_Q8_0: + case GGML_TYPE_MXFP4: case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -304,7 +437,7 @@ bool ggml_cuda_should_use_mmq(enum ggml_ return false; } - if (new_mma_available(cc)) { + if (turing_mma_available(cc)) { return true; } @@ -320,5 +453,21 @@ bool ggml_cuda_should_use_mmq(enum ggml_ return !fp16_mma_hardware_available(cc) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE; } + if (amd_mfma_available(cc)) { + // As of ROCM 7.0 rocblas/tensile performs very poorly on CDNA3 and hipblaslt (via ROCBLAS_USE_HIPBLASLT) + // performs better but is currently suffering from a crash on this architecture. + // TODO: Revisit when hipblaslt is fixed on CDNA3 + if (GGML_CUDA_CC_IS_CDNA3(cc)) { + return true; + } + if (ne11 <= 128 || type == GGML_TYPE_Q4_0 || type == GGML_TYPE_Q4_1 || type == GGML_TYPE_Q5_0 || type == GGML_TYPE_Q5_1) { + return true; + } + if (ne11 <= 256 && (type == GGML_TYPE_Q4_K || type == GGML_TYPE_Q5_K)) { + return true; + } + return false; + } + return (!GGML_CUDA_CC_IS_RDNA4(cc) && !GGML_CUDA_CC_IS_RDNA3(cc) && !GGML_CUDA_CC_IS_CDNA(cc)) || ne11 < MMQ_DP4A_MAX_BATCH_SIZE; } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmq.cuh 6641+dfsg-2/ggml/src/ggml-cuda/mmq.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/mmq.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmq.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -58,6 +58,8 @@ static mmq_q8_1_ds_layout mmq_get_q8_1_d return MMQ_Q8_1_DS_LAYOUT_DS4; case GGML_TYPE_Q8_0: return MMQ_Q8_1_DS_LAYOUT_D4; + case GGML_TYPE_MXFP4: + return MMQ_Q8_1_DS_LAYOUT_D4; case GGML_TYPE_Q2_K: return MMQ_Q8_1_DS_LAYOUT_D2S6; case GGML_TYPE_Q3_K: @@ -90,7 +92,7 @@ struct tile_x_sizes { }; static int get_mmq_x_max_host(const int cc) { - return new_mma_available(cc) ? 128 : + return (amd_mfma_available(cc) || turing_mma_available(cc)) ? 128 : GGML_CUDA_CC_IS_NVIDIA(cc) && ggml_cuda_highest_compiled_arch(cc) >= GGML_CUDA_CC_VOLTA ? #ifdef GGML_CUDA_FORCE_MMQ 128 : 64; @@ -100,13 +102,13 @@ static int get_mmq_x_max_host(const int } static constexpr __device__ int get_mmq_x_max_device() { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) return 128; -#else // NEW_MMA_AVAILABLE +#else // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) - return 128; -#else // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) + return 64; +#else // defined(GGML_USE_HIP) #if __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA #ifdef GGML_CUDA_FORCE_MMQ @@ -115,12 +117,11 @@ static constexpr __device__ int get_mmq_ return MMQ_DP4A_MAX_BATCH_SIZE; #endif // GGML_CUDA_FORCE_MMQ #else // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA - return 64; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) -#endif // NEW_MMA_AVAILABLE +#endif // defined(GGML_USE_HIP) +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } static int get_mmq_y_host(const int cc) { @@ -129,7 +130,7 @@ static int get_mmq_y_host(const int cc) } static constexpr __device__ int get_mmq_y_device() { -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#if defined(GGML_USE_HIP) #if defined(RDNA1) return 64; #else @@ -141,19 +142,28 @@ static constexpr __device__ int get_mmq_ #else return 64; #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) } -#define MMQ_DP4A_TXS_Q4_0 tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_0 + mmq_y/QI4_0, 0} -#define MMQ_DP4A_TXS_Q4_1 tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_1 + mmq_y/QI4_1, 0} -#define MMQ_DP4A_TXS_Q8_0 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*2/QI8_0 + mmq_y/(QI8_0/2), 0} -#define MMQ_DP4A_TXS_Q8_0_16 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*4/QI8_0 + mmq_y/(QI8_0/4), 0} -#define MMQ_DP4A_TXS_Q8_1 tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE*2/QI8_1 + mmq_y/(QI8_1/2), 0} -#define MMQ_DP4A_TXS_Q2_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE + mmq_y, 0} -#define MMQ_DP4A_TXS_Q3_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q4_K tile_x_sizes{mmq_y*WARP_SIZE + mmq_y, mmq_y*WARP_SIZE/QI4_K, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q5_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE/QI5_K + mmq_y/QI5_K, mmq_y*WARP_SIZE/8 + mmq_y/8} -#define MMQ_DP4A_TXS_Q6_K tile_x_sizes{mmq_y*WARP_SIZE*2 + mmq_y, mmq_y*WARP_SIZE/QI6_K + mmq_y/QI6_K, mmq_y*WARP_SIZE/8 + mmq_y/8} +// Decouple shared memory tile sizes from WARP_SIZE to allow for different warp sizes. +// The K dimension of the tiles has either, +// 1*MMQ_TILE_NE_K==32 (always for TILE_Y_K) or 2*MMQ_TILE_NE_K==64 (typically for TILE_X_K), +// 32 bit elements for the quantized data (does not include scales). +// In other words, the size of the quantized data in the K dimension is a multiple of MMQ_TILE_NE_K. +// The final tile size in K direction is padded to avoid shared memory bank conflicts, +// in terms of 32 bit elements that means K % 2 == 1 for dp4a or K % 8 == 4 for mma. +#define MMQ_TILE_NE_K 32 + +#define MMQ_DP4A_TXS_Q4_0 tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_0 + mmq_y/QI4_0, 0} +#define MMQ_DP4A_TXS_Q4_1 tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_1 + mmq_y/QI4_1, 0} +#define MMQ_DP4A_TXS_Q8_0 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*2/QI8_0 + mmq_y/(QI8_0/2), 0} +#define MMQ_DP4A_TXS_Q8_0_16 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*4/QI8_0 + mmq_y/(QI8_0/4), 0} +#define MMQ_DP4A_TXS_Q8_1 tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K*2/QI8_1 + mmq_y/(QI8_1/2), 0} +#define MMQ_DP4A_TXS_Q2_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K + mmq_y, 0} +#define MMQ_DP4A_TXS_Q3_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q4_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K + mmq_y, mmq_y*MMQ_TILE_NE_K/QI4_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q5_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K/QI5_K + mmq_y/QI5_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} +#define MMQ_DP4A_TXS_Q6_K tile_x_sizes{mmq_y*MMQ_TILE_NE_K*2 + mmq_y, mmq_y*MMQ_TILE_NE_K/QI6_K + mmq_y/QI6_K, mmq_y*MMQ_TILE_NE_K/8 + mmq_y/8} static constexpr __host__ __device__ tile_x_sizes mmq_get_dp4a_tile_x_sizes(ggml_type type, int mmq_y) { switch (type) { @@ -162,6 +172,7 @@ static constexpr __host__ __device__ til case GGML_TYPE_Q5_0: return MMQ_DP4A_TXS_Q8_0; case GGML_TYPE_Q5_1: return MMQ_DP4A_TXS_Q8_1; case GGML_TYPE_Q8_0: return MMQ_DP4A_TXS_Q8_0; + case GGML_TYPE_MXFP4: return MMQ_DP4A_TXS_Q8_1; case GGML_TYPE_Q2_K: return MMQ_DP4A_TXS_Q2_K; case GGML_TYPE_Q3_K: return MMQ_DP4A_TXS_Q3_K; case GGML_TYPE_Q4_K: return MMQ_DP4A_TXS_Q4_K; @@ -179,11 +190,11 @@ static constexpr __host__ __device__ til } } -#define MMQ_MMA_TILE_X_K_Q8_0 (2*WARP_SIZE + 2*WARP_SIZE/QI8_0 + 4) -#define MMQ_MMA_TILE_X_K_Q8_1 (2*WARP_SIZE + 2*WARP_SIZE/QI8_0 + 4) -#define MMQ_MMA_TILE_X_K_Q2_K (2*WARP_SIZE + WARP_SIZE + 4) -#define MMQ_MMA_TILE_X_K_Q3_K (2*WARP_SIZE + WARP_SIZE/2 + 4) -#define MMQ_MMA_TILE_X_K_Q6_K (2*WARP_SIZE + WARP_SIZE/QI6_K + WARP_SIZE/8 + 7) +#define MMQ_MMA_TILE_X_K_Q8_0 (2*MMQ_TILE_NE_K + 2*MMQ_TILE_NE_K/QI8_0 + 4) +#define MMQ_MMA_TILE_X_K_Q8_1 (2*MMQ_TILE_NE_K + 2*MMQ_TILE_NE_K/QI8_0 + 4) +#define MMQ_MMA_TILE_X_K_Q2_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K + 4) +#define MMQ_MMA_TILE_X_K_Q3_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K/2 + 4) +#define MMQ_MMA_TILE_X_K_Q6_K (2*MMQ_TILE_NE_K + MMQ_TILE_NE_K/QI6_K + MMQ_TILE_NE_K/8 + 7) static_assert(MMQ_MMA_TILE_X_K_Q8_0 % 8 == 4, "Wrong padding."); static_assert(MMQ_MMA_TILE_X_K_Q8_1 % 8 == 4, "Wrong padding."); @@ -198,6 +209,7 @@ static constexpr __host__ __device__ int case GGML_TYPE_Q5_0: return MMQ_MMA_TILE_X_K_Q8_0; case GGML_TYPE_Q5_1: return MMQ_MMA_TILE_X_K_Q8_1; case GGML_TYPE_Q8_0: return MMQ_MMA_TILE_X_K_Q8_0; + case GGML_TYPE_MXFP4: return MMQ_MMA_TILE_X_K_Q8_1; case GGML_TYPE_Q2_K: return MMQ_MMA_TILE_X_K_Q2_K; case GGML_TYPE_Q3_K: return MMQ_MMA_TILE_X_K_Q3_K; case GGML_TYPE_Q4_K: return MMQ_MMA_TILE_X_K_Q8_1; @@ -215,42 +227,76 @@ static constexpr __host__ __device__ int } } -#define MMQ_TILE_Y_K (WARP_SIZE + WARP_SIZE/QI8_1) +// block_q8_1_mmq has (128 8-bit ints == 32 32-bit ints + 4 32-bit scales) +#define MMQ_TILE_Y_K (MMQ_TILE_NE_K + MMQ_TILE_NE_K/QI8_1) static int mmq_get_granularity_host(const int mmq_x, const int cc) { - return new_mma_available(cc) && mmq_x >= 48 ? 16 : 8; + if (amd_mfma_available(cc)) { + return mmq_x >= 128 ? 32 : 16; + } else if (turing_mma_available(cc) && mmq_x >= 48) { + return 16; + } else { + return 8; + } } -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) +static constexpr __device__ int mmq_get_granularity_device(const int mmq_x) { + return mmq_x >= 128 ? 32 : 16; +} +#elif defined(TURING_MMA_AVAILABLE) static constexpr __device__ int mmq_get_granularity_device(const int mmq_x) { return mmq_x >= 48 ? 16 : 8; } #else -static constexpr __device__ int mmq_get_granularity_device(const int /* mmq_x */) { +static constexpr __device__ int mmq_get_granularity_device(const int /*mmq_x*/) { return 8; } -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE + +#if defined(GGML_USE_HIP) +static int mmq_get_nwarps_host(const int cc, const int warp_size) { + return amd_mfma_available(cc) ? 8 : 256/warp_size; +} +#else +static int mmq_get_nwarps_host(const int /*cc*/, const int warp_size) { + return 256/warp_size; +} +#endif // (GGML_USE_HIP) + +static constexpr __device__ int mmq_get_nwarps_device() { +#if defined(AMD_MFMA_AVAILABLE) + return 8; +#else + return 256/ggml_cuda_get_physical_warp_size(); +#endif // AMD_MFMA_AVAILABLE +} // ------------------------------------------------------------ -template static __device__ __forceinline__ void load_tiles_q4_0( +template static __device__ __forceinline__ void load_tiles_q4_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + 2*WARP_SIZE); + float * x_df = (float *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_0; - const int kqsx = threadIdx.x % QI4_0; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_0); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_0; + const int kqsx = txi % QI4_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -259,20 +305,21 @@ template qs, kqsx); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI4_0) + kqsx + 0] = __vsubss4((qs0 >> 0) & 0x0F0F0F0F, 0x08080808); x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI4_0) + kqsx + QI4_0] = __vsubss4((qs0 >> 4) & 0x0F0F0F0F, 0x08080808); #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_0; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_0; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_0) { - int i = i0 + threadIdx.y * QI4_0 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -280,17 +327,19 @@ template d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; #else - x_df[i*(WARP_SIZE/QI4_0) + i/QI4_0 + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI4_0) + i/QI4_0 + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q4_0_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_0, mmq_y); const int * x_qs = (const int *) x; @@ -299,7 +348,7 @@ static __device__ __forceinline__ void v const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_0*VDR_Q4_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_0*VDR_Q4_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -307,7 +356,7 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; const int kyqs = QI8_1 * ((k01/2) / (QI8_1/2)) + (k01/2) % (QI8_1/2); @@ -320,32 +369,37 @@ static __device__ __forceinline__ void v u[2*l+1] = y_qs[j*MMQ_TILE_Y_K + kyqs + (l + QI4_0)]; } - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_0_q8_1_impl - (&x_qs[i*(WARP_SIZE + 1) + k0/QR4_0], u, - x_df[i*(WARP_SIZE/QI4_0) + i/QI4_0 + k0/(QR4_0*QI4_0)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_0_q8_1_impl + (&x_qs[i*(MMQ_TILE_NE_K + 1) + k0/QR4_0], u, + x_df[i*(MMQ_TILE_NE_K/QI4_0) + i/QI4_0 + k0/(QR4_0*QI4_0)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q4_1( +template static __device__ __forceinline__ void load_tiles_q4_1( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_1, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_1; - const int kqsx = threadIdx.x % QI4_1; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_1); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_1; + const int kqsx = txi % QI4_1; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -354,20 +408,21 @@ template qs, kqsx); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI4_1) + kqsx + 0] = (qs0 >> 0) & 0x0F0F0F0F; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI4_1) + kqsx + QI4_1] = (qs0 >> 4) & 0x0F0F0F0F; #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_1; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_1; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_1) { - int i = i0 + threadIdx.y * QI4_1 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -375,17 +430,19 @@ template dm; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; #else - x_dm[i*(WARP_SIZE/QI4_1) + i/QI4_1 + kbxd] = bxi->dm; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K/QI4_1) + i/QI4_1 + kbxd] = bxi->dm; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q4_1_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_1, mmq_y); const int * x_qs = (const int *) x; @@ -394,7 +451,7 @@ static __device__ __forceinline__ void v const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_1*VDR_Q4_1_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_1*VDR_Q4_1_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -402,7 +459,7 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; const int kyqs = QI8_1 * ((k01/2) / (QI8_1/2)) + (k01/2) % (QI8_1/2); @@ -415,32 +472,37 @@ static __device__ __forceinline__ void v u[2*l+1] = y_qs[j*MMQ_TILE_Y_K + kyqs + (l + QI4_1)]; } - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_1_q8_1_impl - (&x_qs[i*(WARP_SIZE + 1) + k0/QR4_1], u, - x_dm[i*(WARP_SIZE/QI4_1) + i/QI4_1 + k0/(QR4_1*QI4_1)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_1_q8_1_impl + (&x_qs[i*(MMQ_TILE_NE_K + 1) + k0/QR4_1], u, + x_dm[i*(MMQ_TILE_NE_K/QI4_1) + i/QI4_1 + k0/(QR4_1*QI4_1)], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q5_0( +template static __device__ __forceinline__ void load_tiles_q5_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI5_0; - const int kqsx = threadIdx.x % QI5_0; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_0); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI5_0; + const int kqsx = txi % QI5_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -449,7 +511,7 @@ template qs, kqsx); - const int qh = get_int_b2(bxi->qh, 0) >> (4 * (threadIdx.x % QI5_0)); + const int qh = get_int_b2(bxi->qh, 0) >> (4 * kqsx); int qs0 = (ql >> 0) & 0x0F0F0F0F; qs0 |= (qh << 4) & 0x00000010; // 0 -> 4 @@ -465,21 +527,22 @@ template 28 qs1 = __vsubss4(qs1, 0x10101010); // subtract 16 -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI5_0) + kqsx + 0] = qs0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; #else - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_0) + kqsx + 0] = qs0; - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_0) + kqsx + 0] = qs0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_0) + kqsx + QI5_0] = qs1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI5_0; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI5_0; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI5_0) { - int i = i0 + threadIdx.y * QI5_0 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -487,32 +550,37 @@ template d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; #else - x_df[i*(WARP_SIZE/QI5_0) + i/QI5_0 + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI5_0) + i/QI5_0 + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_q5_1( +template static __device__ __forceinline__ void load_tiles_q5_1( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_1, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI5_1; - const int kqsx = threadIdx.x % QI5_1; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_1); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI5_1; + const int kqsx = txi % QI5_1; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -521,7 +589,7 @@ template qs, kqsx); - const int qh = get_int_b4(bxi->qh, 0) >> (4 * (threadIdx.x % QI5_1)); + const int qh = get_int_b4(bxi->qh, 0) >> (4 * kqsx); int qs0 = (ql >> 0) & 0x0F0F0F0F; qs0 |= (qh << 4) & 0x00000010; // 0 -> 4 @@ -535,21 +603,22 @@ template 20 qs1 |= (qh << 9) & 0x10000000; // 19 -> 28 -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI5_1) + kqsx + 0] = qs0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; #else - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_1) + kqsx + 0] = qs0; - x_qs[i*(2*WARP_SIZE + 1) + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_1) + kqsx + 0] = qs0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kbx*(2*QI5_1) + kqsx + QI5_1] = qs1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI5_1; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI5_1; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI5_1) { - int i = i0 + threadIdx.y * QI5_1 + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -557,32 +626,38 @@ template dm; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = bxi->dm; #else - x_dm[i*(WARP_SIZE/QI5_1) + i/QI5_1 + kbxd] = bxi->dm; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K/QI5_1) + i/QI5_1 + kbxd] = bxi->dm; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_q8_0( +template static __device__ __forceinline__ void load_tiles_q8_0( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_tile + 2*WARP_SIZE); + float * x_df = (float *) (x_tile + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q8_0, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI8_0; - const int kqsx = threadIdx.x % QI8_0; + // MMQ_ITER_K / (4 * QR8_0) == 64 required. but NV has only 32 threads per warp + constexpr int threads_per_row = 32; + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI8_0; + const int kqsx = txi % QI8_0; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -590,21 +665,22 @@ template d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = bxi->d; +#else + x_df[i*(2*MMQ_TILE_NE_K/QI8_0) + i/(QI8_0/2) + kbxd] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + } +} + +template static __device__ __forceinline__ void load_tiles_mxfp4( + const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); +#else + constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_MXFP4, mmq_y); + int * x_qs = (int *) x_tile; + float * x_df = (float *) (x_qs + txs.qs); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR_MXFP4); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI_MXFP4; + const int kqsx = txi % QI_MXFP4; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); + + if (need_check) { + i = min(i, i_max); + } + + const block_mxfp4 * bxi = (const block_mxfp4 *) x + kbx0 + i*stride + kbx; + + const int aux_q4 = get_int_b1(bxi->qs, kqsx); + const int2 v = get_int_from_table_16(aux_q4, kvalues_mxfp4); + const int k0 = kbx * (2 * QI_MXFP4) + kqsx; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + k0 + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + k0 + QI_MXFP4] = v.y; #else - x_df[i*(2*WARP_SIZE/QI8_0) + i/(QI8_0/2) + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + QI_MXFP4] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + } + + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI_MXFP4; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; + const int kbxd = threadIdx.x % blocks_per_tile_x_row; + +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; + + if (need_check) { + i = min(i, i_max); + } + + const block_mxfp4 * bxi = (const block_mxfp4 *) x + kbx0 + i*stride + kbxd; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_1 + kbxd] = ggml_cuda_e8m0_to_fp32(bxi->e)*0.5f; +#else + x_df[i*(MMQ_TILE_NE_K/QI_MXFP4) + i/QI_MXFP4 + kbxd] = ggml_cuda_e8m0_to_fp32(bxi->e)*0.5f; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q8_0_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q8_0, mmq_y); const int * x_qs = (const int *) x; @@ -631,7 +774,7 @@ static __device__ __forceinline__ void v const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += VDR_Q8_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += VDR_Q8_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -639,21 +782,76 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_0_q8_1_impl - (&x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k0 % WARP_SIZE], - x_df[i*(2*WARP_SIZE/QI8_0) + i/(QI8_0/2) + k0/QI8_0], y_df[j*MMQ_TILE_Y_K + (k0/QI8_1) % (WARP_SIZE/QI8_1)]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_0_q8_1_impl + (&x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k0 % MMQ_TILE_NE_K], + x_df[i*(2*MMQ_TILE_NE_K/QI8_0) + i/(QI8_0/2) + k0/QI8_0], y_df[j*MMQ_TILE_Y_K + (k0/QI8_1) % (MMQ_TILE_NE_K/QI8_1)]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q8_0_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + 2*MMQ_TILE_NE_K; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + const half2 * y_ds = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(A[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_0 + k0, MMQ_MMA_TILE_X_K_Q8_0); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B; + load_generic(B, y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + float dB; + const int j = j0 + tile_C::get_j(0); + if (ds_layout == MMQ_Q8_1_DS_LAYOUT_D4) { + dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1]; + } else { + dB = __low2float(y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + } + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_A::I + tile_C::get_i(l); + const float dA = x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + k0/QI8_0]; + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l]*dA*dB; + } + } + } + } +#else typedef tile<16, 8, int> tile_A; typedef tile< 8, 8, int> tile_B; typedef tile<16, 8, int> tile_C; @@ -662,23 +860,23 @@ static __device__ __forceinline__ void v constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + 2*WARP_SIZE; + const float * x_df = (const float *) x_qs + 2*MMQ_TILE_NE_K; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; const half2 * y_ds = (const half2 *) y; - tile_A A[ntx][WARP_SIZE/QI8_0]; - float dA[ntx][tile_C::ne/2][WARP_SIZE/QI8_0]; + tile_A A[ntx][MMQ_TILE_NE_K/QI8_0]; + float dA[ntx][tile_C::ne/2][MMQ_TILE_NE_K/QI8_0]; const int i0 = (threadIdx.y/ntx)*rows_per_warp; #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/QI8_0], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_0 + k0, MMQ_MMA_TILE_X_K_Q8_0); @@ -689,7 +887,7 @@ static __device__ __forceinline__ void v const int i = i0 + n*tile_A::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; dA[n][l][k01/QI8_0] = x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + k0/QI8_0]; @@ -700,7 +898,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { tile_B B; float dB[tile_C::ne/2]; @@ -729,11 +927,14 @@ static __device__ __forceinline__ void v } } } +#endif // defined(AMD_MFMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q8_1_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_1, mmq_y); const int * x_qs = (const int *) x; @@ -742,7 +943,7 @@ static __device__ __forceinline__ void v const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += VDR_Q8_0_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += VDR_Q8_0_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -750,45 +951,95 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_1_q8_1_impl - (&x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - x_dm[i*(WARP_SIZE/QI5_1) + i/QI5_1 + k0/QI8_1], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_1_q8_1_impl + (&x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + x_dm[i*(MMQ_TILE_NE_K/QI5_1) + i/QI5_1 + k0/QI8_1], y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q8_1_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; - typedef tile<16, 8, int> tile_A; - typedef tile< 8, 8, int> tile_B; - typedef tile<16, 8, int> tile_C; + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const half2 * x_dm = (const half2 *) x_qs + 2*MMQ_TILE_NE_K; + const int * y_qs = (const int *) y + 4; + const half2 * y_dm = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(A[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_1 + k0, MMQ_MMA_TILE_X_K_Q8_1); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B; + load_generic(B, y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float2 dsB = __half22float2(y_dm[j*MMQ_TILE_Y_K + k01/QI8_1]); + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_A::I + tile_C::get_i(l); + float2 dmA = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + k0/QI8_1]); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += dmA.x*dsB.x*C.x[l]; + sum[(j0/tile_C::J + n)*tile_C::ne + l] += dmA.y*dsB.y; + } + } + } + } +#else + typedef tile<16, 8, int> tile_A; + typedef tile< 8, 8, int> tile_B; + typedef tile<16, 8, int> tile_C; constexpr int granularity = mmq_get_granularity_device(mmq_x); constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::J*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const half2 * x_dm = (const half2 *) x_qs + 2*WARP_SIZE; + const half2 * x_dm = (const half2 *) x_qs + 2*MMQ_TILE_NE_K; const int * y_qs = (const int *) y + 4; const half2 * y_dm = (const half2 *) y; - tile_A A[ntx][WARP_SIZE/QI8_1]; - float2 dmA[ntx][tile_C::ne/2][WARP_SIZE/QI8_1]; + tile_A A[ntx][MMQ_TILE_NE_K/QI8_1]; + float2 dmA[ntx][tile_C::ne/2][MMQ_TILE_NE_K/QI8_1]; const int i0 = (threadIdx.y/ntx)*rows_per_warp; #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/QI8_1], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q8_1 + k0, MMQ_MMA_TILE_X_K_Q8_1); @@ -799,7 +1050,7 @@ static __device__ __forceinline__ void v const int i = i0 + n*tile_A::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; dmA[n][l][k01/QI8_1] = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + k0/QI8_1]); @@ -810,7 +1061,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { tile_B B; float2 dsB[tile_C::ne/2]; @@ -836,11 +1087,15 @@ static __device__ __forceinline__ void v } } } +#endif // defined(AMD_MFMA_AVAILABLE) } -template +// Used for Q3_K, IQ2_S, and IQ2_XS +template static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16; const int * x_qs = (const int *) x; @@ -849,7 +1104,7 @@ static __device__ __forceinline__ void v const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_0) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_0) { const int k0 = k00 + k01; #pragma unroll @@ -857,23 +1112,73 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q8_0_16_q8_1_impl( - &x_qs[i*(2*WARP_SIZE + 1) + k0], + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q8_0_16_q8_1_impl( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + k0/(QI8_0/2)], + &x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + k0/(QI8_0/2)], y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +// Used for Q3_K, IQ2_S, and IQ2_XS: +template static __device__ __forceinline__ void vec_dot_q8_0_16_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q3_K + k0, MMQ_MMA_TILE_X_K_Q3_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1] / 2; + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l] * x_df[i*MMQ_MMA_TILE_X_K_Q3_K + k0/4] * dB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile<16, 8, int> tile_A_8; @@ -884,10 +1189,10 @@ static __device__ __forceinline__ void v constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + WARP_SIZE*2; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; @@ -899,7 +1204,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { const int k0 = k00 + k01; load_ldmatrix(((tile_A_8 *) A[n])[k01/8], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q3_K + k0, MMQ_MMA_TILE_X_K_Q3_K); @@ -910,7 +1215,7 @@ static __device__ __forceinline__ void v const int i = i0 + n*tile_C::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 4) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { const int k0 = k00 + k01; dA[n][l][k01/4] = x_df[i*MMQ_MMA_TILE_X_K_Q3_K + k0/4]; @@ -921,7 +1226,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { tile_B B[2]; float dB[tile_C::ne/2]; @@ -950,28 +1255,31 @@ static __device__ __forceinline__ void v } } #else - GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); + GGML_UNUSED_VARS(x, y, sum, k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_q2_K( +template static __device__ __forceinline__ void load_tiles_q2_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q2_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI2_K; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR2_K); + constexpr int nrows = ggml_cuda_get_physical_warp_size() / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI2_K) { - int i = i0 + threadIdx.y*(WARP_SIZE/QI2_K) + threadIdx.x/QI2_K; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -987,11 +1295,11 @@ template > (2*l)) & 0x03030303; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q2_K + k] = x_qs_k; #else - x_qs[i*(2*WARP_SIZE + 1) + k] = x_qs_k; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k] = x_qs_k; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const int sc_m = bxi->scales[kqsx]; @@ -1002,17 +1310,19 @@ template > 4)); #endif // FAST_FP16_AVAILABLE -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + kqsx] = x_dm_ik; #else - x_dm[i*(WARP_SIZE + 1) + kqsx] = x_dm_ik; -#endif // NEW_MMA_AVAILABLE + x_dm[i*(MMQ_TILE_NE_K + 1) + kqsx] = x_dm_ik; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q2_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q2_K, mmq_y); const int * x_qs = (const int *) x; @@ -1029,7 +1339,7 @@ static __device__ __forceinline__ void v } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE/2; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K/2; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1037,13 +1347,13 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; constexpr int ns = 2; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q2_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_dm[i*(WARP_SIZE + 1) + k0/4], k01 < WARP_SIZE/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q2_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + &x_dm[i*(MMQ_TILE_NE_K + 1) + k0/4], k01 < MMQ_TILE_NE_K/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, &y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]); } } @@ -1052,7 +1362,7 @@ static __device__ __forceinline__ void v // Some compilers fail to unroll the loop over k01 if there is a conditional statement for ns in the inner loop. // As a workaround 2 separate loops are used instead. #pragma unroll - for (int k01 = WARP_SIZE/2; k01 < WARP_SIZE; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { + for (int k01 = MMQ_TILE_NE_K/2; k01 < MMQ_TILE_NE_K; k01 += QR2_K*VDR_Q2_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1060,23 +1370,89 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; constexpr int ns = 1; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q2_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], - &x_dm[i*(WARP_SIZE + 1) + k0/4], k01 < WARP_SIZE/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q2_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], + &x_dm[i*(MMQ_TILE_NE_K + 1) + k0/4], k01 < MMQ_TILE_NE_K/2 ? y_df[j0/nwarps].x : y_df[j0/nwarps].y, &y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q2_K_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const half2 * x_dm = (const half2 *) x_qs + MMQ_TILE_NE_K*2; + const int * y_qs = (const int *) y + 4; + const half2 * y_ds = (const half2 *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q2_K + k0, MMQ_MMA_TILE_X_K_Q2_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = (k01 < MMQ_TILE_NE_K/2) ? __half22float2(y_ds[j*MMQ_TILE_Y_K]).x/2 : __half22float2(y_ds[j*MMQ_TILE_Y_K]).y/2; + const float sB = (k01 >= MMQ_TILE_NE_K * 3/4) ? 0 + : (((k01/4)%2) ? __half22float2(y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]).y + : __half22float2(y_ds[j*MMQ_TILE_Y_K + (1 + k01/QI8_1)]).x); + + tile_C Cm; + if (k01 >= MMQ_TILE_NE_K * 3/4) { + tile_A A1; + A1.x[0] = 0x01010101; + A1.x[1] = 0x01010101; + mma(Cm, A1, B[0]); + } + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C Cd; + mma(Cd, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + const float2 dm = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + k0/4]); + float tmp = Cd.x[l]*dm.x; + if (k01 >= MMQ_TILE_NE_K * 3/4) { + tmp -= Cm.x[l]*dm.y; + } + sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*dB; + sum[(j0/tile_C::J + n)*tile_C::ne + l] -= dm.y*sB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile<16, 8, int> tile_A_8; @@ -1087,10 +1463,10 @@ static __device__ __forceinline__ void v constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const half2 * x_dm = (const half2 *) x_qs + WARP_SIZE*2; + const half2 * x_dm = (const half2 *) x_qs + MMQ_TILE_NE_K*2; const int * y_qs = (const int *) y + 4; const half2 * y_ds = (const half2 *) y; @@ -1103,7 +1479,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { const int k0 = k00 + k01; load_ldmatrix(((tile_A_8 *) A[n])[k01/QI8_1], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q2_K + k0, MMQ_MMA_TILE_X_K_Q2_K); @@ -1117,7 +1493,7 @@ static __device__ __forceinline__ void v const int i = i0 + n*tile_C::I + tile_C::get_i(2*l); #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1/2) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1/2) { const int k0 = k00 + k01; const float2 dm = __half22float2(x_dm[i*MMQ_MMA_TILE_X_K_Q2_K + k0/(QI8_1/2)]); @@ -1140,7 +1516,7 @@ static __device__ __forceinline__ void v } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QI8_1) { tile_B B[2]; // Here load_generic is faster than load_ldmatrix. @@ -1148,7 +1524,7 @@ static __device__ __forceinline__ void v load_generic(B[1], y_qs + j0*MMQ_TILE_Y_K + (k01 + tile_B::J), MMQ_TILE_Y_K); tile_C Cm[2]; - if (k01 >= WARP_SIZE * 3/4) { + if (k01 >= MMQ_TILE_NE_K * 3/4) { tile_A A1; A1.x[0] = 0x01010101; A1.x[1] = 0x01010101; @@ -1166,16 +1542,16 @@ static __device__ __forceinline__ void v #pragma unroll for (int l = 0; l < tile_C::ne; ++l) { float tmp = Cd[0].x[l]*dA[n][l/2][k01/4 + 0] + Cd[1].x[l]*dA[n][l/2][k01/4 + 1]; - if (k01 >= WARP_SIZE * 3/4) { + if (k01 >= MMQ_TILE_NE_K * 3/4) { tmp -= Cm[0].x[l]*mA[n][l/2][k01/4 + 0] + Cm[1].x[l]*mA[n][l/2][k01/4 + 1]; } - sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*(k01 < WARP_SIZE/2 ? dB[l%2].x : dB[l%2].y); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += tmp*(k01 < MMQ_TILE_NE_K/2 ? dB[l%2].x : dB[l%2].y); } } } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE * 3/4; k01 += QI8_1) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K * 3/4; k01 += QI8_1) { float2 sB[tile_C::ne/2]; #pragma unroll @@ -1196,29 +1572,33 @@ static __device__ __forceinline__ void v } } #else - GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); + GGML_UNUSED_VARS(x, y, sum, k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_q3_K( +template static __device__ __forceinline__ void load_tiles_q3_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q3_K, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); int * x_sc = (int *) (x_df + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI3_K; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR3_K); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI3_K) { - int i = i0 + threadIdx.y * (WARP_SIZE/QI3_K) + threadIdx.x / QI3_K; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1238,17 +1618,18 @@ template d; #pragma unroll for (int l = 0; l < int(sizeof(int)); ++l) { - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + sizeof(int)*(threadIdx.x % (WARP_SIZE/8)) + l] = d*sc8[l]; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + sizeof(int)*ksc + l] = d*sc8[l]; } #else - x_sc[i*(WARP_SIZE/8) + i/8 + threadIdx.x % (WARP_SIZE/8)] = sc; -#endif // NEW_MMA_AVAILABLE + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = sc; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -#ifndef NEW_MMA_AVAILABLE +#if !(defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE)) #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*WARP_SIZE) { - int i = (i0 + threadIdx.y*WARP_SIZE + threadIdx.x) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1294,12 +1675,14 @@ template d; } -#endif // NEW_MMA_AVAILABLE +#endif // !(defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE)) } -template +template static __device__ __forceinline__ void vec_dot_q3_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q3_K, mmq_y); const int * x_qs = (const int *) x; @@ -1309,7 +1692,7 @@ static __device__ __forceinline__ void v const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR3_K*VDR_Q3_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1317,13 +1700,13 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const int8_t * scales = ((const int8_t *) (x_sc + i*(WARP_SIZE/8) + i/8)) + k0/4; + const int8_t * scales = ((const int8_t *) (x_sc + i*(MMQ_TILE_NE_K/8) + i/8)) + k0/4; - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q3_K_q8_1_impl_mmq( - &x_qs[i*(2*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], scales, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q3_K_q8_1_impl_mmq( + &x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], scales, x_df[i], y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } @@ -1340,72 +1723,85 @@ static __device__ __forceinline__ int un ((scales[ksc/2] >> (2 * (ksc % 2))) & 0x30303030); // upper 2 bits } -template static __device__ __forceinline__ void load_tiles_q4_K( +template static __device__ __forceinline__ void load_tiles_q4_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + 2*WARP_SIZE); + half2 * x_dm = (half2 *) (x_qs + 2*MMQ_TILE_NE_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); int * x_sc = (int *) (x_dm + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; - const int qs0 = get_int_b4(bxi->qs, threadIdx.x); + const int qs0 = get_int_b4(bxi->qs, txi); -#ifdef NEW_MMA_AVAILABLE - x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(threadIdx.x/8) + threadIdx.x % 8 + 0] = (qs0 >> 0) & 0x0F0F0F0F; - x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(threadIdx.x/8) + threadIdx.x % 8 + 8] = (qs0 >> 4) & 0x0F0F0F0F; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(txi/8) + txi % 8 + 0] = (qs0 >> 0) & 0x0F0F0F0F; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 16*(txi/8) + txi % 8 + 8] = (qs0 >> 4) & 0x0F0F0F0F; #else - x_qs[i*(WARP_SIZE + 1) + threadIdx.x] = qs0; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(MMQ_TILE_NE_K + 1) + txi] = qs0; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -#ifdef NEW_MMA_AVAILABLE - +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr int rows_per_warp = warp_size / 2; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*16) { - int i = (i0 + threadIdx.y*16 + threadIdx.x/(WARP_SIZE/16)) % mmq_y; - - if (need_check) { - i = min(i, i_max); - } + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { +#if defined(AMD_MFMA_AVAILABLE) + // Need if on AMD instead of % because warp_size == 64 + // This causes double work and throughput loss (MI300X) + // H100 loses about 100 t/s with 'if' condition over '%' + int i = i0 + threadIdx.y*rows_per_warp + threadIdx.x/2; + if (i < mmq_y) { +#else + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/2) % mmq_y; + { +#endif // defined(AMD_MFMA_AVAILABLE) + if (need_check) { + i = min(i, i_max); + } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; + const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride; - const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/16); + const int * scales = (const int *) bxi->scales; + const int ksc = threadIdx.x % 2; - const int sc32 = unpack_scales_q45_K(scales, ksc + 0); - const int m32 = unpack_scales_q45_K(scales, ksc + 2); + const int sc32 = unpack_scales_q45_K(scales, ksc + 0); + const int m32 = unpack_scales_q45_K(scales, ksc + 2); - const uint8_t * sc8 = (const uint8_t *) &sc32; - const uint8_t * m8 = (const uint8_t *) &m32; + const uint8_t * sc8 = (const uint8_t *) &sc32; + const uint8_t * m8 = (const uint8_t *) &m32; - const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); + const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); -#pragma unroll - for (int l = 0; l < int(sizeof(int)); ++l) { - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + #pragma unroll + for (int l = 0; l < sizeof(int); ++l) { + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + } } } - #else - #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*QI4_K) { - int i = (i0 + threadIdx.y*QI4_K + threadIdx.x) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1415,30 +1811,32 @@ template dm; } - + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 8) { - int i = (i0 + threadIdx.y * 8 + threadIdx.x / (WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride + (threadIdx.x % (WARP_SIZE/8)) / (QI4_K/8); + const block_q4_K * bxi = (const block_q4_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / (QI4_K/8); const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/8); + const int ksc = threadIdx.x % (MMQ_TILE_NE_K/8); const int scales8 = unpack_scales_q45_K(scales, ksc); - x_sc[i*(WARP_SIZE/8) + i/8 + ksc] = scales8; + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = scales8; } -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q4_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q4_K, mmq_y); const int * x_qs = (const int *) x; @@ -1448,7 +1846,7 @@ static __device__ __forceinline__ void v const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR4_K*VDR_Q4_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR4_K*VDR_Q4_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1456,97 +1854,110 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const uint8_t * sc = (const uint8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k0/32] + 2*(k01/16); + const uint8_t * sc = (const uint8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k0/32] + 2*(k01/16); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q4_K_q8_1_impl_mmq( - &x_qs[i*(WARP_SIZE + 1) + k0/2], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q4_K_q8_1_impl_mmq( + &x_qs[i*(MMQ_TILE_NE_K + 1) + k0/2], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, x_dm[i], &y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q5_K( +template static __device__ __forceinline__ void load_tiles_q5_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_dm = (half2 *) (x_qs + WARP_SIZE*2); + half2 * x_dm = (half2 *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_K, mmq_y); int * x_qs = (int *) x_tile; half2 * x_dm = (half2 *) (x_qs + txs.qs); int * x_sc = (int *) (x_dm + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR5_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; - const int ky = QR5_K*threadIdx.x; + const int ky = QR5_K*txi; - const int ql = get_int_b4(bxi->qs, threadIdx.x); + const int ql = get_int_b4(bxi->qs, txi); const int ql0 = (ql >> 0) & 0x0F0F0F0F; const int ql1 = (ql >> 4) & 0x0F0F0F0F; - const int qh = get_int_b4(bxi->qh, threadIdx.x % (QI5_K/4)); - const int qh0 = ((qh >> (2 * (threadIdx.x / (QI5_K/4)) + 0)) << 4) & 0x10101010; - const int qh1 = ((qh >> (2 * (threadIdx.x / (QI5_K/4)) + 1)) << 4) & 0x10101010; + const int qh = get_int_b4(bxi->qh, txi % (QI5_K/4)); + const int qh0 = ((qh >> (2 * (txi / (QI5_K/4)) + 0)) << 4) & 0x10101010; + const int qh1 = ((qh >> (2 * (txi / (QI5_K/4)) + 1)) << 4) & 0x10101010; - const int kq0 = ky - ky % (QI5_K/2) + threadIdx.x % (QI5_K/4) + 0; - const int kq1 = ky - ky % (QI5_K/2) + threadIdx.x % (QI5_K/4) + QI5_K/4; + const int kq0 = ky - ky % (QI5_K/2) + txi % (QI5_K/4) + 0; + const int kq1 = ky - ky % (QI5_K/2) + txi % (QI5_K/4) + QI5_K/4; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kq0] = ql0 | qh0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + kq1] = ql1 | qh1; #else - x_qs[i*(2*WARP_SIZE + 1) + kq0] = ql0 | qh0; - x_qs[i*(2*WARP_SIZE + 1) + kq1] = ql1 | qh1; -#endif // NEW_MMA_AVAILABLE - } - -#ifdef NEW_MMA_AVAILABLE - -#pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*16) { - int i = (i0 + threadIdx.y*16 + threadIdx.x/(WARP_SIZE/16)) % mmq_y; - - if (need_check) { - i = min(i, i_max); - } + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq0] = ql0 | qh0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq1] = ql1 | qh1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + } + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr int rows_per_warp = warp_size / 2; +#pragma unroll + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { +#if defined(AMD_MFMA_AVAILABLE) + // Need if on AMD instead of % because warp_size == 64 + // This causes double work and throughput loss (MI300X) + // H100 loses about 100 t/s with 'if' condition over '%' + int i = i0 + threadIdx.y*rows_per_warp + threadIdx.x/2; + if (i < mmq_y) { +#else + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/2) % mmq_y; + { +#endif // defined(AMD_MFMA_AVAILABLE) + if (need_check) { + i = min(i, i_max); + } - const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; + const block_q5_K * bxi = (const block_q5_K *) x + kbx0 + i*stride; - const int * scales = (const int *) bxi->scales; - const int ksc = threadIdx.x % (WARP_SIZE/16); + const int * scales = (const int *) bxi->scales; + const int ksc = threadIdx.x % 2; - const int sc32 = unpack_scales_q45_K(scales, ksc + 0); - const int m32 = unpack_scales_q45_K(scales, ksc + 2); + const int sc32 = unpack_scales_q45_K(scales, ksc + 0); + const int m32 = unpack_scales_q45_K(scales, ksc + 2); - const uint8_t * sc8 = (const uint8_t *) &sc32; - const uint8_t * m8 = (const uint8_t *) &m32; + const uint8_t * sc8 = (const uint8_t *) &sc32; + const uint8_t * m8 = (const uint8_t *) &m32; - const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); + const half2 dm = bxi->dm * make_half2(1.0f, -1.0f); #pragma unroll - for (int l = 0; l < int(sizeof(int)); ++l) { - x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + for (int l = 0; l < int(sizeof(int)); ++l) { + x_dm[i*MMQ_MMA_TILE_X_K_Q8_1 + sizeof(int)*ksc + l] = dm*make_half2(sc8[l], m8[l]); + } } } - #else - #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*QI5_K) { - int i = (i0 + threadIdx.y*QI5_K + threadIdx.x) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1557,9 +1968,10 @@ template dm; } + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps*8) { - int i = (i0 + threadIdx.y*8 + threadIdx.x/(WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); @@ -1569,17 +1981,19 @@ template scales; - const int ksc = threadIdx.x % (WARP_SIZE/8); + const int ksc = threadIdx.x % (MMQ_TILE_NE_K/8); const int scales8 = unpack_scales_q45_K(scales, ksc); - x_sc[i*(WARP_SIZE/8) + i/8 + ksc] = scales8; + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + ksc] = scales8; } -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } -template +template static __device__ __forceinline__ void vec_dot_q5_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q5_K, mmq_y); const int * x_qs = (const int *) x; @@ -1589,7 +2003,7 @@ static __device__ __forceinline__ void v const half2 * y_ds = (const half2 *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR5_K*VDR_Q5_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR5_K*VDR_Q5_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1597,36 +2011,42 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const uint8_t * sc = ((const uint8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k00/32]) + 2*(k01/16); + const uint8_t * sc = ((const uint8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k00/32]) + 2*(k01/16); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q5_K_q8_1_impl_mmq( - &x_qs[i*(QR5_K*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q5_K_q8_1_impl_mmq( + &x_qs[i*(QR5_K*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, sc+8, x_dm[i], &y_ds[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template static __device__ __forceinline__ void load_tiles_q6_K( +template static __device__ __forceinline__ void load_tiles_q6_K( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); - int * x_sc = (int *) (x_df + WARP_SIZE/QI6_K); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); + int * x_sc = (int *) (x_df + MMQ_TILE_NE_K/QI6_K); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q6_K, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); int * x_sc = (int *) (x_df + txs.dm); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR6_K); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -1634,67 +2054,67 @@ template ql, threadIdx.x); + const int ql = get_int_b2(bxi->ql, txi); const int ql0 = (ql >> 0) & 0x0F0F0F0F; const int ql1 = (ql >> 4) & 0x0F0F0F0F; - const int qh = get_int_b2(bxi->qh, (QI6_K/4) * (threadIdx.x / (QI6_K/2)) + threadIdx.x % (QI6_K/4)); - const int qh0 = ((qh >> ((threadIdx.x & 0x08) >> 2)) << 4) & 0x30303030; - const int qh1 = (qh >> ((threadIdx.x & 0x08) >> 2)) & 0x30303030; + const int qh = get_int_b2(bxi->qh, (QI6_K/4) * (txi / (QI6_K/2)) + txi % (QI6_K/4)); + const int qh0 = ((qh >> ((txi & 0x08) >> 2)) << 4) & 0x30303030; + const int qh1 = (qh >> ((txi & 0x08) >> 2)) & 0x30303030; - const int kq0 = 2*threadIdx.x - threadIdx.x % (QI6_K/2) + 0; - const int kq1 = 2*threadIdx.x - threadIdx.x % (QI6_K/2) + QI6_K/2; + const int kq0 = 2*txi - txi % (QI6_K/2) + 0; + const int kq1 = 2*txi - txi % (QI6_K/2) + QI6_K/2; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q6_K + kq0] = __vsubss4(ql0 | qh0, 0x20202020); x_qs[i*MMQ_MMA_TILE_X_K_Q6_K + kq1] = __vsubss4(ql1 | qh1, 0x20202020); #else - x_qs[i*(2*WARP_SIZE + 1) + kq0] = __vsubss4(ql0 | qh0, 0x20202020); - x_qs[i*(2*WARP_SIZE + 1) + kq1] = __vsubss4(ql1 | qh1, 0x20202020); -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq0] = __vsubss4(ql0 | qh0, 0x20202020); + x_qs[i*(2*MMQ_TILE_NE_K + 1) + kq1] = __vsubss4(ql1 | qh1, 0x20202020); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI6_K; // == 1 if QK_K == 256 - const int kbxd = threadIdx.x % blocks_per_tile_x_row; // == 0 if QK_K == 256 - #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI6_K) { - int i = (i0 + threadIdx.y * QI6_K + threadIdx.x / blocks_per_tile_x_row) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*warp_size) { + int i = (i0 + threadIdx.y*warp_size + threadIdx.x) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + kbxd; + const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q6_K + kbxd] = bxi->d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q6_K] = bxi->d; #else - x_df[i*(WARP_SIZE/QI6_K) + i/QI6_K + kbxd] = bxi->d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI6_K) + i/QI6_K] = bxi->d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } + constexpr int rows_per_warp = warp_size / 4; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 8) { - int i = (i0 + threadIdx.y * 8 + threadIdx.x / (WARP_SIZE/8)) % mmq_y; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps*rows_per_warp) { + int i = (i0 + threadIdx.y*rows_per_warp + threadIdx.x/(MMQ_TILE_NE_K/8)) % mmq_y; if (need_check) { i = min(i, i_max); } - const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + (threadIdx.x % (WARP_SIZE/8)) / 4; + const block_q6_K * bxi = (const block_q6_K *) x + kbx0 + i*stride + (threadIdx.x % (MMQ_TILE_NE_K/8)) / 4; -#ifdef NEW_MMA_AVAILABLE - x_sc[i*MMQ_MMA_TILE_X_K_Q6_K + threadIdx.x % (WARP_SIZE/8)] = get_int_b2(bxi->scales, threadIdx.x % (QI6_K/8)); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_sc[i*MMQ_MMA_TILE_X_K_Q6_K + threadIdx.x%4] = get_int_b2(bxi->scales, threadIdx.x % (MMQ_TILE_NE_K/8)); #else - x_sc[i*(WARP_SIZE/8) + i/8 + threadIdx.x % (WARP_SIZE/8)] = get_int_b2(bxi->scales, threadIdx.x % (QI6_K/8)); -#endif // NEW_MMA_AVAILABLE + x_sc[i*(MMQ_TILE_NE_K/8) + i/8 + threadIdx.x%(MMQ_TILE_NE_K/8)] = get_int_b2(bxi->scales, threadIdx.x%(QI6_K/8)); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void vec_dot_q6_K_q8_1_dp4a( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_Q6_K, mmq_y); const int * x_qs = (const int *) x; @@ -1704,7 +2124,7 @@ static __device__ __forceinline__ void v const float * y_df = (const float *) y; // #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += QR6_K*VDR_Q6_K_Q8_1_MMQ) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += QR6_K*VDR_Q6_K_Q8_1_MMQ) { const int k0 = k00 + k01; #pragma unroll @@ -1712,23 +2132,74 @@ static __device__ __forceinline__ void v const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - const int8_t * sc = ((const int8_t *) &x_sc[i * (WARP_SIZE/8) + i/8 + k0/16]); + const int8_t * sc = ((const int8_t *) &x_sc[i * (MMQ_TILE_NE_K/8) + i/8 + k0/16]); - sum[j0/nwarps*mmq_y/WARP_SIZE + i0/WARP_SIZE] += vec_dot_q6_K_q8_1_impl_mmq( - &x_qs[i*(QR6_K*WARP_SIZE + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, - x_df[i*(WARP_SIZE/QI6_K) + i/QI6_K], &y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); + sum[j0/nwarps*mmq_y/warp_size + i0/warp_size] += vec_dot_q6_K_q8_1_impl_mmq( + &x_qs[i*(QR6_K*MMQ_TILE_NE_K + 1) + k0], &y_qs[j*MMQ_TILE_Y_K + k01], sc, + x_df[i*(MMQ_TILE_NE_K/QI6_K) + i/QI6_K], &y_df[j*MMQ_TILE_Y_K + k01/QI8_1]); } } } } -template +template static __device__ __forceinline__ void vec_dot_q6_K_q8_1_mma( const int * __restrict__ x, const int * __restrict__ y, float * __restrict__ sum, const int k00) { -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) + typedef tile<16, 8, int> tile_A; + typedef tile<16, 8, int> tile_B; + typedef tile<16, 16, int> tile_C; + typedef tile<64, 2, int> tile_load; + + constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int rows_per_warp = granularity; + constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. + + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); + + const int * x_qs = (const int *) x; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * x_sc = (const int *) x_df + MMQ_TILE_NE_K/QI6_K; + const int * y_qs = (const int *) y + 4; + const float * y_df = (const float *) y; + + const int i0 = (threadIdx.y / ntx) * rows_per_warp; + + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 4) { + const int k0 = k00 + k01; + + tile_A A[ntx]; +#pragma unroll + for (int n = 0; n < ntx; ++n) { + load_generic(((tile_load *) A)[n], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q6_K + k0, MMQ_MMA_TILE_X_K_Q6_K); + } + +#pragma unroll + for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { + tile_B B[1]; + load_generic(((tile_load *) B)[0], y_qs + j0*MMQ_TILE_Y_K + k01, MMQ_TILE_Y_K); + + const int j = j0 + tile_C::get_j(0); + const float dB = y_df[j*MMQ_TILE_Y_K + k01/QI8_1] / 2; + +#pragma unroll + for (int n = 0; n < ntx; ++n) { + tile_C C; + mma(C, A[n], B[0]); + +#pragma unroll + for (int l = 0; l < tile_C::ne; ++l) { + const int i = i0 + n*tile_C::I + tile_C::get_i(l); + const int8_t * sc = (const int8_t *) (x_sc + i*MMQ_MMA_TILE_X_K_Q6_K + k00/16); + sum[(j0/tile_C::J + n)*tile_C::ne + l] += C.x[l] * sc[k01/4] * x_df[i*MMQ_MMA_TILE_X_K_Q6_K] * dB; + } + } + } + } +#elif defined(TURING_MMA_AVAILABLE) typedef tile<16, 4, int> tile_A; typedef tile< 8, 4, int> tile_B; @@ -1738,11 +2209,11 @@ static __device__ __forceinline__ void v constexpr int rows_per_warp = 2 * granularity; constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. - y += (threadIdx.y % ntx) * (tile_B::I*MMQ_TILE_Y_K); + y += (threadIdx.y % ntx) * (tile_C::J*MMQ_TILE_Y_K); const int * x_qs = (const int *) x; - const float * x_df = (const float *) x_qs + WARP_SIZE*2; - const int * x_sc = (const int *) x_df + WARP_SIZE/QI6_K; + const float * x_df = (const float *) x_qs + MMQ_TILE_NE_K*2; + const int * x_sc = (const int *) x_df + MMQ_TILE_NE_K/QI6_K; const int * y_qs = (const int *) y + 4; const float * y_df = (const float *) y; @@ -1755,7 +2226,7 @@ static __device__ __forceinline__ void v #pragma unroll for (int n = 0; n < ntx; ++n) { #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { const int k0 = k00 + k01; load_ldmatrix(A[n][k01/4 + 0], x_qs + (i0 + n*tile_A::I)*MMQ_MMA_TILE_X_K_Q6_K + (k0 + 0), MMQ_MMA_TILE_X_K_Q6_K); @@ -1763,7 +2234,7 @@ static __device__ __forceinline__ void v } #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 16) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 16) { const int k0 = k00 + k01; #pragma unroll @@ -1793,7 +2264,7 @@ static __device__ __forceinline__ void v float tmp[ntx][tile_C::ne] = {{0.0f}}; #pragma unroll - for (int k01 = 0; k01 < WARP_SIZE; k01 += 8) { + for (int k01 = 0; k01 < MMQ_TILE_NE_K; k01 += 8) { tile_B B[2]; float dB[tile_C::ne/2]; @@ -1830,29 +2301,34 @@ static __device__ __forceinline__ void v } } #else - GGML_UNUSED(x); GGML_UNUSED(y); GGML_UNUSED(sum); GGML_UNUSED(k00); + GGML_UNUSED_VARS(x, y, sum, k00); NO_DEVICE_CODE; -#endif // NEW_MMA_AVAILABLE +#endif // AMD_MFMA_AVAILABLE } -template static __device__ __forceinline__ void load_tiles_iq4_nl( +template static __device__ __forceinline__ void load_tiles_iq4_nl( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_NL, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = threadIdx.x / QI4_NL; - const int kqsx = threadIdx.x % QI4_NL; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_NL); + constexpr int nrows = warp_size / threads_per_row; + const int txi = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; + const int kbx = txi / QI4_NL; + const int kqsx = txi % QI4_NL; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); @@ -1861,23 +2337,25 @@ template qs, kqsx); - const int2 v = get_int_from_table_16(aux_q4); - const int k0 = 8 * (threadIdx.x / 4) + threadIdx.x % 4; -#ifdef NEW_MMA_AVAILABLE - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; - x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 4] = v.y; + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); + const int k0 = kbx * (2 * QI4_NL) + kqsx; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; + x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + QI4_NL] = v.y; #else - x_qs[i*(2*WARP_SIZE + 1) + k0 + 0] = v.x; - x_qs[i*(2*WARP_SIZE + 1) + k0 + 4] = v.y; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + QI4_NL] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } - const int blocks_per_tile_x_row = WARP_SIZE / QI4_NL; + constexpr int blocks_per_tile_x_row = MMQ_TILE_NE_K / QI4_NL; + constexpr int rows_per_warp = warp_size / blocks_per_tile_x_row; const int kbxd = threadIdx.x % blocks_per_tile_x_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * QI4_NL) { - int i = i0 + threadIdx.y * QI4_NL + threadIdx.x / blocks_per_tile_x_row; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / blocks_per_tile_x_row; if (need_check) { i = min(i, i_max); @@ -1885,31 +2363,35 @@ template d); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kbxd] = __half2float(bxi->d); #else - x_df[i*(WARP_SIZE/4) + i/4 + kbxd] = __half2float(bxi->d); -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/QI4_NL) + i/QI4_NL + kbxd] = __half2float(bxi->d); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_xxs( +template static __device__ __forceinline__ void load_tiles_iq2_xxs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ2_XXS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_XXS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_XXS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = warp_size > threads_per_row ? threadIdx.x % threads_per_row : threadIdx.x; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_XXS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_XXS) + threadIdx.x/(QI2_XXS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1932,42 +2414,46 @@ template > 28; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/4; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = (ls*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = (ls*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_xs( +template static __device__ __forceinline__ void load_tiles_iq2_xs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = MMQ_DP4A_TXS_Q8_0_16; int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_XS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_XS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_XS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_XS) + threadIdx.x/(QI2_XS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -1986,44 +2472,48 @@ template scales[kqsx]; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; #else - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq2_s( +template static __device__ __forceinline__ void load_tiles_iq2_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ2_S, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI2_S/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR2_S)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI2_S/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI2_S) + threadIdx.x/(QI2_S/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2049,44 +2539,48 @@ template scales[kqsx]; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*MMQ_MMA_TILE_X_K_Q3_K + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; #else - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; - x_df[i*(2*WARP_SIZE*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; -#endif // NEW_MMA_AVAILABLE + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+0] = ((ls & 0x0F)*d + d/2)/4; + x_df[i*(2*MMQ_TILE_NE_K*2/QI8_0) + i/(QI8_0/4) + 2*kqsx+1] = ((ls >> 4)*d + d/2)/4; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq3_xxs( +template static __device__ __forceinline__ void load_tiles_iq3_xxs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_XXS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI3_XXS/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR3_XXS)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI3_XXS/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI3_XXS) + threadIdx.x/(QI3_XXS/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2107,42 +2601,46 @@ template > 28; const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/2; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = (ls*d + d/2)/2; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = (ls*d + d/2)/2; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = (ls*d + d/2)/2; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq3_s( +template static __device__ __forceinline__ void load_tiles_iq3_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_S, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % (QI3_S/2); + constexpr int threads_per_row = (MMQ_ITER_K / (4 * QR3_S)) / 2; + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/(QI3_S/2)) { - int i = i0 + threadIdx.y*(2*WARP_SIZE/QI3_S) + threadIdx.x/(QI3_S/2); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2170,42 +2668,46 @@ template scales[kqsx/2] >> (((2*kqsx) << 1) & 0x04)) & 0x0F); const float d = bxi->d; -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = ls*d; +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + kqsx] = ls*d; #else - x_df[i*(WARP_SIZE/4) + i/4 + kqsx] = ls*d; -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = ls*d; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq1_s( +template static __device__ __forceinline__ void load_tiles_iq1_s( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - half2 * x_ds = (half2 *) (x_qs + WARP_SIZE*2); + half2 * x_ds = (half2 *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ3_S, mmq_y); int * x_qs = (int *) x_tile; half2 * x_ds = (half2 *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kqsx = threadIdx.x % QI1_S; + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR1_S); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * WARP_SIZE/QI1_S) { - int i = i0 + threadIdx.y*(WARP_SIZE/QI1_S) + threadIdx.x/QI1_S; + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * nrows) { + int i = i0 + threadIdx.y*nrows + threadIdx.x/threads_per_row; if (need_check) { i = min(i, i_max); @@ -2225,66 +2727,71 @@ template > 0) & 0x0F0F0F0F; const int grid1 = (grid >> 4) & 0x0F0F0F0F; -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 8*kqsx + (2*l+0)] = grid0; x_qs[i*MMQ_MMA_TILE_X_K_Q8_1 + 8*kqsx + (2*l+1)] = grid1; #else - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+0)] = grid0; - x_qs[i*(2*WARP_SIZE + 1) + 8*kqsx + (2*l+1)] = grid1; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+0)] = grid0; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + 8*kqsx + (2*l+1)] = grid1; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } const float d1q = __half2float(bxi->d) * (((qh >> 11) & 0x0E) + 1); const float delta = -1.0f + IQ1S_DELTA - (qh & 0x8000) * (2.0f*IQ1S_DELTA/0x8000); -#ifdef NEW_MMA_AVAILABLE - x_ds[i*MMQ_MMA_TILE_X_K_Q8_1 + kqsx] = make_half2(d1q, d1q*delta); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_ds[i*MMQ_MMA_TILE_X_K_Q8_1 + kqsx] = make_half2(d1q, d1q*delta); #else - x_ds[i*(WARP_SIZE/4) + i/4 + kqsx] = make_half2(d1q, d1q*delta); -#endif // NEW_MMA_AVAILABLE + x_ds[i*(MMQ_TILE_NE_K/4) + i/4 + kqsx] = make_half2(d1q, d1q*delta); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template static __device__ __forceinline__ void load_tiles_iq4_xs( +template static __device__ __forceinline__ void load_tiles_iq4_xs( const char * __restrict__ x, int * __restrict__ x_tile, const int kbx0, const int i_max, const int stride) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); -#ifdef NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) int * x_qs = (int *) x_tile; - float * x_df = (float *) (x_qs + WARP_SIZE*2); + float * x_df = (float *) (x_qs + MMQ_TILE_NE_K*2); #else constexpr tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(GGML_TYPE_IQ4_XS, mmq_y); int * x_qs = (int *) x_tile; float * x_df = (float *) (x_qs + txs.qs); -#endif // NEW_MMA_AVAILABLE +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) - const int kbx = 0; // threadIdx.x / QI4_XS - const int kqsx = threadIdx.x; // threadIdx.x % QI4_XS + constexpr int threads_per_row = MMQ_ITER_K / (4 * QR4_XS); + constexpr int nrows = warp_size / threads_per_row; + const int kqsx = threadIdx.x % threads_per_row; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps) { - int i = i0 + threadIdx.y; + for (int i0 = 0; i0 < mmq_y; i0 += nrows*nwarps) { + int i = i0 + (nrows == 1 ? threadIdx.y : threadIdx.y*nrows + threadIdx.x/threads_per_row); if (need_check) { i = min(i, i_max); } - const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride + kbx; + const block_iq4_xs * bxi = (const block_iq4_xs *) x + kbx0 + i*stride; const int aux_q4 = get_int_b4(bxi->qs, kqsx); - const int2 v = get_int_from_table_16(aux_q4); - const int k0 = 8 * (threadIdx.x / 4) + threadIdx.x % 4; -#ifdef NEW_MMA_AVAILABLE + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); + const int k0 = 8 * (kqsx / 4) + kqsx % 4; + +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 0] = v.x; x_qs[i*MMQ_MMA_TILE_X_K_Q8_0 + k0 + 4] = v.y; #else - x_qs[i*(2*WARP_SIZE + 1) + k0 + 0] = v.x; - x_qs[i*(2*WARP_SIZE + 1) + k0 + 4] = v.y; -#endif // NEW_MMA_AVAILABLE + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 0] = v.x; + x_qs[i*(2*MMQ_TILE_NE_K + 1) + k0 + 4] = v.y; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } + constexpr int rows_per_warp = warp_size / 8; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += nwarps * 4) { - int i = i0 + threadIdx.y * 4 + threadIdx.x / (WARP_SIZE/4); + for (int i0 = 0; i0 < mmq_y; i0 += nwarps * rows_per_warp) { + int i = i0 + threadIdx.y * rows_per_warp + threadIdx.x / (MMQ_TILE_NE_K/4); if (need_check) { i = min(i, i_max); @@ -2297,18 +2804,21 @@ template scales_l[(threadIdx.x % 8)/2] >> (4*(threadIdx.x % 2))) & 0x0F) | (((bxi->scales_h >> (2*(threadIdx.x % 8))) & 0x03) << 4); -#ifdef NEW_MMA_AVAILABLE - x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = d * (ls - 32); +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + x_df[i*MMQ_MMA_TILE_X_K_Q8_0 + threadIdx.x % 8] = d * (ls - 32); #else - x_df[i*(WARP_SIZE/4) + i/4 + threadIdx.x % 8] = d * (ls - 32); -#endif // NEW_MMA_AVAILABLE + x_df[i*(MMQ_TILE_NE_K/4) + i/4 + threadIdx.x % 8] = d * (ls - 32); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) } } -template +template static __device__ __forceinline__ void mmq_write_back_dp4a( const float * __restrict__ sum, const int32_t * __restrict__ ids_dst, float * __restrict__ dst, const int stride, const int i_max, const int j_max) { + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += nwarps) { const int j = j0 + threadIdx.y; @@ -2318,32 +2828,42 @@ static __device__ __forceinline__ void m } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[ids_dst[j]*stride + i] = sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[ids_dst[j]*stride + i] = sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } } -template +template static __device__ __forceinline__ void mmq_write_back_mma( const float * __restrict__ sum, const int * __restrict__ ids_dst, float * __restrict__ dst, const int stride, const int i_max, const int j_max) { - typedef tile<16, 8, int> tile_C; constexpr int granularity = mmq_get_granularity_device(mmq_x); + constexpr int nwarps = mmq_get_nwarps_device(); + +#if defined(AMD_MFMA_AVAILABLE) + constexpr int tileC_IJ = mmq_get_granularity_device(0); + typedef tile tile_C; + constexpr int rows_per_warp = granularity; +#else + typedef tile<16, 8, int> tile_C; constexpr int rows_per_warp = 2 * granularity; +#endif // defined(AMD_MFMA_AVAILABLE) constexpr int ntx = rows_per_warp/tile_C::I; // Number of x minitiles per warp. const int i0 = (threadIdx.y / ntx) * (ntx*tile_C::I); -#ifdef NEW_MMA_AVAILABLE +#if defined(TURING_MMA_AVAILABLE) || defined(AMD_MFMA_AVAILABLE) static_assert(nwarps*tile_C::I == mmq_y, "nwarps*tile_C::I != mmq_y"); -#endif // NEW_MMA_AVAILABLE +#else + GGML_UNUSED(nwarps); +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) #pragma unroll for (int j0 = 0; j0 < mmq_x; j0 += ntx*tile_C::J) { @@ -2371,179 +2891,189 @@ static __device__ __forceinline__ void m // ------------------------------------------------------------------------------------------------------------------------------------- -template +template struct mmq_type_traits; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_1_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_1; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_1; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_1_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_1; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_1; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q8_0_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q8_0; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q8_0; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; +}; + +template +struct mmq_type_traits { + static constexpr int vdr = VDR_MXFP4_Q8_1_MMQ; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_mxfp4; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q2_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q2_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q2_K_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q2_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q2_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q2_K_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q2_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q3_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q3_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q3_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q3_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q3_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q4_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q4_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q4_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q5_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q5_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q5_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q5_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_Q6_K_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_q6_K; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q6_K_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q6_K_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_q6_K; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q6_K_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q6_K_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_XXS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xxs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xxs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_XS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_xs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ2_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq2_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_16_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_16_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ3_XXS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_xxs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_xxs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ3_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq3_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ1_S_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq1_s; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq1_s; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_1_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_1_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ4_NL_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_nl; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_nl; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template -struct mmq_type_traits { +template +struct mmq_type_traits { static constexpr int vdr = VDR_IQ4_XS_Q8_1_MMQ; - static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_xs; - static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; - static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; + static constexpr load_tiles_mmq_t load_tiles = load_tiles_iq4_xs; + static constexpr vec_dot_mmq_t vec_dot_mma = vec_dot_q8_0_q8_1_mma; + static constexpr vec_dot_mmq_t vec_dot_dp4a = vec_dot_q8_0_q8_1_dp4a; }; -template +template static __device__ __forceinline__ void mul_mat_q_process_tile( const char * __restrict__ x, const int offset_x, const int * __restrict__ y, const int * __restrict__ ids_dst, float * __restrict__ dst, float * __restrict__ tmp_fixup, const int stride_row_x, const int ncols_y, const int stride_col_dst, const int tile_x_max_i, const int tile_y_max_j, const int kb0_start, const int kb0_stop) { + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int nwarps = mmq_get_nwarps_device(); constexpr int qk = ggml_cuda_type_traits::qk; constexpr int mmq_y = get_mmq_y_device(); - constexpr load_tiles_mmq_t load_tiles = mmq_type_traits::load_tiles; + constexpr load_tiles_mmq_t load_tiles = mmq_type_traits::load_tiles; extern __shared__ int data_mul_mat_q[]; int * tile_y = data_mul_mat_q + mmq_x; - int * tile_x = tile_y + GGML_PAD(mmq_x*(WARP_SIZE + WARP_SIZE/QI8_1), nwarps*WARP_SIZE); + int * tile_x = tile_y + GGML_PAD(mmq_x*MMQ_TILE_Y_K, nwarps*warp_size); -#ifdef NEW_MMA_AVAILABLE - constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_mma; - constexpr mmq_write_back_t write_back = mmq_write_back_mma; -#else - constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_dp4a; - constexpr mmq_write_back_t write_back = mmq_write_back_dp4a; -#endif // NEW_MMA_AVAILABLE +#if defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) + constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_mma; + constexpr mmq_write_back_t write_back = mmq_write_back_mma; +#else + constexpr vec_dot_mmq_t vec_dot = mmq_type_traits::vec_dot_dp4a; + constexpr mmq_write_back_t write_back = mmq_write_back_dp4a; +#endif // defined(AMD_MFMA_AVAILABLE) || defined(TURING_MMA_AVAILABLE) constexpr int blocks_per_iter = MMQ_ITER_K / qk; - float sum[mmq_x*mmq_y / (nwarps*WARP_SIZE)] = {0.0f}; + float sum[mmq_x*mmq_y / (nwarps*warp_size)] = {0.0f}; for (int kb0 = kb0_start; kb0 < kb0_stop; kb0 += blocks_per_iter) { load_tiles(x, tile_x, offset_x + kb0, tile_x_max_i, stride_row_x); @@ -2551,8 +3081,8 @@ static __device__ __forceinline__ void m { const int * by0 = y + ncols_y*(kb0*(qk*sizeof(block_q8_1_mmq) / (4*QK8_1*sizeof(int))) + 0*sizeof(block_q8_1_mmq)/sizeof(int)); #pragma unroll - for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*WARP_SIZE) { - int l = l0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; tile_y[l] = by0[l]; } @@ -2567,8 +3097,8 @@ static __device__ __forceinline__ void m { const int * by0 = y + ncols_y*(kb0*(qk*sizeof(block_q8_1_mmq) / (4*QK8_1*sizeof(int))) + 1*sizeof(block_q8_1_mmq)/sizeof(int)); #pragma unroll - for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*WARP_SIZE) { - int l = l0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int l0 = 0; l0 < mmq_x*MMQ_TILE_Y_K; l0 += nwarps*warp_size) { + int l = l0 + threadIdx.y*warp_size + threadIdx.x; tile_y[l] = by0[l]; } @@ -2576,7 +3106,7 @@ static __device__ __forceinline__ void m __syncthreads(); - vec_dot(tile_x, tile_y, sum, WARP_SIZE); + vec_dot(tile_x, tile_y, sum, MMQ_TILE_NE_K); __syncthreads(); } @@ -2591,24 +3121,25 @@ static __device__ __forceinline__ void m // The mul_mat_q kernel implements "stream-k" work partitioning as described in https://arxiv.org/abs/2301.03598 -template -#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +template +#if defined(GGML_USE_HIP) #if defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(CDNA) || defined(GCN) - __launch_bounds__(WARP_SIZE*nwarps, 2) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 2) #endif // defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(CDNA) || defined(GCN) #else #if __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA - __launch_bounds__(WARP_SIZE*nwarps, 1) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 1) #else - __launch_bounds__(WARP_SIZE*nwarps, 2) + __launch_bounds__(ggml_cuda_get_physical_warp_size()*mmq_get_nwarps_device(), 2) #endif // __CUDA_ARCH__ >= GGML_CUDA_CC_VOLTA -#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__) +#endif // defined(GGML_USE_HIP) static __global__ void mul_mat_q( const char * __restrict__ x, const int * __restrict__ y, const int32_t * __restrict__ ids_dst, const int32_t * __restrict__ expert_bounds, float * __restrict__ dst, float * __restrict__ tmp_fixup, const int ncols_x, const int nrows_x, const int ncols_dst, const int stride_row_x, const int ncols_y, const int stride_col_dst, const int channel_ratio, const int nchannels_y, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, - const int sample_ratio, const int nsamples_y, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { + const int sample_ratio, const int nsamples_y, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst, + const int ncols_max) { // Skip unused template specializations for faster compilation: if (mmq_x > get_mmq_x_max_device() || mmq_x % mmq_get_granularity_device(mmq_x) != 0) { @@ -2616,10 +3147,13 @@ static __global__ void mul_mat_q( return; } + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + constexpr int qk = ggml_cuda_type_traits::qk; constexpr int mmq_y = get_mmq_y_device(); - const int ntx = (ncols_dst + mmq_x - 1) / mmq_x; // Number of tiles x + const int ntx = (ncols_max + mmq_x - 1) / mmq_x; // Number of tiles x const int nty = (nrows_x + mmq_y - 1) / mmq_y; // Number of tiles y // Initialize the ids for writing back data with just the index. @@ -2627,10 +3161,10 @@ static __global__ void mul_mat_q( // For MoE the correct indices are loaded from ids_dst. extern __shared__ int ids_dst_shared[]; // Stored at beginning of shared memory. #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2638,8 +3172,8 @@ static __global__ void mul_mat_q( } __syncthreads(); - // On AMD or old CUDA the performance with stream-k was worse, use conventional tiling instead: -#if (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA + // On non-CDNA AMD or old CUDA the performance with stream-k was worse, use conventional tiling instead: +#if (defined(GGML_USE_HIP) && !defined(CDNA)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA { const int wt = blockIdx.z / nchannels_y; const int zt = blockIdx.z - wt*nchannels_y; @@ -2667,10 +3201,10 @@ static __global__ void mul_mat_q( // __syncthreads(); // There is no previous tile that could cause a race condition. #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2688,12 +3222,12 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = false; - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, 0, ncols_x/qk); return; } -#endif // (defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA +#endif // (defined(GGML_USE_HIP) && !defined(CDNA3)) || __CUDA_ARCH__ < GGML_CUDA_CC_VOLTA const int64_t blocks_per_ne00 = ncols_x / qk; constexpr int blocks_per_iter = MMQ_ITER_K / qk; @@ -2745,10 +3279,10 @@ static __global__ void mul_mat_q( __syncthreads(); #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2766,7 +3300,7 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = false; // All but (potentially) the last iterations write their data to dst rather than the fixup buffer. - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); @@ -2812,10 +3346,10 @@ static __global__ void mul_mat_q( // The memory layout for the fixup buffer is always contiguous, therefore reset ids: __syncthreads(); #pragma unroll - for (int j0 = 0; j0 < mmq_x; j0 += nwarps*WARP_SIZE) { - const int j = j0 + threadIdx.y*WARP_SIZE + threadIdx.x; + for (int j0 = 0; j0 < mmq_x; j0 += nwarps*warp_size) { + const int j = j0 + threadIdx.y*warp_size + threadIdx.x; - if (j0 + nwarps*WARP_SIZE > mmq_x && j >= mmq_x) { + if (j0 + nwarps*warp_size > mmq_x && j >= mmq_x) { break; } @@ -2833,25 +3367,29 @@ static __global__ void mul_mat_q( const int offset_x = (wt/sample_ratio)*stride_sample_x + (zt/channel_ratio)*stride_channel_x + it*mmq_y*stride_row_x; constexpr bool fixup = true; // Last index writes its data to fixup buffer to avoid data races with other blocks. - mul_mat_q_process_tile + mul_mat_q_process_tile (x, offset_x, y + offset_y, ids_dst_shared, dst + offset_dst, tmp_fixup, stride_row_x, ncols_y, stride_col_dst, tile_x_max_i, tile_y_max_j, kb0_start, kb0_stop); } -template +template static __global__ void mul_mat_q_stream_k_fixup( const int32_t * ids_dst, const int32_t * expert_bounds, float * __restrict__ dst, const float * __restrict__ tmp_last_tile, const int ncols_x, const int nrows_x, const int ncols_dst, const int stride_col_dst, - const int nchannels_y, const int stride_channel_dst, const int nsamples_y, const int stride_sample_dst) { + const int nchannels_y, const int stride_channel_dst, const int nsamples_y, const int stride_sample_dst, + const int ncols_max) { constexpr int mmq_y = get_mmq_y_device(); constexpr int qk = ggml_cuda_type_traits::qk; constexpr int blocks_per_iter = MMQ_ITER_K / qk; const int64_t blocks_per_ne00 = ncols_x / qk; - float sum[mmq_x*mmq_y / (nwarps*WARP_SIZE)] = {0.0f}; + constexpr int nwarps = mmq_get_nwarps_device(); + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + + float sum[mmq_x*mmq_y / (nwarps*warp_size)] = {0.0f}; - const int ntx = (ncols_dst + mmq_x - 1) / mmq_x; + const int ntx = (ncols_max + mmq_x - 1) / mmq_x; const int nty = (nrows_x + mmq_y - 1) / mmq_y; const int bidx0 = blockIdx.x; @@ -2893,10 +3431,10 @@ static __global__ void mul_mat_q_stream_ const int j = j0 + threadIdx.y; #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; - sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE] += tmp_last_tile[bidx*(mmq_x*mmq_y) + j*mmq_y + i]; + sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size] += tmp_last_tile[bidx*(mmq_x*mmq_y) + j*mmq_y + i]; } } @@ -2937,14 +3475,14 @@ static __global__ void mul_mat_q_stream_ } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[j*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[j*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } return; @@ -2955,7 +3493,7 @@ static __global__ void mul_mat_q_stream_ const int col_high = expert_bounds[zt + 1]; const int col_diff = col_high - col_low; - for (int j = threadIdx.y*WARP_SIZE + threadIdx.x; j < mmq_x; j += nwarps*WARP_SIZE) { + for (int j = threadIdx.y*warp_size + threadIdx.x; j < mmq_x; j += nwarps*warp_size) { ids_dst_shared[j] = ids_dst[col_low + j]; } __syncthreads(); @@ -2975,14 +3513,14 @@ static __global__ void mul_mat_q_stream_ } #pragma unroll - for (int i0 = 0; i0 < mmq_y; i0 += WARP_SIZE) { + for (int i0 = 0; i0 < mmq_y; i0 += warp_size) { const int i = i0 + threadIdx.x; if (need_check && i > i_max) { continue; } - dst[ids_dst_shared[j]*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/WARP_SIZE) + i0/WARP_SIZE]; + dst[ids_dst_shared[j]*stride_col_dst + i] += sum[(j0/nwarps) * (mmq_y/warp_size) + i0/warp_size]; } } } @@ -2992,17 +3530,17 @@ struct mmq_args { int64_t ncols_x; int64_t nrows_x; int64_t ncols_dst; int64_t stride_row_x; int64_t ncols_y; int64_t nrows_dst; int64_t nchannels_x; int64_t nchannels_y; int64_t stride_channel_x; int64_t stride_channel_y; int64_t stride_channel_dst; int64_t nsamples_x; int64_t nsamples_y; int64_t stride_sample_x; int64_t stride_sample_y; int64_t stride_sample_dst; - bool use_stream_k; + bool use_stream_k; int64_t ncols_max; }; template -static size_t mmq_get_nbytes_shared(const int mmq_x, const int mmq_y, const int cc) { +static size_t mmq_get_nbytes_shared(const int mmq_x, const int mmq_y, const int cc, const int warp_size, const int nwarps) { const tile_x_sizes txs = mmq_get_dp4a_tile_x_sizes(type, mmq_y); const int mmq_tile_x_k = mmq_get_mma_tile_x_k(type); const size_t nbs_ids = mmq_x*sizeof(int); - const size_t nbs_x = new_mma_available(cc) ? mmq_y*mmq_tile_x_k*sizeof(int) : txs.qs*sizeof(int) + txs.dm*sizeof(half2) + txs.sc*sizeof(int); + const size_t nbs_x = (turing_mma_available(cc) || amd_mfma_available(cc)) ? mmq_y*mmq_tile_x_k*sizeof(int) : txs.qs*sizeof(int) + txs.dm*sizeof(half2) + txs.sc*sizeof(int); const size_t nbs_y = mmq_x*sizeof(block_q8_1_mmq); - return nbs_ids + nbs_x + GGML_PAD(nbs_y, MMQ_NWARPS*WARP_SIZE*sizeof(int)); + return nbs_ids + nbs_x + GGML_PAD(nbs_y, nwarps*warp_size*sizeof(int)); } template @@ -3010,17 +3548,19 @@ static void launch_mul_mat_q(ggml_backen const int id = ggml_cuda_get_device(); const int cc = ggml_cuda_info().devices[id].cc; const int nsm = ggml_cuda_info().devices[id].nsm; + const int warp_size = ggml_cuda_info().devices[id].warp_size; + const int nwarps = mmq_get_nwarps_host(cc, warp_size); const int mmq_y = get_mmq_y_host(cc); - const dim3 block_dims(WARP_SIZE, MMQ_NWARPS, 1); + const dim3 block_dims(warp_size, nwarps, 1); - const int nbytes_shared = mmq_get_nbytes_shared(mmq_x, mmq_y, cc); + const int nbytes_shared = mmq_get_nbytes_shared(mmq_x, mmq_y, cc, warp_size, nwarps); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); - CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); + CUDA_SET_SHARED_MEMORY_LIMIT((mul_mat_q), nbytes_shared); const int nty = (args.nrows_x + mmq_y - 1) / mmq_y; - const int ntx = (args.ncols_dst + mmq_x - 1) / mmq_x; + const int ntx = (args.ncols_max + mmq_x - 1) / mmq_x; const int ntzw = args.nchannels_y * args.nsamples_y; const dim3 block_nums_xy_tiling(nty, ntx, ntzw); @@ -3032,18 +3572,20 @@ static void launch_mul_mat_q(ggml_backen if (!args.use_stream_k) { if (args.nrows_x % mmq_y == 0) { constexpr bool need_check = false; - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, - sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst); + sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, + args.ncols_max); } else { constexpr bool need_check = true; - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, nullptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, - sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst); + sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, + args.ncols_max); } return; } @@ -3059,44 +3601,48 @@ static void launch_mul_mat_q(ggml_backen if (args.nrows_x % mmq_y == 0) { constexpr bool need_check = false; - - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, - sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst); + sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, + args.ncols_max); if (!fixup_needed) { return; } - mul_mat_q_stream_k_fixup<<>> + mul_mat_q_stream_k_fixup<<>> (args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, - args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst); + args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst, + args.ncols_max); } else { constexpr bool need_check = true; - - mul_mat_q<<>> + mul_mat_q<<>> (args.x, args.y, args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, args.stride_row_x, args.ncols_y, args.nrows_dst, channel_ratio, args.nchannels_y, args.stride_channel_x, args.stride_channel_y, args.stride_channel_dst, - sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst); + sample_ratio, args.nsamples_y, args.stride_sample_x, args.stride_sample_y, args.stride_sample_dst, + args.ncols_max); if (!fixup_needed) { return; } - mul_mat_q_stream_k_fixup<<>> + mul_mat_q_stream_k_fixup<<>> (args.ids_dst, args.expert_bounds, args.dst, tmp_fixup.ptr, args.ncols_x, args.nrows_x, args.ncols_dst, - args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst); + args.nrows_dst, args.nchannels_y, args.stride_channel_dst, args.nsamples_y, args.stride_sample_dst, + args.ncols_max); } } template void mul_mat_q_case(ggml_backend_cuda_context & ctx, const mmq_args & args, cudaStream_t stream) { - const int id = ggml_cuda_get_device(); - const int cc = ggml_cuda_info().devices[id].cc; - const size_t smpbo = ggml_cuda_info().devices[id].smpbo; + const int id = ggml_cuda_get_device(); + const int cc = ggml_cuda_info().devices[id].cc; + const size_t smpbo = ggml_cuda_info().devices[id].smpbo; + const int warp_size = ggml_cuda_info().devices[id].warp_size; + const int nwarps = mmq_get_nwarps_host(cc, warp_size); const int mmq_x_max = get_mmq_x_max_host(cc); const int mmq_y = get_mmq_y_host(cc); @@ -3107,11 +3653,11 @@ void mul_mat_q_case(ggml_backend_cuda_co for (int mmq_x = 8; mmq_x <= mmq_x_max && ntiles_x_best > 1; mmq_x += 8) { const int granularity = mmq_get_granularity_host(mmq_x, cc); - if (mmq_x % granularity != 0 || mmq_get_nbytes_shared(mmq_x, mmq_y, cc) > smpbo) { + if (mmq_x % granularity != 0 || mmq_get_nbytes_shared(mmq_x, mmq_y, cc, warp_size, nwarps) > smpbo) { continue; } - const int ntiles_x = (args.ncols_y + mmq_x - 1) / mmq_x; + const int ntiles_x = (args.ncols_max + mmq_x - 1) / mmq_x; if (ntiles_x < ntiles_x_best) { mmq_x_best = mmq_x; @@ -3183,6 +3729,7 @@ extern DECL_MMQ_CASE(GGML_TYPE_Q4_1); extern DECL_MMQ_CASE(GGML_TYPE_Q5_0); extern DECL_MMQ_CASE(GGML_TYPE_Q5_1); extern DECL_MMQ_CASE(GGML_TYPE_Q8_0); +extern DECL_MMQ_CASE(GGML_TYPE_MXFP4); extern DECL_MMQ_CASE(GGML_TYPE_Q2_K); extern DECL_MMQ_CASE(GGML_TYPE_Q3_K); extern DECL_MMQ_CASE(GGML_TYPE_Q4_K); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmv.cu 6641+dfsg-2/ggml/src/ggml-cuda/mmv.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mmv.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmv.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,506 +0,0 @@ -#include "ggml.h" -#include "common.cuh" -#include "mmv.cuh" - -template -static __global__ void mul_mat_vec( - const T * __restrict__ x, const float * __restrict__ y, const int32_t * __restrict__ ids, float * __restrict__ dst, - const int ncols2, const int nchannels_y, const int stride_row, const int stride_col_y2, const int stride_col_dst, - const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, - const int sample_ratio, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { - const int row = blockIdx.x; - const int channel_dst = blockIdx.y; - const int channel_x = ids ? ids[channel_dst] : channel_dst / channel_ratio; - const int channel_y = ids ? channel_dst % nchannels_y : channel_dst; - const int sample_dst = blockIdx.z; - const int sample_x = sample_dst / sample_ratio; - const int sample_y = sample_dst; - const int tid = threadIdx.x; - - constexpr int warp_size = ggml_cuda_get_physical_warp_size(); - - x += int64_t(sample_x) *stride_sample_x + channel_x *stride_channel_x + row*stride_row; - y += int64_t(sample_y) *stride_sample_y + channel_y *stride_channel_y; - dst += int64_t(sample_dst)*stride_sample_dst + channel_dst*stride_channel_dst; - - const float2 * y2 = (const float2 *) y; - - extern __shared__ char data_mmv[]; - float * buf_iw = (float *) data_mmv; - - if (block_size > warp_size) { - if (tid < warp_size) { - buf_iw[tid] = 0.0f; - } - __syncthreads(); - } - - float sumf[ncols_dst] = {0.0f}; - - if constexpr (std::is_same::value) { - const float2 * x2 = (const float2 *) x; - - for (int col2 = tid; col2 < ncols2; col2 += block_size) { - const float2 tmpx = x2[col2]; - -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - const float2 tmpy = y2[j*stride_col_y2 + col2]; - sumf[j] += tmpx.x*tmpy.x; - sumf[j] += tmpx.y*tmpy.y; - } - } - } else if constexpr (std::is_same::value) { - const half2 * x2 = (const half2 *) x; - - if (std::is_same::value) { - for (int col2 = tid; col2 < ncols2; col2 += block_size) { - const float2 tmpx = __half22float2(x2[col2]); - -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - const float2 tmpy = y2[j*stride_col_y2 + col2]; - sumf[j] += tmpx.x * tmpy.x; - sumf[j] += tmpx.y * tmpy.y; - } - } - } else { -#ifdef FP16_AVAILABLE - half2 sumh2[ncols_dst] = {{0.0f, 0.0f}}; - - for (int col2 = tid; col2 < ncols2; col2 += block_size) { - const half2 tmpx = x2[col2]; - -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - const float2 tmpy = y2[j*stride_col_y2 + col2]; - sumh2[j] += tmpx * make_half2(tmpy.x, tmpy.y); - } - } - -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - sumf[j] = __low2float(sumh2[j]) + __high2float(sumh2[j]); - } -#else - NO_DEVICE_CODE; -#endif // FP16_AVAILABLE - } - } else if constexpr (std::is_same::value) { - const int * x2 = (const int *) x; - for (int col2 = tid; col2 < ncols2; col2 += block_size) { - const int tmpx = x2[col2]; -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - const float2 tmpy = y2[j*stride_col_y2 + col2]; - sumf[j] += float(reinterpret_cast(&tmpx)[0]) * tmpy.x; - sumf[j] += float(reinterpret_cast(&tmpx)[1]) * tmpy.y; - } - } - } else { - static_assert(std::is_same::value, "unsupported type"); - } - -#pragma unroll - for (int j = 0; j < ncols_dst; ++j) { - sumf[j] = warp_reduce_sum(sumf[j]); - - if (block_size > warp_size) { - buf_iw[tid/warp_size] = sumf[j]; - __syncthreads(); - if (tid < warp_size) { - sumf[j] = buf_iw[tid]; - sumf[j] = warp_reduce_sum(sumf[j]); - } - if (j < ncols_dst) { - __syncthreads(); - } - } - } - - if (tid >= ncols_dst) { - return; - } - - dst[tid*stride_col_dst + row] = sumf[tid]; -} - -template -static void launch_mul_mat_vec_cuda( - const T * x, const float * y, const int32_t * ids, float * dst, - const int64_t ncols, const int64_t nrows, - const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, - const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, - const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, - const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, - cudaStream_t stream) { - GGML_ASSERT(ncols % 2 == 0); - GGML_ASSERT(stride_row % 2 == 0); - GGML_ASSERT(stride_col_y % 2 == 0); - GGML_ASSERT(ids || nchannels_dst % nchannels_x == 0); - GGML_ASSERT( nsamples_dst % nsamples_x == 0); - const int64_t channel_ratio = nchannels_dst / nchannels_x; - const int64_t sample_ratio = nsamples_dst / nsamples_x; - int device; - int warp_size; - - CUDA_CHECK(cudaGetDevice(&device)); - warp_size = ggml_cuda_info().devices[device].warp_size; - - int64_t block_size_best = warp_size; - int64_t niter_best = (ncols + 2*warp_size - 1) / (2*warp_size); - int64_t max_block_size = 256; - if(ggml_cuda_info().devices[device].cc > GGML_CUDA_CC_OFFSET_AMD && ggml_cuda_info().devices[device].cc < GGML_CUDA_CC_RDNA1) { - max_block_size = 128; - } - for (int64_t block_size = 2*warp_size; block_size <= max_block_size; block_size += warp_size) { - const int64_t niter = (ncols + 2*block_size - 1) / (2*block_size); - if (niter < niter_best) { - niter_best = niter; - block_size_best = block_size; - } - } - - const int smem = warp_size*sizeof(float); - const dim3 block_nums(nrows, nchannels_dst, nsamples_dst); - const dim3 block_dims(block_size_best, 1, 1); - switch (block_size_best) { - case 32: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 64: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 96: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 128: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 160: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 192: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 224: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - case 256: { - mul_mat_vec<<>> - (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - } break; - default: { - GGML_ABORT("fatal error"); - } break; - } -} - -template -static void mul_mat_vec_cuda_switch_ncols_dst( - const T * x, const float * y, const int32_t * ids, float * dst, - const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, - const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, - const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, - const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, - const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, - cudaStream_t stream) { - switch (ncols_dst) { - case 1: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 2: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 3: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 4: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 5: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 6: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 7: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - case 8: - launch_mul_mat_vec_cuda - (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - break; - default: - GGML_ABORT("fatal error"); - break; - } -} - -template -static void mul_mat_vec_cuda( - const T * x, const float * y, const int32_t * ids, float * dst, - const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, - const int64_t stride_row, const int64_t stride_col_y, const int stride_col_dst, - const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, - const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, - const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, - enum ggml_prec prec, cudaStream_t stream) { - if constexpr(std::is_same::value) { - if (prec == GGML_PREC_DEFAULT) { - mul_mat_vec_cuda_switch_ncols_dst - (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); - return; - } - } - mul_mat_vec_cuda_switch_ncols_dst - (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, - stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); -} - -void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { - GGML_ASSERT( src1->type == GGML_TYPE_F32); - GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); - GGML_ASSERT( dst->type == GGML_TYPE_F32); - - GGML_TENSOR_BINARY_OP_LOCALS; - - const size_t ts_src0 = ggml_type_size(src0->type); - const size_t ts_src1 = ggml_type_size(src1->type); - const size_t ts_dst = ggml_type_size(dst->type); - - GGML_ASSERT(!ids || ne12 == 1); // Implementation is only correct for batch size 1. - GGML_ASSERT(ne13 == ne3); - - GGML_ASSERT( nb00 == ts_src0); - GGML_ASSERT( nb10 == ts_src1); - GGML_ASSERT(!ids || ids->nb[0] == ggml_type_size(ids->type)); - GGML_ASSERT( nb0 == ts_dst); - - const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; - const enum ggml_prec prec = fast_fp16_available(cc) ? ggml_prec(dst->op_params[0]) : GGML_PREC_F32; - - const float * src1_d = (const float *) src1->data; - const int32_t * ids_d = ids ? (const int32_t *) ids->data : nullptr; - float * dst_d = (float *) dst->data; - - const int64_t s01 = src0->nb[1] / ts_src0; - const int64_t s11 = src1->nb[1] / ts_src1; - const int64_t s1 = dst->nb[1] / ts_dst; - const int64_t s02 = src0->nb[2] / ts_src0; - const int64_t s12 = src1->nb[2] / ts_src1; - const int64_t s2 = dst->nb[2] / ts_dst; - const int64_t s03 = src0->nb[3] / ts_src0; - const int64_t s13 = src1->nb[3] / ts_src1; - const int64_t s3 = dst->nb[3] / ts_dst; - - // For MUL_MAT_ID the memory layout is different than for MUL_MAT: - const int64_t ncols_dst = ids ? ne2 : ne1; - const int64_t nchannels_y = ids ? ne11 : ne12; - const int64_t nchannels_dst = ids ? ne1 : ne2; - const int64_t stride_channel_dst = ids ? s1 : s2; - const int64_t stride_channel_y = ids ? s11 : s12; - - GGML_ASSERT(!ids || ncols_dst == 1); - - switch (src0->type) { - case GGML_TYPE_F32: { - const float * src0_d = (const float *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, - ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, - ne03, ne3, s03, s13, s3, prec, ctx.stream()); - } break; - case GGML_TYPE_F16: { - const half * src0_d = (const half *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, - ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, - ne03, ne3, s03, s13, s3, prec, ctx.stream()); - } break; - case GGML_TYPE_BF16: { - const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0->data; - mul_mat_vec_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, - ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, - ne03, ne3, s03, s13, s3, prec, ctx.stream()); - } break; - default: - GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); - } -} - -void ggml_cuda_op_mul_mat_vec( - ggml_backend_cuda_context & ctx, - const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, - const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, - const int64_t src1_padded_row_size, cudaStream_t stream) { - - GGML_ASSERT(src1->type == GGML_TYPE_F32); - GGML_ASSERT(dst->type == GGML_TYPE_F32); - - const int64_t ne00 = src0->ne[0]; - const int64_t ne10 = src1->ne[0]; - const int64_t ne0 = dst->ne[0]; - const int64_t row_diff = row_high - row_low; - - const int id = ggml_cuda_get_device(); - const int cc = ggml_cuda_info().devices[id].cc; - const enum ggml_prec prec = fast_fp16_available(cc) ? ggml_prec(dst->op_params[0]) : GGML_PREC_F32; - - - // ggml_cuda_op provides single, contiguous matrices - const int64_t stride_row = ne00; - const int64_t stride_col_y = ne10; - const int64_t stride_col_dst = id == ctx.device ? ne0 : row_diff; // main device has larger memory buffer - const int64_t nchannels_x = 1; - const int64_t nchannels_y = 1; - const int64_t nchannels_dst = 1; - const int64_t stride_channel_x = 0; - const int64_t stride_channel_y = 0; - const int64_t stride_channel_dst = 0; - const int64_t nsamples_x = 1; - const int64_t nsamples_dst = 1; - const int64_t stride_sample_x = 0; - const int64_t stride_sample_y = 0; - const int64_t stride_sample_dst = 0; - - switch (src0->type) { - case GGML_TYPE_F32: { - const float * src0_d = (const float *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, - nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); - } break; - case GGML_TYPE_F16: { - const half * src0_d = (const half *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, - nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); - } break; - case GGML_TYPE_BF16: { - const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0_dd_i; - mul_mat_vec_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, - nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, - nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); - } break; - default: - GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); - } - - GGML_UNUSED(ctx); - GGML_UNUSED(src1); - GGML_UNUSED(dst); - GGML_UNUSED(src1_ddq_i); - GGML_UNUSED(src1_ncols); - GGML_UNUSED(src1_padded_row_size); -} - -bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11) { - if (src0_ne[0] % 2 != 0) { - return false; - } - switch (type) { - case GGML_TYPE_F32: - if (GGML_CUDA_CC_IS_NVIDIA(cc)) { - if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { - return ne11 <= 8; - } - if (cc >= GGML_CUDA_CC_TURING) { - return ne11 <= 4; - } - return ne11 <= 3; - } else if (GGML_CUDA_CC_IS_AMD(cc)) { - if (fp32_mma_hardware_available(cc)) { - return ne11 <= 3; - } - return ne11 <= 8; - } - return ne11 <= 8; - case GGML_TYPE_F16: - if (GGML_CUDA_CC_IS_NVIDIA(cc)) { - const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); - if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { - return src0_small && ne11 <= 4; - } - if (fp16_mma_hardware_available(cc)) { - return src0_small && ne11 <= 3; - } - return ne11 <= 8; - } else if (GGML_CUDA_CC_IS_AMD(cc)) { - if (fp16_mma_hardware_available(cc)) { - if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4(cc)) { - return ne11 <= 5; - } - return ne11 <= 2; - } - return ne11 <= 8; - } - return ne11 <= 8; - case GGML_TYPE_BF16: - if (GGML_CUDA_CC_IS_NVIDIA(cc)) { - const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); - if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { - return src0_small && ne11 <= 4; - } - if (bf16_mma_hardware_available(cc)) { - return src0_small && ne11 <= 3; - } - return ne11 <= 8; - } else if (GGML_CUDA_CC_IS_AMD(cc)) { - if (bf16_mma_hardware_available(cc)) { - return ne11 <= 3; - } - return ne11 <= 8; - } - return ne11 <= 8; - default: - return false; - } -} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmv.cuh 6641+dfsg-2/ggml/src/ggml-cuda/mmv.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/mmv.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmv.cuh 1970-01-01 00:00:00.000000000 +0000 @@ -1,11 +0,0 @@ -#include "common.cuh" - -void ggml_cuda_mul_mat_vec(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); - -void ggml_cuda_op_mul_mat_vec( - ggml_backend_cuda_context & ctx, - const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, - const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, - const int64_t src1_padded_row_size, cudaStream_t stream); - -bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmvf.cu 6641+dfsg-2/ggml/src/ggml-cuda/mmvf.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mmvf.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmvf.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,506 @@ +#include "ggml.h" +#include "common.cuh" +#include "convert.cuh" +#include "mmvf.cuh" + +template +static __global__ void mul_mat_vec_f( + const T * __restrict__ x, const float * __restrict__ y, const int32_t * __restrict__ ids, float * __restrict__ dst, + const int ncols2, const int nchannels_y, const int stride_row, const int stride_col_y2, const int stride_col_dst, + const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, + const int sample_ratio, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { + const int row = blockIdx.x; + const int channel_dst = blockIdx.y; + const int channel_x = ids ? ids[channel_dst] : channel_dst / channel_ratio; + const int channel_y = ids ? channel_dst % nchannels_y : channel_dst; + const int sample_dst = blockIdx.z; + const int sample_x = sample_dst / sample_ratio; + const int sample_y = sample_dst; + const int tid = threadIdx.x; + + constexpr int warp_size = ggml_cuda_get_physical_warp_size(); + + x += int64_t(sample_x) *stride_sample_x + channel_x *stride_channel_x + row*stride_row; + y += int64_t(sample_y) *stride_sample_y + channel_y *stride_channel_y; + dst += int64_t(sample_dst)*stride_sample_dst + channel_dst*stride_channel_dst; + + const float2 * y2 = (const float2 *) y; + + extern __shared__ char data_mmv[]; + float * buf_iw = (float *) data_mmv; + + if (block_size > warp_size) { + if (tid < warp_size) { + buf_iw[tid] = 0.0f; + } + __syncthreads(); + } + + float sumf[ncols_dst] = {0.0f}; + + if constexpr (std::is_same_v) { + const float2 * x2 = (const float2 *) x; + + for (int col2 = tid; col2 < ncols2; col2 += block_size) { + const float2 tmpx = x2[col2]; + +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + const float2 tmpy = y2[j*stride_col_y2 + col2]; + sumf[j] += tmpx.x*tmpy.x; + sumf[j] += tmpx.y*tmpy.y; + } + } + } else if constexpr (std::is_same_v) { + const half2 * x2 = (const half2 *) x; + + if (std::is_same_v) { + for (int col2 = tid; col2 < ncols2; col2 += block_size) { + const float2 tmpx = __half22float2(x2[col2]); + +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + const float2 tmpy = y2[j*stride_col_y2 + col2]; + sumf[j] += tmpx.x * tmpy.x; + sumf[j] += tmpx.y * tmpy.y; + } + } + } else { +#ifdef FP16_AVAILABLE + half2 sumh2[ncols_dst] = {{0.0f, 0.0f}}; + + for (int col2 = tid; col2 < ncols2; col2 += block_size) { + const half2 tmpx = x2[col2]; + +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + const float2 tmpy = y2[j*stride_col_y2 + col2]; + sumh2[j] += tmpx * make_half2(tmpy.x, tmpy.y); + } + } + +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + sumf[j] = __low2float(sumh2[j]) + __high2float(sumh2[j]); + } +#else + NO_DEVICE_CODE; +#endif // FP16_AVAILABLE + } + } else if constexpr (std::is_same_v) { + const int * x2 = (const int *) x; + for (int col2 = tid; col2 < ncols2; col2 += block_size) { + const int tmpx = x2[col2]; +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + const float2 tmpy = y2[j*stride_col_y2 + col2]; + sumf[j] += ggml_cuda_cast(reinterpret_cast(&tmpx)[0]) * tmpy.x; + sumf[j] += ggml_cuda_cast(reinterpret_cast(&tmpx)[1]) * tmpy.y; + } + } + } else { + static_assert(std::is_same_v, "unsupported type"); + } + +#pragma unroll + for (int j = 0; j < ncols_dst; ++j) { + sumf[j] = warp_reduce_sum(sumf[j]); + + if (block_size > warp_size) { + buf_iw[tid/warp_size] = sumf[j]; + __syncthreads(); + if (tid < warp_size) { + sumf[j] = buf_iw[tid]; + sumf[j] = warp_reduce_sum(sumf[j]); + } + if (j < ncols_dst) { + __syncthreads(); + } + } + } + + if (tid >= ncols_dst) { + return; + } + + dst[tid*stride_col_dst + row] = sumf[tid]; +} + +template +static void launch_mul_mat_vec_f_cuda( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols, const int64_t nrows, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + GGML_ASSERT(ncols % 2 == 0); + GGML_ASSERT(stride_row % 2 == 0); + GGML_ASSERT(stride_col_y % 2 == 0); + GGML_ASSERT(ids || nchannels_dst % nchannels_x == 0); + GGML_ASSERT( nsamples_dst % nsamples_x == 0); + const int64_t channel_ratio = nchannels_dst / nchannels_x; + const int64_t sample_ratio = nsamples_dst / nsamples_x; + + const int device = ggml_cuda_get_device(); + const int warp_size = ggml_cuda_info().devices[device].warp_size; + + int64_t block_size_best = warp_size; + int64_t niter_best = (ncols + 2*warp_size - 1) / (2*warp_size); + int64_t max_block_size = 256; + if(ggml_cuda_info().devices[device].cc > GGML_CUDA_CC_OFFSET_AMD && ggml_cuda_info().devices[device].cc < GGML_CUDA_CC_RDNA1) { + max_block_size = 128; + } + for (int64_t block_size = 2*warp_size; block_size <= max_block_size; block_size += warp_size) { + const int64_t niter = (ncols + 2*block_size - 1) / (2*block_size); + if (niter < niter_best) { + niter_best = niter; + block_size_best = block_size; + } + } + + const int nbytes_shared = warp_size*sizeof(float); + const dim3 block_nums(nrows, nchannels_dst, nsamples_dst); + const dim3 block_dims(block_size_best, 1, 1); + switch (block_size_best) { + case 32: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 64: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 96: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 128: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 160: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 192: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 224: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 256: { + mul_mat_vec_f<<>> + (x, y, ids, dst, ncols/2, nchannels_y, stride_row, stride_col_y/2, stride_col_dst, + channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + default: { + GGML_ABORT("fatal error"); + } break; + } +} + +template +static void mul_mat_vec_f_cuda_switch_ncols_dst( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, + const int64_t stride_row, const int64_t stride_col_y, const int64_t stride_col_dst, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + cudaStream_t stream) { + switch (ncols_dst) { + case 1: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 2: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 3: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 4: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 5: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 6: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 7: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + case 8: + launch_mul_mat_vec_f_cuda + (x, y, ids, dst, ncols, nrows, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + break; + default: + GGML_ABORT("fatal error"); + break; + } +} + +template +static void mul_mat_vec_f_cuda( + const T * x, const float * y, const int32_t * ids, float * dst, + const int64_t ncols, const int64_t nrows, const int64_t ncols_dst, + const int64_t stride_row, const int64_t stride_col_y, const int stride_col_dst, + const int64_t nchannels_x, const int64_t nchannels_y, const int64_t nchannels_dst, + const int64_t stride_channel_x, const int64_t stride_channel_y, const int64_t stride_channel_dst, const int64_t nsamples_x, + const int64_t nsamples_dst, const int64_t stride_sample_x, const int64_t stride_sample_y, const int64_t stride_sample_dst, + enum ggml_prec prec, cudaStream_t stream) { + if constexpr(std::is_same_v) { + if (prec == GGML_PREC_DEFAULT) { + mul_mat_vec_f_cuda_switch_ncols_dst + (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); + return; + } + } + mul_mat_vec_f_cuda_switch_ncols_dst + (x, y, ids, dst, ncols, nrows, ncols_dst, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, + stride_channel_dst, nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); +} + +void ggml_cuda_mul_mat_vec_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst) { + GGML_ASSERT( src1->type == GGML_TYPE_F32); + GGML_ASSERT(!ids || ids->type == GGML_TYPE_I32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + GGML_TENSOR_BINARY_OP_LOCALS; + + const size_t ts_src0 = ggml_type_size(src0->type); + const size_t ts_src1 = ggml_type_size(src1->type); + const size_t ts_dst = ggml_type_size(dst->type); + + GGML_ASSERT(!ids || ne12 == 1); // Implementation is only correct for batch size 1. + GGML_ASSERT(ne13 == ne3); + + GGML_ASSERT( nb00 == ts_src0); + GGML_ASSERT( nb10 == ts_src1); + GGML_ASSERT(!ids || ids->nb[0] == ggml_type_size(ids->type)); + GGML_ASSERT( nb0 == ts_dst); + + const int cc = ggml_cuda_info().devices[ggml_cuda_get_device()].cc; + const enum ggml_prec prec = fast_fp16_available(cc) ? ggml_prec(dst->op_params[0]) : GGML_PREC_F32; + + const float * src1_d = (const float *) src1->data; + const int32_t * ids_d = ids ? (const int32_t *) ids->data : nullptr; + float * dst_d = (float *) dst->data; + + const int64_t s01 = src0->nb[1] / ts_src0; + const int64_t s11 = src1->nb[1] / ts_src1; + const int64_t s1 = dst->nb[1] / ts_dst; + const int64_t s02 = src0->nb[2] / ts_src0; + const int64_t s12 = src1->nb[2] / ts_src1; + const int64_t s2 = dst->nb[2] / ts_dst; + const int64_t s03 = src0->nb[3] / ts_src0; + const int64_t s13 = src1->nb[3] / ts_src1; + const int64_t s3 = dst->nb[3] / ts_dst; + + // For MUL_MAT_ID the memory layout is different than for MUL_MAT: + const int64_t ncols_dst = ids ? ne2 : ne1; + const int64_t nchannels_y = ids ? ne11 : ne12; + const int64_t nchannels_dst = ids ? ne1 : ne2; + const int64_t stride_channel_dst = ids ? s1 : s2; + const int64_t stride_channel_y = ids ? s11 : s12; + + GGML_ASSERT(!ids || ncols_dst == 1); + + switch (src0->type) { + case GGML_TYPE_F32: { + const float * src0_d = (const float *) src0->data; + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, + ne03, ne3, s03, s13, s3, prec, ctx.stream()); + } break; + case GGML_TYPE_F16: { + const half * src0_d = (const half *) src0->data; + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, + ne03, ne3, s03, s13, s3, prec, ctx.stream()); + } break; + case GGML_TYPE_BF16: { + const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0->data; + mul_mat_vec_f_cuda(src0_d, src1_d, ids_d, dst_d, ne00, ne01, ncols_dst, s01, s11, s1, + ne02, nchannels_y, nchannels_dst, s02, stride_channel_y, stride_channel_dst, + ne03, ne3, s03, s13, s3, prec, ctx.stream()); + } break; + default: + GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); + } +} + +void ggml_cuda_op_mul_mat_vec_f( + ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, + const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, + const int64_t src1_padded_row_size, cudaStream_t stream) { + + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + const int64_t ne00 = src0->ne[0]; + const int64_t ne10 = src1->ne[0]; + const int64_t ne0 = dst->ne[0]; + const int64_t row_diff = row_high - row_low; + + const int id = ggml_cuda_get_device(); + const int cc = ggml_cuda_info().devices[id].cc; + const enum ggml_prec prec = fast_fp16_available(cc) ? ggml_prec(dst->op_params[0]) : GGML_PREC_F32; + + + // ggml_cuda_op provides single, contiguous matrices + const int64_t stride_row = ne00; + const int64_t stride_col_y = ne10; + const int64_t stride_col_dst = id == ctx.device ? ne0 : row_diff; // main device has larger memory buffer + const int64_t nchannels_x = 1; + const int64_t nchannels_y = 1; + const int64_t nchannels_dst = 1; + const int64_t stride_channel_x = 0; + const int64_t stride_channel_y = 0; + const int64_t stride_channel_dst = 0; + const int64_t nsamples_x = 1; + const int64_t nsamples_dst = 1; + const int64_t stride_sample_x = 0; + const int64_t stride_sample_y = 0; + const int64_t stride_sample_dst = 0; + + switch (src0->type) { + case GGML_TYPE_F32: { + const float * src0_d = (const float *) src0_dd_i; + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); + } break; + case GGML_TYPE_F16: { + const half * src0_d = (const half *) src0_dd_i; + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); + } break; + case GGML_TYPE_BF16: { + const nv_bfloat16 * src0_d = (const nv_bfloat16 *) src0_dd_i; + mul_mat_vec_f_cuda(src0_d, src1_ddf_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, prec, stream); + } break; + default: + GGML_ABORT("unsupported type: %s", ggml_type_name(src0->type)); + } + + GGML_UNUSED_VARS(ctx, src1, dst, src1_ddq_i, src1_ncols, src1_padded_row_size); +} + +bool ggml_cuda_should_use_mmvf(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11) { + if (src0_ne[0] % 2 != 0) { + return false; + } + switch (type) { + case GGML_TYPE_F32: + if (GGML_CUDA_CC_IS_NVIDIA(cc)) { + if (ampere_mma_available(cc)) { + return ne11 <= 3; + } + if (cc >= GGML_CUDA_CC_TURING) { + return ne11 <= 4; + } + return ne11 <= 3; + } else if (GGML_CUDA_CC_IS_AMD(cc)) { + if (fp32_mma_hardware_available(cc)) { + return ne11 <= 3; + } + return ne11 <= 8; + } + return ne11 <= 8; + case GGML_TYPE_F16: + if (GGML_CUDA_CC_IS_NVIDIA(cc)) { + const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); + if (ampere_mma_available(cc)) { + return src0_small && ne11 == 1; + } + if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { + return src0_small && ne11 <= 4; + } + if (fp16_mma_hardware_available(cc)) { + return src0_small && ne11 <= 3; + } + return ne11 <= 8; + } else if (GGML_CUDA_CC_IS_AMD(cc)) { + if (fp16_mma_hardware_available(cc)) { + if (GGML_CUDA_CC_IS_RDNA3(cc) || GGML_CUDA_CC_IS_RDNA4(cc)) { + return ne11 <= 5; + } + return ne11 <= 2; + } + return ne11 <= 8; + } + return ne11 <= 8; + case GGML_TYPE_BF16: + if (GGML_CUDA_CC_IS_NVIDIA(cc)) { + const bool src0_small = (src0_ne[1] <= 512 || src0_ne[2]*src0_ne[3] == 1); + if (ampere_mma_available(cc)) { + return src0_small && ne11 == 1; + } + if (cc >= GGML_CUDA_CC_ADA_LOVELACE) { + return src0_small && ne11 <= 4; + } + if (bf16_mma_hardware_available(cc)) { + return src0_small && ne11 <= 3; + } + return ne11 <= 8; + } else if (GGML_CUDA_CC_IS_AMD(cc)) { + if (bf16_mma_hardware_available(cc)) { + return ne11 <= 3; + } + return ne11 <= 8; + } + return ne11 <= 8; + default: + return false; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmvf.cuh 6641+dfsg-2/ggml/src/ggml-cuda/mmvf.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/mmvf.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmvf.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,11 @@ +#include "common.cuh" + +void ggml_cuda_mul_mat_vec_f(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, const ggml_tensor * ids, ggml_tensor * dst); + +void ggml_cuda_op_mul_mat_vec_f( + ggml_backend_cuda_context & ctx, + const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst, const char * src0_dd_i, const float * src1_ddf_i, + const char * src1_ddq_i, float * dst_dd_i, const int64_t row_low, const int64_t row_high, const int64_t src1_ncols, + const int64_t src1_padded_row_size, cudaStream_t stream); + +bool ggml_cuda_should_use_mmvf(enum ggml_type type, int cc, const int64_t * src0_ne, int64_t ne11); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/mmvq.cu 6641+dfsg-2/ggml/src/ggml-cuda/mmvq.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/mmvq.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/mmvq.cu 2025-09-30 07:36:33.000000000 +0000 @@ -13,6 +13,7 @@ static constexpr __device__ vec_dot_q_cu case GGML_TYPE_Q5_0: return vec_dot_q5_0_q8_1; case GGML_TYPE_Q5_1: return vec_dot_q5_1_q8_1; case GGML_TYPE_Q8_0: return vec_dot_q8_0_q8_1; + case GGML_TYPE_MXFP4: return vec_dot_mxfp4_q8_1; case GGML_TYPE_Q2_K: return vec_dot_q2_K_q8_1; case GGML_TYPE_Q3_K: return vec_dot_q3_K_q8_1; case GGML_TYPE_Q4_K: return vec_dot_q4_K_q8_1; @@ -38,6 +39,7 @@ static constexpr __device__ int get_vdr_ case GGML_TYPE_Q5_0: return VDR_Q5_0_Q8_1_MMVQ; case GGML_TYPE_Q5_1: return VDR_Q5_1_Q8_1_MMVQ; case GGML_TYPE_Q8_0: return VDR_Q8_0_Q8_1_MMVQ; + case GGML_TYPE_MXFP4: return VDR_MXFP4_Q8_1_MMVQ; case GGML_TYPE_Q2_K: return VDR_Q2_K_Q8_1_MMVQ; case GGML_TYPE_Q3_K: return VDR_Q3_K_Q8_1_MMVQ; case GGML_TYPE_Q4_K: return VDR_Q4_K_Q8_1_MMVQ; @@ -139,9 +141,10 @@ template __launch_bounds__(calc_nwarps(ncols_dst, get_device_table_id())*ggml_cuda_get_physical_warp_size(), 1) static __global__ void mul_mat_vec_q( const void * __restrict__ vx, const void * __restrict__ vy, const int32_t * __restrict__ ids, float * __restrict__ dst, - const int ncols_x, const int nchannels_y, const int stride_row_x, const int stride_col_y, const int stride_col_dst, - const int channel_ratio, const int stride_channel_x, const int stride_channel_y, const int stride_channel_dst, - const int sample_ratio, const int stride_sample_x, const int stride_sample_y, const int stride_sample_dst) { + const uint32_t ncols_x, const uint3 nchannels_y, const uint32_t stride_row_x, const uint32_t stride_col_y, + const uint32_t stride_col_dst, const uint3 channel_ratio, const uint32_t stride_channel_x, + const uint32_t stride_channel_y, const uint32_t stride_channel_dst, const uint3 sample_ratio, + const uint32_t stride_sample_x, const uint32_t stride_sample_y, const uint32_t stride_sample_dst) { constexpr int qk = ggml_cuda_type_traits::qk; constexpr int qi = ggml_cuda_type_traits::qi; @@ -159,12 +162,12 @@ static __global__ void mul_mat_vec_q( constexpr int blocks_per_iter = vdr * nwarps*warp_size / qi; // The MUL_MAT_ID code path with ids != nullptr is only implemented for ncols_dst == 1. - const int channel_dst = blockIdx.y; - const int channel_x = ncols_dst == 1 && ids ? ids[channel_dst] : channel_dst / channel_ratio; - const int channel_y = ncols_dst == 1 && ids ? channel_dst % nchannels_y : channel_dst; - const int sample_dst = blockIdx.z; - const int sample_x = sample_dst / sample_ratio; - const int sample_y = sample_dst; + const uint32_t channel_dst = blockIdx.y; + const uint32_t channel_x = ncols_dst == 1 && ids ? ids[channel_dst] : fastdiv(channel_dst, channel_ratio); + const uint32_t channel_y = ncols_dst == 1 && ids ? fastmodulo(channel_dst, nchannels_y) : channel_dst; + const uint32_t sample_dst = blockIdx.z; + const uint32_t sample_x = fastdiv(sample_dst, sample_ratio); + const uint32_t sample_y = sample_dst; // partial sum for each thread float tmp[ncols_dst][rows_per_cuda_block] = {{0.0f}}; @@ -217,7 +220,7 @@ static __global__ void mul_mat_vec_q( tmp[j][i] = warp_reduce_sum(tmp[j][i]); } - if (threadIdx.x < rows_per_cuda_block && (rows_per_cuda_block == 1 || row0 + int(threadIdx.x) < stride_col_dst)) { + if (threadIdx.x < rows_per_cuda_block && (rows_per_cuda_block == 1 || uint32_t(row0 + threadIdx.x) < stride_col_dst)) { dst[j*stride_col_dst + threadIdx.x] = tmp[j][threadIdx.x]; } } @@ -245,8 +248,9 @@ static void mul_mat_vec_q_switch_ncols_d GGML_ASSERT(ncols_x % ggml_blck_size(type) == 0); GGML_ASSERT(ncols_dst <= MMVQ_MAX_BATCH_SIZE); - const int channel_ratio = nchannels_dst / nchannels_x; - const int sample_ratio = nsamples_dst / nsamples_x; + const uint3 nchannels_y_fd = ids ? init_fastdiv_values(nchannels_y) : make_uint3(0, 0, 0); + const uint3 channel_ratio_fd = ids ? make_uint3(0, 0, 0) : init_fastdiv_values(nchannels_dst / nchannels_x); + const uint3 sample_ratio_fd = init_fastdiv_values(nsamples_dst / nsamples_x); const int device = ggml_cuda_get_device(); const int warp_size = ggml_cuda_info().devices[device].warp_size; @@ -254,86 +258,70 @@ static void mul_mat_vec_q_switch_ncols_d GGML_ASSERT(!ids || ncols_dst == 1); switch (ncols_dst) { - case 1: - { + case 1: { constexpr int c_ncols_dst = 1; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 2: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 2: { constexpr int c_ncols_dst = 2; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 3: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 3: { constexpr int c_ncols_dst = 3; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 4: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 4: { constexpr int c_ncols_dst = 4; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 5: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 5: { constexpr int c_ncols_dst = 5; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 6: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 6: { constexpr int c_ncols_dst = 6; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 7: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 7: { constexpr int c_ncols_dst = 7; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } - case 8: - { + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; + case 8: { constexpr int c_ncols_dst = 8; std::pair dims = calc_launch_params(c_ncols_dst, nrows_x, nchannels_dst, nsamples_dst, warp_size, table_id); mul_mat_vec_q<<>> - (vx, vy, ids, dst, ncols_x, nchannels_y, stride_row_x, stride_col_y, stride_col_dst, - channel_ratio, stride_channel_x, stride_channel_y, stride_channel_dst, - sample_ratio, stride_sample_x, stride_sample_y, stride_sample_dst); - break; - } + (vx, vy, ids, dst, ncols_x, nchannels_y_fd, stride_row_x, stride_col_y, stride_col_dst, + channel_ratio_fd, stride_channel_x, stride_channel_y, stride_channel_dst, + sample_ratio_fd, stride_sample_x, stride_sample_y, stride_sample_dst); + } break; default: GGML_ABORT("fatal error"); break; @@ -384,6 +372,13 @@ static void mul_mat_vec_q_switch_type( nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, stream); break; + case GGML_TYPE_MXFP4: + mul_mat_vec_q_switch_ncols_dst + (vx, vy, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row_x, stride_col_y, stride_col_dst, + nchannels_x, nchannels_y, nchannels_dst, stride_channel_x, stride_channel_y, stride_channel_dst, + nsamples_x, nsamples_dst, stride_sample_x, stride_sample_y, stride_sample_dst, + stream); + break; case GGML_TYPE_Q2_K: mul_mat_vec_q_switch_ncols_dst (vx, vy, ids, dst, ncols_x, nrows_x, ncols_dst, stride_row_x, stride_col_y, stride_col_dst, @@ -587,9 +582,5 @@ void ggml_cuda_op_mul_mat_vec_q( src0_dd_i, src0->type, src1_ddq_i, nullptr, dst_dd_i, ne00, row_diff, src1_ncols, stride_row_x, stride_col_y, nrows_dst, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, stream); - GGML_UNUSED(src1); - GGML_UNUSED(dst); - GGML_UNUSED(src1_ddf_i); - GGML_UNUSED(src1_ncols); - GGML_UNUSED(src1_padded_row_size); + GGML_UNUSED_VARS(src1, dst, src1_ddf_i, src1_ncols, src1_padded_row_size); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/norm.cu 6641+dfsg-2/ggml/src/ggml-cuda/norm.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/norm.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/norm.cu 2025-09-30 07:36:33.000000000 +0000 @@ -104,10 +104,30 @@ static __global__ void group_norm_f32(co } } -template -static __global__ void rms_norm_f32( - const float * x, float * dst, const int ncols, const int64_t stride_row, const int64_t stride_channel, - const int64_t stride_sample, const float eps) { +template +static __global__ void rms_norm_f32(const float * x, + float * dst, + const int ncols, + const int64_t stride_row, + const int64_t stride_channel, + const int64_t stride_sample, + const float eps, + const float * mul = nullptr, + const int64_t mul_stride_row = 0, + const int64_t mul_stride_channel = 0, + const int64_t mul_stride_sample = 0, + const uint3 mul_ncols_packed = make_uint3(0, 0, 0), + const uint3 mul_nrows_packed = make_uint3(0, 0, 0), + const uint3 mul_nchannels_packed = make_uint3(0, 0, 0), + const uint3 mul_nsamples_packed = make_uint3(0, 0, 0), + const float * add = nullptr, + const int64_t add_stride_row = 0, + const int64_t add_stride_channel = 0, + const int64_t add_stride_sample = 0, + const uint3 add_ncols_packed = make_uint3(0, 0, 0), + const uint3 add_nrows_packed = make_uint3(0, 0, 0), + const uint3 add_nchannels_packed = make_uint3(0, 0, 0), + const uint3 add_nsamples_packed = make_uint3(0, 0, 0)) { const int nrows = gridDim.x; const int nchannels = gridDim.y; @@ -116,9 +136,25 @@ static __global__ void rms_norm_f32( const int sample = blockIdx.z; const int tid = threadIdx.x; + static_assert(!do_add || do_multiply, "fusing add is not supported without multiplying"); + x += sample*stride_sample + channel*stride_channel + row*stride_row; dst += ((sample*nchannels + channel)*nrows + row)*ncols; + if constexpr (do_multiply) { + const uint32_t mul_row = fastmodulo(row, mul_nrows_packed); + const uint32_t mul_channel = fastmodulo(channel, mul_nchannels_packed); + const uint32_t mul_sample = fastmodulo(sample, mul_nsamples_packed); + mul += mul_sample * mul_stride_sample + mul_channel * mul_stride_channel + mul_row * mul_stride_row; + } + + if constexpr (do_add) { + const int add_row = fastmodulo(row, add_nrows_packed); + const int add_channel = fastmodulo(channel, add_nchannels_packed); + const int add_sample = fastmodulo(sample, add_nsamples_packed); + add += add_sample * add_stride_sample + add_channel * add_stride_channel + add_row * add_stride_row; + } + float tmp = 0.0f; // partial sum for thread in warp for (int col = tid; col < ncols; col += block_size) { @@ -129,15 +165,18 @@ static __global__ void rms_norm_f32( // sum up partial sums tmp = warp_reduce_sum(tmp); if constexpr (block_size > WARP_SIZE) { - static_assert(block_size == 1024, "unexpected block_size"); + static_assert((block_size <= 1024) && (block_size % 32 == 0), "unexpected block_size"); __shared__ float s_sum[32]; - const int warp_id = threadIdx.x / WARP_SIZE; - const int lane_id = threadIdx.x % WARP_SIZE; + const int warp_id = tid / WARP_SIZE; + const int lane_id = tid % WARP_SIZE; if (lane_id == 0) { s_sum[warp_id] = tmp; } __syncthreads(); - tmp = s_sum[lane_id]; + tmp = 0.0f; + if (lane_id < (block_size / WARP_SIZE)) { + tmp = s_sum[lane_id]; + } tmp = warp_reduce_sum(tmp); } @@ -145,7 +184,16 @@ static __global__ void rms_norm_f32( const float scale = rsqrtf(mean + eps); for (int col = tid; col < ncols; col += block_size) { - dst[col] = scale * x[col]; + if constexpr (do_multiply && do_add) { + const int mul_col = fastmodulo(col, mul_ncols_packed); + const int add_col = fastmodulo(col, add_ncols_packed); + dst[col] = scale * x[col] * mul[mul_col] + add[add_col]; + } else if constexpr (do_multiply) { + const int mul_col = fastmodulo(col, mul_ncols_packed); + dst[col] = scale * x[col] * mul[mul_col]; + } else { + dst[col] = scale * x[col]; + } } } @@ -309,11 +357,87 @@ static void rms_norm_f32_cuda( const int64_t stride_row, const int64_t stride_channel, const int64_t stride_sample, const float eps, cudaStream_t stream) { const dim3 blocks_num(nrows, nchannels, nsamples); if (ncols < 1024) { - const dim3 block_dims(WARP_SIZE, 1, 1); - rms_norm_f32<<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + const dim3 block_dims(256, 1, 1); + rms_norm_f32<256, false><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); } else { const dim3 block_dims(1024, 1, 1); - rms_norm_f32<1024><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + rms_norm_f32<1024, false><<>>(x, dst, ncols, stride_row, stride_channel, stride_sample, eps); + } +} + +static void rms_norm_mul_f32_cuda(const float * x, + const float * mul, + const float * add, + float * dst, + const int ncols, + const int nrows, + const int nchannels, + const int nsamples, + const int64_t stride_row, + const int64_t stride_channel, + const int64_t stride_sample, + const int64_t mul_stride_row, + const int64_t mul_stride_channel, + const int64_t mul_stride_sample, + const uint32_t mul_ncols, + const uint32_t mul_nrows, + const uint32_t mul_nchannels, + const uint32_t mul_nsamples, + const int64_t add_stride_row, + const int64_t add_stride_channel, + const int64_t add_stride_sample, + const uint32_t add_ncols, + const uint32_t add_nrows, + const uint32_t add_nchannels, + const uint32_t add_nsamples, + const float eps, + cudaStream_t stream) { + const dim3 blocks_num(nrows, nchannels, nsamples); + if (mul == nullptr) { + rms_norm_f32_cuda(x, dst, ncols, nrows, nchannels, nsamples, stride_row, stride_channel, stride_sample, eps, stream); + return; + } + if (add == nullptr) { + const uint3 mul_ncols_packed = init_fastdiv_values(mul_ncols); + const uint3 mul_nrows_packed = init_fastdiv_values(mul_nrows); + const uint3 mul_nchannels_packed = init_fastdiv_values(mul_nchannels); + const uint3 mul_nsamples_packed = init_fastdiv_values(mul_nsamples); + if (ncols < 1024) { + const dim3 block_dims(256, 1, 1); + rms_norm_f32<256, true><<>>( + x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, + mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed); + } else { + const dim3 block_dims(1024, 1, 1); + rms_norm_f32<1024, true><<>>( + x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, + mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed); + } + } else { + const uint3 mul_ncols_packed = init_fastdiv_values(mul_ncols); + const uint3 mul_nrows_packed = init_fastdiv_values(mul_nrows); + const uint3 mul_nchannels_packed = init_fastdiv_values(mul_nchannels); + const uint3 mul_nsamples_packed = init_fastdiv_values(mul_nsamples); + + const uint3 add_ncols_packed = init_fastdiv_values(add_ncols); + const uint3 add_nrows_packed = init_fastdiv_values(add_nrows); + const uint3 add_nchannels_packed = init_fastdiv_values(add_nchannels); + const uint3 add_nsamples_packed = init_fastdiv_values(add_nsamples); + if (ncols < 1024) { + const dim3 block_dims(256, 1, 1); + rms_norm_f32<256, true, true><<>>( + x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, + mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, add, + add_stride_row, add_stride_channel, add_stride_sample, add_ncols_packed, add_nrows_packed, + add_nchannels_packed, add_nsamples_packed); + } else { + const dim3 block_dims(1024, 1, 1); + rms_norm_f32<1024, true, true><<>>( + x, dst, ncols, stride_row, stride_channel, stride_sample, eps, mul, mul_stride_row, mul_stride_channel, + mul_stride_sample, mul_ncols_packed, mul_nrows_packed, mul_nchannels_packed, mul_nsamples_packed, add, + add_stride_row, add_stride_channel, add_stride_sample, add_ncols_packed, add_nrows_packed, + add_nchannels_packed, add_nsamples_packed); + } } } @@ -407,6 +531,154 @@ void ggml_cuda_op_rms_norm(ggml_backend_ rms_norm_f32_cuda(src0_d, dst_d, ne00, ne01, ne02, ne03, s01, s02, s03, eps, stream); } +void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * mul_tensor) { + const ggml_tensor * rms_norm_src = (ggml_tensor *) dst->src[0]; + float eps = 0.0f; + + memcpy(&eps, dst->op_params, sizeof(float)); + + const float * src0_d = (const float *) rms_norm_src->data; + const float * mul_d = nullptr; + const ggml_tensor * mul_src = nullptr; + + if (mul_tensor->src[0] == dst) { + mul_d = (float *) mul_tensor->src[1]->data; + mul_src = mul_tensor->src[1]; + } else if(mul_tensor->src[1] == dst) { + mul_d = (float *) mul_tensor->src[0]->data; + mul_src = mul_tensor->src[0]; + } else { + GGML_ASSERT(false); + } + + float * dst_d = (float *) mul_tensor->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(rms_norm_src->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(mul_tensor->type == GGML_TYPE_F32); + GGML_ASSERT(eps >= 0.0f); + + const int64_t ne00 = rms_norm_src->ne[0]; + const int64_t ne01 = rms_norm_src->ne[1]; + const int64_t ne02 = rms_norm_src->ne[2]; + const int64_t ne03 = rms_norm_src->ne[3]; + + const size_t ts0 = ggml_type_size(rms_norm_src->type); + GGML_ASSERT(rms_norm_src->nb[0] == ts0); + const int64_t s01 = rms_norm_src->nb[1] / ts0; + const int64_t s02 = rms_norm_src->nb[2] / ts0; + const int64_t s03 = rms_norm_src->nb[3] / ts0; + + const size_t ts_mul = ggml_type_size(mul_src->type); + GGML_ASSERT(mul_src->nb[0] == ts_mul); + const int64_t mul_s01 = mul_src->nb[1] / ts_mul; + const int64_t mul_s02 = mul_src->nb[2] / ts_mul; + const int64_t mul_s03 = mul_src->nb[3] / ts_mul; + + const int mul_ncols = mul_src->ne[0]; + const int mul_nrows = mul_src->ne[1]; + const int mul_nchannels = mul_src->ne[2]; + const int mul_nsamples = mul_src->ne[3]; + + rms_norm_mul_f32_cuda(src0_d, mul_d, nullptr, dst_d, + ne00, ne01, ne02, ne03, + /*s00*/ s01, s02, s03, + /*mul_s00*/ mul_s01, mul_s02, mul_s03, + mul_ncols, mul_nrows, mul_nchannels, mul_nsamples, + /*add_s00*/ 0, 0, 0, + 0, 0, 0, 0, + eps, stream); +} + +void ggml_cuda_op_rms_norm_fused_add(ggml_backend_cuda_context & ctx, + ggml_tensor * dst, + ggml_tensor * mul_tensor, + ggml_tensor * add_tensor) { + const ggml_tensor * rms_norm_src = (ggml_tensor *) dst->src[0]; + float eps = 0.0f; + + memcpy(&eps, dst->op_params, sizeof(float)); + + const float * src0_d = (const float *) rms_norm_src->data; + const float * mul_d = nullptr; + const ggml_tensor * mul_src = nullptr; + + if (mul_tensor->src[0] == dst) { + mul_d = (float *) mul_tensor->src[1]->data; + mul_src = mul_tensor->src[1]; + } else if (mul_tensor->src[1] == dst) { + mul_d = (float *) mul_tensor->src[0]->data; + mul_src = mul_tensor->src[0]; + } else { + GGML_ASSERT(false); + } + + const float * add_d = nullptr; + const ggml_tensor * add_src = nullptr; + + if (add_tensor->src[0] == mul_tensor) { + add_d = (float *) add_tensor->src[1]->data; + add_src = add_tensor->src[1]; + } else if (add_tensor->src[1] == mul_tensor) { + add_d = (float *) add_tensor->src[0]->data; + add_src = add_tensor->src[0]; + } else { + GGML_ASSERT(false); + } + + float * dst_d = (float *) add_tensor->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(rms_norm_src->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + GGML_ASSERT(mul_tensor->type == GGML_TYPE_F32); + GGML_ASSERT(add_tensor->type == GGML_TYPE_F32); + GGML_ASSERT(eps >= 0.0f); + + const int64_t ne00 = rms_norm_src->ne[0]; + const int64_t ne01 = rms_norm_src->ne[1]; + const int64_t ne02 = rms_norm_src->ne[2]; + const int64_t ne03 = rms_norm_src->ne[3]; + + const size_t ts0 = ggml_type_size(rms_norm_src->type); + GGML_ASSERT(rms_norm_src->nb[0] == ts0); + const int64_t s01 = rms_norm_src->nb[1] / ts0; + const int64_t s02 = rms_norm_src->nb[2] / ts0; + const int64_t s03 = rms_norm_src->nb[3] / ts0; + + const size_t ts_mul = ggml_type_size(mul_src->type); + GGML_ASSERT(mul_src->nb[0] == ts_mul); + const int64_t mul_s01 = mul_src->nb[1] / ts_mul; + const int64_t mul_s02 = mul_src->nb[2] / ts_mul; + const int64_t mul_s03 = mul_src->nb[3] / ts_mul; + + const int mul_ncols = mul_src->ne[0]; + const int mul_nrows = mul_src->ne[1]; + const int mul_nchannels = mul_src->ne[2]; + const int mul_nsamples = mul_src->ne[3]; + + const size_t ts_add = ggml_type_size(add_src->type); + GGML_ASSERT(add_src->nb[0] == ts_add); + const int64_t add_s01 = add_src->nb[1] / ts_add; + const int64_t add_s02 = add_src->nb[2] / ts_add; + const int64_t add_s03 = add_src->nb[3] / ts_add; + + const int add_ncols = add_src->ne[0]; + const int add_nrows = add_src->ne[1]; + const int add_nchannels = add_src->ne[2]; + const int add_nsamples = add_src->ne[3]; + + rms_norm_mul_f32_cuda(src0_d, mul_d,add_d,dst_d, + ne00,ne01, ne02, ne03, + /*s00*/ s01, s02, s03, + /*mul_s00*/ mul_s01, mul_s02, mul_s03, + mul_ncols, mul_nrows, mul_nchannels, mul_nsamples, + /*add_s00*/ add_s01, add_s02, add_s03, + add_ncols, add_nrows, add_nchannels, add_nsamples, + eps, stream); +} + void ggml_cuda_op_rms_norm_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * grad = dst->src[0]; // gradients const ggml_tensor * src0f = dst->src[1]; // src0 from forward pass diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/norm.cuh 6641+dfsg-2/ggml/src/ggml-cuda/norm.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/norm.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/norm.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -6,6 +6,13 @@ void ggml_cuda_op_group_norm(ggml_backen void ggml_cuda_op_rms_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_rms_norm_fused(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * mul_tensor); + +void ggml_cuda_op_rms_norm_fused_add(ggml_backend_cuda_context & ctx, + ggml_tensor * dst, + ggml_tensor * mul_tensor, + ggml_tensor * add_tensor); + void ggml_cuda_op_rms_norm_back(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_l2_norm(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cu 6641+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,49 @@ +#include "ggml-impl.h" +#include "opt-step-sgd.cuh" + +#include + +static __global__ void opt_step_sgd_f32( + float * __restrict__ x, const float * __restrict__ g, + const float * __restrict__ pars, const int64_t k) { + + const int64_t i = (int64_t) blockIdx.x*blockDim.x + threadIdx.x; + + if (i >= k) { + return; + } + x[i] = x[i] * (1.0f - pars[0] * pars[1]) - pars[0] * g[i]; +} + +static void opt_step_sgd_f32_cuda( + float * x, const float * g, const float * __restrict__ pars, const int64_t k, cudaStream_t stream) { + + const dim3 block_dims(CUDA_OPT_STEP_SGD_BLOCK_SIZE, 1, 1); + const dim3 block_nums((k + CUDA_OPT_STEP_SGD_BLOCK_SIZE - 1) / CUDA_OPT_STEP_SGD_BLOCK_SIZE, 1, 1); + opt_step_sgd_f32<<>>(x, g, pars, k); +} + +void ggml_cuda_opt_step_sgd(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src0_grad = dst->src[1]; + const ggml_tensor * params = dst->src[2]; + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src0_grad->type == GGML_TYPE_F32); + GGML_ASSERT(params->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_is_contiguous(src0)); + GGML_ASSERT(ggml_is_contiguous(src0_grad)); + GGML_ASSERT(ggml_is_contiguous(params)); + GGML_ASSERT(ggml_are_same_shape(src0, src0_grad)); + GGML_ASSERT(ggml_nelements(params) == 2); + + float * src0_d = (float *) src0->data; + const float * src0_grad_d = (const float *) src0_grad->data; + const float * params_d = (const float *) params->data; + + cudaStream_t stream = ctx.stream(); + + const int64_t ne = ggml_nelements(src0); + + opt_step_sgd_f32_cuda(src0_d, src0_grad_d, params_d, ne, stream); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cuh 6641+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/opt-step-sgd.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_OPT_STEP_SGD_BLOCK_SIZE 256 + +void ggml_cuda_opt_step_sgd(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/pad.cu 6641+dfsg-2/ggml/src/ggml-cuda/pad.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/pad.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/pad.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,36 +1,50 @@ #include "pad.cuh" -static __global__ void pad_f32(const float * x, float * dst, const int ne0, const int ne00, const int ne01, const int ne02, const int ne03) { - // blockIdx.z: idx of ne2*ne3, aka ne02*ne03 - // blockIdx.y: idx of ne1 - // blockIDx.x: idx of ne0 / BLOCK_SIZE - int nidx = threadIdx.x + blockIdx.x * blockDim.x; - if (nidx >= ne0) { +static __global__ void pad_f32(const float * src, float * dst, + const int lp0, const int rp0, const int lp1, const int rp1, + const int lp2, const int rp2, const int lp3, const int rp3, + const int ne0, const int ne1, const int ne2, const int ne3) { + // blockIdx.z: i3*ne2+i2 + // blockIdx.y: i1 + // blockIDx.x: i0 / CUDA_PAD_BLOCK_SIZE + // gridDim.y: ne1 + int i0 = threadIdx.x + blockIdx.x * blockDim.x; + int i1 = blockIdx.y; + int i2 = blockIdx.z % ne2; + int i3 = blockIdx.z / ne2; + if (i0 >= ne0 || i1 >= ne1 || i2 >= ne2 || i3 >= ne3) { return; } // operation - int offset_dst = - nidx + - blockIdx.y * ne0 + - blockIdx.z * ne0 * gridDim.y; - if (nidx < ne00 && blockIdx.y < (unsigned)ne01 && blockIdx.z < (unsigned)(ne02*ne03)) { - int offset_src = - nidx + - blockIdx.y * ne00 + - blockIdx.z * ne00 * ne01; - dst[offset_dst] = x[offset_src]; + const int64_t dst_idx = i3*(ne0*ne1*ne2) + i2*(ne0*ne1) + i1*ne0 + i0; + if ((i0 >= lp0 && i0 < ne0 - rp0) && + (i1 >= lp1 && i1 < ne1 - rp1) && + (i2 >= lp2 && i2 < ne2 - rp2) && + (i3 >= lp3 && i3 < ne3 - rp3)) { + const int64_t i00 = i0 - lp0; + const int64_t i01 = i1 - lp1; + const int64_t i02 = i2 - lp2; + const int64_t i03 = i3 - lp3; + const int64_t ne02 = ne2 - lp2 - rp2; + const int64_t ne01 = ne1 - lp1 - rp1; + const int64_t ne00 = ne0 - lp0 - rp0; + + const int64_t src_idx = i03*(ne00*ne01*ne02) + i02*(ne00*ne01) + i01*ne00 + i00; + + dst[dst_idx] = src[src_idx]; } else { - dst[offset_dst] = 0.0f; + dst[dst_idx] = 0.0f; } } -static void pad_f32_cuda(const float * x, float * dst, - const int ne00, const int ne01, const int ne02, const int ne03, +static void pad_f32_cuda(const float * src, float * dst, + const int lp0, const int rp0, const int lp1, const int rp1, + const int lp2, const int rp2, const int lp3, const int rp3, const int ne0, const int ne1, const int ne2, const int ne3, cudaStream_t stream) { int num_blocks = (ne0 + CUDA_PAD_BLOCK_SIZE - 1) / CUDA_PAD_BLOCK_SIZE; dim3 gridDim(num_blocks, ne1, ne2*ne3); - pad_f32<<>>(x, dst, ne0, ne00, ne01, ne02, ne03); + pad_f32<<>>(src, dst, lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3, ne0, ne1, ne2, ne3); } void ggml_cuda_op_pad(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -41,9 +55,18 @@ void ggml_cuda_op_pad(ggml_backend_cuda_ GGML_ASSERT(src0->type == GGML_TYPE_F32); GGML_ASSERT(dst->type == GGML_TYPE_F32); - GGML_ASSERT(src0->ne[3] == 1 && dst->ne[3] == 1); // just 3D tensors + GGML_ASSERT(ggml_is_contiguous(src0)); + + const int32_t lp0 = ((const int32_t*)(dst->op_params))[0]; + const int32_t rp0 = ((const int32_t*)(dst->op_params))[1]; + const int32_t lp1 = ((const int32_t*)(dst->op_params))[2]; + const int32_t rp1 = ((const int32_t*)(dst->op_params))[3]; + const int32_t lp2 = ((const int32_t*)(dst->op_params))[4]; + const int32_t rp2 = ((const int32_t*)(dst->op_params))[5]; + const int32_t lp3 = ((const int32_t*)(dst->op_params))[6]; + const int32_t rp3 = ((const int32_t*)(dst->op_params))[7]; pad_f32_cuda(src0_d, dst_d, - src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3], - dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], stream); + lp0, rp0, lp1, rp1, lp2, rp2, lp3, rp3, + dst->ne[0], dst->ne[1], dst->ne[2], dst->ne[3], stream); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cu 6641+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,91 @@ +#include "pad_reflect_1d.cuh" + +static __global__ __launch_bounds__(CUDA_PAD_REFLECT_1D_BLOCK_SIZE, 1) void + pad_reflect_1d_kernel_f32( + const void * __restrict__ src0, + void * __restrict__ dst, + const int64_t ne0, + const int64_t ne00, + const uint3 ne01, + const int64_t ne02, + const int64_t ne03, + const int64_t nb00, + const int64_t nb01, + const int64_t nb02, + const int64_t nb03, + const int64_t nb0, + const int64_t nb1, + const int64_t nb2, + const int64_t nb3, + const int p0, + const int p1) { + const int64_t i3 = blockIdx.z; + const int64_t i2 = blockIdx.y; + + const uint2 div_mod_packed = fast_div_modulo(blockIdx.x, ne01); + const int64_t tile1 = div_mod_packed.y; // i1 + const int64_t tile0 = div_mod_packed.x; // nth i0 tile + const int64_t i1 = tile1; + const int64_t i0 = threadIdx.x + tile0 * blockDim.x; + + // ne01.z is original value of unpacked ne01 (see init_fastdiv_values in common.cuh) + if (i0 >= ne0 || i1 >= ne01.z || i2 >= ne02 || i3 >= ne03) { + return; + } + + const char * src0_ptr = (const char *) src0 + i3 * nb03 + i2 * nb02 + i1 * nb01; + char * dst_ptr = (char *) dst + i3 * nb3 + i2 * nb2 + i1 * nb1; + + const int64_t rel_i0 = i0 - p0; // relative i0 in src0 + int64_t src_idx; + + if (rel_i0 < 0) { + // Left padding - reflect + src_idx = -rel_i0; + } else if (rel_i0 < ne00) { + // Middle - copy + src_idx = rel_i0; + } else { + // Right padding - reflect + src_idx = 2 * ne00 - 2 - rel_i0; + } + const float value = *(const float *) (src0_ptr + src_idx * nb00); + *(float *) (dst_ptr + i0 * nb0) = value; + + GGML_UNUSED(p1); +} + +void ggml_cuda_op_pad_reflect_1d(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + const int32_t * opts = (const int32_t *) dst->op_params; + const int p0 = opts[0]; + const int p1 = opts[1]; + + const int64_t ne00 = src0->ne[0]; + const int64_t ne01 = src0->ne[1]; + const uint3 ne01_packed = init_fastdiv_values(ne01); + const int64_t ne02 = src0->ne[2]; + const int64_t ne03 = src0->ne[3]; + + const int64_t ne0 = dst->ne[0]; + + // sanity: padded length matches + GGML_ASSERT(ne0 == ne00 + p0 + p1); + + constexpr int64_t bx = CUDA_PAD_REFLECT_1D_BLOCK_SIZE; // threads per block (x) + const int64_t tiles0 = (ne0 + bx - 1) / bx; // number of tiles along i0 + // grid.x covers i1 and all tiles of i0: [ne01 * tiles0] + // grid.y covers i2: [ne02] + // grid.z covers i3: [ne03] + const dim3 grid_dims((unsigned) (ne01 * tiles0), (unsigned) ne02, (unsigned) ne03); + const dim3 block_dims((unsigned) bx, 1, 1); + + pad_reflect_1d_kernel_f32<<>>( + src0->data, dst->data, ne0, ne00, ne01_packed, ne02, ne03, src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3], + dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3], p0, p1); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cuh 6641+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/pad_reflect_1d.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_PAD_REFLECT_1D_BLOCK_SIZE 256 + +void ggml_cuda_op_pad_reflect_1d(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/quantize.cu 6641+dfsg-2/ggml/src/ggml-cuda/quantize.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/quantize.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/quantize.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,26 +1,27 @@ #include "quantize.cuh" #include +__launch_bounds__(CUDA_QUANTIZE_BLOCK_SIZE, 1) static __global__ void quantize_q8_1( const float * __restrict__ x, void * __restrict__ vy, const int64_t ne00, const int64_t s01, const int64_t s02, const int64_t s03, - const int64_t ne0, const int ne1, const int ne2) { + const int64_t ne0, const uint32_t ne1, const uint3 ne2) { const int64_t i0 = (int64_t)blockDim.x*blockIdx.x + threadIdx.x; if (i0 >= ne0) { return; } + const int64_t i3 = fastdiv(blockIdx.z, ne2); + const int64_t i2 = blockIdx.z - i3*ne2.z; const int64_t i1 = blockIdx.y; - const int64_t i2 = blockIdx.z % ne2; - const int64_t i3 = blockIdx.z / ne2; const int64_t & i00 = i0; const int64_t & i01 = i1; const int64_t & i02 = i2; const int64_t & i03 = i3; - const int64_t i_cont = ((i3*ne2 + i2) * ne1 + i1) * ne0 + i0; + const int64_t i_cont = ((i3*ne2.z + i2) * ne1 + i1) * ne0 + i0; block_q8_1 * y = (block_q8_1 *) vy; @@ -31,10 +32,10 @@ static __global__ void quantize_q8_1( float amax = fabsf(xi); float sum = xi; - amax = warp_reduce_max(amax); - sum = warp_reduce_sum(sum); + amax = warp_reduce_max(amax); + sum = warp_reduce_sum(sum); - const float d = amax / 127; + const float d = amax / 127.0f; const int8_t q = amax == 0.0f ? 0 : roundf(xi / d); y[ib].qs[iqs] = q; @@ -43,8 +44,7 @@ static __global__ void quantize_q8_1( return; } - reinterpret_cast(y[ib].ds.x) = d; - reinterpret_cast(y[ib].ds.y) = sum; + y[ib].ds = make_half2(d, sum); } template @@ -152,10 +152,12 @@ void quantize_row_q8_1_cuda( GGML_ASSERT(!ids); GGML_ASSERT(ne0 % QK8_1 == 0); + const uint3 ne2_fastdiv = init_fastdiv_values(ne2); + const int64_t block_num_x = (ne0 + CUDA_QUANTIZE_BLOCK_SIZE - 1) / CUDA_QUANTIZE_BLOCK_SIZE; const dim3 num_blocks(block_num_x, ne1, ne2*ne3); const dim3 block_size(CUDA_QUANTIZE_BLOCK_SIZE, 1, 1); - quantize_q8_1<<>>(x, vy, ne00, s01, s02, s03, ne0, ne1, ne2); + quantize_q8_1<<>>(x, vy, ne00, s01, s02, s03, ne0, ne1, ne2_fastdiv); GGML_UNUSED(type_src0); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/reduce_rows.cuh 6641+dfsg-2/ggml/src/ggml-cuda/reduce_rows.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/reduce_rows.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/reduce_rows.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,53 @@ +#include "common.cuh" + +// Row reduction kernel template - compute sum (norm=false) or mean (norm=true) +template +static __global__ void reduce_rows_f32(const float * __restrict__ x, float * __restrict__ dst, const int ncols) { + const int row = blockIdx.x; + const int col = threadIdx.x; + + float sum = 0.0f; + const int num_unroll = 8; + float temp[num_unroll]; + float sum_temp[num_unroll] = { 0.0f }; + for (int i = col; i < ncols;) { + for (int j = 0; j < num_unroll; ++j) { + if (i < ncols) { + temp[j] = x[row * ncols + i]; + } else { + temp[j] = 0; + } + i += blockDim.x; + } + for (int j = 0; j < num_unroll; ++j) { + sum_temp[j] += temp[j]; + } + } + for (int j = 0; j < num_unroll; ++j) { + sum += sum_temp[j]; + } + + // sum up partial sums + sum = warp_reduce_sum(sum); + if (blockDim.x > WARP_SIZE) { + assert((blockDim.x <= 1024) && (blockDim.x % WARP_SIZE) == 0); + __shared__ float s_sum[32]; + const int warp_id = threadIdx.x / WARP_SIZE; + const int lane_id = threadIdx.x % WARP_SIZE; + if (lane_id == 0) { + s_sum[warp_id] = sum; + } + __syncthreads(); + sum = 0.0f; + if (lane_id < (static_cast(blockDim.x) / WARP_SIZE)) { + sum = s_sum[lane_id]; + } + sum = warp_reduce_sum(sum); + } + + if (col != 0) { + return; + } + + dst[row] = norm ? sum / ncols : sum; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/roll.cu 6641+dfsg-2/ggml/src/ggml-cuda/roll.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/roll.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/roll.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,67 @@ +#include "ggml-cuda/common.cuh" +#include "roll.cuh" + +static __forceinline__ __device__ int64_t wrap_index(const int64_t idx, const int64_t ne) { + if (idx < 0) { + return idx + ne; + } + if (idx >= ne) { + return idx - ne; + } + return idx; +} + +static __global__ void roll_f32_cuda(const float * __restrict__ src, + float * __restrict__ dst, + const int64_t ne00, + const int64_t ne01, + const int64_t ne02, + const int64_t ne03, + const int s0, + const int s1, + const int s2, + const int s3) { + const int64_t idx = int64_t(blockDim.x) * blockIdx.x + threadIdx.x; + const int64_t n_elements = ne00 * ne01 * ne02 * ne03; + + if (idx >= n_elements) { + return; + } + + const int64_t i0 = idx % ne00; + const int64_t i1 = (idx / ne00) % ne01; + const int64_t i2 = (idx / (ne00 * ne01)) % ne02; + const int64_t i3 = (idx / (ne00 * ne01 * ne02)) % ne03; + + const int64_t d0 = wrap_index(i0 - s0, ne00); + const int64_t d1 = wrap_index(i1 - s1, ne01); + const int64_t d2 = wrap_index(i2 - s2, ne02); + const int64_t d3 = wrap_index(i3 - s3, ne03); + + dst[i3 * (ne00 * ne01 * ne02) + i2 * (ne01 * ne00) + i1 * ne00 + i0] = + src[d3 * (ne00 * ne01 * ne02) + d2 * (ne01 * ne00) + d1 * ne00 + d0]; +} + +void ggml_cuda_op_roll(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + int s0 = dst->op_params[0]; + int s1 = dst->op_params[1]; + int s2 = dst->op_params[2]; + int s3 = dst->op_params[3]; + + const ggml_tensor * src0 = dst->src[0]; + const float * src0_d = (const float *) dst->src[0]->data; + float * dst_d = (float *) dst->data; + + GGML_TENSOR_UNARY_OP_LOCALS; + + GGML_ASSERT(dst->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_are_same_shape(dst->src[0], dst)); + + cudaStream_t stream = ctx.stream(); + + int64_t sz = (ne00 * ne01 * ne02 * ne03); + int64_t num_blocks = (sz + CUDA_ROLL_BLOCK_SIZE - 1) / CUDA_ROLL_BLOCK_SIZE; + + roll_f32_cuda<<>>( + src0_d, dst_d, ne00, ne01, ne02, ne03, s0, s1, s2, s3); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/roll.cuh 6641+dfsg-2/ggml/src/ggml-cuda/roll.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/roll.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/roll.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_ROLL_BLOCK_SIZE 256 + +void ggml_cuda_op_roll(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/scale.cu 6641+dfsg-2/ggml/src/ggml-cuda/scale.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/scale.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/scale.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,18 +1,19 @@ #include "scale.cuh" -static __global__ void scale_f32(const float * x, float * dst, const float scale, const float bias, const int k) { - const int i = blockDim.x*blockIdx.x + threadIdx.x; +#define MAX_GRIDDIM_X 0x7FFFFFFF - if (i >= k) { - return; - } +static __global__ void scale_f32(const float * x, float * dst, const float scale, const float bias, const int64_t nelements) { + int64_t tid = (int64_t)blockIdx.x * (int64_t)blockDim.x + (int64_t)threadIdx.x; + int64_t stride = (int64_t)blockDim.x * (int64_t)gridDim.x; - dst[i] = scale * x[i] + bias; + for (int64_t i = tid; i < nelements; i += stride) { + dst[i] = scale * x[i] + bias; + } } -static void scale_f32_cuda(const float * x, float * dst, const float scale, const float bias, const int k, cudaStream_t stream) { - const int num_blocks = (k + CUDA_SCALE_BLOCK_SIZE - 1) / CUDA_SCALE_BLOCK_SIZE; - scale_f32<<>>(x, dst, scale, bias, k); +static void scale_f32_cuda(const float * x, float * dst, const float scale, const float bias, const int64_t nelements, cudaStream_t stream) { + const int64_t num_blocks = (nelements + CUDA_SCALE_BLOCK_SIZE - 1) / CUDA_SCALE_BLOCK_SIZE; + scale_f32<<>>(x, dst, scale, bias, nelements); } void ggml_cuda_op_scale(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/set-rows.cu 6641+dfsg-2/ggml/src/ggml-cuda/set-rows.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/set-rows.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/set-rows.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,23 +1,90 @@ #include "set-rows.cuh" +#include "cpy-utils.cuh" typedef void (*set_rows_kernel_t)(const char * src, char * dst); -template -__device__ void set_rows_1(const src_t * src_f, dst_t * dst_f) {} +// Generic quantized set_rows kernel template +template +static __global__ void k_set_rows_quant( + const float * __restrict__ src0, const idx_t * __restrict__ src1, block_type * __restrict__ dst, + const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, + const int64_t ne10, const int64_t ne11, const int64_t ne12, const int64_t ne13, + const int64_t s01, const int64_t s02, const int64_t s03, + const int64_t s10, const int64_t s11, const int64_t s12, + const int64_t s1, const int64_t s2, const int64_t s3) { + + const int64_t i = int64_t(blockDim.x) * blockIdx.x + threadIdx.x; + const int64_t ne_total = (ne00 * ne01 * ne02 * ne03) / qk; + + if (i >= ne_total) { + return; + } + + const int64_t i_base = i * qk; + const int64_t i03 = i_base / (ne00 * ne01 * ne02); + const int64_t i02 = (i_base - i03 * ne00 * ne01 * ne02) / (ne00 * ne01); + const int64_t i01 = (i_base - i03 * ne00 * ne01 * ne02 - i02 * ne00 * ne01) / ne00; + const int64_t i00 = i_base - i03 * ne00 * ne01 * ne02 - i02 * ne00 * ne01 - i01 * ne00; + + const int64_t i12 = i03 % ne12; + const int64_t i11 = i02 % ne11; + const int64_t i10 = i01; + + const int64_t dst_row = *(src1 + i10*s10 + i11*s11 + i12*s12); + + const float * src0_row = src0 + i01*s01 + i02*s02 + i03*s03; + block_type * dst_row_ptr = dst + (dst_row*s1 + i02*s2 + i03*s3) / sizeof(block_type); + + const float * src_block = src0_row + i00; + block_type * dst_block = dst_row_ptr + i00 / qk; + + quantize_func(src_block, dst_block); -template<> -__device__ __forceinline__ void set_rows_1(const float * src_f, half * dst_h) { - *dst_h = __float2half(*src_f); + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); } -template<> -__device__ __forceinline__ void set_rows_1(const float * src_f, float * dst_f) { - *dst_f = *src_f; +// Template dispatch function for quantized set_rows +template +static void set_rows_cuda_quant( + const float * src0_d, const idx_t * src1_d, block_type * dst_d, + const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, + const int64_t ne10, const int64_t ne11, const int64_t ne12, const int64_t ne13, + const size_t nb01, const size_t nb02, const size_t nb03, + const size_t nb10, const size_t nb11, const size_t nb12, + const size_t nb1, const size_t nb2, const size_t nb3, + cudaStream_t stream) { + + GGML_ASSERT(ne00 % qk == 0); + const int64_t ne_total = (ne00 * ne01 * ne02 * ne03) / qk; + const int num_blocks = (ne_total + CUDA_SET_ROWS_BLOCK_SIZE - 1) / CUDA_SET_ROWS_BLOCK_SIZE; + const dim3 block_size(CUDA_SET_ROWS_BLOCK_SIZE); + const dim3 grid_size(num_blocks); + + const int64_t s01 = nb01/sizeof(float); + const int64_t s02 = nb02/sizeof(float); + const int64_t s03 = nb03/sizeof(float); + const int64_t s10 = nb10/sizeof(idx_t); + const int64_t s11 = nb11/sizeof(idx_t); + const int64_t s12 = nb12/sizeof(idx_t); + const int64_t s1 = nb1; + const int64_t s2 = nb2; + const int64_t s3 = nb3; + + if (ne_total > 0) { + k_set_rows_quant<<>>( + src0_d, src1_d, dst_d, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + s01, s02, s03, + s10, s11, s12, + s1, s2, s3); + } } -template +template static __global__ void k_set_rows( - const src_t * __restrict__ src0, const int64_t * __restrict__ src1, dst_t * __restrict__ dst, + const src_t * __restrict__ src0, const idx_t * __restrict__ src1, dst_t * __restrict__ dst, const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, const int64_t ne10, const int64_t ne11, const int64_t ne12, const int64_t ne13, const int64_t s01, const int64_t s02, const int64_t s03, @@ -45,14 +112,15 @@ static __global__ void k_set_rows( const src_t * src0_row = src0 + i01*s01 + i02*s02 + i03*s03; dst_t * dst_row_ptr = dst + dst_row*s1 + i02*s2 + i03*s3; - const src_t* src_elem = src0_row + i00; - dst_t* dst_elem = dst_row_ptr + i00; - set_rows_1(src_elem, dst_elem); + dst_row_ptr[i00] = ggml_cuda_cast(src0_row[i00]); + + GGML_UNUSED(ne10); + GGML_UNUSED(ne13); } -template +template static void set_rows_cuda( - const src_t * src0_d, const int64_t * src1_d, dst_t * dst_d, + const src_t * src0_d, const idx_t * src1_d, dst_t * dst_d, const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03, const int64_t ne10, const int64_t ne11, const int64_t ne12, const int64_t ne13, const size_t nb01, const size_t nb02, const size_t nb03, @@ -69,9 +137,9 @@ static void set_rows_cuda( const int64_t s01 = nb01/sizeof(src_t); const int64_t s02 = nb02/sizeof(src_t); const int64_t s03 = nb03/sizeof(src_t); - const int64_t s10 = nb10/sizeof(int64_t); - const int64_t s11 = nb11/sizeof(int64_t); - const int64_t s12 = nb12/sizeof(int64_t); + const int64_t s10 = nb10/sizeof(idx_t); + const int64_t s11 = nb11/sizeof(idx_t); + const int64_t s12 = nb12/sizeof(idx_t); const int64_t s1 = nb1/sizeof(dst_t); const int64_t s2 = nb2/sizeof(dst_t); const int64_t s3 = nb3/sizeof(dst_t); @@ -87,23 +155,16 @@ static void set_rows_cuda( } } - -void ggml_cuda_op_set_rows(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { - const ggml_tensor * src0 = dst->src[0]; - const ggml_tensor * src1 = dst->src[1]; - - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(src1->type == GGML_TYPE_I64); +template +static void set_rows_cuda(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + const src_t * src0_d = (const src_t *)src0->data; + const idx_t * src1_d = (const idx_t *)src1->data; GGML_TENSOR_BINARY_OP_LOCALS - const float * src0_d = (const float *)src0->data; - const int64_t * src1_d = (const int64_t *)src1->data; - cudaStream_t stream = ctx.stream(); - if (dst->type == GGML_TYPE_F32) { set_rows_cuda( src0_d, src1_d, (float*)dst->data, @@ -124,7 +185,92 @@ void ggml_cuda_op_set_rows(ggml_backend_ nb1, nb2, nb3, stream ); + } else if (dst->type == GGML_TYPE_BF16) { + set_rows_cuda( + src0_d, src1_d, (nv_bfloat16*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_Q4_0) { + set_rows_cuda_quant( + src0_d, src1_d, (block_q4_0*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_Q4_1) { + set_rows_cuda_quant( + src0_d, src1_d, (block_q4_1*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_Q5_0) { + set_rows_cuda_quant( + src0_d, src1_d, (block_q5_0*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_Q5_1) { + set_rows_cuda_quant( + src0_d, src1_d, (block_q5_1*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_Q8_0) { + set_rows_cuda_quant( + src0_d, src1_d, (block_q8_0*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else if (dst->type == GGML_TYPE_IQ4_NL) { + set_rows_cuda_quant( + src0_d, src1_d, (block_iq4_nl*)dst->data, + ne00, ne01, ne02, ne03, + ne10, ne11, ne12, ne13, + nb01, nb02, nb03, + nb10, nb11, nb12, + nb1, nb2, nb3, + stream + ); + } else { + GGML_ABORT("unsupported type %s", ggml_type_name(dst->type)); + } +} + + +void ggml_cuda_op_set_rows(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_I64 || src1->type == GGML_TYPE_I32); + + if (src1->type == GGML_TYPE_I64) { + set_rows_cuda(ctx, src0, src1, dst); } else { - GGML_ABORT("unsupported type"); + set_rows_cuda(ctx, src0, src1, dst); } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/softcap.cu 6641+dfsg-2/ggml/src/ggml-cuda/softcap.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/softcap.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/softcap.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,34 @@ +#include "softcap.cuh" + +static __global__ void softcap_f32(const float * x, float * dst, const float scale, const float softcap, const int k) { + const int i = blockDim.x*blockIdx.x + threadIdx.x; + + if (i >= k) { + return; + } + + dst[i] = tanhf(scale * x[i]) * softcap; +} + +static void softcap_f32_cuda(const float * x, float * dst, const float scale, const float softcap, const int k, cudaStream_t stream) { + const int num_blocks = (k + CUDA_SOFTCAP_BLOCK_SIZE - 1) / CUDA_SOFTCAP_BLOCK_SIZE; + softcap_f32<<>>(x, dst, scale, softcap, k); +} + +// fused GGML_OP_SCALE + GGML_UNARY_OP_TANH + GGML_OP_SCALE +void ggml_cuda_op_softcap(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * src) { + const ggml_tensor * src0 = src->src[0]; + const float * src0_d = (const float *)src0->data; + float * dst_d = (float *)dst->data; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + + float scale; + float softcap; + memcpy(&scale, (float *) src->op_params + 0, sizeof(float)); + memcpy(&softcap, (float *) dst->op_params + 0, sizeof(float)); + + softcap_f32_cuda(src0_d, dst_d, scale, softcap, ggml_nelements(src0), stream); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/softcap.cuh 6641+dfsg-2/ggml/src/ggml-cuda/softcap.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/softcap.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/softcap.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +#include "common.cuh" + +#define CUDA_SOFTCAP_BLOCK_SIZE 256 + +void ggml_cuda_op_softcap(ggml_backend_cuda_context & ctx, ggml_tensor * dst, ggml_tensor * src); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/softmax.cu 6641+dfsg-2/ggml/src/ggml-cuda/softmax.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/softmax.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/softmax.cu 2025-09-30 07:36:33.000000000 +0000 @@ -45,7 +45,7 @@ struct soft_max_params { #endif // __clang__ template static __global__ void soft_max_f32( - const float * x, const T * mask, float * dst, const soft_max_params p) { + const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params p) { const int ncols = ncols_template == 0 ? p.ncols : ncols_template; const int tid = threadIdx.x; @@ -77,7 +77,7 @@ static __global__ void soft_max_f32( // shared memory buffer to cache values between iterations: float * vals = use_shared ? buf_iw + WARP_SIZE : dst; - float max_val = -INFINITY; + float max_val = sinks ? sinks[i02] : -INFINITY; #pragma unroll for (int col0 = 0; col0 < ncols; col0 += block_size) { @@ -143,6 +143,10 @@ static __global__ void soft_max_f32( tmp = warp_reduce_sum(tmp); } + if (sinks) { + tmp += expf(sinks[i02] - max_val); + } + const float inv_sum = 1.0f / tmp; #pragma unroll @@ -183,7 +187,7 @@ static __global__ void soft_max_back_f32 } template -static void launch_soft_max_kernels(const float * x, const T * mask, float * dst, +static void launch_soft_max_kernels(const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params & p, cudaStream_t stream, dim3 block_dims, dim3 block_nums, size_t nbytes_shared) { const int id = ggml_cuda_get_device(); @@ -196,7 +200,7 @@ static void launch_soft_max_kernels(cons if (p.ncols == ncols) { CUDA_SET_SHARED_MEMORY_LIMIT((soft_max_f32), smpbo); soft_max_f32<<>> - (x, mask, dst, p); + (x, mask, sinks, dst, p); return true; } return false; @@ -209,12 +213,12 @@ static void launch_soft_max_kernels(cons //default case CUDA_SET_SHARED_MEMORY_LIMIT((soft_max_f32), smpbo); - soft_max_f32<<>>(x, mask, dst, p); + soft_max_f32<<>>(x, mask, sinks, dst, p); } template -static void soft_max_f32_cuda(const float * x, const T * mask, float * dst, const soft_max_params & params, cudaStream_t stream) { +static void soft_max_f32_cuda(const float * x, const T * mask, const float * sinks, float * dst, const soft_max_params & params, cudaStream_t stream) { int nth = WARP_SIZE; const int64_t ncols_x = params.ncols; @@ -230,10 +234,10 @@ static void soft_max_f32_cuda(const floa if (nbytes_shared <= smpbo) { - launch_soft_max_kernels<32, 64, 128, 256, 512, 1024, 2048, 4096>(x, mask, dst, params, stream, block_dims, block_nums, nbytes_shared); + launch_soft_max_kernels<32, 64, 128, 256, 512, 1024, 2048, 4096>(x, mask, sinks, dst, params, stream, block_dims, block_nums, nbytes_shared); } else { const size_t nbytes_shared_low = WARP_SIZE*sizeof(float); - soft_max_f32<<>>(x, mask, dst, params); + soft_max_f32<<>>(x, mask, sinks, dst, params); } } @@ -249,9 +253,11 @@ static void soft_max_back_f32_cuda( void ggml_cuda_op_soft_max(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { const ggml_tensor * src0 = dst->src[0]; const ggml_tensor * src1 = dst->src[1]; + const ggml_tensor * src2 = dst->src[2]; const float * src0_d = (const float *) src0->data; const void * src1_d = src1 ? (const void *) src1->data : nullptr; + const void * src2_d = src2 ? (const void *) src2->data : nullptr; float * dst_d = (float *) dst->data; cudaStream_t stream = ctx.stream(); @@ -309,9 +315,9 @@ void ggml_cuda_op_soft_max(ggml_backend_ params.m1 = m1; if (use_f16) { - soft_max_f32_cuda(src0_d, (const half *) src1_d, dst_d, params, stream); + soft_max_f32_cuda(src0_d, (const half *) src1_d, (const float *) src2_d, dst_d, params, stream); } else { - soft_max_f32_cuda(src0_d, (const float *) src1_d, dst_d, params, stream); + soft_max_f32_cuda(src0_d, (const float *) src1_d, (const float *) src2_d, dst_d, params, stream); } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/ssm-scan.cu 6641+dfsg-2/ggml/src/ggml-cuda/ssm-scan.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/ssm-scan.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/ssm-scan.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,87 +1,117 @@ +#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +#define USE_CUB +#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 + +#ifdef USE_CUB +#include +using namespace cub; +#endif // USE_CUB + #include "ssm-scan.cuh" -template -__global__ void __launch_bounds__(splitD, 2) - ssm_scan_f32(const float * __restrict__ src0, const float * __restrict__ src1, const float * __restrict__ src2, - const float * __restrict__ src3, const float * __restrict__ src4, const float * __restrict__ src5, +// We would like to keep pragma unroll for cases where L_template is not 0, +// so we suppress the clang transformation warning. +#ifdef __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wpass-failed" +#endif // __clang__ +template +__global__ void __launch_bounds__(splitD, 1) + ssm_scan_f32(const float *__restrict__ src0, const float *__restrict__ src1, const float *__restrict__ src2, + const float *__restrict__ src3, const float *__restrict__ src4, const float *__restrict__ src5, const int32_t * __restrict__ src6, float * __restrict__ dst, const int src0_nb2, const int src0_nb3, const int src1_nb2, const int src1_nb3, const int src2_nb1, const int src2_nb2, const int src3_nb1, const int src4_nb2, const int src4_nb3, const int src5_nb2, const int src5_nb3, - const int64_t s_off, const int64_t d_inner, const int64_t L) { - - constexpr int warp_size = ggml_cuda_get_physical_warp_size(); - const int bidx = blockIdx.x; // split along B (sequences) - const int bidy = blockIdx.y; // split along D (d_inner) - const int tid = threadIdx.x; - const int wid = tid / 32; - const int wtid = tid % 32; - - extern __shared__ float smem[]; - const int stride_sA = N + 1; - const int stride_ss0 = N + 1; - float * smem_A = smem; - float * smem_s0 = smem_A + splitD * stride_sA; - - const float * s0_block = (const float *) ((const char *) src0 + src6[bidx] * src0_nb3 + bidy * splitD * src0_nb2); - const float * x_block = (const float *) ((const char *) src1 + (bidx * src1_nb3) + bidy * splitD * sizeof(float)); - const float * dt_block = (const float *) ((const char *) src2 + (bidx * src2_nb2) + bidy * splitD * sizeof(float)); - const float * A_block = (const float *) ((const char *) src3 + bidy * splitD * src3_nb1); - const float * B_block = (const float *) ((const char *) src4 + (bidx * src4_nb3)); - const float * C_block = (const float *) ((const char *) src5 + (bidx * src5_nb3)); - float * y_block = (float *) ((char *) dst + (bidx * d_inner * L * sizeof(float)) + bidy * splitD * sizeof(float)); - float * s_block = (float *) ((char *) dst + s_off + bidx * src0_nb3 + bidy * splitD * src0_nb2); + const int64_t s_off, const int64_t d_inner, const int64_t L_param) +{ + const size_t L = L_template == 0 ? L_param : L_template; + const float *s0_block = (const float *)((const char *)src0 + src6[blockIdx.x] * src0_nb3 + blockIdx.y * splitD * src0_nb2); + const float *x_block = (const float *)((const char *)src1 + (blockIdx.x * src1_nb3) + blockIdx.y * splitD * sizeof(float)); + const float *dt_block = (const float *)((const char *)src2 + (blockIdx.x * src2_nb2) + blockIdx.y * splitD * sizeof(float)); + const float *A_block = (const float *)((const char *)src3 + blockIdx.y * splitD * src3_nb1); + const float *B_block = (const float *)((const char *)src4 + (blockIdx.x * src4_nb3)); + const float *C_block = (const float *)((const char *)src5 + (blockIdx.x * src5_nb3)); + float *y_block = (float *)((char *)dst + (blockIdx.x * d_inner * L * sizeof(float)) + blockIdx.y * splitD * sizeof(float)); + float *s_block = (float *)((char *)dst + s_off + blockIdx.x * src0_nb3 + blockIdx.y * splitD * src0_nb2); - const int stride_s0 = src0_nb2 / sizeof(float); - const int stride_x = src1_nb2 / sizeof(float); + const int stride_x = src1_nb2 / sizeof(float); const int stride_dt = src2_nb1 / sizeof(float); - const int stride_A = src3_nb1 / sizeof(float); - const int stride_B = src4_nb2 / sizeof(float); - const int stride_C = src5_nb2 / sizeof(float); - const int stride_s = stride_s0; - const int stride_y = d_inner; - - // can N not be 16? for example 32? - if (N == 16) { -#pragma unroll - for (size_t i = 0; i < splitD / 4; i += 2) { - float value = A_block[(wid * warp_size + i) * stride_A + wtid]; - // todo: bank conflict - // I am always confused with how to use the swizzling method to solve - // bank conflit. Hoping somebody can tell me. - smem_A[(wid * warp_size + i) * stride_sA + wtid + ((wtid / 16) > 0 ? 1 : 0)] = value; - } + const int stride_B = src4_nb2 / sizeof(float); + const int stride_C = src5_nb2 / sizeof(float); + const int stride_y = d_inner; + + float regA[N]; + float regs0[N]; + + __shared__ float smemB[N]; + __shared__ float smemC[N]; + +#ifdef USE_CUB + using BlockLoad = cub::BlockLoad; + using BlockStore = cub::BlockStore; + + union CubTempStorage { + typename BlockLoad::TempStorage load_temp; + typename BlockStore::TempStorage store_temp; + }; + __shared__ CubTempStorage cub_temp_storage; + + BlockLoad(cub_temp_storage.load_temp).Load(A_block, regA); + BlockLoad(cub_temp_storage.load_temp).Load(s0_block, regs0); +#else + const int stride_s0 = src0_nb2 / sizeof(float); + const int stride_A = src3_nb1 / sizeof(float); #pragma unroll - for (size_t i = 0; i < splitD / 4; i += 2) { - float value = s0_block[(wid * warp_size + i) * stride_s0 + wtid]; - smem_s0[(wid * warp_size + i) * stride_ss0 + wtid + ((wtid / 16) > 0 ? 1 : 0)] = value; - } + for (size_t n = 0; n < N; ++n) + { + regA[n] = A_block[threadIdx.x * stride_A + n]; + regs0[n] = s0_block[threadIdx.x * stride_s0 + n]; } +#endif - __syncthreads(); +#pragma unroll + for (size_t i = 0; i < L; i++) + { + if (threadIdx.x < N) + { + smemB[threadIdx.x] = B_block[i * stride_B + threadIdx.x]; + smemC[threadIdx.x] = C_block[i * stride_C + threadIdx.x]; + } + __syncthreads(); - for (int64_t i = 0; i < L; i++) { - float dt_soft_plus = dt_block[i * stride_dt + tid]; - if (dt_soft_plus <= 20.0f) { - dt_soft_plus = log1pf(exp(dt_soft_plus)); + float dt_soft_plus = dt_block[i * stride_dt + threadIdx.x]; + if (dt_soft_plus <= 20.0f) + { + dt_soft_plus = log1pf(expf(dt_soft_plus)); } - float x_dt = x_block[i * stride_x + tid] * dt_soft_plus; + float x_dt = x_block[i * stride_x + threadIdx.x] * dt_soft_plus; + float sumf = 0.0f; #pragma unroll - for (size_t j = 0; j < N; j++) { - float state = (smem_s0[tid * stride_ss0 + j] * expf(dt_soft_plus * smem_A[tid * stride_sA + j])) + - (B_block[i * stride_B + j] * x_dt); - sumf += state * C_block[i * stride_C + j]; - if (i == L - 1) { - s_block[tid * stride_s + j] = state; - } else { - smem_s0[tid * stride_ss0 + j] = state; - } + for (size_t n = 0; n < N; n++) + { + float state = regs0[n] * expf(dt_soft_plus * regA[n]) + smemB[n] * x_dt; + sumf += state * smemC[n]; + regs0[n] = state; } - __syncthreads(); - y_block[i * stride_y + tid] = sumf; + y_block[i * stride_y + threadIdx.x] = sumf; + } + +#ifdef USE_CUB + BlockStore(cub_temp_storage.store_temp).Store(s_block, regs0); +#else + const int stride_s = stride_s0; +#pragma unroll + for (size_t n = 0; n < N; ++n) + { + s_block[threadIdx.x * stride_s + n] = regs0[n]; } +#endif } +#ifdef __clang__ +#pragma clang diagnostic pop +#endif // __clang__ // assumes as many threads as d_state template @@ -99,7 +129,7 @@ __global__ void __launch_bounds__(d_stat const int head_off = ((blockIdx.x * splitH) % d_head) * sizeof(float); const int seq_idx = blockIdx.y; - const int group_off = (head_idx & (n_group - 1)) * d_state * sizeof(float); + const int group_off = (head_idx / (n_head / n_group)) * d_state * sizeof(float); const float * s0_block = (const float *) ((const char *) src0 + src6[seq_idx] * src0_nb3 + head_idx * src0_nb2 + head_off * d_state); const float * x_block = (const float *) ((const char *) src1 + (seq_idx * src1_nb3) + blockIdx.x * splitH * sizeof(float)); @@ -201,11 +231,11 @@ static void ssm_scan_f32_cuda(const floa const int src5_nb3, const int64_t s_off, const int64_t d_state, const int64_t head_dim, const int64_t n_head, const int64_t n_group, const int64_t n_tok, const int64_t n_seq, cudaStream_t stream) { + const int threads = 128; // NOTE: if you change conditions here, be sure to update the corresponding supports_op condition! if (src3_nb1 == sizeof(float)) { // Mamba-2 if (d_state == 128) { - const int threads = 128; GGML_ASSERT(d_state % threads == 0); // NOTE: can be any power of two between 4 and 64 const int splitH = 16; @@ -229,7 +259,6 @@ static void ssm_scan_f32_cuda(const floa GGML_ABORT("doesn't support d_state!=(128 or 256)."); } } else { - const int threads = 128; // Mamba-1 GGML_ASSERT(n_head % threads == 0); GGML_ASSERT(head_dim == 1); @@ -237,10 +266,63 @@ static void ssm_scan_f32_cuda(const floa const dim3 blocks(n_seq, (n_head + threads - 1) / threads, 1); const int smem_size = (threads * (d_state + 1) * 2) * sizeof(float); if (d_state == 16) { - ssm_scan_f32<128, 16><<>>( - src0, src1, src2, src3, src4, src5, src6, dst, + switch (n_tok) + { + case 1: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 2: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 3: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 4: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 5: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 6: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 7: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + case 8: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + default: + ssm_scan_f32<<>>( + src0, src1, src2, src3, src4, src5, src6, dst, + src0_nb2, src0_nb3, src1_nb2, src1_nb3, src2_nb1, src2_nb2, + src3_nb1, src4_nb2, src4_nb3, src5_nb2, src5_nb3, s_off, n_head, n_tok); + break; + } } else { GGML_ABORT("doesn't support d_state!=16."); } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/sum.cu 6641+dfsg-2/ggml/src/ggml-cuda/sum.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/sum.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/sum.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,19 +1,15 @@ -#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 -#define USE_CUB -#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11070 +#include "sum.cuh" +#include "sumrows.cuh" -#ifdef USE_CUB +#ifdef GGML_CUDA_USE_CUB #include using namespace cub; -#endif // USE_CUB - -#include "sumrows.cuh" -#include "sum.cuh" +#endif // GGML_CUDA_USE_CUB #include void sum_f32_cuda(ggml_cuda_pool & pool, const float * x, float * dst, const int64_t ne, cudaStream_t stream) { -#ifdef USE_CUB +#ifdef GGML_CUDA_USE_CUB size_t tmp_size = 0; DeviceReduce::Sum(nullptr, tmp_size, x, dst, ne, stream); ggml_cuda_pool_alloc tmp_alloc(pool, tmp_size); @@ -23,7 +19,7 @@ void sum_f32_cuda(ggml_cuda_pool & pool, // For AMD there is rocPRIM which could be used as a drop-in replacement via hipcub but this would require C++11 -> C++14. sum_rows_f32_cuda(x, dst, ne, 1, stream); GGML_UNUSED(pool); -#endif // USE_CUB +#endif // GGML_CUDA_USE_CUB } void ggml_cuda_op_sum(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/sumrows.cu 6641+dfsg-2/ggml/src/ggml-cuda/sumrows.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/sumrows.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/sumrows.cu 2025-09-30 07:36:33.000000000 +0000 @@ -1,9 +1,17 @@ +#include "reduce_rows.cuh" #include "sumrows.cuh" void sum_rows_f32_cuda(const float * x, float * dst, const int ncols, const int nrows, cudaStream_t stream) { - const dim3 block_dims(WARP_SIZE, 1, 1); + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(x, dst, ncols); + if ((nrows / nsm) < 2) { + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(x, dst, ncols); + } else { + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(x, dst, ncols); + } } void ggml_cuda_op_sum_rows(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { @@ -19,8 +27,17 @@ void ggml_cuda_op_sum_rows(ggml_backend_ const int64_t ncols = src0->ne[0]; const int64_t nrows = ggml_nrows(src0); - const dim3 block_dims(WARP_SIZE, 1, 1); const dim3 block_nums(nrows, 1, 1); - reduce_rows_f32<<>>(src0_d, dst_d, ncols); + const int id = ggml_cuda_get_device(); + const int nsm = ggml_cuda_info().devices[id].nsm; + if ((nrows / nsm) < 2) { + // Increase num threads to 512 for small nrows to better hide the latency + const dim3 block_dims(512, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } else { + // Enough active SMs to hide latency, use smaller blocks to allow better scheduling + const dim3 block_dims(ncols < 1024 ? 32 : 128, 1, 1); + reduce_rows_f32<<>>(src0_d, dst_d, ncols); + } } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-f16-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q4_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q5_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs128-q8_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs256-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs256-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs256-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs256-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f16-instance-hs64-f16-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f16.cuh" - -DECL_FATTN_VEC_F16_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-f16-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q4_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q5_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs128-q8_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs256-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs256-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs256-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs256-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-f16.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_1.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q8_0.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-f32-instance-hs64-f16-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -// This file has been autogenerated by generate_cu_files.py, do not edit manually. - -#include "../fattn-vec-f32.cuh" - -DECL_FATTN_VEC_F32_CASE(64, GGML_TYPE_F16, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-f16-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_F16, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_F16, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_F16, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_0-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q4_1-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q4_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_0-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q5_1-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q5_1, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-f16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-f16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-f16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-f16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_F16); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_F16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_Q4_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q4_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_Q4_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_Q5_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q5_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_Q5_1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q8_0.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q8_0.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q8_0.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/fattn-vec-instance-q8_0-q8_0.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,7 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../fattn-vec.cuh" + +DECL_FATTN_VEC_CASE( 64, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(128, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); +DECL_FATTN_VEC_CASE(256, GGML_TYPE_Q8_0, GGML_TYPE_Q8_0); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/generate_cu_files.py 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/generate_cu_files.py --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/generate_cu_files.py 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/generate_cu_files.py 2025-09-30 07:36:33.000000000 +0000 @@ -3,13 +3,15 @@ from glob import glob import os -TYPES_KV = ["GGML_TYPE_Q4_0", "GGML_TYPE_Q4_1", "GGML_TYPE_Q5_0", "GGML_TYPE_Q5_1", "GGML_TYPE_Q8_0", "GGML_TYPE_F16"] +TYPES_KV = ["GGML_TYPE_F16", "GGML_TYPE_Q4_0", "GGML_TYPE_Q4_1", "GGML_TYPE_Q5_0", "GGML_TYPE_Q5_1", "GGML_TYPE_Q8_0"] SOURCE_FATTN_VEC = """// This file has been autogenerated by generate_cu_files.py, do not edit manually. -#include "../fattn-vec-f{vkq_size}.cuh" +#include "../fattn-vec.cuh" -DECL_FATTN_VEC_F{vkq_size}_CASE({head_size}, {type_k}, {type_v}); +DECL_FATTN_VEC_CASE( 64, {type_k}, {type_v}); +DECL_FATTN_VEC_CASE(128, {type_k}, {type_v}); +DECL_FATTN_VEC_CASE(256, {type_k}, {type_v}); """ SOURCE_FATTN_MMA_START = """// This file has been autogenerated by generate_cu_files.py, do not edit manually. @@ -24,7 +26,7 @@ TYPES_MMQ = [ "GGML_TYPE_Q4_0", "GGML_TYPE_Q4_1", "GGML_TYPE_Q5_0", "GGML_TYPE_Q5_1", "GGML_TYPE_Q8_0", "GGML_TYPE_Q2_K", "GGML_TYPE_Q3_K", "GGML_TYPE_Q4_K", "GGML_TYPE_Q5_K", "GGML_TYPE_Q6_K", "GGML_TYPE_IQ2_XXS", "GGML_TYPE_IQ2_XS", "GGML_TYPE_IQ2_S", "GGML_TYPE_IQ3_XXS", "GGML_TYPE_IQ3_S", - "GGML_TYPE_IQ1_S", "GGML_TYPE_IQ4_NL", "GGML_TYPE_IQ4_XS" + "GGML_TYPE_IQ1_S", "GGML_TYPE_IQ4_NL", "GGML_TYPE_IQ4_XS", "GGML_TYPE_MXFP4" ] SOURCE_MMQ = """// This file has been autogenerated by generate_cu_files.py, do not edit manually. @@ -34,28 +36,25 @@ SOURCE_MMQ = """// This file has been au DECL_MMQ_CASE({type}); """ +SOURCE_MMF = """// This file has been autogenerated by generate_cu_files.py, do not edit manually. -def get_short_name(long_quant_name): - return long_quant_name.replace("GGML_TYPE_", "").lower() +#include "../mmf.cuh" +DECL_MMF_CASE({type}); +""" -def get_head_sizes(type_k, type_v): - if type_k == "GGML_TYPE_F16" and type_v == "GGML_TYPE_F16": - return [64, 128, 256] - if type_k == "GGML_TYPE_F16": - return [64, 128] - return [128] + +def get_short_name(long_quant_name): + return long_quant_name.replace("GGML_TYPE_", "").lower() for filename in glob("*.cu"): os.remove(filename) -for vkq_size in [16, 32]: - for type_k in TYPES_KV: - for type_v in TYPES_KV: - for head_size in get_head_sizes(type_k, type_v): - with open(f"fattn-vec-f{vkq_size}-instance-hs{head_size}-{get_short_name(type_k)}-{get_short_name(type_v)}.cu", "w") as f: - f.write(SOURCE_FATTN_VEC.format(vkq_size=vkq_size, head_size=head_size, type_k=type_k, type_v=type_v)) +for type_k in TYPES_KV: + for type_v in TYPES_KV: + with open(f"fattn-vec-instance-{get_short_name(type_k)}-{get_short_name(type_v)}.cu", "w") as f: + f.write(SOURCE_FATTN_VEC.format(type_k=type_k, type_v=type_v)) for ncols in [8, 16, 32, 64]: for ncols2 in [1, 2, 4, 8, 16]: @@ -76,3 +75,7 @@ for ncols in [8, 16, 32, 64]: for type in TYPES_MMQ: with open(f"mmq-instance-{get_short_name(type)}.cu", "w") as f: f.write(SOURCE_MMQ.format(type=type)) + +for type in range(1, 17): + with open(f"mmf-instance-ncols_{type}.cu", "w") as f: + f.write(SOURCE_MMF.format(type=type)) diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_1.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_1.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_1.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_1.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(1); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_10.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_10.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_10.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_10.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(10); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_11.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_11.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_11.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_11.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(11); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_12.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_12.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_12.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_12.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(12); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_13.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_13.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_13.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_13.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(13); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_14.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_14.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_14.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_14.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(14); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_15.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_15.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_15.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_15.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(15); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_16.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_16.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_16.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_16.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(16); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_2.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_2.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_2.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_2.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(2); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_3.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_3.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_3.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_3.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(3); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_4.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_4.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_4.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_4.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(4); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_5.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_5.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_5.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_5.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(5); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_6.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_6.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_6.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_6.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(6); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_7.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_7.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_7.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_7.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(7); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_8.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_8.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_8.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_8.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(8); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_9.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_9.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_9.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmf-instance-ncols_9.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmf.cuh" + +DECL_MMF_CASE(9); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/template-instances/mmq-instance-mxfp4.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,5 @@ +// This file has been autogenerated by generate_cu_files.py, do not edit manually. + +#include "../mmq.cuh" + +DECL_MMQ_CASE(GGML_TYPE_MXFP4); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/topk-moe.cu 6641+dfsg-2/ggml/src/ggml-cuda/topk-moe.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/topk-moe.cu 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/topk-moe.cu 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,259 @@ +#include "ggml-cuda/common.cuh" +#include "ggml.h" +#include "topk-moe.cuh" + +#include + +/* + This kernel does the following: + 1. softmax over the logits per token [n_experts, n_tokens] + 2. argmax reduce over the top-k (n_experts_used) logits + 3. write weights + ids to global memory + 4. optionally normalize the weights + + It is intended as fusion of softmax->top-k->get_rows pipeline for MoE models +*/ +template +__launch_bounds__(4 * WARP_SIZE, 1) __global__ void topk_moe_cuda(const float * logits, + float * weights, + int32_t * ids, + const int n_rows, + const int n_expert_used) { + const int row = blockIdx.x * blockDim.y + threadIdx.y; + if (row >= n_rows) { + return; + } + + logits += n_experts * row; + weights += n_expert_used * row; + ids += n_experts * row; + + constexpr int experts_per_thread = (n_experts > WARP_SIZE) ? n_experts / WARP_SIZE : 1; + + float logits_r[experts_per_thread]; + +#pragma unroll + for (int i = 0; i < n_experts; i += WARP_SIZE) { + const int expert = i + threadIdx.x; + logits_r[i / WARP_SIZE] = n_experts % WARP_SIZE == 0 || expert < n_experts ? logits[expert] : -INFINITY; + } + + float max_val = logits_r[0]; + +#pragma unroll + for (int i = 1; i < experts_per_thread; i++) { + const float val = logits_r[i]; + max_val = max(val, max_val); + } + + max_val = warp_reduce_max(max_val); + + float wt[experts_per_thread]; + float tmp = 0.f; + +#pragma unroll + for (int i = 0; i < experts_per_thread; i++) { + const float val = logits_r[i]; + wt[i] = expf(val - max_val); + tmp += wt[i]; + } + + tmp = warp_reduce_sum(tmp); + + const float inv_sum = 1.0f / tmp; + +#pragma unroll + for (int i = 0; i < experts_per_thread; i++) { + wt[i] = wt[i] * inv_sum; + } + + //at this point, each thread holds a portion of softmax, + //we do the argmax reduce over n_expert_used, each time marking + //the expert weight as -inf to exclude from the next iteration + + float wt_sum = 0.f; + + extern __shared__ float data_topk_shared[]; + float * wt_shared_ptr = data_topk_shared + threadIdx.y * n_expert_used; + + for (int k = 0; k < n_expert_used; k++) { + float max_val = wt[0]; + int max_expert = threadIdx.x; + +#pragma unroll + for (int i = 1; i < experts_per_thread; i++) { + const int expert = threadIdx.x + i * WARP_SIZE; + if ((n_experts % WARP_SIZE == 0 || expert < n_experts) && wt[i] > max_val) { + max_val = wt[i]; + max_expert = expert; + } + } + +#pragma unroll + for (int mask = WARP_SIZE / 2; mask > 0; mask /= 2) { + const float val = __shfl_xor_sync(0xFFFFFFFF, max_val, mask, WARP_SIZE); + const int expert = __shfl_xor_sync(0xFFFFFFFF, max_expert, mask, WARP_SIZE); + if (val > max_val || (val == max_val && expert < max_expert)) { + max_val = val; + max_expert = expert; + } + } + + if ((max_expert & (WARP_SIZE - 1)) == threadIdx.x) { + wt[max_expert / WARP_SIZE] = -INFINITY; + + wt_shared_ptr[k] = max_val; + ids[k] = max_expert; + if constexpr (with_norm) { + wt_sum += max_val; + } + } + } + + if constexpr (with_norm) { + wt_sum = warp_reduce_sum(wt_sum); + const float inv_sum = 1.0f / wt_sum; + + for (int i = threadIdx.x; i < n_expert_used; i += WARP_SIZE) { + wt_shared_ptr[i] = wt_shared_ptr[i] * inv_sum; + } + } + + for (int i = threadIdx.x; i < n_expert_used; i += WARP_SIZE) { + weights[i] = wt_shared_ptr[i]; + } +} + +template +static void launch_topk_moe_cuda(ggml_backend_cuda_context & ctx, + const float * logits, + float * weights, + int32_t * ids, + const int n_rows, + const int n_expert, + const int n_expert_used) { + const int rows_per_block = 4; + dim3 grid_dims((n_rows + rows_per_block - 1) / rows_per_block, 1, 1); + dim3 block_dims(WARP_SIZE, rows_per_block, 1); + cudaStream_t stream = ctx.stream(); + + const int nbytes_shared = n_expert_used * rows_per_block * sizeof(float); + + switch (n_expert) { + case 1: + topk_moe_cuda<1, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 2: + topk_moe_cuda<2, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 4: + topk_moe_cuda<4, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 8: + topk_moe_cuda<8, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 16: + topk_moe_cuda<16, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 32: + topk_moe_cuda<32, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 64: + topk_moe_cuda<64, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 128: + topk_moe_cuda<128, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 256: + topk_moe_cuda<256, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + case 512: + topk_moe_cuda<512, with_norm> + <<>>(logits, weights, ids, n_rows, n_expert_used); + break; + default: + GGML_ASSERT(false && "fatal error"); + break; + } +} + +void ggml_cuda_op_topk_moe(ggml_backend_cuda_context & ctx, + const ggml_tensor * logits, + ggml_tensor * weights, + ggml_tensor * ids, + const bool with_norm) { + GGML_ASSERT(logits->type == GGML_TYPE_F32); + GGML_ASSERT(weights->type == GGML_TYPE_F32); + GGML_ASSERT(ids->type == GGML_TYPE_I32); + + const int n_experts = logits->ne[0]; + const int n_rows = logits->ne[1]; + + const float * logits_d = (const float *) logits->src[0]->data; + float * weights_d = (float *) weights->data; + int32_t * ids_d = (int32_t *) ids->data; + + GGML_ASSERT(ids->nb[1] / ggml_type_size(ids->type) == (size_t) n_experts); + + cudaStream_t stream = ctx.stream(); + + const int n_expert_used = weights->ne[1]; + + if (with_norm) { + launch_topk_moe_cuda(ctx, logits_d, weights_d, ids_d, n_rows, n_experts, n_expert_used); + } else { + launch_topk_moe_cuda(ctx, logits_d, weights_d, ids_d, n_rows, n_experts, n_expert_used); + } +} + +bool ggml_cuda_should_use_topk_moe(const ggml_tensor * softmax, const ggml_tensor * weights) { + float scale = 1.0f; + float max_bias = 0.0f; + + memcpy(&scale, (const float *) softmax->op_params + 0, sizeof(float)); + memcpy(&max_bias, (const float *) softmax->op_params + 1, sizeof(float)); + + if (!ggml_is_contiguous(softmax->src[0]) || !ggml_is_contiguous(weights)) { + return false; + } + + if (scale != 1.0f || max_bias != 0.0f) { + return false; + } + + // don't fuse when masks or sinks are present + if (softmax->src[1] || softmax->src[2]) { + return false; + } + + const int n_expert = softmax->ne[0]; + // n_expert must be a power of 2 + if ((n_expert & (n_expert - 1)) != 0 || n_expert > 512) { + return false; + } + + return true; +} + +std::initializer_list ggml_cuda_topk_moe_ops(bool norm) { + static std::initializer_list norm_ops = { GGML_OP_SOFT_MAX, GGML_OP_RESHAPE, GGML_OP_ARGSORT, + GGML_OP_VIEW, GGML_OP_GET_ROWS, GGML_OP_RESHAPE, + GGML_OP_SUM_ROWS, GGML_OP_DIV, GGML_OP_RESHAPE }; + + static std::initializer_list no_norm_ops = { GGML_OP_SOFT_MAX, GGML_OP_RESHAPE, GGML_OP_ARGSORT, + GGML_OP_VIEW, GGML_OP_GET_ROWS }; + + if (norm) { + return norm_ops; + } + return no_norm_ops; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/topk-moe.cuh 6641+dfsg-2/ggml/src/ggml-cuda/topk-moe.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/topk-moe.cuh 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/topk-moe.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,14 @@ +#include "common.cuh" +#include "ggml.h" + +#include + +void ggml_cuda_op_topk_moe(ggml_backend_cuda_context & ctx, + const ggml_tensor * logits, + ggml_tensor * weights, + ggml_tensor * top_k, + const bool with_norm); + +bool ggml_cuda_should_use_topk_moe(const ggml_tensor * softmax, const ggml_tensor * weights); + +std::initializer_list ggml_cuda_topk_moe_ops(bool with_norm); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/tsembd.cu 6641+dfsg-2/ggml/src/ggml-cuda/tsembd.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/tsembd.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/tsembd.cu 2025-09-30 07:36:33.000000000 +0000 @@ -7,11 +7,11 @@ static __global__ void timestep_embeddin int j = threadIdx.x + blockIdx.x * blockDim.x; float * embed_data = (float *)((char *)dst + i*nb1); - if (dim % 2 != 0 && j == ((dim + 1) / 2)) { - embed_data[dim] = 0.f; + int half = dim / 2; + if (dim % 2 != 0 && j == half) { + embed_data[2 * half] = 0.f; } - int half = dim / 2; if (j >= half) { return; } diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/unary.cu 6641+dfsg-2/ggml/src/ggml-cuda/unary.cu --- 5882+dfsg-2/ggml/src/ggml-cuda/unary.cu 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/unary.cu 2025-09-30 07:36:33.000000000 +0000 @@ -83,6 +83,10 @@ static __device__ __forceinline__ float return logf(x); } +static __device__ __forceinline__ float op_elu(float x) { + return (x > 0.f) ? x : expm1f(x); +} + template static __global__ void unary_op_kernel(const T * x, T * dst, const int k) { const int i = blockDim.x*blockIdx.x + threadIdx.x; @@ -196,6 +200,9 @@ void ggml_cuda_op_log(ggml_backend_cuda_ ggml_cuda_op_unary(ctx, dst); } +void ggml_cuda_op_elu(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + ggml_cuda_op_unary(ctx, dst); +} /* gated ops */ template @@ -293,6 +300,81 @@ void ggml_cuda_op_geglu_quick(ggml_backe ggml_cuda_op_unary_gated(ctx, dst); } +// swiglu_oai + +template +static __global__ void swiglu_oai_kernel(const T * x, const T * g, T * dst, const int64_t k, const int64_t n, const int64_t o0, const int64_t o1, float alpha, float limit) { + const int64_t i = int64_t(blockDim.x)*blockIdx.x + threadIdx.x; + + if (i >= k) { + return; + } + + // perform base op and multiply with gate (either offset in same tensor or a separate one) + const int64_t j0 = (i / n) * o0 + (i % n); + const int64_t j1 = o0 == o1 ? j0 : (i / n) * o1 + (i % n); + + float xi = x[j0]; + float gi = g[j1]; + xi = fminf(xi, limit); + gi = fmaxf(fminf(gi, limit), -limit); + + float out_glu = xi / (1.0f + expf(-xi * alpha)); + out_glu = out_glu * (1.0f + gi); + + dst[i] = out_glu; +} + +template +static void swiglu_oai_cuda(const T * x, const T * g, T * dst, const int64_t k, const int64_t n, const int64_t o0, const int64_t o1, const float alpha, const float limit, cudaStream_t stream) { + const int64_t num_blocks = (k + CUDA_GLU_BLOCK_SIZE - 1) / CUDA_GLU_BLOCK_SIZE; + swiglu_oai_kernel<<>>(x, g, dst, k, n, o0, o1, alpha, limit); +} + +void ggml_cuda_op_swiglu_oai(ggml_backend_cuda_context & ctx, ggml_tensor * dst) { + const ggml_tensor * src0 = dst->src[0]; + const ggml_tensor * src1 = dst->src[1]; + void * src0_d = src0->data; + void * src1_d = src1 ? src1->data : src0->data; + const int64_t src0_o = src0->nb[1]; + const int64_t src1_o = src1 ? src1->nb[1] : src0->nb[1]; + void * dst_d = dst->data; + const int64_t nc = src1 ? src0->ne[0] : src0->ne[0] / 2; + cudaStream_t stream = ctx.stream(); + + GGML_ASSERT(ggml_is_contiguous_1(src0)); + GGML_ASSERT(src0->nb[0] == ggml_element_size(src0)); + GGML_ASSERT(ggml_is_contiguous(dst)); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT( dst->type == GGML_TYPE_F32); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(dst->ne[0] == nc); + GGML_ASSERT(ggml_nrows(dst) == ggml_nrows(src0)); + + if (src1) { + GGML_ASSERT(ggml_is_contiguous_1(src1)); + GGML_ASSERT(src1->nb[0] == ggml_element_size(src1)); + GGML_ASSERT(src1->ne[0] == nc); + GGML_ASSERT(src0->type == src1->type); + } + + //const int32_t swapped = ((const int32_t *) dst->op_params)[1]; + const int32_t swapped = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + + float * src0_p = (float *) src0_d; + float * src1_p = (float *) src1_d; + + if (!src1) { + src0_p += swapped ? nc : 0; + src1_p += swapped ? 0 : nc; + } + + swiglu_oai_cuda(src0_p, src1_p, (float *)dst_d, ggml_nelements(dst), nc, src0_o / sizeof(float), src1_o / sizeof(float), alpha, limit, stream); +} + /* silu_back */ static __device__ __forceinline__ float op_silu_back(float grad, float x) { diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/unary.cuh 6641+dfsg-2/ggml/src/ggml-cuda/unary.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/unary.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/unary.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -59,12 +59,16 @@ void ggml_cuda_op_cos(ggml_backend_cuda_ void ggml_cuda_op_log(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_elu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); + void ggml_cuda_op_reglu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_geglu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_swiglu(ggml_backend_cuda_context & ctx, ggml_tensor * dst); +void ggml_cuda_op_swiglu_oai(ggml_backend_cuda_context & ctx, ggml_tensor * dst); + void ggml_cuda_op_geglu_erf(ggml_backend_cuda_context & ctx, ggml_tensor * dst); void ggml_cuda_op_geglu_quick(ggml_backend_cuda_context & ctx, ggml_tensor * dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/vecdotq.cuh 6641+dfsg-2/ggml/src/ggml-cuda/vecdotq.cuh --- 5882+dfsg-2/ggml/src/ggml-cuda/vecdotq.cuh 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/vecdotq.cuh 2025-09-30 07:36:33.000000000 +0000 @@ -1,8 +1,20 @@ #pragma once #include "common.cuh" + #include +static __device__ __forceinline__ int get_int_b1(const void * x, const int & i32) { + const uint8_t * x8 = (const uint8_t *) x; + + int x32 = x8[4*i32 + 0] << 0; + x32 |= x8[4*i32 + 1] << 8; + x32 |= x8[4*i32 + 2] << 16; + x32 |= x8[4*i32 + 3] << 24; + + return x32; +} + static __device__ __forceinline__ int get_int_b2(const void * x, const int & i32) { const uint16_t * x16 = (const uint16_t *) x; // assume at least 2 byte alignment @@ -16,6 +28,72 @@ static __device__ __forceinline__ int ge return ((const int *) x)[i32]; // assume at least 4 byte alignment } +// q4 contains 8 indices with 4 bit each. +// This function selects those bytes from table that are at those indices and returns them as int2. +// The first int contains the bytes with even indices in q4, the second int contains the bytes with odd indices in q4. +static __device__ __forceinline__ int2 get_int_from_table_16(const int & q4, const int8_t * table) { +#if defined(GGML_USE_HIP) + // Load the 16-byte table into four 32-bit unsigned integers. + const uint32_t *values = (const uint32_t *)table; + + const uint32_t q_even = q4; + const uint32_t q_odd = (q4 >> 4); + + // Perform lookups in the lower half of the table (indices 0-7). + uint32_t v_even_low = __builtin_amdgcn_perm(values[1], values[0], q_even & 0x07070707); + uint32_t v_odd_low = __builtin_amdgcn_perm(values[1], values[0], q_odd & 0x07070707); + + // Perform lookups in the upper half of the table (indices 8-15). + uint32_t v_even_high = __builtin_amdgcn_perm(values[3], values[2], q_even & 0x07070707); + uint32_t v_odd_high = __builtin_amdgcn_perm(values[3], values[2], q_odd & 0x07070707); + + // Select between the low and high results based on the MSB of each index nibble. + uint32_t mask_even = 0x03020100 | ((q_even & 0x08080808) >> 1); + uint32_t res_x = __builtin_amdgcn_perm(v_even_high, v_even_low, mask_even); + uint32_t mask_odd = 0x03020100 | ((q_odd & 0x08080808) >> 1); + uint32_t res_y = __builtin_amdgcn_perm(v_odd_high, v_odd_low, mask_odd); + + return make_int2(res_x, res_y); +#elif !defined(GGML_USE_MUSA) + // CUDA does not have an instruction for selecting bytes with 4 bit indices. + // However, __byte_perm is an instruction that selects bytes with 3 bit indices that can be used instead. + const uint32_t * table32 = (const uint32_t *) table; + + // __byte_perm selects bytes based on the lower 16 bits in its third argument. + // Therefore, do 2 iterations over the 32 bits in q4 with 0 and 16 shift. + // To handle the fourth bit, first call _byte_perm both for the low and the high 64 bit of table, using the low 3 bits. + // Then, call __byte_perm again to select from the low and high bytes based on the fourth bit. + uint32_t tmp[2]; + const uint32_t low_high_selection_indices = (0x32103210 | ((q4 & 0x88888888) >> 1)); +#pragma unroll + for (uint32_t i = 0; i < 2; ++i) { + const uint32_t shift = 16 * i; + + const uint32_t low = __byte_perm(table32[0], table32[1], q4 >> shift); + const uint32_t high = __byte_perm(table32[2], table32[3], q4 >> shift); + tmp[i] = __byte_perm(low, high, low_high_selection_indices >> shift); + } + + // tmp contains the bytes from tyble in the same order as the 4 bit indices in q4. + // However, for the result we need ints with all even/odd 4 bit indices in q4. + // Therefore, 2 more calls to __byte_perm to put the bytes in the correct order. + return make_int2(__byte_perm(tmp[0], tmp[1], 0x6420), __byte_perm(tmp[0], tmp[1], 0x7531)); +#else + // Generic implementation. + const int q0_32 = (q4 >> 0) & 0x0F0F0F0F; + const int8_t * q0_8 = (const int8_t *) &q0_32; + const char4 val0_8 = make_char4( + table[q0_8[0]], table[q0_8[1]], table[q0_8[2]], table[q0_8[3]]); + + const int q1_32 = (q4 >> 4) & 0x0F0F0F0F; + const int8_t * q1_8 = (const int8_t *) &q1_32; + const char4 val1_8 = make_char4( + table[q1_8[0]], table[q1_8[1]], table[q1_8[2]], table[q1_8[3]]); + + return make_int2(*((const int *) &val0_8), *((const int *) &val1_8)); +#endif +} + // VDR = vec dot ratio, how many contiguous integers each thread processes when the vec dot kernel is called // MMVQ = mul_mat_vec_q, MMQ = mul_mat_q @@ -61,7 +139,7 @@ template static __device__ __f sumi = ggml_cuda_dp4a(vi1, u[2*i+1], sumi); } -#ifdef GGML_CUDA_F16 +#ifdef FAST_FP16_AVAILABLE const float2 tmp = __half22float2(__hmul2(dm4, ds8)); const float d4d8 = tmp.x; const float m4s8 = tmp.y; @@ -70,7 +148,7 @@ template static __device__ __f const float2 ds8f = __half22float2(ds8); const float d4d8 = dm4f.x * ds8f.x; const float m4s8 = dm4f.y * ds8f.y; -#endif // GGML_CUDA_F16 +#endif // FAST_FP16_AVAILABLE // scale second part of sum by QI8_1/(vdr * QR4_1) to compensate for multiple threads adding it return sumi * d4d8 + m4s8 / (QI8_1 / (vdr * QR4_1)); @@ -132,7 +210,7 @@ template static __device__ __f sumi = ggml_cuda_dp4a(vi1, u[2*i+1], sumi); // SIMD dot product of quantized values } -#ifdef GGML_CUDA_F16 +#ifdef FAST_FP16_AVAILABLE const float2 tmp = __half22float2(__hmul2(dm5, ds8)); const float d5d8 = tmp.x; const float m5s8 = tmp.y; @@ -141,7 +219,7 @@ template static __device__ __f const float2 ds8f = __half22float2(ds8); const float d5d8 = dm5f.x * ds8f.x; const float m5s8 = dm5f.y * ds8f.y; -#endif // GGML_CUDA_F16 +#endif // FAST_FP16_AVAILABLE // scale second part of sum by QI5_1 / vdr to compensate for multiple threads adding it return sumi*d5d8 + m5s8 / (QI5_1 / vdr); @@ -175,7 +253,7 @@ template static __device__ __f sumi = ggml_cuda_dp4a(v[i], u[i], sumi); } -#ifdef GGML_CUDA_F16 +#ifdef FAST_FP16_AVAILABLE const float2 tmp = __half22float2(__hmul2(dm8, ds8)); const float d8d8 = tmp.x; const float m8s8 = tmp.y; @@ -184,7 +262,7 @@ template static __device__ __f const float2 ds8f = __half22float2(ds8); const float d8d8 = dm8f.x * ds8f.x; const float m8s8 = dm8f.y * ds8f.y; -#endif // GGML_CUDA_F16 +#endif // FAST_FP16_AVAILABLE // scale second part of sum by QI8_1/ vdr to compensate for multiple threads adding it return sumi*d8d8 + m8s8 / (QI8_1 / vdr); @@ -211,6 +289,30 @@ template static __device__ __f return d8_1*sumf; } +#define VDR_MXFP4_Q8_1_MMVQ 2 +#define VDR_MXFP4_Q8_1_MMQ 4 + +static __device__ __forceinline__ float vec_dot_mxfp4_q8_1( + const void * __restrict__ vbq, const block_q8_1 * __restrict__ bq8_1, const int & kbx, const int & iqs) { + + const block_mxfp4 * bq4 = (const block_mxfp4 *) vbq + kbx; + + const int * q8 = (const int *) bq8_1->qs + iqs; + + int sumi = 0; +#pragma unroll + for (int l = 0; l < VDR_MXFP4_Q8_1_MMVQ; ++l) { + const int aux_q4 = get_int_b1(bq4->qs, iqs + l); + const int2 v = get_int_from_table_16(aux_q4, kvalues_mxfp4); + + sumi = ggml_cuda_dp4a(v.x, q8[l + 0], sumi); + sumi = ggml_cuda_dp4a(v.y, q8[l + 4], sumi); + } + + const float d = ggml_cuda_e8m0_to_fp32(bq4->e) * 0.5f * __low2float(bq8_1->ds); + return d * sumi; +} + #define VDR_Q2_K_Q8_1_MMVQ 1 #define VDR_Q2_K_Q8_1_MMQ 4 @@ -1068,20 +1170,6 @@ static __device__ __forceinline__ float return d * ((sumi[0] + sumf[0]) * sc0 + (sumi[1] + sumf[1]) * sc1); } -static __device__ __forceinline__ int2 get_int_from_table_16(const int & q4) { - const int q0_32 = (q4 >> 0) & 0x0F0F0F0F; - const int8_t * q0_8 = (const int8_t *) &q0_32; - const char4 val0_8 = make_char4( - kvalues_iq4nl[q0_8[0]], kvalues_iq4nl[q0_8[1]], kvalues_iq4nl[q0_8[2]], kvalues_iq4nl[q0_8[3]]); - - const int q1_32 = (q4 >> 4) & 0x0F0F0F0F; - const int8_t * q1_8 = (const int8_t *) &q1_32; - const char4 val1_8 = make_char4( - kvalues_iq4nl[q1_8[0]], kvalues_iq4nl[q1_8[1]], kvalues_iq4nl[q1_8[2]], kvalues_iq4nl[q1_8[3]]); - - return make_int2(*((const int *) &val0_8), *((const int *) &val1_8)); -} - #define VDR_IQ4_NL_Q8_1_MMVQ 2 #define VDR_IQ4_NL_Q8_1_MMQ 4 @@ -1096,7 +1184,7 @@ static __device__ __forceinline__ float #pragma unroll for (int l = 0; l < VDR_Q4_0_Q8_1_MMVQ; ++l) { const int aux_q4 = get_int_b2(bq4->qs, iqs + l); - const int2 v = get_int_from_table_16(aux_q4); + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); sumi = ggml_cuda_dp4a(v.x, q8[l + 0], sumi); sumi = ggml_cuda_dp4a(v.y, q8[l + 4], sumi); @@ -1118,7 +1206,7 @@ static __device__ __forceinline__ float #pragma unroll for (int j = 0; j < 4; ++j) { const int aux_q4 = get_int_b4(bq4->qs, iqs + j); - const int2 v = get_int_from_table_16(aux_q4); + const int2 v = get_int_from_table_16(aux_q4, kvalues_iq4nl); const int u0 = get_int_b4(bq8_1[iqs/4].qs, j + 0); const int u1 = get_int_b4(bq8_1[iqs/4].qs, j + 4); diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/vendors/cuda.h 6641+dfsg-2/ggml/src/ggml-cuda/vendors/cuda.h --- 5882+dfsg-2/ggml/src/ggml-cuda/vendors/cuda.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/vendors/cuda.h 2025-09-30 07:36:33.000000000 +0000 @@ -6,6 +6,10 @@ #include #include +#if CUDART_VERSION >= 12050 +#include +#endif // CUDART_VERSION >= 12050 + #if CUDART_VERSION < 11020 #define CU_DEVICE_ATTRIBUTE_VIRTUAL_MEMORY_MANAGEMENT_SUPPORTED CU_DEVICE_ATTRIBUTE_VIRTUAL_ADDRESS_MANAGEMENT_SUPPORTED #define CUBLAS_TF32_TENSOR_OP_MATH CUBLAS_TENSOR_OP_MATH diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/vendors/hip.h 6641+dfsg-2/ggml/src/ggml-cuda/vendors/hip.h --- 5882+dfsg-2/ggml/src/ggml-cuda/vendors/hip.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/vendors/hip.h 2025-09-30 07:36:33.000000000 +0000 @@ -1,14 +1,10 @@ #pragma once -#define HIP_ENABLE_WARP_SYNC_BUILTINS 1 +#define HIP_DISABLE_WARP_SYNC_BUILTINS 1 #include #include #include -#include -#ifdef __HIP_PLATFORM_AMD__ -// for rocblas_initialize() -#include "rocblas/rocblas.h" -#endif // __HIP_PLATFORM_AMD__ +#include #define CUBLAS_GEMM_DEFAULT HIPBLAS_GEMM_DEFAULT #define CUBLAS_GEMM_DEFAULT_TENSOR_OP HIPBLAS_GEMM_DEFAULT @@ -26,7 +22,10 @@ #define CU_MEM_ACCESS_FLAGS_PROT_READWRITE hipMemAccessFlagsProtReadWrite #define CU_CHECK(fn) {hipError_t err = fn; if(err != hipSuccess) { GGML_ABORT("HipVMM Failure: %s\n", hipGetErrorString(err)); }} #define __shfl_sync(mask, var, laneMask, width) __shfl(var, laneMask, width) +#define __shfl_up_sync(mask, var, laneMask, width) __shfl_up(var, laneMask, width) #define __shfl_xor_sync(mask, var, laneMask, width) __shfl_xor(var, laneMask, width) +#define __all_sync(mask, var) __all(var) +#define __any_sync(mask, var) __any(var) #define cublasCreate hipblasCreate #define cublasDestroy hipblasDestroy #define cublasGemmEx hipblasGemmEx @@ -139,7 +138,7 @@ #define CUBLAS_STATUS_INTERNAL_ERROR HIPBLAS_STATUS_INTERNAL_ERROR #define CUBLAS_STATUS_NOT_SUPPORTED HIPBLAS_STATUS_NOT_SUPPORTED -#if defined(__HIP_PLATFORM_AMD__) && HIP_VERSION >= 70000000 +#if HIP_VERSION >= 60500000 #define CUBLAS_COMPUTE_16F HIPBLAS_COMPUTE_16F #define CUBLAS_COMPUTE_32F HIPBLAS_COMPUTE_32F #define CUBLAS_COMPUTE_32F_FAST_16F HIPBLAS_COMPUTE_32F_FAST_16F @@ -151,26 +150,49 @@ #define CUBLAS_COMPUTE_32F_FAST_16F HIPBLAS_R_32F #define cublasComputeType_t hipblasDatatype_t #define cudaDataType_t hipblasDatatype_t -#endif +#endif // HIP_VERSION >= 6050000 + +#if !defined(__HIP_PLATFORM_AMD__) +#error "The HIP backend supports only AMD targets" +#endif // !defined(__HIP_PLATFORM_AMD__) #define __CUDA_ARCH__ 1300 -#if defined(__gfx803__) || defined(__gfx900__) || defined(__gfx906__) +#if defined(__gfx900__) || defined(__gfx906__) +#define GCN5 +#endif // defined(__gfx900__) || defined(__gfx906__) + +#if defined(__gfx803__) +#define GCN4 +#endif // defined(__gfx803__) + +#if defined(GCN5) || defined(GCN4) #define GCN -#endif +#endif // defined(GCN5) || defined(GCN4) -#if defined(__gfx908__) || defined(__gfx90a__) || defined(__gfx942__) -#define CDNA -#endif +#if defined(__gfx942__) +#define CDNA3 +#endif // defined(__gfx942__) + +#if defined(__gfx90a__) +#define CDNA2 +#endif // defined(__gfx90a__) + +#if defined(__gfx908__) +#define CDNA1 +#endif // defined(__gfx908__) + +#if defined(CDNA3) || defined(CDNA2) || defined(CDNA1) +#define CDNA // For the entire family +#endif // defined(CDNA3) || defined(CDNA2) || defined(CDNA1) #if defined(__GFX12__) #define RDNA4 -#endif +#endif // defined(__GFX12__) -#if defined(__gfx1100__) || defined(__gfx1101__) || defined(__gfx1102__) || defined(__gfx1103__) || \ - defined(__gfx1150__) || defined(__gfx1151__) +#if defined(__GFX11__) #define RDNA3 -#endif +#endif // defined(__GFX11__) #if defined(__gfx1030__) || defined(__gfx1031__) || defined(__gfx1032__) || defined(__gfx1033__) || \ defined(__gfx1034__) || defined(__gfx1035__) || defined(__gfx1036__) || defined(__gfx1037__) @@ -179,13 +201,18 @@ #if defined(__gfx1010__) || defined(__gfx1012__) #define RDNA1 -#endif +#endif // defined(__gfx1010__) || defined(__gfx1012__) + +#if defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) +#define RDNA // For the entire family +#endif // defined(RDNA4) || defined(RDNA3) || defined(RDNA2) || defined(RDNA1) #ifndef __has_builtin #define __has_builtin(x) 0 #endif -typedef hip_bfloat16 nv_bfloat16; +typedef __hip_bfloat16 nv_bfloat16; +typedef __hip_bfloat162 nv_bfloat162; typedef int8_t int8x4_t __attribute__((ext_vector_type(4))); typedef uint8_t uint8x4_t __attribute__((ext_vector_type(4))); @@ -236,17 +263,3 @@ static __device__ __forceinline__ unsign } return c; } - -#if defined(__HIP_PLATFORM_AMD__) && HIP_VERSION < 50600000 -// __shfl_xor() for half2 was added in ROCm 5.6 -static __device__ __forceinline__ half2 __shfl_xor(half2 var, int laneMask, int width) { - typedef union half2_b32 { - half2 val; - int b32; - } half2_b32_t; - half2_b32_t tmp; - tmp.val = var; - tmp.b32 = __shfl_xor(tmp.b32, laneMask, width); - return tmp.val; -} -#endif // defined(__HIP_PLATFORM_AMD__) && HIP_VERSION < 50600000 diff -pruN 5882+dfsg-2/ggml/src/ggml-cuda/vendors/musa.h 6641+dfsg-2/ggml/src/ggml-cuda/vendors/musa.h --- 5882+dfsg-2/ggml/src/ggml-cuda/vendors/musa.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-cuda/vendors/musa.h 2025-09-30 07:36:33.000000000 +0000 @@ -13,7 +13,7 @@ #define CUBLAS_OP_N MUBLAS_OP_N #define CUBLAS_OP_T MUBLAS_OP_T #define CUBLAS_STATUS_SUCCESS MUBLAS_STATUS_SUCCESS -#define CUBLAS_TF32_TENSOR_OP_MATH MUBLAS_MATH_MODE_DEFAULT +#define CUBLAS_TF32_TENSOR_OP_MATH MUBLAS_TENSOR_OP_MATH #define CUDA_R_16F MUSA_R_16F #define CUDA_R_16BF MUSA_R_16BF #define CUDA_R_32F MUSA_R_32F @@ -29,7 +29,7 @@ #define cublasSgemm mublasSgemm #define cublasStatus_t mublasStatus_t #define cublasOperation_t mublasOperation_t -#define cublasGetStatusString mublasStatus_to_string +#define cublasGetStatusString mublasGetStatusString #define cudaDataType_t musaDataType_t #define cudaDeviceCanAccessPeer musaDeviceCanAccessPeer #define cudaDeviceDisablePeerAccess musaDeviceDisablePeerAccess @@ -137,4 +137,5 @@ #define cudaStreamEndCapture musaStreamEndCapture #define cudaOccupancyMaxActiveBlocksPerMultiprocessor musaOccupancyMaxActiveBlocksPerMultiprocessor -typedef mt_bfloat16 nv_bfloat16; +typedef __mt_bfloat16 nv_bfloat16; +typedef __mt_bfloat162 nv_bfloat162; diff -pruN 5882+dfsg-2/ggml/src/ggml-hip/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-hip/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-hip/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-hip/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -46,8 +46,8 @@ if (GGML_HIP_ROCWMMA_FATTN) endif() endif() -if (${hip_VERSION} VERSION_LESS 5.5) - message(FATAL_ERROR "At least ROCM/HIP V5.5 is required") +if (${hip_VERSION} VERSION_LESS 6.1) + message(FATAL_ERROR "At least ROCM/HIP V6.1 is required") endif() message(STATUS "HIP and hipBLAS found") @@ -113,10 +113,18 @@ if (GGML_HIP_ROCWMMA_FATTN) add_compile_definitions(GGML_HIP_ROCWMMA_FATTN) endif() +if (NOT GGML_HIP_MMQ_MFMA) + add_compile_definitions(GGML_HIP_NO_MMQ_MFMA) +endif() + if (GGML_HIP_FORCE_ROCWMMA_FATTN_GFX12 OR ${hip_VERSION} VERSION_GREATER_EQUAL 7.0) add_compile_definitions(GGML_HIP_ROCWMMA_FATTN_GFX12) endif() +if (GGML_HIP_EXPORT_METRICS) + set(CMAKE_HIP_FLAGS "${CMAKE_HIP_FLAGS} -Rpass-analysis=kernel-resource-usage --save-temps") +endif() + if (NOT GGML_CUDA_FA) add_compile_definitions(GGML_CUDA_NO_FA) endif() diff -pruN 5882+dfsg-2/ggml/src/ggml-impl.h 6641+dfsg-2/ggml/src/ggml-impl.h --- 5882+dfsg-2/ggml/src/ggml-impl.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-impl.h 2025-09-30 07:36:33.000000000 +0000 @@ -73,6 +73,35 @@ static inline int ggml_up(int n, int m) return (n + m - 1) & ~(m - 1); } +// TODO: move to ggml.h? (won't be able to inline) +static bool ggml_are_same_layout(const struct ggml_tensor * a, const struct ggml_tensor * b) { + if (a->type != b->type) { + return false; + } + for (int i = 0; i < GGML_MAX_DIMS; i++) { + if (a->ne[i] != b->ne[i]) { + return false; + } + if (a->nb[i] != b->nb[i]) { + return false; + } + } + return true; +} + +static bool ggml_op_is_empty(enum ggml_op op) { + switch (op) { + case GGML_OP_NONE: + case GGML_OP_RESHAPE: + case GGML_OP_TRANSPOSE: + case GGML_OP_VIEW: + case GGML_OP_PERMUTE: + return true; + default: + return false; + } +} + // // logging // @@ -313,6 +342,10 @@ struct ggml_cgraph { // if you need the gradients, get them from the original graph struct ggml_cgraph ggml_graph_view(struct ggml_cgraph * cgraph, int i0, int i1); +// ggml-alloc.c: true if the operation can reuse memory from its sources +GGML_API bool ggml_op_can_inplace(enum ggml_op op); + + // Memory allocation GGML_API void * ggml_aligned_malloc(size_t size); @@ -394,6 +427,67 @@ static inline ggml_fp16_t ggml_compute_f #define GGML_FP16_TO_FP32(x) GGML_COMPUTE_FP16_TO_FP32(x) #define GGML_FP32_TO_FP16(x) GGML_COMPUTE_FP32_TO_FP16(x) +static inline float ggml_e8m0_to_fp32(uint8_t x) { + uint32_t bits; // Stores the raw bit representation of the float + + // Handle special case for minimum exponent (denormalized float) + if (x == 0) { + // Bit pattern for 2^(-127): + // - Sign bit: 0 (positive) + // - Exponent: 0 (denormalized number) + // - Mantissa: 0x400000 (0.5 in fractional form) + // Value = 0.5 * 2^(-126) = 2^(-127) + bits = 0x00400000; + } + // note: disabled as we don't need to handle NaNs + //// Handle special case for NaN (all bits set) + //else if (x == 0xFF) { + // // Standard quiet NaN pattern: + // // - Sign bit: 0 + // // - Exponent: all 1s (0xFF) + // // - Mantissa: 0x400000 (quiet NaN flag) + // bits = 0x7FC00000; + //} + // Normalized values (most common case) + else { + // Construct normalized float by shifting exponent into position: + // - Exponent field: 8 bits (positions 30-23) + // - Mantissa: 0 (implicit leading 1) + // Value = 2^(x - 127) + bits = (uint32_t) x << 23; + } + + float result; // Final float value + // Safely reinterpret bit pattern as float without type-punning issues + memcpy(&result, &bits, sizeof(float)); + return result; +} + +// Equal to ggml_e8m0_to_fp32/2 +// Useful with MXFP4 quantization since the E0M2 values are doubled +static inline float ggml_e8m0_to_fp32_half(uint8_t x) { + uint32_t bits; + + // For x < 2: use precomputed denormal patterns + if (x < 2) { + // 0x00200000 = 2^(-128), 0x00400000 = 2^(-127) + bits = 0x00200000 << x; + } + // For x >= 2: normalized exponent adjustment + else { + // 0.5 * 2^(x-127) = 2^(x-128) = normalized with exponent (x-1) + bits = (uint32_t)(x - 1) << 23; + } + // Note: NaNs are not handled here + + float result; + memcpy(&result, &bits, sizeof(float)); + return result; +} + +#define GGML_E8M0_TO_FP32(x) ggml_e8m0_to_fp32(x) +#define GGML_E8M0_TO_FP32_HALF(x) ggml_e8m0_to_fp32_half(x) + /** * Converts brain16 to float32. * @@ -493,27 +587,27 @@ static inline bool ggml_node_has_n_uses( return true; } -// Returns true if nodes [i, i+ops.size()) are the sequence of ggml_ops in ops[] +// Returns true if nodes with indices { node_idxs } are the sequence of ggml_ops in ops[] // and are fusable. Nodes are considered fusable according to this function if: // - all nodes except the last have only one use and are not views/outputs (see ggml_node_has_N_uses). // - all nodes except the last are a src of the following node. // - all nodes are the same shape. // TODO: Consider allowing GGML_OP_NONE nodes in between -static inline bool ggml_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, const enum ggml_op * ops, int num_ops) { - if (node_idx + num_ops > cgraph->n_nodes) { - return false; - } - +static inline bool ggml_can_fuse_ext(const struct ggml_cgraph * cgraph, const int * node_idxs, const enum ggml_op * ops, int num_ops) { for (int i = 0; i < num_ops; ++i) { - struct ggml_tensor * node = cgraph->nodes[node_idx + i]; + if (node_idxs[i] >= cgraph->n_nodes) { + return false; + } + + struct ggml_tensor * node = cgraph->nodes[node_idxs[i]]; if (node->op != ops[i]) { return false; } - if (i < num_ops - 1 && !ggml_node_has_n_uses(cgraph, node_idx + i, 1)) { + if (i < num_ops - 1 && !ggml_node_has_n_uses(cgraph, node_idxs[i], 1)) { return false; } if (i > 0) { - struct ggml_tensor * prev = cgraph->nodes[node_idx + i - 1]; + struct ggml_tensor * prev = cgraph->nodes[node_idxs[i - 1]]; if (node->src[0] != prev && node->src[1] != prev) { return false; } @@ -525,6 +619,22 @@ static inline bool ggml_can_fuse(const s return true; } +// same as above, for sequential indices starting at node_idx +static inline bool ggml_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, const enum ggml_op * ops, int num_ops) { + assert(num_ops < 32); + + if (node_idx + num_ops > cgraph->n_nodes) { + return false; + } + + int idxs[32]; + for (int i = 0; i < num_ops; ++i) { + idxs[i] = node_idx + i; + } + + return ggml_can_fuse_ext(cgraph, idxs, ops, num_ops); +} + #ifdef __cplusplus } #endif diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-metal/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-metal/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -5,7 +5,12 @@ find_library(METALKIT_FRAMEWORK MetalKit message(STATUS "Metal framework found") ggml_add_backend_library(ggml-metal - ggml-metal.m + ggml-metal.cpp + ggml-metal-device.m + ggml-metal-device.cpp + ggml-metal-common.cpp + ggml-metal-context.m + ggml-metal-ops.cpp ) target_link_libraries(ggml-metal PRIVATE @@ -18,10 +23,6 @@ if (GGML_METAL_NDEBUG) add_compile_definitions(GGML_METAL_NDEBUG) endif() -if (GGML_METAL_USE_BF16) - add_compile_definitions(GGML_METAL_USE_BF16) -endif() - # copy metal files to bin directory configure_file(../ggml-common.h ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/ggml-common.h COPYONLY) configure_file(ggml-metal.metal ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/ggml-metal.metal COPYONLY) diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.cpp 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.cpp --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,446 @@ +#include "ggml-metal-common.h" + +#include "ggml-impl.h" +#include "ggml-backend-impl.h" + +#include + +// represents a memory range (i.e. an interval from a starting address p0 to an ending address p1 in a given buffer pb) +// the type indicates whether it is a source range (i.e. ops read data from it) or a destination range (i.e. ops write data to it) +struct ggml_mem_range { + uint64_t pb; // buffer id + + uint64_t p0; // begin + uint64_t p1; // end + + ggml_mem_range_type pt; +}; + +struct ggml_mem_ranges { + std::vector ranges; + + int debug = 0; +}; + +ggml_mem_ranges_t ggml_mem_ranges_init(int debug) { + auto * res = new ggml_mem_ranges; + + res->ranges.reserve(256); + res->debug = debug; + + return res; +} + +void ggml_mem_ranges_free(ggml_mem_ranges_t mrs) { + delete mrs; +} + +void ggml_mem_ranges_reset(ggml_mem_ranges_t mrs) { + mrs->ranges.clear(); +} + +static bool ggml_mem_ranges_add(ggml_mem_ranges_t mrs, ggml_mem_range mr) { + mrs->ranges.push_back(mr); + + return true; +} + +static ggml_mem_range ggml_mem_range_from_tensor(const ggml_tensor * tensor, ggml_mem_range_type pt) { + // always use the base tensor + tensor = tensor->view_src ? tensor->view_src : tensor; + + GGML_ASSERT(!tensor->view_src); + + ggml_mem_range mr; + + if (tensor->buffer) { + // when the tensor is allocated, use the actual memory address range in the buffer + // + // take the actual allocated size with ggml_backend_buft_get_alloc_size() + // this can be larger than the tensor size if the buffer type allocates extra memory + // ref: https://github.com/ggml-org/llama.cpp/pull/15966 + mr = { + /*.pb =*/ (uint64_t) tensor->buffer, + /*.p0 =*/ (uint64_t) tensor->data, + /*.p1 =*/ (uint64_t) tensor->data + ggml_backend_buft_get_alloc_size(tensor->buffer->buft, tensor), + /*.pt =*/ pt, + }; + } else { + // otherwise, the pointer address is used as an unique id of the memory ranges + // that the tensor will be using when it is allocated + mr = { + /*.pb =*/ (uint64_t) tensor, + /*.p0 =*/ 0, // + /*.p1 =*/ 1024, // [0, 1024) is a dummy range, not used + /*.pt =*/ pt, + }; + }; + + return mr; +} + +static ggml_mem_range ggml_mem_range_from_tensor_src(const ggml_tensor * tensor) { + return ggml_mem_range_from_tensor(tensor, MEM_RANGE_TYPE_SRC); +} + +static ggml_mem_range ggml_mem_range_from_tensor_dst(const ggml_tensor * tensor) { + return ggml_mem_range_from_tensor(tensor, MEM_RANGE_TYPE_DST); +} + +static bool ggml_mem_ranges_add_src(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + GGML_ASSERT(tensor); + + ggml_mem_range mr = ggml_mem_range_from_tensor_src(tensor); + + if (mrs->debug > 2) { + GGML_LOG_DEBUG("%s: add src range buf=%lld, [%lld, %lld)\n", __func__, mr.pb, mr.p0, mr.p1); + } + + return ggml_mem_ranges_add(mrs, mr); +} + +static bool ggml_mem_ranges_add_dst(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + GGML_ASSERT(tensor); + + ggml_mem_range mr = ggml_mem_range_from_tensor_dst(tensor); + + if (mrs->debug > 2) { + GGML_LOG_DEBUG("%s: add dst range buf=%lld, [%lld, %lld)\n", __func__, mr.pb, mr.p0, mr.p1); + } + + return ggml_mem_ranges_add(mrs, mr); +} + +bool ggml_mem_ranges_add(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + for (int i = 0; i < GGML_MAX_DIMS; i++) { + if (tensor->src[i]) { + ggml_mem_ranges_add_src(mrs, tensor->src[i]); + } + } + + return ggml_mem_ranges_add_dst(mrs, tensor); +} + +static bool ggml_mem_ranges_check(ggml_mem_ranges_t mrs, ggml_mem_range mr) { + for (size_t i = 0; i < mrs->ranges.size(); i++) { + const auto & cmp = mrs->ranges[i]; + + // two memory ranges cannot intersect if they are in different buffers + if (mr.pb != cmp.pb) { + continue; + } + + // intersecting source ranges are allowed + if (mr.pt == MEM_RANGE_TYPE_SRC && cmp.pt == MEM_RANGE_TYPE_SRC) { + continue; + } + + if (mr.p0 < cmp.p1 && mr.p1 >= cmp.p0) { + if (mrs->debug > 2) { + GGML_LOG_DEBUG("%s: the %s range buf=%lld, [%lld, %lld) overlaps with a previous %s range buf=%lld, [%lld, %lld)\n", + __func__, + mr.pt == MEM_RANGE_TYPE_SRC ? "src" : "dst", + mr.pb, mr.p0, mr.p1, + cmp.pt == MEM_RANGE_TYPE_SRC ? "src" : "dst", + cmp.pb, cmp.p0, cmp.p1); + } + + return false; + } + } + + return true; +} + +static bool ggml_mem_ranges_check_src(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + GGML_ASSERT(tensor); + + ggml_mem_range mr = ggml_mem_range_from_tensor_src(tensor); + + const bool res = ggml_mem_ranges_check(mrs, mr); + + return res; +} + +static bool ggml_mem_ranges_check_dst(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + GGML_ASSERT(tensor); + + ggml_mem_range mr = ggml_mem_range_from_tensor_dst(tensor); + + const bool res = ggml_mem_ranges_check(mrs, mr); + + return res; +} + +bool ggml_mem_ranges_check(ggml_mem_ranges_t mrs, const ggml_tensor * tensor) { + for (int i = 0; i < GGML_MAX_DIMS; i++) { + if (tensor->src[i]) { + if (!ggml_mem_ranges_check_src(mrs, tensor->src[i])) { + return false; + } + } + } + + return ggml_mem_ranges_check_dst(mrs, tensor); +} + +struct node_info { + ggml_tensor * node; + + std::vector fused; + + ggml_op op() const { + return node->op; + } + + const ggml_tensor * dst() const { + return fused.empty() ? node : fused.back(); + } + + bool is_empty() const { + return ggml_op_is_empty(node->op); + } + + void add_fused(ggml_tensor * t) { + fused.push_back(t); + } +}; + +static std::vector ggml_metal_graph_optimize_reorder(const std::vector & nodes) { + // helper to add node src and dst ranges + const auto & h_add = [](ggml_mem_ranges_t mrs, const node_info & node) { + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (node.node->src[i]) { + if (!ggml_mem_ranges_add_src(mrs, node.node->src[i])) { + return false; + } + } + } + + // keep track of the sources of the fused nodes as well + for (const auto * fused : node.fused) { + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (fused->src[i]) { + if (!ggml_mem_ranges_add_src(mrs, fused->src[i])) { + return false; + } + } + } + } + + return ggml_mem_ranges_add_dst(mrs, node.dst()); + }; + + // helper to check if a node can run concurrently with the existing set of nodes + const auto & h_check = [](ggml_mem_ranges_t mrs, const node_info & node) { + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (node.node->src[i]) { + if (!ggml_mem_ranges_check_src(mrs, node.node->src[i])) { + return false; + } + } + } + + for (const auto * fused : node.fused) { + for (int i = 0; i < GGML_MAX_SRC; i++) { + if (fused->src[i]) { + if (!ggml_mem_ranges_check_src(mrs, fused->src[i])) { + return false; + } + } + } + } + + return ggml_mem_ranges_check_dst(mrs, node.dst()); + }; + + // perform reorders only across these types of ops + // can be expanded when needed + const auto & h_safe = [](ggml_op op) { + switch (op) { + case GGML_OP_MUL_MAT: + case GGML_OP_MUL_MAT_ID: + case GGML_OP_ROPE: + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + case GGML_OP_GROUP_NORM: + case GGML_OP_SUM_ROWS: + case GGML_OP_MUL: + case GGML_OP_ADD: + case GGML_OP_DIV: + case GGML_OP_GLU: + case GGML_OP_SCALE: + case GGML_OP_GET_ROWS: + case GGML_OP_CPY: + case GGML_OP_SET_ROWS: + return true; + default: + return ggml_op_is_empty(op); + } + }; + + const int n = nodes.size(); + + std::vector res; + res.reserve(n); + + std::vector used(n, false); + + // the memory ranges for the set of currently concurrent nodes + ggml_mem_ranges_t mrs0 = ggml_mem_ranges_init(0); + + // the memory ranges for the set of nodes that haven't been processed yet, when looking forward for a node to reorder + ggml_mem_ranges_t mrs1 = ggml_mem_ranges_init(0); + + for (int i0 = 0; i0 < n; i0++) { + if (used[i0]) { + continue; + } + + const auto & node0 = nodes[i0]; + + // the node is not concurrent with the existing concurrent set, so we have to "put a barrier" (i.e reset mrs0) + // but before we do that, look forward for some other nodes that can be added to the concurrent set mrs0 + // + // note: we can always add empty nodes to the concurrent set as they don't read nor write anything + if (!node0.is_empty() && !h_check(mrs0, node0)) { + // this will hold the set of memory ranges from the nodes that haven't been processed yet + // if a node is not concurrent with this set, we cannot reorder it + ggml_mem_ranges_reset(mrs1); + + // initialize it with the current node + h_add(mrs1, node0); + + // that many nodes forward to search for a concurrent node + constexpr int N_FORWARD = 8; + + for (int i1 = i0 + 1; i1 < i0 + N_FORWARD && i1 < n; i1++) { + if (used[i1]) { + continue; + } + + const auto & node1 = nodes[i1]; + + // disallow reordering of certain ops + if (!h_safe(node1.op())) { + break; + } + + const bool is_empty = node1.is_empty(); + + // to reorder a node and add it to the concurrent set, it has to be: + // + empty or concurrent with all nodes in the existing concurrent set (mrs0) + // + concurrent with all nodes prior to it that haven't been processed yet (mrs1) + if ((is_empty || h_check(mrs0, node1)) && h_check(mrs1, node1)) { + // add the node to the existing concurrent set (i.e. reorder it for early execution) + h_add(mrs0, node1); + res.push_back(i1); + + // mark as used, so we skip re-processing it later + used[i1] = true; + } else { + // expand the set of nodes that haven't been processed yet + h_add(mrs1, node1); + } + } + + // finalize the concurrent set and begin a new one + ggml_mem_ranges_reset(mrs0); + } + + // expand the concurrent set with the current node + { + h_add(mrs0, node0); + res.push_back(i0); + } + } + + ggml_mem_ranges_free(mrs0); + ggml_mem_ranges_free(mrs1); + + return res; +} + +void ggml_graph_optimize(ggml_cgraph * gf) { + constexpr int MAX_FUSE = 16; + + const int n = gf->n_nodes; + + enum ggml_op ops[MAX_FUSE]; + + std::vector nodes; + nodes.reserve(gf->n_nodes); + + // fuse nodes: + // we don't want to make reorders that break fusing, so we first pack all fusable tensors + // and perform the reorder over the fused nodes. after the reorder is done, we unfuse + for (int i = 0; i < n; i++) { + node_info node = { + /*.node =*/ gf->nodes[i], + /*.fused =*/ {}, + }; + + // fuse only ops that start with these operations + // can be expanded when needed + if (node.op() == GGML_OP_ADD || + node.op() == GGML_OP_NORM || + node.op() == GGML_OP_RMS_NORM) { + ops[0] = node.op(); + + int f = i + 1; + while (f < n && f < i + MAX_FUSE) { + // conservatively allow fusing only these ops + // can be expanded when needed + if (gf->nodes[f]->op != GGML_OP_ADD && + gf->nodes[f]->op != GGML_OP_MUL && + gf->nodes[f]->op != GGML_OP_NORM && + gf->nodes[f]->op != GGML_OP_RMS_NORM) { + break; + } + ops[f - i] = gf->nodes[f]->op; + f++; + } + + f -= i; + for (; f > 1; f--) { + if (ggml_can_fuse(gf, i, ops, f)) { + break; + } + } + + // add the fused tensors into the node info so we can unfuse them later + for (int k = 1; k < f; k++) { + ++i; + + // the .dst() becomes the last fused tensor + node.add_fused(gf->nodes[i]); + } + } + + nodes.push_back(std::move(node)); + } + +#if 1 + // reorder to improve concurrency + const auto order = ggml_metal_graph_optimize_reorder(nodes); +#else + std::vector order(nodes.size()); + for (size_t i = 0; i < nodes.size(); i++) { + order[i] = i; + } +#endif + + // unfuse + { + int j = 0; + for (const auto i : order) { + const auto & node = nodes[i]; + + gf->nodes[j++] = node.node; + + for (auto * fused : node.fused) { + gf->nodes[j++] = fused; + } + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.h 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.h --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-common.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,52 @@ +// helper functions for ggml-metal that are too difficult to implement in Objective-C + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct ggml_tensor; +struct ggml_cgraph; + +enum ggml_mem_range_type { + MEM_RANGE_TYPE_SRC = 0, + MEM_RANGE_TYPE_DST = 1, +}; + +// a helper object that can be used for reordering operations to improve concurrency +// +// the fundamental idea is that a set of tasks (either ggml ops, or something else) can run concurrently if they +// don't write to a memory that is being read by another task or written to by another task in the set +// +// with this structure, we can add tasks to the set, setting memory constraints. we can also check if a new task +// can be added to the set without violating the constraints (i.e. if it can be executed concurrently with the +// tasks already in the set) +// +typedef struct ggml_mem_ranges * ggml_mem_ranges_t; + +ggml_mem_ranges_t ggml_mem_ranges_init(int debug); +void ggml_mem_ranges_free(ggml_mem_ranges_t mrs); + +// remove all ranges from the set +void ggml_mem_ranges_reset(ggml_mem_ranges_t mrs); + +// add src or dst ranges to track +bool ggml_mem_ranges_add(ggml_mem_ranges_t mrs, const struct ggml_tensor * tensor); + +// return false if: +// - new src range overlaps with any existing dst range +// - new dst range overlaps with any existing range (src or dst) +bool ggml_mem_ranges_check(ggml_mem_ranges_t mrs, const struct ggml_tensor * tensor); + +// reorder the nodes in the graph to improve concurrency, while respecting fusion +// +// note: this implementation is generic and not specific to metal +// if it proves to work well, we can start using it for other backends in the future +void ggml_graph_optimize(struct ggml_cgraph * gf); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.h 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.h --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,33 @@ +#pragma once + +#include "ggml-metal-device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// +// backend context +// + +typedef struct ggml_metal * ggml_metal_t; + +ggml_metal_t ggml_metal_init(ggml_metal_device_t dev); +void ggml_metal_free(ggml_metal_t ctx); + +void ggml_metal_synchronize(ggml_metal_t ctx); + +void ggml_metal_set_tensor_async(ggml_metal_t ctx, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size); +void ggml_metal_get_tensor_async(ggml_metal_t ctx, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size); + +enum ggml_status ggml_metal_graph_compute (ggml_metal_t ctx, struct ggml_cgraph * gf); +void ggml_metal_graph_optimize(ggml_metal_t ctx, struct ggml_cgraph * gf); + +void ggml_metal_set_n_cb (ggml_metal_t ctx, int n_cb); +void ggml_metal_set_abort_callback (ggml_metal_t ctx, ggml_abort_callback abort_callback, void * user_data); +bool ggml_metal_supports_family (ggml_metal_t ctx, int family); +void ggml_metal_capture_next_compute(ggml_metal_t ctx); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.m 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.m --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.m 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-context.m 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,600 @@ +#import "ggml-metal-context.h" + +#import "ggml-impl.h" +#import "ggml-backend-impl.h" + +#import "ggml-metal-impl.h" +#import "ggml-metal-common.h" +#import "ggml-metal-ops.h" + +#import + +#import + +#undef MIN +#undef MAX +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +// max number of MTLCommandBuffer used to submit a graph for processing +#define GGML_METAL_MAX_COMMAND_BUFFERS 8 + +struct ggml_metal_command_buffer { + id obj; +}; + +struct ggml_metal { + id device; + id queue; // currently a pointer to the device queue, but might become separate queue [TAG_QUEUE_PER_BACKEND] + + ggml_metal_device_t dev; + ggml_metal_library_t lib; + + dispatch_queue_t d_queue; + + // additional, inference-time compiled pipelines + ggml_metal_pipelines_t pipelines_ext; + + bool use_bfloat; + bool use_fusion; + bool use_concurrency; + bool use_graph_optimize; + + int debug_graph; + int debug_fusion; + + // how many times a given op was fused + uint64_t fuse_cnt[GGML_OP_COUNT]; + + // capture state + bool capture_next_compute; + bool capture_started; + + id capture_scope; + + // command buffer state + int n_cb; // number of extra threads used to submit the command buffers + int n_nodes_0; // number of nodes submitted by the main thread + int n_nodes_1; // remaining number of nodes submitted by the n_cb threads + int n_nodes_per_cb; + + struct ggml_cgraph * gf; + + // the callback given to the thread pool + void (^encode_async)(size_t ith); + + // n_cb command buffers + 1 used by the main thread + struct ggml_metal_command_buffer cmd_bufs[GGML_METAL_MAX_COMMAND_BUFFERS + 1]; + + // extra command buffers for things like getting, setting and copying tensors + NSMutableArray * cmd_bufs_ext; + + // the last command buffer queued into the Metal queue with operations relevant to the current Metal backend + id cmd_buf_last; + + // abort ggml_metal_graph_compute if callback returns true + ggml_abort_callback abort_callback; + void * abort_callback_data; +}; + +ggml_metal_t ggml_metal_init(ggml_metal_device_t dev) { + GGML_LOG_INFO("%s: allocating\n", __func__); + +#if TARGET_OS_OSX && !GGML_METAL_NDEBUG + // Show all the Metal device instances in the system + NSArray * devices = MTLCopyAllDevices(); + for (id device in devices) { + GGML_LOG_INFO("%s: found device: %s\n", __func__, [[device name] UTF8String]); + } + [devices release]; // since it was created by a *Copy* C method +#endif + + // init context + ggml_metal_t res = calloc(1, sizeof(struct ggml_metal)); + + res->device = ggml_metal_device_get_obj(dev); + + GGML_LOG_INFO("%s: picking default device: %s\n", __func__, [[res->device name] UTF8String]); + + // TODO: would it be better to have one queue for the backend and one queue for the device? + // the graph encoders and async ops would use the backend queue while the sync ops would use the device queue? + //res->queue = [device newCommandQueue]; [TAG_QUEUE_PER_BACKEND] + res->queue = ggml_metal_device_get_queue(dev); + if (res->queue == nil) { + GGML_LOG_ERROR("%s: error: failed to create command queue\n", __func__); + return NULL; + } + + res->dev = dev; + res->lib = ggml_metal_device_get_library(dev); + if (res->lib == NULL) { + GGML_LOG_WARN("%s: the device does not have a precompiled Metal library - this is unexpected\n", __func__); + GGML_LOG_WARN("%s: will try to compile it on the fly\n", __func__); + + res->lib = ggml_metal_library_init(dev); + if (res->lib == NULL) { + GGML_LOG_ERROR("%s: error: failed to initialize the Metal library\n", __func__); + + free(res); + + return NULL; + } + } + + const struct ggml_metal_device_props * props_dev = ggml_metal_device_get_props(dev); + + res->d_queue = dispatch_queue_create("ggml-metal", DISPATCH_QUEUE_CONCURRENT); + + res->use_bfloat = props_dev->has_bfloat; + res->use_fusion = getenv("GGML_METAL_FUSION_DISABLE") == nil; + res->use_concurrency = getenv("GGML_METAL_CONCURRENCY_DISABLE") == nil; + + { + const char * val = getenv("GGML_METAL_GRAPH_DEBUG"); + res->debug_graph = val ? atoi(val) : 0; + } + + { + const char * val = getenv("GGML_METAL_FUSION_DEBUG"); + res->debug_fusion = val ? atoi(val) : 0; + } + + res->use_graph_optimize = true; + + if (getenv("GGML_METAL_GRAPH_OPTIMIZE_DISABLE") != NULL) { + res->use_graph_optimize = false; + } + + memset(res->fuse_cnt, 0, sizeof(res->fuse_cnt)); + + GGML_LOG_INFO("%s: use bfloat = %s\n", __func__, res->use_bfloat ? "true" : "false"); + GGML_LOG_INFO("%s: use fusion = %s\n", __func__, res->use_fusion ? "true" : "false"); + GGML_LOG_INFO("%s: use concurrency = %s\n", __func__, res->use_concurrency ? "true" : "false"); + GGML_LOG_INFO("%s: use graph optimize = %s\n", __func__, res->use_graph_optimize ? "true" : "false"); + + res->capture_next_compute = false; + res->capture_started = false; + res->capture_scope = nil; + + res->gf = nil; + res->encode_async = nil; + for (int i = 0; i < GGML_METAL_MAX_COMMAND_BUFFERS; ++i) { + res->cmd_bufs[i].obj = nil; + } + + res->cmd_bufs_ext = [[NSMutableArray alloc] init]; + + res->cmd_buf_last = nil; + + res->pipelines_ext = ggml_metal_pipelines_init(); + + return res; +} + +void ggml_metal_free(ggml_metal_t ctx) { + GGML_LOG_INFO("%s: deallocating\n", __func__); + + for (int i = 0; i < GGML_METAL_MAX_COMMAND_BUFFERS; ++i) { + if (ctx->cmd_bufs[i].obj) { + [ctx->cmd_bufs[i].obj release]; + } + } + + for (int i = 0; i < (int) ctx->cmd_bufs_ext.count; ++i) { + if (ctx->cmd_bufs_ext[i]) { + [ctx->cmd_bufs_ext[i] release]; + } + } + + [ctx->cmd_bufs_ext removeAllObjects]; + [ctx->cmd_bufs_ext release]; + + if (ctx->pipelines_ext) { + ggml_metal_pipelines_free(ctx->pipelines_ext); + ctx->pipelines_ext = nil; + } + + if (ctx->debug_fusion > 0) { + GGML_LOG_DEBUG("%s: fusion stats:\n", __func__); + for (int i = 0; i < GGML_OP_COUNT; i++) { + if (ctx->fuse_cnt[i] == 0) { + continue; + } + + // note: cannot use ggml_log here + GGML_LOG_DEBUG("%s: - %s: %" PRIu64 "\n", __func__, ggml_op_name((enum ggml_op) i), ctx->fuse_cnt[i]); + } + } + + Block_release(ctx->encode_async); + + //[ctx->queue release]; // [TAG_QUEUE_PER_BACKEND] + + dispatch_release(ctx->d_queue); + + free(ctx); +} + +void ggml_metal_synchronize(ggml_metal_t ctx) { + // wait for any backend operations to finish + if (ctx->cmd_buf_last) { + [ctx->cmd_buf_last waitUntilCompleted]; + ctx->cmd_buf_last = nil; + } + + // check status of all command buffers + { + const int n_cb = ctx->n_cb; + + for (int cb_idx = 0; cb_idx <= n_cb; ++cb_idx) { + id cmd_buf = ctx->cmd_bufs[cb_idx].obj; + if (!cmd_buf) { + continue; + } + + MTLCommandBufferStatus status = [cmd_buf status]; + if (status != MTLCommandBufferStatusCompleted) { + GGML_LOG_ERROR("%s: error: command buffer %d failed with status %d\n", __func__, cb_idx, (int) status); + if (status == MTLCommandBufferStatusError) { + GGML_LOG_ERROR("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); + } + GGML_ABORT("fatal error"); + } + } + } + + // release any completed extra command buffers + if (ctx->cmd_bufs_ext.count > 0) { + for (size_t i = 0; i < ctx->cmd_bufs_ext.count; ++i) { + id cmd_buf = ctx->cmd_bufs_ext[i]; + + MTLCommandBufferStatus status = [cmd_buf status]; + if (status != MTLCommandBufferStatusCompleted) { + GGML_LOG_ERROR("%s: error: command buffer %d failed with status %d\n", __func__, (int) i, (int) status); + if (status == MTLCommandBufferStatusError) { + GGML_LOG_ERROR("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); + } + GGML_ABORT("fatal error"); + } + + [cmd_buf release]; + } + + [ctx->cmd_bufs_ext removeAllObjects]; + } +} + +static struct ggml_metal_buffer_id ggml_metal_get_buffer_id(const struct ggml_tensor * t) { + if (!t) { + return (struct ggml_metal_buffer_id) { nil, 0 }; + } + + ggml_backend_buffer_t buffer = t->view_src ? t->view_src->buffer : t->buffer; + + return ggml_metal_buffer_get_id(buffer->context, t); +} + +void ggml_metal_set_tensor_async(ggml_metal_t ctx, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + @autoreleasepool { + // wrap the source data into a Metal buffer + id buf_src = [ctx->device newBufferWithBytes:data + length:size + options:MTLResourceStorageModeShared]; + + GGML_ASSERT(buf_src); + + struct ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(tensor); + if (bid_dst.metal == nil) { + GGML_ABORT("%s: failed to find buffer for tensor '%s'\n", __func__, tensor->name); + } + + bid_dst.offs += offset; + + // queue the copy operation into the queue of the Metal context + // this will be queued at the end, after any currently ongoing GPU operations + id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder copyFromBuffer:buf_src + sourceOffset:0 + toBuffer:bid_dst.metal + destinationOffset:bid_dst.offs + size:size]; + + [encoder endEncoding]; + [cmd_buf commit]; + + // do not wait here for completion + //[cmd_buf waitUntilCompleted]; + + // instead, remember a reference to the command buffer and wait for it later if needed + [ctx->cmd_bufs_ext addObject:cmd_buf]; + ctx->cmd_buf_last = cmd_buf; + + [cmd_buf retain]; + } +} + +void ggml_metal_get_tensor_async(ggml_metal_t ctx, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size) { + @autoreleasepool { + id buf_dst = [ctx->device newBufferWithBytesNoCopy:data + length:size + options:MTLResourceStorageModeShared + deallocator:nil]; + + GGML_ASSERT(buf_dst); + + struct ggml_metal_buffer_id bid_src = ggml_metal_get_buffer_id(tensor); + if (bid_src.metal == nil) { + GGML_ABORT("%s: failed to find buffer for tensor '%s'\n", __func__, tensor->name); + } + + bid_src.offs += offset; + + // queue the copy operation into the queue of the Metal context + // this will be queued at the end, after any currently ongoing GPU operations + id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder copyFromBuffer:bid_src.metal + sourceOffset:bid_src.offs + toBuffer:buf_dst + destinationOffset:0 + size:size]; + + [encoder endEncoding]; + [cmd_buf commit]; + + // do not wait here for completion + //[cmd_buf waitUntilCompleted]; + + // instead, remember a reference to the command buffer and wait for it later if needed + [ctx->cmd_bufs_ext addObject:cmd_buf]; + ctx->cmd_buf_last = cmd_buf; + + [cmd_buf retain]; + } +} + +enum ggml_status ggml_metal_graph_compute(ggml_metal_t ctx, struct ggml_cgraph * gf) { + // number of nodes encoded by the main thread (empirically determined) + const int n_main = 64; + + // number of threads in addition to the main thread + const int n_cb = ctx->n_cb; + + // submit the ggml compute graph to the GPU by creating command buffers and encoding the ops in them + // the first n_nodes_0 are encoded and submitted for processing directly by the calling thread + // while these nodes are processing, we start n_cb threads to enqueue the rest of the nodes + // each thread creates it's own command buffer and enqueues the ops in parallel + // + // tests on M1 Pro and M2 Ultra using LLaMA models, show that optimal values for n_cb are 1 or 2 + + @autoreleasepool { + ctx->gf = gf; + + ctx->n_nodes_0 = MIN(n_main, gf->n_nodes); + ctx->n_nodes_1 = gf->n_nodes - ctx->n_nodes_0; + + ctx->n_nodes_per_cb = (ctx->n_nodes_1 + ctx->n_cb - 1) / ctx->n_cb; + + const bool use_capture = ctx->capture_next_compute; + if (use_capture) { + ctx->capture_next_compute = false; + + // make sure all previous computations have finished before starting the capture + if (ctx->cmd_buf_last) { + [ctx->cmd_buf_last waitUntilCompleted]; + ctx->cmd_buf_last = nil; + } + + if (!ctx->capture_started) { + // create capture scope + ctx->capture_scope = [[MTLCaptureManager sharedCaptureManager] newCaptureScopeWithDevice:ctx->device]; + + MTLCaptureDescriptor * descriptor = [MTLCaptureDescriptor new]; + descriptor.captureObject = ctx->capture_scope; + descriptor.destination = MTLCaptureDestinationGPUTraceDocument; + descriptor.outputURL = [NSURL fileURLWithPath:[NSString stringWithFormat:@"/tmp/perf-metal.gputrace"]]; + + NSError * error = nil; + if (![[MTLCaptureManager sharedCaptureManager] startCaptureWithDescriptor:descriptor error:&error]) { + GGML_LOG_ERROR("%s: error: unable to start capture '%s'\n", __func__, [[error localizedDescription] UTF8String]); + } else { + [ctx->capture_scope beginScope]; + ctx->capture_started = true; + } + } + } + + // the main thread commits the first few commands immediately + // cmd_buf[n_cb] + { + id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; + [cmd_buf retain]; + + if (ctx->cmd_bufs[n_cb].obj) { + [ctx->cmd_bufs[n_cb].obj release]; + } + ctx->cmd_bufs[n_cb].obj = cmd_buf; + + [cmd_buf enqueue]; + + ctx->encode_async(n_cb); + } + + // remember the command buffer for the next iteration + ctx->cmd_buf_last = ctx->cmd_bufs[n_cb].obj; + + // prepare the rest of the command buffers asynchronously (optional) + // cmd_buf[0.. n_cb) + for (int cb_idx = 0; cb_idx < n_cb; ++cb_idx) { + id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; + [cmd_buf retain]; + + if (ctx->cmd_bufs[cb_idx].obj) { + [ctx->cmd_bufs[cb_idx].obj release]; + } + ctx->cmd_bufs[cb_idx].obj = cmd_buf; + + // always enqueue the first two command buffers + // enqueue all of the command buffers if we don't need to abort + if (cb_idx < 2 || ctx->abort_callback == NULL) { + [cmd_buf enqueue]; + + // update the pointer to the last queued command buffer + // this is needed to implement synchronize() + ctx->cmd_buf_last = cmd_buf; + } + } + + dispatch_apply(n_cb, ctx->d_queue, ctx->encode_async); + + // for debugging: block until graph is computed + //[ctx->cmd_buf_last waitUntilCompleted]; + + // enter here only when capturing in order to wait for all computation to finish + // otherwise, we leave the graph to compute asynchronously + if (!use_capture && ctx->capture_started) { + // wait for completion and check status of each command buffer + // needed to detect if the device ran out-of-memory for example (#1881) + { + id cmd_buf = ctx->cmd_bufs[n_cb].obj; + [cmd_buf waitUntilCompleted]; + + MTLCommandBufferStatus status = [cmd_buf status]; + if (status != MTLCommandBufferStatusCompleted) { + GGML_LOG_INFO("%s: command buffer %d failed with status %lu\n", __func__, n_cb, status); + if (status == MTLCommandBufferStatusError) { + GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); + } + + return GGML_STATUS_FAILED; + } + } + + for (int i = 0; i < n_cb; ++i) { + id cmd_buf = ctx->cmd_bufs[i].obj; + [cmd_buf waitUntilCompleted]; + + MTLCommandBufferStatus status = [cmd_buf status]; + if (status != MTLCommandBufferStatusCompleted) { + GGML_LOG_INFO("%s: command buffer %d failed with status %lu\n", __func__, i, status); + if (status == MTLCommandBufferStatusError) { + GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); + } + + return GGML_STATUS_FAILED; + } + + id next_buffer = (i + 1 < n_cb ? ctx->cmd_bufs[i + 1].obj : nil); + if (!next_buffer) { + continue; + } + + const bool next_queued = ([next_buffer status] != MTLCommandBufferStatusNotEnqueued); + if (next_queued) { + continue; + } + + if (ctx->abort_callback && ctx->abort_callback(ctx->abort_callback_data)) { + GGML_LOG_INFO("%s: command buffer %d aborted", __func__, i); + return GGML_STATUS_ABORTED; + } + + [next_buffer commit]; + } + + [ctx->capture_scope endScope]; + [[MTLCaptureManager sharedCaptureManager] stopCapture]; + } + } + + return GGML_STATUS_SUCCESS; +} + +void ggml_metal_graph_optimize(ggml_metal_t ctx, struct ggml_cgraph * gf) { + //const int64_t t_start = ggml_time_us(); + + if (ctx->use_graph_optimize) { + ggml_graph_optimize(gf); + } + + //printf("%s: graph optimize took %.3f ms\n", __func__, (ggml_time_us() - t_start) / 1000.0); +} + +void ggml_metal_set_n_cb(ggml_metal_t ctx, int n_cb) { + if (ctx->n_cb != n_cb) { + ctx->n_cb = MIN(n_cb, GGML_METAL_MAX_COMMAND_BUFFERS); + + if (ctx->n_cb > 2) { + GGML_LOG_WARN("%s: n_cb = %d, using n_cb > 2 is not recommended and can degrade the performance in some cases\n", __func__, n_cb); + } + } + + if (ctx->encode_async) { + Block_release(ctx->encode_async); + } + + ctx->encode_async = Block_copy(^(size_t iter) { + const int cb_idx = iter; + const int n_cb_l = ctx->n_cb; + + const int n_nodes_0 = ctx->n_nodes_0; + const int n_nodes_1 = ctx->n_nodes_1; + + const int n_nodes_per_cb = ctx->n_nodes_per_cb; + + int idx_start = 0; + int idx_end = n_nodes_0; + + if (cb_idx < n_cb_l) { + idx_start = n_nodes_0 + ( (cb_idx + 0) * n_nodes_per_cb); + idx_end = n_nodes_0 + (MIN((cb_idx == n_cb_l - 1) ? n_nodes_1 : (cb_idx + 1) * n_nodes_per_cb, n_nodes_1)); + } + + id cmd_buf = ctx->cmd_bufs[cb_idx].obj; + + ggml_metal_op_t ctx_op = ggml_metal_op_init( + ctx->dev, + cmd_buf, + ctx->gf, + idx_start, + idx_end, + ctx->use_fusion, + ctx->use_concurrency, + ctx->capture_next_compute, + ctx->debug_graph, + ctx->debug_fusion); + + for (int idx = 0; idx < ggml_metal_op_n_nodes(ctx_op); ++idx) { + const int res = ggml_metal_op_encode(ctx_op, idx); + if (res == 0) { + break; + } + + idx += res - 1; + } + + ggml_metal_op_free(ctx_op); + + if (cb_idx < 2 || ctx->abort_callback == NULL) { + [cmd_buf commit]; + } + }); +} + +void ggml_metal_set_abort_callback(ggml_metal_t ctx, ggml_abort_callback abort_callback, void * user_data) { + ctx->abort_callback = abort_callback; + ctx->abort_callback_data = user_data; +} + +bool ggml_metal_supports_family(ggml_metal_t ctx, int family) { + GGML_ASSERT(ctx->device != nil); + + return [ctx->device supportsFamily:(MTLGPUFamilyApple1 + family - 1)]; +} + +void ggml_metal_capture_next_compute(ggml_metal_t ctx) { + ctx->capture_next_compute = true; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.cpp 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.cpp --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,1388 @@ +#include "ggml-metal-device.h" + +#include "ggml-metal-impl.h" + +#include "ggml-impl.h" + +#include +#include +#include +#include + +struct ggml_metal_device_deleter { + void operator()(ggml_metal_device_t ctx) { + ggml_metal_device_free(ctx); + } +}; + +typedef std::unique_ptr ggml_metal_device_ptr; + +ggml_metal_device_t ggml_metal_device_get(void) { + static ggml_metal_device_ptr ctx { ggml_metal_device_init() }; + + return ctx.get(); +} + +struct ggml_metal_pipelines { + std::unordered_map data; +}; + +ggml_metal_pipelines_t ggml_metal_pipelines_init(void) { + ggml_metal_pipelines_t res = new ggml_metal_pipelines(); + + return res; +} + +void ggml_metal_pipelines_free(ggml_metal_pipelines_t ppls) { + if (!ppls) { + return; + } + + for (auto it = ppls->data.begin(); it != ppls->data.end(); ++it) { + ggml_metal_pipeline_free(it->second); + } + + delete ppls; +} + +void ggml_metal_pipelines_add(ggml_metal_pipelines_t ppls, const char * name, ggml_metal_pipeline_t pipeline) { + ppls->data[name] = pipeline; +} + +ggml_metal_pipeline_t ggml_metal_pipelines_get(ggml_metal_pipelines_t ppls, const char * name) { + if (ppls->data.find(name) == ppls->data.end()) { + return nullptr; + } + + return ppls->data[name]; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_base(ggml_metal_library_t lib, ggml_op op) { + char base[256]; + char name[256]; + + const char * op_str = "undefined"; + switch (op) { + case GGML_OP_ADD_ID: op_str = "add_id"; break; + case GGML_OP_CONCAT: op_str = "concat"; break; + default: GGML_ABORT("fatal error"); + }; + + snprintf(base, 256, "kernel_%s", op_str); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_cpy(ggml_metal_library_t lib, ggml_type tsrc, ggml_type tdst) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_cpy_%s_%s", ggml_type_name(tsrc), ggml_type_name(tdst)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pool_2d(ggml_metal_library_t lib, const ggml_tensor * op, ggml_op_pool op_pool) { + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32 && op->src[0]->type == op->type); + + const char * pool_str = "undefined"; + switch (op_pool) { + case GGML_OP_POOL_AVG: pool_str = "avg"; break; + case GGML_OP_POOL_MAX: pool_str = "max"; break; + default: GGML_ASSERT(false && "not implemented"); + }; + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_pool_2d_%s_%s", pool_str, ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_get_rows(ggml_metal_library_t lib, ggml_type tsrc) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_get_rows_%s", ggml_type_name(tsrc)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_set_rows(ggml_metal_library_t lib, ggml_type tidx, ggml_type tdst) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_set_rows_%s_%s", ggml_type_name(tdst), ggml_type_name(tidx)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_repeat(ggml_metal_library_t lib, ggml_type tsrc) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_repeat_%s", ggml_type_name(tsrc)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_unary(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + + char base[256]; + char name[256]; + + const int64_t n = ggml_nelements(op); + + const char * op_str = "undefined"; + switch (op->op) { + case GGML_OP_SCALE: op_str = "scale"; break; + case GGML_OP_CLAMP: op_str = "clamp"; break; + case GGML_OP_SQR: op_str = "sqr"; break; + case GGML_OP_SQRT: op_str = "sqrt"; break; + case GGML_OP_SIN: op_str = "sin"; break; + case GGML_OP_COS: op_str = "cos"; break; + case GGML_OP_LOG: op_str = "log"; break; + case GGML_OP_LEAKY_RELU: op_str = "leaky_relu"; break; + case GGML_OP_UNARY: + switch (ggml_get_unary_op(op)) { + case GGML_UNARY_OP_TANH: op_str = "tanh"; break; + case GGML_UNARY_OP_RELU: op_str = "relu"; break; + case GGML_UNARY_OP_SIGMOID: op_str = "sigmoid"; break; + case GGML_UNARY_OP_GELU: op_str = "gelu"; break; + case GGML_UNARY_OP_GELU_ERF: op_str = "gelu_erf"; break; + case GGML_UNARY_OP_GELU_QUICK: op_str = "gelu_quick"; break; + case GGML_UNARY_OP_SILU: op_str = "silu"; break; + case GGML_UNARY_OP_ELU: op_str = "elu"; break; + case GGML_UNARY_OP_NEG: op_str = "neg"; break; + case GGML_UNARY_OP_ABS: op_str = "abs"; break; + case GGML_UNARY_OP_SGN: op_str = "sgn"; break; + case GGML_UNARY_OP_STEP: op_str = "step"; break; + case GGML_UNARY_OP_HARDSWISH: op_str = "hardswish"; break; + case GGML_UNARY_OP_HARDSIGMOID: op_str = "hardsigmoid"; break; + case GGML_UNARY_OP_EXP: op_str = "exp"; break; + default: GGML_ABORT("fatal error"); + } break; + default: GGML_ABORT("fatal error"); + }; + + const char * suffix = ""; + if (n % 4 == 0) { + suffix = "_4"; + } + + snprintf(base, 256, "kernel_%s_%s%s", op_str, ggml_type_name(op->src[0]->type), suffix); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_glu(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(ggml_is_contiguous_1(op->src[0])); + + char base[256]; + char name[256]; + + const char * op_str = "undefined"; + switch (op->op) { + case GGML_OP_GLU: + switch (ggml_get_glu_op(op)) { + case GGML_GLU_OP_REGLU: op_str = "reglu"; break; + case GGML_GLU_OP_GEGLU: op_str = "geglu"; break; + case GGML_GLU_OP_SWIGLU: op_str = "swiglu"; break; + case GGML_GLU_OP_SWIGLU_OAI: op_str = "swiglu_oai"; break; + case GGML_GLU_OP_GEGLU_ERF: op_str = "geglu_erf"; break; + case GGML_GLU_OP_GEGLU_QUICK: op_str = "geglu_quick"; break; + default: GGML_ABORT("fatal error"); + } break; + default: GGML_ABORT("fatal error"); + }; + + snprintf(base, 256, "kernel_%s_%s", op_str, ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_sum_rows(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(op->src[0]->nb[0] == ggml_type_size(op->src[0]->type)); + + char base[256]; + char name[256]; + + const char * op_str = "undefined"; + switch (op->op) { + case GGML_OP_SUM_ROWS: + op_str = "sum_rows"; break; + case GGML_OP_MEAN: + op_str = "mean"; break; + default: GGML_ABORT("fatal error"); + }; + + snprintf(base, 256, "kernel_%s_%s", op_str, ggml_type_name(op->src[0]->type)); + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_soft_max(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(!op->src[1] || op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32); + + char base[256]; + char name[256]; + + const char * suffix = ""; + + if (op->src[0]->ne[0] % 4 == 0) { + suffix = "_4"; + } + + const ggml_type tsrc1 = op->src[1] ? op->src[1]->type : GGML_TYPE_F32; + + snprintf(base, 256, "kernel_soft_max_%s%s", ggml_type_name(tsrc1), suffix); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_ssm_conv(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + GGML_ASSERT(ggml_is_contiguous(op->src[1])); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_ssm_conv_%s_%s", ggml_type_name(op->src[0]->type), ggml_type_name(op->src[1]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_ssm_scan(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + if (op->src[3]->ne[0] == 1) { + snprintf(base, 256, "kernel_ssm_scan_group_%s", ggml_type_name(op->src[0]->type)); + } else { + snprintf(base, 256, "kernel_ssm_scan_%s", ggml_type_name(op->src[0]->type)); + } + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_rwkv(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + const int64_t C = op->ne[0]; + const int64_t H = op->src[0]->ne[1]; + + switch (op->op) { + case GGML_OP_RWKV_WKV6: + { + GGML_ASSERT(op->src[5]->type == GGML_TYPE_F32); + GGML_ASSERT(C % H == 0); + GGML_ASSERT(C / H == 64); + + snprintf(base, 256, "kernel_rwkv_wkv6_%s", ggml_type_name(op->src[0]->type)); + } break; + case GGML_OP_RWKV_WKV7: + { + GGML_ASSERT(op->src[6]->type == GGML_TYPE_F32); + GGML_ASSERT(C % H == 0); + GGML_ASSERT(C / H == 64); + + snprintf(base, 256, "kernel_rwkv_wkv7_%s", ggml_type_name(op->src[0]->type)); + } break; + default: + GGML_ABORT("fatal error"); + } + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv_ext(ggml_metal_library_t lib, ggml_type tsrc0, ggml_type tsrc1, int nsg, int nxpsg, int r1ptg) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_mul_mv_ext_%s_%s_r1_%d", ggml_type_name(tsrc0), ggml_type_name(tsrc1), r1ptg); + snprintf(name, 256, "%s_nsg=%d_nxpsg=%d", base, nsg, nxpsg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_int16(cv, nsg, FC_MUL_MV + 0); + ggml_metal_cv_set_int16(cv, nxpsg, FC_MUL_MV + 1); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const bool bc_inp = op->src[0]->ne[0] % 32 != 0; + const bool bc_out = op->ne[0] % 64 != 0 || op->ne[1] % 32 != 0; + + snprintf(base, 256, "kernel_mul_mm_%s_%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1)); + snprintf(name, 256, "%s_bci=%d_bco=%d", base, bc_inp, bc_out); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, bc_inp, FC_MUL_MM + 0); + ggml_metal_cv_set_bool(cv, bc_out, FC_MUL_MM + 1); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + // when the output size is not multiple of 64x32, we need extra smem to prevent out-of-bounds writes + ggml_metal_pipeline_set_smem(res, bc_out ? 8192 : 4096 + 2048); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + + char base[256]; + char name[256]; + + int nsg = 0; // number of simdgroups + int nr0 = 0; // number of src0 rows per simdgroup + int nr1 = 1; // number of src1 rows per threadgroup + + size_t smem = 0; // shared memory + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const char * suffix = ""; + + // use custom matrix x vector kernel + switch (tsrc0) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + case GGML_TYPE_BF16: + { + if (ne00 == 4) { + nsg = 1; + nr0 = 32; + nr1 = 4; + suffix = "_c4"; + } else if (ne00 % 4 == 0) { + nsg = N_SG_F; + nr0 = N_R0_F; + nr1 = 1; + smem = 32*sizeof(float)*N_R0_F; + suffix = "_4"; + } else { + nsg = N_SG_F; + nr0 = N_R0_F; + nr1 = 1; + smem = 32*sizeof(float)*N_R0_F; + } + } break; + case GGML_TYPE_Q4_0: + { + nsg = N_SG_Q4_0; + nr0 = N_R0_Q4_0; + } break; + case GGML_TYPE_Q4_1: + { + nsg = N_SG_Q4_1; + nr0 = N_R0_Q4_1; + } break; + case GGML_TYPE_Q5_0: + { + nsg = N_SG_Q5_0; + nr0 = N_R0_Q5_0; + } break; + case GGML_TYPE_Q5_1: + { + nsg = N_SG_Q5_1; + nr0 = N_R0_Q5_1; + } break; + case GGML_TYPE_Q8_0: + { + nsg = N_SG_Q8_0; + nr0 = N_R0_Q8_0; + smem = 32*sizeof(float)*N_R0_Q8_0; + } break; + case GGML_TYPE_MXFP4: + { + nsg = N_SG_MXFP4; + nr0 = N_R0_MXFP4; + smem = 32*sizeof(float); + } break; + case GGML_TYPE_Q2_K: + { + nsg = N_SG_Q2_K; + nr0 = N_R0_Q2_K; + } break; + case GGML_TYPE_Q3_K: + { + nsg = N_SG_Q3_K; + nr0 = N_R0_Q3_K; + } break; + case GGML_TYPE_Q4_K: + { + nsg = N_SG_Q4_K; + nr0 = N_R0_Q4_K; + } break; + case GGML_TYPE_Q5_K: + { + nsg = N_SG_Q5_K; + nr0 = N_R0_Q5_K; + } break; + case GGML_TYPE_Q6_K: + { + nsg = N_SG_Q6_K; + nr0 = N_R0_Q6_K; + } break; + case GGML_TYPE_IQ2_XXS: + { + nsg = N_SG_IQ2_XXS; + nr0 = N_R0_IQ2_XXS; + smem = 256*8+128; + } break; + case GGML_TYPE_IQ2_XS: + { + nsg = N_SG_IQ2_XS; + nr0 = N_R0_IQ2_XS; + smem = 512*8+128; + } break; + case GGML_TYPE_IQ3_XXS: + { + nsg = N_SG_IQ3_XXS; + nr0 = N_R0_IQ3_XXS; + smem = 256*4+128; + } break; + case GGML_TYPE_IQ3_S: + { + nsg = N_SG_IQ3_S; + nr0 = N_R0_IQ3_S; + smem = 512*4; + } break; + case GGML_TYPE_IQ2_S: + { + nsg = N_SG_IQ2_S; + nr0 = N_R0_IQ2_S; + } break; + case GGML_TYPE_IQ1_S: + { + nsg = N_SG_IQ1_S; + nr0 = N_R0_IQ1_S; + } break; + case GGML_TYPE_IQ1_M: + { + nsg = N_SG_IQ1_M; + nr0 = N_R0_IQ1_M; + } break; + case GGML_TYPE_IQ4_NL: + { + nsg = N_SG_IQ4_NL; + nr0 = N_R0_IQ4_NL; + smem = 32*sizeof(float); + } break; + case GGML_TYPE_IQ4_XS: + { + nsg = N_SG_IQ4_XS; + nr0 = N_R0_IQ4_XS; + smem = 32*sizeof(float); + } break; + default: + { + GGML_LOG_ERROR("Asserting on type %d\n", (int) tsrc0); + GGML_ABORT("not implemented"); + } + }; + + snprintf(base, 256, "kernel_mul_mv_%s_%s%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1), suffix); + snprintf(name, 256, "%s_nsg=%d", base, nsg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_int16(cv, nsg, FC_MUL_MV + 0); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + ggml_metal_pipeline_set_nr0 (res, nr0); + ggml_metal_pipeline_set_nr1 (res, nr1); + ggml_metal_pipeline_set_nsg (res, nsg); + ggml_metal_pipeline_set_smem(res, smem); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm_id_map0(ggml_metal_library_t lib, int ne02, int ne20) { + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_mul_mm_id_map0_ne20_%d", ne20); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + const size_t smem = (size_t) ne02*ne20*sizeof(uint16_t); + + ggml_metal_pipeline_set_smem(res, smem); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm_id(ggml_metal_library_t lib, const ggml_tensor * op) { + char base[256]; + char name[256]; + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const bool bc_inp = op->src[0]->ne[0] % 32 != 0; + + snprintf(base, 256, "kernel_mul_mm_id_%s_%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1)); + snprintf(name, 256, "%s_bci=%d", base, bc_inp); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, bc_inp, FC_MUL_MM + 0); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + ggml_metal_pipeline_set_smem(res, 8192); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv_id(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + + char base[256]; + char name[256]; + + int nsg = 0; // number of simdgroups + int nr0 = 0; // number of src0 rows per simdgroup + int nr1 = 1; // number of src1 rows per threadgroup + + size_t smem = 0; // shared memory + + const ggml_type tsrc0 = op->src[0]->type; + const ggml_type tsrc1 = op->src[1]->type; + + const char * suffix = ""; + + // use custom matrix x vector kernel + switch (tsrc0) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + case GGML_TYPE_BF16: + { + if (ne00 % 4 == 0) { + nsg = N_SG_F; + nr0 = N_R0_F; + nr1 = 1; + smem = 32*sizeof(float)*N_R0_F; + suffix = "_4"; + } else { + nsg = N_SG_F; + nr0 = N_R0_F; + nr1 = 1; + smem = 32*sizeof(float)*N_R0_F; + } + } break; + case GGML_TYPE_Q4_0: + { + nsg = N_SG_Q4_0; + nr0 = N_R0_Q4_0; + } break; + case GGML_TYPE_Q4_1: + { + nsg = N_SG_Q4_1; + nr0 = N_R0_Q4_1; + } break; + case GGML_TYPE_Q5_0: + { + nsg = N_SG_Q5_0; + nr0 = N_R0_Q5_0; + } break; + case GGML_TYPE_Q5_1: + { + nsg = N_SG_Q5_1; + nr0 = N_R0_Q5_1; + } break; + case GGML_TYPE_Q8_0: + { + nsg = N_SG_Q8_0; + nr0 = N_R0_Q8_0; + smem = 32*sizeof(float)*N_R0_Q8_0; + } break; + case GGML_TYPE_MXFP4: + { + nsg = N_SG_MXFP4; + nr0 = N_R0_MXFP4; + smem = 32*sizeof(float); + } break; + case GGML_TYPE_Q2_K: + { + nsg = N_SG_Q2_K; + nr0 = N_R0_Q2_K; + } break; + case GGML_TYPE_Q3_K: + { + nsg = N_SG_Q3_K; + nr0 = N_R0_Q3_K; + } break; + case GGML_TYPE_Q4_K: + { + nsg = N_SG_Q4_K; + nr0 = N_R0_Q4_K; + } break; + case GGML_TYPE_Q5_K: + { + nsg = N_SG_Q5_K; + nr0 = N_R0_Q5_K; + } break; + case GGML_TYPE_Q6_K: + { + nsg = N_SG_Q6_K; + nr0 = N_R0_Q6_K; + } break; + case GGML_TYPE_IQ2_XXS: + { + nsg = N_SG_IQ2_XXS; + nr0 = N_R0_IQ2_XXS; + smem = 256*8+128; + } break; + case GGML_TYPE_IQ2_XS: + { + nsg = N_SG_IQ2_XS; + nr0 = N_R0_IQ2_XS; + smem = 512*8+128; + } break; + case GGML_TYPE_IQ3_XXS: + { + nsg = N_SG_IQ3_XXS; + nr0 = N_R0_IQ3_XXS; + smem = 256*4+128; + } break; + case GGML_TYPE_IQ3_S: + { + nsg = N_SG_IQ3_S; + nr0 = N_R0_IQ3_S; + smem = 512*4; + } break; + case GGML_TYPE_IQ2_S: + { + nsg = N_SG_IQ2_S; + nr0 = N_R0_IQ2_S; + } break; + case GGML_TYPE_IQ1_S: + { + nsg = N_SG_IQ1_S; + nr0 = N_R0_IQ1_S; + } break; + case GGML_TYPE_IQ1_M: + { + nsg = N_SG_IQ1_M; + nr0 = N_R0_IQ1_M; + } break; + case GGML_TYPE_IQ4_NL: + { + nsg = N_SG_IQ4_NL; + nr0 = N_R0_IQ4_NL; + smem = 32*sizeof(float); + } break; + case GGML_TYPE_IQ4_XS: + { + nsg = N_SG_IQ4_XS; + nr0 = N_R0_IQ4_XS; + smem = 32*sizeof(float); + } break; + default: + { + GGML_LOG_ERROR("Asserting on type %d\n", (int)op->src[2]->type); + GGML_ABORT("not implemented"); + } + }; + + snprintf(base, 256, "kernel_mul_mv_id_%s_%s%s", ggml_type_name(tsrc0), ggml_type_name(tsrc1), suffix); + snprintf(name, 256, "%s_nsg=%d", base, nsg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_int16(cv, nsg, FC_MUL_MV + 0); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + ggml_metal_pipeline_set_nr0 (res, nr0); + ggml_metal_pipeline_set_nr1 (res, nr1); + ggml_metal_pipeline_set_nsg (res, nsg); + ggml_metal_pipeline_set_smem(res, smem); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_argmax(ggml_metal_library_t lib, const ggml_tensor * op) { + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(ggml_is_contiguous_1(op->src[0])); + GGML_ASSERT(op->src[0]->nb[0] == ggml_type_size(op->src[0]->type)); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_argmax_%s", ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*(sizeof(float) + sizeof(int32_t))); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_argsort(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_ARGSORT); + + char base[256]; + char name[256]; + + ggml_sort_order order = (ggml_sort_order) op->op_params[0]; + + const char * order_str = "undefined"; + switch (order) { + case GGML_SORT_ORDER_ASC: order_str = "asc"; break; + case GGML_SORT_ORDER_DESC: order_str = "desc"; break; + default: GGML_ABORT("fatal error"); + }; + + snprintf(base, 256, "kernel_argsort_%s_%s_%s", ggml_type_name(op->src[0]->type), ggml_type_name(op->type), order_str); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext( + ggml_metal_library_t lib, + const ggml_tensor * op, + bool has_mask, + bool has_sinks, + bool has_bias, + bool has_scap, + int32_t nsg) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + char base[256]; + char name[256]; + + const int32_t dk = (int32_t) op->src[1]->ne[0]; + const int32_t dv = (int32_t) op->src[2]->ne[0]; + + const int32_t ns10 = op->src[1]->nb[1]/op->src[1]->nb[0]; + const int32_t ns20 = op->src[2]->nb[1]/op->src[2]->nb[0]; + + snprintf(base, 256, "kernel_%s_%s_dk%d_dv%d", + "flash_attn_ext", + ggml_type_name(op->src[1]->type), + dk, + dv); + + snprintf(name, 256, "%s_mask=%d_sinks=%d_bias=%d_scap=%d_ns10=%d_ns20=%d_nsg=%d", + base, + has_mask, + has_sinks, + has_bias, + has_scap, + ns10, + ns20, + nsg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, has_mask, FC_FLASH_ATTN_EXT + 0); + ggml_metal_cv_set_bool(cv, has_sinks, FC_FLASH_ATTN_EXT + 1); + ggml_metal_cv_set_bool(cv, has_bias, FC_FLASH_ATTN_EXT + 2); + ggml_metal_cv_set_bool(cv, has_scap, FC_FLASH_ATTN_EXT + 3); + + ggml_metal_cv_set_int32(cv, ns10, FC_FLASH_ATTN_EXT + 20); + ggml_metal_cv_set_int32(cv, ns20, FC_FLASH_ATTN_EXT + 21); + ggml_metal_cv_set_int32(cv, nsg, FC_FLASH_ATTN_EXT + 22); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext_vec( + ggml_metal_library_t lib, + const ggml_tensor * op, + bool has_mask, + bool has_sinks, + bool has_bias, + bool has_scap, + int32_t nsg, + int32_t nwg) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + char base[256]; + char name[256]; + + const int32_t dk = (int32_t) op->src[1]->ne[0]; + const int32_t dv = (int32_t) op->src[2]->ne[0]; + + const int32_t ns10 = op->src[1]->nb[1]/op->src[1]->nb[0]; + const int32_t ns20 = op->src[2]->nb[1]/op->src[2]->nb[0]; + + snprintf(base, 256, "kernel_%s_%s_dk%d_dv%d", + "flash_attn_ext_vec", + ggml_type_name(op->src[1]->type), + dk, + dv); + + snprintf(name, 256, "%s_mask=%d_sink=%d_bias=%d_softcap=%d_ns10=%d_ns20=%d_nsg=%d_nwg=%d", + base, + has_mask, + has_sinks, + has_bias, + has_scap, + ns10, + ns20, + nsg, nwg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_bool(cv, has_mask, FC_FLASH_ATTN_EXT_VEC + 0); + ggml_metal_cv_set_bool(cv, has_sinks, FC_FLASH_ATTN_EXT_VEC + 1); + ggml_metal_cv_set_bool(cv, has_bias, FC_FLASH_ATTN_EXT_VEC + 2); + ggml_metal_cv_set_bool(cv, has_scap, FC_FLASH_ATTN_EXT_VEC + 3); + + ggml_metal_cv_set_int32(cv, ns10, FC_FLASH_ATTN_EXT_VEC + 20); + ggml_metal_cv_set_int32(cv, ns20, FC_FLASH_ATTN_EXT_VEC + 21); + ggml_metal_cv_set_int32(cv, nsg, FC_FLASH_ATTN_EXT_VEC + 22); + ggml_metal_cv_set_int32(cv, nwg, FC_FLASH_ATTN_EXT_VEC + 23); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext_vec_reduce( + ggml_metal_library_t lib, + const ggml_tensor * op, + int32_t dv, + int32_t nwg) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_flash_attn_ext_vec_reduce"); + snprintf(name, 256, "%s_dv=%d_nwg=%d", base, dv, nwg); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + ggml_metal_cv_t cv = ggml_metal_cv_init(); + + ggml_metal_cv_set_int32(cv, dv, FC_FLASH_ATTN_EXT_VEC_REDUCE + 0); + ggml_metal_cv_set_int32(cv, nwg, FC_FLASH_ATTN_EXT_VEC_REDUCE + 1); + + res = ggml_metal_library_compile_pipeline(lib, base, name, cv); + + ggml_metal_cv_free(cv); + + return res; + + GGML_UNUSED(op); +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_bin( + ggml_metal_library_t lib, + ggml_op op, + int32_t n_fuse, + bool row) { + char base[256]; + char name[256]; + + const char * op_str = "undefined"; + switch (op) { + case GGML_OP_ADD: op_str = "add"; break; + case GGML_OP_SUB: op_str = "sub"; break; + case GGML_OP_MUL: op_str = "mul"; break; + case GGML_OP_DIV: op_str = "div"; break; + default: GGML_ABORT("fatal error"); + }; + + if (row) { + snprintf(base, 256, "kernel_%s_row_c4_fuse_%d", op_str, n_fuse); + } else { + snprintf(base, 256, "kernel_%s_fuse_%d", op_str, n_fuse); + } + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_l2_norm(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_L2_NORM); + + GGML_ASSERT(op->src[0]->ne[0] % 4 == 0); + GGML_ASSERT(ggml_is_contiguous_1(op->src[0])); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_l2_norm_f32"); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_group_norm(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_GROUP_NORM); + + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_group_norm_f32"); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_norm(ggml_metal_library_t lib, const ggml_tensor * op, int n_fuse) { + assert(op->op == GGML_OP_NORM || op->op == GGML_OP_RMS_NORM); + + GGML_ASSERT(ggml_is_contiguous_rows(op->src[0])); + + char base[256]; + char name[256]; + + const char * suffix = ""; + if (op->ne[0] % 4 == 0) { + suffix = "_4"; + } + + switch (op->op) { + case GGML_OP_NORM: + switch (n_fuse) { + case 1: snprintf(base, 256, "kernel_norm_f32%s", suffix); break; + case 2: snprintf(base, 256, "kernel_norm_mul_f32%s", suffix); break; + case 3: snprintf(base, 256, "kernel_norm_mul_add_f32%s", suffix); break; + default: GGML_ABORT("fatal error"); + } break; + case GGML_OP_RMS_NORM: + switch (n_fuse) { + case 1: snprintf(base, 256, "kernel_rms_norm_f32%s", suffix); break; + case 2: snprintf(base, 256, "kernel_rms_norm_mul_f32%s", suffix); break; + case 3: snprintf(base, 256, "kernel_rms_norm_mul_add_f32%s", suffix); break; + default: GGML_ABORT("fatal error"); + } break; + default: GGML_ABORT("fatal error"); + } + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + ggml_metal_pipeline_set_smem(res, 32*sizeof(float)); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_rope(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_ROPE); + + char base[256]; + char name[256]; + + const int mode = ((const int32_t *) op->op_params)[2]; + + const bool is_neox = mode & GGML_ROPE_TYPE_NEOX; + const bool is_mrope = mode & GGML_ROPE_TYPE_MROPE; + const bool is_vision = mode == GGML_ROPE_TYPE_VISION; + + if (is_neox) { + snprintf(base, 256, "kernel_rope_neox_%s", ggml_type_name(op->src[0]->type)); + } else if (is_mrope && !is_vision) { + GGML_ASSERT(op->src[1]->ne[0]*4 >= op->src[0]->ne[2]); // need at least 4 pos per token + snprintf(base, 256, "kernel_rope_multi_%s", ggml_type_name(op->src[0]->type)); + } else if (is_vision) { + GGML_ASSERT(op->src[1]->ne[0]*4 >= op->src[0]->ne[2]); // need at least 4 pos per token + snprintf(base, 256, "kernel_rope_vision_%s", ggml_type_name(op->src[0]->type)); + } else { + snprintf(base, 256, "kernel_rope_norm_%s", ggml_type_name(op->src[0]->type)); + } + + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_im2col(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_IM2COL); + + GGML_ASSERT(ggml_is_contiguous(op->src[1])); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + GGML_ASSERT(op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_im2col_%s", ggml_type_name(op->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_conv_transpose_1d(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_CONV_TRANSPOSE_1D); + + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + GGML_ASSERT(ggml_is_contiguous(op->src[1])); + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + GGML_ASSERT(op->type == GGML_TYPE_F32); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_conv_transpose_1d_%s_%s", ggml_type_name(op->src[0]->type), ggml_type_name(op->src[1]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_upscale(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_UPSCALE); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_upscale_%s", ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pad(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_PAD); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_pad_%s", ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pad_reflect_1d(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_PAD_REFLECT_1D); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_pad_reflect_1d_%s", ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_arange(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_ARANGE); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_arange_%s", ggml_type_name(op->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_timestep_embedding(ggml_metal_library_t lib, const ggml_tensor * op) { + assert(op->op == GGML_OP_TIMESTEP_EMBEDDING); + + char base[256]; + char name[256]; + + snprintf(base, 256, "kernel_timestep_embedding_%s", ggml_type_name(op->src[0]->type)); + snprintf(name, 256, "%s", base); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + return res; + } + + res = ggml_metal_library_compile_pipeline(lib, base, name, nullptr); + + return res; +} + diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.h 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.h --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,226 @@ +#pragma once + +#include "ggml.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct ggml_metal_buffer_id { + void * metal; // id + size_t offs; +}; + +typedef struct ggml_metal_device * ggml_metal_device_t; + +// +// MTLFunctionConstantValues wrapper +// + +typedef struct ggml_metal_cv * ggml_metal_cv_t; + +ggml_metal_cv_t ggml_metal_cv_init(void); +void ggml_metal_cv_free(ggml_metal_cv_t cv); + +void ggml_metal_cv_set_int16(ggml_metal_cv_t cv, int16_t value, int32_t idx); +void ggml_metal_cv_set_int32(ggml_metal_cv_t cv, int32_t value, int32_t idx); +void ggml_metal_cv_set_bool (ggml_metal_cv_t cv, bool value, int32_t idx); + +// +// MTLComputePipelineState wrapper +// + +typedef struct ggml_metal_pipeline * ggml_metal_pipeline_t; + +ggml_metal_pipeline_t ggml_metal_pipeline_init(void); +void ggml_metal_pipeline_free(ggml_metal_pipeline_t pipeline); + +void ggml_metal_pipeline_set_nsg(ggml_metal_pipeline_t pipeline, int nsg); +int ggml_metal_pipeline_get_nsg(ggml_metal_pipeline_t pipeline); + +void ggml_metal_pipeline_set_nr0(ggml_metal_pipeline_t pipeline, int nr0); +int ggml_metal_pipeline_get_nr0(ggml_metal_pipeline_t pipeline); + +void ggml_metal_pipeline_set_nr1(ggml_metal_pipeline_t pipeline, int nr1); +int ggml_metal_pipeline_get_nr1(ggml_metal_pipeline_t pipeline); + +void ggml_metal_pipeline_set_smem(ggml_metal_pipeline_t pipeline, size_t smem); +size_t ggml_metal_pipeline_get_smem(ggml_metal_pipeline_t pipeline); + +int ggml_metal_pipeline_max_theads_per_threadgroup(ggml_metal_pipeline_t pipeline); + +// a collection of pipelines +typedef struct ggml_metal_pipelines * ggml_metal_pipelines_t; + +ggml_metal_pipelines_t ggml_metal_pipelines_init(void); +void ggml_metal_pipelines_free(ggml_metal_pipelines_t ppls); + +void ggml_metal_pipelines_add(ggml_metal_pipelines_t ppls, const char * name, ggml_metal_pipeline_t pipeline); +ggml_metal_pipeline_t ggml_metal_pipelines_get(ggml_metal_pipelines_t ppls, const char * name); + +// +// MTLCommandBuffer wrapper +// + +typedef void * ggml_metal_cmd_buf_t; + +// +// MTLComputeCommandEncoder wrapper +// + +typedef struct ggml_metal_encoder * ggml_metal_encoder_t; + +ggml_metal_encoder_t ggml_metal_encoder_init(ggml_metal_cmd_buf_t cmd_buf_raw, bool concurrent); +void ggml_metal_encoder_free(ggml_metal_encoder_t encoder); + +void ggml_metal_encoder_debug_group_push(ggml_metal_encoder_t encoder, const char * name); +void ggml_metal_encoder_debug_group_pop (ggml_metal_encoder_t encoder); + +void ggml_metal_encoder_set_pipeline(ggml_metal_encoder_t encoder, ggml_metal_pipeline_t pipeline); + +void ggml_metal_encoder_set_bytes (ggml_metal_encoder_t encoder, void * data, size_t size, int idx); +void ggml_metal_encoder_set_buffer(ggml_metal_encoder_t encoder, struct ggml_metal_buffer_id buffer, int idx); + +void ggml_metal_encoder_set_threadgroup_memory_size(ggml_metal_encoder_t encoder, size_t size, int idx); + +void ggml_metal_encoder_dispatch_threadgroups(ggml_metal_encoder_t encoder, int tg0, int tg1, int tg2, int tptg0, int tptg1, int tptg2); + +void ggml_metal_encoder_memory_barrier(ggml_metal_encoder_t encoder); + +void ggml_metal_encoder_end_encoding(ggml_metal_encoder_t encoder); + +// +// MTLLibrary wrapper +// + +typedef struct ggml_metal_library * ggml_metal_library_t; + +ggml_metal_library_t ggml_metal_library_init(ggml_metal_device_t dev); +void ggml_metal_library_free(ggml_metal_library_t lib); + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline (ggml_metal_library_t lib, const char * name); +ggml_metal_pipeline_t ggml_metal_library_compile_pipeline(ggml_metal_library_t lib, const char * base, const char * name, ggml_metal_cv_t cv); + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_base (ggml_metal_library_t lib, enum ggml_op op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_cpy (ggml_metal_library_t lib, enum ggml_type tsrc, enum ggml_type tdst); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pool_2d (ggml_metal_library_t lib, const struct ggml_tensor * op, enum ggml_op_pool op_pool); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_get_rows (ggml_metal_library_t lib, enum ggml_type tsrc); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_set_rows (ggml_metal_library_t lib, enum ggml_type tidx, enum ggml_type tdst); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_repeat (ggml_metal_library_t lib, enum ggml_type tsrc); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_unary (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_glu (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_sum_rows (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_soft_max (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_ssm_conv (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_ssm_scan (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_rwkv (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv_ext (ggml_metal_library_t lib, enum ggml_type tsrc0, enum ggml_type tsrc1, int nsg, int nxpsg, int r1ptg); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm_id_map0 (ggml_metal_library_t lib, int ne02, int ne20); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mm_id (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_mul_mv_id (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_argmax (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_argsort (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_bin (ggml_metal_library_t lib, enum ggml_op op, int32_t n_fuse, bool row); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_l2_norm (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_group_norm (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_norm (ggml_metal_library_t lib, const struct ggml_tensor * op, int32_t n_fuse); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_rope (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_im2col (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_conv_transpose_1d (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_upscale (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pad (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_pad_reflect_1d (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_arange (ggml_metal_library_t lib, const struct ggml_tensor * op); +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_timestep_embedding(ggml_metal_library_t lib, const struct ggml_tensor * op); + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext( + ggml_metal_library_t lib, + const struct ggml_tensor * op, + bool has_mask, + bool has_sinks, + bool has_bias, + bool has_scap, + int32_t nsg); + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext_vec( + ggml_metal_library_t lib, + const struct ggml_tensor * op, + bool has_mask, + bool has_sinks, + bool has_bias, + bool has_scap, + int32_t nsg, + int32_t nwg); + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline_flash_attn_ext_vec_reduce( + ggml_metal_library_t lib, + const struct ggml_tensor * op, + int32_t dv, + int32_t nwg); + +// +// device +// + +struct ggml_metal_device_props { + char name[128]; + + size_t max_buffer_size; + size_t max_working_set_size; + size_t max_theadgroup_memory_size; + + bool has_simdgroup_reduction; + bool has_simdgroup_mm; + bool has_unified_memory; + bool has_bfloat; + bool use_residency_sets; + bool use_shared_buffers; + + bool supports_gpu_family_apple7; +}; + +ggml_metal_device_t ggml_metal_device_init(void); +void ggml_metal_device_free(ggml_metal_device_t dev); + +// return a singleton that is automatically destroyed when the program exits +ggml_metal_device_t ggml_metal_device_get(void); + +void * ggml_metal_device_get_obj (ggml_metal_device_t dev); // id +void * ggml_metal_device_get_queue(ggml_metal_device_t dev); // id + +ggml_metal_library_t ggml_metal_device_get_library(ggml_metal_device_t dev); + +void ggml_metal_device_get_memory(ggml_metal_device_t dev, size_t * free, size_t * total); +bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_tensor * op); + +const struct ggml_metal_device_props * ggml_metal_device_get_props(ggml_metal_device_t dev); + +// +// device buffers +// + +typedef struct ggml_metal_buffer * ggml_metal_buffer_t; + +ggml_metal_buffer_t ggml_metal_buffer_init(ggml_metal_device_t dev, size_t size, bool shared); +ggml_metal_buffer_t ggml_metal_buffer_map (ggml_metal_device_t dev, void * ptr, size_t size, size_t max_tensor_size); + +void ggml_metal_buffer_free (ggml_metal_buffer_t buf); +void * ggml_metal_buffer_get_base (ggml_metal_buffer_t buf); +bool ggml_metal_buffer_is_shared(ggml_metal_buffer_t buf); + +void ggml_metal_buffer_memset_tensor(ggml_metal_buffer_t buf, struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size); +void ggml_metal_buffer_set_tensor (ggml_metal_buffer_t buf, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size); +void ggml_metal_buffer_get_tensor (ggml_metal_buffer_t buf, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size); +void ggml_metal_buffer_clear (ggml_metal_buffer_t buf, uint8_t value); + +// finds the Metal buffer that contains the tensor data on the GPU device +// the assumption is that there is 1-to-1 mapping between the host and device memory buffers, so we can find the +// Metal buffer based on the host memory pointer +// +struct ggml_metal_buffer_id ggml_metal_buffer_get_id(ggml_metal_buffer_t buf, const struct ggml_tensor * t); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.m 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.m --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.m 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-device.m 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,1308 @@ +#import "ggml-metal-device.h" + +#import "ggml-impl.h" +#import "ggml-threading.h" + +#include + +#include + +#ifndef TARGET_OS_VISION +#define TARGET_OS_VISION 0 +#endif + +// create residency sets only on macOS >= 15.0 +#if !TARGET_CPU_X86_64 && TARGET_OS_OSX && __MAC_OS_X_VERSION_MAX_ALLOWED >= 150000 || \ + TARGET_OS_IOS && __IPHONE_OS_VERSION_MAX_ALLOWED >= 180000 || \ + TARGET_OS_TV && __TV_OS_VERSION_MAX_ALLOWED >= 180000 || \ + TARGET_OS_VISION && __VISION_OS_VERSION_MAX_ALLOWED >= 200000 +#define GGML_METAL_HAS_RESIDENCY_SETS 1 +#endif + +// overload of MTLGPUFamilyMetal3 (not available in some environments) +static const NSInteger MTLGPUFamilyMetal3_GGML = 5001; + +#if !GGML_METAL_EMBED_LIBRARY +// Here to assist with NSBundle Path Hack +@interface GGMLMetalClass : NSObject +@end +@implementation GGMLMetalClass +@end +#endif + +// +// MTLFunctionConstantValues wrapper +// + +struct ggml_metal_cv { + MTLFunctionConstantValues * obj; +}; + +ggml_metal_cv_t ggml_metal_cv_init(void) { + ggml_metal_cv_t res = calloc(1, sizeof(struct ggml_metal_cv)); + + res->obj = [[MTLFunctionConstantValues alloc] init]; + + return res; +} + +void ggml_metal_cv_free(ggml_metal_cv_t cv) { + [cv->obj release]; + free(cv); +} + +void ggml_metal_cv_set_int16(ggml_metal_cv_t cv, int16_t value, int32_t idx) { + [cv->obj setConstantValue:&value type:MTLDataTypeShort atIndex:idx]; +} + +void ggml_metal_cv_set_int32(ggml_metal_cv_t cv, int32_t value, int32_t idx) { + [cv->obj setConstantValue:&value type:MTLDataTypeInt atIndex:idx]; +} + +void ggml_metal_cv_set_bool(ggml_metal_cv_t cv, bool value, int32_t idx) { + [cv->obj setConstantValue:&value type:MTLDataTypeBool atIndex:idx]; +} + +// +// MTLComputePipelineState wrapper +// + +struct ggml_metal_pipeline { + id obj; + + // suggested dispatch sizes + int nsg; + + int nr0; + int nr1; + + size_t smem; +}; + +ggml_metal_pipeline_t ggml_metal_pipeline_init(void) { + ggml_metal_pipeline_t res = calloc(1, sizeof(struct ggml_metal_pipeline)); + + *res = (struct ggml_metal_pipeline) { + /*.obj =*/ nil, + /*.nsg =*/ 0, + /*.nr0 =*/ 0, + /*.nr1 =*/ 0, + /*.smem =*/ 0, + }; + + return res; +} + +void ggml_metal_pipeline_free(ggml_metal_pipeline_t pipeline) { + [pipeline->obj release]; + + free(pipeline); +} + +void ggml_metal_pipeline_set_nsg(ggml_metal_pipeline_t pipeline, int nsg) { + pipeline->nsg = nsg; +} + +int ggml_metal_pipeline_get_nsg(ggml_metal_pipeline_t pipeline) { + return pipeline->nsg; +} + +void ggml_metal_pipeline_set_nr0(ggml_metal_pipeline_t pipeline, int nr0) { + pipeline->nr0 = nr0; +} + +int ggml_metal_pipeline_get_nr0(ggml_metal_pipeline_t pipeline) { + return pipeline->nr0; +} + +void ggml_metal_pipeline_set_nr1(ggml_metal_pipeline_t pipeline, int nr1) { + pipeline->nr1 = nr1; +} + +int ggml_metal_pipeline_get_nr1(ggml_metal_pipeline_t pipeline) { + return pipeline->nr1; +} + +void ggml_metal_pipeline_set_smem(ggml_metal_pipeline_t pipeline, size_t smem) { + pipeline->smem = smem; +} + +size_t ggml_metal_pipeline_get_smem(ggml_metal_pipeline_t pipeline) { + return pipeline->smem; +} + +int ggml_metal_pipeline_max_theads_per_threadgroup(ggml_metal_pipeline_t pipeline) { + return pipeline->obj.maxTotalThreadsPerThreadgroup; +} + +struct ggml_metal_library { + id obj; + id device; + + ggml_metal_pipelines_t pipelines; // cache of compiled pipelines +}; + +ggml_metal_library_t ggml_metal_library_init(ggml_metal_device_t dev) { + id library = nil; + id device = ggml_metal_device_get_obj(dev); + + // load library + // + // - first check if the library is embedded + // - then check if the library is in the bundle + // - if not found, load the source and compile it + // - if that fails, return NULL + // + // TODO: move to a function + { + const int64_t t_start = ggml_time_us(); + + NSError * error = nil; + NSString * src = nil; + +#if GGML_METAL_EMBED_LIBRARY + GGML_LOG_INFO("%s: using embedded metal library\n", __func__); + + extern const char ggml_metallib_start[]; + extern const char ggml_metallib_end[]; + + src = [[NSString alloc] initWithBytes:ggml_metallib_start length:(ggml_metallib_end-ggml_metallib_start) encoding:NSUTF8StringEncoding]; +#else + +#ifdef SWIFT_PACKAGE + NSBundle * bundle = SWIFTPM_MODULE_BUNDLE; +#else + NSBundle * bundle = [NSBundle bundleForClass:[GGMLMetalClass class]]; +#endif + + NSString * path_lib = [bundle pathForResource:@"default" ofType:@"metallib"]; + if (path_lib == nil) { + // Try to find the resource in the directory where the current binary located. + NSString * bin_cur = [[NSProcessInfo processInfo] arguments][0]; + NSString * bin_dir = [bin_cur stringByDeletingLastPathComponent]; + + NSString * path_lib_default = [NSString pathWithComponents:@[bin_dir, @"default.metallib"]]; + if ([[NSFileManager defaultManager] isReadableFileAtPath:path_lib_default]) { + GGML_LOG_INFO("%s: found '%s'\n", __func__, [path_lib_default UTF8String]); + + NSDictionary * atts = [[NSFileManager defaultManager] attributesOfItemAtPath:path_lib_default error:&error]; + if (atts && atts[NSFileType] == NSFileTypeSymbolicLink) { + // Optionally, if this is a symlink, try to resolve it. + path_lib_default = [[NSFileManager defaultManager] destinationOfSymbolicLinkAtPath:path_lib_default error:&error]; + if (path_lib_default && [path_lib_default length] > 0 && ![[path_lib_default substringToIndex:1] isEqualToString:@"/"]) { + // It is a relative path, adding the binary directory as directory prefix. + path_lib_default = [NSString pathWithComponents:@[bin_dir, path_lib_default]]; + } + if (!path_lib_default || ![[NSFileManager defaultManager] isReadableFileAtPath:path_lib_default]) { + // Link to the resource could not be resolved. + path_lib_default = nil; + } else { + GGML_LOG_INFO("%s: symlink resolved '%s'\n", __func__, [path_lib_default UTF8String]); + } + } + } else { + // The resource couldn't be found in the binary's directory. + path_lib_default = nil; + } + + path_lib = path_lib_default; + } + + if (path_lib != nil) { + // pre-compiled library found + NSURL * libURL = [NSURL fileURLWithPath:path_lib]; + GGML_LOG_INFO("%s: loading '%s'\n", __func__, [path_lib UTF8String]); + + library = [device newLibraryWithURL:libURL error:&error]; + if (error) { + GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); + return nil; + } + } else { + GGML_LOG_INFO("%s: default.metallib not found, loading from source\n", __func__); + + NSString * path_source; + NSString * path_resource = [[NSProcessInfo processInfo].environment objectForKey:@"GGML_METAL_PATH_RESOURCES"]; + + GGML_LOG_INFO("%s: GGML_METAL_PATH_RESOURCES = %s\n", __func__, path_resource ? [path_resource UTF8String] : "nil"); + + if (path_resource) { + path_source = [path_resource stringByAppendingPathComponent:@"ggml-metal.metal"]; + } else { + path_source = [bundle pathForResource:@"ggml-metal" ofType:@"metal"]; + } + + if (path_source == nil) { + GGML_LOG_WARN("%s: error: could not use bundle path to find ggml-metal.metal, falling back to trying cwd\n", __func__); + path_source = @"ggml-metal.metal"; + } + + GGML_LOG_INFO("%s: loading '%s'\n", __func__, [path_source UTF8String]); + + src = [NSString stringWithContentsOfFile:path_source encoding:NSUTF8StringEncoding error:&error]; + if (error) { + GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); + return nil; + } + } +#endif + + if (!library) { + @autoreleasepool { + // dictionary of preprocessor macros + NSMutableDictionary * prep = [NSMutableDictionary dictionary]; + + if (ggml_metal_device_get_props(dev)->has_bfloat) { + [prep setObject:@"1" forKey:@"GGML_METAL_HAS_BF16"]; + } + +#if GGML_METAL_EMBED_LIBRARY + [prep setObject:@"1" forKey:@"GGML_METAL_EMBED_LIBRARY"]; +#endif + + MTLCompileOptions * options = [MTLCompileOptions new]; + options.preprocessorMacros = prep; + + //[options setFastMathEnabled:false]; + + library = [device newLibraryWithSource:src options:options error:&error]; + if (error) { + GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); + return nil; + } + +#if !__has_feature(objc_arc) + [options release]; +#endif + } + } + +#if GGML_METAL_EMBED_LIBRARY + [src release]; +#endif // GGML_METAL_EMBED_LIBRARY + + GGML_LOG_INFO("%s: loaded in %.3f sec\n", __func__, (ggml_time_us() - t_start) / 1e6); + } + + ggml_metal_library_t res = calloc(1, sizeof(struct ggml_metal_library)); + + res->obj = library; + res->device = device; + res->pipelines = ggml_metal_pipelines_init(); + + return res; +} + +void ggml_metal_library_free(ggml_metal_library_t lib) { + if (!lib) { + return; + } + + if (lib->obj) { + [lib->obj release]; + } + + ggml_metal_pipelines_free(lib->pipelines); + + free(lib); +} + +ggml_metal_pipeline_t ggml_metal_library_get_pipeline(ggml_metal_library_t lib, const char * name) { + return ggml_metal_pipelines_get(lib->pipelines, name); +} + +ggml_metal_pipeline_t ggml_metal_library_compile_pipeline(ggml_metal_library_t lib, const char * base, const char * name, ggml_metal_cv_t cv) { + // note: the pipelines are cached in the library per device, so they are shared across all metal contexts + ggml_critical_section_start(); + + ggml_metal_pipeline_t res = ggml_metal_library_get_pipeline(lib, name); + if (res) { + ggml_critical_section_end(); + + return res; + } + + res = ggml_metal_pipeline_init(); + + @autoreleasepool { + NSError * error = nil; + + NSString * base_func = [NSString stringWithUTF8String:base]; + + GGML_LOG_DEBUG("%s: compiling pipeline: base = '%s', name = '%s'\n", __func__, base, name); + + id mtl_function; + if (!cv) { + mtl_function = [lib->obj newFunctionWithName:base_func]; + } else { + mtl_function = [lib->obj newFunctionWithName:base_func constantValues:cv->obj error:&error]; + } + if (!mtl_function) { + ggml_critical_section_end(); + + GGML_LOG_ERROR("%s: error: failed to compile pipeline: base = '%s', name = '%s'\n", __func__, base, name); + if (error) { + GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); + } + + return nil; + } + + res->obj = [lib->device newComputePipelineStateWithFunction:mtl_function error:&error]; + + ggml_metal_pipelines_add(lib->pipelines, name, res); + + [mtl_function release]; + + GGML_LOG_DEBUG("%s: loaded %-40s %16p | th_max = %4d | th_width = %4d\n", __func__, name, (void *) res->obj, + (int) res->obj.maxTotalThreadsPerThreadgroup, + (int) res->obj.threadExecutionWidth); + } + + ggml_critical_section_end(); + + return res; +} + +// +// MTLComputeCommandEncoder wrapper +// + +struct ggml_metal_encoder { + id obj; +}; + +ggml_metal_encoder_t ggml_metal_encoder_init(ggml_metal_cmd_buf_t cmd_buf_raw, bool concurrent) { + ggml_metal_encoder_t res = calloc(1, sizeof(struct ggml_metal_encoder)); + + id cmd_buf = (id) cmd_buf_raw; + + if (concurrent) { + res->obj = [cmd_buf computeCommandEncoderWithDispatchType: MTLDispatchTypeConcurrent]; + } else { + res->obj = [cmd_buf computeCommandEncoder]; + } + + [res->obj retain]; + + return res; +} + +void ggml_metal_encoder_free(ggml_metal_encoder_t encoder) { + [encoder->obj release]; + free(encoder); +} + +void ggml_metal_encoder_debug_group_push(ggml_metal_encoder_t encoder, const char * name) { + [encoder->obj pushDebugGroup:[NSString stringWithCString:name encoding:NSUTF8StringEncoding]]; +} + +void ggml_metal_encoder_debug_group_pop (ggml_metal_encoder_t encoder) { + [encoder->obj popDebugGroup]; +} + +void ggml_metal_encoder_set_pipeline(ggml_metal_encoder_t encoder, ggml_metal_pipeline_t pipeline) { + [encoder->obj setComputePipelineState:pipeline->obj]; +} + +void ggml_metal_encoder_set_bytes(ggml_metal_encoder_t encoder, void * data, size_t size, int idx) { + [encoder->obj setBytes:data length:size atIndex:idx]; +} + +void ggml_metal_encoder_set_buffer(ggml_metal_encoder_t encoder, struct ggml_metal_buffer_id buffer, int idx) { + [encoder->obj setBuffer:buffer.metal offset:buffer.offs atIndex:idx]; +} + +void ggml_metal_encoder_set_threadgroup_memory_size(ggml_metal_encoder_t encoder, size_t size, int idx) { + [encoder->obj setThreadgroupMemoryLength:size atIndex:idx]; +} + +void ggml_metal_encoder_dispatch_threadgroups(ggml_metal_encoder_t encoder, int tg0, int tg1, int tg2, int tptg0, int tptg1, int tptg2) { + [encoder->obj dispatchThreadgroups:MTLSizeMake(tg0, tg1, tg2) threadsPerThreadgroup:MTLSizeMake(tptg0, tptg1, tptg2)]; +} + +void ggml_metal_encoder_memory_barrier(ggml_metal_encoder_t encoder) { + [encoder->obj memoryBarrierWithScope:MTLBarrierScopeBuffers]; +} + +void ggml_metal_encoder_end_encoding(ggml_metal_encoder_t encoder) { + [encoder->obj endEncoding]; +} + +struct ggml_metal_device { + id mtl_device; + + // a single global queue shared by all Metal backends + // technically not needed for devices with unified memory, but enables discrete GPUs support + // ref: https://github.com/ggml-org/llama.cpp/pull/15906 + id mtl_queue; + + ggml_metal_library_t library; + + struct ggml_metal_device_props props; +}; + +ggml_metal_device_t ggml_metal_device_init(void) { + ggml_metal_device_t dev = calloc(1, sizeof(struct ggml_metal_device)); + + assert(dev != NULL); + + if (dev->mtl_device == nil) { + dev->mtl_device = MTLCreateSystemDefaultDevice(); + + if (dev->mtl_device) { + dev->mtl_queue = [dev->mtl_device newCommandQueue]; + if (dev->mtl_queue == nil) { + GGML_LOG_ERROR("%s: error: failed to create command queue\n", __func__); + } + + dev->props.has_simdgroup_reduction = [dev->mtl_device supportsFamily:MTLGPUFamilyApple7]; + dev->props.has_simdgroup_reduction |= [dev->mtl_device supportsFamily:MTLGPUFamilyMetal3_GGML]; + + dev->props.has_simdgroup_mm = [dev->mtl_device supportsFamily:MTLGPUFamilyApple7]; + dev->props.has_unified_memory = dev->mtl_device.hasUnifiedMemory; + + dev->props.has_bfloat = [dev->mtl_device supportsFamily:MTLGPUFamilyMetal3_GGML]; + dev->props.has_bfloat |= [dev->mtl_device supportsFamily:MTLGPUFamilyApple6]; + + dev->props.use_residency_sets = true; +#if defined(GGML_METAL_HAS_RESIDENCY_SETS) + dev->props.use_residency_sets = getenv("GGML_METAL_NO_RESIDENCY") == nil; +#endif + + dev->props.use_shared_buffers = dev->props.has_unified_memory; + + if (getenv("GGML_METAL_SHARED_BUFFERS_DISABLE") != NULL) { + dev->props.use_shared_buffers = false; + } + + dev->props.supports_gpu_family_apple7 = [dev->mtl_device supportsFamily:MTLGPUFamilyApple7]; + + dev->props.max_buffer_size = dev->mtl_device.maxBufferLength; + dev->props.max_working_set_size = dev->mtl_device.recommendedMaxWorkingSetSize; + dev->props.max_theadgroup_memory_size = dev->mtl_device.maxThreadgroupMemoryLength; + + strncpy(dev->props.name, [[dev->mtl_device name] UTF8String], sizeof(dev->props.name) - 1); + + dev->library = ggml_metal_library_init(dev); + if (!dev->library) { + GGML_LOG_ERROR("%s: error: failed to create library\n", __func__); + } + + // -------------------------------------------------- + + // print MTL GPU family: + GGML_LOG_INFO("%s: GPU name: %s\n", __func__, dev->props.name); + + // determine max supported GPU family + // https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf + // https://developer.apple.com/metal/Metal-Feature-Set-Tables.pdf + { + for (int i = MTLGPUFamilyApple1 + 20; i >= MTLGPUFamilyApple1; --i) { + if ([dev->mtl_device supportsFamily:i]) { + GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyApple%d (%d)\n", __func__, i - (int) MTLGPUFamilyApple1 + 1, i); + break; + } + } + + for (int i = MTLGPUFamilyCommon1 + 5; i >= MTLGPUFamilyCommon1; --i) { + if ([dev->mtl_device supportsFamily:i]) { + GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyCommon%d (%d)\n", __func__, i - (int) MTLGPUFamilyCommon1 + 1, i); + break; + } + } + + for (int i = MTLGPUFamilyMetal3_GGML + 5; i >= MTLGPUFamilyMetal3_GGML; --i) { + if ([dev->mtl_device supportsFamily:i]) { + GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyMetal%d (%d)\n", __func__, i - (int) MTLGPUFamilyMetal3_GGML + 3, i); + break; + } + } + } + + GGML_LOG_INFO("%s: simdgroup reduction = %s\n", __func__, dev->props.has_simdgroup_reduction ? "true" : "false"); + GGML_LOG_INFO("%s: simdgroup matrix mul. = %s\n", __func__, dev->props.has_simdgroup_mm ? "true" : "false"); + GGML_LOG_INFO("%s: has unified memory = %s\n", __func__, dev->props.has_unified_memory ? "true" : "false"); + GGML_LOG_INFO("%s: has bfloat = %s\n", __func__, dev->props.has_bfloat ? "true" : "false"); + GGML_LOG_INFO("%s: use residency sets = %s\n", __func__, dev->props.use_residency_sets ? "true" : "false"); + GGML_LOG_INFO("%s: use shared buffers = %s\n", __func__, dev->props.use_shared_buffers ? "true" : "false"); + +#if TARGET_OS_OSX || (TARGET_OS_IOS && __clang_major__ >= 15) + if (@available(macOS 10.12, iOS 16.0, *)) { + GGML_LOG_INFO("%s: recommendedMaxWorkingSetSize = %8.2f MB\n", __func__, dev->props.max_working_set_size / 1e6); + } +#endif + } + } + + return dev; +} + +void ggml_metal_device_free(ggml_metal_device_t dev) { + assert(dev != NULL); + + ggml_metal_library_free(dev->library); + dev->library = NULL; + + if (dev->mtl_queue) { + [dev->mtl_queue release]; + dev->mtl_queue = nil; + } + + if (dev->mtl_device) { + [dev->mtl_device release]; + dev->mtl_device = nil; + } + + free(dev); +} + +void * ggml_metal_device_get_obj(ggml_metal_device_t dev) { + return dev->mtl_device; +} + +void * ggml_metal_device_get_queue(ggml_metal_device_t dev) { + return dev->mtl_queue; +} + +ggml_metal_library_t ggml_metal_device_get_library(ggml_metal_device_t dev) { + return dev->library; +} + +void ggml_metal_device_get_memory(ggml_metal_device_t dev, size_t * free, size_t * total) { + if (@available(macOS 10.12, iOS 16.0, *)) { + *total = dev->mtl_device.recommendedMaxWorkingSetSize; + *free = *total - dev->mtl_device.currentAllocatedSize; + } else { + *free = 0; + *total = 0; + } +} + +bool ggml_metal_device_supports_op(ggml_metal_device_t dev, const struct ggml_tensor * op) { + const bool has_simdgroup_mm = dev->props.has_simdgroup_mm; + const bool has_simdgroup_reduction = dev->props.has_simdgroup_reduction; + const bool has_bfloat = dev->props.has_bfloat; + + if (!has_bfloat) { + if (op->type == GGML_TYPE_BF16) { + return false; + } + + for (size_t i = 0, n = 3; i < n; ++i) { + if (op->src[i] != NULL && op->src[i]->type == GGML_TYPE_BF16) { + return false; + } + } + } + + switch (op->op) { + case GGML_OP_UNARY: + switch (ggml_get_unary_op(op)) { + case GGML_UNARY_OP_TANH: + case GGML_UNARY_OP_RELU: + case GGML_UNARY_OP_SIGMOID: + case GGML_UNARY_OP_GELU: + case GGML_UNARY_OP_GELU_ERF: + case GGML_UNARY_OP_GELU_QUICK: + case GGML_UNARY_OP_SILU: + case GGML_UNARY_OP_ELU: + case GGML_UNARY_OP_NEG: + case GGML_UNARY_OP_ABS: + case GGML_UNARY_OP_SGN: + case GGML_UNARY_OP_STEP: + case GGML_UNARY_OP_HARDSWISH: + case GGML_UNARY_OP_HARDSIGMOID: + case GGML_UNARY_OP_EXP: + return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; + default: + return false; + } + case GGML_OP_GLU: + switch (ggml_get_glu_op(op)) { + case GGML_GLU_OP_REGLU: + case GGML_GLU_OP_GEGLU: + case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: + case GGML_GLU_OP_GEGLU_ERF: + case GGML_GLU_OP_GEGLU_QUICK: + return ggml_is_contiguous_1(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; + default: + return false; + } + case GGML_OP_NONE: + case GGML_OP_RESHAPE: + case GGML_OP_VIEW: + case GGML_OP_TRANSPOSE: + case GGML_OP_PERMUTE: + case GGML_OP_CONCAT: + return true; + case GGML_OP_ADD: + case GGML_OP_SUB: + case GGML_OP_MUL: + case GGML_OP_DIV: + case GGML_OP_ADD_ID: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_ACC: + case GGML_OP_REPEAT: + case GGML_OP_SCALE: + case GGML_OP_CONV_TRANSPOSE_1D: + return true; + case GGML_OP_CLAMP: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_SQR: + case GGML_OP_SQRT: + case GGML_OP_SIN: + case GGML_OP_COS: + case GGML_OP_LOG: + return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_SUM_ROWS: + case GGML_OP_MEAN: + case GGML_OP_SOFT_MAX: + case GGML_OP_GROUP_NORM: + return has_simdgroup_reduction && ggml_is_contiguous_rows(op->src[0]); + case GGML_OP_L2_NORM: + return has_simdgroup_reduction && (op->ne[0] % 4 == 0 && ggml_is_contiguous_1(op->src[0])); + case GGML_OP_ARGMAX: + return has_simdgroup_reduction; + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + return has_simdgroup_reduction && (ggml_is_contiguous_rows(op->src[0])); + case GGML_OP_ROPE: + return true; + case GGML_OP_IM2COL: + return ggml_is_contiguous(op->src[1]) && op->src[1]->type == GGML_TYPE_F32 && (op->type == GGML_TYPE_F16 || op->type == GGML_TYPE_F32); + case GGML_OP_POOL_1D: + return false; + case GGML_OP_UPSCALE: + return op->src[0]->type == GGML_TYPE_F32 && op->op_params[0] == GGML_SCALE_MODE_NEAREST; + case GGML_OP_POOL_2D: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_PAD: + return (ggml_get_op_params_i32(op, 0) == 0) && (ggml_get_op_params_i32(op, 2) == 0) && + (ggml_get_op_params_i32(op, 4) == 0) && (ggml_get_op_params_i32(op, 6) == 0); + case GGML_OP_PAD_REFLECT_1D: + case GGML_OP_TIMESTEP_EMBEDDING: + case GGML_OP_LEAKY_RELU: + return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_ARGSORT: + // TODO: Support arbitrary column width + return op->src[0]->ne[0] <= 1024; + case GGML_OP_ARANGE: + return true; + case GGML_OP_FLASH_ATTN_EXT: + // for new head sizes, add checks here + if (op->src[0]->ne[0] != 40 && + op->src[0]->ne[0] != 64 && + op->src[0]->ne[0] != 80 && + op->src[0]->ne[0] != 96 && + op->src[0]->ne[0] != 112 && + op->src[0]->ne[0] != 128 && + op->src[0]->ne[0] != 192 && + op->src[0]->ne[0] != 256) { + return false; + } + if (op->src[0]->ne[0] == 576) { + // DeepSeek sizes + // TODO: disabled for now, until optmized + return false; + } + if (op->src[1]->type != op->src[2]->type) { + return false; + } + return has_simdgroup_mm; // TODO: over-restricted for vec-kernels + case GGML_OP_SSM_CONV: + case GGML_OP_SSM_SCAN: + return has_simdgroup_reduction; + case GGML_OP_RWKV_WKV6: + case GGML_OP_RWKV_WKV7: + return true; + case GGML_OP_MUL_MAT: + case GGML_OP_MUL_MAT_ID: + return has_simdgroup_reduction; + case GGML_OP_CPY: + case GGML_OP_DUP: + case GGML_OP_CONT: + { + switch (op->src[0]->type) { + case GGML_TYPE_F32: + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + case GGML_TYPE_BF16: + case GGML_TYPE_Q8_0: + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: + case GGML_TYPE_IQ4_NL: + case GGML_TYPE_I32: + return true; + default: + return false; + } + case GGML_TYPE_F16: + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + return true; + default: + return false; + } + case GGML_TYPE_BF16: + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_BF16: + return true; + default: + return false; + } + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: + case GGML_TYPE_Q8_0: + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + return true; + default: + return false; + } + case GGML_TYPE_I32: + return op->type == GGML_TYPE_F32; + default: + return false; + }; + } + case GGML_OP_GET_ROWS: + { + return op->ne[3] == 1; + } + case GGML_OP_SET_ROWS: + { + if (op->src[0]->type != GGML_TYPE_F32) { + return false; + } + + switch (op->type) { + case GGML_TYPE_F32: + case GGML_TYPE_F16: + case GGML_TYPE_BF16: + case GGML_TYPE_Q8_0: + case GGML_TYPE_Q4_0: + case GGML_TYPE_Q4_1: + case GGML_TYPE_Q5_0: + case GGML_TYPE_Q5_1: + case GGML_TYPE_IQ4_NL: + return true; + default: + return false; + }; + } + default: + return false; + } +} + +const struct ggml_metal_device_props * ggml_metal_device_get_props(ggml_metal_device_t dev) { + return &dev->props; +} + +// +// device buffers +// + +// max memory buffers that can be mapped to the device +#define GGML_METAL_MAX_BUFFERS 64 + +struct ggml_metal_buffer_wrapper { + void * data; + size_t size; + + id metal; +}; + +struct ggml_metal_buffer { + void * all_data; // TODO: https://github.com/ggml-org/llama.cpp/pull/15985 + size_t all_size; + + // if false, the Metal buffer data is allocated in private GPU memory and is not shared with the host + bool is_shared; + bool owned; + + // multiple buffers are used only to avoid the maximum buffer size limitation when using mmap + int n_buffers; + struct ggml_metal_buffer_wrapper buffers[GGML_METAL_MAX_BUFFERS]; + + bool use_residency_sets; + + // optional MTLResidencySet + // note: cannot use explicity "id" here because it is not available on certain OSes + id rset; + + // pointers to global device objects + id device; + id queue; +}; + +static void ggml_metal_log_allocated_size(id device, size_t size_aligned) { +#ifndef GGML_METAL_NDEBUG +#if TARGET_OS_OSX || (TARGET_OS_IOS && __clang_major__ >= 15) + if (@available(macOS 10.12, iOS 16.0, *)) { + GGML_LOG_DEBUG("%s: allocated buffer, size = %8.2f MiB, (%8.2f / %8.2f)\n", + __func__, + size_aligned / 1024.0 / 1024.0, + device.currentAllocatedSize / 1024.0 / 1024.0, + device.recommendedMaxWorkingSetSize / 1024.0 / 1024.0); + + if (device.currentAllocatedSize > device.recommendedMaxWorkingSetSize) { + GGML_LOG_WARN("%s: warning: current allocated size is greater than the recommended max working set size\n", __func__); + } + } else { + GGML_LOG_INFO("%s: allocated buffer, size = %8.2f MiB, (%8.2f)\n", + __func__, + size_aligned / 1024.0 / 1024.0, + device.currentAllocatedSize / 1024.0 / 1024.0); + } +#endif +#endif + GGML_UNUSED(device); + GGML_UNUSED(size_aligned); +} + +// rset init +static bool ggml_metal_buffer_rset_init(ggml_metal_buffer_t buf) { + buf->rset = nil; + + if (!buf->use_residency_sets) { + return true; + } + +#if defined(GGML_METAL_HAS_RESIDENCY_SETS) + if (@available(macOS 15.0, iOS 18.0, tvOS 18.0, visionOS 2.0, *)) { + MTLResidencySetDescriptor * desc = [[MTLResidencySetDescriptor alloc] init]; + desc.label = @"ggml_metal"; + desc.initialCapacity = buf->n_buffers; + + NSError * error; + buf->rset = [buf->device newResidencySetWithDescriptor:desc error:&error]; + if (error) { + GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); + [desc release]; + return false; + } + + [desc release]; + + for (int i = 0; i < buf->n_buffers; i++) { + [buf->rset addAllocation:buf->buffers[i].metal]; + } + + [buf->rset commit]; + [buf->rset requestResidency]; + + return true; + } +#endif + + return true; +} + +// rset free +static void ggml_metal_buffer_rset_free(ggml_metal_buffer_t buf) { +#if defined(GGML_METAL_HAS_RESIDENCY_SETS) + if (@available(macOS 15.0, iOS 18.0, tvOS 18.0, visionOS 2.0, *)) { + if (buf->rset) { + [buf->rset endResidency]; + [buf->rset removeAllAllocations]; + [buf->rset release]; + } + } +#else + GGML_UNUSED(buf); +#endif +} + +static void * ggml_metal_host_malloc(size_t n) { + void * data = NULL; + +#if TARGET_OS_OSX + kern_return_t err = vm_allocate((vm_map_t) mach_task_self(), (void *) &data, n, VM_FLAGS_ANYWHERE); + if (err != KERN_SUCCESS) { + GGML_LOG_ERROR("%s: error: vm_allocate failed\n", __func__); + return NULL; + } +#else + const int result = posix_memalign((void **) &data, sysconf(_SC_PAGESIZE), n); + if (result != 0) { + GGML_LOG_ERROR("%s: error: posix_memalign failed\n", __func__); + return NULL; + } +#endif + + return data; +} + +ggml_metal_buffer_t ggml_metal_buffer_init(ggml_metal_device_t dev, size_t size, bool shared) { + ggml_metal_buffer_t res = calloc(1, sizeof(struct ggml_metal_buffer)); + + const size_t size_page = sysconf(_SC_PAGESIZE); + + size_t size_aligned = size; + if ((size_aligned % size_page) != 0) { + size_aligned += (size_page - (size_aligned % size_page)); + } + + const struct ggml_metal_device_props * props_dev = ggml_metal_device_get_props(dev); + + shared = shared && props_dev->use_shared_buffers; + + // allocate shared buffer if the device supports it and it is required by the buffer type + if (shared) { + res->all_data = ggml_metal_host_malloc(size_aligned); + res->is_shared = true; + res->owned = true; + } else { + // dummy, non-NULL value - we'll populate this after creating the Metal buffer below + res->all_data = (void *) 0x000000400ULL; + res->is_shared = false; + } + res->all_size = size_aligned; + + res->device = ggml_metal_device_get_obj(dev); + res->queue = ggml_metal_device_get_queue(dev); + + res->n_buffers = 1; + + if (res->all_data != NULL) { + res->buffers[0].size = size; + res->buffers[0].metal = nil; + + if (size_aligned > 0) { + if (props_dev->use_shared_buffers &&shared) { + res->buffers[0].metal = [res->device newBufferWithBytesNoCopy:res->all_data + length:size_aligned + options:MTLResourceStorageModeShared + deallocator:nil]; + } else { + res->buffers[0].metal = [res->device newBufferWithLength:size_aligned options:MTLResourceStorageModePrivate]; + + res->all_data = (void *) (res->buffers[0].metal.gpuAddress); + } + } + + res->buffers[0].data = res->all_data; + } + + if (size_aligned > 0 && (res->all_data == NULL || res->buffers[0].metal == nil)) { + GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_aligned / 1024.0 / 1024.0); + free(res); + return NULL; + } + + res->use_residency_sets = props_dev->use_residency_sets; + + if (!ggml_metal_buffer_rset_init(res)) { + GGML_LOG_ERROR("%s: error: failed to initialize residency set\n", __func__); + free(res); + return NULL; + } + + //ggml_metal_log_allocated_size(device, size_aligned); + + return res; +} + +ggml_metal_buffer_t ggml_metal_buffer_map(ggml_metal_device_t dev, void * ptr, size_t size, size_t max_tensor_size) { + ggml_metal_buffer_t res = calloc(1, sizeof(struct ggml_metal_buffer)); + + res->all_data = ptr; + res->all_size = size; + + res->is_shared = true; + res->owned = false; + + res->n_buffers = 0; + + const size_t size_page = sysconf(_SC_PAGESIZE); + + // page-align the data ptr + { + const uintptr_t offs = (uintptr_t) ptr % size_page; + ptr = (void *) ((char *) ptr - offs); + size += offs; + } + + size_t size_aligned = size; + if ((size_aligned % size_page) != 0) { + size_aligned += (size_page - (size_aligned % size_page)); + } + + res->device = ggml_metal_device_get_obj(dev); + res->queue = ggml_metal_device_get_queue(dev); + + const struct ggml_metal_device_props * props_dev = ggml_metal_device_get_props(dev); + + // the buffer fits into the max buffer size allowed by the device + if (size_aligned <= props_dev->max_buffer_size) { + res->buffers[res->n_buffers].data = ptr; + res->buffers[res->n_buffers].size = size; + res->buffers[res->n_buffers].metal = nil; + + if (size_aligned > 0) { + res->buffers[res->n_buffers].metal = [res->device newBufferWithBytesNoCopy:ptr length:size_aligned options:MTLResourceStorageModeShared deallocator:nil]; + + if (res->buffers[res->n_buffers].metal == nil) { + GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_aligned / 1024.0 / 1024.0); + free(res); + return NULL; + } + } + + ggml_metal_log_allocated_size(res->device, size_aligned); + + ++res->n_buffers; + } else { + // this overlap between the views will guarantee that the tensor with the maximum size will fully fit into + // one of the views + const size_t size_ovlp = ((max_tensor_size + size_page - 1) / size_page + 1) * size_page; // round-up 2 pages just in case + const size_t size_step = props_dev->max_buffer_size - size_ovlp; + const size_t size_view = props_dev->max_buffer_size; + + for (size_t i = 0; i < size; i += size_step) { + const size_t size_step_aligned = (i + size_view <= size) ? size_view : (size_aligned - i); + + res->buffers[res->n_buffers].data = (void *) ((uint8_t *) ptr + i); + res->buffers[res->n_buffers].size = size_step_aligned; + res->buffers[res->n_buffers].metal = nil; + + if (size_step_aligned > 0) { + res->buffers[res->n_buffers].metal = [res->device newBufferWithBytesNoCopy:(void *) ((uint8_t *) ptr + i) length:size_step_aligned options:MTLResourceStorageModeShared deallocator:nil]; + + if (res->buffers[res->n_buffers].metal == nil) { + GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_step_aligned / 1024.0 / 1024.0); + free(res); + return NULL; + } + } + + ggml_metal_log_allocated_size(res->device, size_step_aligned); + + if (i + size_step < size) { + GGML_LOG_INFO("\n"); + } + + ++res->n_buffers; + } + } + + res->use_residency_sets = props_dev->use_residency_sets; + + if (!ggml_metal_buffer_rset_init(res)) { + GGML_LOG_ERROR("%s: error: failed to initialize residency set\n", __func__); + free(res); + return NULL; + } + + return res; +} + +void ggml_metal_buffer_free(ggml_metal_buffer_t buf) { + for (int i = 0; i < buf->n_buffers; i++) { + [buf->buffers[i].metal release]; + } + + ggml_metal_buffer_rset_free(buf); + + if (buf->is_shared && buf->owned) { +#if TARGET_OS_OSX + vm_deallocate((vm_map_t)mach_task_self(), (vm_address_t)buf->all_data, buf->all_size); +#else + free(buf->all_data); +#endif + } + + free(buf); +} + +void * ggml_metal_buffer_get_base(ggml_metal_buffer_t buf) { + return buf->all_data; +} + +bool ggml_metal_buffer_is_shared(ggml_metal_buffer_t buf) { + return buf->is_shared; +} + +void ggml_metal_buffer_memset_tensor(ggml_metal_buffer_t buf, struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { + if (buf->is_shared) { + memset((char *)tensor->data + offset, value, size); + return; + } + + @autoreleasepool { + // dst + struct ggml_metal_buffer_id bid_dst = ggml_metal_buffer_get_id(buf, tensor); + bid_dst.offs += offset; + + id queue = buf->queue; + id cmd_buf = [queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder fillBuffer:bid_dst.metal + range:NSMakeRange(bid_dst.offs, bid_dst.offs + size) + value:value]; + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + } +} + +void ggml_metal_buffer_set_tensor(ggml_metal_buffer_t buf, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + if (buf->is_shared) { + memcpy((char *)tensor->data + offset, data, size); + return; + } + + @autoreleasepool { + // src + void * data_ptr = (void *)(uintptr_t) data; // "const cast" the src data + id buf_src = [buf->device newBufferWithBytesNoCopy:data_ptr + length:size + options:MTLResourceStorageModeShared + deallocator:nil]; + + GGML_ASSERT(buf_src); + + // dst + struct ggml_metal_buffer_id bid_dst = ggml_metal_buffer_get_id(buf, tensor); + bid_dst.offs += offset; + + // note: for experimentation purposes, here we use a semaphore to wait for the copy to complete + // this is alternative to waitUntilCompleted, which should be faster, but don't seem to make much difference + dispatch_semaphore_t completion_semaphore = dispatch_semaphore_create(0); + + id queue = buf->queue; + id cmd_buf = [queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder copyFromBuffer:buf_src + sourceOffset:0 + toBuffer:bid_dst.metal + destinationOffset:bid_dst.offs + size:size]; + + [encoder endEncoding]; + } + + [cmd_buf addCompletedHandler:^(id cb) { + // TODO: can check for errors here + GGML_UNUSED(cb); + + dispatch_semaphore_signal(completion_semaphore); + }]; + + [cmd_buf commit]; + + dispatch_semaphore_wait(completion_semaphore, DISPATCH_TIME_FOREVER); + dispatch_release(completion_semaphore); + + //[cmd_buf waitUntilCompleted]; + } +} + +void ggml_metal_buffer_get_tensor(ggml_metal_buffer_t buf, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size) { + if (buf->is_shared) { + memcpy(data, (const char *)tensor->data + offset, size); + return; + } + + @autoreleasepool { + // src + struct ggml_metal_buffer_id bid_src = ggml_metal_buffer_get_id(buf, tensor); + bid_src.offs += offset; + + // dst + id buf_dst = [buf->device newBufferWithBytesNoCopy:data + length:size + options:MTLResourceStorageModeShared + deallocator:nil]; + + GGML_ASSERT(buf_dst); + + id queue = buf->queue; + id cmd_buf = [queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder copyFromBuffer:bid_src.metal + sourceOffset:bid_src.offs + toBuffer:buf_dst + destinationOffset:0 + size:size]; + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + } +} + +void ggml_metal_buffer_clear(ggml_metal_buffer_t buf, uint8_t value) { + if (buf->is_shared) { + memset(buf->all_data, value, buf->all_size); + return; + } + + @autoreleasepool { + id queue = buf->queue; + id cmd_buf = [queue commandBufferWithUnretainedReferences]; + + { + id encoder = [cmd_buf blitCommandEncoder]; + + [encoder fillBuffer:buf->buffers[0].metal + range:NSMakeRange(0, buf->buffers[0].size) + value:value]; + + [encoder endEncoding]; + } + + [cmd_buf commit]; + [cmd_buf waitUntilCompleted]; + } +} + +struct ggml_metal_buffer_id ggml_metal_buffer_get_id(ggml_metal_buffer_t buf, const struct ggml_tensor * t) { + struct ggml_metal_buffer_id res = { nil, 0 }; + + const int64_t tsize = ggml_nbytes(t); + + // find the view that contains the tensor fully + for (int i = 0; i < buf->n_buffers; ++i) { + const int64_t ioffs = (int64_t) t->data - (int64_t) buf->buffers[i].data; + + //GGML_LOG_INFO("ioffs = %10ld, tsize = %10ld, sum = %10ld, buf->buffers[%d].size = %10ld\n", ioffs, tsize, ioffs + tsize, i, buf->buffers[i].size); + if (ioffs >= 0 && ioffs + tsize <= (int64_t) buf->buffers[i].size) { + res.metal = buf->buffers[i].metal; + res.offs = (size_t) ioffs; + + //GGML_LOG_INFO("%s: tensor '%16s', offs = %8ld\n", __func__, t->name, *offs); + + return res; + } + } + + GGML_LOG_ERROR("%s: error: tensor '%s' buffer is nil\n", __func__, t->name); + + return res; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-impl.h 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-impl.h --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-impl.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-impl.h 2025-09-30 07:36:33.000000000 +0000 @@ -8,6 +8,9 @@ // // TODO: for optimal performance, become function of the device and work size +#define N_R0_F 2 +#define N_SG_F 4 + #define N_R0_Q4_0 4 #define N_SG_Q4_0 2 @@ -20,8 +23,11 @@ #define N_R0_Q5_1 4 #define N_SG_Q5_1 2 -#define N_R0_Q8_0 4 -#define N_SG_Q8_0 2 +#define N_R0_Q8_0 2 +#define N_SG_Q8_0 4 + +#define N_R0_MXFP4 2 +#define N_SG_MXFP4 2 #define N_R0_Q2_K 4 #define N_SG_Q2_K 2 @@ -29,13 +35,13 @@ #define N_R0_Q3_K 2 #define N_SG_Q3_K 2 -#define N_R0_Q4_K 4 +#define N_R0_Q4_K 2 #define N_SG_Q4_K 2 #define N_R0_Q5_K 2 #define N_SG_Q5_K 2 -#define N_R0_Q6_K 1 +#define N_R0_Q6_K 2 #define N_SG_Q6_K 2 #define N_R0_IQ1_S 4 @@ -65,6 +71,13 @@ #define N_R0_IQ4_XS 2 #define N_SG_IQ4_XS 2 +// function constants offsets +#define FC_FLASH_ATTN_EXT 100 +#define FC_FLASH_ATTN_EXT_VEC 200 +#define FC_FLASH_ATTN_EXT_VEC_REDUCE 300 +#define FC_MUL_MV 400 +#define FC_MUL_MM 500 + // kernel argument structs // // - element counters (e.g. ne00) typically use int32_t to reduce register usage @@ -126,9 +139,19 @@ typedef struct { uint64_t nb2; uint64_t nb3; uint64_t offs; + uint64_t o1[8]; } ggml_metal_kargs_bin; typedef struct { + int64_t ne0; + int64_t ne1; + size_t nb01; + size_t nb02; + size_t nb11; + size_t nb21; +} ggml_metal_kargs_add_id; + +typedef struct { int32_t ne00; int32_t ne01; int32_t ne02; @@ -148,6 +171,16 @@ typedef struct { } ggml_metal_kargs_repeat; typedef struct { + float scale; + float bias; +} ggml_metal_kargs_scale; + +typedef struct { + float min; + float max; +} ggml_metal_kargs_clamp; + +typedef struct { int64_t ne00; int64_t ne01; int64_t ne02; @@ -223,9 +256,11 @@ typedef struct { int32_t ne11; int32_t ne_12_2; // assume K and V are same shape int32_t ne_12_3; + int32_t ns10; uint64_t nb11; uint64_t nb12; uint64_t nb13; + int32_t ns20; uint64_t nb21; uint64_t nb22; uint64_t nb23; @@ -236,15 +271,54 @@ typedef struct { uint64_t nb33; int32_t ne1; int32_t ne2; + int32_t ne3; float scale; float max_bias; float m0; float m1; - uint16_t n_head_log2; + int32_t n_head_log2; float logit_softcap; } ggml_metal_kargs_flash_attn_ext; typedef struct { + int32_t ne01; + int32_t ne02; + int32_t ne03; + uint64_t nb01; + uint64_t nb02; + uint64_t nb03; + int32_t ne11; + int32_t ne_12_2; // assume K and V are same shape + int32_t ne_12_3; + int32_t ns10; + uint64_t nb11; + uint64_t nb12; + uint64_t nb13; + int32_t ns20; + uint64_t nb21; + uint64_t nb22; + uint64_t nb23; + int32_t ne32; + int32_t ne33; + uint64_t nb31; + uint64_t nb32; + uint64_t nb33; + int32_t ne1; + int32_t ne2; + int32_t ne3; + float scale; + float max_bias; + float m0; + float m1; + int32_t n_head_log2; + float logit_softcap; +} ggml_metal_kargs_flash_attn_ext_vec; + +typedef struct { + int32_t nrows; +} ggml_metal_kargs_flash_attn_ext_vec_reduce; + +typedef struct { int32_t ne00; int32_t ne02; uint64_t nb01; @@ -301,46 +375,34 @@ typedef struct { int32_t ne1; int16_t r2; int16_t r3; - int16_t nsg; - int16_t nxpsg; - int16_t r1ptg; } ggml_metal_kargs_mul_mv_ext; typedef struct { + int32_t ne02; int32_t ne10; int32_t ne11; // n_expert_used (bcast) uint64_t nb11; uint64_t nb12; - int32_t neh11; // n_tokens - uint64_t nbh11; + int32_t ne21; // n_tokens int32_t ne20; // n_expert_used uint64_t nb21; } ggml_metal_kargs_mul_mm_id_map0; typedef struct { - int32_t ne20; // n_expert_used - int32_t neh0; - int32_t neh1; - uint64_t nbh1; - uint64_t nbh2; - int32_t ne0; - uint64_t nb1; - uint64_t nb2; -} ggml_metal_kargs_mul_mm_id_map1; - -typedef struct { int32_t ne00; int32_t ne02; uint64_t nb01; uint64_t nb02; uint64_t nb03; - int32_t neh12; - uint64_t nbh10; - uint64_t nbh11; - uint64_t nbh12; - uint64_t nbh13; - int32_t neh0; - int32_t neh1; + int32_t ne11; + uint64_t nb10; + uint64_t nb11; + uint64_t nb12; + uint64_t nb13; + int32_t ne20; + int32_t ne21; + int32_t ne0; + int32_t ne1; int16_t r2; int16_t r3; } ggml_metal_kargs_mul_mm_id; @@ -367,11 +429,21 @@ typedef struct { uint64_t nb1; } ggml_metal_kargs_mul_mv_id; +// NORM +// RMS_NORM typedef struct { int32_t ne00; - int32_t ne00_4; - uint64_t nb01; + int32_t ne00_t; + uint64_t nb1; + uint64_t nb2; + uint64_t nb3; float eps; + int32_t nef1[3]; + int32_t nef2[3]; + int32_t nef3[3]; + uint64_t nbf1[3]; + uint64_t nbf2[3]; + uint64_t nbf3[3]; } ggml_metal_kargs_norm; typedef struct { @@ -379,13 +451,6 @@ typedef struct { int32_t ne00_4; uint64_t nb01; float eps; -} ggml_metal_kargs_rms_norm; - -typedef struct { - int32_t ne00; - int32_t ne00_4; - uint64_t nb01; - float eps; } ggml_metal_kargs_l2_norm; typedef struct { @@ -395,7 +460,7 @@ typedef struct { uint64_t nb00; uint64_t nb01; uint64_t nb02; - int32_t n_groups; + int32_t ngrp; float eps; } ggml_metal_kargs_group_norm; @@ -435,6 +500,8 @@ typedef struct{ uint64_t nb1; int32_t i00; int32_t i10; + float alpha; + float limit; } ggml_metal_kargs_glu; typedef struct { @@ -446,14 +513,6 @@ typedef struct { uint64_t nb01; uint64_t nb02; uint64_t nb03; - int64_t ne10; - int64_t ne11; - int64_t ne12; - int64_t ne13; - uint64_t nb10; - uint64_t nb11; - uint64_t nb12; - uint64_t nb13; int64_t ne0; int64_t ne1; int64_t ne2; @@ -484,18 +543,12 @@ typedef struct { float max_bias; float m0; float m1; - uint32_t n_head_log2; + int32_t n_head_log2; } ggml_metal_kargs_soft_max; typedef struct { int64_t ne00; int64_t ne01; - int n_past; -} ggml_metal_kargs_diag_mask_inf; - -typedef struct { - int64_t ne00; - int64_t ne01; int64_t ne02; uint64_t nb00; uint64_t nb01; @@ -519,6 +572,7 @@ typedef struct { int64_t n_group; int64_t n_seq_tokens; int64_t n_seqs; + uint64_t s_off; uint64_t nb01; uint64_t nb02; uint64_t nb03; @@ -658,7 +712,12 @@ typedef struct { int64_t IW; int64_t OH; int64_t OW; - int64_t parallel_elements; + int64_t np; } ggml_metal_kargs_pool_2d; +typedef struct { + int64_t ne00; + uint64_t nb01; +} ggml_metal_kargs_argmax; + #endif // GGML_METAL_IMPL diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.cpp 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.cpp --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,3156 @@ +#include "ggml-metal-ops.h" + +#include "ggml.h" +#include "ggml-impl.h" +#include "ggml-backend-impl.h" + +#include "ggml-metal-impl.h" +#include "ggml-metal-common.h" +#include "ggml-metal-device.h" + +#include +#include + +static ggml_metal_buffer_id ggml_metal_get_buffer_id(const ggml_tensor * t) { + if (!t) { + return { nullptr, 0 }; + } + + ggml_backend_buffer_t buffer = t->view_src ? t->view_src->buffer : t->buffer; + + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t) buffer->context; + + return ggml_metal_buffer_get_id(ctx, t); +} + +struct ggml_metal_op { + ggml_metal_op( + ggml_metal_device_t dev, + ggml_metal_cmd_buf_t cmd_buf, + ggml_cgraph * gf, + int idx_start, + int idx_end, + bool use_fusion, + bool use_concurrency, + bool use_capture, + int debug_graph, + int debug_fusion) { + this->dev = dev; + this->lib = ggml_metal_device_get_library(dev); + this->enc = ggml_metal_encoder_init(cmd_buf, use_concurrency); + this->mem_ranges = ggml_mem_ranges_init(debug_graph); + this->idx_start = idx_start; + this->idx_end = idx_end; + this->use_fusion = use_fusion; + this->use_concurrency = use_concurrency; + this->use_capture = use_capture; + this->debug_graph = debug_graph; + this->debug_fusion = debug_fusion; + this->gf = gf; + + idxs.reserve(gf->n_nodes); + + // filter empty nodes + // TODO: this can be removed when the allocator starts filtering them earlier + // https://github.com/ggml-org/llama.cpp/pull/16130#issuecomment-3327905830 + for (int i = idx_start; i < idx_end; i++) { + if (!ggml_op_is_empty(gf->nodes[i]->op) && !ggml_is_empty(gf->nodes[i])) { + idxs.push_back(i); + } + } + } + + ~ggml_metal_op() { + ggml_metal_encoder_end_encoding(this->enc); + ggml_metal_encoder_free(this->enc); + ggml_mem_ranges_free(this->mem_ranges); + } + + int n_nodes() const { + return idxs.size(); + } + + ggml_tensor * node(int i) const { + assert(i >= 0 && i < (int) idxs.size()); + return ggml_graph_node(gf, idxs[i]); + } + + bool can_fuse(int i0, const ggml_op * ops, int n_ops) const { + assert(use_fusion); + assert(i0 >= 0 && i0 < n_nodes()); + + if (i0 + n_ops > n_nodes()) { + return false; + } + + return ggml_can_fuse_ext(gf, idxs.data() + i0, ops, n_ops); + } + + ggml_metal_device_t dev; + ggml_metal_library_t lib; + ggml_metal_encoder_t enc; + ggml_mem_ranges_t mem_ranges; + + bool use_fusion; + bool use_concurrency; + bool use_capture; + + int debug_graph; + int debug_fusion; + +private: + ggml_cgraph * gf; + + int idx_start; + int idx_end; + + // non-empty node indices + std::vector idxs; +}; + +ggml_metal_op_t ggml_metal_op_init( + ggml_metal_device_t dev, + ggml_metal_cmd_buf_t cmd_buf, + ggml_cgraph * gf, + int idx_start, + int idx_end, + bool use_fusion, + bool use_concurrency, + bool use_capture, + int debug_graph, + int debug_fusion) { + ggml_metal_op_t res = new ggml_metal_op( + dev, + cmd_buf, + gf, + idx_start, + idx_end, + use_fusion, + use_concurrency, + use_capture, + debug_graph, + debug_fusion); + + return res; +} + +void ggml_metal_op_free(ggml_metal_op_t ctx) { + delete ctx; +} + +int ggml_metal_op_n_nodes(ggml_metal_op_t ctx) { + return ctx->n_nodes(); +} + +static bool ggml_metal_op_concurrency_reset(ggml_metal_op_t ctx) { + if (!ctx->mem_ranges) { + return true; + } + + ggml_metal_encoder_memory_barrier(ctx->enc); + + ggml_mem_ranges_reset(ctx->mem_ranges); + + return true; +} + +static bool ggml_metal_op_concurrency_check(ggml_metal_op_t ctx, const ggml_tensor * node) { + if (!ctx->mem_ranges) { + return false; + } + + return ggml_mem_ranges_check(ctx->mem_ranges, node); +} + +static bool ggml_metal_op_concurrency_add(ggml_metal_op_t ctx, const ggml_tensor * node) { + if (!ctx->mem_ranges) { + return true; + } + + return ggml_mem_ranges_add(ctx->mem_ranges, node); +} + +static int ggml_metal_op_encode_impl(ggml_metal_op_t ctx, int idx) { + struct ggml_tensor * node = ctx->node(idx); + + //GGML_LOG_INFO("%s: encoding node %3d, op = %8s\n", __func__, idx, ggml_op_name(node->op)); + + if (ggml_is_empty(node)) { + return 1; + } + + switch (node->op) { + case GGML_OP_NONE: + case GGML_OP_RESHAPE: + case GGML_OP_VIEW: + case GGML_OP_TRANSPOSE: + case GGML_OP_PERMUTE: + { + // noop -> next node + if (ctx->debug_graph > 0) { + GGML_LOG_DEBUG("%s: node[%5d] - %-12s %s\n", __func__, idx, ggml_op_name(node->op), "(noop)"); + } + } return 1; + default: + { + } break; + } + + if (!ggml_metal_device_supports_op(ctx->dev, node)) { + GGML_LOG_ERROR("%s: error: unsupported op '%s'\n", __func__, ggml_op_desc(node)); + GGML_ABORT("unsupported op"); + } + + int n_fuse = 1; + + // check if the current node can run concurrently with other nodes before it + // the condition is that: + // - the current node cannot write to any previous src or dst ranges + // - the current node cannot read from any previous dst ranges + // + // if the condition is not satisfied, we put a memory barrier and clear all ranges + // otherwise, we add the new ranges to the encoding context and process the node concurrently + // + { + const bool is_concurrent = ggml_metal_op_concurrency_check(ctx, node); + + if (!is_concurrent) { + ggml_metal_op_concurrency_reset(ctx); + } + + if (ctx->debug_graph > 0) { + GGML_LOG_DEBUG("%s: node[%5d] - %-12s %s\n", __func__, idx, ggml_op_name(node->op), is_concurrent ? "(concurrent)" : ""); + } + if (ctx->debug_graph > 1) { + GGML_TENSOR_LOCALS( int64_t, ne0, node->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, node->src[0], nb); + GGML_TENSOR_LOCALS( int64_t, ne1, node->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, node->src[1], nb); + GGML_TENSOR_LOCALS( int64_t, ne, node, ne); + GGML_TENSOR_LOCALS(uint64_t, nb, node, nb); + + if (node->src[0]) { + GGML_LOG_DEBUG("%s: src0 - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], %d, %s\n", __func__, ggml_type_name(node->src[0]->type), ne00, ne01, ne02, ne03, nb00, nb01, nb02, nb03, + ggml_is_contiguous(node->src[0]), node->src[0]->name); + } + if (node->src[1]) { + GGML_LOG_DEBUG("%s: src1 - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], %d, %s\n", __func__, ggml_type_name(node->src[1]->type), ne10, ne11, ne12, ne13, nb10, nb11, nb12, nb13, + ggml_is_contiguous(node->src[1]), node->src[1]->name); + } + if (node) { + GGML_LOG_DEBUG("%s: node - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], 1, %s\n", __func__, ggml_type_name(node->type), ne0, ne1, ne2, ne3, nb0, nb1, nb2, nb3, + node->name); + } + } + } + + switch (node->op) { + case GGML_OP_CONCAT: + { + n_fuse = ggml_metal_op_concat(ctx, idx); + } break; + case GGML_OP_ADD: + case GGML_OP_SUB: + case GGML_OP_MUL: + case GGML_OP_DIV: + { + n_fuse = ggml_metal_op_bin(ctx, idx); + } break; + case GGML_OP_ADD_ID: + { + n_fuse = ggml_metal_op_add_id(ctx, idx); + } break; + case GGML_OP_REPEAT: + { + n_fuse = ggml_metal_op_repeat(ctx, idx); + } break; + case GGML_OP_ACC: + { + n_fuse = ggml_metal_op_acc(ctx, idx); + } break; + case GGML_OP_SCALE: + { + n_fuse = ggml_metal_op_scale(ctx, idx); + } break; + case GGML_OP_CLAMP: + { + n_fuse = ggml_metal_op_clamp(ctx, idx); + } break; + case GGML_OP_SQR: + case GGML_OP_SQRT: + case GGML_OP_SIN: + case GGML_OP_COS: + case GGML_OP_LOG: + case GGML_OP_UNARY: + { + n_fuse = ggml_metal_op_unary(ctx, idx); + } break; + case GGML_OP_GLU: + { + n_fuse = ggml_metal_op_glu(ctx, idx); + } break; + case GGML_OP_SUM_ROWS: + case GGML_OP_MEAN: + { + n_fuse = ggml_metal_op_sum_rows(ctx, idx); + } break; + case GGML_OP_SOFT_MAX: + { + n_fuse = ggml_metal_op_soft_max(ctx, idx); + } break; + case GGML_OP_SSM_CONV: + { + n_fuse = ggml_metal_op_ssm_conv(ctx, idx); + } break; + case GGML_OP_SSM_SCAN: + { + n_fuse = ggml_metal_op_ssm_scan(ctx, idx); + } break; + case GGML_OP_RWKV_WKV6: + case GGML_OP_RWKV_WKV7: + { + n_fuse = ggml_metal_op_rwkv(ctx, idx); + } break; + case GGML_OP_MUL_MAT: + { + n_fuse = ggml_metal_op_mul_mat(ctx, idx); + } break; + case GGML_OP_MUL_MAT_ID: + { + n_fuse = ggml_metal_op_mul_mat_id(ctx, idx); + } break; + case GGML_OP_GET_ROWS: + { + n_fuse = ggml_metal_op_get_rows(ctx, idx); + } break; + case GGML_OP_SET_ROWS: + { + n_fuse = ggml_metal_op_set_rows(ctx, idx); + } break; + case GGML_OP_L2_NORM: + { + n_fuse = ggml_metal_op_l2_norm(ctx, idx); + } break; + case GGML_OP_GROUP_NORM: + { + n_fuse = ggml_metal_op_group_norm(ctx, idx); + } break; + case GGML_OP_NORM: + case GGML_OP_RMS_NORM: + { + n_fuse = ggml_metal_op_norm(ctx, idx); + } break; + case GGML_OP_ROPE: + { + n_fuse = ggml_metal_op_rope(ctx, idx); + } break; + case GGML_OP_IM2COL: + { + n_fuse = ggml_metal_op_im2col(ctx, idx); + } break; + case GGML_OP_CONV_TRANSPOSE_1D: + { + n_fuse = ggml_metal_op_conv_transpose_1d(ctx, idx); + } break; + case GGML_OP_UPSCALE: + { + n_fuse = ggml_metal_op_upscale(ctx, idx); + } break; + case GGML_OP_PAD: + { + n_fuse = ggml_metal_op_pad(ctx, idx); + } break; + case GGML_OP_PAD_REFLECT_1D: + { + n_fuse = ggml_metal_op_pad_reflect_1d(ctx, idx); + } break; + case GGML_OP_ARANGE: + { + n_fuse = ggml_metal_op_arange(ctx, idx); + } break; + case GGML_OP_TIMESTEP_EMBEDDING: + { + n_fuse = ggml_metal_op_timestep_embedding(ctx, idx); + } break; + case GGML_OP_ARGSORT: + { + n_fuse = ggml_metal_op_argsort(ctx, idx); + } break; + case GGML_OP_LEAKY_RELU: + { + n_fuse = ggml_metal_op_leaky_relu(ctx, idx); + } break; + case GGML_OP_FLASH_ATTN_EXT: + { + n_fuse = ggml_metal_op_flash_attn_ext(ctx, idx); + } break; + case GGML_OP_DUP: + case GGML_OP_CPY: + case GGML_OP_CONT: + { + n_fuse = ggml_metal_op_cpy(ctx, idx); + } break; + case GGML_OP_POOL_2D: + { + n_fuse = ggml_metal_op_pool_2d(ctx, idx); + } break; + case GGML_OP_ARGMAX: + { + n_fuse = ggml_metal_op_argmax(ctx, idx); + } break; + default: + { + GGML_LOG_ERROR("%s: error: node %3d, op = %8s not implemented\n", __func__, idx, ggml_op_name(node->op)); + GGML_ABORT("fatal error"); + } + } + + if (ctx->debug_graph > 0) { + if (n_fuse > 1) { + GGML_LOG_DEBUG("%s: fuse %d ops\n", __func__, n_fuse); + } + } + + // update the mem ranges in the encoding context + for (int i = 0; i < n_fuse; ++i) { + if (!ggml_metal_op_concurrency_add(ctx, ctx->node(idx + i))) { + ggml_metal_op_concurrency_reset(ctx); + } + } + + return n_fuse; +} + +int ggml_metal_op_encode(ggml_metal_op_t ctx, int idx) { + if (ctx->use_capture) { + ggml_metal_encoder_debug_group_push(ctx->enc, ggml_op_desc(ctx->node(idx))); + } + + int res = ggml_metal_op_encode_impl(ctx, idx); + if (idx + res > ctx->n_nodes()) { + GGML_ABORT("fusion error: nodes spanning multiple encoders have been fused. this indicates a bug in the fusion logic %s", + "https://github.com/ggml-org/llama.cpp/pull/14849"); + } + + if (ctx->use_capture) { + ggml_metal_encoder_debug_group_pop(ctx->enc); + } + + return res; +} + +int ggml_metal_op_concat(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint64_t, nb, op, nb); + + const int32_t dim = ((const int32_t *) op->op_params)[0]; + + ggml_metal_kargs_concat args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.ne13 =*/ ne13, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.dim =*/ dim, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_base(lib, GGML_OP_CONCAT); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + const int nth = std::min(1024, ne0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne1, ne2, ne3, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_repeat(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_repeat(lib, op->type); + + ggml_metal_kargs_repeat args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne1, ne2, ne3, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_acc(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + GGML_ASSERT(op->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + GGML_ASSERT(ggml_is_contiguous(op->src[1])); + + const size_t pnb1 = ((const int32_t *) op->op_params)[0]; + const size_t pnb2 = ((const int32_t *) op->op_params)[1]; + const size_t pnb3 = ((const int32_t *) op->op_params)[2]; + const size_t offs = ((const int32_t *) op->op_params)[3]; + + const bool inplace = (bool) ((const int32_t *) op->op_params)[4]; + + if (!inplace) { + // run a separete kernel to cpy src->dst + // not sure how to avoid this + // TODO: make a simpler cpy_bytes kernel + + //const id pipeline = ctx->pipelines[GGML_METAL_PIPELINE_TYPE_CPY_F32_F32].obj; + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_cpy(lib, op->src[0]->type, op->type); + + ggml_metal_kargs_cpy args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne00); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + + ggml_metal_op_concurrency_reset(ctx); + } + + ggml_metal_kargs_bin args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ pnb1, + /*.nb02 =*/ pnb2, + /*.nb03 =*/ pnb3, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.ne13 =*/ ne13, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ pnb1, + /*.nb2 =*/ pnb2, + /*.nb3 =*/ pnb3, + /*.offs =*/ offs, + /*.o1 =*/ { 0 }, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_bin(lib, GGML_OP_ADD, 1, false); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne00); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne11, ne12, ne13, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_scale(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float scale; + float bias; + memcpy(&scale, ((const int32_t *) op->op_params) + 0, sizeof(float)); + memcpy(&bias, ((const int32_t *) op->op_params) + 1, sizeof(float)); + + ggml_metal_kargs_scale args = { + /*.scale =*/ scale, + /*.bias =*/ bias, + }; + + int64_t n = ggml_nelements(op); + + if (n % 4 == 0) { + n /= 4; + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_unary(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + + return 1; +} + +int ggml_metal_op_clamp(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float min; + float max; + memcpy(&min, ((const int32_t *) op->op_params) + 0, sizeof(float)); + memcpy(&max, ((const int32_t *) op->op_params) + 1, sizeof(float)); + + ggml_metal_kargs_clamp args = { + /*.min =*/ min, + /*.max =*/ max, + }; + + int64_t n = ggml_nelements(op); + + if (n % 4 == 0) { + n /= 4; + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_unary(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + + return 1; +} + +int ggml_metal_op_unary(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + int64_t n = ggml_nelements(op); + + if (n % 4 == 0) { + n /= 4; + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_unary(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 1); + + ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + + return 1; +} + +int ggml_metal_op_glu(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + if (op->src[1]) { + GGML_ASSERT(ggml_are_same_shape(op->src[0], op->src[1])); + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_glu(lib, op); + + const int32_t swp = ggml_get_op_params_i32(op, 1); + const float alpha = ggml_get_op_params_f32(op, 2); + const float limit = ggml_get_op_params_f32(op, 3); + + const int32_t i00 = swp ? ne0 : 0; + const int32_t i10 = swp ? 0 : ne0; + + ggml_metal_kargs_glu args = { + /*.ne00 =*/ ne00, + /*.nb01 =*/ nb01, + /*.ne10 =*/ op->src[1] ? ne10 : ne00, + /*.nb11 =*/ op->src[1] ? nb11 : nb01, + /*.ne0 =*/ ne0, + /*.nb1 =*/ nb1, + /*.i00 =*/ op->src[1] ? 0 : i00, + /*.i10 =*/ op->src[1] ? 0 : i10, + /*.alpha=*/ alpha, + /*.limit=*/ limit + }; + + const int64_t nrows = ggml_nrows(op->src[0]); + + const int32_t nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne00/2); + + //[encoder setComputePipelineState:pipeline]; + //[encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; + //if (src1) { + // [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; + //} else { + // [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; + //} + //[encoder setBuffer:id_dst offset:offs_dst atIndex:2]; + //[encoder setBytes:&args length:sizeof(args) atIndex:3]; + + //[encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + if (op->src[1]) { + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + } else { + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 2); + } + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_sum_rows(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_kargs_sum_rows args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_sum_rows(lib, op); + + int nth = 32; // SIMD width + + while (nth < ne00 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + nth = std::min(nth, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + nth = std::min(nth, ne00); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + //[encoder setComputePipelineState:pipeline]; + //[encoder setBytes:&args length:sizeof(args) atIndex:0]; + //[encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; + //[encoder setBuffer:id_dst offset:offs_dst atIndex:2]; + //[encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; + + //[encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_get_rows(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_get_rows(lib, op->src[0]->type); + + ggml_metal_kargs_get_rows args = { + /*.ne00 =*/ ne00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.ne10 =*/ ne10, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne10, ne11, ne12, 32, 1, 1); + + return 1; +} + +int ggml_metal_op_set_rows(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_set_rows(lib, op->src[1]->type, op->type); + + const int32_t nk0 = ne0/ggml_blck_size(op->type); + + int nth = 32; // SIMD width + + while (nth < nk0 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + int nrptg = 1; + if (nth > nk0) { + nrptg = (nth + nk0 - 1)/nk0; + nth = nk0; + + if (nrptg*nth > ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nrptg--; + } + } + + nth = std::min(nth, nk0); + + ggml_metal_kargs_set_rows args = { + /*.nk0 =*/ nk0, + /*.ne01 =*/ ne01, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nrptg - 1)/nrptg, ne02, ne03, nth, nrptg, 1); + + return 1; +} + +int ggml_metal_op_soft_max(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + GGML_TENSOR_LOCALS(uint64_t, nb2, op->src[2], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float scale; + float max_bias; + + memcpy(&scale, ((const int32_t *) op->op_params) + 0, sizeof(scale)); + memcpy(&max_bias, ((const int32_t *) op->op_params) + 1, sizeof(max_bias)); + + const uint32_t n_head = op->src[0]->ne[2]; + const int32_t n_head_log2 = 1u << (uint32_t) floorf(log2f((float) n_head)); + + const float m0 = powf(2.0f, -(max_bias ) / n_head_log2); + const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); + + // softmax + + ggml_metal_kargs_soft_max args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.ne13 =*/ ne13, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.scale =*/ scale, + /*.max_bias =*/ max_bias, + /*.m0 =*/ m0, + /*.m1 =*/ m1, + /*.n_head_log2 =*/ n_head_log2, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_soft_max(lib, op); + + int nth = 32; // SIMD width + + if (ne00%4 == 0) { + while (nth < ne00/4 && nth*ne01*ne02*ne03 < 256) { + nth *= 2; + } + } else { + while (nth < ne00 && nth*ne01*ne02*ne03 < 256) { + nth *= 2; + } + } + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes(enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 1); + if (op->src[1]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[1]), 2); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 2); + } + if (op->src[2]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[2]), 3); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 3); + } + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op), 4); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_ssm_conv(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_kargs_ssm_conv args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_ssm_conv(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes(enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne1, ne02, 1, 1, 1); + + return 1; +} + +int ggml_metal_op_ssm_scan(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + GGML_TENSOR_LOCALS(uint64_t, nb2, op->src[2], nb); + GGML_TENSOR_LOCALS( int32_t, ne3, op->src[3], ne); + GGML_TENSOR_LOCALS(uint64_t, nb3, op->src[3], nb); + GGML_TENSOR_LOCALS( int32_t, ne4, op->src[4], ne); + GGML_TENSOR_LOCALS(uint64_t, nb4, op->src[4], nb); + GGML_TENSOR_LOCALS( int32_t, ne5, op->src[5], ne); + GGML_TENSOR_LOCALS(uint64_t, nb5, op->src[5], nb); + GGML_TENSOR_LOCALS( int32_t, ne6, op->src[6], ne); + GGML_TENSOR_LOCALS(uint64_t, nb6, op->src[6], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const ggml_tensor * src3 = op->src[3]; + const ggml_tensor * src4 = op->src[4]; + const ggml_tensor * src5 = op->src[5]; + const ggml_tensor * src6 = op->src[6]; + + GGML_ASSERT(src3); + GGML_ASSERT(src4); + GGML_ASSERT(src5); + GGML_ASSERT(src6); + + const int64_t d_state = ne00; + const int64_t d_inner = ne01; + const int64_t n_head = ne02; + const int64_t n_group = ne41; + const int64_t n_seq_tokens = ne12; + const int64_t n_seqs = ne13; + + ggml_metal_kargs_ssm_scan args = { + /*.d_state =*/ d_state, + /*.d_inner =*/ d_inner, + /*.n_head =*/ n_head, + /*.n_group =*/ n_group, + /*.n_seq_tokens =*/ n_seq_tokens, + /*.n_seqs =*/ n_seqs, + /*.s_off =*/ ggml_nelements(op->src[1]) * sizeof(float), + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.nb21 =*/ nb21, + /*.nb22 =*/ nb22, + /*.nb31 =*/ nb31, + /*.nb41 =*/ nb41, + /*.nb42 =*/ nb42, + /*.nb43 =*/ nb43, + /*.nb51 =*/ nb51, + /*.nb52 =*/ nb52, + /*.nb53 =*/ nb53, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_ssm_scan(lib, op); + + const size_t sms = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), 3); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[3]), 4); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[4]), 5); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[5]), 6); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[6]), 7); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 8); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, sms, 0); + + if (ne30 == 1) { + // Mamba-2 + ggml_metal_encoder_dispatch_threadgroups(enc, d_inner, n_head, n_seqs, d_state, 1, 1); + } else { + GGML_ASSERT(d_inner == 1); + ggml_metal_encoder_dispatch_threadgroups(enc, n_head, n_seqs, 1, d_state, 1, 1); + } + + return 1; +} + +int ggml_metal_op_rwkv(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int64_t B = op->op == GGML_OP_RWKV_WKV6 ? op->src[5]->ne[1] : op->src[6]->ne[1]; + const int64_t T = op->src[0]->ne[2]; + const int64_t C = op->ne[0]; + const int64_t H = op->src[0]->ne[1]; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_rwkv(lib, op); + + int ida = 0; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[3]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[4]), ida++); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[5]), ida++); + if (op->op == GGML_OP_RWKV_WKV7) { + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[6]), ida++); + } + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), ida++); + ggml_metal_encoder_set_bytes (enc, (void *) &B, sizeof(B), ida++); + ggml_metal_encoder_set_bytes (enc, (void *) &T, sizeof(T), ida++); + ggml_metal_encoder_set_bytes (enc, (void *) &C, sizeof(C), ida++); + ggml_metal_encoder_set_bytes (enc, (void *) &H, sizeof(H), ida++); + + ggml_metal_encoder_dispatch_threadgroups(enc, B * H, 1, 1, C/H, 1, 1); + + return 1; +} + +int ggml_metal_op_cpy(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_cpy(lib, op->src[0]->type, op->type); + + GGML_ASSERT(ne00 % ggml_blck_size(op->src[0]->type) == 0); + + // TODO: support + //const int32_t nk00 = ne00/ggml_blck_size(op->type); + const int32_t nk00 = ne00; + + int nth = 32; // SIMD width + + while (nth < nk00 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + nth = std::min(nth, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + + // when rows are small, we can batch them together in a single threadgroup + int nrptg = 1; + + // TODO: relax this constraint in the future + if (ggml_blck_size(op->src[0]->type) == 1 && ggml_blck_size(op->type) == 1) { + if (nth > nk00) { + nrptg = (nth + nk00 - 1)/nk00; + nth = nk00; + + if (nrptg*nth > ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nrptg--; + } + } + } + + nth = std::min(nth, nk00); + + ggml_metal_kargs_cpy args = { + /*.ne00 =*/ nk00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, nrptg, 1); + + return 1; +} + +int ggml_metal_op_pool_2d(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int32_t * opts = op->op_params; + ggml_op_pool op_pool = (ggml_op_pool) opts[0]; + + const int32_t k0 = opts[1]; + const int32_t k1 = opts[2]; + const int32_t s0 = opts[3]; + const int32_t s1 = opts[4]; + const int32_t p0 = opts[5]; + const int32_t p1 = opts[6]; + + const int64_t IH = op->src[0]->ne[1]; + const int64_t IW = op->src[0]->ne[0]; + + const int64_t N = op->ne[3]; + const int64_t OC = op->ne[2]; + const int64_t OH = op->ne[1]; + const int64_t OW = op->ne[0]; + + const int64_t np = N * OC * OH * OW; + + ggml_metal_kargs_pool_2d args_pool_2d = { + /* .k0 = */ k0, + /* .k1 = */ k1, + /* .s0 = */ s0, + /* .s1 = */ s1, + /* .p0 = */ p0, + /* .p1 = */ p1, + /* .IH = */ IH, + /* .IW = */ IW, + /* .OH = */ OH, + /* .OW = */ OW, + /* .np = */ np + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_pool_2d(lib, op, op_pool); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), (int) np); + const int ntg = (np + nth - 1) / nth; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args_pool_2d, sizeof(args_pool_2d), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ntg, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_mul_mat(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const ggml_metal_device_props * props_dev = ggml_metal_device_get_props(ctx->dev); + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + GGML_ASSERT(ne00 == ne10); + + GGML_ASSERT(ne12 % ne02 == 0); + GGML_ASSERT(ne13 % ne03 == 0); + + const int16_t r2 = ne12/ne02; + const int16_t r3 = ne13/ne03; + + // find the break-even point where the matrix-matrix kernel becomes more efficient compared + // to the matrix-vector kernel + const int ne11_mm_min = 8; + + // first try to use small-batch mat-mv kernels + // these should be efficient for BS [2, ~8] + if (op->src[1]->type == GGML_TYPE_F32 && (ne00%128 == 0) && + ( + ( + ( + op->src[0]->type == GGML_TYPE_F32 || // TODO: helper function + op->src[0]->type == GGML_TYPE_F16 || + op->src[0]->type == GGML_TYPE_Q4_0 || + op->src[0]->type == GGML_TYPE_Q4_1 || + op->src[0]->type == GGML_TYPE_Q5_0 || + op->src[0]->type == GGML_TYPE_Q5_1 || + op->src[0]->type == GGML_TYPE_Q8_0 || + op->src[0]->type == GGML_TYPE_MXFP4 || + op->src[0]->type == GGML_TYPE_IQ4_NL || + false) && (ne11 >= 2 && ne11 <= 8) + ) || + ( + ( + op->src[0]->type == GGML_TYPE_Q4_K || + op->src[0]->type == GGML_TYPE_Q5_K || + op->src[0]->type == GGML_TYPE_Q6_K || + false) && (ne11 >= 4 && ne11 <= 8) + ) + ) + ) { + // TODO: determine the optimal parameters based on grid utilization + // I still don't know why we should not always use the maximum available threads: + // + // nsg = pipeline.maxTotalThreadsPerThreadgroup / 32 + // + // my current hypothesis is that the work grid is not evenly divisible for different nsg + // values and there can be some tail effects when nsg is high. need to confirm this + // + const int nsg = 2; // num simdgroups per threadgroup + + // num threads along row per simdgroup + int16_t nxpsg = 0; + if (ne00 % 256 == 0 && ne11 < 3) { + nxpsg = 16; + } else if (ne00 % 128 == 0) { + nxpsg = 8; + } else { + nxpsg = 4; + } + + const int16_t nypsg = 32/nxpsg; // num threads along col per simdgroup (i.e. a simdgroup processes that many src0 rows at a time) + const int16_t r0ptg = nypsg*nsg; // num src0 rows per threadgroup + int16_t r1ptg = 4; // num src1 rows per threadgroup + + // note: not sure how optimal are those across all different hardware. there might be someting cleverer + switch (ne11) { + case 2: + r1ptg = 2; break; + case 3: + case 6: + r1ptg = 3; break; + case 4: + case 7: + case 8: + r1ptg = 4; break; + case 5: + r1ptg = 5; break; + default: + GGML_ABORT("unsupported ne11"); + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mv_ext(lib, op->src[0]->type, op->src[1]->type, nsg, nxpsg, r1ptg); + + ggml_metal_kargs_mul_mv_ext args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne01 + r0ptg - 1)/r0ptg), ((ne11 + r1ptg - 1)/r1ptg), ne12*ne13, 32, nsg, 1); + } else if ( + !ggml_is_transposed(op->src[0]) && + !ggml_is_transposed(op->src[1]) && + // for now the matrix-matrix multiplication kernel only works on A14+/M1+ SoCs + // AMD GPU and older A-chips will reuse matrix-vector multiplication kernel + props_dev->has_simdgroup_mm && ne00 >= 64 && + (ne11 > ne11_mm_min || (ggml_is_quantized(op->src[0]->type) && ne12 > 1))) { + //printf("matrix: ne00 = %6d, ne01 = %6d, ne02 = %6d, ne11 = %6d, ne12 = %6d\n", ne00, ne01, ne02, ne11, ne12); + + // some Metal matrix data types require aligned pointers + // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (Table 2.5) + //switch (op->src[0]->type) { + // case GGML_TYPE_F32: GGML_ASSERT(nb01 % 16 == 0); break; + // case GGML_TYPE_F16: GGML_ASSERT(nb01 % 8 == 0); break; + // case GGML_TYPE_BF16: GGML_ASSERT(nb01 % 8 == 0); break; + // default: break; + //} + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mm(lib, op); + + ggml_metal_kargs_mul_mm args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne11 + 31)/32), ((ne01 + 63)/64), ne12*ne13, 128, 1, 1); + } else { + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mv(lib, op); + + ggml_metal_kargs_mul_mv args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + const int nr0 = ggml_metal_pipeline_get_nr0(pipeline); + const int nr1 = ggml_metal_pipeline_get_nr1(pipeline); + const int nsg = ggml_metal_pipeline_get_nsg(pipeline); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + if (op->src[0]->type == GGML_TYPE_F32 || + op->src[0]->type == GGML_TYPE_F16 || + op->src[0]->type == GGML_TYPE_BF16 || + op->src[0]->type == GGML_TYPE_Q8_0) { + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne01 + nr0 - 1)/(nr0)), ((ne11 + nr1 - 1)/nr1), ne12*ne13, 32, nsg, 1); + } else { + ggml_metal_encoder_dispatch_threadgroups(enc, ((ne01 + nr0*nsg - 1)/(nr0*nsg)), ((ne11 + nr1 - 1)/nr1), ne12*ne13, 32, nsg, 1); + } + } + + return 1; +} + +size_t ggml_metal_op_mul_mat_id_extra_tpe(const ggml_tensor * op) { + assert(op->op == GGML_OP_MUL_MAT_ID); + + const int64_t ne02 = op->src[0]->ne[2]; // n_expert + + return ggml_type_size(GGML_TYPE_I32)*ne02; +} + +size_t ggml_metal_op_mul_mat_id_extra_ids(const ggml_tensor * op) { + assert(op->op == GGML_OP_MUL_MAT_ID); + + const int64_t ne02 = op->src[0]->ne[2]; // n_expert + const int64_t ne21 = op->src[2]->ne[1]; // n_token + + return ggml_type_size(GGML_TYPE_I32)*ne02*ne21; +} + +int ggml_metal_op_mul_mat_id(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const ggml_metal_device_props * props_dev = ggml_metal_device_get_props(ctx->dev); + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + GGML_TENSOR_LOCALS(uint64_t, nb2, op->src[2], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + // src2 = ids + GGML_ASSERT(op->src[2]->type == GGML_TYPE_I32); + + GGML_ASSERT(!ggml_is_transposed(op->src[0])); + GGML_ASSERT(!ggml_is_transposed(op->src[1])); + + GGML_ASSERT(ne03 == 1); + GGML_ASSERT(ne13 == 1); + + ggml_metal_buffer_id bid_src0 = ggml_metal_get_buffer_id(op->src[0]); + ggml_metal_buffer_id bid_src1 = ggml_metal_get_buffer_id(op->src[1]); + ggml_metal_buffer_id bid_src2 = ggml_metal_get_buffer_id(op->src[2]); + ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(op); + + const uint32_t r2 = 1; + const uint32_t r3 = 1; + + // find the break-even point where the matrix-matrix kernel becomes more efficient compared + // to the matrix-vector kernel + // ne20 = n_used_experts + // ne21 = n_rows (batch size) + const int ne21_mm_id_min = 32; + + if (props_dev->has_simdgroup_mm && ne00 >= 64 && (ne21 >= ne21_mm_id_min)) { + // some Metal matrix data types require aligned pointers + // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (Table 2.5) + //switch (op->src[0]->type) { + // case GGML_TYPE_F32: GGML_ASSERT(nb01 % 16 == 0); break; + // case GGML_TYPE_F16: GGML_ASSERT(nb01 % 8 == 0); break; + // case GGML_TYPE_BF16: GGML_ASSERT(nb01 % 8 == 0); break; + // default: break; + //} + + // extra buffers for intermediate id mapping + ggml_metal_buffer_id bid_tpe = bid_dst; + bid_tpe.offs += ggml_nbytes(op); + + ggml_metal_buffer_id bid_ids = bid_tpe; + bid_ids.offs += ggml_metal_op_mul_mat_id_extra_tpe(op); + + { + ggml_metal_kargs_mul_mm_id_map0 args = { + ne02, + ne10, + ne11, // n_expert_used (bcast) + nb11, + nb12, + ne21, // n_tokens + ne20, // n_expert_used + nb21, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mm_id_map0(lib, ne02, ne20); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + GGML_ASSERT(ne02 <= ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + + GGML_ASSERT(smem <= props_dev->max_theadgroup_memory_size); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src2, 1); + ggml_metal_encoder_set_buffer (enc, bid_tpe, 2); + ggml_metal_encoder_set_buffer (enc, bid_ids, 3); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, 1, 1, 1, ne02, 1, 1); + } + + // this barrier is always needed because the next kernel has to wait for the id maps to be computed + ggml_metal_op_concurrency_reset(ctx); + + { + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mm_id(lib, op); + + ggml_metal_kargs_mul_mm_id args = { + /*.ne00 =*/ ne00, + /*.ne02 =*/ ne02, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, // n_expert_used (bcast) + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne20 =*/ ne20, // n_expert_used + /*.ne21 =*/ ne21, // n_tokens + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.r2 =*/ r2, + /*.r3 =*/ r3, + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src0, 1); + ggml_metal_encoder_set_buffer (enc, bid_src1, 2); + ggml_metal_encoder_set_buffer (enc, bid_tpe, 3); + ggml_metal_encoder_set_buffer (enc, bid_ids, 4); + ggml_metal_encoder_set_buffer (enc, bid_dst, 5); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, (ne21 + 31)/32, (ne01 + 63)/64, ne02, 128, 1, 1); + } + } else { + ggml_metal_kargs_mul_mv_id args = { + /*.nei0 =*/ ne20, + /*.nei1 =*/ ne21, + /*.nbi1 =*/ nb21, + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.ne13 =*/ ne13, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.nb1 =*/ nb1, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_mul_mv_id(lib, op); + + const int nr0 = ggml_metal_pipeline_get_nr0(pipeline); + const int nr1 = ggml_metal_pipeline_get_nr1(pipeline); + const int nsg = ggml_metal_pipeline_get_nsg(pipeline); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + if (ggml_is_quantized(op->src[0]->type)) { + GGML_ASSERT(ne00 >= nsg*nr0); + } + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes(enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer(enc, bid_src0, 1); + ggml_metal_encoder_set_buffer(enc, bid_src1, 2); + ggml_metal_encoder_set_buffer(enc, bid_dst, 3); + ggml_metal_encoder_set_buffer(enc, bid_src2, 4); + + const int64_t _ne1 = 1; + const int64_t ne123 = ne20*ne21; + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + if (op->src[0]->type == GGML_TYPE_F32 || + op->src[0]->type == GGML_TYPE_F16 || + op->src[0]->type == GGML_TYPE_BF16 || + op->src[0]->type == GGML_TYPE_Q8_0) { + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nr0 - 1)/(nr0), (_ne1 + nr1 - 1)/nr1, ne123, 32, nsg, 1); + } else { + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nr0*nsg - 1)/(nr0*nsg), (_ne1 + nr1 - 1)/nr1, ne123, 32, nsg, 1); + } + } + + return 1; +} + +int ggml_metal_op_add_id(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + GGML_TENSOR_LOCALS(uint64_t, nb2, op->src[2], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[2]->type == GGML_TYPE_I32); + GGML_ASSERT(op->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(op->src[0])); + + ggml_metal_kargs_add_id args = { + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb11 =*/ nb11, + /*.nb21 =*/ nb21, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_base(lib, GGML_OP_ADD_ID); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), 3); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 4); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne00); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, 1, nth, 1, 1); + + return 1; +} + +bool ggml_metal_op_flash_attn_ext_use_vec(const ggml_tensor * op) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + const int64_t ne00 = op->src[0]->ne[0]; // head size + const int64_t ne01 = op->src[0]->ne[1]; // batch size + + // use vec kernel if the batch size is small and if the head size is supported + return (ne01 < 20) && (ne00 % 32 == 0); +} + +size_t ggml_metal_op_flash_attn_ext_extra_tmp(const ggml_tensor * op) { + assert(op->op == GGML_OP_FLASH_ATTN_EXT); + + const int64_t nwg = 32; + + const int64_t ne01 = op->src[0]->ne[1]; + const int64_t ne02 = op->src[0]->ne[2]; + const int64_t ne03 = op->src[0]->ne[3]; + const int64_t ne20 = op->src[2]->ne[0]; + + // temp buffer for writing the results from each workgroup + // - ne20: the size of the Value head + // - + 2: the S and M values for each intermediate result + return ggml_type_size(GGML_TYPE_F32)*(ne01*ne02*ne03*nwg*(ne20 + 2)); +} + +int ggml_metal_op_flash_attn_ext(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const ggml_metal_device_props * props_dev = ggml_metal_device_get_props(ctx->dev); + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne2, op->src[2], ne); + GGML_TENSOR_LOCALS(uint64_t, nb2, op->src[2], nb); + GGML_TENSOR_LOCALS( int32_t, ne3, op->src[3], ne); + GGML_TENSOR_LOCALS(uint64_t, nb3, op->src[3], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS( int32_t, nb, op, nb); + + GGML_ASSERT(ne00 % 4 == 0); + GGML_ASSERT(ne11 % 32 == 0); + + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == op->src[2]->type); + + //GGML_ASSERT(ggml_are_same_shape (src1, src2)); + GGML_ASSERT(ne11 == ne21); + GGML_ASSERT(ne12 == ne22); + + GGML_ASSERT(!op->src[3] || op->src[3]->type == GGML_TYPE_F16); + GGML_ASSERT(!op->src[3] || op->src[3]->ne[1] >= GGML_PAD(op->src[0]->ne[1], 8) && + "the Flash-Attention Metal kernel requires the mask to be padded to 8 and at least n_queries big"); + + float scale; + float max_bias; + float logit_softcap; + + memcpy(&scale, ((const int32_t *) op->op_params) + 0, sizeof(scale)); + memcpy(&max_bias, ((const int32_t *) op->op_params) + 1, sizeof(max_bias)); + memcpy(&logit_softcap, ((const int32_t *) op->op_params) + 2, sizeof(logit_softcap)); + + if (logit_softcap != 0.0f) { + scale /= logit_softcap; + } + + const bool has_mask = op->src[3] != NULL; + const bool has_sinks = op->src[4] != NULL; + const bool has_bias = max_bias != 0.0f; + const bool has_scap = logit_softcap != 0.0f; + + const uint32_t n_head = op->src[0]->ne[2]; + const int32_t n_head_log2 = 1u << (uint32_t) floorf(log2f((float) n_head)); + + const float m0 = powf(2.0f, -(max_bias ) / n_head_log2); + const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); + + GGML_ASSERT(ne01 < 65536); + + if (!ggml_metal_op_flash_attn_ext_use_vec(op)) { + // half8x8 kernel + const int64_t nqptg = 8; // queries per threadgroup !! sync with kernel template arguments !! + const int64_t ncpsg = 64; // cache values per simdgroup !! sync with kernel template arguments !! + + GGML_ASSERT(nqptg <= 32); + GGML_ASSERT(nqptg % 8 == 0); + GGML_ASSERT(ncpsg % 32 == 0); + + const int is_q = ggml_is_quantized(op->src[1]->type) ? 1 : 0; + + // 2*(2*ncpsg) + // ncpsg soft_max values + ncpsg mask values + // + // 16*32*(nsg) + // the shared memory needed for the simdgroups to load the KV cache + // each thread loads (dequantizes) 16 head elements, there are 32 threads in th SG + // +#define FATTN_SMEM(nsg) (GGML_PAD((nqptg*(ne00 + 2*GGML_PAD(ne20, 64) + 2*(2*ncpsg)) + is_q*(16*32*(nsg)))*(sizeof(float)/2), 16)) + + //int64_t nsgmax = 4; + // + //if (is_q) { + // nsgmax = 2; + // while (true) { + // const size_t smem = FATTN_SMEM(nsgmax); + // if (smem > props_dev->max_theadgroup_memory_size) { + // break; + // } + // nsgmax *= 2; + // } + // nsgmax /= 2; + //} + + // simdgroups per threadgroup (a.k.a. warps) + //nsg = ne01 <= nqptg ? MAX(4, MIN(nsgmax, MIN(ne11/ncpsg, (int64_t) pipeline.maxTotalThreadsPerThreadgroup/32))) : 4; + int32_t nsg = 4; + + const size_t smem = FATTN_SMEM(nsg); + + ggml_metal_kargs_flash_attn_ext args = { + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.ne_12_2 =*/ ne12, + /*.ne_12_3 =*/ ne13, + /*.ns10 =*/ int32_t(nb11/nb10), + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ns20 =*/ int32_t(nb21/nb20), + /*.nb21 =*/ nb21, + /*.nb22 =*/ nb22, + /*.nb23 =*/ nb23, + /*.ne32 =*/ ne32, + /*.ne33 =*/ ne33, + /*.nb31 =*/ nb31, + /*.nb32 =*/ nb32, + /*.nb33 =*/ nb33, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.scale =*/ scale, + /*.max_bias =*/ max_bias, + /*.m0 =*/ m0, + /*.m1 =*/ m1, + /*.n_head_log2 =*/ n_head_log2, + /*.logit_softcap =*/ logit_softcap, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_flash_attn_ext(lib, op, has_mask, has_sinks, has_bias, has_scap, nsg); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), 3); + if (op->src[3]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[3]), 4); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 4); + } + if (op->src[4]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[4]), 5); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 5); + } + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 6); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nqptg - 1)/nqptg, ne02, ne03, 32, nsg, 1); +#undef FATTN_SMEM + } else { + // half4x4 kernel + const int64_t nqptg = 1; // queries per threadgroup !! sync with kernel template arguments !! + const int64_t ncpsg = 32; // cache values per simdgroup !! sync with kernel template arguments !! + const int64_t nkpsg = 1*ncpsg; + + GGML_ASSERT(nqptg <= 32); + GGML_ASSERT(nqptg % 1 == 0); + GGML_ASSERT(ncpsg % 32 == 0); + + // ne00 + 2*ncpsg*(nsg) + // for each query, we load it as f16 in shared memory (ne00) + // and store the soft_max values and the mask + // + // ne20*(nsg) + // each simdgroup has a full f32 head vector in shared mem to accumulate results + // +#define FATTN_SMEM(nsg) (GGML_PAD((nqptg*(GGML_PAD(ne00, 128) + 4*ncpsg*(nsg)) + 2*GGML_PAD(ne20, 128)*(nsg))*(sizeof(float)/2), 16)) + + int64_t nsgmax = 2; + while (true) { + const size_t smem = FATTN_SMEM(nsgmax); + // avoid using more than half of the threadgroup memory - can cause slow downs especially for large head sizes + if (smem > props_dev->max_theadgroup_memory_size/2) { + break; + } + nsgmax *= 2; + } + nsgmax /= 2; + + // simdgroups per threadgroup (a.k.a. warps) + //const int64_t nsgt = MAX(2, MIN(nsgmax, MIN((ne11 + nkpsg - 1)/(nkpsg), (int64_t) pipeline.maxTotalThreadsPerThreadgroup/32))); + const int64_t nsgt = MAX(2, MIN(nsgmax, MIN((ne11 + nkpsg - 1)/(nkpsg), (int64_t) 1024/32))); + + int64_t nsg = 1; + while (nsg <= nsgt) { + nsg *= 2; + } + nsg /= 2; + + // workgroups + // each workgroup handles nsg*nkpsg cache values + int32_t nwg = 1; + if (false) { + // for small KV caches, we could launch a single workgroup and write the results directly to dst/ + // however, this does not lead to significant improvement, so disabled + nwg = 1; + nsg = 4; + } else { + nwg = 32; + nsg = 1; + while (2*nwg*nsg*nkpsg < ne11 && nsg < 4) { + nsg *= 2; + } + } + + ggml_metal_kargs_flash_attn_ext_vec args = { + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne11 =*/ ne11, + /*.ne_12_2 =*/ ne12, + /*.ne_12_3 =*/ ne13, + /*.ns10 =*/ int32_t(nb11/nb10), + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ns20 =*/ int32_t(nb21/nb20), + /*.nb21 =*/ nb21, + /*.nb22 =*/ nb22, + /*.nb23 =*/ nb23, + /*.ne32 =*/ ne32, + /*.ne33 =*/ ne33, + /*.nb31 =*/ nb31, + /*.nb32 =*/ nb32, + /*.nb33 =*/ nb33, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.scale =*/ scale, + /*.max_bias =*/ max_bias, + /*.m0 =*/ m0, + /*.m1 =*/ m1, + /*.n_head_log2 =*/ n_head_log2, + /*.logit_softcap =*/ logit_softcap, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_flash_attn_ext_vec(lib, op, has_mask, has_sinks, has_bias, has_scap, nsg, nwg); + + GGML_ASSERT(nsg*32 <= ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), 3); + if (op->src[3]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[3]), 4); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 4); + } + if (op->src[4]) { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[4]), 5); + } else { + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op->src[0]), 5); + } + + const size_t smem = FATTN_SMEM(nsg); + + //printf("smem: %zu, max: %zu, nsg = %d, nsgmax = %d\n", smem, props_dev->max_theadgroup_memory_size, (int) nsg, (int) nsgmax); + GGML_ASSERT(smem <= props_dev->max_theadgroup_memory_size); + + if (nwg == 1) { + // using 1 workgroup -> write the result directly into dst + ggml_metal_encoder_set_buffer(enc, ggml_metal_get_buffer_id(op), 6); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nqptg - 1)/nqptg, ne02, ne03*nwg, 32, nsg, 1); + } else { + // sanity checks + GGML_ASSERT(ne01*ne02*ne03 == ne1*ne2*ne3); + GGML_ASSERT((uint64_t)ne1*ne2*ne3 <= (1u << 31)); + + ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(op); + + // write the results from each workgroup into a temp buffer + ggml_metal_buffer_id bid_tmp = bid_dst; + bid_tmp.offs += ggml_nbytes(op); + ggml_metal_encoder_set_buffer(enc, bid_tmp, 6); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + ggml_metal_encoder_dispatch_threadgroups(enc, (ne01 + nqptg - 1)/nqptg, ne02, ne03*nwg, 32, nsg, 1); + + // sync the 2 kernels + ggml_metal_op_concurrency_reset(ctx); + + // reduce the results from the workgroups + { + const int32_t nrows = ne1*ne2*ne3; + + ggml_metal_kargs_flash_attn_ext_vec_reduce args0 = { + nrows, + }; + + ggml_metal_pipeline_t pipeline0 = ggml_metal_library_get_pipeline_flash_attn_ext_vec_reduce(lib, op, ne20, nwg); + + ggml_metal_encoder_set_pipeline(enc, pipeline0); + ggml_metal_encoder_set_bytes (enc, &args0, sizeof(args0), 0); + ggml_metal_encoder_set_buffer (enc, bid_tmp, 1); + ggml_metal_encoder_set_buffer (enc, bid_dst, 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, 32*nwg, 1, 1); + } + } +#undef FATTN_SMEM + } + + return 1; +} + +int ggml_metal_op_bin(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const bool use_fusion = ctx->use_fusion; + + const int debug_fusion = ctx->debug_fusion; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint64_t, nb, op, nb); + + GGML_ASSERT(op->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(op->src[1]->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(op->src[0])); + GGML_ASSERT(ggml_is_contiguous_rows(op->src[1])); + + bool bcast_row = false; + + ggml_metal_buffer_id bid_src0 = ggml_metal_get_buffer_id(op->src[0]); + ggml_metal_buffer_id bid_src1 = ggml_metal_get_buffer_id(op->src[1]); + ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(op); + + ggml_metal_kargs_bin args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne10 =*/ ne10, + /*.ne11 =*/ ne11, + /*.ne12 =*/ ne12, + /*.ne13 =*/ ne13, + /*.nb10 =*/ nb10, + /*.nb11 =*/ nb11, + /*.nb12 =*/ nb12, + /*.nb13 =*/ nb13, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.offs =*/ 0, + /*.o1 =*/ { bid_src1.offs }, + }; + + ggml_op fops[8]; + + int n_fuse = 1; + + // c[0] = add(a, b[0]) + // c[1] = add(c[0], b[1]) + // c[2] = add(c[1], b[2]) + // ... + if (use_fusion) { + fops[0] = GGML_OP_ADD; + fops[1] = GGML_OP_ADD; + fops[2] = GGML_OP_ADD; + fops[3] = GGML_OP_ADD; + fops[4] = GGML_OP_ADD; + fops[5] = GGML_OP_ADD; + fops[6] = GGML_OP_ADD; + fops[7] = GGML_OP_ADD; + + // note: in metal, we sometimes encode the graph in parallel so we have to avoid fusing ops + // across splits. idx_end indicates the last node in the current split + for (n_fuse = 0; n_fuse <= 6; ++n_fuse) { + if (!ctx->can_fuse(idx + n_fuse, fops + n_fuse, 2)) { + break; + } + + ggml_tensor * f0 = ctx->node(idx + n_fuse); + ggml_tensor * f1 = ctx->node(idx + n_fuse + 1); + + if (f0 != f1->src[0]) { + break; + } + + // b[0] === b[1] === ... + if (!ggml_are_same_layout(f0->src[1], f1->src[1])) { + break; + } + + // only fuse ops if src1 is in the same Metal buffer + ggml_metal_buffer_id bid_fuse = ggml_metal_get_buffer_id(f1->src[1]); + if (bid_fuse.metal != bid_src1.metal) { + break; + } + + //ctx->fuse_cnt[ops[n_fuse + 1]->op]++; + + args.o1[n_fuse + 1] = bid_fuse.offs; + } + + ++n_fuse; + + if (debug_fusion > 1 && n_fuse > 1) { + GGML_LOG_DEBUG("%s: fuse: ADD x %d\n", __func__, n_fuse); + } + } + + // the offsets of src1 and all fused buffers are relative to the start of the src1 buffer + bid_src1.offs = 0; + + ggml_metal_pipeline_t pipeline = nullptr; + + if (ggml_nelements(op->src[1]) == ne10 && ggml_is_contiguous(op->src[1]) && ne00 % 4 == 0 && ne10 % 4 == 0) { + GGML_ASSERT(ggml_is_contiguous(op->src[0])); + + // src1 is a row + GGML_ASSERT(ne11 == 1); + + pipeline = ggml_metal_library_get_pipeline_bin(lib, op->op, n_fuse, true); + + bcast_row = true; + } else { + pipeline = ggml_metal_library_get_pipeline_bin(lib, op->op, n_fuse, false); + } + + if (n_fuse > 1) { + bid_dst = ggml_metal_get_buffer_id(ctx->node(idx + n_fuse - 1)); + + for (int i = 1; i < n_fuse; ++i) { + if (!ggml_metal_op_concurrency_check(ctx, ctx->node(idx + i))) { + ggml_metal_op_concurrency_reset(ctx); + + break; + } + } + } + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src0, 1); + ggml_metal_encoder_set_buffer (enc, bid_src1, 2); + ggml_metal_encoder_set_buffer (enc, bid_dst, 3); + + if (bcast_row) { + const int64_t n = ggml_nelements(op)/4; + + ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + } else { + int nth = 32; + + while (16*nth < ne0 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + } + + return n_fuse; +} + +int ggml_metal_op_l2_norm(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float eps; + memcpy(&eps, op->op_params, sizeof(float)); + + int nth = 32; // SIMD width + + ggml_metal_kargs_l2_norm args = { + /*.ne00 =*/ ne00, + /*.ne00_4 =*/ ne00/4, + /*.nb01 =*/ nb01, + /*.eps =*/ eps, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_l2_norm(lib, op); + + while (nth < ne00/4 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + nth = std::min(nth, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + nth = std::min(nth, ne00/4); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + const int64_t nrows = ggml_nrows(op->src[0]); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_group_norm(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int32_t ngrp = ((const int32_t *) op->op_params)[0]; + + float eps; + memcpy(&eps, op->op_params + 1, sizeof(float)); + + ggml_metal_kargs_group_norm args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.ngrp =*/ ngrp, + /*.eps =*/ eps, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_group_norm(lib, op); + + int nth = 32; // SIMD width + //while (nth < ne00/4 && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + // nth *= 2; + //} + + //nth = std::min(nth, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + //nth = std::min(nth, ne00/4); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ngrp, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_norm(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + const bool use_fusion = ctx->use_fusion; + + const int debug_fusion = ctx->debug_fusion; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float eps; + memcpy(&eps, op->op_params, sizeof(float)); + + ggml_metal_buffer_id bid_src0 = ggml_metal_get_buffer_id(op->src[0]); + ggml_metal_buffer_id bid_dst = ggml_metal_get_buffer_id(op); + + ggml_metal_kargs_norm args = { + /*.ne00 =*/ ne00, + /*.ne00_t =*/ ne00 % 4 == 0 ? ne00/4 : ne00, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.eps =*/ eps, + /*.nef1 =*/ { ne01 }, + /*.nef2 =*/ { ne02 }, + /*.nef3 =*/ { ne03 }, + /*.nbf1 =*/ { nb01 }, + /*.nbf2 =*/ { nb02 }, + /*.nbf3 =*/ { nb03 }, + }; + + ggml_op fops[8]; + + int n_fuse = 1; + + ggml_metal_buffer_id bid_fuse[2] = { bid_src0, bid_src0 }; + + // d[0] = norm(a) + // d[1] = mul(d[0], b) + // d[2] = add(d[1], c) + if (use_fusion) { + fops[0] = op->op; + fops[1] = GGML_OP_MUL; + fops[2] = GGML_OP_ADD; + + for (n_fuse = 0; n_fuse <= 1; ++n_fuse) { + if (!ctx->can_fuse(idx + n_fuse, fops + n_fuse, 2)) { + break; + } + + ggml_tensor * f0 = ctx->node(idx + n_fuse); + ggml_tensor * f1 = ctx->node(idx + n_fuse + 1); + + if (f0 != f1->src[0]) { + break; + } + + if (f1->src[1]->ne[0] != op->ne[0]) { + break; + } + + if (!ggml_is_contiguous_rows(f1->src[1])) { + break; + } + + if (f1->type != GGML_TYPE_F32) { + break; + } + + //ctx->fuse_cnt[f1->op]++; + + bid_fuse[n_fuse] = ggml_metal_get_buffer_id(f1->src[1]); + + args.nef1[n_fuse + 1] = f1->src[1]->ne[1]; + args.nef2[n_fuse + 1] = f1->src[1]->ne[2]; + args.nef3[n_fuse + 1] = f1->src[1]->ne[3]; + + args.nbf1[n_fuse + 1] = f1->src[1]->nb[1]; + args.nbf2[n_fuse + 1] = f1->src[1]->nb[2]; + args.nbf3[n_fuse + 1] = f1->src[1]->nb[3]; + } + + ++n_fuse; + + if (debug_fusion > 1 && n_fuse > 1) { + if (n_fuse == 2) { + GGML_LOG_DEBUG("%s: fuse: %s + MUL\n", __func__, ggml_op_name(op->op)); + } + if (n_fuse == 3) { + GGML_LOG_DEBUG("%s: fuse: %s + MUL + ADD\n", __func__, ggml_op_name(op->op)); + } + } + } + + if (n_fuse > 1) { + bid_dst = ggml_metal_get_buffer_id(ctx->node(idx + n_fuse - 1)); + + for (int i = 1; i < n_fuse; ++i) { + if (!ggml_metal_op_concurrency_check(ctx, ctx->node(idx + i))) { + ggml_metal_op_concurrency_reset(ctx); + + break; + } + } + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_norm(lib, op, n_fuse); + + int nth = 32; // SIMD width + + while (nth < args.ne00_t && nth < ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)) { + nth *= 2; + } + + nth = std::min(nth, ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + nth = std::min(nth, args.ne00_t); + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, bid_src0, 1); + ggml_metal_encoder_set_buffer (enc, bid_fuse[0], 2); + ggml_metal_encoder_set_buffer (enc, bid_fuse[1], 3); + ggml_metal_encoder_set_buffer (enc, bid_dst, 4); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + + return n_fuse; +} + +int ggml_metal_op_rope(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + // make sure we have one or more position id(ne10) per token(ne02) + GGML_ASSERT(ne10 % ne02 == 0); + GGML_ASSERT(ne10 >= ne02); + + const int nth = std::min(1024, ne00); + + const int n_past = ((const int32_t *) op->op_params)[0]; + const int n_dims = ((const int32_t *) op->op_params)[1]; + //const int mode = ((const int32_t *) op->op_params)[2]; + // skip 3, n_ctx, used in GLM RoPE, unimplemented in metal + const int n_ctx_orig = ((const int32_t *) op->op_params)[4]; + + float freq_base; + float freq_scale; + float ext_factor; + float attn_factor; + float beta_fast; + float beta_slow; + + memcpy(&freq_base, (const int32_t *) op->op_params + 5, sizeof(float)); + memcpy(&freq_scale, (const int32_t *) op->op_params + 6, sizeof(float)); + memcpy(&ext_factor, (const int32_t *) op->op_params + 7, sizeof(float)); + memcpy(&attn_factor, (const int32_t *) op->op_params + 8, sizeof(float)); + memcpy(&beta_fast, (const int32_t *) op->op_params + 9, sizeof(float)); + memcpy(&beta_slow, (const int32_t *) op->op_params + 10, sizeof(float)); + + // mrope + const int sect_0 = ((const int32_t *) op->op_params)[11]; + const int sect_1 = ((const int32_t *) op->op_params)[12]; + const int sect_2 = ((const int32_t *) op->op_params)[13]; + const int sect_3 = ((const int32_t *) op->op_params)[14]; + + ggml_metal_kargs_rope args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.n_past =*/ n_past, + /*.n_dims =*/ n_dims, + /*.n_ctx_orig =*/ n_ctx_orig, + /*.freq_base =*/ freq_base, + /*.freq_scale =*/ freq_scale, + /*.ext_factor =*/ ext_factor, + /*.attn_factor =*/ attn_factor, + /*.beta_fast =*/ beta_fast, + /*.beta_slow =*/ beta_slow, + /* sect_0 =*/ sect_0, + /* sect_1 =*/ sect_1, + /* sect_2 =*/ sect_2, + /* sect_3 =*/ sect_3, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_rope(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + if (op->src[2]) { + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[2]), 3); + } else { + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 3); + } + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 4); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne01, ne02, ne03, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_im2col(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int32_t s0 = ((const int32_t *)(op->op_params))[0]; + const int32_t s1 = ((const int32_t *)(op->op_params))[1]; + const int32_t p0 = ((const int32_t *)(op->op_params))[2]; + const int32_t p1 = ((const int32_t *)(op->op_params))[3]; + const int32_t d0 = ((const int32_t *)(op->op_params))[4]; + const int32_t d1 = ((const int32_t *)(op->op_params))[5]; + + const bool is_2D = ((const int32_t *)(op->op_params))[6] == 1; + + const int32_t N = op->src[1]->ne[is_2D ? 3 : 2]; + const int32_t IC = op->src[1]->ne[is_2D ? 2 : 1]; + const int32_t IH = is_2D ? op->src[1]->ne[1] : 1; + const int32_t IW = op->src[1]->ne[0]; + + const int32_t KH = is_2D ? op->src[0]->ne[1] : 1; + const int32_t KW = op->src[0]->ne[0]; + + const int32_t OH = is_2D ? op->ne[2] : 1; + const int32_t OW = op->ne[1]; + + const int32_t CHW = IC * KH * KW; + + const uint64_t ofs0 = op->src[1]->nb[is_2D ? 3 : 2] / 4; + const uint64_t ofs1 = op->src[1]->nb[is_2D ? 2 : 1] / 4; + + ggml_metal_kargs_im2col args = { + /*.ofs0 =*/ ofs0, + /*.ofs1 =*/ ofs1, + /*.IW =*/ IW, + /*.IH =*/ IH, + /*.CHW =*/ CHW, + /*.s0 =*/ s0, + /*.s1 =*/ s1, + /*.p0 =*/ p0, + /*.p1 =*/ p1, + /*.d0 =*/ d0, + /*.d1 =*/ d1, + /*.N =*/ N, + /*.KH =*/ KH, + /*.KW =*/ KW, + /*.KHW =*/ KH * KW, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_im2col(lib, op); + + GGML_ASSERT(KH*KW <= ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)); + + const uint64_t ntptg0 = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline)/(KH*KW), N); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, IC, OH, OW, ntptg0, KH, KW); + + return 1; +} + +int ggml_metal_op_conv_transpose_1d(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne1, op->src[1], ne); + GGML_TENSOR_LOCALS(uint64_t, nb1, op->src[1], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int32_t s0 = ((const int32_t *)(op->op_params))[0]; + + const int32_t IC = op->src[1]->ne[1]; + const int32_t IL = op->src[1]->ne[0]; + + const int32_t K = op->src[0]->ne[0]; + + const int32_t OL = op->ne[0]; + const int32_t OC = op->ne[1]; + + ggml_metal_kargs_conv_transpose_1d args = { + /*.IC =*/ IC, + /*.IL =*/ IL, + /*.K =*/ K, + /*.s0 =*/ s0, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_conv_transpose_1d(lib, op); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[1]), 2); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 3); + + ggml_metal_encoder_dispatch_threadgroups(enc, OL, OC, 1, 1, 1, 1); + + return 1; +} + +int ggml_metal_op_upscale(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const float sf0 = (float)ne0/op->src[0]->ne[0]; + const float sf1 = (float)ne1/op->src[0]->ne[1]; + const float sf2 = (float)ne2/op->src[0]->ne[2]; + const float sf3 = (float)ne3/op->src[0]->ne[3]; + + ggml_metal_kargs_upscale args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.sf0 =*/ sf0, + /*.sf1 =*/ sf1, + /*.sf2 =*/ sf2, + /*.sf3 =*/ sf3 + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_upscale(lib, op); + + const int nth = std::min(ggml_metal_pipeline_max_theads_per_threadgroup(pipeline), ne0); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne1, ne2, ne3, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_pad(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_kargs_pad args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3 + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_pad(lib, op); + + const int nth = std::min(1024, ne0); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne1, ne2, ne3, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_pad_reflect_1d(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_kargs_pad_reflect_1d args = { + /*.ne00 =*/ ne00, + /*.ne01 =*/ ne01, + /*.ne02 =*/ ne02, + /*.ne03 =*/ ne03, + /*.nb00 =*/ nb00, + /*.nb01 =*/ nb01, + /*.nb02 =*/ nb02, + /*.nb03 =*/ nb03, + /*.ne0 =*/ ne0, + /*.ne1 =*/ ne1, + /*.ne2 =*/ ne2, + /*.ne3 =*/ ne3, + /*.nb0 =*/ nb0, + /*.nb1 =*/ nb1, + /*.nb2 =*/ nb2, + /*.nb3 =*/ nb3, + /*.p0 =*/ ((const int32_t *)(op->op_params))[0], + /*.p1 =*/ ((const int32_t *)(op->op_params))[1] + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_pad_reflect_1d(lib, op); + + const int nth = std::min(1024, ne0); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne1, ne2, ne3, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_arange(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float start; + float step; + + memcpy(&start, ((const int32_t *) op->op_params) + 0, sizeof(float)); + memcpy(&step, ((const int32_t *) op->op_params) + 2, sizeof(float)); + + ggml_metal_kargs_arange args = { + /*.ne0 =*/ ne0, + /*.start =*/ start, + /*.step =*/ step + }; + + const int nth = std::min(1024, ne0); + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_arange(lib, op); + + //[encoder setComputePipelineState:pipeline]; + //[encoder setBuffer:id_dst offset:offs_dst atIndex:0]; + //[encoder setBytes:&args length:sizeof(args) atIndex:1]; + + //[encoder dispatchThreadgroups:MTLSizeMake(1, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 1); + + ggml_metal_encoder_dispatch_threadgroups(enc, 1, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_timestep_embedding(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + const int dim = op->op_params[0]; + const int max_period = op->op_params[1]; + + ggml_metal_kargs_timestep_embedding args = { + /*.nb1 =*/ nb1, + /*.dim =*/ dim, + /*.max_period =*/ max_period, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_timestep_embedding(lib, op); + + const int nth = std::max(1, std::min(1024, dim/2)); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, ne00, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_argmax(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + ggml_metal_kargs_argmax args = { + /*.ne00 = */ ne00, + /*.nb01 = */ nb01, + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_argmax(lib, op); + + const int64_t nrows = ggml_nrows(op->src[0]); + + int nth = 32; // SIMD width + while (nth < ne00 && nth*ne01*ne02*ne03 < 256) { + nth *= 2; + } + + const size_t smem = ggml_metal_pipeline_get_smem(pipeline); + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, nrows, 1, 1, nth, 1, 1); + + return 1; +} + +int ggml_metal_op_argsort(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + // bitonic sort requires the number of elements to be power of 2 + int64_t ne00_padded = 1; + while (ne00_padded < ne00) { + ne00_padded *= 2; + } + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_argsort(lib, op); + + const int64_t nrows = ggml_nrows(op->src[0]); + + // Metal kernels require the buffer size to be multiple of 16 bytes + // https://developer.apple.com/documentation/metal/mtlcomputecommandencoder/1443142-setthreadgroupmemorylength + const size_t smem = GGML_PAD(ne00_padded*sizeof(int32_t), 16); + + ggml_metal_kargs_argsort args = { + /*.ncols =*/ ne00, + /*.ncols_pad =*/ ne00_padded + }; + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_set_threadgroup_memory_size(enc, smem, 0); + + ggml_metal_encoder_dispatch_threadgroups(enc, 1, nrows, 1, ne00_padded, 1, 1); + + return 1; +} + +int ggml_metal_op_leaky_relu(ggml_metal_op_t ctx, int idx) { + ggml_tensor * op = ctx->node(idx); + + ggml_metal_library_t lib = ctx->lib; + ggml_metal_encoder_t enc = ctx->enc; + + GGML_TENSOR_LOCALS( int32_t, ne0, op->src[0], ne); + GGML_TENSOR_LOCALS(uint64_t, nb0, op->src[0], nb); + GGML_TENSOR_LOCALS( int32_t, ne, op, ne); + GGML_TENSOR_LOCALS(uint32_t, nb, op, nb); + + float slope; + memcpy(&slope, op->op_params, sizeof(float)); + + ggml_metal_kargs_leaky_relu args = { + /*.slope =*/ slope + }; + + ggml_metal_pipeline_t pipeline = ggml_metal_library_get_pipeline_unary(lib, op); + + int64_t n = ggml_nelements(op); + + if (n % 4 == 0) { + n /= 4; + } + + ggml_metal_encoder_set_pipeline(enc, pipeline); + ggml_metal_encoder_set_bytes (enc, &args, sizeof(args), 0); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op->src[0]), 1); + ggml_metal_encoder_set_buffer (enc, ggml_metal_get_buffer_id(op), 2); + + ggml_metal_encoder_dispatch_threadgroups(enc, n, 1, 1, 1, 1, 1); + + return 1; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.h 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.h --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.h 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal-ops.h 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,82 @@ +#pragma once + +#include "ggml-metal-device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct ggml_metal_op * ggml_metal_op_t; + +ggml_metal_op_t ggml_metal_op_init( + ggml_metal_device_t dev, + ggml_metal_cmd_buf_t cmd_buf, + struct ggml_cgraph * gf, + int idx_start, + int idx_end, + bool use_fusion, + bool use_concurrency, + bool use_capture, + int debug_graph, + int debug_fusion); + +void ggml_metal_op_free(ggml_metal_op_t ctx); + +int ggml_metal_op_n_nodes(ggml_metal_op_t ctx); + +int ggml_metal_op_encode(ggml_metal_op_t ctx, int idx); + +// +// available ops: +// + +// tokens per expert +size_t ggml_metal_op_mul_mat_id_extra_tpe(const struct ggml_tensor * op); + +// id map [n_tokens, n_expert] +size_t ggml_metal_op_mul_mat_id_extra_ids(const struct ggml_tensor * op); + +// return true if we should use the FA vector kernel for this op +bool ggml_metal_op_flash_attn_ext_use_vec(const struct ggml_tensor * op); + +size_t ggml_metal_op_flash_attn_ext_extra_tmp(const struct ggml_tensor * op); + +int ggml_metal_op_concat (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_repeat (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_acc (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_scale (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_clamp (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_unary (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_glu (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_sum_rows (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_get_rows (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_set_rows (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_soft_max (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_ssm_conv (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_ssm_scan (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_rwkv (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_cpy (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_pool_2d (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_mul_mat (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_mul_mat_id (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_add_id (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_flash_attn_ext (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_bin (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_l2_norm (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_group_norm (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_norm (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_rope (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_im2col (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_conv_transpose_1d (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_upscale (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_pad (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_pad_reflect_1d (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_arange (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_timestep_embedding(ggml_metal_op_t ctx, int idx); +int ggml_metal_op_argmax (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_argsort (ggml_metal_op_t ctx, int idx); +int ggml_metal_op_leaky_relu (ggml_metal_op_t ctx, int idx); + +#ifdef __cplusplus +} +#endif diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.cpp 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.cpp --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.cpp 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,718 @@ +#include "ggml-metal.h" + +#include "ggml-impl.h" +#include "ggml-backend-impl.h" + +#include "ggml-metal-device.h" +#include "ggml-metal-context.h" +#include "ggml-metal-ops.h" + +// globals + +// initialized in ggml_backend_metal_reg +static ggml_backend_reg g_ggml_metal_reg; +static ggml_backend_device g_ggml_metal_device; + +//////////////////////////////////////////////////////////////////////////////// +// backend interface +//////////////////////////////////////////////////////////////////////////////// + +// shared buffer + +static void ggml_backend_metal_buffer_shared_free_buffer(ggml_backend_buffer_t buffer) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_free(ctx); +} + +static void * ggml_backend_metal_buffer_shared_get_base(ggml_backend_buffer_t buffer) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + return ggml_metal_buffer_get_base(ctx); +} + +static void ggml_backend_metal_buffer_shared_memset_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_memset_tensor(ctx, tensor, value, offset, size); +} + +static void ggml_backend_metal_buffer_shared_set_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_set_tensor(ctx, tensor, data, offset, size); +} + +static void ggml_backend_metal_buffer_shared_get_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_get_tensor(ctx, tensor, data, offset, size); +} + +static bool ggml_backend_metal_buffer_shared_cpy_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * src, ggml_tensor * dst) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + GGML_UNUSED(buffer); + GGML_UNUSED(src); + GGML_UNUSED(dst); + + return false; +} + +static void ggml_backend_metal_buffer_shared_clear(ggml_backend_buffer_t buffer, uint8_t value) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_clear(ctx, value); +} + +static ggml_backend_buffer_i ggml_backend_metal_buffer_shared_i = { + /* .free_buffer = */ ggml_backend_metal_buffer_shared_free_buffer, + /* .get_base = */ ggml_backend_metal_buffer_shared_get_base, + /* .init_tensor = */ NULL, + /* .memset_tensor = */ ggml_backend_metal_buffer_shared_memset_tensor, + /* .set_tensor = */ ggml_backend_metal_buffer_shared_set_tensor, + /* .get_tensor = */ ggml_backend_metal_buffer_shared_get_tensor, + /* .cpy_tensor = */ ggml_backend_metal_buffer_shared_cpy_tensor, + /* .clear = */ ggml_backend_metal_buffer_shared_clear, + /* .reset = */ NULL, +}; + +// private buffer + +static void ggml_backend_metal_buffer_private_free_buffer(ggml_backend_buffer_t buffer) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_free(ctx); +} + +static void * ggml_backend_metal_buffer_private_get_base(ggml_backend_buffer_t buffer) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + return ggml_metal_buffer_get_base(ctx); +} + +static void ggml_backend_metal_buffer_private_memset_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_memset_tensor(ctx, tensor, value, offset, size); +} + +static void ggml_backend_metal_buffer_private_set_tensor(ggml_backend_buffer_t buffer, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_set_tensor(ctx, tensor, data, offset, size); +} + +static void ggml_backend_metal_buffer_private_get_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_get_tensor(ctx, tensor, data, offset, size); +} + +static bool ggml_backend_metal_buffer_private_cpy_tensor(ggml_backend_buffer_t buffer, const ggml_tensor * src, ggml_tensor * dst) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + GGML_UNUSED(buffer); + GGML_UNUSED(src); + GGML_UNUSED(dst); + + return false; +} + +static void ggml_backend_metal_buffer_private_clear(ggml_backend_buffer_t buffer, uint8_t value) { + ggml_metal_buffer_t ctx = (ggml_metal_buffer_t)buffer->context; + + GGML_ASSERT(!ggml_metal_buffer_is_shared(ctx)); + + ggml_metal_buffer_clear(ctx, value); +} + +static ggml_backend_buffer_i ggml_backend_metal_buffer_private_i = { + /* .free_buffer = */ ggml_backend_metal_buffer_private_free_buffer, + /* .get_base = */ ggml_backend_metal_buffer_private_get_base, + /* .init_tensor = */ NULL, + /* .memset_tensor = */ ggml_backend_metal_buffer_private_memset_tensor, + /* .set_tensor = */ ggml_backend_metal_buffer_private_set_tensor, + /* .get_tensor = */ ggml_backend_metal_buffer_private_get_tensor, + /* .cpy_tensor = */ ggml_backend_metal_buffer_private_cpy_tensor, + /* .clear = */ ggml_backend_metal_buffer_private_clear, + /* .reset = */ NULL, +}; + +// +// buffer types +// + +// common method for allocating shread or private Metal buffers +static ggml_backend_buffer_t ggml_backend_metal_buffer_type_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size, bool shared) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)buft->device->context; + ggml_metal_buffer_t res = ggml_metal_buffer_init(ctx_dev, size, shared); + + ggml_backend_buffer_i buf_i = ggml_metal_buffer_is_shared(res) + ? ggml_backend_metal_buffer_shared_i + : ggml_backend_metal_buffer_private_i; + + return ggml_backend_buffer_init(buft, buf_i, res, size); +} + +static size_t ggml_backend_metal_buffer_type_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { + size_t res = ggml_nbytes(tensor); + + // some operations require additional memory for fleeting data: + switch (tensor->op) { + case GGML_OP_MUL_MAT_ID: + { + res += ggml_metal_op_mul_mat_id_extra_tpe(tensor); + res += ggml_metal_op_mul_mat_id_extra_ids(tensor); + } break; + case GGML_OP_FLASH_ATTN_EXT: + { + if (ggml_metal_op_flash_attn_ext_use_vec(tensor)) { + res += ggml_metal_op_flash_attn_ext_extra_tmp(tensor); + } + } break; + default: + break; + } + + return res; + + GGML_UNUSED(buft); +} + +// default (shared) buffer type + +static const char * ggml_backend_metal_buffer_type_shared_get_name(ggml_backend_buffer_type_t buft) { + return "Metal"; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_t ggml_backend_metal_buffer_type_shared_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size) { + return ggml_backend_metal_buffer_type_alloc_buffer(buft, size, true); +} + +static size_t ggml_backend_metal_buffer_type_shared_get_alignment(ggml_backend_buffer_type_t buft) { + return 32; + + GGML_UNUSED(buft); +} + +static size_t ggml_backend_metal_buffer_type_shared_get_max_size(ggml_backend_buffer_type_t buft) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)buft->device->context; + + return ggml_metal_device_get_props(ctx_dev)->max_buffer_size; +} + +static size_t ggml_backend_metal_buffer_type_shared_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { + return ggml_backend_metal_buffer_type_get_alloc_size(buft, tensor); +} + +static bool ggml_backend_metal_buffer_type_shared_is_host(ggml_backend_buffer_type_t buft) { + return false; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_type_t ggml_backend_metal_buffer_type_shared(void) { + static ggml_backend_buffer_type ggml_backend_buffer_type_metal = { + /* .iface = */ { + /* .get_name = */ ggml_backend_metal_buffer_type_shared_get_name, + /* .alloc_buffer = */ ggml_backend_metal_buffer_type_shared_alloc_buffer, + /* .get_alignment = */ ggml_backend_metal_buffer_type_shared_get_alignment, + /* .get_max_size = */ ggml_backend_metal_buffer_type_shared_get_max_size, + /* .get_alloc_size = */ ggml_backend_metal_buffer_type_shared_get_alloc_size, + /* .is_host = */ ggml_backend_metal_buffer_type_shared_is_host, + }, + /* .device = */ &g_ggml_metal_device, + /* .context = */ NULL, + }; + + return &ggml_backend_buffer_type_metal; +} + +// default (private) buffer type + +static const char * ggml_backend_metal_buffer_type_private_get_name(ggml_backend_buffer_type_t buft) { + return "Metal_Private"; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_t ggml_backend_metal_buffer_type_private_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size) { + return ggml_backend_metal_buffer_type_alloc_buffer(buft, size, false); +} + +static size_t ggml_backend_metal_buffer_type_private_get_alignment(ggml_backend_buffer_type_t buft) { + return 32; + + GGML_UNUSED(buft); +} + +static size_t ggml_backend_metal_buffer_type_private_get_max_size(ggml_backend_buffer_type_t buft) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)buft->device->context; + + return ggml_metal_device_get_props(ctx_dev)->max_buffer_size; +} + +static size_t ggml_backend_metal_buffer_type_private_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { + return ggml_backend_metal_buffer_type_get_alloc_size(buft, tensor); +} + +static bool ggml_backend_metal_buffer_type_private_is_host(ggml_backend_buffer_type_t buft) { + return false; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_type_t ggml_backend_metal_buffer_type_private(void) { + static ggml_backend_buffer_type ggml_backend_buffer_type_metal = { + /* .iface = */ { + /* .get_name = */ ggml_backend_metal_buffer_type_private_get_name, + /* .alloc_buffer = */ ggml_backend_metal_buffer_type_private_alloc_buffer, + /* .get_alignment = */ ggml_backend_metal_buffer_type_private_get_alignment, + /* .get_max_size = */ ggml_backend_metal_buffer_type_private_get_max_size, + /* .get_alloc_size = */ ggml_backend_metal_buffer_type_private_get_alloc_size, + /* .is_host = */ ggml_backend_metal_buffer_type_private_is_host, + }, + /* .device = */ &g_ggml_metal_device, + /* .context = */ NULL, + }; + + return &ggml_backend_buffer_type_metal; +} + +// mapped buffer type + +static const char * ggml_backend_metal_buffer_type_mapped_get_name(ggml_backend_buffer_type_t buft) { + return "Metal_Mapped"; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_t ggml_backend_metal_buffer_type_mapped_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size) { + // for mapped buffers, prefer shared memory + return ggml_backend_metal_buffer_type_alloc_buffer(buft, size, true); +} + +static size_t ggml_backend_metal_buffer_type_mapped_get_alignment(ggml_backend_buffer_type_t buft) { + return 32; + + GGML_UNUSED(buft); +} + +static size_t ggml_backend_metal_buffer_type_mapped_get_max_size(ggml_backend_buffer_type_t buft) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)buft->device->context; + + return ggml_metal_device_get_props(ctx_dev)->max_buffer_size; +} + +static size_t ggml_backend_metal_buffer_type_mapped_get_alloc_size(ggml_backend_buffer_type_t buft, const ggml_tensor * tensor) { + return ggml_backend_metal_buffer_type_get_alloc_size(buft, tensor); +} + +static bool ggml_backend_metal_buffer_type_mapped_is_host(ggml_backend_buffer_type_t buft) { + return false; + + GGML_UNUSED(buft); +} + +static ggml_backend_buffer_type_t ggml_backend_metal_buffer_type_mapped(void) { + // note: not obvious, but this buffer type still needs to implement .alloc_buffer: + // https://github.com/ggml-org/llama.cpp/pull/15832#discussion_r2333177099 + static ggml_backend_buffer_type ggml_backend_buffer_type_mapped_metal = { + /* .iface = */ { + /* .get_name = */ ggml_backend_metal_buffer_type_mapped_get_name, + /* .alloc_buffer = */ ggml_backend_metal_buffer_type_mapped_alloc_buffer, + /* .get_alignment = */ ggml_backend_metal_buffer_type_mapped_get_alignment, + /* .get_max_size = */ ggml_backend_metal_buffer_type_mapped_get_max_size, + /* .get_alloc_size = */ ggml_backend_metal_buffer_type_mapped_get_alloc_size, + /* .is_host = */ ggml_backend_metal_buffer_type_mapped_is_host, + }, + /* .device = */ &g_ggml_metal_device, + /* .context = */ NULL, + }; + + return &ggml_backend_buffer_type_mapped_metal; +} + +// backend + +static const char * ggml_backend_metal_name(ggml_backend_t backend) { + return "Metal"; + + GGML_UNUSED(backend); +} + +static void ggml_backend_metal_free(ggml_backend_t backend) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + // wait for any ongoing async operations to finish + ggml_metal_synchronize(ctx); + + ggml_metal_free(ctx); + + free(backend); +} + +static void ggml_backend_metal_synchronize(ggml_backend_t backend) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_synchronize(ctx); +} + +static void ggml_backend_metal_set_tensor_async(ggml_backend_t backend, ggml_tensor * tensor, const void * data, size_t offset, size_t size) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_set_tensor_async(ctx, tensor, data, offset, size); +} + +static void ggml_backend_metal_get_tensor_async(ggml_backend_t backend, const ggml_tensor * tensor, void * data, size_t offset, size_t size) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_get_tensor_async(ctx, tensor, data, offset, size); +} + +static bool ggml_backend_metal_cpy_tensor_async(ggml_backend_t backend_src, ggml_backend_t backend_dst, const ggml_tensor * src, ggml_tensor * dst) { + return false; + + GGML_UNUSED(backend_src); + GGML_UNUSED(backend_dst); + GGML_UNUSED(src); + GGML_UNUSED(dst); +} + +static enum ggml_status ggml_backend_metal_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + return ggml_metal_graph_compute(ctx, cgraph); +} + +static void ggml_backend_metal_graph_optimize(ggml_backend_t backend, ggml_cgraph * cgraph) { + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_graph_optimize(ctx, cgraph); +} + +static void ggml_backend_metal_set_n_cb(ggml_backend_t backend, int n_cb) { + GGML_ASSERT(ggml_backend_is_metal(backend)); + + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_set_n_cb(ctx, n_cb); + +} + +static ggml_backend_i ggml_backend_metal_i = { + /* .get_name = */ ggml_backend_metal_name, + /* .free = */ ggml_backend_metal_free, + /* .set_tensor_async = */ ggml_backend_metal_set_tensor_async, + /* .get_tensor_async = */ ggml_backend_metal_get_tensor_async, + /* .cpy_tensor_async = */ ggml_backend_metal_cpy_tensor_async, // only needed for multi-GPU setups + /* .synchronize = */ ggml_backend_metal_synchronize, + /* .graph_plan_create = */ NULL, + /* .graph_plan_free = */ NULL, + /* .graph_plan_update = */ NULL, + /* .graph_plan_compute = */ NULL, + /* .graph_compute = */ ggml_backend_metal_graph_compute, + + // the events API is needed only for multi-GPU setups, so likely no need to implement it for Metal + // in any case, these docs seem relevant if we ever decide to implement it: + // https://developer.apple.com/documentation/metal/mtlcommandbuffer#Synchronizing-Passes-with-Events + /* .event_record = */ NULL, + /* .event_wait = */ NULL, + /* .graph_optimize = */ ggml_backend_metal_graph_optimize, +}; + +static ggml_guid_t ggml_backend_metal_guid(void) { + static ggml_guid guid = { 0x81, 0xa1, 0x8b, 0x1e, 0x71, 0xec, 0x79, 0xed, 0x2b, 0x85, 0xdc, 0x8a, 0x61, 0x98, 0x30, 0xe6 }; + return &guid; +} + +ggml_backend_t ggml_backend_metal_init(void) { + ggml_backend_dev_t dev = ggml_backend_reg_dev_get(ggml_backend_metal_reg(), 0); + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + ggml_metal_t ctx = ggml_metal_init(ctx_dev); + if (ctx == NULL) { + GGML_LOG_ERROR("%s: error: failed to allocate context\n", __func__); + return NULL; + } + + ggml_backend_t backend = (ggml_backend_t) malloc(sizeof(ggml_backend)); + + *backend = { + /* .guid = */ ggml_backend_metal_guid(), + /* .interface = */ ggml_backend_metal_i, + /* .device = */ dev, + /* .context = */ ctx, + }; + + ggml_backend_metal_set_n_cb(backend, 1); + + return backend; +} + +bool ggml_backend_is_metal(ggml_backend_t backend) { + return backend != NULL && ggml_guid_matches(backend->guid, ggml_backend_metal_guid()); +} + +void ggml_backend_metal_set_abort_callback(ggml_backend_t backend, ggml_abort_callback abort_callback, void * user_data) { + GGML_ASSERT(ggml_backend_is_metal(backend)); + + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_set_abort_callback(ctx, abort_callback, user_data); +} + +bool ggml_backend_metal_supports_family(ggml_backend_t backend, int family) { + GGML_ASSERT(ggml_backend_is_metal(backend)); + + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + return ggml_metal_supports_family(ctx, family); +} + +void ggml_backend_metal_capture_next_compute(ggml_backend_t backend) { + GGML_ASSERT(ggml_backend_is_metal(backend)); + + ggml_metal_t ctx = (ggml_metal_t)backend->context; + + ggml_metal_capture_next_compute(ctx); +} + +// backend device + +static const char * ggml_backend_metal_device_get_name(ggml_backend_dev_t dev) { + return "Metal"; + + GGML_UNUSED(dev); +} + +static const char * ggml_backend_metal_device_get_description(ggml_backend_dev_t dev) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + return ggml_metal_device_get_props(ctx_dev)->name; +} + +static void ggml_backend_metal_device_get_memory(ggml_backend_dev_t dev, size_t * free, size_t * total) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + ggml_metal_device_get_memory(ctx_dev, free, total); +} + +static enum ggml_backend_dev_type ggml_backend_metal_device_get_type(ggml_backend_dev_t dev) { + return GGML_BACKEND_DEVICE_TYPE_GPU; + + GGML_UNUSED(dev); +} + +static void ggml_backend_metal_device_get_props(ggml_backend_dev_t dev, ggml_backend_dev_props * props) { + props->name = ggml_backend_metal_device_get_name(dev); + props->description = ggml_backend_metal_device_get_description(dev); + props->type = ggml_backend_metal_device_get_type(dev); + + ggml_backend_metal_device_get_memory(dev, &props->memory_free, &props->memory_total); + + props->caps = { + /* .async = */ true, + /* .host_buffer = */ false, + /* .buffer_from_host_ptr = */ true, + /* .events = */ false, + }; +} + +static ggml_backend_t ggml_backend_metal_device_init(ggml_backend_dev_t dev, const char * params) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + ggml_metal_t ctx = ggml_metal_init(ctx_dev); + if (ctx == NULL) { + GGML_LOG_ERROR("%s: error: failed to allocate context\n", __func__); + return NULL; + } + + ggml_backend_t backend = (ggml_backend_t) malloc(sizeof(ggml_backend)); + + *backend = { + /* .guid = */ ggml_backend_metal_guid(), + /* .interface = */ ggml_backend_metal_i, + /* .device = */ dev, + /* .context = */ ctx, + }; + + ggml_backend_metal_set_n_cb(backend, 1); + + return backend; + + GGML_UNUSED(params); +} + +static ggml_backend_buffer_type_t ggml_backend_metal_device_get_buffer_type(ggml_backend_dev_t dev) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + const ggml_metal_device_props * props_dev = ggml_metal_device_get_props(ctx_dev); + + return props_dev->use_shared_buffers ? ggml_backend_metal_buffer_type_shared() : ggml_backend_metal_buffer_type_private(); +} + +static ggml_backend_buffer_t ggml_backend_metal_device_buffer_mapped(ggml_backend_dev_t dev, void * ptr, size_t size, size_t max_tensor_size) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + ggml_metal_buffer_t res = ggml_metal_buffer_map(ctx_dev, ptr, size, max_tensor_size); + + return ggml_backend_buffer_init(ggml_backend_metal_buffer_type_mapped(), ggml_backend_metal_buffer_shared_i, res, size); +} + +static bool ggml_backend_metal_device_supports_op(ggml_backend_dev_t dev, const ggml_tensor * op) { + ggml_metal_device_t ctx_dev = (ggml_metal_device_t)dev->context; + + return ggml_metal_device_supports_op(ctx_dev, op); +} + +static bool ggml_backend_metal_device_supports_buft(ggml_backend_dev_t dev, ggml_backend_buffer_type_t buft) { + return + buft->iface.get_name == ggml_backend_metal_buffer_type_shared_get_name || + buft->iface.get_name == ggml_backend_metal_buffer_type_private_get_name || + buft->iface.get_name == ggml_backend_metal_buffer_type_mapped_get_name; + + GGML_UNUSED(dev); +} + +static int64_t get_op_batch_size(const ggml_tensor * op) { + switch (op->op) { + case GGML_OP_MUL_MAT: + return op->ne[1]; + case GGML_OP_MUL_MAT_ID: + return op->ne[2]; + default: + return ggml_nrows(op); + } +} + +static bool ggml_backend_metal_device_offload_op(ggml_backend_dev_t dev, const ggml_tensor * op) { + const int min_batch_size = 32; + + return (op->op == GGML_OP_MUL_MAT || + op->op == GGML_OP_MUL_MAT_ID) && + get_op_batch_size(op) >= min_batch_size; + + GGML_UNUSED(dev); + GGML_UNUSED(op); +} + +static ggml_backend_device_i ggml_backend_metal_device_i = { + /* .get_name = */ ggml_backend_metal_device_get_name, + /* .get_description = */ ggml_backend_metal_device_get_description, + /* .get_memory = */ ggml_backend_metal_device_get_memory, + /* .get_type = */ ggml_backend_metal_device_get_type, + /* .get_props = */ ggml_backend_metal_device_get_props, + /* .init_backend = */ ggml_backend_metal_device_init, + /* .get_buffer_type = */ ggml_backend_metal_device_get_buffer_type, + /* .get_host_buffer_type = */ NULL, + /* .buffer_from_host_ptr = */ ggml_backend_metal_device_buffer_mapped, + /* .supports_op = */ ggml_backend_metal_device_supports_op, + /* .supports_buft = */ ggml_backend_metal_device_supports_buft, + /* .offload_op = */ ggml_backend_metal_device_offload_op, + /* .event_new = */ NULL, + /* .event_free = */ NULL, + /* .event_synchronize = */ NULL, +}; + +// backend registry + +static const char * ggml_backend_metal_reg_get_name(ggml_backend_reg_t reg) { + return "Metal"; + + GGML_UNUSED(reg); +} + +static size_t ggml_backend_metal_reg_device_count(ggml_backend_reg_t reg) { + return 1; + + GGML_UNUSED(reg); +} + +static ggml_backend_dev_t ggml_backend_metal_reg_device_get(ggml_backend_reg_t reg, size_t index) { + GGML_ASSERT(index == 0); + + return &g_ggml_metal_device; + + GGML_UNUSED(reg); + GGML_UNUSED(index); +} + +static ggml_backend_feature g_ggml_backend_metal_features[] = { +#if defined(GGML_METAL_EMBED_LIBRARY) + { "EMBED_LIBRARY", "1" }, +#endif + { NULL, NULL }, +}; + +static ggml_backend_feature * ggml_backend_metal_get_features(ggml_backend_reg_t reg) { + return g_ggml_backend_metal_features; + + GGML_UNUSED(reg); +} + +static void * ggml_backend_metal_get_proc_address(ggml_backend_reg_t reg, const char * name) { + if (strcmp(name, "ggml_backend_get_features") == 0) { + return (void *)ggml_backend_metal_get_features; + } + + return NULL; + + GGML_UNUSED(reg); +} + +static ggml_backend_reg_i ggml_backend_metal_reg_i = { + /* .get_name = */ ggml_backend_metal_reg_get_name, + /* .device_count = */ ggml_backend_metal_reg_device_count, + /* .device_get = */ ggml_backend_metal_reg_device_get, + /* .get_proc_address = */ ggml_backend_metal_get_proc_address, +}; + +ggml_backend_reg_t ggml_backend_metal_reg(void) { + { + g_ggml_metal_reg = { + /* .api_version = */ GGML_BACKEND_API_VERSION, + /* .iface = */ ggml_backend_metal_reg_i, + /* .context = */ NULL, + }; + + g_ggml_metal_device = { + /* .iface = */ ggml_backend_metal_device_i, + /* .reg = */ &g_ggml_metal_reg, + /* .context = */ ggml_metal_device_get(), + }; + } + + return &g_ggml_metal_reg; +} + +GGML_BACKEND_DL_IMPL(ggml_backend_metal_reg) diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.m 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.m --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.m 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.m 1970-01-01 00:00:00.000000000 +0000 @@ -1,6337 +0,0 @@ -#import "ggml-metal.h" - -#import "ggml-impl.h" -#import "ggml-backend-impl.h" -#import "ggml-metal-impl.h" - -#import - -#import - -#undef MIN -#undef MAX -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -// max memory buffers that can be mapped to the device -#define GGML_METAL_MAX_BUFFERS 64 - -// max number of MTLCommandBuffer used to submit a graph for processing -#define GGML_METAL_MAX_COMMAND_BUFFERS 8 - -#ifndef TARGET_OS_VISION -#define TARGET_OS_VISION 0 -#endif - -// create residency sets only on macOS >= 15.0 -#if !TARGET_CPU_X86_64 && TARGET_OS_OSX && __MAC_OS_X_VERSION_MAX_ALLOWED >= 150000 || \ - TARGET_OS_IOS && __IPHONE_OS_VERSION_MAX_ALLOWED >= 180000 || \ - TARGET_OS_TV && __TV_OS_VERSION_MAX_ALLOWED >= 180000 || \ - TARGET_OS_VISION && __VISION_OS_VERSION_MAX_ALLOWED >= 200000 -#define GGML_METAL_HAS_RESIDENCY_SETS 1 -#endif - -// globals - -// overload of MTLGPUFamilyMetal3 (not available in some environments) -static const NSInteger MTLGPUFamilyMetal3_GGML = 5001; - -// initialized in ggml_backend_metal_reg -static struct ggml_backend_reg g_ggml_backend_metal_reg; -static struct ggml_backend_device g_ggml_backend_metal_device; - -// information about a Metal device -// note: assumes single GPU device - the default one -// TODO: support multiple GPU devices -static struct ggml_backend_metal_device_context { - id mtl_device; - int mtl_device_ref_count; - id mtl_library; - - NSLock * mtl_lock; - - bool has_simdgroup_reduction; - bool has_simdgroup_mm; - bool has_residency_sets; - bool has_bfloat; - bool use_bfloat; - - size_t max_size; - - char name[128]; -} g_ggml_ctx_dev_main = { - /*.mtl_device =*/ nil, - /*.mtl_device_ref_count =*/ 0, - /*.mtl_library =*/ nil, - /*.mtl_lock =*/ nil, - /*.has_simdgroup_reduction =*/ false, - /*.has_simdgroup_mm =*/ false, - /*.has_residency_sets =*/ false, - /*.has_bfloat =*/ false, - /*.use_bfloat =*/ false, - /*.max_size =*/ 0, - /*.name =*/ "", -}; - -// acquire -static id ggml_backend_metal_device_acq(struct ggml_backend_metal_device_context * ctx) { - assert(ctx != NULL); - - if (ctx->mtl_lock == nil) { - ctx->mtl_lock = [[NSLock alloc] init]; - } - - if (ctx->mtl_device == nil) { - ctx->mtl_device = MTLCreateSystemDefaultDevice(); - } - - if (ctx->mtl_device) { - ctx->has_simdgroup_reduction = [ctx->mtl_device supportsFamily:MTLGPUFamilyApple7]; - ctx->has_simdgroup_reduction |= [ctx->mtl_device supportsFamily:MTLGPUFamilyMetal3_GGML]; - - ctx->has_simdgroup_mm = [ctx->mtl_device supportsFamily:MTLGPUFamilyApple7]; - -#if defined(GGML_METAL_HAS_RESIDENCY_SETS) - ctx->has_residency_sets = getenv("GGML_METAL_NO_RESIDENCY") == NULL; -#endif - - ctx->has_bfloat = [ctx->mtl_device supportsFamily:MTLGPUFamilyMetal3_GGML]; - ctx->has_bfloat |= [ctx->mtl_device supportsFamily:MTLGPUFamilyApple6]; - -#if defined(GGML_METAL_USE_BF16) - ctx->use_bfloat = ctx->has_bfloat; -#else - ctx->use_bfloat = false; -#endif - - ctx->max_size = ctx->mtl_device.maxBufferLength; - - strncpy(ctx->name, [[ctx->mtl_device name] UTF8String], sizeof(ctx->name) - 1); - } - - ctx->mtl_device_ref_count++; - - return ctx->mtl_device; -} - -// release -static void ggml_backend_metal_device_rel(struct ggml_backend_metal_device_context * ctx) { - assert(ctx != NULL); - assert(ctx->mtl_device_ref_count > 0); - - ctx->mtl_device_ref_count--; - - if (ctx->mtl_device_ref_count == 0) { - if (ctx->mtl_lock) { - [ctx->mtl_lock release]; - ctx->mtl_lock = nil; - } - - if (ctx->mtl_library) { - [ctx->mtl_library release]; - ctx->mtl_library = nil; - } - - if (ctx->mtl_device) { - [ctx->mtl_device release]; - ctx->mtl_device = nil; - } - } -} - -// kernels - -struct ggml_metal_kernel { - id pipeline; -}; - -enum ggml_metal_kernel_type { - GGML_METAL_KERNEL_TYPE_ADD, - GGML_METAL_KERNEL_TYPE_ADD_ROW, - GGML_METAL_KERNEL_TYPE_SUB, - GGML_METAL_KERNEL_TYPE_SUB_ROW, - GGML_METAL_KERNEL_TYPE_MUL, - GGML_METAL_KERNEL_TYPE_MUL_ROW, - GGML_METAL_KERNEL_TYPE_DIV, - GGML_METAL_KERNEL_TYPE_DIV_ROW, - GGML_METAL_KERNEL_TYPE_REPEAT_F32, - GGML_METAL_KERNEL_TYPE_REPEAT_F16, - GGML_METAL_KERNEL_TYPE_REPEAT_I32, - GGML_METAL_KERNEL_TYPE_REPEAT_I16, - GGML_METAL_KERNEL_TYPE_SCALE, - GGML_METAL_KERNEL_TYPE_SCALE_4, - GGML_METAL_KERNEL_TYPE_CLAMP, - GGML_METAL_KERNEL_TYPE_TANH, - GGML_METAL_KERNEL_TYPE_RELU, - GGML_METAL_KERNEL_TYPE_SIGMOID, - GGML_METAL_KERNEL_TYPE_GELU, - GGML_METAL_KERNEL_TYPE_GELU_4, - GGML_METAL_KERNEL_TYPE_GELU_ERF, - GGML_METAL_KERNEL_TYPE_GELU_ERF_4, - GGML_METAL_KERNEL_TYPE_GELU_QUICK, - GGML_METAL_KERNEL_TYPE_GELU_QUICK_4, - GGML_METAL_KERNEL_TYPE_SILU, - GGML_METAL_KERNEL_TYPE_SILU_4, - GGML_METAL_KERNEL_TYPE_ELU, - GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16, - GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16_4, - GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32, - GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32_4, - GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF, - GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF_8, - GGML_METAL_KERNEL_TYPE_GET_ROWS_F32, - GGML_METAL_KERNEL_TYPE_GET_ROWS_F16, - GGML_METAL_KERNEL_TYPE_GET_ROWS_BF16, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_0, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_1, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_K, - GGML_METAL_KERNEL_TYPE_GET_ROWS_Q6_K, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_S, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_M, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL, - GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_XS, - GGML_METAL_KERNEL_TYPE_GET_ROWS_I32, - GGML_METAL_KERNEL_TYPE_SET_ROWS_F32, - GGML_METAL_KERNEL_TYPE_SET_ROWS_F16, - GGML_METAL_KERNEL_TYPE_SET_ROWS_BF16, - GGML_METAL_KERNEL_TYPE_SET_ROWS_Q8_0, - GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_0, - GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_1, - GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_0, - GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_1, - GGML_METAL_KERNEL_TYPE_SET_ROWS_IQ4_NL, - GGML_METAL_KERNEL_TYPE_RMS_NORM, - GGML_METAL_KERNEL_TYPE_L2_NORM, - GGML_METAL_KERNEL_TYPE_GROUP_NORM, - GGML_METAL_KERNEL_TYPE_NORM, - GGML_METAL_KERNEL_TYPE_SSM_CONV_F32, - GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32, - GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32_GROUP, - GGML_METAL_KERNEL_TYPE_RWKV_WKV6_F32, - GGML_METAL_KERNEL_TYPE_RWKV_WKV7_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32_C4, - GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_C4, - GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_1ROW, - GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_L4, - GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F16, - GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_C4, - GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_1ROW, - GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_L4, - GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_BF16, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_2, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_3, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_4, - GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_5, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q2_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q3_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_Q6_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_M_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_NL_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F32_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32, - //GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32_1ROW, - //GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32_L4, - //GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F16, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_BF16_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q2_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q3_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q6_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_M_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_NL_F32, - GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_F32_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_F16_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_BF16_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_Q6_K_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_M_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_XS_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP0_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP1_F32, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F32_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F16_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_BF16_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_0_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_1_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_K_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q6_K_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_S_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_M_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F16, - GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_XS_F16, - GGML_METAL_KERNEL_TYPE_ROPE_NORM_F32, - GGML_METAL_KERNEL_TYPE_ROPE_NORM_F16, - GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F32, - GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F16, - GGML_METAL_KERNEL_TYPE_ROPE_VISION_F32, - GGML_METAL_KERNEL_TYPE_ROPE_VISION_F16, - GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F32, - GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F16, - GGML_METAL_KERNEL_TYPE_IM2COL_F16, - GGML_METAL_KERNEL_TYPE_IM2COL_F32, - GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F16, - GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F32, - GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F32_F32, - GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F16_F32, - GGML_METAL_KERNEL_TYPE_UPSCALE_F32, - GGML_METAL_KERNEL_TYPE_PAD_F32, - GGML_METAL_KERNEL_TYPE_PAD_REFLECT_1D_F32, - GGML_METAL_KERNEL_TYPE_ARANGE_F32, - GGML_METAL_KERNEL_TYPE_TIMESTEP_EMBEDDING_F32, - GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_ASC, - GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_DESC, - GGML_METAL_KERNEL_TYPE_LEAKY_RELU_F32, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H80, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H112, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H64, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H96, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H192, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK192_HV128, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H256, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK576_HV512, - GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK576_HV512, - GGML_METAL_KERNEL_TYPE_SET_I32, - GGML_METAL_KERNEL_TYPE_SET_F32, - GGML_METAL_KERNEL_TYPE_CPY_F32_F32, - GGML_METAL_KERNEL_TYPE_CPY_F32_F16, - GGML_METAL_KERNEL_TYPE_CPY_F32_BF16, - GGML_METAL_KERNEL_TYPE_CPY_F16_F16, - GGML_METAL_KERNEL_TYPE_CPY_F16_F32, - GGML_METAL_KERNEL_TYPE_CPY_BF16_F32, - GGML_METAL_KERNEL_TYPE_CPY_BF16_BF16, - GGML_METAL_KERNEL_TYPE_CPY_F32_Q8_0, - GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_0, - GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_1, - GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_0, - GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_1, - GGML_METAL_KERNEL_TYPE_CPY_F32_IQ4_NL, - GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F32, - GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F16, - GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F32, - GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F16, - GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F32, - GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F16, - GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F32, - GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F16, - GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F32, - GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F16, - GGML_METAL_KERNEL_TYPE_CONCAT, - GGML_METAL_KERNEL_TYPE_SQR, - GGML_METAL_KERNEL_TYPE_SQRT, - GGML_METAL_KERNEL_TYPE_SIN, - GGML_METAL_KERNEL_TYPE_COS, - GGML_METAL_KERNEL_TYPE_NEG, - GGML_METAL_KERNEL_TYPE_REGLU, - GGML_METAL_KERNEL_TYPE_GEGLU, - GGML_METAL_KERNEL_TYPE_SWIGLU, - GGML_METAL_KERNEL_TYPE_GEGLU_ERF, - GGML_METAL_KERNEL_TYPE_GEGLU_QUICK, - GGML_METAL_KERNEL_TYPE_SUM_ROWS, - GGML_METAL_KERNEL_TYPE_MEAN, - GGML_METAL_KERNEL_TYPE_POOL_2D_AVG_F32, - GGML_METAL_KERNEL_TYPE_POOL_2D_MAX_F32, - GGML_METAL_KERNEL_TYPE_ARGMAX, - - GGML_METAL_KERNEL_TYPE_COUNT -}; - -// -// ggml_metal_heap -// - -struct ggml_metal_heap { - // number of times the heap was unused - int n_unused; - - // total number of buffer allocations in this heap across all computes - int64_t n_alloc; - - // current offset in the heap - we reset this after each node in order to reuse the memory - size_t offs; - - // the currently allocated MTLBuffer objects in this heap - id obj; - - NSMutableArray * bufs; -}; - -static struct ggml_metal_heap * ggml_metal_heap_init(id device, size_t size) { - struct ggml_metal_heap * heap = calloc(1, sizeof(struct ggml_metal_heap)); - - MTLHeapDescriptor * desc = [[MTLHeapDescriptor alloc] init]; - desc.storageMode = MTLStorageModePrivate; - desc.cpuCacheMode = MTLCPUCacheModeDefaultCache; - desc.type = MTLHeapTypePlacement; - desc.size = size; - - heap->n_unused = 0; - heap->n_alloc = 0; - - heap->obj = [device newHeapWithDescriptor:desc]; - if (!heap->obj) { - GGML_LOG_ERROR("%s: error: failed to create MTLHeap with size %zu\n", __func__, size); - - free(heap); - - return false; - } - - [desc release]; - - heap->bufs = [[NSMutableArray alloc] init]; - - return heap; -} - -static void ggml_metal_heap_reset(struct ggml_metal_heap * heap) { - heap->offs = 0; - - // count how many graph computes the heap ended up being unused - if ([heap->bufs count] > 0) { - heap->n_unused = 0; - } else { - heap->n_unused++; - } - - for (id buf in heap->bufs) { - [buf release]; - } - [heap->bufs removeAllObjects]; - - // tell the OS that it can reuse this memory if needed - // ref: https://developer.apple.com/documentation/metal/mtlpurgeablestate?language=objc - [heap->obj setPurgeableState:MTLPurgeableStateVolatile]; -} - -static void ggml_metal_heap_free(struct ggml_metal_heap * heap) { - if (heap == nil) { - return; - } - - ggml_metal_heap_reset(heap); - - [heap->obj release]; - [heap->bufs release]; - - free(heap); -} - -@interface ggml_metal_heap_ptr : NSObject - -@property (nonatomic, assign) struct ggml_metal_heap * data; - -@end - -@implementation ggml_metal_heap_ptr -@end - -// -// ggml_metal_mem_pool -// - -struct ggml_metal_mem_pool { - id device; - - int n_heaps; // total number of heaps ever created (including those that were removed) - - NSMutableArray * heaps; - NSMutableArray * heaps_to_remove; -}; - -static struct ggml_metal_mem_pool * ggml_metal_mem_pool_init(void) { - struct ggml_metal_mem_pool * mem_pool = calloc(1, sizeof(struct ggml_metal_mem_pool)); - - mem_pool->n_heaps = 0; - - mem_pool->heaps = [[NSMutableArray alloc] init]; - mem_pool->heaps_to_remove = [[NSMutableArray alloc] init]; - - return mem_pool; -} - -static void ggml_metal_mem_pool_free(struct ggml_metal_mem_pool * mem_pool) { - GGML_LOG_DEBUG("%s: freeing memory pool, num heaps = %zu (total = %d)\n", __func__, [mem_pool->heaps count], mem_pool->n_heaps); - - size_t size_all = 0; - size_t size_cur = 0; - - for (ggml_metal_heap_ptr * ptr in mem_pool->heaps) { - GGML_LOG_DEBUG("%s: heap: %p\n", __func__, (void *) ptr.data); - GGML_LOG_DEBUG("%s: n_alloc: %" PRId64 "\n", __func__, ptr.data->n_alloc); - GGML_LOG_DEBUG("%s: n_unused: %d\n", __func__, ptr.data->n_unused); - GGML_LOG_DEBUG("%s: size: %.2f MiB\n", __func__, [ptr.data->obj size] / 1024.0 / 1024.0); - GGML_LOG_DEBUG("%s: bufs: %zu\n", __func__, [ptr.data->bufs count]); - - if ([ptr.data->bufs count] > 0) { - size_cur += [ptr.data->obj size]; - } - size_all += [ptr.data->obj size]; - - ggml_metal_heap_free(ptr.data); - [ptr release]; - } - [mem_pool->heaps release]; - [mem_pool->heaps_to_remove release]; - - if (size_all > 0) { - GGML_LOG_DEBUG("%s: size_all: %.2f MiB\n", __func__, size_all / 1024.0 / 1024.0); - GGML_LOG_DEBUG("%s: size_cur: %.2f MiB\n", __func__, size_cur / 1024.0 / 1024.0); - } - - free(mem_pool); -} - -static void ggml_metal_mem_pool_reset(struct ggml_metal_mem_pool * mem_pool) { - for (NSUInteger i = 0; i < [mem_pool->heaps count]; i++) { - ggml_metal_heap_ptr * ptr = [mem_pool->heaps objectAtIndex:i]; - - struct ggml_metal_heap * heap = ptr.data; - ggml_metal_heap_reset(heap); - - // if the heap hasn't been used for a while, remove it - if (heap->n_unused >= 128) { - [mem_pool->heaps_to_remove addObject:@(i)]; - } - } - - if (mem_pool->heaps_to_remove.count > 0) { - // remove in reverse order - for (NSUInteger i = [mem_pool->heaps_to_remove count] - 1; ; --i) { - NSUInteger index = [[mem_pool->heaps_to_remove objectAtIndex:i] intValue]; - ggml_metal_heap_ptr * ptr = [mem_pool->heaps objectAtIndex:index]; - - struct ggml_metal_heap * heap = ptr.data; - ggml_metal_heap_free(heap); - - [mem_pool->heaps removeObjectAtIndex:index]; - [ptr release]; - - if (i == 0) { - break; - } - } - - [mem_pool->heaps_to_remove removeAllObjects]; - } -} - -static void ggml_metal_mem_pool_clear(struct ggml_metal_mem_pool * mem_pool) { - for (ggml_metal_heap_ptr * ptr in mem_pool->heaps) { - ptr.data->offs = 0; - } -} - -static id ggml_metal_mem_pool_alloc(struct ggml_metal_mem_pool * mem_pool, size_t size) { - const size_t alignment = 256; - - const size_t size_aligned = GGML_PAD(size, alignment); - - // try one of the existing heaps - for (ggml_metal_heap_ptr * ptr in mem_pool->heaps) { - struct ggml_metal_heap * heap = ptr.data; - if (heap->offs + size_aligned <= [heap->obj size]) { - // if this is the first buffer in the heap for the current command buffer, tell the OS that - // it cannot free the memory used by the heap - // ref: https://developer.apple.com/documentation/metal/mtlpurgeablestate?language=objc - if ([heap->bufs count] == 0) { - [heap->obj setPurgeableState:MTLPurgeableStateNonVolatile]; - } - - id buf = [heap->obj newBufferWithLength:size_aligned options:MTLResourceStorageModePrivate offset:heap->offs]; - if (buf == nil) { - GGML_LOG_ERROR("%s: error: failed to create MTLBuffer with size %zu\n", __func__, size_aligned); - return nil; - } - - heap->n_alloc++; - heap->offs += size_aligned; - - [heap->bufs addObject:buf]; - - return buf; - } - } - - // create a new heap that can fit this buffer - ggml_metal_heap_ptr * heap_ptr = [ggml_metal_heap_ptr new]; - - struct ggml_metal_heap * heap = ggml_metal_heap_init(mem_pool->device, size_aligned); - if (heap == NULL) { - GGML_LOG_ERROR("%s: error: failed to create heap of size %zu\n", __func__, size_aligned); - return NULL; - } - - //GGML_LOG_DEBUG("%s: creating new heap of size %zu, got %zu\n", __func__, size_aligned, [heap->obj size]); - - heap_ptr.data = heap; - ggml_metal_heap_reset(heap); - - [heap->obj setPurgeableState:MTLPurgeableStateNonVolatile]; - id buf = [heap->obj newBufferWithLength:size_aligned options:MTLResourceStorageModePrivate offset:heap->offs]; - if (buf == nil) { - GGML_LOG_ERROR("%s: error: failed to create MTLBuffer with size %zu\n", __func__, size_aligned); - return NULL; - } - - heap->n_alloc++; - heap->offs += size_aligned; - - [heap->bufs addObject:buf]; - - [mem_pool->heaps addObject:heap_ptr]; - mem_pool->n_heaps++; - - return buf; -} - -struct ggml_metal_command_buffer { - id obj; - - // each command buffer has a memory pool from which it can allocate temporary buffers during the compute - struct ggml_metal_mem_pool * mem_pool; -}; - -struct ggml_backend_metal_context { - id device; - id queue; - - dispatch_queue_t d_queue; - - struct ggml_metal_kernel kernels[GGML_METAL_KERNEL_TYPE_COUNT]; - - // capture state - bool capture_next_compute; - bool capture_started; - - id capture_scope; - - // command buffer state - int n_cb; // number of extra threads used to submit the command buffers - int n_nodes_0; // number of nodes submitted by the main thread - int n_nodes_1; // remaining number of nodes submitted by the n_cb threads - int n_nodes_per_cb; - - struct ggml_cgraph * gf; - - // the callback given to the thread pool - void (^encode_async)(size_t ith); - - // n_cb command buffers + 1 used by the main thread - struct ggml_metal_command_buffer cmd_bufs[GGML_METAL_MAX_COMMAND_BUFFERS + 1]; - - // abort ggml_metal_graph_compute if callback returns true - ggml_abort_callback abort_callback; - void * abort_callback_data; -}; - -// MSL code -// TODO: move the contents here when ready -// for now it is easier to work in a separate file -// static NSString * const msl_library_source = @"see metal.metal"; - -#if !GGML_METAL_EMBED_LIBRARY -// Here to assist with NSBundle Path Hack -@interface GGMLMetalClass : NSObject -@end -@implementation GGMLMetalClass -@end -#endif - -static void * ggml_metal_host_malloc(size_t n) { - void * data = NULL; - -#if TARGET_OS_OSX - kern_return_t err = vm_allocate((vm_map_t) mach_task_self(), (void *) &data, n, VM_FLAGS_ANYWHERE); - if (err != KERN_SUCCESS) { - GGML_LOG_ERROR("%s: error: vm_allocate failed\n", __func__); - return NULL; - } -#else - const int result = posix_memalign((void **) &data, sysconf(_SC_PAGESIZE), n); - if (result != 0) { - GGML_LOG_ERROR("%s: error: posix_memalign failed\n", __func__); - return NULL; - } -#endif - - return data; -} - -// load library -// -// - first check if the library is embedded -// - then check if the library is in the bundle -// - if not found, load the source and compile it -// - if that fails, return NULL -static id ggml_metal_load_library(id device, bool use_bfloat) { - id metal_library = nil; - NSError * error = nil; - NSString * src = nil; - -#if GGML_METAL_EMBED_LIBRARY - GGML_LOG_INFO("%s: using embedded metal library\n", __func__); - - extern const char ggml_metallib_start[]; - extern const char ggml_metallib_end[]; - - src = [[NSString alloc] initWithBytes:ggml_metallib_start length:(ggml_metallib_end-ggml_metallib_start) encoding:NSUTF8StringEncoding]; - -#else - -#ifdef SWIFT_PACKAGE - NSBundle * bundle = SWIFTPM_MODULE_BUNDLE; -#else - NSBundle * bundle = [NSBundle bundleForClass:[GGMLMetalClass class]]; -#endif - - NSString * path_lib = [bundle pathForResource:@"default" ofType:@"metallib"]; - if (path_lib == nil) { - // Try to find the resource in the directory where the current binary located. - NSString * current_binary = [[NSProcessInfo processInfo] arguments][0]; - NSString * bin_dir = [current_binary stringByDeletingLastPathComponent]; - NSString * default_metallib_path = [NSString pathWithComponents:@[bin_dir, @"default.metallib"]]; - if ([[NSFileManager defaultManager] isReadableFileAtPath:default_metallib_path]) { - GGML_LOG_INFO("%s: found '%s'\n", __func__, [default_metallib_path UTF8String]); - NSDictionary * atts = [[NSFileManager defaultManager] attributesOfItemAtPath:default_metallib_path error:&error]; - if (atts && atts[NSFileType] == NSFileTypeSymbolicLink) { - // Optionally, if this is a symlink, try to resolve it. - default_metallib_path = [[NSFileManager defaultManager] destinationOfSymbolicLinkAtPath:default_metallib_path error:&error]; - if (default_metallib_path && [default_metallib_path length] > 0 && ![[default_metallib_path substringToIndex:1] isEqualToString:@"/"]) { - // It is a relative path, adding the binary directory as directory prefix. - default_metallib_path = [NSString pathWithComponents:@[bin_dir, default_metallib_path]]; - } - if (!default_metallib_path || ![[NSFileManager defaultManager] isReadableFileAtPath:default_metallib_path]) { - // Link to the resource could not be resolved. - default_metallib_path = nil; - } else { - GGML_LOG_INFO("%s: symlink resolved '%s'\n", __func__, [default_metallib_path UTF8String]); - } - } - } else { - // The resource couldn't be found in the binary's directory. - default_metallib_path = nil; - } - path_lib = default_metallib_path; - } - - if (path_lib != nil) { - // pre-compiled library found - NSURL * libURL = [NSURL fileURLWithPath:path_lib]; - GGML_LOG_INFO("%s: loading '%s'\n", __func__, [path_lib UTF8String]); - - metal_library = [device newLibraryWithURL:libURL error:&error]; - if (error) { - GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); - return NULL; - } - } else { - GGML_LOG_INFO("%s: default.metallib not found, loading from source\n", __func__); - - NSString * path_source; - NSString * path_resource = [[NSProcessInfo processInfo].environment objectForKey:@"GGML_METAL_PATH_RESOURCES"]; - - GGML_LOG_INFO("%s: GGML_METAL_PATH_RESOURCES = %s\n", __func__, path_resource ? [path_resource UTF8String] : "nil"); - - if (path_resource) { - path_source = [path_resource stringByAppendingPathComponent:@"ggml-metal.metal"]; - } else { - path_source = [bundle pathForResource:@"ggml-metal" ofType:@"metal"]; - } - - if (path_source == nil) { - GGML_LOG_WARN("%s: error: could not use bundle path to find ggml-metal.metal, falling back to trying cwd\n", __func__); - path_source = @"ggml-metal.metal"; - } - - GGML_LOG_INFO("%s: loading '%s'\n", __func__, [path_source UTF8String]); - - src = [NSString stringWithContentsOfFile:path_source encoding:NSUTF8StringEncoding error:&error]; - if (error) { - GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); - return NULL; - } - } -#endif - - if (!metal_library) { - @autoreleasepool { - // dictionary of preprocessor macros - NSMutableDictionary * prep = [NSMutableDictionary dictionary]; - - if (use_bfloat) { - [prep setObject:@"1" forKey:@"GGML_METAL_USE_BF16"]; - } - -#if GGML_METAL_EMBED_LIBRARY - [prep setObject:@"1" forKey:@"GGML_METAL_EMBED_LIBRARY"]; -#endif - - MTLCompileOptions * options = [MTLCompileOptions new]; - options.preprocessorMacros = prep; - - //[options setFastMathEnabled:false]; - - metal_library = [device newLibraryWithSource:src options:options error:&error]; - if (error) { - GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); - return NULL; - } - -#if !__has_feature(objc_arc) - [options release]; -#endif - } - } - -#if GGML_METAL_EMBED_LIBRARY - [src release]; -#endif // GGML_METAL_EMBED_LIBRARY - - return metal_library; -} - -static struct ggml_backend_metal_context * ggml_metal_init(ggml_backend_dev_t dev) { - GGML_LOG_INFO("%s: allocating\n", __func__); - -#if TARGET_OS_OSX && !GGML_METAL_NDEBUG - // Show all the Metal device instances in the system - NSArray * devices = MTLCopyAllDevices(); - for (id device in devices) { - GGML_LOG_INFO("%s: found device: %s\n", __func__, [[device name] UTF8String]); - } - [devices release]; // since it was created by a *Copy* C method -#endif - - // init context - struct ggml_backend_metal_context * ctx = calloc(1, sizeof(struct ggml_backend_metal_context)); - struct ggml_backend_metal_device_context * ctx_dev = dev->context; - - id device = ctx_dev->mtl_device; - - GGML_LOG_INFO("%s: picking default device: %s\n", __func__, [[device name] UTF8String]); - - ctx->device = device; - ctx->queue = [device newCommandQueue]; - if (ctx->queue == nil) { - GGML_LOG_ERROR("%s: error: failed to create command queue\n", __func__); - return NULL; - } - - ctx->d_queue = dispatch_queue_create("ggml-metal", DISPATCH_QUEUE_CONCURRENT); - - // load library - { - [ctx_dev->mtl_lock lock]; - - if (ctx_dev->mtl_library == nil) { - ctx_dev->mtl_library = ggml_metal_load_library(device, ctx_dev->use_bfloat); - } - - [ctx_dev->mtl_lock unlock]; - } - - id metal_library = ctx_dev->mtl_library; - if (metal_library == nil) { - GGML_LOG_ERROR("%s: error: metal library is nil\n", __func__); - return NULL; - } - - // print MTL GPU family: - GGML_LOG_INFO("%s: GPU name: %s\n", __func__, [[device name] UTF8String]); - - // determine max supported GPU family - // https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf - // https://developer.apple.com/metal/Metal-Feature-Set-Tables.pdf - { - for (int i = MTLGPUFamilyApple1 + 20; i >= MTLGPUFamilyApple1; --i) { - if ([device supportsFamily:i]) { - GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyApple%d (%d)\n", __func__, i - (int) MTLGPUFamilyApple1 + 1, i); - break; - } - } - - for (int i = MTLGPUFamilyCommon1 + 5; i >= MTLGPUFamilyCommon1; --i) { - if ([device supportsFamily:i]) { - GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyCommon%d (%d)\n", __func__, i - (int) MTLGPUFamilyCommon1 + 1, i); - break; - } - } - - for (int i = MTLGPUFamilyMetal3_GGML + 5; i >= MTLGPUFamilyMetal3_GGML; --i) { - if ([device supportsFamily:i]) { - GGML_LOG_INFO("%s: GPU family: MTLGPUFamilyMetal%d (%d)\n", __func__, i - (int) MTLGPUFamilyMetal3_GGML + 3, i); - break; - } - } - } - - GGML_LOG_INFO("%s: simdgroup reduction = %s\n", __func__, ctx_dev->has_simdgroup_reduction ? "true" : "false"); - GGML_LOG_INFO("%s: simdgroup matrix mul. = %s\n", __func__, ctx_dev->has_simdgroup_mm ? "true" : "false"); - GGML_LOG_INFO("%s: has residency sets = %s\n", __func__, ctx_dev->has_residency_sets ? "true" : "false"); - GGML_LOG_INFO("%s: has bfloat = %s\n", __func__, ctx_dev->has_bfloat ? "true" : "false"); - GGML_LOG_INFO("%s: use bfloat = %s\n", __func__, ctx_dev->use_bfloat ? "true" : "false"); - GGML_LOG_INFO("%s: hasUnifiedMemory = %s\n", __func__, ctx_dev->mtl_device.hasUnifiedMemory ? "true" : "false"); - - ctx->capture_next_compute = false; - ctx->capture_started = false; - ctx->capture_scope = nil; - - ctx->gf = nil; - ctx->encode_async = nil; - for (int i = 0; i < GGML_METAL_MAX_COMMAND_BUFFERS; ++i) { - ctx->cmd_bufs[i].obj = nil; - - ctx->cmd_bufs[i].mem_pool = ggml_metal_mem_pool_init(); - ctx->cmd_bufs[i].mem_pool->device = device; - } - -#if TARGET_OS_OSX || (TARGET_OS_IOS && __clang_major__ >= 15) - if (@available(macOS 10.12, iOS 16.0, *)) { - GGML_LOG_INFO("%s: recommendedMaxWorkingSetSize = %8.2f MB\n", __func__, device.recommendedMaxWorkingSetSize / 1e6); - } -#endif - - // load kernels - { - NSError * error = nil; - - for (int i = 0; i < GGML_METAL_KERNEL_TYPE_COUNT; ++i) { - ctx->kernels[i].pipeline = nil; - } - -#define GGML_METAL_ADD_KERNEL(e, name, supported) \ - if (supported) { \ - struct ggml_metal_kernel * kernel = &ctx->kernels[e]; \ - id metal_function = [metal_library newFunctionWithName:@"kernel_"#name]; \ - kernel->pipeline = [device newComputePipelineStateWithFunction:metal_function error:&error]; \ - GGML_LOG_DEBUG("%s: loaded %-40s %16p | th_max = %4d | th_width = %4d\n", __func__, "kernel_"#name, (void *) kernel->pipeline, \ - (int) kernel->pipeline.maxTotalThreadsPerThreadgroup, \ - (int) kernel->pipeline.threadExecutionWidth); \ - [metal_function release]; \ - if (error) { \ - GGML_LOG_ERROR("%s: error: load pipeline error: %s\n", __func__, [[error description] UTF8String]); \ - return NULL; \ - } \ - } else { \ - GGML_LOG_WARN("%s: skipping %-40s (not supported)\n", __func__, "kernel_"#name); \ - } - - const bool has_simdgroup_mm = ctx_dev->has_simdgroup_mm; - const bool has_simdgroup_reduction = ctx_dev->has_simdgroup_reduction; - const bool use_bfloat = ctx_dev->use_bfloat; - - // simd_sum and simd_max requires MTLGPUFamilyApple7 - - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ADD, add, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ADD_ROW, add_row, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SUB, sub, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SUB_ROW, sub_row, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL, mul, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_ROW, mul_row, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIV, div, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIV_ROW, div_row, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_F32, repeat_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_F16, repeat_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_I32, repeat_i32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REPEAT_I16, repeat_i16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SCALE, scale, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SCALE_4, scale_4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CLAMP, clamp, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_TANH, tanh, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_RELU, relu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SIGMOID, sigmoid, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU, gelu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU_4, gelu_4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU_ERF, gelu_erf, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU_ERF_4, gelu_erf_4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU_QUICK, gelu_quick, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GELU_QUICK_4, gelu_quick_4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SILU, silu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SILU_4, silu_4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ELU, elu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16, soft_max_f16, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16_4, soft_max_f16_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32, soft_max_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32_4, soft_max_f32_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF, diag_mask_inf, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF_8, diag_mask_inf_8, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_F32, get_rows_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_F16, get_rows_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_BF16, get_rows_bf16, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_0, get_rows_q4_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_1, get_rows_q4_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0, get_rows_q5_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1, get_rows_q5_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0, get_rows_q8_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K, get_rows_q2_K, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K, get_rows_q3_K, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K, get_rows_q4_K, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_K, get_rows_q5_K, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_Q6_K, get_rows_q6_K, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS, get_rows_iq2_xxs, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS, get_rows_iq2_xs, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS, get_rows_iq3_xxs, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S, get_rows_iq3_s, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_S, get_rows_iq2_s, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S, get_rows_iq1_s, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_M, get_rows_iq1_m, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL, get_rows_iq4_nl, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_XS, get_rows_iq4_xs, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GET_ROWS_I32, get_rows_i32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_F32, set_rows_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_F16, set_rows_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_BF16, set_rows_bf16, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_Q8_0, set_rows_q8_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_0, set_rows_q4_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_1, set_rows_q4_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_0, set_rows_q5_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_1, set_rows_q5_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_ROWS_IQ4_NL, set_rows_iq4_nl, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_RMS_NORM, rms_norm, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_L2_NORM, l2_norm, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GROUP_NORM, group_norm, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_NORM, norm, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SSM_CONV_F32, ssm_conv_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32, ssm_scan_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32_GROUP, ssm_scan_f32_group, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_RWKV_WKV6_F32, rwkv_wkv6_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_RWKV_WKV7_F32, rwkv_wkv7_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32, mul_mv_f32_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32_C4, mul_mv_f32_f32_c4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32, mul_mv_bf16_f32, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_C4, mul_mv_bf16_f32_c4, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_1ROW, mul_mv_bf16_f32_1row, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_L4, mul_mv_bf16_f32_l4, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_BF16, mul_mv_bf16_bf16, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32, mul_mv_f16_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_C4, mul_mv_f16_f32_c4, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_1ROW, mul_mv_f16_f32_1row, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_L4, mul_mv_f16_f32_l4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F16, mul_mv_f16_f16, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_0_F32, mul_mv_q4_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_1_F32, mul_mv_q4_1_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_0_F32, mul_mv_q5_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_1_F32, mul_mv_q5_1_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32, mul_mv_q8_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_2, mul_mv_ext_f16_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_3, mul_mv_ext_f16_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_4, mul_mv_ext_f16_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_5, mul_mv_ext_f16_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_2, mul_mv_ext_q4_0_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_3, mul_mv_ext_q4_0_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_4, mul_mv_ext_q4_0_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_5, mul_mv_ext_q4_0_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_2, mul_mv_ext_q4_1_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_3, mul_mv_ext_q4_1_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_4, mul_mv_ext_q4_1_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_5, mul_mv_ext_q4_1_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_2, mul_mv_ext_q5_0_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_3, mul_mv_ext_q5_0_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_4, mul_mv_ext_q5_0_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_5, mul_mv_ext_q5_0_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_2, mul_mv_ext_q5_1_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_3, mul_mv_ext_q5_1_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_4, mul_mv_ext_q5_1_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_5, mul_mv_ext_q5_1_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_2, mul_mv_ext_q8_0_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_3, mul_mv_ext_q8_0_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_4, mul_mv_ext_q8_0_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5, mul_mv_ext_q8_0_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2, mul_mv_ext_q4_K_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_3, mul_mv_ext_q4_K_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_4, mul_mv_ext_q4_K_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_5, mul_mv_ext_q4_K_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_2, mul_mv_ext_q5_K_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_3, mul_mv_ext_q5_K_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_4, mul_mv_ext_q5_K_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_5, mul_mv_ext_q5_K_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_2, mul_mv_ext_q6_K_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_3, mul_mv_ext_q6_K_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_4, mul_mv_ext_q6_K_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_5, mul_mv_ext_q6_K_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_2, mul_mv_ext_iq4_nl_f32_r1_2, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_3, mul_mv_ext_iq4_nl_f32_r1_3, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_4, mul_mv_ext_iq4_nl_f32_r1_4, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_5, mul_mv_ext_iq4_nl_f32_r1_5, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q2_K_F32, mul_mv_q2_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q3_K_F32, mul_mv_q3_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_K_F32, mul_mv_q4_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_K_F32, mul_mv_q5_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_Q6_K_F32, mul_mv_q6_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XXS_F32, mul_mv_iq2_xxs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XS_F32, mul_mv_iq2_xs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32, mul_mv_iq3_xxs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32, mul_mv_iq3_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_S_F32, mul_mv_iq2_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_S_F32, mul_mv_iq1_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_M_F32, mul_mv_iq1_m_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_NL_F32, mul_mv_iq4_nl_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_XS_F32, mul_mv_iq4_xs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F32_F32, mul_mv_id_f32_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32, mul_mv_id_f16_f32, has_simdgroup_reduction); - //GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32_1ROW, mul_mv_id_f16_f32_1row, has_simdgroup_reduction); - //GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32_L4, mul_mv_id_f16_f32_l4, has_simdgroup_reduction); - //GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F16, mul_mv_id_f16_f16, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_BF16_F32, mul_mv_id_bf16_f32, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_0_F32, mul_mv_id_q4_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_1_F32, mul_mv_id_q4_1_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_0_F32, mul_mv_id_q5_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_1_F32, mul_mv_id_q5_1_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32, mul_mv_id_q8_0_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q2_K_F32, mul_mv_id_q2_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q3_K_F32, mul_mv_id_q3_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_K_F32, mul_mv_id_q4_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_K_F32, mul_mv_id_q5_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q6_K_F32, mul_mv_id_q6_K_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XXS_F32, mul_mv_id_iq2_xxs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XS_F32, mul_mv_id_iq2_xs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32, mul_mv_id_iq3_xxs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32, mul_mv_id_iq3_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_S_F32, mul_mv_id_iq2_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_S_F32, mul_mv_id_iq1_s_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_M_F32, mul_mv_id_iq1_m_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_NL_F32, mul_mv_id_iq4_nl_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_XS_F32, mul_mv_id_iq4_xs_f32, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_F32_F32, mul_mm_f32_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_F16_F32, mul_mm_f16_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_BF16_F32, mul_mm_bf16_f32, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_0_F32, mul_mm_q4_0_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_1_F32, mul_mm_q4_1_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32, mul_mm_q5_0_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32, mul_mm_q5_1_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32, mul_mm_q8_0_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32, mul_mm_q2_K_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32, mul_mm_q3_K_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32, mul_mm_q4_K_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_K_F32, mul_mm_q5_K_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_Q6_K_F32, mul_mm_q6_K_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32, mul_mm_iq2_xxs_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32, mul_mm_iq2_xs_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32, mul_mm_iq3_xxs_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32, mul_mm_iq3_s_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_S_F32, mul_mm_iq2_s_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32, mul_mm_iq1_s_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_M_F32, mul_mm_iq1_m_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32, mul_mm_iq4_nl_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_XS_F32, mul_mm_iq4_xs_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP0_F16, mul_mm_id_map0_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP1_F32, mul_mm_id_map1_f32, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F32_F16, mul_mm_id_f32_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F16_F16, mul_mm_id_f16_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_BF16_F16, mul_mm_id_bf16_f16, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_0_F16, mul_mm_id_q4_0_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_1_F16, mul_mm_id_q4_1_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16, mul_mm_id_q5_0_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16, mul_mm_id_q5_1_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16, mul_mm_id_q8_0_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16, mul_mm_id_q2_K_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16, mul_mm_id_q3_K_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16, mul_mm_id_q4_K_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_K_F16, mul_mm_id_q5_K_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q6_K_F16, mul_mm_id_q6_K_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F16, mul_mm_id_iq2_xxs_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F16, mul_mm_id_iq2_xs_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F16, mul_mm_id_iq3_xxs_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F16, mul_mm_id_iq3_s_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_S_F16, mul_mm_id_iq2_s_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F16, mul_mm_id_iq1_s_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_M_F16, mul_mm_id_iq1_m_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F16, mul_mm_id_iq4_nl_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_XS_F16, mul_mm_id_iq4_xs_f16, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_NORM_F32, rope_norm_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_NORM_F16, rope_norm_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F32, rope_multi_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F16, rope_multi_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_VISION_F32, rope_vision_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_VISION_F16, rope_vision_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F32, rope_neox_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F16, rope_neox_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_IM2COL_F16, im2col_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_IM2COL_F32, im2col_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F16, im2col_ext_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F32, im2col_ext_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F32_F32, conv_transpose_1d_f32_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F16_F32, conv_transpose_1d_f16_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_UPSCALE_F32, upscale_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_PAD_F32, pad_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_PAD_REFLECT_1D_F32, pad_reflect_1d_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_TIMESTEP_EMBEDDING_F32, timestep_embedding_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ARANGE_F32, arange_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_ASC, argsort_f32_i32_asc, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_DESC, argsort_f32_i32_desc, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_LEAKY_RELU_F32, leaky_relu_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H64, flash_attn_ext_f16_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H80, flash_attn_ext_f16_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H96, flash_attn_ext_f16_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H112, flash_attn_ext_f16_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H128, flash_attn_ext_f16_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H192, flash_attn_ext_f16_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK192_HV128, flash_attn_ext_f16_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H256, flash_attn_ext_f16_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK576_HV512, flash_attn_ext_f16_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H64, flash_attn_ext_bf16_h64, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H80, flash_attn_ext_bf16_h80, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H96, flash_attn_ext_bf16_h96, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H112, flash_attn_ext_bf16_h112, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H128, flash_attn_ext_bf16_h128, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H192, flash_attn_ext_bf16_h192, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK192_HV128, flash_attn_ext_bf16_hk192_hv128, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H256, flash_attn_ext_bf16_h256, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK576_HV512, flash_attn_ext_bf16_hk576_hv512, has_simdgroup_mm && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H64, flash_attn_ext_q4_0_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H80, flash_attn_ext_q4_0_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H96, flash_attn_ext_q4_0_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H112, flash_attn_ext_q4_0_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H128, flash_attn_ext_q4_0_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H192, flash_attn_ext_q4_0_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK192_HV128, flash_attn_ext_q4_0_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H256, flash_attn_ext_q4_0_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK576_HV512, flash_attn_ext_q4_0_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H64, flash_attn_ext_q4_1_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H80, flash_attn_ext_q4_1_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H96, flash_attn_ext_q4_1_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H112, flash_attn_ext_q4_1_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H128, flash_attn_ext_q4_1_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H192, flash_attn_ext_q4_1_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK192_HV128, flash_attn_ext_q4_1_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H256, flash_attn_ext_q4_1_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK576_HV512, flash_attn_ext_q4_1_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H64, flash_attn_ext_q5_0_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H80, flash_attn_ext_q5_0_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H96, flash_attn_ext_q5_0_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H112, flash_attn_ext_q5_0_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H128, flash_attn_ext_q5_0_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H192, flash_attn_ext_q5_0_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK192_HV128, flash_attn_ext_q5_0_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H256, flash_attn_ext_q5_0_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK576_HV512, flash_attn_ext_q5_0_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H64, flash_attn_ext_q5_1_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H80, flash_attn_ext_q5_1_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H96, flash_attn_ext_q5_1_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H112, flash_attn_ext_q5_1_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H128, flash_attn_ext_q5_1_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H192, flash_attn_ext_q5_1_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK192_HV128, flash_attn_ext_q5_1_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H256, flash_attn_ext_q5_1_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK576_HV512, flash_attn_ext_q5_1_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H64, flash_attn_ext_q8_0_h64, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H80, flash_attn_ext_q8_0_h80, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H96, flash_attn_ext_q8_0_h96, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H112, flash_attn_ext_q8_0_h112, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H128, flash_attn_ext_q8_0_h128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H192, flash_attn_ext_q8_0_h192, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK192_HV128, flash_attn_ext_q8_0_hk192_hv128, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H256, flash_attn_ext_q8_0_h256, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK576_HV512, flash_attn_ext_q8_0_hk576_hv512, has_simdgroup_mm); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H64, flash_attn_ext_vec_f16_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H64, flash_attn_ext_vec_bf16_h64, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H64, flash_attn_ext_vec_q4_0_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H64, flash_attn_ext_vec_q4_1_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H64, flash_attn_ext_vec_q5_0_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H64, flash_attn_ext_vec_q5_1_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H64, flash_attn_ext_vec_q8_0_h64, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H96, flash_attn_ext_vec_f16_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H96, flash_attn_ext_vec_bf16_h96, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H96, flash_attn_ext_vec_q4_0_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H96, flash_attn_ext_vec_q4_1_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H96, flash_attn_ext_vec_q5_0_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H96, flash_attn_ext_vec_q5_1_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H96, flash_attn_ext_vec_q8_0_h96, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H128, flash_attn_ext_vec_f16_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H128, flash_attn_ext_vec_bf16_h128, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H128, flash_attn_ext_vec_q4_0_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H128, flash_attn_ext_vec_q4_1_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H128, flash_attn_ext_vec_q5_0_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H128, flash_attn_ext_vec_q5_1_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H128, flash_attn_ext_vec_q8_0_h128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H192, flash_attn_ext_vec_f16_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H192, flash_attn_ext_vec_bf16_h192, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H192, flash_attn_ext_vec_q4_0_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H192, flash_attn_ext_vec_q4_1_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H192, flash_attn_ext_vec_q5_0_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H192, flash_attn_ext_vec_q5_1_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H192, flash_attn_ext_vec_q8_0_h192, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK192_HV128, flash_attn_ext_vec_f16_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK192_HV128, flash_attn_ext_vec_bf16_hk192_hv128, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK192_HV128, flash_attn_ext_vec_q4_0_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK192_HV128, flash_attn_ext_vec_q4_1_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK192_HV128, flash_attn_ext_vec_q5_0_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK192_HV128, flash_attn_ext_vec_q5_1_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK192_HV128, flash_attn_ext_vec_q8_0_hk192_hv128, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H256, flash_attn_ext_vec_f16_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H256, flash_attn_ext_vec_bf16_h256, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H256, flash_attn_ext_vec_q4_0_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H256, flash_attn_ext_vec_q4_1_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H256, flash_attn_ext_vec_q5_0_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H256, flash_attn_ext_vec_q5_1_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H256, flash_attn_ext_vec_q8_0_h256, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK576_HV512, flash_attn_ext_vec_f16_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK576_HV512, flash_attn_ext_vec_bf16_hk576_hv512, has_simdgroup_reduction && use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK576_HV512, flash_attn_ext_vec_q4_0_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK576_HV512, flash_attn_ext_vec_q4_1_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK576_HV512, flash_attn_ext_vec_q5_0_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK576_HV512, flash_attn_ext_vec_q5_1_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK576_HV512, flash_attn_ext_vec_q8_0_hk576_hv512, has_simdgroup_reduction); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_F32, set_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SET_I32, set_i32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_F32, cpy_f32_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_F16, cpy_f32_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_BF16, cpy_f32_bf16, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F16_F32, cpy_f16_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F16_F16, cpy_f16_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_BF16_F32, cpy_bf16_f32, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_BF16_BF16, cpy_bf16_bf16, use_bfloat); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_Q8_0, cpy_f32_q8_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_0, cpy_f32_q4_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_1, cpy_f32_q4_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_0, cpy_f32_q5_0, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_1, cpy_f32_q5_1, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_F32_IQ4_NL, cpy_f32_iq4_nl, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F32, cpy_q4_0_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F16, cpy_q4_0_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F32, cpy_q4_1_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F16, cpy_q4_1_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F32, cpy_q5_0_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F16, cpy_q5_0_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F32, cpy_q5_1_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F16, cpy_q5_1_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F32, cpy_q8_0_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F16, cpy_q8_0_f16, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_CONCAT, concat, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SQR, sqr, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SQRT, sqrt, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SIN, sin, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_COS, cos, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_NEG, neg, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_REGLU, reglu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU, geglu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SWIGLU, swiglu, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU_ERF, geglu_erf, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_GEGLU_QUICK, geglu_quick, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_SUM_ROWS, sum_rows, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_MEAN, mean, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_ARGMAX, argmax, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_POOL_2D_AVG_F32, pool_2d_avg_f32, true); - GGML_METAL_ADD_KERNEL(GGML_METAL_KERNEL_TYPE_POOL_2D_MAX_F32, pool_2d_max_f32, true); - } - - return ctx; -} - -static void ggml_metal_free(struct ggml_backend_metal_context * ctx) { - GGML_LOG_INFO("%s: deallocating\n", __func__); - - for (int i = 0; i < GGML_METAL_KERNEL_TYPE_COUNT; ++i) { - [ctx->kernels[i].pipeline release]; - } - - Block_release(ctx->encode_async); - - [ctx->queue release]; - - for (int i = 0; i < GGML_METAL_MAX_COMMAND_BUFFERS; ++i) { - // ctx->cmd_bufs[i].obj is auto released - - ggml_metal_mem_pool_free(ctx->cmd_bufs[i].mem_pool); - } - - dispatch_release(ctx->d_queue); - - free(ctx); -} - -// temporarily defined here for compatibility between ggml-backend and the old API - -struct ggml_backend_metal_buffer { - void * data; - size_t size; - - id metal; -}; - -struct ggml_backend_metal_buffer_context { - void * all_data; - size_t all_size; - bool owned; - - // multiple buffers are used only to avoid the maximum buffer size limitation when using mmap - int n_buffers; - struct ggml_backend_metal_buffer buffers[GGML_METAL_MAX_BUFFERS]; - - // optional MTLResidencySet - id rset; -}; - -// rset init -static bool ggml_backend_metal_buffer_rset_init( - struct ggml_backend_metal_buffer_context * ctx, - struct ggml_backend_metal_device_context * ctx_dev, - id device) { - ctx->rset = nil; - - if (!ctx_dev->has_residency_sets) { - return true; - } - -#if defined(GGML_METAL_HAS_RESIDENCY_SETS) - if (@available(macOS 15.0, iOS 18.0, tvOS 18.0, visionOS 2.0, *)) { - MTLResidencySetDescriptor * desc = [[MTLResidencySetDescriptor alloc] init]; - desc.label = @"ggml_backend_metal"; - desc.initialCapacity = ctx->n_buffers; - - NSError * error; - ctx->rset = [device newResidencySetWithDescriptor:desc error:&error]; - if (error) { - GGML_LOG_ERROR("%s: error: %s\n", __func__, [[error description] UTF8String]); - [desc release]; - return false; - } - - [desc release]; - - for (int i = 0; i < ctx->n_buffers; i++) { - [ctx->rset addAllocation:ctx->buffers[i].metal]; - } - - [ctx->rset commit]; - [ctx->rset requestResidency]; - - return true; - } -#else - GGML_UNUSED(ctx_dev); - GGML_UNUSED(device); -#endif - - return true; -} - -// rset free -static void ggml_backend_metal_buffer_rset_free(struct ggml_backend_metal_buffer_context * ctx) { -#if defined(GGML_METAL_HAS_RESIDENCY_SETS) - if (@available(macOS 15.0, iOS 18.0, tvOS 18.0, visionOS 2.0, *)) { - if (ctx->rset) { - [ctx->rset endResidency]; - [ctx->rset removeAllAllocations]; - [ctx->rset release]; - } - } -#else - GGML_UNUSED(ctx); -#endif -} - -// finds the Metal buffer that contains the tensor data on the GPU device -// the assumption is that there is 1-to-1 mapping between the host and device memory buffers, so we can find the -// Metal buffer based on the host memory pointer -// -static id ggml_metal_get_buffer(struct ggml_tensor * t, size_t * offs) { - //GGML_LOG_INFO("%s: data tensor '%16s', offs_data = %8ld, offs_eval = %8ld, offs_cach = %8ld\n", __func__, t->name, offs_data, offs_eval, offs_cach); - - const int64_t tsize = ggml_nbytes(t); - - ggml_backend_buffer_t buffer = t->view_src ? t->view_src->buffer : t->buffer; - - struct ggml_backend_metal_buffer_context * buf_ctx = (struct ggml_backend_metal_buffer_context *) buffer->context; - - // find the view that contains the tensor fully - for (int i = 0; i < buf_ctx->n_buffers; ++i) { - const int64_t ioffs = (int64_t) t->data - (int64_t) buf_ctx->buffers[i].data; - - //GGML_LOG_INFO("ioffs = %10ld, tsize = %10ld, sum = %10ld, buf_ctx->buffers[%d].size = %10ld\n", ioffs, tsize, ioffs + tsize, i, buf_ctx->buffers[i].size); - if (ioffs >= 0 && ioffs + tsize <= (int64_t) buf_ctx->buffers[i].size) { - *offs = (size_t) ioffs; - - //GGML_LOG_INFO("%s: tensor '%16s', offs = %8ld\n", __func__, t->name, *offs); - - return buf_ctx->buffers[i].metal; - } - } - - GGML_LOG_ERROR("%s: error: tensor '%s' buffer is nil\n", __func__, t->name); - - return nil; -} - -static bool ggml_metal_supports_op(const struct ggml_backend_metal_device_context * ctx_dev, const struct ggml_tensor * op) { - const bool has_simdgroup_mm = ctx_dev->has_simdgroup_mm; - const bool has_simdgroup_reduction = ctx_dev->has_simdgroup_reduction; - const bool use_bfloat = ctx_dev->use_bfloat; - - if (!use_bfloat) { - if (op->type == GGML_TYPE_BF16) { - return false; - } - - for (size_t i = 0, n = 3; i < n; ++i) { - if (op->src[i] != NULL && op->src[i]->type == GGML_TYPE_BF16) { - return false; - } - } - } - - switch (op->op) { - case GGML_OP_UNARY: - switch (ggml_get_unary_op(op)) { - case GGML_UNARY_OP_TANH: - case GGML_UNARY_OP_RELU: - case GGML_UNARY_OP_SIGMOID: - case GGML_UNARY_OP_GELU: - case GGML_UNARY_OP_GELU_ERF: - case GGML_UNARY_OP_GELU_QUICK: - case GGML_UNARY_OP_SILU: - case GGML_UNARY_OP_ELU: - case GGML_UNARY_OP_NEG: - return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; - default: - return false; - } - case GGML_OP_GLU: - switch (ggml_get_glu_op(op)) { - case GGML_GLU_OP_REGLU: - case GGML_GLU_OP_GEGLU: - case GGML_GLU_OP_SWIGLU: - case GGML_GLU_OP_GEGLU_ERF: - case GGML_GLU_OP_GEGLU_QUICK: - return ggml_is_contiguous_1(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; - default: - return false; - } - case GGML_OP_NONE: - case GGML_OP_RESHAPE: - case GGML_OP_VIEW: - case GGML_OP_TRANSPOSE: - case GGML_OP_PERMUTE: - case GGML_OP_CONCAT: - return true; - case GGML_OP_ADD: - case GGML_OP_SUB: - case GGML_OP_MUL: - case GGML_OP_DIV: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_ACC: - case GGML_OP_REPEAT: - case GGML_OP_SCALE: - case GGML_OP_CONV_TRANSPOSE_1D: - return true; - case GGML_OP_CLAMP: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_SQR: - case GGML_OP_SQRT: - case GGML_OP_SIN: - case GGML_OP_COS: - return ggml_is_contiguous(op->src[0]) && op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_LOG: - return false; // TODO: implement - case GGML_OP_SUM_ROWS: - case GGML_OP_MEAN: - case GGML_OP_SOFT_MAX: - case GGML_OP_GROUP_NORM: - return has_simdgroup_reduction && ggml_is_contiguous_rows(op->src[0]); - case GGML_OP_RMS_NORM: - case GGML_OP_L2_NORM: - return has_simdgroup_reduction && (op->ne[0] % 4 == 0 && ggml_is_contiguous_1(op->src[0])); - case GGML_OP_ARGMAX: - return true; - case GGML_OP_NORM: - return has_simdgroup_reduction && (op->ne[0] % 4 == 0 && ggml_is_contiguous_1(op->src[0])); - case GGML_OP_ROPE: - return true; - case GGML_OP_IM2COL: - return op->src[0]->type == GGML_TYPE_F16; - case GGML_OP_POOL_1D: - return false; - case GGML_OP_UPSCALE: - return op->src[0]->type == GGML_TYPE_F32 && op->op_params[0] == GGML_SCALE_MODE_NEAREST; - case GGML_OP_POOL_2D: - case GGML_OP_PAD: - case GGML_OP_PAD_REFLECT_1D: - case GGML_OP_TIMESTEP_EMBEDDING: - case GGML_OP_ARGSORT: - case GGML_OP_LEAKY_RELU: - return op->src[0]->type == GGML_TYPE_F32; - case GGML_OP_ARANGE: - return true; - case GGML_OP_FLASH_ATTN_EXT: - if (op->src[0]->ne[0] == 32) { - // head size == 32 (e.g. bert-bge-small) - // TODO: not sure if it is worth adding kernels for this size - return false; - } - if (op->src[0]->ne[0] == 576) { - // DeepSeek sizes - // TODO: disabled for now, until optmized - return false; - } - if (op->src[1]->type != op->src[2]->type) { - return false; - } - return has_simdgroup_mm; // TODO: over-restricted for vec-kernels - case GGML_OP_SSM_CONV: - case GGML_OP_SSM_SCAN: - case GGML_OP_RWKV_WKV6: - case GGML_OP_RWKV_WKV7: - return true; - case GGML_OP_MUL_MAT: - case GGML_OP_MUL_MAT_ID: - return has_simdgroup_reduction && - (op->src[0]->type != GGML_TYPE_F32 || op->src[1]->type == GGML_TYPE_F32); - case GGML_OP_CPY: - case GGML_OP_DUP: - case GGML_OP_CONT: - { - switch (op->src[0]->type) { - case GGML_TYPE_F32: - switch (op->type) { - case GGML_TYPE_F32: - case GGML_TYPE_F16: - case GGML_TYPE_BF16: - case GGML_TYPE_Q8_0: - case GGML_TYPE_Q4_0: - case GGML_TYPE_Q4_1: - case GGML_TYPE_Q5_0: - case GGML_TYPE_Q5_1: - case GGML_TYPE_IQ4_NL: - return true; - default: - return false; - } - case GGML_TYPE_F16: - switch (op->type) { - case GGML_TYPE_F32: - case GGML_TYPE_F16: - return true; - default: - return false; - } - case GGML_TYPE_BF16: - switch (op->type) { - case GGML_TYPE_F32: - case GGML_TYPE_BF16: - return true; - default: - return false; - } - case GGML_TYPE_Q4_0: - case GGML_TYPE_Q4_1: - case GGML_TYPE_Q5_0: - case GGML_TYPE_Q5_1: - case GGML_TYPE_Q8_0: - switch (op->type) { - case GGML_TYPE_F32: - case GGML_TYPE_F16: - return true; - default: - return false; - } - default: - return false; - }; - } - case GGML_OP_SET: - { - switch (op->src[0]->type) { - case GGML_TYPE_F32: - case GGML_TYPE_I32: - return true; - default: - return false; - }; - } - case GGML_OP_DIAG_MASK_INF: - case GGML_OP_GET_ROWS: - { - return op->ne[3] == 1; - } - case GGML_OP_SET_ROWS: - { - if (op->src[0]->type != GGML_TYPE_F32) { - return false; - } - - switch (op->type) { - case GGML_TYPE_F32: - case GGML_TYPE_F16: - case GGML_TYPE_BF16: - case GGML_TYPE_Q8_0: - case GGML_TYPE_Q4_0: - case GGML_TYPE_Q4_1: - case GGML_TYPE_Q5_0: - case GGML_TYPE_Q5_1: - case GGML_TYPE_IQ4_NL: - return true; - default: - return false; - }; - } - default: - return false; - } -} - -static bool ggml_metal_encode_node( - ggml_backend_t backend, - int idx, - id encoder, - struct ggml_metal_mem_pool * mem_pool) { - struct ggml_backend_metal_context * ctx = backend->context; - struct ggml_backend_metal_device_context * ctx_dev = backend->device->context; - - struct ggml_cgraph * gf = ctx->gf; - - struct ggml_tensor * node = ggml_graph_node(gf, idx); - - //GGML_LOG_INFO("%s: encoding node %3d, op = %8s\n", __func__, idx, ggml_op_name(node->op)); - - struct ggml_tensor * src0 = node->src[0]; - struct ggml_tensor * src1 = node->src[1]; - struct ggml_tensor * src2 = node->src[2]; - struct ggml_tensor * dst = node; - - if (ggml_is_empty(dst)) { - return true; - } - - switch (dst->op) { - case GGML_OP_NONE: - case GGML_OP_RESHAPE: - case GGML_OP_VIEW: - case GGML_OP_TRANSPOSE: - case GGML_OP_PERMUTE: - { - // noop -> next node - } return true; - default: - { - } break; - } - - if (!ggml_metal_supports_op(ctx_dev, dst)) { - GGML_LOG_ERROR("%s: error: unsupported op '%s'\n", __func__, ggml_op_desc(dst)); - GGML_ABORT("unsupported op"); - } - - ggml_metal_mem_pool_clear(mem_pool); - - const int64_t ne00 = src0 ? src0->ne[0] : 0; - const int64_t ne01 = src0 ? src0->ne[1] : 0; - const int64_t ne02 = src0 ? src0->ne[2] : 0; - const int64_t ne03 = src0 ? src0->ne[3] : 0; - - const uint64_t nb00 = src0 ? src0->nb[0] : 0; - const uint64_t nb01 = src0 ? src0->nb[1] : 0; - const uint64_t nb02 = src0 ? src0->nb[2] : 0; - const uint64_t nb03 = src0 ? src0->nb[3] : 0; - - const int64_t ne10 = src1 ? src1->ne[0] : 0; - const int64_t ne11 = src1 ? src1->ne[1] : 0; - const int64_t ne12 = src1 ? src1->ne[2] : 0; - const int64_t ne13 = src1 ? src1->ne[3] : 0; - - const uint64_t nb10 = src1 ? src1->nb[0] : 0; - const uint64_t nb11 = src1 ? src1->nb[1] : 0; - const uint64_t nb12 = src1 ? src1->nb[2] : 0; - const uint64_t nb13 = src1 ? src1->nb[3] : 0; - - const int64_t ne20 = src2 ? src2->ne[0] : 0; - const int64_t ne21 = src2 ? src2->ne[1] : 0; - const int64_t ne22 = src2 ? src2->ne[2] : 0; GGML_UNUSED(ne22); - const int64_t ne23 = src2 ? src2->ne[3] : 0; GGML_UNUSED(ne23); - - const uint64_t nb20 = src2 ? src2->nb[0] : 0; GGML_UNUSED(nb20); - const uint64_t nb21 = src2 ? src2->nb[1] : 0; - const uint64_t nb22 = src2 ? src2->nb[2] : 0; - const uint64_t nb23 = src2 ? src2->nb[3] : 0; GGML_UNUSED(nb23); - - const int64_t ne0 = dst ? dst->ne[0] : 0; - const int64_t ne1 = dst ? dst->ne[1] : 0; - const int64_t ne2 = dst ? dst->ne[2] : 0; - const int64_t ne3 = dst ? dst->ne[3] : 0; - - const uint64_t nb0 = dst ? dst->nb[0] : 0; - const uint64_t nb1 = dst ? dst->nb[1] : 0; - const uint64_t nb2 = dst ? dst->nb[2] : 0; - const uint64_t nb3 = dst ? dst->nb[3] : 0; - - const enum ggml_type src0t = src0 ? src0->type : GGML_TYPE_COUNT; - const enum ggml_type src1t = src1 ? src1->type : GGML_TYPE_COUNT; - const enum ggml_type dstt = dst ? dst->type : GGML_TYPE_COUNT; - - size_t offs_src0 = 0; - size_t offs_src1 = 0; - size_t offs_src2 = 0; - size_t offs_dst = 0; - - id id_src0 = src0 ? ggml_metal_get_buffer(src0, &offs_src0) : nil; - id id_src1 = src1 ? ggml_metal_get_buffer(src1, &offs_src1) : nil; - id id_src2 = src2 ? ggml_metal_get_buffer(src2, &offs_src2) : nil; - id id_dst = dst ? ggml_metal_get_buffer(dst, &offs_dst) : nil; - -#if 0 - GGML_LOG_INFO("%s: op - %s\n", __func__, ggml_op_name(dst->op)); - if (src0) { - GGML_LOG_INFO("%s: src0 - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], %d, %s\n", __func__, ggml_type_name(src0t), ne00, ne01, ne02, ne03, nb00, nb01, nb02, nb03, - ggml_is_contiguous(src0), src0->name); - } - if (src1) { - GGML_LOG_INFO("%s: src1 - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], %d, %s\n", __func__, ggml_type_name(src1t), ne10, ne11, ne12, ne13, nb10, nb11, nb12, nb13, - ggml_is_contiguous(src1), src1->name); - } - if (dst) { - GGML_LOG_INFO("%s: dst - %4s [%5lld, %5lld, %5lld, %5lld] [%5lld, %5lld, %5lld, %5lld], 1, %s\n", __func__, ggml_type_name(dstt), ne0, ne1, ne2, ne3, nb0, nb1, nb2, nb3, - dst->name); - } -#endif - - id device = ctx_dev->mtl_device; - - switch (dst->op) { - case GGML_OP_CONCAT: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CONCAT].pipeline; - - const int32_t dim = ((const int32_t *) dst->op_params)[0]; - - ggml_metal_kargs_concat args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.dim =*/ dim, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - const int nth = MIN(1024, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne1, ne2, ne3) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_ADD: - case GGML_OP_SUB: - case GGML_OP_MUL: - case GGML_OP_DIV: - { - GGML_ASSERT(src0t == GGML_TYPE_F32); - GGML_ASSERT(src1t == GGML_TYPE_F32); - - const size_t offs = 0; - - bool bcast_row = false; - - id pipeline = nil; - - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { - GGML_ASSERT(ggml_is_contiguous(src0)); - - // src1 is a row - GGML_ASSERT(ne11 == 1); - - switch (dst->op) { - case GGML_OP_ADD: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ADD_ROW].pipeline; break; - case GGML_OP_SUB: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SUB_ROW].pipeline; break; - case GGML_OP_MUL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_ROW].pipeline; break; - case GGML_OP_DIV: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_DIV_ROW].pipeline; break; - default: GGML_ABORT("fatal error"); - } - - bcast_row = true; - } else { - switch (dst->op) { - case GGML_OP_ADD: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ADD].pipeline; break; - case GGML_OP_SUB: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SUB].pipeline; break; - case GGML_OP_MUL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL].pipeline; break; - case GGML_OP_DIV: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_DIV].pipeline; break; - default: GGML_ABORT("fatal error"); - } - } - - ggml_metal_kargs_bin args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.offs =*/ offs, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - if (bcast_row) { - const int64_t n = ggml_nelements(dst)/4; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } else { - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } - } break; - case GGML_OP_REPEAT: - { - id pipeline; - - switch (src0t) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_REPEAT_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_REPEAT_F16].pipeline; break; - case GGML_TYPE_I32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_REPEAT_I32].pipeline; break; - case GGML_TYPE_I16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_REPEAT_I16].pipeline; break; - default: GGML_ABORT("fatal error"); - } - - ggml_metal_kargs_repeat args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne1, ne2, ne3) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_ACC: - { - GGML_ASSERT(src0t == GGML_TYPE_F32); - GGML_ASSERT(src1t == GGML_TYPE_F32); - GGML_ASSERT(dstt == GGML_TYPE_F32); - - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(src1)); - - const size_t pnb1 = ((const int32_t *) dst->op_params)[0]; - const size_t pnb2 = ((const int32_t *) dst->op_params)[1]; - const size_t pnb3 = ((const int32_t *) dst->op_params)[2]; - const size_t offs = ((const int32_t *) dst->op_params)[3]; - - const bool inplace = (bool) ((const int32_t *) dst->op_params)[4]; - - if (!inplace) { - // run a separete kernel to cpy src->dst - // not sure how to avoid this - // TODO: make a simpler cpy_bytes kernel - - const id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_F32].pipeline; - - ggml_metal_kargs_cpy args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne00); - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } - - const id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ADD].pipeline; - - ggml_metal_kargs_bin args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ pnb1, - /*.nb02 =*/ pnb2, - /*.nb03 =*/ pnb3, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ pnb1, - /*.nb2 =*/ pnb2, - /*.nb3 =*/ pnb3, - /*.offs =*/ offs, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne00); - - [encoder dispatchThreadgroups:MTLSizeMake(ne11, ne12, ne13) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_SCALE: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - float scale; - float bias; - memcpy(&scale, ((const int32_t *) dst->op_params) + 0, sizeof(float)); - memcpy(&bias, ((const int32_t *) dst->op_params) + 1, sizeof(float)); - - int64_t n = ggml_nelements(dst); - - id pipeline = nil; - - if (n % 4 == 0) { - n /= 4; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SCALE_4].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SCALE].pipeline; - } - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&scale length:sizeof(scale) atIndex:2]; - [encoder setBytes:&bias length:sizeof(bias) atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_CLAMP: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CLAMP].pipeline; - - float min; - float max; - memcpy(&min, ((const int32_t *) dst->op_params) + 0, sizeof(float)); - memcpy(&max, ((const int32_t *) dst->op_params) + 1, sizeof(float)); - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&min length:sizeof(min) atIndex:2]; - [encoder setBytes:&max length:sizeof(max) atIndex:3]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_UNARY: - switch (ggml_get_unary_op(node)) { - // we are not taking into account the strides, so for now require contiguous tensors - GGML_ASSERT(ggml_is_contiguous(src0)); - - case GGML_UNARY_OP_TANH: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_TANH].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_RELU: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RELU].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_SIGMOID: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SIGMOID].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_GELU: - { - int64_t n = ggml_nelements(dst); - - id pipeline = nil; - - if (n % 4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU_4].pipeline; - n /= 4; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU].pipeline; - } - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_GELU_ERF: - { - int64_t n = ggml_nelements(dst); - - id pipeline = nil; - - if (n % 4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU_ERF_4].pipeline; - n /= 4; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU_ERF].pipeline; - } - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_GELU_QUICK: - { - int64_t n = ggml_nelements(dst); - - id pipeline = nil; - - if (n % 4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU_QUICK_4].pipeline; - n /= 4; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GELU_QUICK].pipeline; - } - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_SILU: - { - int64_t n = ggml_nelements(dst); - - id pipeline = nil; - - if (n % 4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SILU_4].pipeline; - n /= 4; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SILU].pipeline; - } - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_ELU: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ELU].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_UNARY_OP_NEG: - { - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_NEG].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - default: - { - GGML_LOG_WARN("%s: node %3d, op = %8s not implemented\n", __func__, idx, ggml_op_name(dst->op)); - GGML_ABORT("fatal error"); - } - } break; - case GGML_OP_GLU: - { - GGML_ASSERT(ggml_is_contiguous_1(src0)); - - if (src1) { - GGML_ASSERT(ggml_are_same_shape(src0, src1)); - } - - id pipeline = nil; - - switch (ggml_get_glu_op(node)) { - case GGML_GLU_OP_REGLU: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_REGLU].pipeline; - break; - case GGML_GLU_OP_GEGLU: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GEGLU].pipeline; - break; - case GGML_GLU_OP_SWIGLU: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SWIGLU].pipeline; - break; - case GGML_GLU_OP_GEGLU_ERF: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GEGLU_ERF].pipeline; - break; - case GGML_GLU_OP_GEGLU_QUICK: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GEGLU_QUICK].pipeline; - break; - default: - GGML_ABORT("fatal error"); - } - - const int32_t swp = ((const int32_t *) dst->op_params)[1]; - - const int32_t i00 = swp ? ne0 : 0; - const int32_t i10 = swp ? 0 : ne0; - - ggml_metal_kargs_glu args = { - /*.ne00 =*/ ne00, - /*.nb01 =*/ nb01, - /*.ne10 =*/ src1 ? ne10 : ne00, - /*.nb11 =*/ src1 ? nb11 : nb01, - /*.ne0 =*/ ne0, - /*.nb1 =*/ nb1, - /*.i00 =*/ src1 ? 0 : i00, - /*.i10 =*/ src1 ? 0 : i10, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - if (src1) { - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - } else { - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - } - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setBytes:&args length:sizeof(args) atIndex:3]; - - const int64_t nrows = ggml_nrows(src0); - - const int32_t nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne00/2); - - [encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_SQR: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SQR].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_SQRT: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SQRT].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_SIN: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SIN].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_COS: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_COS].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_SUM_ROWS: - case GGML_OP_MEAN: - { - GGML_ASSERT(src0->nb[0] == ggml_type_size(src0->type)); - - id pipeline = nil; - - switch (dst->op) { - case GGML_OP_SUM_ROWS: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SUM_ROWS].pipeline; - break; - case GGML_OP_MEAN: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MEAN].pipeline; - break; - default: - GGML_ABORT("fatal error"); - } - - int nth = 32; // SIMD width - - while (nth < ne00 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - nth = MIN(nth, (int) pipeline.maxTotalThreadsPerThreadgroup); - nth = MIN(nth, ne00); - - ggml_metal_kargs_sum_rows args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_SOFT_MAX: - { - GGML_ASSERT(!src1 || src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); - - int nth = 32; // SIMD width - - id pipeline = nil; - - const bool use_f16 = (src1 && src1->type == GGML_TYPE_F16); - - if (ne00%4 == 0) { - while (nth < ne00/4 && nth*ne01*ne02*ne03 < 256) { - nth *= 2; - } - if (use_f16) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16_4].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32_4].pipeline; - } - } else { - while (nth < ne00 && nth*ne01*ne02*ne03 < 256) { - nth *= 2; - } - if (use_f16) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SOFT_MAX_F16].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SOFT_MAX_F32].pipeline; - } - } - - float scale; - float max_bias; - - memcpy(&scale, ((const int32_t *) dst->op_params) + 0, sizeof(scale)); - memcpy(&max_bias, ((const int32_t *) dst->op_params) + 1, sizeof(max_bias)); - - const uint32_t n_head = src0->ne[2]; - const uint32_t n_head_log2 = 1u << (uint32_t) floorf(log2f((float) n_head)); - - const float m0 = powf(2.0f, -(max_bias ) / n_head_log2); - const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); - -// use this branch to test the ggml_metal_mem_pool functionality -#if 0 - // cpy to tmp buffer in MTLHeap - - id h_src0 = h_src0 = ggml_metal_mem_pool_alloc(mem_pool, ggml_nbytes(src0)); - if (!h_src0) { - GGML_LOG_ERROR("%s: failed to allocate buffer from memory pool, size = %zu\n", __func__, ggml_nbytes(src0)); - return false; - } - - offs_src0 = 0; - - ggml_metal_kargs_cpy args_cpy = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne00, - /*.ne1 =*/ ne01, - /*.ne2 =*/ ne02, - /*.ne3 =*/ ne03, - /*.nb0 =*/ nb00, - /*.nb1 =*/ nb01, - /*.nb2 =*/ nb02, - /*.nb3 =*/ nb03, - }; - - if (src0->type == GGML_TYPE_F16) { - [encoder setComputePipelineState:ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F16_F16].pipeline]; - } else { - [encoder setComputePipelineState:ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_F32].pipeline]; - } - [encoder setBytes:&args_cpy length:sizeof(args_cpy) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:h_src0 offset:0 atIndex:2]; - - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - int nth_cpy = MIN(1024, ne00 / ggml_blck_size(src0->type)); - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth_cpy, 1, 1)]; - -#else - id h_src0 = id_src0; -#endif - // softmax - - ggml_metal_kargs_soft_max args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.scale =*/ scale, - /*.max_bias =*/ max_bias, - /*.m0 =*/ m0, - /*.m1 =*/ m1, - /*.n_head_log2 =*/ n_head_log2, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:h_src0 offset:offs_src0 atIndex:0]; - if (id_src1) { - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - } else { - [encoder setBuffer:h_src0 offset:offs_src0 atIndex:1]; - } - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setBytes:&args length:sizeof(args) atIndex:3]; - - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_DIAG_MASK_INF: - { - const int n_past = ((const int32_t *)(dst->op_params))[0]; - - id pipeline = nil; - - if (ne00%8 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF_8].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_DIAG_MASK_INF].pipeline; - } - - ggml_metal_kargs_diag_mask_inf args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.n_past =*/ n_past, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - if (ne00%8 == 0) { - [encoder dispatchThreadgroups:MTLSizeMake(ne00*ne01*ne02/8, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } - else { - [encoder dispatchThreadgroups:MTLSizeMake(ne00, ne01, ne02) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } - } break; - case GGML_OP_SSM_CONV: - { - GGML_ASSERT(src0t == GGML_TYPE_F32); - GGML_ASSERT(src1t == GGML_TYPE_F32); - - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(src1)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SSM_CONV_F32].pipeline; - - ggml_metal_kargs_ssm_conv args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setBytes:&args length:sizeof(args) atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne1, ne02) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_SSM_SCAN: - { - struct ggml_tensor * src3 = node->src[3]; - struct ggml_tensor * src4 = node->src[4]; - struct ggml_tensor * src5 = node->src[5]; - struct ggml_tensor * src6 = node->src[6]; - - GGML_ASSERT(src3); - GGML_ASSERT(src4); - GGML_ASSERT(src5); - GGML_ASSERT(src6); - - size_t offs_src3 = 0; - size_t offs_src4 = 0; - size_t offs_src5 = 0; - size_t offs_src6 = 0; - - id id_src3 = src3 ? ggml_metal_get_buffer(src3, &offs_src3) : nil; - id id_src4 = src4 ? ggml_metal_get_buffer(src4, &offs_src4) : nil; - id id_src5 = src5 ? ggml_metal_get_buffer(src5, &offs_src5) : nil; - id id_src6 = src6 ? ggml_metal_get_buffer(src6, &offs_src6) : nil; - - const int64_t ne30 = src3->ne[0]; - const int64_t ne31 = src3->ne[1]; GGML_UNUSED(ne31); - - const uint64_t nb30 = src3->nb[0]; GGML_UNUSED(nb30); - const uint64_t nb31 = src3->nb[1]; - - const int64_t ne40 = src4->ne[0]; GGML_UNUSED(ne40); - const int64_t ne41 = src4->ne[1]; - const int64_t ne42 = src4->ne[2]; GGML_UNUSED(ne42); - const int64_t ne43 = src4->ne[3]; GGML_UNUSED(ne43); - - const uint64_t nb40 = src4->nb[0]; GGML_UNUSED(nb40); - const uint64_t nb41 = src4->nb[1]; - const uint64_t nb42 = src4->nb[2]; - const uint64_t nb43 = src4->nb[3]; - - const int64_t ne50 = src5->ne[0]; GGML_UNUSED(ne50); - const int64_t ne51 = src5->ne[1]; GGML_UNUSED(ne51); - const int64_t ne52 = src5->ne[2]; GGML_UNUSED(ne52); - const int64_t ne53 = src5->ne[3]; GGML_UNUSED(ne53); - - const uint64_t nb50 = src5->nb[0]; GGML_UNUSED(nb50); - const uint64_t nb51 = src5->nb[1]; - const uint64_t nb52 = src5->nb[2]; - const uint64_t nb53 = src5->nb[3]; - - const int64_t ne60 = src6->ne[0]; GGML_UNUSED(ne60); - - const uint64_t nb60 = src6->nb[0]; GGML_UNUSED(nb60); - - const int64_t d_state = ne00; - const int64_t d_inner = ne01; - const int64_t n_head = ne02; - const int64_t n_group = ne41; - const int64_t n_seq_tokens = ne12; - const int64_t n_seqs = ne13; - - id pipeline = nil; - - if (ne30 == 1) { - // Mamba-2 - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32_GROUP].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SSM_SCAN_F32].pipeline; - } - - ggml_metal_kargs_ssm_scan args = { - /*.d_state =*/ d_state, - /*.d_inner =*/ d_inner, - /*.n_head =*/ n_head, - /*.n_group =*/ n_group, - /*.n_seq_tokens =*/ n_seq_tokens, - /*.n_seqs =*/ n_seqs, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.nb21 =*/ nb21, - /*.nb22 =*/ nb22, - /*.nb31 =*/ nb31, - /*.nb41 =*/ nb41, - /*.nb42 =*/ nb42, - /*.nb43 =*/ nb43, - /*.nb51 =*/ nb51, - /*.nb52 =*/ nb52, - /*.nb53 =*/ nb53, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:2]; - [encoder setBuffer:id_src3 offset:offs_src3 atIndex:3]; - [encoder setBuffer:id_src4 offset:offs_src4 atIndex:4]; - [encoder setBuffer:id_src5 offset:offs_src5 atIndex:5]; - [encoder setBuffer:id_src6 offset:offs_src6 atIndex:6]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:7]; - [encoder setBytes:&args length:sizeof(args) atIndex:8]; - - if (ne30 == 1) { - // Mamba-2 - [encoder dispatchThreadgroups:MTLSizeMake(d_inner, n_head, n_seqs) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } else { - GGML_ASSERT(d_inner == 1); - [encoder dispatchThreadgroups:MTLSizeMake(n_head, n_seqs, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } - } break; - case GGML_OP_RWKV_WKV6: - { - const int64_t B = dst->src[5]->ne[1]; - const int64_t T = dst->src[0]->ne[2]; - const int64_t C = dst->ne[0]; - const int64_t H = dst->src[0]->ne[1]; - - GGML_ASSERT(dst->src[5]->type == GGML_TYPE_F32); - GGML_ASSERT(C % H == 0); - GGML_ASSERT(C / H == 64); - - size_t offs_src3 = 0; - size_t offs_src4 = 0; - size_t offs_src5 = 0; - - id id_src3 = dst->src[3] ? ggml_metal_get_buffer(dst->src[3], &offs_src3) : nil; - id id_src4 = dst->src[4] ? ggml_metal_get_buffer(dst->src[4], &offs_src4) : nil; - id id_src5 = dst->src[5] ? ggml_metal_get_buffer(dst->src[5], &offs_src5) : nil; - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RWKV_WKV6_F32].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:2]; - [encoder setBuffer:id_src3 offset:offs_src3 atIndex:3]; - [encoder setBuffer:id_src4 offset:offs_src4 atIndex:4]; - [encoder setBuffer:id_src5 offset:offs_src5 atIndex:5]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:6]; - - [encoder setBytes:&B length:sizeof(B) atIndex:7]; - [encoder setBytes:&T length:sizeof(T) atIndex:8]; - [encoder setBytes:&C length:sizeof(C) atIndex:9]; - [encoder setBytes:&H length:sizeof(H) atIndex:10]; - - [encoder dispatchThreadgroups:MTLSizeMake(B * H, 1, 1) threadsPerThreadgroup:MTLSizeMake(C/ H, 1, 1)]; - } break; - case GGML_OP_RWKV_WKV7: - { - const int64_t B = dst->src[6]->ne[1]; - const int64_t T = dst->src[0]->ne[2]; - const int64_t C = dst->ne[0]; - const int64_t H = dst->src[0]->ne[1]; - - GGML_ASSERT(dst->src[6]->type == GGML_TYPE_F32); - GGML_ASSERT(C % H == 0); - GGML_ASSERT(C / H == 64); - - size_t offs_src3 = 0; - size_t offs_src4 = 0; - size_t offs_src5 = 0; - size_t offs_src6 = 0; - - id id_src3 = dst->src[3] ? ggml_metal_get_buffer(dst->src[3], &offs_src3) : nil; - id id_src4 = dst->src[4] ? ggml_metal_get_buffer(dst->src[4], &offs_src4) : nil; - id id_src5 = dst->src[5] ? ggml_metal_get_buffer(dst->src[5], &offs_src5) : nil; - id id_src6 = dst->src[6] ? ggml_metal_get_buffer(dst->src[6], &offs_src6) : nil; - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RWKV_WKV7_F32].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:2]; - [encoder setBuffer:id_src3 offset:offs_src3 atIndex:3]; - [encoder setBuffer:id_src4 offset:offs_src4 atIndex:4]; - [encoder setBuffer:id_src5 offset:offs_src5 atIndex:5]; - [encoder setBuffer:id_src6 offset:offs_src6 atIndex:6]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:7]; - - [encoder setBytes:&B length:sizeof(B) atIndex:8]; - [encoder setBytes:&T length:sizeof(T) atIndex:9]; - [encoder setBytes:&C length:sizeof(C) atIndex:10]; - [encoder setBytes:&H length:sizeof(H) atIndex:11]; - - [encoder dispatchThreadgroups:MTLSizeMake(B * H, 1, 1) threadsPerThreadgroup:MTLSizeMake(C/ H, 1, 1)]; - } break; - case GGML_OP_MUL_MAT: - { - GGML_ASSERT(ne00 == ne10); - - GGML_ASSERT(ne12 % ne02 == 0); - GGML_ASSERT(ne13 % ne03 == 0); - - const uint32_t r2 = ne12/ne02; - const uint32_t r3 = ne13/ne03; - - // find the break-even point where the matrix-matrix kernel becomes more efficient compared - // to the matrix-vector kernel - const int ne11_mm_min = 4; - - // first try to use small-batch mat-mv kernels - // these should be efficient for BS [2, ~8] - if (src1t == GGML_TYPE_F32 && (ne00%256 == 0) && - ( - ( - ( - src0t == GGML_TYPE_F16 || // TODO: helper function - src0t == GGML_TYPE_Q4_0 || - src0t == GGML_TYPE_Q4_1 || - src0t == GGML_TYPE_Q5_0 || - src0t == GGML_TYPE_Q5_1 || - src0t == GGML_TYPE_Q8_0 || - src0t == GGML_TYPE_IQ4_NL || - false) && (ne11 >= 2 && ne11 <= 8) - ) || - ( - ( - src0t == GGML_TYPE_Q4_K || - src0t == GGML_TYPE_Q5_K || - src0t == GGML_TYPE_Q6_K || - false) && (ne11 >= 4 && ne11 <= 8) - ) - ) - ) { - // TODO: determine the optimal parameters based on grid utilization - // I still don't know why we should not always use the maximum available threads: - // - // nsg = pipeline.maxTotalThreadsPerThreadgroup / 32 - // - // my current hypothesis is that the work grid is not evenly divisible for different nsg - // values and there can be some tail effects when nsg is high. need to confirm this - // - const int nsg = 2; // num simdgroups per threadgroup - const int nxpsg = ne11 < 3 ? 16 : 8; // num threads along row per simdgroup - const int nypsg = 32/nxpsg; // num threads along col per simdgroup (i.e. a simdgroup processes that many src0 rows at a time) - const int r0ptg = nypsg*nsg; // num src0 rows per threadgroup - int r1ptg = 4; // num src1 rows per threadgroup - - // note: not sure how optimal are those across all different hardware. there might be someting cleverer - switch (ne11) { - case 2: - r1ptg = 2; break; - case 3: - case 6: - r1ptg = 3; break; - case 4: - case 7: - case 8: - r1ptg = 4; break; - case 5: - r1ptg = 5; break; - }; - - id pipeline = nil; - - switch (src0->type) { - case GGML_TYPE_F16: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_F16_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q4_0: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_0_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q4_1: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_1_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q5_0: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_0_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q5_1: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_1_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q8_0: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q8_0_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q4_K: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q4_K_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q5_K: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q5_K_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_Q6_K: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_Q6_K_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - case GGML_TYPE_IQ4_NL: - switch (r1ptg) { - case 2: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_2].pipeline; break; - case 3: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_3].pipeline; break; - case 4: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_4].pipeline; break; - case 5: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_EXT_IQ4_NL_F32_R1_5].pipeline; break; - default: GGML_ABORT("not implemented"); - } break; - default: GGML_ABORT("not implemented"); - } - - ggml_metal_kargs_mul_mv_ext args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - /*.nsg =*/ nsg, - /*.nxpsg =*/ nxpsg, - /*.r1ptg =*/ r1ptg, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - //printf("ne01 = %lld nr0ptg = %d\n", ne01, nr0ptg); - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + r0ptg - 1)/r0ptg, (ne11 + r1ptg - 1)/r1ptg, ne12*ne13) threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)]; - } else - // for now the matrix-matrix multiplication kernel only works on A14+/M1+ SoCs - // AMD GPU and older A-chips will reuse matrix-vector multiplication kernel - if ([device supportsFamily:MTLGPUFamilyApple7] && - !ggml_is_transposed(src0) && - !ggml_is_transposed(src1) && - src1t == GGML_TYPE_F32 && - ne00 % 32 == 0 && ne00 >= 64 && - (ne11 > ne11_mm_min || (ggml_is_quantized(src0t) && ne12 > 1))) { - //printf("matrix: ne00 = %6d, ne01 = %6d, ne02 = %6d, ne11 = %6d, ne12 = %6d\n", ne00, ne01, ne02, ne11, ne12); - - // some Metal matrix data types require aligned pointers - // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (Table 2.5) - switch (src0->type) { - case GGML_TYPE_F32: GGML_ASSERT(nb01 % 16 == 0); break; - case GGML_TYPE_F16: GGML_ASSERT(nb01 % 8 == 0); break; - case GGML_TYPE_BF16: GGML_ASSERT(nb01 % 8 == 0); break; - default: break; - } - - id pipeline = nil; - - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_F32_F32 ].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_F16_F32 ].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_BF16_F32 ].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_0_F32 ].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_1_F32 ].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_0_F32 ].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_1_F32 ].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q8_0_F32 ].pipeline; break; - case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q2_K_F32 ].pipeline; break; - case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q3_K_F32 ].pipeline; break; - case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q4_K_F32 ].pipeline; break; - case GGML_TYPE_Q5_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q5_K_F32 ].pipeline; break; - case GGML_TYPE_Q6_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_Q6_K_F32 ].pipeline; break; - case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XXS_F32].pipeline; break; - case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_XS_F32 ].pipeline; break; - case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_XXS_F32].pipeline; break; - case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ3_S_F32 ].pipeline; break; - case GGML_TYPE_IQ2_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ2_S_F32 ].pipeline; break; - case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_S_F32 ].pipeline; break; - case GGML_TYPE_IQ1_M: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ1_M_F32 ].pipeline; break; - case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_NL_F32 ].pipeline; break; - case GGML_TYPE_IQ4_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_IQ4_XS_F32 ].pipeline; break; - default: GGML_ABORT("MUL MAT-MAT not implemented"); - } - - ggml_metal_kargs_mul_mm args = { - /*.ne00 =*/ ne00, - /*.ne02 =*/ ne02, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - [encoder setThreadgroupMemoryLength:8192 atIndex:0]; - [encoder dispatchThreadgroups:MTLSizeMake((ne11 + 31)/32, (ne01 + 63)/64, ne12*ne13) threadsPerThreadgroup:MTLSizeMake(128, 1, 1)]; - } else { - id pipeline = nil; - - int nsg = 0; // number of simdgroups - int nr0 = 0; // number of src0 rows per simdgroup - int nr1 = 1; // number of src1 rows per threadgroup - - size_t smem = 0; // shared memory - - // use custom matrix x vector kernel - switch (src0t) { - case GGML_TYPE_F32: - { - GGML_ASSERT(src1t == GGML_TYPE_F32); - nsg = 1; - nr0 = 1; - nr1 = 4; - if (ne00 == 4) { - nr0 = 32; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32_C4].pipeline; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F32_F32].pipeline; - } - } break; - case GGML_TYPE_F16: - { - nsg = 1; - nr0 = 1; - if (src1t == GGML_TYPE_F32) { - if (ne00 == 4) { - nr0 = 32; - nr1 = 4; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_C4].pipeline; - } else if (ne11 * ne12 < 4) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_1ROW].pipeline; - } else if (ne00 >= 128 && ne01 >= 8 && ne00%4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32_L4].pipeline; - nr1 = ne11; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F32].pipeline; - nr1 = 4; - } - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_F16_F16].pipeline; - nr1 = 4; - } - } break; - case GGML_TYPE_BF16: - { - nsg = 1; - nr0 = 1; - if (src1t == GGML_TYPE_F32) { - if (ne00 == 4) { - nr0 = 32; - nr1 = 4; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_C4].pipeline; - } else if (ne11 * ne12 < 4) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_1ROW].pipeline; - } else if (ne00 >= 128 && ne01 >= 8 && ne00%4 == 0) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32_L4].pipeline; - nr1 = ne11; - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_F32].pipeline; - nr1 = 4; - } - } else { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_BF16_BF16].pipeline; - nr1 = 4; - } - } break; - case GGML_TYPE_Q4_0: - { - nsg = N_SG_Q4_0; - nr0 = N_R0_Q4_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_0_F32].pipeline; - } break; - case GGML_TYPE_Q4_1: - { - nsg = N_SG_Q4_1; - nr0 = N_R0_Q4_1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_1_F32].pipeline; - } break; - case GGML_TYPE_Q5_0: - { - nsg = N_SG_Q5_0; - nr0 = N_R0_Q5_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_0_F32].pipeline; - } break; - case GGML_TYPE_Q5_1: - { - nsg = N_SG_Q5_1; - nr0 = N_R0_Q5_1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_1_F32].pipeline; - } break; - case GGML_TYPE_Q8_0: - { - nsg = N_SG_Q8_0; - nr0 = N_R0_Q8_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q8_0_F32].pipeline; - } break; - case GGML_TYPE_Q2_K: - { - nsg = N_SG_Q2_K; - nr0 = N_R0_Q2_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q2_K_F32].pipeline; - } break; - case GGML_TYPE_Q3_K: - { - nsg = N_SG_Q3_K; - nr0 = N_R0_Q3_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q3_K_F32].pipeline; - } break; - case GGML_TYPE_Q4_K: - { - nsg = N_SG_Q4_K; - nr0 = N_R0_Q4_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q4_K_F32].pipeline; - } break; - case GGML_TYPE_Q5_K: - { - nsg = N_SG_Q5_K; - nr0 = N_R0_Q5_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q5_K_F32].pipeline; - } break; - case GGML_TYPE_Q6_K: - { - nsg = N_SG_Q6_K; - nr0 = N_R0_Q6_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_Q6_K_F32].pipeline; - } break; - case GGML_TYPE_IQ2_XXS: - { - nsg = N_SG_IQ2_XXS; - nr0 = N_R0_IQ2_XXS; - smem = 256*8+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XXS_F32].pipeline; - } break; - case GGML_TYPE_IQ2_XS: - { - nsg = N_SG_IQ2_XS; - nr0 = N_R0_IQ2_XS; - smem = 512*8+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_XS_F32].pipeline; - } break; - case GGML_TYPE_IQ3_XXS: - { - nsg = N_SG_IQ3_XXS; - nr0 = N_R0_IQ3_XXS; - smem = 256*4+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_XXS_F32].pipeline; - } break; - case GGML_TYPE_IQ3_S: - { - nsg = N_SG_IQ3_S; - nr0 = N_R0_IQ3_S; - smem = 512*4; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ3_S_F32].pipeline; - } break; - case GGML_TYPE_IQ2_S: - { - nsg = N_SG_IQ2_S; - nr0 = N_R0_IQ2_S; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ2_S_F32].pipeline; - } break; - case GGML_TYPE_IQ1_S: - { - nsg = N_SG_IQ1_S; - nr0 = N_R0_IQ1_S; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_S_F32].pipeline; - } break; - case GGML_TYPE_IQ1_M: - { - nsg = N_SG_IQ1_M; - nr0 = N_R0_IQ1_M; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ1_M_F32].pipeline; - } break; - case GGML_TYPE_IQ4_NL: - { - nsg = N_SG_IQ4_NL; - nr0 = N_R0_IQ4_NL; - smem = 32*sizeof(float); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_NL_F32].pipeline; - } break; - case GGML_TYPE_IQ4_XS: - { - nsg = N_SG_IQ4_XS; - nr0 = N_R0_IQ4_XS; - smem = 32*sizeof(float); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_IQ4_XS_F32].pipeline; - } break; - default: - { - GGML_LOG_ERROR("Asserting on type %d\n", (int)src0t); - GGML_ABORT("not implemented"); - } - }; - - ggml_metal_kargs_mul_mv args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - if (smem > 0) { - [encoder setThreadgroupMemoryLength:smem atIndex:0]; - } - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nr0*nsg - 1)/(nr0*nsg), (ne11 + nr1 - 1)/nr1, ne12*ne13) threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)]; - } - } break; - case GGML_OP_MUL_MAT_ID: - { - // src2 = ids - const enum ggml_type src2t = src2->type; GGML_UNUSED(src2t); - - GGML_ASSERT(src2t == GGML_TYPE_I32); - - GGML_ASSERT(!ggml_is_transposed(src0)); - GGML_ASSERT(!ggml_is_transposed(src1)); - - GGML_ASSERT(src1t == GGML_TYPE_F32); - - GGML_ASSERT(ne03 == 1); - GGML_ASSERT(ne13 == 1); - - const uint32_t r2 = 1; - const uint32_t r3 = 1; - - // find the break-even point where the matrix-matrix kernel becomes more efficient compared - // to the matrix-vector kernel - // ne20 = n_used_experts - // ne21 = n_rows (batch size) - const int ne21_mm_id_min = 32; - - // for now the matrix-matrix multiplication kernel only works on A14+/M1+ SoCs - // AMD GPU and older A-chips will reuse matrix-vector multiplication kernel - if ([device supportsFamily:MTLGPUFamilyApple7] && - ne00 % 32 == 0 && ne00 >= 64 && - (ne21 >= ne21_mm_id_min)) { - GGML_ASSERT(ne00 % 4 == 0); - - // some Metal matrix data types require aligned pointers - // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (Table 2.5) - switch (src0->type) { - case GGML_TYPE_F32: GGML_ASSERT(nb01 % 16 == 0); break; - case GGML_TYPE_F16: GGML_ASSERT(nb01 % 8 == 0); break; - case GGML_TYPE_BF16: GGML_ASSERT(nb01 % 8 == 0); break; - default: break; - } - - const int64_t neh10 = ne10; // n_embd - const int64_t neh11 = ne21; // n_tokens - const int64_t neh12 = ne02; // n_expert - - const uint64_t nbh10 = ggml_type_size(GGML_TYPE_F16); - const uint64_t nbh11 = nbh10*neh10; - const uint64_t nbh12 = nbh11*neh11; - const uint64_t nbh13 = nbh12*neh12; - - const size_t s_src1 = ggml_type_size(GGML_TYPE_F16)*neh10*neh11*neh12; - id h_src1 = ggml_metal_mem_pool_alloc(mem_pool, s_src1); - if (!h_src1) { - GGML_LOG_ERROR("%s: failed to allocate buffer from memory pool, size = %zu\n", __func__, s_src1); - return false; - } - - const int64_t neh0 = ne0; - const int64_t neh1 = ne21; - const int64_t neh2 = ne02; - - const uint64_t nbh0 = ggml_type_size(GGML_TYPE_F32); - const uint64_t nbh1 = nbh0*neh0; - const uint64_t nbh2 = nbh1*neh1; - //const uint64_t nbh3 = nbh2*neh2; - - const size_t s_dst = ggml_type_size(GGML_TYPE_F32)*neh0*neh1*neh2; - id h_dst = ggml_metal_mem_pool_alloc(mem_pool, s_dst); - if (!h_dst) { - GGML_LOG_ERROR("%s: failed to allocate buffer from memory pool, size = %zu\n", __func__, s_dst); - return false; - } - - // tokens per expert - const size_t s_tpe = ggml_type_size(GGML_TYPE_I32)*ne02; - id h_tpe = ggml_metal_mem_pool_alloc(mem_pool, s_tpe); - if (!h_tpe) { - GGML_LOG_ERROR("%s: failed to allocate buffer from memory pool, size = %zu\n", __func__, s_tpe); - return false; - } - - // id map - // [n_expert_used, n_tokens] - const size_t s_ids = ggml_type_size(GGML_TYPE_I32)*ne20*ne21; - id h_ids = ggml_metal_mem_pool_alloc(mem_pool, s_ids); - if (!h_ids) { - GGML_LOG_ERROR("%s: failed to allocate buffer from memory pool, size = %zu\n", __func__, s_ids); - return false; - } - - { - const int nth = MIN(1024, ne10/4); - - ggml_metal_kargs_mul_mm_id_map0 args = { - ne10, - ne11, // n_expert_used (bcast) - nb11, - nb12, - neh11, // n_tokens - nbh11, - ne20, // n_expert_used - nb21, - }; - - id pipeline = nil; - - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP0_F16].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:2]; - [encoder setBuffer: h_src1 offset:0 atIndex:3]; - [encoder setBuffer: h_tpe offset:0 atIndex:4]; - [encoder setBuffer: h_ids offset:0 atIndex:5]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne02, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } - - { - id pipeline = nil; - - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F32_F16 ].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_F16_F16 ].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_BF16_F16 ].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_0_F16 ].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_1_F16 ].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_0_F16 ].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_1_F16 ].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q8_0_F16 ].pipeline; break; - case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q2_K_F16 ].pipeline; break; - case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q3_K_F16 ].pipeline; break; - case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q4_K_F16 ].pipeline; break; - case GGML_TYPE_Q5_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q5_K_F16 ].pipeline; break; - case GGML_TYPE_Q6_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_Q6_K_F16 ].pipeline; break; - case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XXS_F16].pipeline; break; - case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_XS_F16 ].pipeline; break; - case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_XXS_F16].pipeline; break; - case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ3_S_F16 ].pipeline; break; - case GGML_TYPE_IQ2_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ2_S_F16 ].pipeline; break; - case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_S_F16 ].pipeline; break; - case GGML_TYPE_IQ1_M: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ1_M_F16 ].pipeline; break; - case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_NL_F16 ].pipeline; break; - case GGML_TYPE_IQ4_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_IQ4_XS_F16 ].pipeline; break; - default: GGML_ABORT("MUL_MAT_ID not implemented"); - } - - ggml_metal_kargs_mul_mm_id args = { - /*.ne00 =*/ ne00, - /*.ne02 =*/ ne02, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.neh12 =*/ neh12, - /*.nbh10 =*/ nbh10, - /*.nbh11 =*/ nbh11, - /*.nbh12 =*/ nbh12, - /*.nbh13 =*/ nbh13, - /*.neh0 =*/ neh0, - /*.neh1 =*/ neh1, - /*.r2 =*/ r2, - /*.r3 =*/ r3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer: h_src1 offset:0 atIndex:2]; - [encoder setBuffer: h_tpe offset:0 atIndex:3]; - [encoder setBuffer: h_dst offset:0 atIndex:4]; - - [encoder setThreadgroupMemoryLength:8192 atIndex:0]; - [encoder dispatchThreadgroups:MTLSizeMake((ne21 + 31)/32, (ne01 + 63)/64, ne02) threadsPerThreadgroup:MTLSizeMake(128, 1, 1)]; - } - - { - GGML_ASSERT(ne0 % 4 == 0); - - const int nth = MIN(1024, ne0/4); - - ggml_metal_kargs_mul_mm_id_map1 args = { - ne20, // n_expert_used - neh0, - neh1, - nbh1, - nbh2, - ne0, - nb1, - nb2, - }; - - id pipeline = nil; - - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MM_ID_MAP1_F32].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer: h_dst offset:0 atIndex:1]; - [encoder setBuffer: h_ids offset:0 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne20, ne21, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } - } else { - id pipeline = nil; - - int nsg = 0; // number of simdgroups - int nr0 = 0; // number of src0 rows per simdgroup - int nr1 = 1; // number of src1 rows per threadgroup - - size_t smem = 0; // shared memory - - // use custom matrix x vector kernel - switch (src0t) { - case GGML_TYPE_F32: - { - GGML_ASSERT(src1t == GGML_TYPE_F32); - nsg = 1; - nr0 = 1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F32_F32].pipeline; - } break; - case GGML_TYPE_F16: - { - GGML_ASSERT(src1t == GGML_TYPE_F32); - nsg = 1; - nr0 = 1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_F16_F32].pipeline; - } break; - case GGML_TYPE_BF16: - { - GGML_ASSERT(src1t == GGML_TYPE_F32); - nsg = 1; - nr0 = 1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_BF16_F32].pipeline; - } break; - case GGML_TYPE_Q4_0: - { - nsg = N_SG_Q4_0; - nr0 = N_R0_Q4_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_0_F32].pipeline; - } break; - case GGML_TYPE_Q4_1: - { - nsg = N_SG_Q4_1; - nr0 = N_R0_Q4_1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_1_F32].pipeline; - } break; - case GGML_TYPE_Q5_0: - { - nsg = N_SG_Q5_0; - nr0 = N_R0_Q5_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_0_F32].pipeline; - } break; - case GGML_TYPE_Q5_1: - { - nsg = N_SG_Q5_1; - nr0 = N_R0_Q5_1; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_1_F32].pipeline; - } break; - case GGML_TYPE_Q8_0: - { - nsg = N_SG_Q8_0; - nr0 = N_R0_Q8_0; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q8_0_F32].pipeline; - } break; - case GGML_TYPE_Q2_K: - { - nsg = N_SG_Q2_K; - nr0 = N_R0_Q2_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q2_K_F32].pipeline; - } break; - case GGML_TYPE_Q3_K: - { - nsg = N_SG_Q3_K; - nr0 = N_R0_Q3_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q3_K_F32].pipeline; - } break; - case GGML_TYPE_Q4_K: - { - nsg = N_SG_Q4_K; - nr0 = N_R0_Q4_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q4_K_F32].pipeline; - } break; - case GGML_TYPE_Q5_K: - { - nsg = N_SG_Q5_K; - nr0 = N_R0_Q5_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q5_K_F32].pipeline; - } break; - case GGML_TYPE_Q6_K: - { - nsg = N_SG_Q6_K; - nr0 = N_R0_Q6_K; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_Q6_K_F32].pipeline; - } break; - case GGML_TYPE_IQ2_XXS: - { - nsg = N_SG_IQ2_XXS; - nr0 = N_R0_IQ2_XXS; - smem = 256*8+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XXS_F32].pipeline; - } break; - case GGML_TYPE_IQ2_XS: - { - nsg = N_SG_IQ2_XS; - nr0 = N_R0_IQ2_XS; - smem = 512*8+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_XS_F32].pipeline; - } break; - case GGML_TYPE_IQ3_XXS: - { - nsg = N_SG_IQ3_XXS; - nr0 = N_R0_IQ3_XXS; - smem = 256*4+128; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_XXS_F32].pipeline; - } break; - case GGML_TYPE_IQ3_S: - { - nsg = N_SG_IQ3_S; - nr0 = N_R0_IQ3_S; - smem = 512*4; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ3_S_F32].pipeline; - } break; - case GGML_TYPE_IQ2_S: - { - nsg = N_SG_IQ2_S; - nr0 = N_R0_IQ2_S; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ2_S_F32].pipeline; - } break; - case GGML_TYPE_IQ1_S: - { - nsg = N_SG_IQ1_S; - nr0 = N_R0_IQ1_S; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_S_F32].pipeline; - } break; - case GGML_TYPE_IQ1_M: - { - nsg = N_SG_IQ1_M; - nr0 = N_R0_IQ1_M; - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ1_M_F32].pipeline; - } break; - case GGML_TYPE_IQ4_NL: - { - nsg = N_SG_IQ4_NL; - nr0 = N_R0_IQ4_NL; - smem = 32*sizeof(float); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_NL_F32].pipeline; - } break; - case GGML_TYPE_IQ4_XS: - { - nsg = N_SG_IQ4_XS; - nr0 = N_R0_IQ4_XS; - smem = 32*sizeof(float); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_MUL_MV_ID_IQ4_XS_F32].pipeline; - } break; - default: - { - GGML_LOG_ERROR("Asserting on type %d\n", (int)src2t); - GGML_ABORT("not implemented"); - } - }; - - if (ggml_is_quantized(src0t)) { - GGML_ASSERT(ne00 >= nsg*nr0); - } - - ggml_metal_kargs_mul_mv_id args = { - /*.nei0 =*/ ne20, - /*.nei1 =*/ ne21, - /*.nbi1 =*/ nb21, - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.ne13 =*/ ne13, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.nb1 =*/ nb1, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:4]; - - const int64_t _ne1 = 1; - const int64_t ne123 = ne20*ne21; - - if (smem > 0) { - [encoder setThreadgroupMemoryLength:smem atIndex:0]; - } - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nr0*nsg - 1)/(nr0*nsg), (_ne1 + nr1 - 1)/nr1, ne123) threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)]; - } - } break; - case GGML_OP_GET_ROWS: - { - id pipeline = nil; - - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_F32 ].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_F16 ].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_BF16 ].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_0 ].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_1 ].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_0 ].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_1 ].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q8_0 ].pipeline; break; - case GGML_TYPE_Q2_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q2_K ].pipeline; break; - case GGML_TYPE_Q3_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q3_K ].pipeline; break; - case GGML_TYPE_Q4_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q4_K ].pipeline; break; - case GGML_TYPE_Q5_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q5_K ].pipeline; break; - case GGML_TYPE_Q6_K: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_Q6_K ].pipeline; break; - case GGML_TYPE_IQ2_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XXS].pipeline; break; - case GGML_TYPE_IQ2_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_XS ].pipeline; break; - case GGML_TYPE_IQ3_XXS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_XXS].pipeline; break; - case GGML_TYPE_IQ3_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ3_S ].pipeline; break; - case GGML_TYPE_IQ2_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ2_S ].pipeline; break; - case GGML_TYPE_IQ1_S: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_S ].pipeline; break; - case GGML_TYPE_IQ1_M: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ1_M ].pipeline; break; - case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_NL ].pipeline; break; - case GGML_TYPE_IQ4_XS: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_IQ4_XS ].pipeline; break; - case GGML_TYPE_I32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GET_ROWS_I32 ].pipeline; break; - default: GGML_ABORT("not implemented"); - } - - ggml_metal_kargs_get_rows args = { - /*.ne00 =*/ ne00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.ne10 =*/ ne10, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne10, ne11, 1) threadsPerThreadgroup:MTLSizeMake(32, 1, 1)]; - } break; - case GGML_OP_SET_ROWS: - { - id pipeline = nil; - - switch (dst->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_F32 ].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_F16 ].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_BF16 ].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_Q8_0 ].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_0 ].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_Q4_1 ].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_0 ].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_Q5_1 ].pipeline; break; - case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_ROWS_IQ4_NL].pipeline; break; - default: GGML_ABORT("not implemented"); - } - - const int32_t nk0 = ne0/ggml_blck_size(dst->type); - - int nth = 32; // SIMD width - - while (nth < nk0 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - int nrptg = 1; - if (nth > nk0) { - nrptg = (nth + nk0 - 1)/nk0; - nth = nk0; - - if (nrptg*nth > (int) pipeline.maxTotalThreadsPerThreadgroup) { - nrptg--; - } - } - - nth = MIN(nth, nk0); - - ggml_metal_kargs_set_rows args = { - /*.nk0 =*/ nk0, - /*.ne01 =*/ ne01, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nrptg - 1)/nrptg, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, nrptg, 1)]; - } break; - case GGML_OP_RMS_NORM: - { - GGML_ASSERT(ne00 % 4 == 0); - GGML_ASSERT(ggml_is_contiguous_1(src0)); - - float eps; - memcpy(&eps, dst->op_params, sizeof(float)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_RMS_NORM].pipeline; - - int nth = 32; // SIMD width - - while (nth < ne00/4 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - nth = MIN(nth, (int) pipeline.maxTotalThreadsPerThreadgroup); - nth = MIN(nth, ne00/4); - - ggml_metal_kargs_rms_norm args = { - /*.ne00 =*/ ne00, - /*.ne00_4 =*/ ne00/4, - /*.nb01 =*/ nb01, - /*.eps =*/ eps, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - const int64_t nrows = ggml_nrows(src0); - - [encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_L2_NORM: - { - GGML_ASSERT(ne00 % 4 == 0); - GGML_ASSERT(ggml_is_contiguous_1(src0)); - - float eps; - memcpy(&eps, dst->op_params, sizeof(float)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_L2_NORM].pipeline; - - int nth = 32; // SIMD width - - while (nth < ne00/4 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - nth = MIN(nth, (int) pipeline.maxTotalThreadsPerThreadgroup); - nth = MIN(nth, ne00/4); - - ggml_metal_kargs_l2_norm args = { - /*.ne00 =*/ ne00, - /*.ne00_4 =*/ ne00/4, - /*.nb01 =*/ nb01, - /*.eps =*/ eps, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - const int64_t nrows = ggml_nrows(src0); - - [encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_GROUP_NORM: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - - float eps; - memcpy(&eps, dst->op_params + 1, sizeof(float)); - - const int32_t n_groups = ((const int32_t *) dst->op_params)[0]; - - int nth = 32; // SIMD width - - //while (nth < ne00/4 && nth < 1024) { - // nth *= 2; - //} - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_GROUP_NORM].pipeline; - - ggml_metal_kargs_group_norm args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.n_groups =*/ n_groups, - /*.eps =*/ eps, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - [encoder dispatchThreadgroups:MTLSizeMake(n_groups, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_NORM: - { - GGML_ASSERT(ne00 % 4 == 0); - GGML_ASSERT(ggml_is_contiguous_1(src0)); - - float eps; - memcpy(&eps, dst->op_params, sizeof(float)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_NORM].pipeline; - - int nth = 32; // SIMD width - - while (nth < ne00/4 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - nth = MIN(nth, (int) pipeline.maxTotalThreadsPerThreadgroup); - nth = MIN(nth, ne00/4); - - ggml_metal_kargs_norm args = { - /*.ne00 =*/ ne00, - /*.ne00_4 =*/ ne00/4, - /*.nb01 =*/ nb01, - /*.eps =*/ eps, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - - const int64_t nrows = ggml_nrows(src0); - - [encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_ROPE: - { - - // make sure we have one or more position id(ne10) per token(ne02) - GGML_ASSERT(ne10 % ne02 == 0); - GGML_ASSERT(ne10 >= ne02); - - const int nth = MIN(1024, ne00); - - const int n_past = ((const int32_t *) dst->op_params)[0]; - const int n_dims = ((const int32_t *) dst->op_params)[1]; - const int mode = ((const int32_t *) dst->op_params)[2]; - // skip 3, n_ctx, used in GLM RoPE, unimplemented in metal - const int n_ctx_orig = ((const int32_t *) dst->op_params)[4]; - - float freq_base; - float freq_scale; - float ext_factor; - float attn_factor; - float beta_fast; - float beta_slow; - - memcpy(&freq_base, (const int32_t *) dst->op_params + 5, sizeof(float)); - memcpy(&freq_scale, (const int32_t *) dst->op_params + 6, sizeof(float)); - memcpy(&ext_factor, (const int32_t *) dst->op_params + 7, sizeof(float)); - memcpy(&attn_factor, (const int32_t *) dst->op_params + 8, sizeof(float)); - memcpy(&beta_fast, (const int32_t *) dst->op_params + 9, sizeof(float)); - memcpy(&beta_slow, (const int32_t *) dst->op_params + 10, sizeof(float)); - - const bool is_neox = mode & GGML_ROPE_TYPE_NEOX; - const bool is_mrope = mode & GGML_ROPE_TYPE_MROPE; - const bool is_vision = mode == GGML_ROPE_TYPE_VISION; - - // mrope - const int sect_0 = ((const int32_t *) dst->op_params)[11]; - const int sect_1 = ((const int32_t *) dst->op_params)[12]; - const int sect_2 = ((const int32_t *) dst->op_params)[13]; - const int sect_3 = ((const int32_t *) dst->op_params)[14]; - - id pipeline = nil; - - if (is_neox) { - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_NEOX_F16].pipeline; break; - default: GGML_ABORT("fatal error"); - }; - } else if (is_mrope && !is_vision) { - GGML_ASSERT(ne10*4 >= ne02); // need at least 4 pos per token - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_MULTI_F16].pipeline; break; - default: GGML_ABORT("fatal error"); - }; - } else if (is_vision) { - GGML_ASSERT(ne10*4 >= ne02); // need at least 4 pos per token - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_VISION_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_VISION_F16].pipeline; break; - default: GGML_ABORT("fatal error"); - }; - } else { - switch (src0->type) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_NORM_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ROPE_NORM_F16].pipeline; break; - default: GGML_ABORT("fatal error"); - }; - } - - ggml_metal_kargs_rope args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.n_past =*/ n_past, - /*.n_dims =*/ n_dims, - /*.n_ctx_orig =*/ n_ctx_orig, - /*.freq_base =*/ freq_base, - /*.freq_scale =*/ freq_scale, - /*.ext_factor =*/ ext_factor, - /*.attn_factor =*/ attn_factor, - /*.beta_fast =*/ beta_fast, - /*.beta_slow =*/ beta_slow, - /* sect_0 =*/ sect_0, - /* sect_1 =*/ sect_1, - /* sect_2 =*/ sect_2, - /* sect_3 =*/ sect_3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - if (id_src2 != nil) { - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:3]; - } else { - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:3]; - } - [encoder setBuffer:id_dst offset:offs_dst atIndex:4]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_IM2COL: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(src1)); - GGML_ASSERT(src0->type == GGML_TYPE_F16); - GGML_ASSERT(src1->type == GGML_TYPE_F32); - GGML_ASSERT( dst->type == GGML_TYPE_F16 || dst->type == GGML_TYPE_F32); - - const int32_t s0 = ((const int32_t *)(dst->op_params))[0]; - const int32_t s1 = ((const int32_t *)(dst->op_params))[1]; - const int32_t p0 = ((const int32_t *)(dst->op_params))[2]; - const int32_t p1 = ((const int32_t *)(dst->op_params))[3]; - const int32_t d0 = ((const int32_t *)(dst->op_params))[4]; - const int32_t d1 = ((const int32_t *)(dst->op_params))[5]; - - const bool is_2D = ((const int32_t *)(dst->op_params))[6] == 1; - - const int32_t N = src1->ne[is_2D ? 3 : 2]; - const int32_t IC = src1->ne[is_2D ? 2 : 1]; - const int32_t IH = is_2D ? src1->ne[1] : 1; - const int32_t IW = src1->ne[0]; - - const int32_t KH = is_2D ? src0->ne[1] : 1; - const int32_t KW = src0->ne[0]; - - const int32_t OH = is_2D ? dst->ne[2] : 1; - const int32_t OW = dst->ne[1]; - - const int32_t CHW = IC * KH * KW; - - const uint64_t ofs0 = src1->nb[is_2D ? 3 : 2] / 4; - const uint64_t ofs1 = src1->nb[is_2D ? 2 : 1] / 4; - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_IM2COL_F32].pipeline; - - const bool is_gt_mttpt = ((size_t)(N * KH * KW)) > pipeline.maxTotalThreadsPerThreadgroup; - - switch (dst->type) { - case GGML_TYPE_F32: { - pipeline = (is_gt_mttpt ? - ctx->kernels[GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F32].pipeline - : - ctx->kernels[GGML_METAL_KERNEL_TYPE_IM2COL_F32].pipeline); - } break; - case GGML_TYPE_F16: { - pipeline = (is_gt_mttpt ? - ctx->kernels[GGML_METAL_KERNEL_TYPE_IM2COL_EXT_F16].pipeline - : - ctx->kernels[GGML_METAL_KERNEL_TYPE_IM2COL_F16].pipeline); - } break; - default: GGML_ABORT("fatal error"); - }; - - ggml_metal_kargs_im2col args = { - /*.ofs0 =*/ ofs0, - /*.ofs1 =*/ ofs1, - /*.IW =*/ IW, - /*.IH =*/ IH, - /*.CHW =*/ CHW, - /*.s0 =*/ s0, - /*.s1 =*/ s1, - /*.p0 =*/ p0, - /*.p1 =*/ p1, - /*.d0 =*/ d0, - /*.d1 =*/ d1, - /*.N =*/ N, - /*.KH =*/ KH, - /*.KW =*/ KW, - /*.KHW =*/ KH * KW, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - if (is_gt_mttpt) { - const uint64_t n_threads = MIN(pipeline.maxTotalThreadsPerThreadgroup, (uint64_t)N); - - const int64_t quotient = N / n_threads + (N % n_threads > 0 ? 1 : 0); - - [encoder dispatchThreadgroups:MTLSizeMake(quotient * CHW, OH, OW) threadsPerThreadgroup:MTLSizeMake(n_threads, 1, 1)]; - } else { - [encoder dispatchThreadgroups:MTLSizeMake(IC, OH, OW) threadsPerThreadgroup:MTLSizeMake(N, KH, KW)]; - } - } break; - case GGML_OP_CONV_TRANSPOSE_1D: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(ggml_is_contiguous(src1)); - GGML_ASSERT(src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_F32); - GGML_ASSERT(src1->type == GGML_TYPE_F32); - GGML_ASSERT( dst->type == GGML_TYPE_F32); - - const int32_t s0 = ((const int32_t *)(dst->op_params))[0]; - - const int32_t IC = src1->ne[1]; - const int32_t IL = src1->ne[0]; - - const int32_t K = src0->ne[0]; - - const int32_t OL = dst->ne[0]; - const int32_t OC = dst->ne[1]; - - id pipeline; - - switch (src0->type) { - case GGML_TYPE_F32: { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F32_F32].pipeline; - } break; - case GGML_TYPE_F16: { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CONV_TRANSPOSE_1D_F16_F32].pipeline; - } break; - default: GGML_ABORT("fatal error"); - }; - - ggml_metal_kargs_conv_transpose_1d args = { - /*.IC =*/ IC, - /*.IL =*/ IL, - /*.K =*/ K, - /*.s0 =*/ s0, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - [encoder setBytes:&args length:sizeof(args) atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(OL, OC, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_UPSCALE: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - - const float sf0 = (float)ne0/src0->ne[0]; - const float sf1 = (float)ne1/src0->ne[1]; - const float sf2 = (float)ne2/src0->ne[2]; - const float sf3 = (float)ne3/src0->ne[3]; - - const id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_UPSCALE_F32].pipeline; - - ggml_metal_kargs_upscale args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.sf0 =*/ sf0, - /*.sf1 =*/ sf1, - /*.sf2 =*/ sf2, - /*.sf3 =*/ sf3 - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne1, ne2, ne3) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_PAD: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_PAD_F32].pipeline; - - ggml_metal_kargs_pad args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3 - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - const int nth = MIN(1024, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne1, ne2, ne3) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_PAD_REFLECT_1D: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - - const int32_t p0 = ((const int32_t *)(dst->op_params))[0]; - const int32_t p1 = ((const int32_t *)(dst->op_params))[1]; - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_PAD_REFLECT_1D_F32].pipeline; - - ggml_metal_kargs_pad_reflect_1d args = { - /*.ne00 =*/ ne00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - /*.p0 =*/ p0, - /*.p1 =*/ p1 - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - const int nth = MIN(1024, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(ne1, ne2, ne3) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_ARANGE: - { - GGML_ASSERT(dst->type == GGML_TYPE_F32); - - float start; - float step; - - memcpy(&start, ((const int32_t *) dst->op_params) + 0, sizeof(float)); - memcpy(&step, ((const int32_t *) dst->op_params) + 2, sizeof(float)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ARANGE_F32].pipeline; - - ggml_metal_kargs_arange args = { - /*.ne0 =*/ ne0, - /*.start =*/ start, - /*.step =*/ step - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:0]; - [encoder setBytes:&args length:sizeof(args) atIndex:1]; - - const int nth = MIN(1024, ne0); - - [encoder dispatchThreadgroups:MTLSizeMake(1, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_TIMESTEP_EMBEDDING: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - - const int dim = dst->op_params[0]; - const int max_period = dst->op_params[1]; - - const int half = dim / 2; - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_TIMESTEP_EMBEDDING_F32].pipeline; - - ggml_metal_kargs_timestep_embedding args = { - /*.nb1 =*/ nb1, - /*.dim =*/ dim, - /*.max_period =*/ max_period - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - const int nth = MIN(1024, half); - - [encoder dispatchThreadgroups:MTLSizeMake(ne00, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_ARGSORT: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT( dst->type == GGML_TYPE_I32); - - const int nrows = ggml_nrows(src0); - - enum ggml_sort_order order = (enum ggml_sort_order) dst->op_params[0]; - - // bitonic sort requires the number of elements to be power of 2 - int64_t ne00_padded = 1; - while (ne00_padded < ne00) { - ne00_padded *= 2; - } - - // Metal kernels require the buffer size to be multiple of 16 bytes - // https://developer.apple.com/documentation/metal/mtlcomputecommandencoder/1443142-setthreadgroupmemorylength - const int mem_size = GGML_PAD(ne00_padded*sizeof(int32_t), 16); - - id pipeline = nil; - - switch (order) { - case GGML_SORT_ORDER_ASC: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_ASC].pipeline; break; - case GGML_SORT_ORDER_DESC: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ARGSORT_F32_I32_DESC].pipeline; break; - default: GGML_ABORT("fatal error"); - }; - - ggml_metal_kargs_argsort args = { - /*.ncols =*/ ne00, - /*.ncols_pad =*/ ne00_padded - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - [encoder setThreadgroupMemoryLength:mem_size atIndex:0]; - - [encoder dispatchThreadgroups:MTLSizeMake(1, nrows, 1) threadsPerThreadgroup:MTLSizeMake(ne00_padded, 1, 1)]; - } break; - case GGML_OP_LEAKY_RELU: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - - float slope; - memcpy(&slope, dst->op_params, sizeof(float)); - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_LEAKY_RELU_F32].pipeline; - - ggml_metal_kargs_leaky_relu args = { - /*.slope =*/ slope - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args length:sizeof(args) atIndex:2]; - - const int64_t n = ggml_nelements(dst); - - [encoder dispatchThreadgroups:MTLSizeMake(n, 1, 1) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)]; - } break; - case GGML_OP_FLASH_ATTN_EXT: - { - GGML_ASSERT(ne00 % 4 == 0); - GGML_ASSERT(ne11 % 32 == 0); - - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(src1->type == src2->type); - - //GGML_ASSERT(ggml_are_same_shape (src1, src2)); - GGML_ASSERT(ne11 == ne21); - GGML_ASSERT(ne12 == ne22); - - struct ggml_tensor * src3 = node->src[3]; - - size_t offs_src3 = 0; - - id id_src3 = src3 ? ggml_metal_get_buffer(src3, &offs_src3) : nil; - - GGML_ASSERT(!src3 || src3->type == GGML_TYPE_F16); - GGML_ASSERT(!src3 || src3->ne[1] >= GGML_PAD(src0->ne[1], 8) && - "the Flash-Attention Metal kernel requires the mask to be padded to 8 and at least n_queries big"); - - const int64_t ne30 = src3 ? src3->ne[0] : 0; GGML_UNUSED(ne30); - //const int64_t ne31 = src3 ? src3->ne[1] : 0; - const int64_t ne32 = src3 ? src3->ne[2] : 0; GGML_UNUSED(ne32); - const int64_t ne33 = src3 ? src3->ne[3] : 0; GGML_UNUSED(ne33); - - const uint64_t nb30 = src3 ? src3->nb[0] : 0; GGML_UNUSED(nb30); - const uint64_t nb31 = src3 ? src3->nb[1] : 0; - const uint64_t nb32 = src3 ? src3->nb[2] : 0; GGML_UNUSED(nb32); - const uint64_t nb33 = src3 ? src3->nb[3] : 0; GGML_UNUSED(nb33); - - const enum ggml_type src2t = src2 ? src2->type : GGML_TYPE_COUNT; GGML_UNUSED(src2t); - - float scale; - float max_bias; - float logit_softcap; - memcpy(&scale, ((const int32_t *) dst->op_params) + 0, sizeof(scale)); - memcpy(&max_bias, ((const int32_t *) dst->op_params) + 1, sizeof(max_bias)); - memcpy(&logit_softcap, ((const int32_t *) dst->op_params) + 2, sizeof(logit_softcap)); - - if (logit_softcap != 0.0f) { - scale /= logit_softcap; - } - - const uint32_t n_head = src0->ne[2]; - const uint32_t n_head_log2 = 1u << (uint32_t) floorf(log2f((float) n_head)); - - const float m0 = powf(2.0f, -(max_bias ) / n_head_log2); - const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2); - - id pipeline = nil; - - bool use_vec_kernel = false; - - // TODO: add vec kernels for (ne00%64 == 0) and maybe also for (ne00%32 == 0) - // for now avoiding mainly to keep the number of templates/kernels a bit lower - // these are now trivial to add after: https://github.com/ggml-org/llama.cpp/pull/12612 - if (ne01 >= 20 || (ne00%128 != 0 && ne00 != 64 && ne00 != 96 && ne00 != 192 && ne00 != 576)) { - switch (src1->type) { - case GGML_TYPE_F16: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_F16_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_BF16: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_BF16_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_Q4_0: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_0_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_Q4_1: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q4_1_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_Q5_0: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_0_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_Q5_1: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q5_1_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - case GGML_TYPE_Q8_0: - { - if (ne00 == 192 && ne20 == 128) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK192_HV128].pipeline; - } else if (ne00 == 576 && ne20 == 512) { - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_HK576_HV512].pipeline; - } else { - switch (ne00) { - case 64: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H64 ].pipeline; break; - case 80: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H80 ].pipeline; break; - case 96: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H96 ].pipeline; break; - case 112: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H112].pipeline; break; - case 128: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H128].pipeline; break; - case 192: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H192].pipeline; break; - case 256: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_Q8_0_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - } break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } else { - use_vec_kernel = true; - - switch (ne00) { - case 64: - { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H64].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H64].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H64].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H64].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H64].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H64].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H64].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } break; - case 96: - { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H96].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H96].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H96].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H96].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H96].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H96].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H96].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } break; - case 128: - { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H128].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H128].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H128].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H128].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H128].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H128].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H128].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } break; - case 192: - { - if (ne20 == 128) { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK192_HV128].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK192_HV128].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK192_HV128].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK192_HV128].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK192_HV128].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK192_HV128].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK192_HV128].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } else { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H192].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H192].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H192].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H192].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H192].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H192].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H192].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } - } break; - case 256: - { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_H256].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_H256].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_H256].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_H256].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_H256].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_H256].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_H256].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } break; - case 576: - { - if (ne20 == 512) { - switch (src1->type) { - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_F16_HK576_HV512].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_BF16_HK576_HV512].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_0_HK576_HV512].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q4_1_HK576_HV512].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_0_HK576_HV512].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q5_1_HK576_HV512].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_FLASH_ATTN_EXT_VEC_Q8_0_HK576_HV512].pipeline; break; - default: - { - GGML_LOG_ERROR("unsupported type: %d\n", src1->type); - GGML_LOG_ERROR("add template specialization for this type\n"); - GGML_ABORT("add template specialization for this type"); - } - } - } else { - GGML_LOG_ERROR("unsupported size: %lld\n", ne20); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } break; - default: - { - GGML_LOG_ERROR("unsupported size: %lld\n", ne00); - GGML_LOG_ERROR("add template specialization for this size\n"); - GGML_ABORT("add template specialization for this size"); - } - } - } - - ggml_metal_kargs_flash_attn_ext args = { - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne11 =*/ ne11, - /*.ne_12_2 =*/ ne12, - /*.ne_12_3 =*/ ne13, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.nb21 =*/ nb21, - /*.nb22 =*/ nb22, - /*.nb23 =*/ nb23, - /*.ne32 =*/ ne32, - /*.ne33 =*/ ne33, - /*.nb31 =*/ nb31, - /*.nb32 =*/ nb32, - /*.nb33 =*/ nb33, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.scale =*/ scale, - /*.max_bias =*/ max_bias, - /*.m0 =*/ m0, - /*.m1 =*/ m1, - /*.n_head_log2 =*/ n_head_log2, - /*.logit_softcap =*/ logit_softcap, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_src2 offset:offs_src2 atIndex:3]; - if (id_src3) { - [encoder setBuffer:id_src3 offset:offs_src3 atIndex:4]; - } else { - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:4]; - } - [encoder setBuffer:id_dst offset:offs_dst atIndex:5]; - - if (!use_vec_kernel) { - // half8x8 kernel - const int64_t nqptg = 8; // queries per threadgroup !! sync with kernel template arguments !! - const int64_t ncpsg = 32; // cache values per simdgroup !! sync with kernel template arguments !! - - GGML_ASSERT(nqptg <= 32); - GGML_ASSERT(nqptg % 8 == 0); - GGML_ASSERT(ncpsg % 32 == 0); - - const int is_q = ggml_is_quantized(src1->type) ? 1 : 0; - - // 2*(2*ncpsg + nqptg)*(nsg) - // ncpsg soft_max values + ncpsg mask values + a diagonal scaling matrix (in float) - // - // 16*32*(nsg) - // the shared memory needed for the simdgroups to load the KV cache - // each thread loads (dequantizes) 16 head elements, there are 32 threads in th SG - // -#define FATTN_SMEM(nsg) (GGML_PAD((nqptg*(2*ne00 + 2*(2*ncpsg + nqptg)*(nsg)) + is_q*(16*32*(nsg)))*(sizeof(float)/2), 16)) - - int64_t nsgmax = 2; - - while (true) { - const size_t smem = FATTN_SMEM(nsgmax); - if (smem > device.maxThreadgroupMemoryLength) { - break; - } - nsgmax *= 2; - } - nsgmax /= 2; - - // simdgroups per threadgroup (a.k.a. warps) - const int64_t nsg = ne01 <= nqptg ? MAX(4, MIN(nsgmax, MIN(ne11/ncpsg, (int64_t) pipeline.maxTotalThreadsPerThreadgroup/32))) : 4; - - const size_t smem = FATTN_SMEM(nsg); - - //printf("smem: %zu, max: %zu, nsg = %d\n", smem, device.maxThreadgroupMemoryLength, (int) nsg); - GGML_ASSERT(smem <= device.maxThreadgroupMemoryLength); - [encoder setThreadgroupMemoryLength:smem atIndex:0]; -#undef FATTN_SMEM - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nqptg - 1)/nqptg, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)]; - } else { - // half4x4 kernel - const int64_t nqptg = 1; // queries per threadgroup !! sync with kernel template arguments !! - const int64_t ncpsg = 32; // cache values per simdgroup !! sync with kernel template arguments !! - - GGML_ASSERT(nqptg <= 32); - GGML_ASSERT(nqptg % 1 == 0); - GGML_ASSERT(ncpsg % 32 == 0); - - // ne00 + 2*ncpsg*(nsg) - // for each query, we load it as f16 in shared memory (ne00) - // and store the soft_max values and the mask - // - // ne00*(nsg) - // each simdgroup has a full f32 head vector in shared mem to accumulate results - // -#define FATTN_SMEM(nsg) (GGML_PAD((nqptg*(GGML_PAD(ne00, 128) + 4*ncpsg*(nsg)) + 2*ne20*(nsg))*(sizeof(float)/2), 16)) - - int64_t nsgmax = 2; - while (true) { - const size_t smem = FATTN_SMEM(nsgmax); - if (smem > device.maxThreadgroupMemoryLength) { - break; - } - nsgmax *= 2; - } - nsgmax /= 2; - - // simdgroups per threadgroup (a.k.a. warps) - const int64_t nsgt = MAX(2, MIN(nsgmax, MIN(ne11/ncpsg, (int64_t) pipeline.maxTotalThreadsPerThreadgroup/32))); - - int64_t nsg = 1; - while (nsg <= nsgt) { - nsg *= 2; - } - nsg /= 2; - - const size_t smem = FATTN_SMEM(nsg); - - //printf("smem: %zu, max: %zu, nsg = %d\n", smem, device.maxThreadgroupMemoryLength, (int) nsg); - GGML_ASSERT(smem <= device.maxThreadgroupMemoryLength); - [encoder setThreadgroupMemoryLength:smem atIndex:0]; -#undef FATTN_SMEM - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nqptg - 1)/nqptg, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(32, nsg, 1)]; - } - } break; - case GGML_OP_DUP: - case GGML_OP_CPY: - case GGML_OP_CONT: - { - id pipeline = nil; - - switch (src0t) { - case GGML_TYPE_F32: - { - GGML_ASSERT(ne0 % ggml_blck_size(dst->type) == 0); - - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_F16].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_BF16].pipeline; break; - case GGML_TYPE_Q8_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_Q8_0].pipeline; break; - case GGML_TYPE_Q4_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_0].pipeline; break; - case GGML_TYPE_Q4_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_Q4_1].pipeline; break; - case GGML_TYPE_Q5_0: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_0].pipeline; break; - case GGML_TYPE_Q5_1: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_Q5_1].pipeline; break; - case GGML_TYPE_IQ4_NL: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F32_IQ4_NL].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_F16: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F16_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_F16_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_BF16: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_BF16_F32].pipeline; break; - case GGML_TYPE_BF16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_BF16_BF16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_Q4_0: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q4_0_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_Q4_1: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q4_1_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_Q5_0: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q5_0_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_Q5_1: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q5_1_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - case GGML_TYPE_Q8_0: - { - switch (dstt) { - case GGML_TYPE_F32: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F32].pipeline; break; - case GGML_TYPE_F16: pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_CPY_Q8_0_F16].pipeline; break; - default: GGML_ABORT("not implemented"); - }; - } break; - default: GGML_ABORT("not implemented"); - } - - GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0); - - // TODO: support - //const int32_t nk00 = ne00/ggml_blck_size(dst->type); - const int32_t nk00 = ne00; - - int nth = 32; // SIMD width - - while (nth < nk00 && nth < (int) pipeline.maxTotalThreadsPerThreadgroup) { - nth *= 2; - } - - nth = MIN(nth, (int) pipeline.maxTotalThreadsPerThreadgroup); - - // when rows are small, we can batch them together in a single threadgroup - int nrptg = 1; - - // TODO: relax this constraint in the future - if (ggml_blck_size(src0->type) == 1 && ggml_blck_size(dst->type) == 1) { - if (nth > nk00) { - nrptg = (nth + nk00 - 1)/nk00; - nth = nk00; - - if (nrptg*nth > (int) pipeline.maxTotalThreadsPerThreadgroup) { - nrptg--; - } - } - } - - nth = MIN(nth, nk00); - - ggml_metal_kargs_cpy args = { - /*.ne00 =*/ nk00, - /*.ne01 =*/ ne01, - /*.ne02 =*/ ne02, - /*.ne03 =*/ ne03, - /*.nb00 =*/ nb00, - /*.nb01 =*/ nb01, - /*.nb02 =*/ nb02, - /*.nb03 =*/ nb03, - /*.ne0 =*/ ne0, - /*.ne1 =*/ ne1, - /*.ne2 =*/ ne2, - /*.ne3 =*/ ne3, - /*.nb0 =*/ nb0, - /*.nb1 =*/ nb1, - /*.nb2 =*/ nb2, - /*.nb3 =*/ nb3, - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:2]; - - [encoder dispatchThreadgroups:MTLSizeMake((ne01 + nrptg - 1)/nrptg, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(nth, nrptg, 1)]; - } break; - case GGML_OP_SET: - { - GGML_ASSERT(ggml_are_same_shape(src0, dst)); - GGML_ASSERT(ggml_is_contiguous(dst) && ggml_is_contiguous(src0)); - - // src0 and dst as viewed during set - const size_t dst_nb0 = ggml_element_size(src0); - - const size_t dst_nb1 = ((int32_t *) dst->op_params)[0]; - const size_t dst_nb2 = ((int32_t *) dst->op_params)[1]; - const size_t dst_nb3 = ((int32_t *) dst->op_params)[2]; - const size_t offset = ((int32_t *) dst->op_params)[3]; - const bool inplace = (bool) ((int32_t *) dst->op_params)[4]; - - if (!inplace) { - memcpy(((char *) dst->data), ((char *) src0->data), ggml_nbytes(dst)); - } - - const int im0 = (ne10 == 0 ? 0 : ne10-1); - const int im1 = (ne11 == 0 ? 0 : ne11-1); - const int im2 = (ne12 == 0 ? 0 : ne12-1); - const int im3 = (ne13 == 0 ? 0 : ne13-1); - - GGML_ASSERT(offset + im0*dst_nb0 + im1*dst_nb1 + im2*dst_nb2 + im3*dst_nb3 <= ggml_nbytes(dst)); - - id pipeline = nil; - - switch (src0t) { - case GGML_TYPE_F32: - GGML_ASSERT(nb10 == sizeof(float)); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_F32].pipeline; break; - case GGML_TYPE_I32: - GGML_ASSERT(nb10 == sizeof(int32_t)); - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_SET_I32].pipeline; break; - default: GGML_ABORT("fatal error"); - } - - ggml_metal_kargs_set args = { - /*.ne10 =*/ ne10, - /*.ne11 =*/ ne11, - /*.ne12 =*/ ne12, - /*.nb10 =*/ nb10, - /*.nb11 =*/ nb11, - /*.nb12 =*/ nb12, - /*.nb13 =*/ nb13, - /*.nb1 =*/ dst_nb1, - /*.nb2 =*/ dst_nb2, - /*.nb3 =*/ dst_nb3, - /*.offs =*/ offset, - /*.inplace =*/ inplace, - }; - - const int nth = MIN((int) pipeline.maxTotalThreadsPerThreadgroup, ne10); - - [encoder setComputePipelineState:pipeline]; - [encoder setBytes:&args length:sizeof(args) atIndex:0]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:1]; - [encoder setBuffer:id_src1 offset:offs_src1 atIndex:2]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:3]; - - [encoder dispatchThreadgroups:MTLSizeMake(ne11, ne12, ne13) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - case GGML_OP_POOL_2D: - { - GGML_ASSERT(ggml_is_contiguous(src0)); - GGML_ASSERT(src0t == GGML_TYPE_F32 && src0t == dstt); - - const int32_t * opts = dst->op_params; - enum ggml_op_pool op = opts[0]; - - id pipeline = nil; - switch (src0t) { - case GGML_TYPE_F32: { - switch(op) { - case GGML_OP_POOL_AVG: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_POOL_2D_AVG_F32].pipeline; break; - case GGML_OP_POOL_MAX: - pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_POOL_2D_MAX_F32].pipeline; break; - default: GGML_ASSERT(false && "not implemented"); - } - } break; - default: GGML_ASSERT(false && "not implemented"); - } - - const int32_t k0 = opts[1]; - const int32_t k1 = opts[2]; - const int32_t s0 = opts[3]; - const int32_t s1 = opts[4]; - const int32_t p0 = opts[5]; - const int32_t p1 = opts[6]; - - const int64_t IH = src0->ne[1]; - const int64_t IW = src0->ne[0]; - - const int64_t N = dst->ne[3]; - const int64_t OC = dst->ne[2]; - const int64_t OH = dst->ne[1]; - const int64_t OW = dst->ne[0]; - - const int64_t parallel_elements = N * OC * OH * OW; - const int64_t n_threads = MIN((int64_t)[pipeline maxTotalThreadsPerThreadgroup], parallel_elements); - const int64_t n_tg = (parallel_elements + n_threads - 1) / n_threads; - - ggml_metal_kargs_pool_2d args_pool_2d = { - /* .k0 = */ k0, - /* .k1 = */ k1, - /* .s0 = */ s0, - /* .s1 = */ s1, - /* .p0 = */ p0, - /* .p1 = */ p1, - /* .IH = */ IH, - /* .IW = */ IW, - /* .OH = */ OH, - /* .OW = */ OW, - /* .parallel_elements = */ parallel_elements - }; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&args_pool_2d length:sizeof(args_pool_2d) atIndex:2]; - - [encoder dispatchThreadgroups:MTLSizeMake(n_tg, 1, 1) threadsPerThreadgroup:MTLSizeMake(n_threads, 1, 1)]; - } break; - case GGML_OP_ARGMAX: - { - GGML_ASSERT(src0->type == GGML_TYPE_F32); - GGML_ASSERT(ggml_is_contiguous_1(src0)); - GGML_ASSERT(nb00 == ggml_type_size(src0->type)); - - const int64_t nrows = ggml_nrows(src0); - - int nth = 32; // SIMD width - while (nth < ne00 && nth*ne01*ne02*ne03 < 256) { - nth *= 2; - } - - id pipeline = ctx->kernels[GGML_METAL_KERNEL_TYPE_ARGMAX].pipeline; - - [encoder setComputePipelineState:pipeline]; - [encoder setBuffer:id_src0 offset:offs_src0 atIndex:0]; - [encoder setBuffer:id_dst offset:offs_dst atIndex:1]; - [encoder setBytes:&ne00 length:sizeof( int64_t) atIndex:2]; - [encoder setBytes:&nb01 length:sizeof(uint64_t) atIndex:3]; - [encoder setThreadgroupMemoryLength:32*sizeof(float) atIndex:0]; - [encoder setThreadgroupMemoryLength:32*sizeof(int32_t) atIndex:1]; - - [encoder dispatchThreadgroups:MTLSizeMake(nrows, 1, 1) threadsPerThreadgroup:MTLSizeMake(nth, 1, 1)]; - } break; - default: - { - GGML_LOG_ERROR("%s: error: node %3d, op = %8s not implemented\n", __func__, idx, ggml_op_name(dst->op)); - GGML_ABORT("fatal error"); - } - } - - return true; -} - -static enum ggml_status ggml_metal_graph_compute( - ggml_backend_t backend, - struct ggml_cgraph * gf) { - struct ggml_backend_metal_context * ctx = backend->context; - struct ggml_backend_metal_device_context * ctx_dev = backend->device->context; - - // number of nodes encoded by the main thread (empirically determined) - const int n_main = 128; - - // number of threads in addition to the main thread - const int n_cb = ctx->n_cb; - - // submit the ggml compute graph to the GPU by creating command buffers and encoding the ops in them - // the first n_nodes_0 are encoded and submitted for processing directly by the calling thread - // while these nodes are processing, we start n_cb threads to enqueue the rest of the nodes - // each thread creates it's own command buffer and enqueues the ops in parallel - // - // tests on M1 Pro and M2 Ultra using LLaMA models, show that optimal values for n_cb are 1 or 2 - - @autoreleasepool { - ctx->gf = gf; - - ctx->n_nodes_0 = MIN(n_main, gf->n_nodes); - ctx->n_nodes_1 = gf->n_nodes - ctx->n_nodes_0; - - ctx->n_nodes_per_cb = (ctx->n_nodes_1 + ctx->n_cb - 1) / ctx->n_cb; - - const bool should_capture = ctx->capture_next_compute; - if (should_capture) { - ctx->capture_next_compute = false; - - if (!ctx->capture_started) { - // create capture scope - ctx->capture_scope = [[MTLCaptureManager sharedCaptureManager] newCaptureScopeWithDevice:ctx_dev->mtl_device]; - - MTLCaptureDescriptor * descriptor = [MTLCaptureDescriptor new]; - descriptor.captureObject = ctx->capture_scope; - descriptor.destination = MTLCaptureDestinationGPUTraceDocument; - descriptor.outputURL = [NSURL fileURLWithPath:[NSString stringWithFormat:@"/tmp/perf-metal.gputrace"]]; - - NSError * error = nil; - if (![[MTLCaptureManager sharedCaptureManager] startCaptureWithDescriptor:descriptor error:&error]) { - GGML_LOG_ERROR("%s: error: unable to start capture '%s'\n", __func__, [[error localizedDescription] UTF8String]); - } else { - [ctx->capture_scope beginScope]; - ctx->capture_started = true; - } - } - } - - // the main thread commits the first few commands immediately - // cmd_buf[n_cb] - { - id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; - ctx->cmd_bufs[n_cb].obj = cmd_buf; - - [cmd_buf enqueue]; - ctx->encode_async(n_cb); - } - - // prepare the rest of the command buffers asynchronously - // cmd_buf[0.. n_cb) - for (int cb_idx = 0; cb_idx < n_cb; ++cb_idx) { - id cmd_buf = [ctx->queue commandBufferWithUnretainedReferences]; - ctx->cmd_bufs[cb_idx].obj = cmd_buf; - - // always enqueue the first two command buffers - // enqueue all of the command buffers if we don't need to abort - if (cb_idx < 2 || ctx->abort_callback == NULL) { - [cmd_buf enqueue]; - } - } - - dispatch_apply(n_cb, ctx->d_queue, ctx->encode_async); - - // wait for completion and check status of each command buffer - // needed to detect if the device ran out-of-memory for example (#1881) - { - id cmd_buf = ctx->cmd_bufs[n_cb].obj; - [cmd_buf waitUntilCompleted]; - - MTLCommandBufferStatus status = [cmd_buf status]; - if (status != MTLCommandBufferStatusCompleted) { - GGML_LOG_INFO("%s: command buffer %d failed with status %lu\n", __func__, n_cb, status); - if (status == MTLCommandBufferStatusError) { - GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); - } - - return GGML_STATUS_FAILED; - } - } - - for (int i = 0; i < n_cb; ++i) { - id cmd_buf = ctx->cmd_bufs[i].obj; - [cmd_buf waitUntilCompleted]; - - MTLCommandBufferStatus status = [cmd_buf status]; - if (status != MTLCommandBufferStatusCompleted) { - GGML_LOG_INFO("%s: command buffer %d failed with status %lu\n", __func__, i, status); - if (status == MTLCommandBufferStatusError) { - GGML_LOG_INFO("error: %s\n", [[cmd_buf error].localizedDescription UTF8String]); - } - - return GGML_STATUS_FAILED; - } - - id next_buffer = (i + 1 < n_cb ? ctx->cmd_bufs[i + 1].obj : nil); - if (!next_buffer) { - continue; - } - - const bool next_queued = ([next_buffer status] != MTLCommandBufferStatusNotEnqueued); - if (next_queued) { - continue; - } - - if (ctx->abort_callback && ctx->abort_callback(ctx->abort_callback_data)) { - GGML_LOG_INFO("%s: command buffer %d aborted", __func__, i); - return GGML_STATUS_ABORTED; - } - - [next_buffer commit]; - } - - if (!should_capture && ctx->capture_started) { - [ctx->capture_scope endScope]; - [[MTLCaptureManager sharedCaptureManager] stopCapture]; - } - } - - return GGML_STATUS_SUCCESS; -} - -//////////////////////////////////////////////////////////////////////////////// - -// backend interface - -static void ggml_backend_metal_buffer_free_buffer(ggml_backend_buffer_t buffer) { - struct ggml_backend_metal_buffer_context * ctx = (struct ggml_backend_metal_buffer_context *)buffer->context; - - for (int i = 0; i < ctx->n_buffers; i++) { - [ctx->buffers[i].metal release]; - } - - ggml_backend_metal_buffer_rset_free(ctx); - - if (ctx->owned) { -#if TARGET_OS_OSX - vm_deallocate((vm_map_t)mach_task_self(), (vm_address_t)ctx->all_data, ctx->all_size); -#else - free(ctx->all_data); -#endif - } - - free(ctx); -} - -static void * ggml_backend_metal_buffer_get_base(ggml_backend_buffer_t buffer) { - struct ggml_backend_metal_buffer_context * ctx = (struct ggml_backend_metal_buffer_context *)buffer->context; - - return ctx->all_data; -} - -static void ggml_backend_metal_buffer_memset_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, uint8_t value, size_t offset, size_t size) { - memset((char *)tensor->data + offset, value, size); - - GGML_UNUSED(buffer); -} - -static void ggml_backend_metal_buffer_set_tensor(ggml_backend_buffer_t buffer, struct ggml_tensor * tensor, const void * data, size_t offset, size_t size) { - memcpy((char *)tensor->data + offset, data, size); - - GGML_UNUSED(buffer); -} - -static void ggml_backend_metal_buffer_get_tensor(ggml_backend_buffer_t buffer, const struct ggml_tensor * tensor, void * data, size_t offset, size_t size) { - memcpy(data, (const char *)tensor->data + offset, size); - - GGML_UNUSED(buffer); -} - -static bool ggml_backend_metal_buffer_cpy_tensor(ggml_backend_buffer_t buffer, const struct ggml_tensor * src, struct ggml_tensor * dst) { - if (ggml_backend_buffer_is_host(src->buffer)) { - memcpy(dst->data, src->data, ggml_nbytes(src)); - return true; - } - return false; - - GGML_UNUSED(buffer); -} - -static void ggml_backend_metal_buffer_clear(ggml_backend_buffer_t buffer, uint8_t value) { - struct ggml_backend_metal_buffer_context * ctx = (struct ggml_backend_metal_buffer_context *)buffer->context; - - memset(ctx->all_data, value, ctx->all_size); -} - -static struct ggml_backend_buffer_i ggml_backend_metal_buffer_i = { - /* .free_buffer = */ ggml_backend_metal_buffer_free_buffer, - /* .get_base = */ ggml_backend_metal_buffer_get_base, - /* .init_tensor = */ NULL, - /* .memset_tensor = */ ggml_backend_metal_buffer_memset_tensor, - /* .set_tensor = */ ggml_backend_metal_buffer_set_tensor, - /* .get_tensor = */ ggml_backend_metal_buffer_get_tensor, - /* .cpy_tensor = */ ggml_backend_metal_buffer_cpy_tensor, - /* .clear = */ ggml_backend_metal_buffer_clear, - /* .reset = */ NULL, -}; - -// default buffer type - -static const char * ggml_backend_metal_buffer_type_get_name(ggml_backend_buffer_type_t buft) { - return "Metal"; - - GGML_UNUSED(buft); -} - -static void ggml_backend_metal_log_allocated_size(id device, size_t size_aligned) { -#ifndef GGML_METAL_NDEBUG -#if TARGET_OS_OSX || (TARGET_OS_IOS && __clang_major__ >= 15) - if (@available(macOS 10.12, iOS 16.0, *)) { - GGML_LOG_DEBUG("%s: allocated buffer, size = %8.2f MiB, (%8.2f / %8.2f)\n", - __func__, - size_aligned / 1024.0 / 1024.0, - device.currentAllocatedSize / 1024.0 / 1024.0, - device.recommendedMaxWorkingSetSize / 1024.0 / 1024.0); - - if (device.currentAllocatedSize > device.recommendedMaxWorkingSetSize) { - GGML_LOG_WARN("%s: warning: current allocated size is greater than the recommended max working set size\n", __func__); - } - } else { - GGML_LOG_INFO("%s: allocated buffer, size = %8.2f MiB, (%8.2f)\n", - __func__, - size_aligned / 1024.0 / 1024.0, - device.currentAllocatedSize / 1024.0 / 1024.0); - } -#endif -#endif - GGML_UNUSED(device); - GGML_UNUSED(size_aligned); -} - -static ggml_backend_buffer_t ggml_backend_metal_buffer_type_alloc_buffer(ggml_backend_buffer_type_t buft, size_t size) { - struct ggml_backend_metal_buffer_context * ctx = calloc(1, sizeof(struct ggml_backend_metal_buffer_context)); - - const size_t size_page = sysconf(_SC_PAGESIZE); - - size_t size_aligned = size; - if ((size_aligned % size_page) != 0) { - size_aligned += (size_page - (size_aligned % size_page)); - } - - struct ggml_backend_metal_device_context * ctx_dev = (struct ggml_backend_metal_device_context *)buft->device->context; - - GGML_ASSERT(ctx_dev->mtl_device != nil); - - id device = ctx_dev->mtl_device; - - ctx->all_data = ggml_metal_host_malloc(size_aligned); - ctx->all_size = size_aligned; - ctx->owned = true; - ctx->n_buffers = 1; - - if (ctx->all_data != NULL) { - ctx->buffers[0].data = ctx->all_data; - ctx->buffers[0].size = size; - ctx->buffers[0].metal = nil; - - if (size_aligned > 0) { - ctx->buffers[0].metal = [device newBufferWithBytesNoCopy:ctx->all_data - length:size_aligned - options:MTLResourceStorageModeShared - deallocator:nil]; - } - } - - if (size_aligned > 0 && (ctx->all_data == NULL || ctx->buffers[0].metal == nil)) { - GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_aligned / 1024.0 / 1024.0); - free(ctx); - return NULL; - } - - if (!ggml_backend_metal_buffer_rset_init(ctx, ctx_dev, device)) { - GGML_LOG_ERROR("%s: error: failed to initialize residency set\n", __func__); - free(ctx); - return NULL; - } - - //ggml_backend_metal_log_allocated_size(device, size_aligned); - - return ggml_backend_buffer_init(buft, ggml_backend_metal_buffer_i, ctx, size); -} - -static size_t ggml_backend_metal_buffer_type_get_alignment(ggml_backend_buffer_type_t buft) { - return 32; - - GGML_UNUSED(buft); -} - -static size_t ggml_backend_metal_buffer_type_get_max_size(ggml_backend_buffer_type_t buft) { - const size_t max_size = ((struct ggml_backend_metal_device_context *)buft->device->context)->max_size; - - return max_size; -} - -static bool ggml_backend_metal_buffer_type_is_host(ggml_backend_buffer_type_t buft) { - return true; - - GGML_UNUSED(buft); -} - -ggml_backend_buffer_type_t ggml_backend_metal_buffer_type(void) { - static struct ggml_backend_buffer_type ggml_backend_buffer_type_metal = { - /* .iface = */ { - /* .get_name = */ ggml_backend_metal_buffer_type_get_name, - /* .alloc_buffer = */ ggml_backend_metal_buffer_type_alloc_buffer, - /* .get_alignment = */ ggml_backend_metal_buffer_type_get_alignment, - /* .get_max_size = */ ggml_backend_metal_buffer_type_get_max_size, - /* .get_alloc_size = */ NULL, // defaults to ggml_nbytes - /* .is_host = */ ggml_backend_metal_buffer_type_is_host, - }, - /* .device = */ &g_ggml_backend_metal_device, - /* .context = */ NULL, - }; - - return &ggml_backend_buffer_type_metal; -} - -static const char * ggml_backend_metal_buffer_from_ptr_type_get_name(ggml_backend_buffer_type_t buft) { - return "Metal_Mapped"; - - GGML_UNUSED(buft); -} - -static ggml_backend_buffer_type_t ggml_backend_metal_buffer_from_ptr_type(void) { - static struct ggml_backend_buffer_type ggml_backend_buffer_from_ptr_type_metal = { - /* .iface = */ { - /* .get_name = */ ggml_backend_metal_buffer_from_ptr_type_get_name, - /* .alloc_buffer = */ ggml_backend_metal_buffer_type_alloc_buffer, - /* .get_alignment = */ ggml_backend_metal_buffer_type_get_alignment, - /* .get_max_size = */ ggml_backend_metal_buffer_type_get_max_size, - /* .get_alloc_size = */ NULL, // defaults to ggml_nbytes - /* .is_host = */ ggml_backend_metal_buffer_type_is_host, - }, - /* .device = */ &g_ggml_backend_metal_device, - /* .context = */ NULL, - }; - - return &ggml_backend_buffer_from_ptr_type_metal; -} - -// TODO: obsoleted by ggml_backend_metal_device_buffer_from_ptr -ggml_backend_buffer_t ggml_backend_metal_buffer_from_ptr(void * data, size_t size, size_t max_size) { - struct ggml_backend_metal_buffer_context * ctx = calloc(1, sizeof(struct ggml_backend_metal_buffer_context)); - - ctx->all_data = data; - ctx->all_size = size; - ctx->owned = false; - ctx->n_buffers = 0; - - const size_t size_page = sysconf(_SC_PAGESIZE); - - // page-align the data ptr - { - const uintptr_t offs = (uintptr_t) data % size_page; - data = (void *) ((char *) data - offs); - size += offs; - } - - size_t size_aligned = size; - if ((size_aligned % size_page) != 0) { - size_aligned += (size_page - (size_aligned % size_page)); - } - - struct ggml_backend_metal_device_context * ctx_dev = &g_ggml_ctx_dev_main; - - GGML_ASSERT(ctx_dev->mtl_device != nil); - - id device = ctx_dev->mtl_device; - - // the buffer fits into the max buffer size allowed by the device - if (size_aligned <= device.maxBufferLength) { - ctx->buffers[ctx->n_buffers].data = data; - ctx->buffers[ctx->n_buffers].size = size; - ctx->buffers[ctx->n_buffers].metal = nil; - - if (size_aligned > 0) { - ctx->buffers[ctx->n_buffers].metal = [device newBufferWithBytesNoCopy:data length:size_aligned options:MTLResourceStorageModeShared deallocator:nil]; - - if (ctx->buffers[ctx->n_buffers].metal == nil) { - GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_aligned / 1024.0 / 1024.0); - return false; - } - } - - ggml_backend_metal_log_allocated_size(device, size_aligned); - - ++ctx->n_buffers; - } else { - // this overlap between the views will guarantee that the tensor with the maximum size will fully fit into - // one of the views - const size_t size_ovlp = ((max_size + size_page - 1) / size_page + 1) * size_page; // round-up 2 pages just in case - const size_t size_step = device.maxBufferLength - size_ovlp; - const size_t size_view = device.maxBufferLength; - - for (size_t i = 0; i < size; i += size_step) { - const size_t size_step_aligned = (i + size_view <= size) ? size_view : (size_aligned - i); - - ctx->buffers[ctx->n_buffers].data = (void *) ((uint8_t *) data + i); - ctx->buffers[ctx->n_buffers].size = size_step_aligned; - ctx->buffers[ctx->n_buffers].metal = nil; - - if (size_step_aligned > 0) { - ctx->buffers[ctx->n_buffers].metal = [device newBufferWithBytesNoCopy:(void *) ((uint8_t *) data + i) length:size_step_aligned options:MTLResourceStorageModeShared deallocator:nil]; - - if (ctx->buffers[ctx->n_buffers].metal == nil) { - GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_step_aligned / 1024.0 / 1024.0); - return false; - } - } - - ggml_backend_metal_log_allocated_size(device, size_step_aligned); - - if (i + size_step < size) { - GGML_LOG_INFO("\n"); - } - - ++ctx->n_buffers; - } - } - - if (!ggml_backend_metal_buffer_rset_init(ctx, ctx_dev, device)) { - GGML_LOG_ERROR("%s: error: failed to initialize residency set\n", __func__); - free(ctx); - return NULL; - } - - return ggml_backend_buffer_init(ggml_backend_metal_buffer_from_ptr_type(), ggml_backend_metal_buffer_i, ctx, size); -} - -// backend - -static const char * ggml_backend_metal_name(ggml_backend_t backend) { - return "Metal"; - - GGML_UNUSED(backend); -} - -static void ggml_backend_metal_free(ggml_backend_t backend) { - struct ggml_backend_metal_context * ctx = backend->context; - - ggml_metal_free(ctx); - - free(backend); -} - -static enum ggml_status ggml_backend_metal_graph_compute(ggml_backend_t backend, struct ggml_cgraph * cgraph) { - return ggml_metal_graph_compute(backend, cgraph); -} - -static void ggml_backend_metal_set_n_cb(ggml_backend_t backend, int n_cb) { - GGML_ASSERT(ggml_backend_is_metal(backend)); - - struct ggml_backend_metal_context * ctx = (struct ggml_backend_metal_context *)backend->context; - - if (ctx->n_cb != n_cb) { - ctx->n_cb = MIN(n_cb, GGML_METAL_MAX_COMMAND_BUFFERS); - - if (ctx->n_cb > 2) { - GGML_LOG_WARN("%s: n_cb = %d, using n_cb > 2 is not recommended and can degrade the performance in some cases\n", __func__, n_cb); - } - } - - if (ctx->encode_async) { - Block_release(ctx->encode_async); - } - - ctx->encode_async = Block_copy(^(size_t iter) { - const int cb_idx = iter; - const int n_cb_l = ctx->n_cb; - - const int n_nodes_0 = ctx->n_nodes_0; - const int n_nodes_1 = ctx->n_nodes_1; - - const int n_nodes_per_cb = ctx->n_nodes_per_cb; - - id cmd_buf = ctx->cmd_bufs[cb_idx].obj; - - id encoder = [cmd_buf computeCommandEncoder]; - - int node_start = 0; - int node_end = n_nodes_0; - - if (cb_idx < n_cb_l) { - node_start = n_nodes_0 + ( (cb_idx + 0) * n_nodes_per_cb); - node_end = n_nodes_0 + (MIN((cb_idx == n_cb_l - 1) ? n_nodes_1 : (cb_idx + 1) * n_nodes_per_cb, n_nodes_1)); - } - - const bool should_capture = ctx->capture_next_compute; - - struct ggml_metal_mem_pool * mem_pool = ctx->cmd_bufs[cb_idx].mem_pool; - ggml_metal_mem_pool_reset(mem_pool); - - for (int idx = node_start; idx < node_end; ++idx) { - if (should_capture) { - [encoder pushDebugGroup:[NSString stringWithCString:ggml_op_desc(ggml_graph_node(ctx->gf, idx)) encoding:NSUTF8StringEncoding]]; - } - - const bool res = ggml_metal_encode_node(backend, idx, encoder, mem_pool); - - if (should_capture) { - [encoder popDebugGroup]; - } - - if (!res) { - break; - } - } - - [encoder endEncoding]; - - if (cb_idx < 2 || ctx->abort_callback == NULL) { - [cmd_buf commit]; - } - }); -} - -static struct ggml_backend_i ggml_backend_metal_i = { - /* .get_name = */ ggml_backend_metal_name, - /* .free = */ ggml_backend_metal_free, - /* .set_tensor_async = */ NULL, - /* .get_tensor_async = */ NULL, - /* .cpy_tensor_async = */ NULL, - /* .synchronize = */ NULL, - /* .graph_plan_create = */ NULL, - /* .graph_plan_free = */ NULL, - /* .graph_plan_update = */ NULL, - /* .graph_plan_compute = */ NULL, - /* .graph_compute = */ ggml_backend_metal_graph_compute, - /* .event_record = */ NULL, - /* .event_wait = */ NULL, -}; - -static ggml_guid_t ggml_backend_metal_guid(void) { - static ggml_guid guid = { 0x81, 0xa1, 0x8b, 0x1e, 0x71, 0xec, 0x79, 0xed, 0x2b, 0x85, 0xdc, 0x8a, 0x61, 0x98, 0x30, 0xe6 }; - return &guid; -} - -// TODO: remove in the future -ggml_backend_t ggml_backend_metal_init(void) { - ggml_backend_dev_t dev = ggml_backend_reg_dev_get(ggml_backend_metal_reg(), 0); - - struct ggml_backend_metal_context * ctx = ggml_metal_init(dev); - if (ctx == NULL) { - GGML_LOG_ERROR("%s: error: failed to allocate context\n", __func__); - return NULL; - } - - ggml_backend_t backend = malloc(sizeof(struct ggml_backend)); - - *backend = (struct ggml_backend) { - /* .guid = */ ggml_backend_metal_guid(), - /* .interface = */ ggml_backend_metal_i, - /* .device = */ dev, - /* .context = */ ctx, - }; - - ggml_backend_metal_set_n_cb(backend, 1); - - return backend; -} - -bool ggml_backend_is_metal(ggml_backend_t backend) { - return backend != NULL && ggml_guid_matches(backend->guid, ggml_backend_metal_guid()); -} - -void ggml_backend_metal_set_abort_callback(ggml_backend_t backend, ggml_abort_callback abort_callback, void * user_data) { - GGML_ASSERT(ggml_backend_is_metal(backend)); - - struct ggml_backend_metal_context * ctx = (struct ggml_backend_metal_context *)backend->context; - - ctx->abort_callback = abort_callback; - ctx->abort_callback_data = user_data; -} - -bool ggml_backend_metal_supports_family(ggml_backend_t backend, int family) { - GGML_ASSERT(ggml_backend_is_metal(backend)); - - struct ggml_backend_metal_device_context * ctx_dev = backend->device->context; - - GGML_ASSERT(ctx_dev->mtl_device != nil); - - return [ctx_dev->mtl_device supportsFamily:(MTLGPUFamilyApple1 + family - 1)]; -} - -void ggml_backend_metal_capture_next_compute(ggml_backend_t backend) { - GGML_ASSERT(ggml_backend_is_metal(backend)); - - struct ggml_backend_metal_context * ctx = (struct ggml_backend_metal_context *)backend->context; - ctx->capture_next_compute = true; -} - -// backend device - -static const char * ggml_backend_metal_device_get_name(ggml_backend_dev_t dev) { - return "Metal"; - - GGML_UNUSED(dev); -} - -static const char * ggml_backend_metal_device_get_description(ggml_backend_dev_t dev) { - struct ggml_backend_metal_device_context * ctx_dev = (struct ggml_backend_metal_device_context *)dev->context; - - return ctx_dev->name; -} - -static void ggml_backend_metal_device_get_memory(ggml_backend_dev_t dev, size_t * free, size_t * total) { - if (@available(macOS 10.12, iOS 16.0, *)) { - struct ggml_backend_metal_device_context * ctx_dev = (struct ggml_backend_metal_device_context *)dev->context; - id device = ctx_dev->mtl_device; - - *total = device.recommendedMaxWorkingSetSize; - *free = *total - device.currentAllocatedSize; - } else { - *free = 1; - *total = 1; - } -} - -static enum ggml_backend_dev_type ggml_backend_metal_device_get_type(ggml_backend_dev_t dev) { - return GGML_BACKEND_DEVICE_TYPE_GPU; - - GGML_UNUSED(dev); -} - -static void ggml_backend_metal_device_get_props(ggml_backend_dev_t dev, struct ggml_backend_dev_props * props) { - props->name = ggml_backend_metal_device_get_name(dev); - props->description = ggml_backend_metal_device_get_description(dev); - props->type = ggml_backend_metal_device_get_type(dev); - ggml_backend_metal_device_get_memory(dev, &props->memory_free, &props->memory_total); - props->caps = (struct ggml_backend_dev_caps) { - /* .async = */ false, - /* .host_buffer = */ false, - /* .buffer_from_host_ptr = */ true, - /* .events = */ false, - }; -} - -static ggml_backend_t ggml_backend_metal_device_init(ggml_backend_dev_t dev, const char * params) { - struct ggml_backend_metal_context * ctx = ggml_metal_init(dev); - if (ctx == NULL) { - GGML_LOG_ERROR("%s: error: failed to allocate context\n", __func__); - return NULL; - } - - ggml_backend_t backend = malloc(sizeof(struct ggml_backend)); - - *backend = (struct ggml_backend) { - /* .guid = */ ggml_backend_metal_guid(), - /* .interface = */ ggml_backend_metal_i, - /* .device = */ dev, - /* .context = */ ctx, - }; - - ggml_backend_metal_set_n_cb(backend, 1); - - return backend; - - GGML_UNUSED(params); -} - -static ggml_backend_buffer_type_t ggml_backend_metal_device_get_buffer_type(ggml_backend_dev_t dev) { - return ggml_backend_metal_buffer_type(); - - GGML_UNUSED(dev); -} - -static ggml_backend_buffer_t ggml_backend_metal_device_buffer_from_ptr(ggml_backend_dev_t dev, void * ptr, size_t size, size_t max_tensor_size) { - struct ggml_backend_metal_buffer_context * ctx = calloc(1, sizeof(struct ggml_backend_metal_buffer_context)); - - ctx->all_data = ptr; - ctx->all_size = size; - ctx->owned = false; - ctx->n_buffers = 0; - - const size_t size_page = sysconf(_SC_PAGESIZE); - - // page-align the data ptr - { - const uintptr_t offs = (uintptr_t) ptr % size_page; - ptr = (void *) ((char *) ptr - offs); - size += offs; - } - - size_t size_aligned = size; - if ((size_aligned % size_page) != 0) { - size_aligned += (size_page - (size_aligned % size_page)); - } - - struct ggml_backend_metal_device_context * ctx_dev = (struct ggml_backend_metal_device_context *)dev->context; - - GGML_ASSERT(ctx_dev->mtl_device != nil); - - id device = ctx_dev->mtl_device; - - // the buffer fits into the max buffer size allowed by the device - if (size_aligned <= device.maxBufferLength) { - ctx->buffers[ctx->n_buffers].data = ptr; - ctx->buffers[ctx->n_buffers].size = size; - ctx->buffers[ctx->n_buffers].metal = nil; - - if (size_aligned > 0) { - ctx->buffers[ctx->n_buffers].metal = [device newBufferWithBytesNoCopy:ptr length:size_aligned options:MTLResourceStorageModeShared deallocator:nil]; - - if (ctx->buffers[ctx->n_buffers].metal == nil) { - GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_aligned / 1024.0 / 1024.0); - return false; - } - } - - ggml_backend_metal_log_allocated_size(device, size_aligned); - - ++ctx->n_buffers; - } else { - // this overlap between the views will guarantee that the tensor with the maximum size will fully fit into - // one of the views - const size_t size_ovlp = ((max_tensor_size + size_page - 1) / size_page + 1) * size_page; // round-up 2 pages just in case - const size_t size_step = device.maxBufferLength - size_ovlp; - const size_t size_view = device.maxBufferLength; - - for (size_t i = 0; i < size; i += size_step) { - const size_t size_step_aligned = (i + size_view <= size) ? size_view : (size_aligned - i); - - ctx->buffers[ctx->n_buffers].data = (void *) ((uint8_t *) ptr + i); - ctx->buffers[ctx->n_buffers].size = size_step_aligned; - ctx->buffers[ctx->n_buffers].metal = nil; - - if (size_step_aligned > 0) { - ctx->buffers[ctx->n_buffers].metal = [device newBufferWithBytesNoCopy:(void *) ((uint8_t *) ptr + i) length:size_step_aligned options:MTLResourceStorageModeShared deallocator:nil]; - - if (ctx->buffers[ctx->n_buffers].metal == nil) { - GGML_LOG_ERROR("%s: error: failed to allocate buffer, size = %8.2f MiB\n", __func__, size_step_aligned / 1024.0 / 1024.0); - return false; - } - } - - ggml_backend_metal_log_allocated_size(device, size_step_aligned); - - if (i + size_step < size) { - GGML_LOG_INFO("\n"); - } - - ++ctx->n_buffers; - } - } - - if (!ggml_backend_metal_buffer_rset_init(ctx, ctx_dev, device)) { - GGML_LOG_ERROR("%s: error: failed to initialize residency set\n", __func__); - free(ctx); - return NULL; - } - - return ggml_backend_buffer_init(ggml_backend_metal_buffer_from_ptr_type(), ggml_backend_metal_buffer_i, ctx, size); -} - -static bool ggml_backend_metal_device_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { - struct ggml_backend_metal_device_context * ctx_dev = dev->context; - - return ggml_metal_supports_op(ctx_dev, op); -} - -static bool ggml_backend_metal_device_supports_buft(ggml_backend_dev_t dev, ggml_backend_buffer_type_t buft) { - return - buft->iface.get_name == ggml_backend_metal_buffer_type_get_name || - buft->iface.get_name == ggml_backend_metal_buffer_from_ptr_type_get_name; - - GGML_UNUSED(dev); -} - -static bool ggml_backend_metal_device_offload_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { - return false; - - GGML_UNUSED(dev); - GGML_UNUSED(op); -} - -static struct ggml_backend_device_i ggml_backend_metal_device_i = { - /* .get_name = */ ggml_backend_metal_device_get_name, - /* .get_description = */ ggml_backend_metal_device_get_description, - /* .get_memory = */ ggml_backend_metal_device_get_memory, - /* .get_type = */ ggml_backend_metal_device_get_type, - /* .get_props = */ ggml_backend_metal_device_get_props, - /* .init_backend = */ ggml_backend_metal_device_init, - /* .get_buffer_type = */ ggml_backend_metal_device_get_buffer_type, - /* .get_host_buffer_type = */ NULL, - /* .buffer_from_host_ptr = */ ggml_backend_metal_device_buffer_from_ptr, - /* .supports_op = */ ggml_backend_metal_device_supports_op, - /* .supports_buft = */ ggml_backend_metal_device_supports_buft, - /* .offload_op = */ ggml_backend_metal_device_offload_op, - /* .event_new = */ NULL, - /* .event_free = */ NULL, - /* .event_synchronize = */ NULL, -}; - -// backend registry - -static const char * ggml_backend_metal_reg_get_name(ggml_backend_reg_t reg) { - return "Metal"; - - GGML_UNUSED(reg); -} - -static size_t ggml_backend_metal_reg_device_count(ggml_backend_reg_t reg) { - return 1; - - GGML_UNUSED(reg); -} - -static ggml_backend_dev_t ggml_backend_metal_reg_device_get(ggml_backend_reg_t reg, size_t index) { - GGML_ASSERT(index == 0); - - return &g_ggml_backend_metal_device; - - GGML_UNUSED(reg); - GGML_UNUSED(index); -} - -static struct ggml_backend_feature g_ggml_backend_metal_features[] = { -#if defined(GGML_METAL_EMBED_LIBRARY) - { "EMBED_LIBRARY", "1" }, -#endif -#if defined(GGML_METAL_USE_BF16) - { "BF16", "1" }, -#endif - { nil, nil }, -}; - -static struct ggml_backend_feature * ggml_backend_metal_get_features(ggml_backend_reg_t reg) { - return g_ggml_backend_metal_features; - - GGML_UNUSED(reg); -} - -static void * ggml_backend_metal_get_proc_address(ggml_backend_reg_t reg, const char * name) { - if (strcmp(name, "ggml_backend_get_features") == 0) { - return (void *)ggml_backend_metal_get_features; - } - - return NULL; - - GGML_UNUSED(reg); -} -static struct ggml_backend_reg_i ggml_backend_metal_reg_i = { - /* .get_name = */ ggml_backend_metal_reg_get_name, - /* .device_count = */ ggml_backend_metal_reg_device_count, - /* .device_get = */ ggml_backend_metal_reg_device_get, - /* .get_proc_address = */ ggml_backend_metal_get_proc_address, -}; - -// called upon program exit -static void ggml_metal_cleanup(void) { - ggml_backend_metal_device_rel(&g_ggml_ctx_dev_main); -} - -// TODO: make thread-safe -ggml_backend_reg_t ggml_backend_metal_reg(void) { - ggml_backend_metal_device_acq(&g_ggml_ctx_dev_main); - - // register cleanup callback - // TODO: not ideal, but not sure if there is a better way to do this in Objective-C - atexit(ggml_metal_cleanup); - - { - g_ggml_backend_metal_reg = (struct ggml_backend_reg) { - /* .api_version = */ GGML_BACKEND_API_VERSION, - /* .iface = */ ggml_backend_metal_reg_i, - /* .context = */ NULL, - }; - - g_ggml_backend_metal_device = (struct ggml_backend_device) { - /* .iface = */ ggml_backend_metal_device_i, - /* .reg = */ &g_ggml_backend_metal_reg, - /* .context = */ &g_ggml_ctx_dev_main, - }; - } - - return &g_ggml_backend_metal_reg; -} - -GGML_BACKEND_DL_IMPL(ggml_backend_metal_reg) diff -pruN 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.metal 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.metal --- 5882+dfsg-2/ggml/src/ggml-metal/ggml-metal.metal 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-metal/ggml-metal.metal 2025-09-30 07:36:33.000000000 +0000 @@ -15,6 +15,10 @@ using namespace metal; #define MIN(x, y) ((x) < (y) ? (x) : (y)) #define SWAP(x, y) { auto tmp = (x); (x) = (y); (y) = tmp; } +#define PAD2(x, n) (((x) + (n) - 1) & ~((n) - 1)) + +#define FOR_UNROLL(x) _Pragma("clang loop unroll(full)") for (x) + #define N_SIMDWIDTH 32 // assuming SIMD group size is 32 // ref: https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf @@ -23,18 +27,23 @@ using namespace metal; // .../usr/bin/metal -dM -E -c ggml/src/ggml-metal/ggml-metal.metal // .../usr/bin/metal -dM -E -c -target air64-apple-ios14.0 ggml/src/ggml-metal/ggml-metal.metal // -#if __METAL_VERSION__ < 310 && defined(GGML_METAL_USE_BF16) -#undef GGML_METAL_USE_BF16 +#if __METAL_VERSION__ < 310 && defined(GGML_METAL_HAS_BF16) +#undef GGML_METAL_HAS_BF16 #endif -#if defined(GGML_METAL_USE_BF16) +#if defined(GGML_METAL_HAS_BF16) typedef matrix bfloat4x4; +typedef matrix bfloat2x4; #endif constexpr constant static float kvalues_iq4nl_f[16] = { -127.f, -104.f, -83.f, -65.f, -49.f, -35.f, -22.f, -10.f, 1.f, 13.f, 25.f, 38.f, 53.f, 69.f, 89.f, 113.f }; +constexpr constant static float kvalues_mxfp4_f[16] = { + 0, .5f, 1.f, 1.5f, 2.f, 3.f, 4.f, 6.f, -0, -.5f, -1.f, -1.5f, -2.f, -3.f, -4.f, -6.f +}; + static inline int best_index_int8(int n, constant float * val, float x) { if (x <= val[0]) return 0; if (x >= val[n-1]) return n-1; @@ -46,12 +55,33 @@ static inline int best_index_int8(int n, return x - val[mu-1] < val[mu] - x ? mu-1 : mu; } +static inline float e8m0_to_fp32(uint8_t x) { + uint32_t bits; + + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint32_t) x << 23; + } + + return as_type(bits); +} + +static inline float dot(float x, float y) { + return x*y; +} + // NOTE: this is not dequantizing - we are simply fitting the template template void dequantize_f32(device const float4x4 * src, short il, thread type4x4 & reg) { reg = (type4x4)(*src); } +template +void dequantize_f32_t4(device const float4 * src, short il, thread type4 & reg) { + reg = (type4)(*src); +} + template void dequantize_f16(device const half4x4 * src, short il, thread type4x4 & reg) { reg = (type4x4)(*src); @@ -62,7 +92,7 @@ void dequantize_f16_t4(device const half reg = (type4)(*(src)); } -#if defined(GGML_METAL_USE_BF16) +#if defined(GGML_METAL_HAS_BF16) template void dequantize_bf16(device const bfloat4x4 * src, short il, thread type4x4 & reg) { reg = (type4x4)(*src); @@ -242,6 +272,27 @@ void quantize_q5_1(device const float * } } +void quantize_q8_0(device const float * src, device block_q8_0 & dst) { +#pragma METAL fp math_mode(safe) + float amax = 0.0f; // absolute max + + for (int j = 0; j < QK8_0; j++) { + const float v = src[j]; + amax = MAX(amax, fabs(v)); + } + + const float d = amax / ((1 << 7) - 1); + const float id = d ? 1.0f/d : 0.0f; + + dst.d = d; + + for (int j = 0; j < QK8_0; ++j) { + const float x0 = src[j]*id; + + dst.qs[j] = round(x0); + } +} + void quantize_iq4_nl(device const float * src, device block_iq4_nl & dst) { #pragma METAL fp math_mode(safe) float amax = 0.0f; // absolute max @@ -462,25 +513,34 @@ void dequantize_q8_0_t4(device const blo } } -void quantize_q8_0(device const float * src, device block_q8_0 & dst) { -#pragma METAL fp math_mode(safe) - float amax = 0.0f; // absolute max +template +void dequantize_mxfp4(device const block_mxfp4 * xb, short il, thread type4x4 & reg) { + device const uint8_t * q2 = (device const uint8_t *)xb->qs; - for (int j = 0; j < QK8_0; j++) { - const float v = src[j]; - amax = MAX(amax, fabs(v)); + const float d = e8m0_to_fp32(xb->e); + const uint8_t shr = il >= 1 ? 4 : 0; + + for (int i = 0; i < 4; ++i) { + reg[i][0] = d * kvalues_mxfp4_f[(q2[4*i + 0] >> shr) & 0x0F]; + reg[i][1] = d * kvalues_mxfp4_f[(q2[4*i + 1] >> shr) & 0x0F]; + reg[i][2] = d * kvalues_mxfp4_f[(q2[4*i + 2] >> shr) & 0x0F]; + reg[i][3] = d * kvalues_mxfp4_f[(q2[4*i + 3] >> shr) & 0x0F]; } +} - const float d = amax / ((1 << 7) - 1); - const float id = d ? 1.0f/d : 0.0f; +template +void dequantize_mxfp4_t4(device const block_mxfp4 * xb, short il, thread type4 & reg) { + device const uint8_t * q2 = (device const uint8_t *)xb->qs; - dst.d = d; + const float d = e8m0_to_fp32(xb->e); + const short il4 = il%4; - for (int j = 0; j < QK8_0; ++j) { - const float x0 = src[j]*id; + const uint8_t shr = il >= 4 ? 4 : 0; - dst.qs[j] = round(x0); - } + reg[0] = d * kvalues_mxfp4_f[(q2[4*il4 + 0] >> shr) & 0x0F]; + reg[1] = d * kvalues_mxfp4_f[(q2[4*il4 + 1] >> shr) & 0x0F]; + reg[2] = d * kvalues_mxfp4_f[(q2[4*il4 + 2] >> shr) & 0x0F]; + reg[3] = d * kvalues_mxfp4_f[(q2[4*il4 + 3] >> shr) & 0x0F]; } template @@ -832,7 +892,8 @@ enum ggml_sort_order { // general-purpose kernel for addition, subtraction, multiplication and division of two tensors // pros: works for non-contiguous tensors, supports broadcast across all dims // cons: not very efficient -kernel void kernel_add( +template +kernel void kernel_add_fuse_impl( constant ggml_metal_kargs_bin & args, device const char * src0, device const char * src1, @@ -848,17 +909,40 @@ kernel void kernel_add( const int i12 = i02%args.ne12; const int i11 = i01%args.ne11; - device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01 + args.offs; - device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11; - device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1 + args.offs; + device const float * src0_ptr = (device const float *) (src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01 + args.offs); + device float * dst_ptr = (device float *) (dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1 + args.offs); + + device const float * src1_ptr[F]; + for (short j = 0; j < F; ++j) { + src1_ptr[j] = (device const float *) (src1 + args.o1[j] + i13*args.nb13 + i12*args.nb12 + i11*args.nb11); + } for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { const int i10 = i0%args.ne10; - *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) + *((device float *)(src1_ptr + i10*args.nb10)); + + float res = src0_ptr[i0]; + +#pragma unroll + for (short j = 0; j < F; ++j) { + res += src1_ptr[j][i10]; + } + + dst_ptr[i0] = res; } } -kernel void kernel_sub( +typedef decltype(kernel_add_fuse_impl<2>) kernel_add_fuse_t; + +template [[host_name("kernel_add_fuse_1")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<1>; +template [[host_name("kernel_add_fuse_2")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<2>; +template [[host_name("kernel_add_fuse_3")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<3>; +template [[host_name("kernel_add_fuse_4")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<4>; +template [[host_name("kernel_add_fuse_5")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<5>; +template [[host_name("kernel_add_fuse_6")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<6>; +template [[host_name("kernel_add_fuse_7")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<7>; +template [[host_name("kernel_add_fuse_8")]] kernel kernel_add_fuse_t kernel_add_fuse_impl<8>; + +kernel void kernel_sub_fuse_1( constant ggml_metal_kargs_bin & args, device const char * src0, device const char * src1, @@ -875,7 +959,7 @@ kernel void kernel_sub( const int i11 = i01%args.ne11; device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01 + args.offs; - device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11; + device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11 + args.o1[0]; device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1 + args.offs; for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { @@ -884,7 +968,7 @@ kernel void kernel_sub( } } -kernel void kernel_mul( +kernel void kernel_mul_fuse_1( constant ggml_metal_kargs_bin & args, device const char * src0, device const char * src1, @@ -900,17 +984,24 @@ kernel void kernel_mul( const int i12 = i02%args.ne12; const int i11 = i01%args.ne11; - device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01; - device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11; - device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1; + device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01 + args.offs; + device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11 + args.o1[0]; + device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1 + args.offs; - for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { - const int i10 = i0%args.ne10; - *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) * *((device float *)(src1_ptr + i10*args.nb10)); + if (args.ne10 == 1) { + const float x = *((device float *)(src1_ptr)); + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) * x; + } + } else { + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + const int i10 = i0%args.ne10; + *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) * *((device float *)(src1_ptr + i10*args.nb10)); + } } } -kernel void kernel_div( +kernel void kernel_div_fuse_1( constant ggml_metal_kargs_bin & args, device const char * src0, device const char * src1, @@ -926,13 +1017,46 @@ kernel void kernel_div( const int i12 = i02%args.ne12; const int i11 = i01%args.ne11; - device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01; - device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11; - device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1; + device const char * src0_ptr = src0 + i03*args.nb03 + i02*args.nb02 + i01*args.nb01 + args.offs; + device const char * src1_ptr = src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11 + args.o1[0]; + device char * dst_ptr = dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1 + args.offs; + + if (args.ne10 == 1) { + const float x = 1.0f / *((device float *)(src1_ptr)); + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) * x; + } + } else { + for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { + const int i10 = i0%args.ne10; + *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) / *((device float *)(src1_ptr + i10*args.nb10)); + } + } +} + +kernel void kernel_add_id( + constant ggml_metal_kargs_add_id & args, + device const char * src0, + device const char * src1, + device const char * src2, + device char * dst, + uint3 tgpig[[threadgroup_position_in_grid]], + ushort3 tpitg[[thread_position_in_threadgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { + const int i1 = tgpig.x; + const int i2 = tgpig.y; + + const int i11 = *((device const int32_t *) (src2 + i1*sizeof(int32_t) + i2*args.nb21)); + + const size_t nb1 = args.ne0 * sizeof(float); + const size_t nb2 = args.ne1 * nb1; + + device float * dst_row = (device float *)((device char *)dst + i1*nb1 + i2*nb2); + device const float * src0_row = (device const float *)((device char *)src0 + i1*args.nb01 + i2*args.nb02); + device const float * src1_row = (device const float *)((device char *)src1 + i11*args.nb11); for (int i0 = tpitg.x; i0 < args.ne0; i0 += ntg.x) { - const int i10 = i0%args.ne10; - *((device float *)(dst_ptr + i0*args.nb0)) = *((device float *)(src0_ptr + i0*args.nb00)) / *((device float *)(src1_ptr + i10*args.nb10)); + dst_row[i0] = src0_row[i0] + src1_row[i0]; } } @@ -970,93 +1094,211 @@ template [[host_name("kernel_repeat_i16" // assumption: src1 is a row // broadcast src1 into src0 -kernel void kernel_add_row( +template +kernel void kernel_add_row_c4_fuse_impl( constant ggml_metal_kargs_bin & args, - device const float4 * src0, - device const float4 * src1, - device float4 * dst, + device const char * src0, + device const char * src1, + device char * dst, uint tpig[[thread_position_in_grid]]) { const uint nb = args.ne00/4; - dst[tpig] = src0[tpig] + src1[tpig % nb]; + const uint i = tpig % nb; + + device const float4 * src0_row = (device const float4 *) (src0); + device float4 * dst_row = (device float4 *) (dst); + + float4 res = src0_row[tpig]; + +#pragma unroll(F) + for (short j = 0; j < F; ++j) { + res += ((device const float4 *) (src1 + args.o1[j]))[i]; + } + + dst_row[tpig] = res; } -kernel void kernel_sub_row( +typedef decltype(kernel_add_row_c4_fuse_impl<1>) kernel_add_row_c4_fuse_t; + +template [[host_name("kernel_add_row_c4_fuse_1")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<1>; +template [[host_name("kernel_add_row_c4_fuse_2")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<2>; +template [[host_name("kernel_add_row_c4_fuse_3")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<3>; +template [[host_name("kernel_add_row_c4_fuse_4")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<4>; +template [[host_name("kernel_add_row_c4_fuse_5")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<5>; +template [[host_name("kernel_add_row_c4_fuse_6")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<6>; +template [[host_name("kernel_add_row_c4_fuse_7")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<7>; +template [[host_name("kernel_add_row_c4_fuse_8")]] kernel kernel_add_row_c4_fuse_t kernel_add_row_c4_fuse_impl<8>; + +template +kernel void kernel_sub_row_c4_fuse_impl( constant ggml_metal_kargs_bin & args, - device const float4 * src0, - device const float4 * src1, - device float4 * dst, + device const char * src0, + device const char * src1, + device char * dst, uint tpig[[thread_position_in_grid]]) { + const uint nb = args.ne00/4; - dst[tpig] = src0[tpig] - src1[tpig % nb]; + const uint i = tpig % nb; + + device const float4 * src0_row = (device const float4 *) (src0); + device float4 * dst_row = (device float4 *) (dst); + + device const float4 * src1_row[F]; + for (short j = 0; j < F; ++j) { + src1_row[j] = (device const float4 *) (src1 + args.o1[j]); + } + + float4 res = src0_row[tpig]; + +#pragma unroll(F) + for (short j = 0; j < F; ++j) { + res -= src1_row[j][i]; + } + + dst_row[tpig] = res; } -kernel void kernel_mul_row( +typedef decltype(kernel_sub_row_c4_fuse_impl<1>) kernel_sub_row_c4_fuse_t; + +template [[host_name("kernel_sub_row_c4_fuse_1")]] kernel kernel_sub_row_c4_fuse_t kernel_sub_row_c4_fuse_impl<1>; + +template +kernel void kernel_mul_row_c4_fuse_impl( constant ggml_metal_kargs_bin & args, - device const float4 * src0, - device const float4 * src1, - device float4 * dst, + device const char * src0, + device const char * src1, + device char * dst, uint tpig[[thread_position_in_grid]]) { + const uint nb = args.ne00/4; - dst[tpig] = src0[tpig] * src1[tpig % nb]; + const uint i = tpig % nb; + + device const float4 * src0_row = (device const float4 *) (src0); + device float4 * dst_row = (device float4 *) (dst); + + device const float4 * src1_row[F]; + for (short j = 0; j < F; ++j) { + src1_row[j] = (device const float4 *) (src1 + args.o1[j]); + } + + float4 res = src0_row[tpig]; + +#pragma unroll(F) + for (short j = 0; j < F; ++j) { + res *= src1_row[j][i]; + } + + dst_row[tpig] = res; } -kernel void kernel_div_row( +typedef decltype(kernel_mul_row_c4_fuse_impl<1>) kernel_mul_row_c4_fuse_t; + +template [[host_name("kernel_mul_row_c4_fuse_1")]] kernel kernel_mul_row_c4_fuse_t kernel_mul_row_c4_fuse_impl<1>; + +template +kernel void kernel_div_row_c4_fuse_impl( constant ggml_metal_kargs_bin & args, - device const float4 * src0, - device const float4 * src1, - device float4 * dst, + device const char * src0, + device const char * src1, + device char * dst, uint tpig[[thread_position_in_grid]]) { + const uint nb = args.ne00/4; - dst[tpig] = src0[tpig] / src1[tpig % nb]; + const uint i = tpig % nb; + + device const float4 * src0_row = (device const float4 *) (src0); + device float4 * dst_row = (device float4 *) (dst); + + device const float4 * src1_row[F]; + for (short j = 0; j < F; ++j) { + src1_row[j] = (device const float4 *) (src1 + args.o1[j]); + } + + float4 res = src0_row[tpig]; + +#pragma unroll(F) + for (short j = 0; j < F; ++j) { + res /= src1_row[j][i]; + } + + dst_row[tpig] = res; } -kernel void kernel_scale( +typedef decltype(kernel_div_row_c4_fuse_impl<1>) kernel_div_row_c4_fuse_t; + +template [[host_name("kernel_div_row_c4_fuse_1")]] kernel kernel_div_row_c4_fuse_t kernel_div_row_c4_fuse_impl<1>; + +kernel void kernel_scale_f32( + constant ggml_metal_kargs_scale & args, device const float * src0, device float * dst, - constant float & scale, - constant float & bias, uint tpig[[thread_position_in_grid]]) { - dst[tpig] = src0[tpig] * scale + bias; + dst[tpig] = src0[tpig] * args.scale + args.bias; } -kernel void kernel_scale_4( +kernel void kernel_scale_f32_4( + constant ggml_metal_kargs_scale & args, device const float4 * src0, device float4 * dst, - constant float & scale, - constant float & bias, uint tpig[[thread_position_in_grid]]) { - dst[tpig] = src0[tpig] * scale + bias; + dst[tpig] = src0[tpig] * args.scale + args.bias; } -kernel void kernel_clamp( +kernel void kernel_clamp_f32( + constant ggml_metal_kargs_clamp & args, device const float * src0, device float * dst, - constant float & min, - constant float & max, uint tpig[[thread_position_in_grid]]) { - dst[tpig] = src0[tpig] < min ? min : (src0[tpig] > max ? max : src0[tpig]); + dst[tpig] = clamp(src0[tpig], args.min, args.max); +} + +kernel void kernel_clamp_f32_4( + constant ggml_metal_kargs_clamp & args, + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = clamp(src0[tpig], args.min, args.max); } -kernel void kernel_relu( +kernel void kernel_relu_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = max(0.0f, src0[tpig]); } -kernel void kernel_sigmoid( +kernel void kernel_relu_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = max(0.0f, src0[tpig]); +} + +kernel void kernel_sigmoid_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = 1.0f / (1.0f + exp(-src0[tpig])); } -kernel void kernel_tanh( +kernel void kernel_sigmoid_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = 1.0f / (1.0f + exp(-src0[tpig])); +} + +kernel void kernel_tanh_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { - device const float & x = src0[tpig]; - dst[tpig] = precise::tanh(x); + dst[tpig] = precise::tanh(src0[tpig]); +} + +kernel void kernel_tanh_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = precise::tanh(src0[tpig]); } constant float GELU_COEF_A = 0.044715f; @@ -1064,7 +1306,7 @@ constant float GELU_QUICK_COEF = -1.702f constant float SQRT_2_OVER_PI = 0.79788456080286535587989211986876f; constant float SQRT_2_INV = 0.70710678118654752440084436210484f; -kernel void kernel_gelu( +kernel void kernel_gelu_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { @@ -1073,7 +1315,7 @@ kernel void kernel_gelu( dst[tpig] = 0.5f*x*(1.0f + precise::tanh(SQRT_2_OVER_PI*x*(1.0f + GELU_COEF_A*x*x))); } -kernel void kernel_gelu_4( +kernel void kernel_gelu_f32_4( device const float4 * src0, device float4 * dst, uint tpig[[thread_position_in_grid]]) { @@ -1086,7 +1328,7 @@ kernel void kernel_gelu_4( dst[tpig] = 0.5f*x*(1.0f + precise::tanh(SQRT_2_OVER_PI*x*(1.0f + GELU_COEF_A*x*x))); } -kernel void kernel_gelu_quick( +kernel void kernel_gelu_quick_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { @@ -1095,7 +1337,7 @@ kernel void kernel_gelu_quick( dst[tpig] = x*(1.0f/(1.0f+exp(GELU_QUICK_COEF*x))); } -kernel void kernel_gelu_quick_4( +kernel void kernel_gelu_quick_f32_4( device const float4 * src0, device float4 * dst, uint tpig[[thread_position_in_grid]]) { @@ -1122,7 +1364,7 @@ T erf_approx(T x) { return sign_x * y; } -kernel void kernel_gelu_erf( +kernel void kernel_gelu_erf_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { @@ -1131,7 +1373,7 @@ kernel void kernel_gelu_erf( dst[tpig] = 0.5f*x*(1.0f+erf_approx(x*SQRT_2_INV)); } -kernel void kernel_gelu_erf_4( +kernel void kernel_gelu_erf_f32_4( device const float4 * src0, device float4 * dst, uint tpig[[thread_position_in_grid]]) { @@ -1140,7 +1382,7 @@ kernel void kernel_gelu_erf_4( dst[tpig] = 0.5f*x*(1.0f+erf_approx(x*SQRT_2_INV)); } -kernel void kernel_silu( +kernel void kernel_silu_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { @@ -1148,7 +1390,7 @@ kernel void kernel_silu( dst[tpig] = x / (1.0f + exp(-x)); } -kernel void kernel_silu_4( +kernel void kernel_silu_f32_4( device const float4 * src0, device float4 * dst, uint tpig[[thread_position_in_grid]]) { @@ -1156,54 +1398,202 @@ kernel void kernel_silu_4( dst[tpig] = x / (1.0f + exp(-x)); } -kernel void kernel_elu( +kernel void kernel_elu_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { - device const float & x = src0[tpig]; + const float x = src0[tpig]; dst[tpig] = (x > 0.0f) ? x : (exp(x) - 1.0f); } -kernel void kernel_sqr( +kernel void kernel_elu_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + const float4 x = src0[tpig]; + dst[tpig][0] = (x[0] > 0.0f) ? x[0] : (exp(x[0]) - 1.0f); + dst[tpig][1] = (x[1] > 0.0f) ? x[1] : (exp(x[1]) - 1.0f); + dst[tpig][2] = (x[2] > 0.0f) ? x[2] : (exp(x[2]) - 1.0f); + dst[tpig][3] = (x[3] > 0.0f) ? x[3] : (exp(x[3]) - 1.0f); +} + +kernel void kernel_sqr_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = src0[tpig] * src0[tpig]; } -kernel void kernel_sqrt( +kernel void kernel_sqr_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = src0[tpig] * src0[tpig]; +} + +kernel void kernel_sqrt_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = sqrt(src0[tpig]); } -kernel void kernel_sin( +kernel void kernel_sqrt_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = sqrt(src0[tpig]); +} + +kernel void kernel_sin_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = sin(src0[tpig]); } -kernel void kernel_cos( +kernel void kernel_sin_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = sin(src0[tpig]); +} + +kernel void kernel_cos_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = cos(src0[tpig]); } -kernel void kernel_neg( +kernel void kernel_cos_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = cos(src0[tpig]); +} + +kernel void kernel_log_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = log(src0[tpig]); +} + +kernel void kernel_log_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = log(src0[tpig]); +} + +kernel void kernel_neg_f32( device const float * src0, device float * dst, uint tpig[[thread_position_in_grid]]) { dst[tpig] = -src0[tpig]; } -kernel void kernel_reglu( +kernel void kernel_neg_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = -src0[tpig]; +} + +kernel void kernel_abs_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = fabs(src0[tpig]); +} + +kernel void kernel_abs_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = fabs(src0[tpig]); +} + +kernel void kernel_sgn_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = sign(src0[tpig]); +} + +kernel void kernel_sgn_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = sign(src0[tpig]); +} + +kernel void kernel_step_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = step(0.0f, src0[tpig]); +} + +kernel void kernel_step_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = step(0.0f, src0[tpig]); +} + +kernel void kernel_hardswish_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + const float x = src0[tpig]; + dst[tpig] = x * fmin(1.0f, fmax(0.0f, (x + 3.0f) / 6.0f)); +} + +kernel void kernel_hardswish_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + const float4 x = src0[tpig]; + dst[tpig] = x * fmin(1.0f, fmax(0.0f, (x + 3.0f) / 6.0f)); +} + +kernel void kernel_hardsigmoid_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + const float x = src0[tpig]; + dst[tpig] = fmin(1.0f, fmax(0.0f, (x + 3.0f) / 6.0f)); +} + +kernel void kernel_hardsigmoid_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + const float4 x = src0[tpig]; + dst[tpig] = fmin(1.0f, fmax(0.0f, (x + 3.0f) / 6.0f)); +} + +kernel void kernel_exp_f32( + device const float * src0, + device float * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = exp(src0[tpig]); +} + +kernel void kernel_exp_f32_4( + device const float4 * src0, + device float4 * dst, + uint tpig[[thread_position_in_grid]]) { + dst[tpig] = exp(src0[tpig]); +} + +kernel void kernel_reglu_f32( + constant ggml_metal_kargs_glu & args, device const char * src0, device const char * src1, device char * dst, - constant ggml_metal_kargs_glu & args, uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint ntg[[threads_per_threadgroup]]) { @@ -1219,11 +1609,11 @@ kernel void kernel_reglu( } } -kernel void kernel_geglu( +kernel void kernel_geglu_f32( + constant ggml_metal_kargs_glu & args, device const char * src0, device const char * src1, device char * dst, - constant ggml_metal_kargs_glu & args, uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint ntg[[threads_per_threadgroup]]) { @@ -1241,11 +1631,11 @@ kernel void kernel_geglu( } } -kernel void kernel_swiglu( +kernel void kernel_swiglu_f32( + constant ggml_metal_kargs_glu & args, device const char * src0, device const char * src1, device char * dst, - constant ggml_metal_kargs_glu & args, uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint ntg[[threads_per_threadgroup]]) { @@ -1263,11 +1653,37 @@ kernel void kernel_swiglu( } } -kernel void kernel_geglu_erf( +kernel void kernel_swiglu_oai_f32( + constant ggml_metal_kargs_glu & args, device const char * src0, device const char * src1, device char * dst, + uint tgpig[[threadgroup_position_in_grid]], + uint tpitg[[thread_position_in_threadgroup]], + uint ntg[[threads_per_threadgroup]]) { + device const float * src0_row = (device const float *) ((device const char *) src0 + tgpig*args.nb01) + args.i00; + device const float * src1_row = (device const float *) ((device const char *) src1 + tgpig*args.nb11) + args.i10; + device float * dst_row = (device float *) ((device char *) dst + tgpig*args.nb1); + + for (int i0 = tpitg; i0 < args.ne0; i0 += ntg) { + float x0 = src0_row[i0]; + float x1 = src1_row[i0]; + + x0 = min(x0, args.limit); + x1 = max(min(x1, args.limit), -args.limit); + + float out_glu = x0 / (1.0f + exp(-x0 * args.alpha)); + out_glu = out_glu * (1.0f + x1); + + dst_row[i0] = out_glu; + } +} + +kernel void kernel_geglu_erf_f32( constant ggml_metal_kargs_glu & args, + device const char * src0, + device const char * src1, + device char * dst, uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint ntg[[threads_per_threadgroup]]) { @@ -1285,11 +1701,11 @@ kernel void kernel_geglu_erf( } } -kernel void kernel_geglu_quick( +kernel void kernel_geglu_quick_f32( + constant ggml_metal_kargs_glu & args, device const char * src0, device const char * src1, device char * dst, - constant ggml_metal_kargs_glu & args, uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint ntg[[threads_per_threadgroup]]) { @@ -1359,15 +1775,16 @@ kernel void kernel_sum_rows( typedef decltype(kernel_sum_rows) kernel_sum_rows_t; -template [[host_name("kernel_sum_rows")]] kernel kernel_sum_rows_t kernel_sum_rows; -template [[host_name("kernel_mean")]] kernel kernel_sum_rows_t kernel_sum_rows; +template [[host_name("kernel_sum_rows_f32")]] kernel kernel_sum_rows_t kernel_sum_rows; +template [[host_name("kernel_mean_f32")]] kernel kernel_sum_rows_t kernel_sum_rows; template kernel void kernel_soft_max( + constant ggml_metal_kargs_soft_max & args, device const char * src0, device const char * src1, + device const char * src2, device char * dst, - constant ggml_metal_kargs_soft_max & args, threadgroup float * buf [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], @@ -1384,6 +1801,7 @@ kernel void kernel_soft_max( device const float * psrc0 = (device const float *) (src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); device const T * pmask = src1 != src0 ? (device const T * ) (src1 + i11*args.nb11 + i12*args.nb12 + i13*args.nb13) : nullptr; + device const float * psrc2 = src2 != src0 ? (device const float *) (src2) : nullptr; device float * pdst = (device float *) (dst + i01*args.nb1 + i02*args.nb2 + i03*args.nb3); float slope = 1.0f; @@ -1399,7 +1817,7 @@ kernel void kernel_soft_max( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = tpitg.x; i00 < args.ne00; i00 += tptg.x) { lmax = MAX(lmax, psrc0[i00]*args.scale + (pmask ? slope*pmask[i00] : 0.0f)); @@ -1455,6 +1873,10 @@ kernel void kernel_soft_max( sum = simd_sum(sum); } + if (psrc2) { + sum += exp(psrc2[i02] - max_val); + } + const float inv_sum = 1.0f/sum; for (int i00 = tpitg.x; i00 < args.ne00; i00 += tptg.x) { @@ -1464,10 +1886,11 @@ kernel void kernel_soft_max( template kernel void kernel_soft_max_4( + constant ggml_metal_kargs_soft_max & args, device const char * src0, device const char * src1, + device const char * src2, device char * dst, - constant ggml_metal_kargs_soft_max & args, threadgroup float * buf [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], @@ -1484,6 +1907,7 @@ kernel void kernel_soft_max_4( device const float4 * psrc4 = (device const float4 *) (src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); device const T * pmask = src1 != src0 ? (device const T * ) (src1 + i11*args.nb11 + i12*args.nb12 + i13*args.nb13) : nullptr; + device const float * psrc2 = src2 != src0 ? (device const float * ) (src2) : nullptr; device float4 * pdst4 = (device float4 *) (dst + i01*args.nb1 + i02*args.nb2 + i03*args.nb3); float slope = 1.0f; @@ -1498,7 +1922,7 @@ kernel void kernel_soft_max_4( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = tpitg.x; i00 < args.ne00/4; i00 += tptg.x) { lmax4 = fmax(lmax4, psrc4[i00]*args.scale + (float4)((pmask ? slope*pmask[i00] : 0.0f))); @@ -1557,6 +1981,10 @@ kernel void kernel_soft_max_4( sum = simd_sum(sum); } + if (psrc2) { + sum += exp(psrc2[i02] - max_val); + } + const float inv_sum = 1.0f/sum; for (int i00 = tpitg.x; i00 < args.ne00/4; i00 += tptg.x) { @@ -1572,53 +2000,12 @@ template [[host_name("kernel_soft_max_f3 template [[host_name("kernel_soft_max_f16_4")]] kernel kernel_soft_max_4_t kernel_soft_max_4; template [[host_name("kernel_soft_max_f32_4")]] kernel kernel_soft_max_4_t kernel_soft_max_4; -kernel void kernel_diag_mask_inf( - device const float * src0, - device float * dst, - constant ggml_metal_kargs_diag_mask_inf & args, - uint3 tpig[[thread_position_in_grid]]) { - const int64_t i02 = tpig[2]; - const int64_t i01 = tpig[1]; - const int64_t i00 = tpig[0]; - - if (i00 > args.n_past + i01) { - dst[i02*args.ne01*args.ne00 + i01*args.ne00 + i00] = -INFINITY; - } else { - dst[i02*args.ne01*args.ne00 + i01*args.ne00 + i00] = src0[i02*args.ne01*args.ne00 + i01*args.ne00 + i00]; - } -} - -kernel void kernel_diag_mask_inf_8( - device const float4 * src0, - device float4 * dst, - constant ggml_metal_kargs_diag_mask_inf & args, - uint3 tpig[[thread_position_in_grid]]) { - - const int64_t i = 2*tpig[0]; - - dst[i+0] = src0[i+0]; - dst[i+1] = src0[i+1]; - int64_t i4 = 4*i; - const int64_t i02 = i4/(args.ne00*args.ne01); i4 -= i02*args.ne00*args.ne01; - const int64_t i01 = i4/(args.ne00); i4 -= i01*args.ne00; - const int64_t i00 = i4; - for (int k = 3; k >= 0; --k) { - if (i00 + 4 + k <= args.n_past + i01) { - break; - } - dst[i+1][k] = -INFINITY; - if (i00 + k > args.n_past + i01) { - dst[i][k] = -INFINITY; - } - } -} - // ref: ggml.c:ggml_compute_forward_ssm_conv_f32 -kernel void kernel_ssm_conv_f32( +kernel void kernel_ssm_conv_f32_f32( + constant ggml_metal_kargs_ssm_conv & args, device const void * src0, device const void * src1, device float * dst, - constant ggml_metal_kargs_ssm_conv & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], uint3 ntg[[threads_per_threadgroup]]) { @@ -1647,6 +2034,7 @@ kernel void kernel_ssm_conv_f32( // ref: ggml.c:ggml_compute_forward_ssm_scan_f32, Mamba-1 part kernel void kernel_ssm_scan_f32( + constant ggml_metal_kargs_ssm_scan & args, device const void * src0, device const void * src1, device const void * src2, @@ -1655,10 +2043,15 @@ kernel void kernel_ssm_scan_f32( device const void * src5, device const void * src6, device float * dst, - constant ggml_metal_kargs_ssm_scan & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]) { + threadgroup float * shared [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgptg[[simdgroups_per_threadgroup]], + uint3 tgpg[[threadgroups_per_grid]]) { + + const int64_t i0 = tpitg.x; const int64_t i1 = 0; const int64_t ir = tgpig.x; // current head const int64_t i3 = tgpig.y; // current seq @@ -1673,42 +2066,91 @@ kernel void kernel_ssm_scan_f32( const int64_t ng = args.n_group; const int64_t n_t = args.n_seq_tokens; - const int64_t s_off = nr * nh * n_t * args.n_seqs * sizeof(float); + const int64_t s_off = args.s_off; device const int32_t * ids = (device const int32_t *) src6; - device const float * s0 = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); - device float * s = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + device const float * s0_buff = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); + device float * s_buff = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + const int64_t i = i0 + i1*nc; + const int64_t g = ir / (nh / ng); // repeat_interleave + float s0 = s0_buff[i]; + float s = s_buff[i]; + + device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); + device const float * x_block = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i3*args.nb13); + device const float * dt_block = (device const float *) ((device const char *) src2 + ir*nb20 + i3*args.nb22); + device const float * B_block = (device const float *) ((device const char *) src4 + g*args.nb41 + i3*args.nb43); + device const float * C_block = (device const float *) ((device const char *) src5 + g*args.nb51 + i3*args.nb53); + device float * y_block = (device float *) ((device char *) dst + (i1 + ir*(nr) + i3*(n_t*nh*nr))*nb00); for (int64_t i2 = 0; i2 < n_t; ++i2) { - device const float * x = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i2*args.nb12 + i3*args.nb13); // {dim, nh, nt, ns} - device const float * dt = (device const float *) ((device const char *) src2 + ir*nb20 + i2*args.nb21 + i3*args.nb22); // {nh, nt, ns} - device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {d_state, nh} - device const float * B = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i2*args.nb42 + i3*args.nb43); // {d_state, ng, nt, ns} - device const float * C = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i2*args.nb52 + i3*args.nb53); // {d_state, ng, nt, ns} - device float * y = (device float *) ((device char *) dst + (i1 + ir*(nr) + i2*(nh*nr) + i3*(n_t*nh*nr))*nb00); // {dim, nh, nt, ns} + device const float * x = (device const float *) ((device const char *) x_block + i2*args.nb12); // {dim, nh, nt, ns} + device const float * dt = (device const float *) ((device const char *) dt_block + i2*args.nb21); // {nh, nt, ns} + device const float * B = (device const float *) ((device const char *) B_block + i2*args.nb42); // {d_state, ng, nt, ns} + device const float * C = (device const float *) ((device const char *) C_block + i2*args.nb52); // {d_state, ng, nt, ns} + device float * y = (device float *) ((device char *) y_block + i2*(nh*nr*nb00)); // {dim, nh, nt, ns} const float dt_soft_plus = dt[0] <= 20.0f ? log(1.0f + exp(dt[0])) : dt[0]; const float x_dt = x[0] * dt_soft_plus; - float sumf = 0.0f; - for (int64_t i0 = 0; i0 < nc; ++i0) { - const int64_t i = i0 + i1*nc; - const float state = (s0[i] * exp(dt_soft_plus * A[i0])) + (B[i0] * x_dt); - sumf += state * C[i0]; - s[i] = state; - } + const float state = (s0 * exp(dt_soft_plus * A[i0])) + (B[i0] * x_dt); + s = state; + + // Parallel sum: This relies on the fact that this kernel will be + // dispatched with each threadgroup having (d_state, 1, 1) threads which + // are subdivided into SIMD groups of size `sgptg`. The goal is to + // compute y = sum({state * C[i] for i in range(d_state)}). + // To parallelize this effectively, we first use simd_sum over each SIMD + // group to compute the sum of each SIMD group, then place the result in + // the SIMD group's indexed bucket in the shared memory. We then sum + // over the individual group sums to compute the final sum. + + // Computed for each thread + float sumf = state * C[i0]; + + // Sum the threads in the simd group => simd sum + sumf = simd_sum(sumf); + + if (sgptg > 1) { + + // Once per simd group, place the group sum into the shared buffer + if (tiisg == 0) { + shared[sgitg] = sumf; + } + + // Wait for all threads in the threadgroup to reach this point. This + // ensures that all elements of the shared buffer are populated with the + // sum of the individual simd groups. + threadgroup_barrier(mem_flags::mem_threadgroup); - y[0] = sumf; + // For simd group 0 at indices < num simd groups, extract the shared + // simd sum + sumf = 0.0f; + if (sgitg == 0) { + if (tiisg < sgptg) { + sumf = shared[tiisg]; + } + sumf = simd_sum(sumf); + if (tiisg == 0) { + y[0] = sumf; + } + } + } else if (tiisg == 0) { + y[0] = sumf; + } // recurse s0 = s; } + + // Assign the final state to the output buffer + s_buff[i] = s; } // ref: ggml.c:ggml_compute_forward_ssm_scan_f32, Mamba-2 part -// TODO: optimize (e.g. by parallelizing over d_state) -kernel void kernel_ssm_scan_f32_group( +kernel void kernel_ssm_scan_group_f32( + constant ggml_metal_kargs_ssm_scan & args, device const void * src0, device const void * src1, device const void * src2, @@ -1717,10 +2159,15 @@ kernel void kernel_ssm_scan_f32_group( device const void * src5, device const void * src6, device float * dst, - constant ggml_metal_kargs_ssm_scan & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]) { + threadgroup float * shared [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + uint3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgptg[[simdgroups_per_threadgroup]], + uint3 tgpg[[threadgroups_per_grid]]) { + + const int64_t i0 = tpitg.x; const int64_t i1 = tgpig.x; const int64_t ir = tgpig.y; // current head const int64_t i3 = tgpig.z; // current seq @@ -1735,38 +2182,82 @@ kernel void kernel_ssm_scan_f32_group( const int64_t ng = args.n_group; const int64_t n_t = args.n_seq_tokens; - const int64_t s_off = nr * nh * n_t * args.n_seqs * sizeof(float); + const int64_t s_off = args.s_off; device const int32_t * ids = (device const int32_t *) src6; - device const float * s0 = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); - device float * s = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + device const float * s0_buff = (device const float *) ((device const char *) src0 + ir*args.nb02 + ids[i3]*args.nb03); + device float * s_buff = (device float *) ((device char *) dst + ir*args.nb02 + i3*args.nb03 + s_off); + const int64_t i = i0 + i1*nc; + const int64_t g = ir / (nh / ng); // repeat_interleave + float s0 = s0_buff[i]; + float s = s_buff[i]; + + device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {1, nh} + device const float * x_block = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i3*args.nb13); + device const float * dt_block = (device const float *) ((device const char *) src2 + ir*nb20 + i3*args.nb22); + device const float * B_block = (device const float *) ((device const char *) src4 + g*args.nb41 + i3*args.nb43); + device const float * C_block = (device const float *) ((device const char *) src5 + g*args.nb51 + i3*args.nb53); + device float * y_block = (device float *) ((device char *) dst + (i1 + ir*(nr) + i3*(n_t*nh*nr))*nb00); for (int64_t i2 = 0; i2 < n_t; ++i2) { - device const float * x = (device const float *) ((device const char *) src1 + i1*nb10 + ir*args.nb11 + i2*args.nb12 + i3*args.nb13); // {dim, nh, nt, ns} - device const float * dt = (device const float *) ((device const char *) src2 + ir*nb20 + i2*args.nb21 + i3*args.nb22); // {nh, nt, ns} - device const float * A = (device const float *) ((device const char *) src3 + ir*args.nb31); // {1, nh} - device const float * B = (device const float *) ((device const char *) src4 + (ir & (ng - 1))*args.nb41 + i2*args.nb42 + i3*args.nb43); // {d_state, ng, nt, ns} - device const float * C = (device const float *) ((device const char *) src5 + (ir & (ng - 1))*args.nb51 + i2*args.nb52 + i3*args.nb53); // {d_state, ng, nt, ns} - device float * y = (device float *) ((device char *) dst + (i1 + ir*(nr) + i2*(nh*nr) + i3*(n_t*nh*nr))*nb00); // {dim, nh, nt, ns} + device const float * x = (device const float *) ((device const char *) x_block + i2*args.nb12); // {dim, nh, nt, ns} + device const float * dt = (device const float *) ((device const char *) dt_block + i2*args.nb21); // {nh, nt, ns} + device const float * B = (device const float *) ((device const char *) B_block + i2*args.nb42); // {d_state, ng, nt, ns} + device const float * C = (device const float *) ((device const char *) C_block + i2*args.nb52); // {d_state, ng, nt, ns} + device float * y = (device float *) ((device char *) y_block + i2*(nh*nr*nb00)); // {dim, nh, nt, ns} const float dt_soft_plus = dt[0] <= 20.0f ? log(1.0f + exp(dt[0])) : dt[0]; const float x_dt = x[0] * dt_soft_plus; const float dA = exp(dt_soft_plus * A[0]); - float sumf = 0.0f; - for (int64_t i0 = 0; i0 < nc; ++i0) { - const int64_t i = i0 + i1*nc; - const float state = (s0[i] * dA) + (B[i0] * x_dt); - sumf += state * C[i0]; - s[i] = state; + const float state = (s0 * dA) + (B[i0] * x_dt); + s = state; + + // Parallel sum: This relies on the fact that this kernel will be + // dispatched with each threadgroup having (d_state, 1, 1) threads which + // are subdivided into SIMD groups of size `sgptg`. The goal is to + // compute y = sum({state * C[i] for i in range(d_state)}). + // To parallelize this effectively, we first use simd_sum over each SIMD + // group to compute the sum of each SIMD group, then place the result in + // the SIMD group's indexed bucket in the shared memory. We then sum + // over the individual group sums to compute the final sum. + + // Computed for each thread + float sumf = state * C[i0]; + + // Sum the threads in the simd group => simd sum + sumf = simd_sum(sumf); + + // Once per simd group, place the group sum into the shared buffer + if (tiisg == 0) { + shared[sgitg] = sumf; } - y[0] = sumf; + // Wait for all threads in the threadgroup to reach this point. This + // ensures that all elements of the shared buffer are populated with the + // sum of the individual simd groups. + threadgroup_barrier(mem_flags::mem_threadgroup); + + // For simd group 0 at indices < num simd groups, extract the shared + // simd sum + sumf = 0.0f; + if (sgitg == 0) { + if (tiisg < sgptg) { + sumf = shared[tiisg]; + } + sumf = simd_sum(sumf); + if (tiisg == 0) { + y[0] = sumf; + } + } // recurse s0 = s; } + + // Assign the final state to the output buffer + s_buff[i] = s; } kernel void kernel_rwkv_wkv6_f32( @@ -1947,24 +2438,22 @@ kernel void kernel_rwkv_wkv7_f32( } } -kernel void kernel_argmax( - device const void * x, - device int32_t * dst, - constant int64_t & ncols, - constant uint64_t & nb01, - threadgroup float * shared_maxval [[threadgroup(0)]], - threadgroup int32_t * shared_argmax [[threadgroup(1)]], +kernel void kernel_argmax_f32( + constant ggml_metal_kargs_argmax & args, + device const char * src0, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], uint sgitg[[simdgroup_index_in_threadgroup]], uint tiisg[[thread_index_in_simdgroup]], uint ntg[[threads_per_threadgroup]]) { - device const float * x_row = (device const float *) ((device const char *) x + tgpig * nb01); + device const float * x_row = (device const float *) ((device const char *) src0 + tgpig * args.nb01); float lmax = -INFINITY; int32_t larg = -1; - for (int i00 = tpitg; i00 < ncols; i00 += ntg) { + for (int i00 = tpitg; i00 < args.ne00; i00 += ntg) { if (x_row[i00] > lmax) { lmax = x_row[i00]; larg = i00; @@ -1975,6 +2464,11 @@ kernel void kernel_argmax( float max_val = simd_max(lmax); int32_t arg_val = simd_max(select(-1, larg, lmax == max_val)); + device int32_t * dst_i32 = (device int32_t *) dst; + + threadgroup float * shared_maxval = (threadgroup float *) shmem; + threadgroup int32_t * shared_argmax = (threadgroup int32_t *) shmem + N_SIMDWIDTH; + if (ntg > N_SIMDWIDTH) { if (sgitg == 0) { shared_maxval[tiisg] = -INFINITY; @@ -1996,38 +2490,51 @@ kernel void kernel_argmax( float max_val_reduced = simd_max(max_val); int32_t arg_val_reduced = simd_max(select(-1, arg_val, max_val == max_val_reduced)); - dst[tgpig] = arg_val_reduced; + dst_i32[tgpig] = arg_val_reduced; return; } - dst[tgpig] = arg_val; + dst_i32[tgpig] = arg_val; } -kernel void kernel_norm( +// F == 1 : norm (no fuse) +// F == 2 : norm + mul +// F == 3 : norm + mul + add +template +kernel void kernel_norm_fuse_impl( constant ggml_metal_kargs_norm & args, device const char * src0, + device const char * src1_0, + device const char * src1_1, device char * dst, threadgroup float * shmem_f32 [[threadgroup(0)]], - uint tgpig[[threadgroup_position_in_grid]], - ushort tpitg[[thread_position_in_threadgroup]], - ushort sgitg[[simdgroup_index_in_threadgroup]], - ushort tiisg[[thread_index_in_simdgroup]], - ushort ntg[[threads_per_threadgroup]]) { + uint3 tgpig[[threadgroup_position_in_grid]], + ushort3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { if (sgitg == 0) { shmem_f32[tiisg] = 0.0f; } - device const float4 * x = (device const float4 *) (src0 + tgpig*args.nb01); + const int i01 = tgpig.x; + const int i02 = tgpig.y; + const int i03 = tgpig.z; - float4 sumf4(0.0f); + device const T * x = (device const T *) (src0 + i03*args.nbf3[0] + i02*args.nbf2[0] + i01*args.nbf1[0]); + + device const T * f0 = (device const T *) (src1_0 + (i03%args.nef3[1])*args.nbf3[1] + (i02%args.nef2[1])*args.nbf2[1] + (i01%args.nef1[1])*args.nbf1[1]); + device const T * f1 = (device const T *) (src1_1 + (i03%args.nef3[2])*args.nbf3[2] + (i02%args.nef2[2])*args.nbf2[2] + (i01%args.nef1[2])*args.nbf1[2]); + + T sumft(0.0f); float sumf = 0.0f; - for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) { - sumf4 += x[i00]; + for (int i00 = tpitg.x; i00 < args.ne00_t; i00 += ntg.x) { + sumft += x[i00]; } - sumf = sumf4[0] + sumf4[1] + sumf4[2] + sumf4[3]; + sumf = dot(sumft, T(1.0f)); sumf = simd_sum(sumf); threadgroup_barrier(mem_flags::mem_threadgroup); @@ -2043,10 +2550,10 @@ kernel void kernel_norm( const float mean = sumf/args.ne00; - device float4 * y = (device float4 *) dst + tgpig*args.ne00_4; + device T * y = (device T *) (dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1); sumf = 0.0f; - for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) { + for (int i00 = tpitg.x; i00 < args.ne00_t; i00 += ntg.x) { y[i00] = x[i00] - mean; sumf += dot(y[i00], y[i00]); } @@ -2066,31 +2573,62 @@ kernel void kernel_norm( const float variance = sumf/args.ne00; const float scale = 1.0f/sqrt(variance + args.eps); - for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) { - y[i00] = y[i00] * scale; + for (int i00 = tpitg.x; i00 < args.ne00_t; i00 += ntg.x) { + if (F == 1) { + y[i00] = (y[i00]*scale); + } + if (F == 2) { + y[i00] = (y[i00]*scale)*f0[i00]; + } + if (F == 3) { + y[i00] = (y[i00]*scale)*f0[i00] + f1[i00]; + } } } -kernel void kernel_rms_norm( - constant ggml_metal_kargs_rms_norm & args, +typedef decltype(kernel_norm_fuse_impl) kernel_norm_fuse_t; + +template [[host_name("kernel_norm_f32")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; +template [[host_name("kernel_norm_mul_f32")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; +template [[host_name("kernel_norm_mul_add_f32")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; + +template [[host_name("kernel_norm_f32_4")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; +template [[host_name("kernel_norm_mul_f32_4")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; +template [[host_name("kernel_norm_mul_add_f32_4")]] kernel kernel_norm_fuse_t kernel_norm_fuse_impl; + +// F == 1 : rms_norm (no fuse) +// F == 2 : rms_norm + mul +// F == 3 : rms_norm + mul + add +template +kernel void kernel_rms_norm_fuse_impl( + constant ggml_metal_kargs_norm & args, device const char * src0, + device const char * src1_0, + device const char * src1_1, device char * dst, threadgroup float * shmem_f32 [[threadgroup(0)]], - uint tgpig[[threadgroup_position_in_grid]], - ushort tpitg[[thread_position_in_threadgroup]], - ushort sgitg[[simdgroup_index_in_threadgroup]], - ushort tiisg[[thread_index_in_simdgroup]], - ushort ntg[[threads_per_threadgroup]]) { + uint3 tgpig[[threadgroup_position_in_grid]], + ushort3 tpitg[[thread_position_in_threadgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort3 ntg[[threads_per_threadgroup]]) { if (sgitg == 0) { shmem_f32[tiisg] = 0.0f; } - device const float4 * x = (device const float4 *) (src0 + tgpig*args.nb01); + const int i01 = tgpig.x; + const int i02 = tgpig.y; + const int i03 = tgpig.z; + + device const T * x = (device const T *) (src0 + i03*args.nbf3[0] + i02*args.nbf2[0] + i01*args.nbf1[0]); + + device const T * f0 = (device const T *) (src1_0 + (i03%args.nef3[1])*args.nbf3[1] + (i02%args.nef2[1])*args.nbf2[1] + (i01%args.nef1[1])*args.nbf1[1]); + device const T * f1 = (device const T *) (src1_1 + (i03%args.nef3[2])*args.nbf3[2] + (i02%args.nef2[2])*args.nbf2[2] + (i01%args.nef1[2])*args.nbf1[2]); float sumf = 0.0f; // parallel sum - for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) { + for (int i00 = tpitg.x; i00 < args.ne00_t; i00 += ntg.x) { sumf += dot(x[i00], x[i00]); } sumf = simd_sum(sumf); @@ -2109,13 +2647,31 @@ kernel void kernel_rms_norm( const float mean = sumf/args.ne00; const float scale = 1.0f/sqrt(mean + args.eps); - device float4 * y = (device float4 *) dst + tgpig*args.ne00_4; - for (int i00 = tpitg; i00 < args.ne00_4; i00 += ntg) { - y[i00] = x[i00] * scale; + device T * y = (device T *) (dst + i03*args.nb3 + i02*args.nb2 + i01*args.nb1); + for (int i00 = tpitg.x; i00 < args.ne00_t; i00 += ntg.x) { + if (F == 1) { + y[i00] = (x[i00]*scale); + } + if (F == 2) { + y[i00] = (x[i00]*scale)*f0[i00]; + } + if (F == 3) { + y[i00] = (x[i00]*scale)*f0[i00] + f1[i00]; + } } } -kernel void kernel_l2_norm( +typedef decltype(kernel_rms_norm_fuse_impl) kernel_rms_norm_fuse_t; + +template [[host_name("kernel_rms_norm_f32")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; +template [[host_name("kernel_rms_norm_mul_f32")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; +template [[host_name("kernel_rms_norm_mul_add_f32")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; + +template [[host_name("kernel_rms_norm_f32_4")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; +template [[host_name("kernel_rms_norm_mul_f32_4")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; +template [[host_name("kernel_rms_norm_mul_add_f32_4")]] kernel kernel_rms_norm_fuse_t kernel_rms_norm_fuse_impl; + +kernel void kernel_l2_norm_f32( constant ggml_metal_kargs_l2_norm & args, device const char * src0, device char * dst, @@ -2158,10 +2714,10 @@ kernel void kernel_l2_norm( } } -kernel void kernel_group_norm( +kernel void kernel_group_norm_f32( + constant ggml_metal_kargs_group_norm & args, device const float * src0, device float * dst, - constant ggml_metal_kargs_group_norm & args, threadgroup float * buf [[threadgroup(0)]], uint tgpig[[threadgroup_position_in_grid]], uint tpitg[[thread_position_in_threadgroup]], @@ -2169,7 +2725,7 @@ kernel void kernel_group_norm( uint tiisg[[thread_index_in_simdgroup]], uint ntg[[threads_per_threadgroup]]) { const int64_t ne = args.ne00*args.ne01*args.ne02; - const int64_t gs = args.ne00*args.ne01*((args.ne02 + args.n_groups - 1) / args.n_groups); + const int64_t gs = args.ne00*args.ne01*((args.ne02 + args.ngrp - 1) / args.ngrp); int start = tgpig * gs; int end = start + gs; @@ -2327,7 +2883,52 @@ inline float block_q_n_dot_y(device cons return d * (acc[0] + acc[1] + acc[2] + acc[3]) + sumy * m; } -template +template +static inline void helper_mv_reduce_and_write( + device float * dst_f32, + float sumf[NR0], + const int r0, + const int ne01, + ushort tiisg, + ushort sgitg, + threadgroup char * shmem) { + constexpr short NW = N_SIMDWIDTH; + + threadgroup float * shmem_f32[NR0]; + + for (short row = 0; row < NR0; ++row) { + shmem_f32[row] = (threadgroup float *) shmem + NW*row; + + if (sgitg == 0) { + shmem_f32[row][tiisg] = 0.0f; + } + + sumf[row] = simd_sum(sumf[row]); + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + for (short row = 0; row < NR0; ++row) { + if (tiisg == 0) { + shmem_f32[row][sgitg] = sumf[row]; + } + } + + threadgroup_barrier(mem_flags::mem_threadgroup); + + for (short row = 0; row < NR0 && r0 + row < ne01; ++row) { + float tot = simd_sum(shmem_f32[row][tiisg]); + + if (tiisg == 0 && sgitg == 0) { + dst_f32[r0 + row] = tot; + } + } +} + +constant short FC_mul_mv_nsg [[function_constant(FC_MUL_MV + 0)]]; +constant short FC_mul_mv_nxpsg [[function_constant(FC_MUL_MV + 1)]]; + +template void mul_vec_q_n_f32_impl( args_t args, device const char * src0, @@ -2337,45 +2938,54 @@ void mul_vec_q_n_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { - const int nb = args.ne00/QK4_0; + const short NSG = FC_mul_mv_nsg; - const int r0 = tgpig.x; - const int r1 = tgpig.y; - const int im = tgpig.z; + constexpr short NW = N_SIMDWIDTH; + constexpr short NQ = 16; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int nb = args.ne00/QK4_0; + + const int r0 = (tgpig.x*NSG + sgitg)*NR0; + //const int r0 = tgpig.x*NR0; + const int r1 = tgpig.y; + const int im = tgpig.z; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; - //const uint64_t offset0 = first_row*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + //const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; //device const block_q_type * x = (device const block_q_type *) (src0 + offset0); device const float * y = (device const float *) (src1 + offset1); // pointers to src0 rows - device const block_q_type * ax[nr0]; - for (int row = 0; row < nr0; ++row) { - const uint64_t offset0 = (first_row + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + device const block_q_type * ax[NR0]; + FOR_UNROLL (int row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; ax[row] = (device const block_q_type *) ((device char *) src0 + offset0); } - float yl[16]; // src1 vector cache - float sumf[nr0] = {0.f}; + float sumf[NR0] = {0.f}; + + const short ix = (tiisg/(NW/NQ)); + const short il = (tiisg%(NW/NQ))*8; + + //const int ib0 = sgitg*NQ + ix; + const int ib0 = ix; - const short ix = (tiisg/2); - const short il = (tiisg%2)*8; + float yl[16]; // src1 vector cache - device const float * yb = y + ix*QK4_0 + il; + //device const float * yb = y + ix*QK4_0 + il; + device const float * yb = y + ib0*QK4_0 + il; // each thread in a SIMD group deals with half a block. - for (int ib = ix; ib < nb; ib += nw/2) { + //for (int ib = ib0; ib < nb; ib += NSG*NQ) { + for (int ib = ib0; ib < nb; ib += NQ) { float sumy[2] = { 0.f, 0.f }; -#pragma unroll - for (short i = 0; i < 8; i += 2) { + FOR_UNROLL (short i = 0; i < 8; i += 2) { sumy[0] += yb[i + 0] + yb[i + 1]; yl[i + 0] = yb[i + 0]; yl[i + 1] = yb[i + 1]/256.f; @@ -2385,21 +2995,23 @@ void mul_vec_q_n_f32_impl( yl[i + 9] = yb[i + 17]/4096.f; } -#pragma unroll - for (short row = 0; row < nr0; row++) { + FOR_UNROLL (short row = 0; row < NR0; row++) { sumf[row] += block_q_n_dot_y(ax[row] + ib, sumy[0] + sumy[1], yl, il); } yb += QK4_0 * 16; + //yb += NSG*NQ*QK4_0; } device float * dst_f32 = (device float *) dst + im*args.ne0*args.ne1 + r1*args.ne0; - for (int row = 0; row < nr0; ++row) { + //helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); + + for (int row = 0; row < NR0; ++row) { const float tot = simd_sum(sumf[row]); - if (tiisg == 0 && first_row + row < args.ne01) { - dst_f32[first_row + row] = tot; + if (tiisg == 0 && r0 + row < args.ne01) { + dst_f32[r0 + row] = tot; } } } @@ -2409,10 +3021,11 @@ kernel void kernel_mul_mv_q4_0_f32( device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - mul_vec_q_n_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + mul_vec_q_n_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } kernel void kernel_mul_mv_q4_1_f32( @@ -2420,10 +3033,11 @@ kernel void kernel_mul_mv_q4_1_f32( device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - mul_vec_q_n_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + mul_vec_q_n_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } kernel void kernel_mul_mv_q5_0_f32( @@ -2431,10 +3045,11 @@ kernel void kernel_mul_mv_q5_0_f32( device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - mul_vec_q_n_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + mul_vec_q_n_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } kernel void kernel_mul_mv_q5_1_f32( @@ -2442,15 +3057,14 @@ kernel void kernel_mul_mv_q5_1_f32( device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - mul_vec_q_n_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + mul_vec_q_n_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -#define NB_Q8_0 8 - -template +template void kernel_mul_mv_q8_0_f32_impl( args_t args, device const char * src0, @@ -2460,66 +3074,68 @@ void kernel_mul_mv_q8_0_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + constexpr short NW = N_SIMDWIDTH; + constexpr short NQ = 8; + const int nb = args.ne00/QK8_0; - const int r0 = tgpig.x; + const int r0 = tgpig.x*NR0; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; - const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; - //const uint64_t offset0 = first_row*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + //const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; //device const block_q8_0 * x = (device const block_q8_0 *) (src0 + offset0); device const float * y = (device const float *) (src1 + offset1); // pointers to src0 rows - device const block_q8_0 * ax[nr0]; - for (int row = 0; row < nr0; ++row) { - const uint64_t offset0 = (first_row + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + device const block_q8_0 * ax[NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; ax[row] = (device const block_q8_0 *) ((device char *) src0 + offset0); } - float yl[NB_Q8_0]; - float sumf[nr0] = { 0.f }; + float sumf[NR0] = { 0.f }; + + const short ix = tiisg/(NW/NQ); + const short il = tiisg%(NW/NQ); - const short ix = tiisg/4; - const short il = tiisg%4; + const int ib0 = sgitg*NQ + ix; - device const float * yb = y + ix*QK8_0 + il*NB_Q8_0; + float yl[NQ]; - // each thread in a SIMD group deals with NB_Q8_0 quants at a time - for (int ib = ix; ib < nb; ib += nw/4) { - for (short i = 0; i < NB_Q8_0; ++i) { + device const float * yb = y + ib0*QK8_0 + il*NQ; + + // each thread in a SIMD group deals with NQ quants at a time + for (int ib = ib0; ib < nb; ib += NSG*NQ) { + for (short i = 0; i < NQ; ++i) { yl[i] = yb[i]; } - for (short row = 0; row < nr0; row++) { - device const int8_t * qs = ax[row][ib].qs + il*NB_Q8_0; + for (short row = 0; row < NR0; row++) { + device const int8_t * qs = ax[row][ib].qs + il*NQ; + float sumq = 0.f; - for (short iq = 0; iq < NB_Q8_0; ++iq) { - sumq += qs[iq] * yl[iq]; + FOR_UNROLL (short i = 0; i < NQ; ++i) { + sumq += qs[i] * yl[i]; } + sumf[row] += sumq*ax[row][ib].d; } - yb += nw*NB_Q8_0; + yb += NSG*NQ*QK8_0; } device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; - for (int row = 0; row < nr0; ++row) { - const float tot = simd_sum(sumf[row]); - - if (tiisg == 0 && first_row + row < args.ne01) { - dst_f32[first_row + row] = tot; - } - } + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); } [[host_name("kernel_mul_mv_q8_0_f32")]] @@ -2528,15 +3144,16 @@ kernel void kernel_mul_mv_q8_0_f32( device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q8_0_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q8_0_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } // mat-vec kernel processing in chunks of float4 // chpb - chunks per quantization block -template +template void kernel_mul_mv_ext_q4_f32_impl( constant ggml_metal_kargs_mul_mv_ext & args, device const char * src0, @@ -2545,6 +3162,9 @@ void kernel_mul_mv_ext_q4_f32_impl( uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { + const short NSG = FC_mul_mv_nsg; + const short nxpsg = FC_mul_mv_nxpsg; + const short chpt = 4; // chunks per thread //const short nxpsg = (32); @@ -2553,7 +3173,7 @@ void kernel_mul_mv_ext_q4_f32_impl( const short tx = tiisg%nxpsg; const short ty = tiisg/nxpsg; - const int i01 = tgpig.x*(nypsg*args.nsg) + nypsg*sgitg + ty; + const int i01 = tgpig.x*(nypsg*NSG) + nypsg*sgitg + ty; const int i11 = tgpig.y*r1ptg; const int i1m = tgpig.z; @@ -2594,7 +3214,6 @@ void kernel_mul_mv_ext_q4_f32_impl( #pragma unroll(r1ptg) for (short ir1 = 0; ir1 < r1ptg; ++ir1) { sumf[ir1] += dot(lx[ch], y4[ir1][ch*nxpsg]); - } } @@ -2637,7 +3256,7 @@ void kernel_mul_mv_ext_q4_f32_impl( } // mat-vec kernel processing in chunks of float4x4 -template +template void kernel_mul_mv_ext_q4x4_f32_impl( constant ggml_metal_kargs_mul_mv_ext & args, device const char * src0, @@ -2646,6 +3265,9 @@ void kernel_mul_mv_ext_q4x4_f32_impl( uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { + const short NSG = FC_mul_mv_nsg; + const short nxpsg = FC_mul_mv_nxpsg; + const short chpt = 1; //const short nxpsg = (32); @@ -2654,7 +3276,7 @@ void kernel_mul_mv_ext_q4x4_f32_impl( const short tx = tiisg%nxpsg; const short ty = tiisg/nxpsg; - const int i01 = tgpig.x*(nypsg*args.nsg) + nypsg*sgitg + ty; + const int i01 = tgpig.x*(nypsg*NSG) + nypsg*sgitg + ty; const int i11 = tgpig.y*r1ptg; const int i1m = tgpig.z; @@ -2751,12 +3373,7 @@ kernel void kernel_mul_mv_ext_q4_f32_dis uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - switch (args.nxpsg) { - case 4: kernel_mul_mv_ext_q4_f32_impl<4, r1ptg, q_t, epb/4, deq_t4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 8: kernel_mul_mv_ext_q4_f32_impl<8, r1ptg, q_t, epb/4, deq_t4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 16: kernel_mul_mv_ext_q4_f32_impl<16, r1ptg, q_t, epb/4, deq_t4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 32: kernel_mul_mv_ext_q4_f32_impl<32, r1ptg, q_t, epb/4, deq_t4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - } + kernel_mul_mv_ext_q4_f32_impl(args, src0, src1, dst, tgpig, tiisg, sgitg); } template @@ -2768,17 +3385,17 @@ kernel void kernel_mul_mv_ext_q4x4_f32_d uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - switch (args.nxpsg) { - case 4: kernel_mul_mv_ext_q4x4_f32_impl<4, r1ptg, q_t, epb/16, deq_t4x4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 8: kernel_mul_mv_ext_q4x4_f32_impl<8, r1ptg, q_t, epb/16, deq_t4x4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 16: kernel_mul_mv_ext_q4x4_f32_impl<16, r1ptg, q_t, epb/16, deq_t4x4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - case 32: kernel_mul_mv_ext_q4x4_f32_impl<32, r1ptg, q_t, epb/16, deq_t4x4>(args, src0, src1, dst, tgpig, tiisg, sgitg); break; - } + kernel_mul_mv_ext_q4x4_f32_impl(args, src0, src1, dst, tgpig, tiisg, sgitg); } typedef decltype(kernel_mul_mv_ext_q4_f32_disp <2, block_q8_0, 32, dequantize_q8_0_t4>) mul_mv_ext_q4_f32_t; typedef decltype(kernel_mul_mv_ext_q4x4_f32_disp<2, block_q4_K, 256, dequantize_q4_K>) mul_mv_ext_q4x4_f32_t; +template [[host_name("kernel_mul_mv_ext_f32_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, float4, 4, dequantize_f32_t4>; +template [[host_name("kernel_mul_mv_ext_f32_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, float4, 4, dequantize_f32_t4>; +template [[host_name("kernel_mul_mv_ext_f32_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, float4, 4, dequantize_f32_t4>; +template [[host_name("kernel_mul_mv_ext_f32_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, float4, 4, dequantize_f32_t4>; + template [[host_name("kernel_mul_mv_ext_f16_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, half4, 4, dequantize_f16_t4>; template [[host_name("kernel_mul_mv_ext_f16_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, half4, 4, dequantize_f16_t4>; template [[host_name("kernel_mul_mv_ext_f16_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, half4, 4, dequantize_f16_t4>; @@ -2809,6 +3426,11 @@ template [[host_name("kernel_mul_mv_ext_ template [[host_name("kernel_mul_mv_ext_q8_0_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_q8_0, 32, dequantize_q8_0_t4>; template [[host_name("kernel_mul_mv_ext_q8_0_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_q8_0, 32, dequantize_q8_0_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_mxfp4, 32, dequantize_mxfp4_t4>; +template [[host_name("kernel_mul_mv_ext_mxfp4_f32_r1_5")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<5, block_mxfp4, 32, dequantize_mxfp4_t4>; + template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_2")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<2, block_iq4_nl, 32, dequantize_iq4_nl_t4>; template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_3")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<3, block_iq4_nl, 32, dequantize_iq4_nl_t4>; template [[host_name("kernel_mul_mv_ext_iq4_nl_f32_r1_4")]] kernel mul_mv_ext_q4_f32_t kernel_mul_mv_ext_q4_f32_disp<4, block_iq4_nl, 32, dequantize_iq4_nl_t4>; @@ -2829,104 +3451,217 @@ template [[host_name("kernel_mul_mv_ext_ template [[host_name("kernel_mul_mv_ext_q6_K_f32_r1_4")]] kernel mul_mv_ext_q4x4_f32_t kernel_mul_mv_ext_q4x4_f32_disp<4, block_q6_K, 256, dequantize_q6_K>; template [[host_name("kernel_mul_mv_ext_q6_K_f32_r1_5")]] kernel mul_mv_ext_q4x4_f32_t kernel_mul_mv_ext_q4x4_f32_disp<5, block_q6_K, 256, dequantize_q6_K>; -#define N_MV_T_T 4 - -template -void kernel_mul_mv_impl( +template +void kernel_mul_mv_t_t_impl( args_t args, device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem, uint3 tgpig, - ushort tiisg) { - const int r0 = tgpig.x; - const int rb = tgpig.y*N_MV_T_T; + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + constexpr short NW = N_SIMDWIDTH; + constexpr short NB = 32; + constexpr short NF = 8; + + const int nb = args.ne00/NB; + + const int r0 = tgpig.x*NR0; + const int r1 = tgpig.y; const int im = tgpig.z; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; - const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + //const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; - device const T0 * x = (device const T0 *) (src0 + offset0); + //device const T0 * x = (device const T0 *) (src0 + offset0); + device const T1 * y = (device const T1 *) (src1 + offset1); - device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1; + // pointers to src0 rows + device const T0 * ax [NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; - if (args.ne00 < 128) { - for (int row = 0; row < N_MV_T_T; ++row) { - int r1 = rb + row; - if (r1 >= args.ne11) { - break; - } + ax[row] = (device const T0 *) ((device char *) src0 + offset0); + } - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + float sumf[NR0] = { 0.f }; - device const T1 * y = (device const T1 *) (src1 + offset1); + const short ix = tiisg/(NW/NF); + const short il = tiisg%(NW/NF); - float sumf = 0; - for (int i = tiisg; i < args.ne00; i += 32) { - sumf += (T0) x[i] * (T1) y[i]; - } + const int ib0 = sgitg*NF + ix; - float sum_all = simd_sum(sumf); - if (tiisg == 0) { - dst_f32[(uint64_t)r1*args.ne0 + r0] = sum_all; - } + T1 yl[NF]; + + device const T1 * yb = y + (ib0*NB + il*NF); + + for (int ib = ib0; ib < nb; ib += NSG*NF) { + for (short i = 0; i < NF; ++i) { + yl[i] = yb[i]; } - } else { - device const T04 * x4 = (device const T04 *) x; - for (int row = 0; row < N_MV_T_T; ++row) { - int r1 = rb + row; - if (r1 >= args.ne11) { - break; + + for (short row = 0; row < NR0; row++) { + device const T0 * xb = ax[row] + (ib*NB + il*NF); + + float sumq = 0.f; + FOR_UNROLL (short i = 0; i < NF; ++i) { + sumq += xb[i] * yl[i]; } - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + sumf[row] += sumq; + } - device const T1 * y = (device const T1 *) (src1 + offset1); - device const T14 * y4 = (device const T14 *) y; + yb += NSG*NF*NW; + } - float sumf = 0; - for (int i = tiisg; i < args.ne00/4; i += 32) { - sumf += dot((float4) x4[i], (float4) y4[i]); - } + for (int i = nb*NB + sgitg*NW + tiisg; i < args.ne00; i += NW*NSG) { + for (short row = 0; row < NR0; row++) { + sumf[row] += ax[row][i] * y[i]; + } + } - float sum_all = simd_sum(sumf); - if (tiisg == 0) { - for (int i = 4*(args.ne00/4); i < args.ne00; ++i) sum_all += (float) (x[i] * y[i]); - dst_f32[(uint64_t)r1*args.ne0 + r0] = sum_all; + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); +} + +template +kernel void kernel_mul_mv_t_t( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + kernel_mul_mv_t_t_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + +typedef decltype(kernel_mul_mv_t_t) mul_mv_t_t; + +template [[host_name("kernel_mul_mv_f32_f32")]] kernel mul_mv_t_t kernel_mul_mv_t_t; +template [[host_name("kernel_mul_mv_f16_f32")]] kernel mul_mv_t_t kernel_mul_mv_t_t; +template [[host_name("kernel_mul_mv_f16_f16")]] kernel mul_mv_t_t kernel_mul_mv_t_t; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mv_bf16_f32")]] kernel mul_mv_t_t kernel_mul_mv_t_t; +template [[host_name("kernel_mul_mv_bf16_bf16")]] kernel mul_mv_t_t kernel_mul_mv_t_t; +#endif + +template +void kernel_mul_mv_t_t_4_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + constexpr short NW = N_SIMDWIDTH; + constexpr short NB = 32; + constexpr short NF = 16; + constexpr short NF4 = NF/4; + + const int nb = args.ne00/NB; + + const int r0 = tgpig.x*NR0; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const uint i12 = im%args.ne12; + const uint i13 = im/args.ne12; + + //const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + + device const T1 * y = (device const T1 *) (src1 + offset1); + device const T14 * y4 = (device const T14 *) (src1 + offset1); + + // pointers to src0 rows + device const T0 * ax [NR0]; + device const T04 * ax4[NR0]; + FOR_UNROLL (short row = 0; row < NR0; ++row) { + const uint64_t offset0 = (r0 + row)*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + + ax [row] = (device const T0 *) ((device char *) src0 + offset0); + ax4[row] = (device const T04 *) ((device char *) src0 + offset0); + } + + float sumf[NR0] = { 0.f }; + + const short ix = tiisg/(NW/NF); + const short il = tiisg%(NW/NF); + + const int ib0 = sgitg*NF + ix; + + T14 yl4[NF4]; + + device const T14 * yb4 = y4 + (ib0*NB + il*NF)/4; + + for (int ib = ib0; ib < nb; ib += NSG*NF) { + for (short i = 0; i < NF4; ++i) { + yl4[i] = yb4[i]; + } + + for (short row = 0; row < NR0; row++) { + device const T04 * xb4 = ax4[row] + (ib*NB + il*NF)/4; + + float sumq = 0.f; + FOR_UNROLL (short i = 0; i < NF4; ++i) { + sumq += dot(float4(xb4[i]), float4(yl4[i])); } + + sumf[row] += sumq; + } + + yb4 += NSG*NF*NW/4; + } + + for (int i = nb*NB + sgitg*NW + tiisg; i < args.ne00; i += NW*NSG) { + for (short row = 0; row < NR0; row++) { + sumf[row] += ax[row][i] * y[i]; } } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + helper_mv_reduce_and_write(dst_f32, sumf, r0, args.ne01, tiisg, sgitg, shmem); } -template -kernel void kernel_mul_mv( +template +kernel void kernel_mul_mv_t_t_4( constant ggml_metal_kargs_mul_mv & args, device const char * src0, device const char * src1, device char * dst, + threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], - ushort tiisg[[thread_index_in_simdgroup]]) { - kernel_mul_mv_impl( - args, - src0, - src1, - dst, - tgpig, - tiisg); + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + kernel_mul_mv_t_t_4_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -typedef decltype(kernel_mul_mv) mul_mv_t; +typedef decltype(kernel_mul_mv_t_t_4) mul_mv_t_t_4; -template [[host_name("kernel_mul_mv_f32_f32")]] kernel mul_mv_t kernel_mul_mv; -template [[host_name("kernel_mul_mv_f16_f32")]] kernel mul_mv_t kernel_mul_mv; -template [[host_name("kernel_mul_mv_f16_f16")]] kernel mul_mv_t kernel_mul_mv; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mv_bf16_f32")]] kernel mul_mv_t kernel_mul_mv; -template [[host_name("kernel_mul_mv_bf16_bf16")]] kernel mul_mv_t kernel_mul_mv; +template [[host_name("kernel_mul_mv_f32_f32_4")]] kernel mul_mv_t_t_4 kernel_mul_mv_t_t_4; +template [[host_name("kernel_mul_mv_f16_f32_4")]] kernel mul_mv_t_t_4 kernel_mul_mv_t_t_4; +template [[host_name("kernel_mul_mv_f16_f16_4")]] kernel mul_mv_t_t_4 kernel_mul_mv_t_t_4; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mv_bf16_f32_4")]] kernel mul_mv_t_t_4 kernel_mul_mv_t_t_4; +template [[host_name("kernel_mul_mv_bf16_bf16_4")]] kernel mul_mv_t_t_4 kernel_mul_mv_t_t_4; #endif +#define N_MV_T_T 4 + template void kernel_mul_mv_c4_impl( args_t args, @@ -2987,112 +3722,10 @@ typedef decltype(kernel_mul_mv_c4; template [[host_name("kernel_mul_mv_f16_f32_c4")]] kernel mul_mv_c4_t kernel_mul_mv_c4; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mv_bf16_f32_c4")]] kernel mul_mv_c4_t kernel_mul_mv_c4; -#endif - -template -kernel void kernel_mul_mv_1row( - constant ggml_metal_kargs_mul_mv & args, - device const char * src0, - device const char * src1, - device char * dst, - uint3 tgpig[[threadgroup_position_in_grid]], - ushort tiisg[[thread_index_in_simdgroup]]) { - - const int r0 = tgpig.x; - const int r1 = tgpig.y; - const int im = tgpig.z; - - const uint i12 = im%args.ne12; - const uint i13 = im/args.ne12; - - const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; - - device const T * x = (device const T *) (src0 + offset0); - device const float * y = (device const float *) (src1 + offset1); - - device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; - - float sumf = 0; - if (args.ne00 < 128) { - for (int i = tiisg; i < args.ne00; i += 32) { - sumf += (float) x[i] * (float) y[i]; - } - float sum_all = simd_sum(sumf); - if (tiisg == 0) { - dst_f32[r0] = sum_all; - } - } else { - device const T4 * x4 = (device const T4 *) x; - device const float4 * y4 = (device const float4 *) y; - - for (int i = tiisg; i < args.ne00/4; i += 32) { - sumf += dot((float4) x4[i], y4[i]); - } - - float sum_all = simd_sum(sumf); - - if (tiisg == 0) { - for (int i = 4*(args.ne00/4); i < args.ne00; ++i) sum_all += (float) (x[i] * y[i]); - dst_f32[r0] = sum_all; - } - } -} - -typedef decltype(kernel_mul_mv_1row) mul_mv_1row_t; - -template [[host_name("kernel_mul_mv_f16_f32_1row")]] kernel mul_mv_1row_t kernel_mul_mv_1row; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mv_bf16_f32_1row")]] kernel mul_mv_1row_t kernel_mul_mv_1row; -#endif - -// Assumes row size (ne00) is a multiple of 4 -template -kernel void kernel_mul_mv_l4( - constant ggml_metal_kargs_mul_mv & args, - device const char * src0, - device const char * src1, - device char * dst, - uint3 tgpig[[threadgroup_position_in_grid]], - ushort tiisg[[thread_index_in_simdgroup]]) { - - const int nrows = args.ne11; - const int r0 = tgpig.x; - const int im = tgpig.z; - - const uint i12 = im%args.ne12; - const uint i13 = im/args.ne12; - - const uint64_t offset0 = r0*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; - - device const T4 * x4 = (device const T4 *) (src0 + offset0); - - device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1; - - for (int r1 = 0; r1 < nrows; ++r1) { - const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; - - device const float4 * y4 = (device const float4 *) (src1 + offset1); - - float sumf = 0; - for (int i = tiisg; i < args.ne00/4; i += 32) { - sumf += dot((float4) x4[i], y4[i]); - } - - float sum_all = simd_sum(sumf); - if (tiisg == 0) { - dst_f32[(uint64_t)r1*args.ne0 + r0] = sum_all; - } - } -} - -typedef decltype(kernel_mul_mv_l4) mul_mv_l4_t; - -template [[host_name("kernel_mul_mv_f16_f32_l4")]] kernel mul_mv_l4_t kernel_mul_mv_l4; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mv_bf16_f32_l4")]] kernel mul_mv_l4_t kernel_mul_mv_l4; +template [[host_name("kernel_mul_mv_f16_f16_c4")]] kernel mul_mv_c4_t kernel_mul_mv_c4; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mv_bf16_f32_c4")]] kernel mul_mv_c4_t kernel_mul_mv_c4; +template [[host_name("kernel_mul_mv_bf16_bf16_c4")]] kernel mul_mv_c4_t kernel_mul_mv_c4; #endif static float rope_yarn_ramp(const float low, const float high, const int i0) { @@ -3395,9 +4028,9 @@ template [[host_name("kernel_rope_vision template [[host_name("kernel_rope_vision_f16")]] kernel kernel_rope_vision_t kernel_rope_vision; typedef void (im2col_t)( + constant ggml_metal_kargs_im2col & args, device const float * x, device char * dst, - constant ggml_metal_kargs_im2col & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]], uint3 tpitg[[thread_position_in_threadgroup]], @@ -3405,9 +4038,9 @@ typedef void (im2col_t)( template kernel void kernel_im2col( + constant ggml_metal_kargs_im2col & args, device const float * x, device char * dst, - constant ggml_metal_kargs_im2col & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]], uint3 tpitg[[thread_position_in_threadgroup]], @@ -3416,11 +4049,10 @@ kernel void kernel_im2col( const int64_t OH = tgpg[1]; const int64_t OW = tgpg[2]; -// const int64_t N = ntg[0]; const int64_t KH = ntg[1]; const int64_t KW = ntg[2]; - const int64_t in = tpitg[0]; + int64_t in = tpitg[0]; const int64_t ikh = tpitg[1]; const int64_t ikw = tpitg[2]; @@ -3431,88 +4063,102 @@ kernel void kernel_im2col( const int64_t iiw = iow*args.s0 + ikw*args.d0 - args.p0; const int64_t iih = ioh*args.s1 + ikh*args.d1 - args.p1; - const int64_t offset_dst = (in*OH*OW + ioh*OW + iow)*args.CHW + (iic*(KH*KW) + ikh*KW + ikw); + int64_t offset_dst = (in*OH*OW + ioh*OW + iow)*args.CHW + (iic*(KH*KW) + ikh*KW + ikw); device T * pdst = (device T *) (dst); if (iih < 0 || iih >= args.IH || iiw < 0 || iiw >= args.IW) { - pdst[offset_dst] = 0.0f; - } else { - const int64_t offset_src = in*args.ofs0 + iic*args.ofs1 + iih*args.IW + iiw; - pdst[offset_dst] = x[offset_src]; - } -} + while (in < args.N) { + pdst[offset_dst] = 0.0f; + offset_dst += ntg[0]*args.CHW*OH*OW; -template [[host_name("kernel_im2col_f32")]] kernel im2col_t kernel_im2col; -template [[host_name("kernel_im2col_f16")]] kernel im2col_t kernel_im2col; - -typedef void (im2col_ext_t)( - device const float * x, - device char * dst, - constant ggml_metal_kargs_im2col & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tgpg[[threadgroups_per_grid]], - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]); - -template -kernel void kernel_im2col_ext( - device const float * x, - device char * dst, - constant ggml_metal_kargs_im2col & args, - uint3 tgpig[[threadgroup_position_in_grid]], - uint3 tgpg[[threadgroups_per_grid]], // tgpg[0] = D x IC x KH x KW, CHW = IC x KH x KW - uint3 tpitg[[thread_position_in_threadgroup]], - uint3 ntg[[threads_per_threadgroup]]) { // [M, 1, 1] - const int64_t KHW = (int64_t)args.KHW; - - const int64_t d = tgpig[0] / args.CHW; - const int64_t chw = tgpig[0] % args.CHW; - const int64_t tgpig_0 = chw / KHW; // 0 ~ (IC - 1) - const int64_t HW = tgpig[0] % KHW; - - const int64_t tpitg_0 = (d * ntg[0]) + tpitg[0]; - if (tpitg_0 >= args.N) { - return; - } - - const int64_t tpitg_1 = HW / args.KW; - const int64_t tpitg_2 = HW % args.KW; - - const int64_t iiw = tgpig[2] * args.s0 + tpitg_2 * args.d0 - args.p0; - const int64_t iih = tgpig[1] * args.s1 + tpitg_1 * args.d1 - args.p1; + in += ntg[0]; + } + } else { + int64_t offset_src = in*args.ofs0 + iic*args.ofs1 + iih*args.IW + iiw; - const int64_t offset_dst = - (tpitg_0 * tgpg[1] * tgpg[2] + tgpig[1] * tgpg[2] + tgpig[2]) * args.CHW + - (tgpig_0 * KHW + tpitg_1 * args.KW + tpitg_2); + while (in < args.N) { + pdst[offset_dst] = x[offset_src]; - device T * pdst = (device T *) (dst); + offset_dst += ntg[0]*args.CHW*OH*OW; + offset_src += ntg[0]*args.ofs0; - if (iih < 0 || iih >= args.IH || iiw < 0 || iiw >= args.IW) { - pdst[offset_dst] = 0.0f; - } else { - const int64_t offset_src = tpitg_0 * args.ofs0 + tgpig_0 * args.ofs1; - pdst[offset_dst] = x[offset_src + iih * args.IW + iiw]; + in += ntg[0]; + } } } -template [[host_name("kernel_im2col_ext_f32")]] kernel im2col_ext_t kernel_im2col_ext; -template [[host_name("kernel_im2col_ext_f16")]] kernel im2col_ext_t kernel_im2col_ext; +template [[host_name("kernel_im2col_f32")]] kernel im2col_t kernel_im2col; +template [[host_name("kernel_im2col_f16")]] kernel im2col_t kernel_im2col; + +// TODO: obolete -- remove +//typedef void (im2col_ext_t)( +// constant ggml_metal_kargs_im2col & args, +// device const float * x, +// device char * dst, +// uint3 tgpig[[threadgroup_position_in_grid]], +// uint3 tgpg[[threadgroups_per_grid]], +// uint3 tpitg[[thread_position_in_threadgroup]], +// uint3 ntg[[threads_per_threadgroup]]); +// +//template +//kernel void kernel_im2col_ext( +// constant ggml_metal_kargs_im2col & args, +// device const float * x, +// device char * dst, +// uint3 tgpig[[threadgroup_position_in_grid]], +// uint3 tgpg[[threadgroups_per_grid]], // tgpg[0] = D x IC x KH x KW, CHW = IC x KH x KW +// uint3 tpitg[[thread_position_in_threadgroup]], +// uint3 ntg[[threads_per_threadgroup]]) { // [M, 1, 1] +// const int64_t KHW = (int64_t)args.KHW; +// +// const int64_t d = tgpig[0] / args.CHW; +// const int64_t chw = tgpig[0] % args.CHW; +// const int64_t tgpig_0 = chw / KHW; // 0 ~ (IC - 1) +// const int64_t HW = tgpig[0] % KHW; +// +// const int64_t tpitg_0 = (d * ntg[0]) + tpitg[0]; +// if (tpitg_0 >= args.N) { +// return; +// } +// +// const int64_t tpitg_1 = HW / args.KW; +// const int64_t tpitg_2 = HW % args.KW; +// +// const int64_t iiw = tgpig[2] * args.s0 + tpitg_2 * args.d0 - args.p0; +// const int64_t iih = tgpig[1] * args.s1 + tpitg_1 * args.d1 - args.p1; +// +// const int64_t offset_dst = +// (tpitg_0 * tgpg[1] * tgpg[2] + tgpig[1] * tgpg[2] + tgpig[2]) * args.CHW + +// (tgpig_0 * KHW + tpitg_1 * args.KW + tpitg_2); +// +// device T * pdst = (device T *) (dst); +// +// if (iih < 0 || iih >= args.IH || iiw < 0 || iiw >= args.IW) { +// pdst[offset_dst] = 0.0f; +// } else { +// const int64_t offset_src = tpitg_0 * args.ofs0 + tgpig_0 * args.ofs1; +// pdst[offset_dst] = x[offset_src + iih * args.IW + iiw]; +// } +//} +// +//template [[host_name("kernel_im2col_ext_f32")]] kernel im2col_ext_t kernel_im2col_ext; +//template [[host_name("kernel_im2col_ext_f16")]] kernel im2col_ext_t kernel_im2col_ext; typedef void (conv_transpose_1d_t)( + constant ggml_metal_kargs_conv_transpose_1d & args, device const float * src0, device const float * src1, device char * dst, - constant ggml_metal_kargs_conv_transpose_1d & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]]); template kernel void kernel_conv_transpose_1d( + constant ggml_metal_kargs_conv_transpose_1d & args, device const T * src0, device const float * src1, device char * dst, - constant ggml_metal_kargs_conv_transpose_1d & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]]) { @@ -3536,26 +4182,26 @@ kernel void kernel_conv_transpose_1d( template [[host_name("kernel_conv_transpose_1d_f32_f32")]] kernel void kernel_conv_transpose_1d( + constant ggml_metal_kargs_conv_transpose_1d & args, device const float * src0, device const float * src1, device char * dst, - constant ggml_metal_kargs_conv_transpose_1d & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]]); template [[host_name("kernel_conv_transpose_1d_f16_f32")]] kernel void kernel_conv_transpose_1d( + constant ggml_metal_kargs_conv_transpose_1d & args, device const half * src0, device const float * src1, device char * dst, - constant ggml_metal_kargs_conv_transpose_1d & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]]); kernel void kernel_upscale_f32( + constant ggml_metal_kargs_upscale & args, device const char * src0, device char * dst, - constant ggml_metal_kargs_upscale & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], uint3 ntg[[threads_per_threadgroup]]) { @@ -3579,9 +4225,9 @@ kernel void kernel_upscale_f32( } kernel void kernel_pad_f32( + constant ggml_metal_kargs_pad & args, device const char * src0, device char * dst, - constant ggml_metal_kargs_pad & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], uint3 ntg[[threads_per_threadgroup]]) { @@ -3615,9 +4261,9 @@ kernel void kernel_pad_f32( } kernel void kernel_pad_reflect_1d_f32( + constant ggml_metal_kargs_pad_reflect_1d & args, device const char * src0, device char * dst, - constant ggml_metal_kargs_pad_reflect_1d & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tgpg[[threadgroups_per_grid]], uint3 tpitg[[thread_position_in_threadgroup]], @@ -3648,8 +4294,8 @@ kernel void kernel_pad_reflect_1d_f32( } kernel void kernel_arange_f32( - device char * dst, constant ggml_metal_kargs_arange & args, + device char * dst, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], uint3 ntg[[threads_per_threadgroup]]) { @@ -3662,9 +4308,9 @@ kernel void kernel_arange_f32( } kernel void kernel_timestep_embedding_f32( + constant ggml_metal_kargs_timestep_embedding & args, device const char * src0, device char * dst, - constant ggml_metal_kargs_timestep_embedding & args, uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]], uint3 ntg[[threads_per_threadgroup]]) { @@ -3682,25 +4328,25 @@ kernel void kernel_timestep_embedding_f3 } if (args.dim % 2 != 0 && tpitg.x == 0) { - embed_data[args.dim] = 0.f; + embed_data[2 * half_] = 0.f; } } // bitonic sort implementation following the CUDA kernels as reference typedef void (argsort_t)( - device const float * x, - device int32_t * dst, constant ggml_metal_kargs_argsort & args, + device const float * x, + device int32_t * dst, threadgroup int32_t * shared_values [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]]); template kernel void kernel_argsort_f32_i32( - device const float * x, - device int32_t * dst, constant ggml_metal_kargs_argsort & args, - threadgroup int32_t * shared_values [[threadgroup(0)]], + device const float * x, + device int32_t * dst, + threadgroup int32_t * shared_values [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], uint3 tpitg[[thread_position_in_threadgroup]]) { // bitonic sort @@ -3753,13 +4399,36 @@ template [[host_name("kernel_argsort_f32 template [[host_name("kernel_argsort_f32_i32_desc")]] kernel argsort_t kernel_argsort_f32_i32; kernel void kernel_leaky_relu_f32( + constant ggml_metal_kargs_leaky_relu & args, device const float * src0, device float * dst, + uint tpig[[thread_position_in_grid]]) { + const float x = src0[tpig]; + dst[tpig] = x > 0.0f ? x : x * args.slope; +} + +kernel void kernel_leaky_relu_f32_4( constant ggml_metal_kargs_leaky_relu & args, + device const float4 * src0, + device float4 * dst, uint tpig[[thread_position_in_grid]]) { - dst[tpig] = src0[tpig] > 0.0f ? src0[tpig] : src0[tpig] * args.slope; + const float4 x = src0[tpig]; + dst[tpig] = float4(x > 0.0f)*x + float4(x <= 0.0f)*(x * args.slope); } +constant bool FC_flash_attn_ext_has_mask [[function_constant(FC_FLASH_ATTN_EXT + 0)]]; +constant bool FC_flash_attn_ext_has_sinks [[function_constant(FC_FLASH_ATTN_EXT + 1)]]; +constant bool FC_flash_attn_ext_has_bias [[function_constant(FC_FLASH_ATTN_EXT + 2)]]; +constant bool FC_flash_attn_ext_has_scap [[function_constant(FC_FLASH_ATTN_EXT + 3)]]; + +//constant float FC_flash_attn_ext_scale [[function_constant(FC_FLASH_ATTN_EXT + 10)]]; +//constant float FC_flash_attn_ext_max_bias [[function_constant(FC_FLASH_ATTN_EXT + 11)]]; +//constant float FC_flash_attn_ext_logit_softcap [[function_constant(FC_FLASH_ATTN_EXT + 12)]]; + +constant int32_t FC_flash_attn_ext_ns10 [[function_constant(FC_FLASH_ATTN_EXT + 20)]]; +constant int32_t FC_flash_attn_ext_ns20 [[function_constant(FC_FLASH_ATTN_EXT + 21)]]; +constant int32_t FC_flash_attn_ext_nsg [[function_constant(FC_FLASH_ATTN_EXT + 22)]]; + // ref: https://arxiv.org/pdf/2307.08691.pdf template< typename q_t, // query types in shared memory @@ -3774,6 +4443,7 @@ template< typename qk_t, // Q*K types typename qk8x8_t, typename s_t, // soft-max types + typename s2_t, typename s8x8_t, typename o_t, // attention accumulation types typename o4_t, @@ -3784,58 +4454,98 @@ template< typename vd4x4_t, // value type in device memory short nl_v, void (*deq_v)(device const vd4x4_t *, short, thread v4x4_t &), - short DK, // K head size - short DV, // V head size - short Q = 8, // queries per threadgroup - short KV = 8, // key/value processed per each simdgroup - short C = 32> // cache items per threadgroup -kernel void kernel_flash_attn_ext( + short DK, // K head size + short DV, // V head size + short Q, // queries per threadgroup + short C, // cache items per threadgroup + short NSG> // number of simd groups +void kernel_flash_attn_ext_impl( constant ggml_metal_kargs_flash_attn_ext & args, device const char * q, device const char * k, device const char * v, device const char * mask, + device const char * sinks, device char * dst, - threadgroup half * shmem_f16 [[threadgroup(0)]], - uint3 tgpig[[threadgroup_position_in_grid]], - ushort3 ntg[[threads_per_threadgroup]], - ushort tiisg[[thread_index_in_simdgroup]], - ushort sgitg[[simdgroup_index_in_threadgroup]]) { - const short nsg = ntg.y; // number of simdgroups + threadgroup half * shmem_f16, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const ushort iq3 = tgpig[2]; + const ushort iq2 = tgpig[1]; + const ushort iq1 = tgpig[0]*Q; + +#define NS10 (FC_flash_attn_ext_ns10) +#define NS20 (FC_flash_attn_ext_ns20) + + // note: I had some concerns that using this instead of the ugly macros above was affecting performance + // need to re-check carefully and if no regressions are observerd - remove the macros + // the concerns is that maybe using const variables requires extra registers? but not sure if the compiler + // is clever enough to avoid this. unfortunately, using constexpr is not possible with FC + //const short NS10 = FC_flash_attn_ext_ns10; + //const short NS20 = FC_flash_attn_ext_ns20; - const int iq3 = tgpig[2]; - const int iq2 = tgpig[1]; - const int iq1 = tgpig[0]*Q; + constexpr short KV = 8; constexpr short DK4 = DK/4; constexpr short DK8 = DK/8; constexpr short DK16 = DK/16; constexpr short DV4 = DV/4; - constexpr short DV8 = DV/8; + //constexpr short DV8 = DV/8; constexpr short DV16 = DV/16; + constexpr short PV = PAD2(DV, 64); + constexpr short PV4 = PV/4; + constexpr short PV8 = PV/8; + //constexpr short PV16 = PV/16; + constexpr short NW = N_SIMDWIDTH; - constexpr short SH = (2*C + Q); // shared memory per simdgroup (s_t == float) + constexpr short NQ = Q/NSG; + constexpr short SH = 2*C; // shared memory per simdgroup (s_t == float) + + constexpr short TS = 2*SH; + constexpr short T = DK + 2*PV; // shared memory size per query in (half) + + threadgroup q_t * sq = (threadgroup q_t *) (shmem_f16 + 0*T); // holds the query data + threadgroup q4_t * sq4 = (threadgroup q4_t *) (shmem_f16 + 0*T); // same as above but in q4_t + threadgroup o_t * so = (threadgroup o_t *) (shmem_f16 + 0*T + Q*DK); // the result for all queries in 8x8 matrices (the O matrix from the paper) + threadgroup o4_t * so4 = (threadgroup o4_t *) (shmem_f16 + 0*T + Q*DK); + threadgroup s_t * ss = (threadgroup s_t *) (shmem_f16 + Q*T); // scratch buffer for attention, mask and diagonal matrix + threadgroup s2_t * ss2 = (threadgroup s2_t *) (shmem_f16 + Q*T); // same as above but in s2_t + + threadgroup k_t * sk = (threadgroup k_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T + Q*TS); // scratch buffer to load K in shared memory + threadgroup k4x4_t * sk4x4 = (threadgroup k4x4_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T + Q*TS); // same as above but in k4x4_t + + threadgroup v_t * sv = (threadgroup v_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T + Q*TS); // scratch buffer to load V in shared memory + threadgroup v4x4_t * sv4x4 = (threadgroup v4x4_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T + Q*TS); // same as above but in v4x4_t - const short TS = nsg*SH; // shared memory size per query in (s_t == float) - const short T = 2*DK + 2*TS; // shared memory size per query in (half) + // mask storage in shared mem + threadgroup half2 * sm2 = (threadgroup half2 *) (shmem_f16 + Q*T + 2*C); - threadgroup q_t * sq = (threadgroup q_t *) (shmem_f16 + 0*DK); // holds the query data - threadgroup q4_t * sq4 = (threadgroup q4_t *) (shmem_f16 + 0*DK); // same as above but in q4_t - threadgroup s_t * ss = (threadgroup s_t *) (shmem_f16 + 2*sgitg*SH + 2*Q*DK); // scratch buffer for attention, mask and diagonal matrix + // per-query mask pointers + device const half2 * pm2[NQ]; - threadgroup k_t * sk = (threadgroup k_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T); // scratch buffer to load K in shared memory - threadgroup k4x4_t * sk4x4 = (threadgroup k4x4_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T); // same as above but in k4x4_t + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; - threadgroup v_t * sv = (threadgroup v_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T); // scratch buffer to load V in shared memory - threadgroup v4x4_t * sv4x4 = (threadgroup v4x4_t *) (shmem_f16 + sgitg*(4*16*KV) + Q*T); // same as above but in v4x4_t + pm2[jj] = (device const half2 *) ((device const char *) mask + (iq1 + j)*args.nb31 + (iq2%args.ne32)*args.nb32 + (iq3%args.ne33)*args.nb33); + } + + { + q += iq1*args.nb01 + iq2*args.nb02 + iq3*args.nb03; + + const short ikv2 = iq2/(args.ne02/args.ne_12_2); + const short ikv3 = iq3/(args.ne03/args.ne_12_3); - // store the result for all queries in local memory in 8x8 matrices (the O matrix from the paper) - o8x8_t lo[DV8]; + k += ikv2*args.nb12 + ikv3*args.nb13; + v += ikv2*args.nb22 + ikv3*args.nb23; + } // load heads from Q to shared memory - for (short j = sgitg; j < Q; j += nsg) { - device const float4 * q4 = (device const float4 *) ((device const char *) q + ((iq1 + j)*args.nb01 + iq2*args.nb02 + iq3*args.nb03)); + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + device const float4 * q4 = (device const float4 *) ((device const char *) q + j*args.nb01); for (short i = tiisg; i < DK4; i += NW) { if (iq1 + j < args.ne01) { @@ -3846,43 +4556,30 @@ kernel void kernel_flash_attn_ext( } } - // zero out lo - for (short i = 0; i < DV8; ++i) { - lo[i] = make_filled_simdgroup_matrix((o_t) 0.0f); - } + // zero out + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + for (short i = tiisg; i < DV4; i += NW) { + so4[j*PV4 + i] = 0; + } - // zero out shared memory SH - for (short j = 0; j < Q; ++j) { for (short i = tiisg; i < SH; i += NW) { - ss[j*TS + i] = 0.0f; + ss[j*SH + i] = 0.0f; } } threadgroup_barrier(mem_flags::mem_threadgroup); - { - float S[Q] = { [0 ... Q-1] = 0.0f }; - float M[Q] = { [0 ... Q-1] = -__FLT_MAX__/2 }; - - // thread indices inside the simdgroup - // TODO: see if we can utilize quad-group functions for better performance - // https://developer.apple.com/metal/Metal-Shading-Language-Specification.pdf (6.9.3) - const short tx = tiisg%4; - const short ty = tiisg/4; - - // broadcast kv - //const short rk2 = args.ne02/args.ne12; - //const short rk3 = args.ne03/args.ne13; + float S[NQ] = { [0 ... NQ-1] = 0.0f }; - const short ikv2 = iq2/(args.ne02/args.ne_12_2); - const short ikv3 = iq3/(args.ne03/args.ne_12_3); - - const bool has_mask = mask != q; + { + float M[NQ] = { [0 ... NQ-1] = -FLT_MAX/2 }; float slope = 1.0f; // ALiBi - if (args.max_bias > 0.0f) { + if (FC_flash_attn_ext_has_bias) { const short h = iq2; const float base = h < args.n_head_log2 ? args.m0 : args.m1; @@ -3893,177 +4590,277 @@ kernel void kernel_flash_attn_ext( // loop over the KV cache // each simdgroup handles blocks of Q rows and C columns - for (int ic0 = 0; ic0 < args.ne11; ic0 += C*nsg) { - const int ic = ic0 + C*sgitg; - if (ic >= args.ne11) { - break; - } + for (int ic = 0; ic < args.ne11; ic += C) { + // read the mask into shared mem + if (FC_flash_attn_ext_has_mask) { + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; - if (has_mask) { - // used to detect blocks full of -INF - float smax = -INFINITY; + sm2[j*SH + tiisg] = pm2[jj][tiisg]; + pm2[jj] += NW; + } - // load the mask in shared memory - #pragma unroll(Q) - for (short j = 0; j < Q; ++j) { - device const half * pm = (device const half *) ((device const char *) mask + (iq1 + j)*args.nb31 + (iq2%args.ne32)*args.nb32 + (iq3%args.ne33)*args.nb33); + threadgroup_barrier(mem_flags::mem_threadgroup); - const float m = pm[ic + tiisg]; + // used to detect blocks full of -INF + // skip only when the entire threadgroup is masked + half2 smax2(-MAXHALF/2, -MAXHALF/2); - ss[j*TS + C + tiisg] = m; - smax = max(smax, m); + FOR_UNROLL (short j = 0; j < Q; ++j) { + smax2 = max(smax2, sm2[j*SH + tiisg]); } - smax = simd_max(smax); + smax2 = simd_max(smax2); + + if (max(smax2[0], smax2[1]) <= -MAXHALF/2) { + // this barrier is important + threadgroup_barrier(mem_flags::mem_threadgroup); - if (smax == -INFINITY) { continue; } } // Q*K^T - { - for (short cc = 0; cc < C/8; ++cc) { + // this is compile-time check, so it does not have runtime overhead + if (is_same::value) { + // we can read directly from global memory + device const k_t * pk = (device const k_t *) ((device const char *) k + ic*args.nb11); + threadgroup const q_t * pq = sq; + threadgroup s_t * ps = ss; + + pk += sgitg*(8*NS10); + ps += sgitg*(8*1); + + static_assert((C/8) % NSG == 0, ""); + + constexpr short NC = (C/8)/NSG; + + // TODO: not good to unroll for large contexts - not sure why? + for (short cc = 0; cc < NC; ++cc) { qk8x8_t mqk = make_filled_simdgroup_matrix((qk_t) 0.0f); - // this is compile-time check, so it does not have runtime overhead - if (is_same::value) { - // we can read directly from global memory - device const k_t * pk = (device const k_t *) ((device const char *) k + ((ic + 8*cc)*args.nb11 + ikv2*args.nb12 + ikv3*args.nb13)); - - #pragma unroll(DK8) - for (short i = 0; i < DK8; ++i) { - k8x8_t mk; - simdgroup_load(mk, pk + i*8, args.nb11/sizeof(k_t), 0, true); // transpose // TODO: use ne10 + if (DK8 % 16 != 0) { + k8x8_t mk; + q8x8_t mq; + + FOR_UNROLL (short i = 0; i < DK8; ++i) { + simdgroup_barrier(mem_flags::mem_none); + + simdgroup_load(mk, pk, NS10, 0, true); + simdgroup_load(mq, pq, DK); + + simdgroup_barrier(mem_flags::mem_none); - q8x8_t mq; - simdgroup_load(mq, sq + i*8, DK); simdgroup_multiply_accumulate(mqk, mq, mk, mqk); + + pk += 8; + pq += 8; } } else { - for (short ii = 0; ii < DK16; ii += 4) { - device const kd4x4_t * pk4x4 = (device const kd4x4_t *) ((device const char *) k + ((ic + 8*cc + ty)*args.nb11 + ikv2*args.nb12 + ikv3*args.nb13)); + k8x8_t mk[2]; + q8x8_t mq[2]; - if (DK16%4 == 0) { - // the head is evenly divisible by 4*16 = 64, so no need for bound checks - { - k4x4_t tmp; - deq_k(pk4x4 + (ii + tx)/nl_k, (ii + tx)%nl_k, tmp); - sk4x4[4*ty + tx] = tmp; - } + FOR_UNROLL (short i = 0; i < DK8/2; ++i) { + simdgroup_barrier(mem_flags::mem_none); - simdgroup_barrier(mem_flags::mem_threadgroup); + simdgroup_load(mk[0], pk + 0*8, NS10, 0, true); + simdgroup_load(mk[1], pk + 1*8, NS10, 0, true); - #pragma unroll(4) - for (short k = 0; k < 4; ++k) { - k8x8_t mk; - q8x8_t mq; - - simdgroup_load(mk, sk + 16*k + 0*8, 4*16, 0, true); // transpose - simdgroup_load(mq, sq + (2*(ii + k) + 0)*8, DK); - simdgroup_multiply_accumulate(mqk, mq, mk, mqk); - - simdgroup_load(mk, sk + 16*k + 1*8, 4*16, 0, true); // transpose - simdgroup_load(mq, sq + (2*(ii + k) + 1)*8, DK); - simdgroup_multiply_accumulate(mqk, mq, mk, mqk); - } - } else { - if (ii + tx < DK16) { - k4x4_t tmp; - deq_k(pk4x4 + (ii + tx)/nl_k, (ii + tx)%nl_k, tmp); - sk4x4[4*ty + tx] = tmp; - } + simdgroup_load(mq[0], pq + 0*8, DK); + simdgroup_load(mq[1], pq + 1*8, DK); - simdgroup_barrier(mem_flags::mem_threadgroup); + simdgroup_barrier(mem_flags::mem_none); - for (short k = 0; k < 4 && ii + k < DK16; ++k) { - k8x8_t mk; - q8x8_t mq; - - simdgroup_load(mk, sk + 16*k + 0*8, 4*16, 0, true); // transpose - simdgroup_load(mq, sq + (2*(ii + k) + 0)*8, DK); - simdgroup_multiply_accumulate(mqk, mq, mk, mqk); - - simdgroup_load(mk, sk + 16*k + 1*8, 4*16, 0, true); // transpose - simdgroup_load(mq, sq + (2*(ii + k) + 1)*8, DK); - simdgroup_multiply_accumulate(mqk, mq, mk, mqk); - } - } + simdgroup_multiply_accumulate(mqk, mq[0], mk[0], mqk); + simdgroup_multiply_accumulate(mqk, mq[1], mk[1], mqk); + + pk += 16; + pq += 16; } } - // cast qk_t -> s_t - //s8x8_t mqks(1.0f); - //simdgroup_multiply(mqks, mqk, mqks); - //simdgroup_store(mqks, ss + 8*cc, TS, 0, false); + simdgroup_store(mqk, ps, SH, 0, false); - simdgroup_store(mqk, ss + 8*cc, TS, 0, false); + pk += 8*(NSG*NS10 - DK8); + pq += 8*(NSG*0 - DK8); + ps += 8*(NSG); } - } - - // online softmax - { - for (ushort j = 0; j < Q; ++j) { - const float m = M[j]; + } else { + // TODO: this is the quantized K cache branch - not optimized yet + for (short ccc = 0; ccc < (C/8)/NSG; ++ccc) { + const short cc = ccc*NSG + sgitg; - // scale and apply the logitcap / mask - float s = ss[j*TS + tiisg]*args.scale; + const short tx = tiisg%4; + const short ty = tiisg/4; - if (args.logit_softcap != 0.0f) { - s = args.logit_softcap*precise::tanh(s); - } + qk8x8_t mqk = make_filled_simdgroup_matrix((qk_t) 0.0f); - // mqk = mqk + mask*slope - s += slope*ss[j*TS + C + tiisg]; + for (short ii = 0; ii < DK16; ii += 4) { + device const kd4x4_t * pk4x4 = (device const kd4x4_t *) ((device const char *) k + ((ic + 8*cc + ty)*args.nb11)); - M[j] = simd_max(max(M[j], s)); + if (DK16%4 == 0) { + // the head is evenly divisible by 4*16 = 64, so no need for bound checks + { + k4x4_t tmp; + deq_k(pk4x4 + (ii + tx)/nl_k, (ii + tx)%nl_k, tmp); + sk4x4[4*ty + tx] = tmp; + } - const float ms = exp(m - M[j]); - const float vs = exp(s - M[j]); + simdgroup_barrier(mem_flags::mem_threadgroup); - S[j] = S[j]*ms + simd_sum(vs); + FOR_UNROLL (short k = 0; k < 4; ++k) { + k8x8_t mk; + q8x8_t mq; + + simdgroup_load(mk, sk + 16*k + 0*8, 4*16, 0, true); // transpose + simdgroup_load(mq, sq + (2*(ii + k) + 0)*8, DK); + simdgroup_multiply_accumulate(mqk, mq, mk, mqk); + + simdgroup_load(mk, sk + 16*k + 1*8, 4*16, 0, true); // transpose + simdgroup_load(mq, sq + (2*(ii + k) + 1)*8, DK); + simdgroup_multiply_accumulate(mqk, mq, mk, mqk); + } + } else { + if (ii + tx < DK16) { + k4x4_t tmp; + deq_k(pk4x4 + (ii + tx)/nl_k, (ii + tx)%nl_k, tmp); + sk4x4[4*ty + tx] = tmp; + } - // the P matrix from the paper (Q rows, C columns) - ss[j*TS + tiisg] = vs; + simdgroup_barrier(mem_flags::mem_threadgroup); - // create a QxQ diagonal matrix for rescaling the output - if (tiisg == j) { - ss[j*TS + 2*C + j] = ms; + for (short k = 0; k < 4 && ii + k < DK16; ++k) { + k8x8_t mk; + q8x8_t mq; + + simdgroup_load(mk, sk + 16*k + 0*8, 4*16, 0, true); // transpose + simdgroup_load(mq, sq + (2*(ii + k) + 0)*8, DK); + simdgroup_multiply_accumulate(mqk, mq, mk, mqk); + + simdgroup_load(mk, sk + 16*k + 1*8, 4*16, 0, true); // transpose + simdgroup_load(mq, sq + (2*(ii + k) + 1)*8, DK); + simdgroup_multiply_accumulate(mqk, mq, mk, mqk); + } + } } + + simdgroup_store(mqk, ss + 8*cc, SH, 0, false); } } - // O = diag(ms)*O - { - s8x8_t ms; - simdgroup_load(ms, ss + 2*C, TS, 0, false); + threadgroup_barrier(mem_flags::mem_threadgroup); + + // online softmax + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + + const float m = M[jj]; + + // scale and apply the logitcap / mask + float2 s2 = ss2[j*SH/2 + tiisg]*args.scale; + + if (FC_flash_attn_ext_has_scap) { + s2 = args.logit_softcap*precise::tanh(s2); + } + + // mqk = mqk + slope*mask + if (FC_flash_attn_ext_has_bias) { + s2 += s2_t(sm2[j*SH + tiisg])*slope; + } else { + s2 += s2_t(sm2[j*SH + tiisg]); + } + + M[jj] = simd_max(max(M[jj], max(s2[0], s2[1]))); + + const float ms = exp(m - M[jj]); + const float2 vs2 = exp(s2 - M[jj]); + + S[jj] = S[jj]*ms + simd_sum(vs2[0] + vs2[1]); + + // the P matrix from the paper (Q rows, C columns) + ss2[j*SH/2 + tiisg] = vs2; + + if (DV4 % NW == 0) { + FOR_UNROLL (short ii = 0; ii < DV4/NW; ++ii) { + const short i = ii*NW + tiisg; - #pragma unroll(DV8) - for (short i = 0; i < DV8; ++i) { - simdgroup_multiply(lo[i], ms, lo[i]); + so4[j*PV4 + i] *= ms; + } + } else { + for (short i = tiisg; i < DV4; i += NW) { + so4[j*PV4 + i] *= ms; + } } } + threadgroup_barrier(mem_flags::mem_threadgroup); + // O = O + (Q*K^T)*V { - for (short cc = 0; cc < C/8; ++cc) { - s8x8_t vs; - simdgroup_load(vs, ss + 8*cc, TS, 0, false); - - if (is_same::value) { - // we can read directly from global memory - device const v_t * pv = (device const v_t *) ((device const char *) v + ((ic + 8*cc)*args.nb21 + ikv2*args.nb22 + ikv3*args.nb23)); - - #pragma unroll(DV8) - for (short i = 0; i < DV8; ++i) { - v8x8_t mv; - simdgroup_load(mv, pv + i*8, args.nb21/sizeof(v_t), 0, false); // TODO: use ne20 + // we can read directly from global memory + if (is_same::value) { + static_assert(PV8 % NSG == 0, ""); + + constexpr short NO = PV8/NSG; - simdgroup_multiply_accumulate(lo[i], vs, mv, lo[i]); + o8x8_t lo[NO]; + + { + auto sot = so + 8*sgitg; + + FOR_UNROLL (short ii = 0; ii < NO; ++ii) { + simdgroup_load(lo[ii], sot, PV, 0, false); + + sot += 8*NSG; } - } else { - for (short ii = 0; ii < DV16; ii += 4) { - device const vd4x4_t * pv4x4 = (device const vd4x4_t *) ((device const char *) v + ((ic + 8*cc + ty)*args.nb21 + ikv2*args.nb22 + ikv3*args.nb23)); + } + + { + auto sst = ss; + + device const v_t * pv = (device const v_t *) ((device const char *) v + ic*args.nb21); + + pv += 8*sgitg; + + FOR_UNROLL (short cc = 0; cc < C/8; ++cc) { + s8x8_t vs; + simdgroup_load(vs, sst, SH, 0, false); + + FOR_UNROLL (short ii = 0; ii < NO; ++ii) { + v8x8_t mv; + + simdgroup_load(mv, pv, NS20, 0, false); + simdgroup_multiply_accumulate(lo[ii], vs, mv, lo[ii]); + + pv += 8*NSG; + } + + pv += 8*(NS20 - NO*NSG); + sst += 8; + } + } + + { + auto sot = so + 8*sgitg; + + FOR_UNROLL (short ii = 0; ii < NO; ++ii) { + simdgroup_store(lo[ii], sot, PV, 0, false); + + sot += 8*NSG; + } + } + } else { + // TODO: this is the quantized V cache branch - not optimized yet + + const short tx = tiisg%4; + const short ty = tiisg/4; + + for (short cc = 0; cc < C/8; ++cc) { + s8x8_t vs; + simdgroup_load(vs, ss + 8*cc, SH, 0, false); + + for (short ii = 4*sgitg; ii < DV16; ii += 4*NSG) { + device const vd4x4_t * pv4x4 = (device const vd4x4_t *) ((device const char *) v + ((ic + 8*cc + ty)*args.nb21)); if (DV16%4 == 0) { // no need for bound checks @@ -4075,15 +4872,20 @@ kernel void kernel_flash_attn_ext( simdgroup_barrier(mem_flags::mem_threadgroup); - #pragma unroll(4) - for (short k = 0; k < 4; ++k) { - v8x8_t mv; + FOR_UNROLL (short k = 0; k < 4; ++k) { + v8x8_t mv[2]; + o8x8_t lo[2]; + + simdgroup_load(mv[0], sv + 16*k + 0*8, 4*16, 0, false); + simdgroup_load(mv[1], sv + 16*k + 1*8, 4*16, 0, false); + simdgroup_load(lo[0], so + 8*(2*(ii + k) + 0), PV, 0, false); + simdgroup_load(lo[1], so + 8*(2*(ii + k) + 1), PV, 0, false); - simdgroup_load(mv, sv + 16*k + 0*8, 4*16, 0, false); - simdgroup_multiply_accumulate(lo[2*(ii + k) + 0], vs, mv, lo[2*(ii + k) + 0]); + simdgroup_multiply_accumulate(lo[0], vs, mv[0], lo[0]); + simdgroup_multiply_accumulate(lo[1], vs, mv[1], lo[1]); - simdgroup_load(mv, sv + 16*k + 1*8, 4*16, 0, false); - simdgroup_multiply_accumulate(lo[2*(ii + k) + 1], vs, mv, lo[2*(ii + k) + 1]); + simdgroup_store(lo[0], so + 8*(2*(ii + k) + 0), PV, 0, false); + simdgroup_store(lo[1], so + 8*(2*(ii + k) + 1), PV, 0, false); } } else { if (ii + tx < DV16) { @@ -4095,207 +4897,249 @@ kernel void kernel_flash_attn_ext( simdgroup_barrier(mem_flags::mem_threadgroup); for (short k = 0; k < 4 && ii + k < DV16; ++k) { - v8x8_t mv; + v8x8_t mv[2]; + o8x8_t lo[2]; - simdgroup_load(mv, sv + 16*k + 0*8, 4*16, 0, false); - simdgroup_multiply_accumulate(lo[2*(ii + k) + 0], vs, mv, lo[2*(ii + k) + 0]); + simdgroup_load(mv[0], sv + 16*k + 0*8, 4*16, 0, false); + simdgroup_load(mv[1], sv + 16*k + 1*8, 4*16, 0, false); + simdgroup_load(lo[0], so + 8*(2*(ii + k) + 0), PV, 0, false); + simdgroup_load(lo[1], so + 8*(2*(ii + k) + 1), PV, 0, false); - simdgroup_load(mv, sv + 16*k + 1*8, 4*16, 0, false); - simdgroup_multiply_accumulate(lo[2*(ii + k) + 1], vs, mv, lo[2*(ii + k) + 1]); + simdgroup_multiply_accumulate(lo[0], vs, mv[0], lo[0]); + simdgroup_multiply_accumulate(lo[1], vs, mv[1], lo[1]); + + simdgroup_store(lo[0], so + 8*(2*(ii + k) + 0), PV, 0, false); + simdgroup_store(lo[1], so + 8*(2*(ii + k) + 1), PV, 0, false); } } } } } } - } - - // these are needed for reducing the results from the simdgroups (reuse the ss buffer) - for (short j = tiisg; j < Q; j += NW) { - ss[j*TS + 0] = S[j]; - ss[j*TS + 1] = M[j]; - } - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - threadgroup float * so = (threadgroup float *) (shmem_f16 + 0*DK); // reuse query data for accumulation - threadgroup float4 * so4 = (threadgroup float4 *) (shmem_f16 + 0*DK); - - // store result to shared memory in F32 - if (sgitg == 0) { - for (short i = 0; i < DV8; ++i) { - //simdgroup_store(lo[i], so + i*8, DV, 0, false); - simdgroup_float8x8 t(1.0f); - simdgroup_multiply(t, lo[i], t); - simdgroup_store(t, so + i*8, DV, 0, false); + threadgroup_barrier(mem_flags::mem_threadgroup); } - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - // reduce the warps sequentially - for (ushort sg = 1; sg < nsg; ++sg) { - if (sgitg == sg) { - for (short j = tiisg; j < Q; j += NW) { - const float S0 = ss[j*TS - 1*SH + 0]; - const float S1 = ss[j*TS + 0]; - const float M0 = ss[j*TS - 1*SH + 1]; - const float M1 = ss[j*TS + 1]; + if (FC_flash_attn_ext_has_sinks) { + FOR_UNROLL (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; - const float M = max(M0, M1); + const float m = M[jj]; + const float s = tiisg == 0 ? ((device const float *) sinks)[iq2] : -FLT_MAX/2; - float ms0 = exp(M0 - M); - float ms1 = exp(M1 - M); + M[jj] = simd_max(max(M[jj], s)); - const float S = S0*ms0 + S1*ms1; + const float ms = exp(m - M[jj]); + const float vs = exp(s - M[jj]); - ss[j*TS + 0] = S; - ss[j*TS + 1] = M; + S[jj] = S[jj]*ms + simd_sum(vs); - ss[j*TS + 2*C + j - 1*SH] = ms0; - ss[j*TS + 2*C + j ] = ms1; + for (short i = tiisg; i < DV4; i += NW) { + so4[j*PV4 + i] *= ms; + } } + } + } - //simdgroup_barrier(mem_flags::mem_threadgroup); - - // O_0 = diag(ms0)*O_0 + diag(ms1)*O_1 - { - s8x8_t ms0; - s8x8_t ms1; + // store to global memory + for (short jj = 0; jj < NQ; ++jj) { + const short j = jj*NSG + sgitg; + if (iq1 + j >= args.ne01) { + break; + } - simdgroup_load(ms0, ss + 2*C - 1*SH, TS, 0, false); - simdgroup_load(ms1, ss + 2*C, TS, 0, false); + device float4 * dst4 = (device float4 *) dst + ((uint64_t)iq3*args.ne2*args.ne1 + iq2 + (uint64_t)(iq1 + j)*args.ne1)*DV4; - #pragma unroll(DV8) - for (short i = 0; i < DV8; ++i) { - simdgroup_float8x8 t; + const float scale = 1.0f/S[jj]; - simdgroup_load (t, so + i*8, DV, 0, false); - simdgroup_multiply(t, ms0, t); + if (DV4 % NW == 0) { + FOR_UNROLL (short ii = 0; ii < DV4/NW; ++ii) { + const short i = ii*NW + tiisg; - simdgroup_multiply_accumulate(t, ms1, lo[i], t); - simdgroup_store(t, so + i*8, DV, 0, false); - } + dst4[i] = (float4) so4[j*PV4 + i]*scale; + } + } else { + for (short i = tiisg; i < DV4; i += NW) { + dst4[i] = (float4) so4[j*PV4 + i]*scale; } } - - threadgroup_barrier(mem_flags::mem_threadgroup); } - threadgroup s_t * sf = (threadgroup s_t *) (shmem_f16 + 2*(nsg-1)*SH + 2*Q*DK); - - // final rescale with 1/S and store to global memory - for (short j = sgitg; j < Q && iq1 + j < args.ne01; j += nsg) { - const float S = 1.0f/sf[j*TS + 0]; - - device float4 * dst4 = (device float4 *) dst + ((uint64_t)iq3*args.ne2*args.ne1 + iq2 + (uint64_t)(iq1 + j)*args.ne1)*DV4; +#undef NS10 +#undef NS20 +} - for (short i = tiisg; i < DV4; i += NW) { - dst4[i] = (float4) so4[j*DV4 + i]*S; - } +template< + typename q_t, // query types in shared memory + typename q4_t, + typename q8x8_t, + typename k_t, // key types in shared memory + typename k4x4_t, + typename k8x8_t, + typename v_t, // value types in shared memory + typename v4x4_t, + typename v8x8_t, + typename qk_t, // Q*K types + typename qk8x8_t, + typename s_t, // soft-max types + typename s2_t, + typename s8x8_t, + typename o_t, // attention accumulation types + typename o4_t, + typename o8x8_t, + typename kd4x4_t, // key type in device memory + short nl_k, + void (*deq_k)(device const kd4x4_t *, short, thread k4x4_t &), + typename vd4x4_t, // value type in device memory + short nl_v, + void (*deq_v)(device const vd4x4_t *, short, thread v4x4_t &), + short DK, // K head size + short DV, // V head size + short Q = 8, // queries per threadgroup + short C = 64> // cache items per threadgroup +kernel void kernel_flash_attn_ext( + constant ggml_metal_kargs_flash_attn_ext & args, + device const char * q, + device const char * k, + device const char * v, + device const char * mask, + device const char * sinks, + device char * dst, + threadgroup half * shmem_f16 [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { +#define FWD_TMPL q_t, q4_t, q8x8_t, k_t, k4x4_t, k8x8_t, v_t, v4x4_t, v8x8_t, qk_t, qk8x8_t, s_t, s2_t, s8x8_t, o_t, o4_t, o8x8_t, kd4x4_t, nl_k, deq_k, vd4x4_t, nl_v, deq_v, DK, DV, Q, C +#define FWD_ARGS args, q, k, v, mask, sinks, dst, shmem_f16, tgpig, tiisg, sgitg + switch (FC_flash_attn_ext_nsg) { + // note: disabled cases to reduce library load time + //case 1: kernel_flash_attn_ext_impl(FWD_ARGS); break; + //case 2: kernel_flash_attn_ext_impl(FWD_ARGS); break; + case 4: kernel_flash_attn_ext_impl(FWD_ARGS); break; } +#undef FWD_TMPL +#undef FWD_ARGS } // TODO: this is quite ugly. in the future these types will be hardcoded in the kernel, but for now keep them as // template to be able to explore different combinations // #define FA_TYPES \ - float, float4, simdgroup_float8x8, \ + half, half4, simdgroup_half8x8, \ half, half4x4, simdgroup_half8x8, \ half, half4x4, simdgroup_half8x8, \ float, simdgroup_float8x8, \ - float, simdgroup_float8x8, \ - half, half4, simdgroup_half8x8 - //float, float4, simdgroup_float8x8 + float, float2, simdgroup_float8x8, \ + float, float4, simdgroup_float8x8 + //half, half4, simdgroup_half8x8 #define FA_TYPES_BF \ bfloat, bfloat4, simdgroup_bfloat8x8, \ bfloat, bfloat4x4, simdgroup_bfloat8x8, \ bfloat, bfloat4x4, simdgroup_bfloat8x8, \ float, simdgroup_float8x8, \ - float, simdgroup_float8x8, \ + float, float2, simdgroup_float8x8, \ half, half4, simdgroup_half8x8 //float, float4, simdgroup_float8x8 typedef decltype(kernel_flash_attn_ext) flash_attn_ext_t; -template [[host_name("kernel_flash_attn_ext_f16_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_f16_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_bf16_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_bf16_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_f16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_bf16_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_bf16_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; #endif -template [[host_name("kernel_flash_attn_ext_q4_0_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_0_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q4_1_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q4_1_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q5_0_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_0_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q5_1_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q5_1_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; - -template [[host_name("kernel_flash_attn_ext_q8_0_h64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_hk192_hv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_h256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; -template [[host_name("kernel_flash_attn_ext_q8_0_hk576_hv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_q4_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q4_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_q5_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_q5_1_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q5_1_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; + +template [[host_name("kernel_flash_attn_ext_q8_0_dk40_dv40" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk64_dv64" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk80_dv80" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk96_dv96" )]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk112_dv112")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk128_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk192_dv192")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk192_dv128")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk256_dv256")]] kernel flash_attn_ext_t kernel_flash_attn_ext; +template [[host_name("kernel_flash_attn_ext_q8_0_dk576_dv512")]] kernel flash_attn_ext_t kernel_flash_attn_ext; #undef FA_TYPES #undef FA_TYPES_BF +constant bool FC_flash_attn_ext_vec_has_mask [[function_constant(FC_FLASH_ATTN_EXT_VEC + 0)]]; +constant bool FC_flash_attn_ext_vec_has_sinks [[function_constant(FC_FLASH_ATTN_EXT_VEC + 1)]]; +constant bool FC_flash_attn_ext_vec_has_bias [[function_constant(FC_FLASH_ATTN_EXT_VEC + 2)]]; +constant bool FC_flash_attn_ext_vec_has_scap [[function_constant(FC_FLASH_ATTN_EXT_VEC + 3)]]; + +//constant float FC_flash_attn_ext_vec_scale [[function_constant(FC_FLASH_ATTN_EXT_VEC + 10)]]; +//constant float FC_flash_attn_ext_vec_max_bias [[function_constant(FC_FLASH_ATTN_EXT_VEC + 11)]]; +//constant float FC_flash_attn_ext_vec_logit_softcap [[function_constant(FC_FLASH_ATTN_EXT_VEC + 12)]]; + +constant int32_t FC_flash_attn_ext_vec_ns10 [[function_constant(FC_FLASH_ATTN_EXT_VEC + 20)]]; +constant int32_t FC_flash_attn_ext_vec_ns20 [[function_constant(FC_FLASH_ATTN_EXT_VEC + 21)]]; +constant int32_t FC_flash_attn_ext_vec_nsg [[function_constant(FC_FLASH_ATTN_EXT_VEC + 22)]]; +constant int32_t FC_flash_attn_ext_vec_nwg [[function_constant(FC_FLASH_ATTN_EXT_VEC + 23)]]; + template< typename q4_t, // query types in shared memory typename k4_t, // key types in shared memory @@ -4314,57 +5158,86 @@ template< short DV, // V head size short NE = 4, // head elements per thread short Q = 1, // queries per threadgroup - short C = 32> // cache items per threadgroup -kernel void kernel_flash_attn_ext_vec( - constant ggml_metal_kargs_flash_attn_ext & args, + short C = 32, // cache items per threadgroup + short NSG> // number of simd groups +void kernel_flash_attn_ext_vec_impl( + constant ggml_metal_kargs_flash_attn_ext_vec & args, device const char * q, device const char * k, device const char * v, device const char * mask, + device const char * sinks, device char * dst, threadgroup half * shmem_f16 [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], - ushort3 ntg[[threads_per_threadgroup]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - const short nsg = ntg.y; // number of simdgroups + static_assert(DK % 32 == 0, "DK must be divisible by 32"); + static_assert(DV % 32 == 0, "DV must be divisible by 32"); + +#define NWG (FC_flash_attn_ext_vec_nwg) + +#define NS10 (FC_flash_attn_ext_vec_ns10) +#define NS20 (FC_flash_attn_ext_vec_ns20) - const int iq3 = tgpig[2]; - const int iq2 = tgpig[1]; - const int iq1 = tgpig[0]; + const short iwg = tgpig[2]%NWG; + + const ushort iq3 = tgpig[2]/NWG; + const ushort iq2 = tgpig[1]; + const ushort iq1 = tgpig[0]; constexpr short DK4 = DK/4; constexpr short DV4 = DV/4; + + constexpr short PK = PAD2(DK, 128); + constexpr short PK4 = PK/4; + + constexpr short PV = PAD2(DV, 128); + constexpr short PV4 = PV/4; + constexpr short NW = N_SIMDWIDTH; constexpr short NL = NW/NE; // note: this can be adjusted to support different head sizes and simdgroup work loads constexpr short SH = 4*C; // shared memory per simdgroup - const short T = DK + nsg*SH; // shared memory size per query in (half) + static_assert(DK4 % NL == 0, "DK4 must be divisible by NL"); + static_assert(DV4 % NL == 0, "DV4 must be divisible by NL"); + + const short T = PK + NSG*SH; // shared memory size per query in (half) - //threadgroup q_t * sq = (threadgroup q_t *) (shmem_f16 + 0*DK); // holds the query data - threadgroup q4_t * sq4 = (threadgroup q4_t *) (shmem_f16 + 0*DK); // same as above but in q4_t - threadgroup s_t * ss = (threadgroup s_t *) (shmem_f16 + sgitg*SH + Q*DK); // scratch buffer for attention - threadgroup s4_t * ss4 = (threadgroup s4_t *) (shmem_f16 + sgitg*SH + Q*DK); // same as above but in s4_t - threadgroup float * sm = (threadgroup float *) (shmem_f16 + sgitg*SH + 2*C + Q*DK); // scratch buffer for mask - threadgroup o4_t * sr4 = (threadgroup o4_t *) (shmem_f16 + 2*sgitg*DV + Q*T); // scratch buffer for the results + //threadgroup q_t * sq = (threadgroup q_t *) (shmem_f16 + 0*PK); // holds the query data + threadgroup q4_t * sq4 = (threadgroup q4_t *) (shmem_f16 + 0*PK); // same as above but in q4_t + threadgroup s_t * ss = (threadgroup s_t *) (shmem_f16 + sgitg*SH + Q*PK); // scratch buffer for attention + threadgroup s4_t * ss4 = (threadgroup s4_t *) (shmem_f16 + sgitg*SH + Q*PK); // same as above but in s4_t + threadgroup half * sm = (threadgroup half *) (shmem_f16 + sgitg*SH + 2*C + Q*PK); // scratch buffer for mask + threadgroup o4_t * so4 = (threadgroup o4_t *) (shmem_f16 + 2*sgitg*PV + Q*T); // scratch buffer for the results - // store the result for all queries in local memory (the O matrix from the paper) - o4_t lo[DV4/NL]; + // store the result for all queries in shared memory (the O matrix from the paper) + so4 += tiisg; + + { + q += iq1*args.nb01 + iq2*args.nb02 + iq3*args.nb03; + + const short ikv2 = iq2/(args.ne02/args.ne_12_2); + const short ikv3 = iq3/(args.ne03/args.ne_12_3); + + k += ikv2*args.nb12 + ikv3*args.nb13; + v += ikv2*args.nb22 + ikv3*args.nb23; + } // load heads from Q to shared memory - device const float4 * q4 = (device const float4 *) ((device const char *) q + (iq1*args.nb01 + iq2*args.nb02 + iq3*args.nb03)); + device const float4 * q4 = (device const float4 *) ((device const char *) q); - for (short i = tiisg; i < DK4; i += NW) { - if (iq1 < args.ne01) { + for (short i = tiisg; i < PK4; i += NW) { + if (iq1 < args.ne01 && i < DK4) { sq4[i] = (q4_t) q4[i]; } else { sq4[i] = (q4_t) 0.0f; } } - // zero out lo + // zero out so for (short i = 0; i < DV4/NL; ++i) { - lo[i] = (o4_t) 0.0f; + so4[i*NL] = (o4_t) 0.0f; } // zero out shared memory SH @@ -4376,28 +5249,19 @@ kernel void kernel_flash_attn_ext_vec( { float S = 0.0f; - float M = -__FLT_MAX__/2; + float M = -FLT_MAX/2; // thread indices inside the simdgroup const short tx = tiisg%NL; const short ty = tiisg/NL; - // broadcast kv - //const short rk2 = args.ne02/args.ne12; - //const short rk3 = args.ne03/args.ne13; - - const short ikv2 = iq2/(args.ne02/args.ne_12_2); - const short ikv3 = iq3/(args.ne03/args.ne_12_3); - - const bool has_mask = mask != q; - // pointer to the mask device const half * pm = (device const half *) (mask + iq1*args.nb31 + (iq2%args.ne32)*args.nb32 + (iq3%args.ne33)*args.nb33); float slope = 1.0f; // ALiBi - if (args.max_bias > 0.0f) { + if (FC_flash_attn_ext_vec_has_bias) { const short h = iq2; const float base = h < args.n_head_log2 ? args.m0 : args.m1; @@ -4408,13 +5272,13 @@ kernel void kernel_flash_attn_ext_vec( // loop over the KV cache // each simdgroup handles blocks of Q rows and C columns - for (int ic0 = 0; ic0 < args.ne11; ic0 += C*nsg) { + for (int ic0 = (int) iwg*C*NSG; ic0 < args.ne11; ic0 += (int) NWG*C*NSG) { const int ic = ic0 + C*sgitg; if (ic >= args.ne11) { break; } - if (has_mask) { + if (FC_flash_attn_ext_vec_has_mask) { sm[tiisg] = pm[ic + tiisg]; } @@ -4425,69 +5289,81 @@ kernel void kernel_flash_attn_ext_vec( // Q*K^T { - // each simdgroup processes 1 query and NE (NW/NL) head elements - for (short cc = 0; cc < C/NE; ++cc) { - qk_t mqk = 0.0f; - - device const kd4_t * pk = (device const kd4_t *) ((device const char *) k + ((ic + NE*cc + ty)*args.nb11 + ikv2*args.nb12 + ikv3*args.nb13)); - - #pragma unroll(DK4/NL) - for (short ii = 0; ii < DK4; ii += NL) { - const short i = ii + tx; + device const k4_t * pk4 = (device const k4_t *) ((device const char *) k + ic*args.nb11); + threadgroup const q4_t * pq4 = sq4; + + pk4 += ty*NS10/4 + tx; + pq4 += tx; + + qk_t mqk[C/NE] = { [ 0 ... C/NE - 1] = 0.0f }; + + // each simdgroup processes 1 query and NE (NW/NL) cache elements + FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { + if (is_same::value) { + FOR_UNROLL (short ii = 0; ii < DK4/NL; ++ii) { + mqk[cc] += dot((float4) pk4[cc*NE*NS10/4 + ii*NL], (float4) pq4[ii*NL]); + } + } else { + device const kd4_t * pk = (device const kd4_t *) ((device const char *) k + ((ic + NE*cc + ty)*args.nb11)); k4_t mk; - deq_k_t4(pk + i/nl_k, i%nl_k, mk); - // note: this is less precise than the version below - //mqka[0] += dot(mq[0], mk[0]); - //mqka[1] += dot(mq[1], mk[1]); - //mqka[2] += dot(mq[2], mk[2]); - //mqka[3] += dot(mq[3], mk[3]); - - //q4x4_t mq = sq4x4[i]; - //mqka[0] += dot((float4) mq[0], (float4) mk[0]); - //mqka[1] += dot((float4) mq[1], (float4) mk[1]); - //mqka[2] += dot((float4) mq[2], (float4) mk[2]); - //mqka[3] += dot((float4) mq[3], (float4) mk[3]); + FOR_UNROLL (short ii = 0; ii < DK4/NL; ++ii) { + const short i = ii*NL + tx; + + deq_k_t4(pk + i/nl_k, i%nl_k, mk); - mqk += dot((float4) mk, (float4) sq4[i]); + mqk[cc] += dot((float4) mk, (float4) sq4[i]); + } } - static_assert(NE > 1, "NE must be > 1"); // note: not sure why NE == 1 fails + if (NE == 1) { + mqk[cc] = simd_sum(mqk[cc]); + } else { + // simdgroup reduce (NE = 4) + // [ 0 .. 7] -> [ 0] + // [ 8 .. 15] -> [ 8] + // [16 .. 23] -> [16] + // [24 .. 31] -> [24] + if (NE <= 1) { + mqk[cc] += simd_shuffle_down(mqk[cc], 16); + } + if (NE <= 2) { + mqk[cc] += simd_shuffle_down(mqk[cc], 8); + } + if (NE <= 4) { + mqk[cc] += simd_shuffle_down(mqk[cc], 4); + } + if (NE <= 8) { + mqk[cc] += simd_shuffle_down(mqk[cc], 2); + } + if (NE <= 16) { + mqk[cc] += simd_shuffle_down(mqk[cc], 1); + } - // simdgroup reduce (NE = 4) - // [ 0 .. 7] -> [ 0] - // [ 8 .. 15] -> [ 8] - // [16 .. 23] -> [16] - // [24 .. 31] -> [24] - if (NE <= 1) { - mqk += simd_shuffle_down(mqk, 16); - } - if (NE <= 2) { - mqk += simd_shuffle_down(mqk, 8); + // broadcast + mqk[cc] = simd_shuffle(mqk[cc], NL*ty); } - if (NE <= 4) { - mqk += simd_shuffle_down(mqk, 4); - } - if (NE <= 8) { - mqk += simd_shuffle_down(mqk, 2); - } - if (NE <= 16) { - mqk += simd_shuffle_down(mqk, 1); - } - - // mqk = mqk*scale + mask*slope - if (tx == 0) { - mqk *= args.scale; + } - if (args.logit_softcap != 0.0f) { - mqk = args.logit_softcap*precise::tanh(mqk); - } + if (FC_flash_attn_ext_vec_has_mask && + !FC_flash_attn_ext_vec_has_scap && + !FC_flash_attn_ext_vec_has_bias) { + ss[NE*tx + ty] = fma(mqk[tx], args.scale, (qk_t) sm[NE*tx + ty]); + } else { + mqk[tx] *= args.scale; - mqk += sm[NE*cc + ty]*slope; + if (FC_flash_attn_ext_vec_has_scap) { + mqk[tx] = args.logit_softcap*precise::tanh(mqk[tx]); + } - ss[NE*cc + ty] = mqk; + if (FC_flash_attn_ext_vec_has_bias) { + mqk[tx] += (qk_t) sm[NE*tx + ty]*slope; + } else { + mqk[tx] += (qk_t) sm[NE*tx + ty]; } + + ss[NE*tx + ty] = mqk[tx]; } } @@ -4509,9 +5385,10 @@ kernel void kernel_flash_attn_ext_vec( ss[tiisg] = vs; // O = diag(ms)*O - #pragma unroll(DV4/NL) - for (short ii = 0; ii < DV4; ii += NL) { - lo[ii/NL] *= ms; + if ((DV4/NL % NW == 0) || ty == 0) { + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + so4[ii*NL] *= ms; + } } } @@ -4519,21 +5396,97 @@ kernel void kernel_flash_attn_ext_vec( // O = O + (Q*K^T)*V { - //#pragma unroll(C/NE) - for (short cc = 0; cc < C/NE; ++cc) { - device const vd4_t * pv4 = (device const vd4_t *) ((device const char *) v + ((ic + NE*cc + ty)*args.nb21 + ikv2*args.nb22 + ikv3*args.nb23)); + o4_t lo[DV4/NL]; + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + lo[ii] = 0.0f; + } + + if (is_same::value) { + device const v4_t * pv4 = (device const v4_t *) ((device const char *) v + ic*args.nb21); + + pv4 += ty*NS20/4 + tx; + + const auto sst = ss + ty; + + FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + lo[ii] += o4_t(float4(pv4[cc*NE*NS20/4 + ii*NL])*float4(sst[cc*NE])); + } + } + } else { + FOR_UNROLL (short cc = 0; cc < C/NE; ++cc) { + device const vd4_t * pv4 = (device const vd4_t *) ((device const char *) v + ((ic + NE*cc + ty)*args.nb21)); + + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + const short i = ii*NL + tx; - const s4_t ms(ss[NE*cc + ty]); + v4_t mv; + deq_v_t4(pv4 + i/nl_v, i%nl_v, mv); - #pragma unroll(DV4/NL) - for (short ii = 0; ii < DV4; ii += NL) { - const short i = ii + tx; + lo[ii] += o4_t(float4(mv)*float4(ss[NE*cc + ty])); + } + } + } - v4_t mv; - deq_v_t4(pv4 + i/nl_v, i%nl_v, mv); + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + if (NE > 1) { + lo[ii][0] += simd_shuffle_down(lo[ii][0], 16); + lo[ii][1] += simd_shuffle_down(lo[ii][1], 16); + lo[ii][2] += simd_shuffle_down(lo[ii][2], 16); + lo[ii][3] += simd_shuffle_down(lo[ii][3], 16); + } + + if (NE > 2) { + lo[ii][0] += simd_shuffle_down(lo[ii][0], 8); + lo[ii][1] += simd_shuffle_down(lo[ii][1], 8); + lo[ii][2] += simd_shuffle_down(lo[ii][2], 8); + lo[ii][3] += simd_shuffle_down(lo[ii][3], 8); + } - lo[ii/NL] += o4_t(float4(mv)*float4(ms)); + if (NE > 4) { + lo[ii][0] += simd_shuffle_down(lo[ii][0], 4); + lo[ii][1] += simd_shuffle_down(lo[ii][1], 4); + lo[ii][2] += simd_shuffle_down(lo[ii][2], 4); + lo[ii][3] += simd_shuffle_down(lo[ii][3], 4); } + + if (NE > 8) { + lo[ii][0] += simd_shuffle_down(lo[ii][0], 2); + lo[ii][1] += simd_shuffle_down(lo[ii][1], 2); + lo[ii][2] += simd_shuffle_down(lo[ii][2], 2); + lo[ii][3] += simd_shuffle_down(lo[ii][3], 2); + } + + if (NE > 16) { + lo[ii][0] += simd_shuffle_down(lo[ii][0], 1); + lo[ii][1] += simd_shuffle_down(lo[ii][1], 1); + lo[ii][2] += simd_shuffle_down(lo[ii][2], 1); + lo[ii][3] += simd_shuffle_down(lo[ii][3], 1); + } + } + + if ((DV4/NL % NW == 0) || ty == 0) { + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + so4[ii*NL] += lo[ii]; + } + } + } + } + + if (FC_flash_attn_ext_vec_has_sinks && sgitg == 0 && iwg == 0) { + const float m = M; + const float s = tiisg == 0 ? ((device const float *) sinks)[iq2] : -FLT_MAX/2; + + M = simd_max(max(M, s)); + + const float ms = exp(m - M); + const float vs = exp(s - M); + + S = S*ms + simd_sum(vs); + + if ((DV4/NL % NW == 0) || ty == 0) { + FOR_UNROLL (short ii = 0; ii < DV4/NL; ++ii) { + so4[ii*NL] *= ms; } } } @@ -4545,63 +5498,12 @@ kernel void kernel_flash_attn_ext_vec( } } - // simdgroup reduce (NE = 4) - // [ 0, 8, 16, 24] -> [ 0] - // [ 1, 9, 17, 25] -> [ 1] - // [ 2, 10, 18, 26] -> [ 2] - // [ 3, 11, 19, 27] -> [ 3] - // [ 4, 12, 20, 28] -> [ 4] - // [ 5, 13, 21, 29] -> [ 5] - // [ 6, 14, 22, 30] -> [ 6] - // [ 7, 15, 23, 31] -> [ 7] - for (short ii = 0; ii < DV4; ii += NL) { - if (NE > 1) { - lo[ii/NL][0] += simd_shuffle_down(lo[ii/NL][0], 16); - lo[ii/NL][1] += simd_shuffle_down(lo[ii/NL][1], 16); - lo[ii/NL][2] += simd_shuffle_down(lo[ii/NL][2], 16); - lo[ii/NL][3] += simd_shuffle_down(lo[ii/NL][3], 16); - } - - if (NE > 2) { - lo[ii/NL][0] += simd_shuffle_down(lo[ii/NL][0], 8); - lo[ii/NL][1] += simd_shuffle_down(lo[ii/NL][1], 8); - lo[ii/NL][2] += simd_shuffle_down(lo[ii/NL][2], 8); - lo[ii/NL][3] += simd_shuffle_down(lo[ii/NL][3], 8); - } - - if (NE > 4) { - lo[ii/NL][0] += simd_shuffle_down(lo[ii/NL][0], 4); - lo[ii/NL][1] += simd_shuffle_down(lo[ii/NL][1], 4); - lo[ii/NL][2] += simd_shuffle_down(lo[ii/NL][2], 4); - lo[ii/NL][3] += simd_shuffle_down(lo[ii/NL][3], 4); - } - - if (NE > 8) { - lo[ii/NL][0] += simd_shuffle_down(lo[ii/NL][0], 2); - lo[ii/NL][1] += simd_shuffle_down(lo[ii/NL][1], 2); - lo[ii/NL][2] += simd_shuffle_down(lo[ii/NL][2], 2); - lo[ii/NL][3] += simd_shuffle_down(lo[ii/NL][3], 2); - } - - if (NE > 16) { - lo[ii/NL][0] += simd_shuffle_down(lo[ii/NL][0], 1); - lo[ii/NL][1] += simd_shuffle_down(lo[ii/NL][1], 1); - lo[ii/NL][2] += simd_shuffle_down(lo[ii/NL][2], 1); - lo[ii/NL][3] += simd_shuffle_down(lo[ii/NL][3], 1); - } - } - - threadgroup_barrier(mem_flags::mem_threadgroup); - - // store results to shared memory - for (short i = tiisg; i < DV4; i += NL) { - sr4[i] = lo[i/NL]; - } + so4 -= tiisg; threadgroup_barrier(mem_flags::mem_threadgroup); // parallel reduce - for (short r = nsg/2; r > 0; r >>= 1) { + for (short r = NSG/2; r > 0; r >>= 1) { if (sgitg < r) { const float S0 = ss[ 0]; const float S1 = ss[r*(SH/2) + 0]; @@ -4623,23 +5525,86 @@ kernel void kernel_flash_attn_ext_vec( // O_0 = diag(ms0)*O_0 + diag(ms1)*O_1 for (short i = tiisg; i < DV4; i += NW) { - sr4[i] = sr4[i]*ms0 + sr4[i + r*DV4]*ms1; + so4[i] = so4[i]*ms0 + so4[i + r*PV4]*ms1; } } threadgroup_barrier(mem_flags::mem_threadgroup); } - device float4 * dst4 = (device float4 *) dst; - // final rescale with 1/S and store to global memory if (sgitg == 0) { - const float S = ss[0]; + const int64_t nrows = args.ne3*args.ne2*args.ne1; + const int64_t rid = iq3*args.ne2*args.ne1 + iq2 + iq1*args.ne1; + + device float4 * dst4 = (device float4 *) dst; + device float * dst1 = (device float *) dst + nrows*DV*NWG; // the S and M are stored after the results + const float S = NWG == 1 ? 1.0f/ss[0] : 1.0f; + + // interleave the workgroup data for (short i = tiisg; i < DV4; i += NW) { - dst4[((uint64_t)iq3*args.ne2*args.ne1 + iq2 + (uint64_t)iq1*args.ne1)*DV4 + i] = (float4) sr4[i]/S; + dst4[rid*DV4*NWG + NWG*i + iwg] = (float4) so4[i]*S; + } + + // store S and M + if (NWG > 1) { + if (tiisg == 0) { + dst1[rid*(2*NWG) + 2*iwg + 0] = ss[0]; + dst1[rid*(2*NWG) + 2*iwg + 1] = ss[1]; + } } } + +#undef NWG +#undef NS10 +#undef NS20 +} + +template< + typename q4_t, // query types in shared memory + typename k4_t, // key types in shared memory + typename v4_t, // value types in shared memory + typename qk_t, // Q*K types + typename s_t, // soft-max types + typename s4_t, + typename o4_t, // attention accumulation types + typename kd4_t, // key type in device memory + short nl_k, + void (*deq_k_t4)(device const kd4_t *, short, thread k4_t &), + typename vd4_t, // value type in device memory + short nl_v, + void (*deq_v_t4)(device const vd4_t *, short, thread v4_t &), + short DK, // K head size + short DV, // V head size + short NE = 4, // head elements per thread + short Q = 1, // queries per threadgroup + short C = 32> // cache items per threadgroup +kernel void kernel_flash_attn_ext_vec( + constant ggml_metal_kargs_flash_attn_ext_vec & args, + device const char * q, + device const char * k, + device const char * v, + device const char * mask, + device const char * sinks, + device char * dst, + threadgroup half * shmem_f16 [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { +#define FWD_TMPL q4_t, k4_t, v4_t, qk_t, s_t, s4_t, o4_t, kd4_t, nl_k, deq_k_t4, vd4_t, nl_v, deq_v_t4, DK, DV, NE, Q, C +#define FWD_ARGS args, q, k, v, mask, sinks, dst, shmem_f16, tgpig, tiisg, sgitg + switch (FC_flash_attn_ext_vec_nsg) { + // note: disabled cases to reduce library load time + case 1: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + case 2: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + case 4: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + //case 8: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + //case 16: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + //case 32: kernel_flash_attn_ext_vec_impl(FWD_ARGS); break; + } +#undef FWD_TMPL +#undef FWD_ARGS } // note: I think the s_t can be half instead of float, because the Q*K scaling is done before storing to shared mem @@ -4655,109 +5620,121 @@ kernel void kernel_flash_attn_ext_vec( typedef decltype(kernel_flash_attn_ext_vec) flash_attn_ext_vec_t; -template [[host_name("kernel_flash_attn_ext_vec_f16_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_f16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_h64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk64_dv64")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_h96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk96_dv96")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_h128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk128_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_h192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk192_dv192")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_hk192_hv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk192_dv128")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_h256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; - -template [[host_name("kernel_flash_attn_ext_vec_f16_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_flash_attn_ext_vec_bf16_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk256_dv256")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; + +template [[host_name("kernel_flash_attn_ext_vec_f16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_flash_attn_ext_vec_bf16_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #endif -template [[host_name("kernel_flash_attn_ext_vec_q4_0_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q4_1_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_0_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q5_1_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; -template [[host_name("kernel_flash_attn_ext_vec_q8_0_hk576_hv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q4_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q5_1_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; +template [[host_name("kernel_flash_attn_ext_vec_q8_0_dk576_dv512")]] kernel flash_attn_ext_vec_t kernel_flash_attn_ext_vec; #undef FA_TYPES -template -kernel void kernel_set( - constant ggml_metal_kargs_set & args, - device const char * src0, - device const char * src1, - device char * dst, - uint3 tgpig[[threadgroup_position_in_grid]], - ushort3 tpitg[[thread_position_in_threadgroup]], - ushort3 ntg[[threads_per_threadgroup]]) { - const int i13 = tgpig[2]; - const int i12 = tgpig[1]; - const int i11 = tgpig[0]; +constant int32_t FC_flash_attn_ext_vec_reduce_DV [[function_constant(FC_FLASH_ATTN_EXT_VEC_REDUCE + 0)]]; +constant int32_t FC_flash_attn_ext_vec_reduce_NWG [[function_constant(FC_FLASH_ATTN_EXT_VEC_REDUCE + 1)]]; + +kernel void kernel_flash_attn_ext_vec_reduce( + constant ggml_metal_kargs_flash_attn_ext_vec_reduce & args, + device const char * htmp, + device char * dst, + uint tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { +#define NWG (FC_flash_attn_ext_vec_reduce_NWG) +#define DV (FC_flash_attn_ext_vec_reduce_DV) - const int64_t n = i13*args.ne12*args.ne11*args.ne10 + i12*args.ne11*args.ne10 + i11*args.ne10; + const uint64_t rid = tgpig; - const int64_t i3 = n / (args.ne12*args.ne11*args.ne10); - const int64_t i2 = (n - i3*args.ne12*args.ne11*args.ne10) / (args.ne11*args.ne10); - const int64_t i1 = (n - i3*args.ne12*args.ne11*args.ne10 - i2*args.ne11*args.ne10) / args.ne10; + const short iwg = tiisg; - device T * dst_data = (device T *) (dst + i3*args.nb3 + i2*args.nb2 + i1*args.nb1 + args.offs); + device const float * ss = (device const float *) htmp + (uint64_t)args.nrows*DV*NWG; - for (int64_t i10 = tpitg.x; i10 < args.ne10; i10 += ntg.x) { - device const T * src = (device T *) (src1 + i13*args.nb13 + i12*args.nb12 + i11*args.nb11 + i10*args.nb10); - dst_data[i10] = (T) src[0]; - } -} + float S = ss[rid*(2*NWG) + 2*iwg + 0]; + float M = ss[rid*(2*NWG) + 2*iwg + 1]; + + const float m = simd_max(M); + const float ms = exp(M - m); -typedef decltype(kernel_set) kernel_set_t; + S = 1.0f/simd_sum(S*ms); -template [[host_name("kernel_set_f32")]] kernel kernel_set_t kernel_set; -template [[host_name("kernel_set_i32")]] kernel kernel_set_t kernel_set; + const short DV4 = DV/4; + + device const float4 * htmp4 = (device const float4 *) htmp + rid*DV4*NWG; + device float4 * dst4 = (device float4 *) dst + rid*DV4; + + for (short i = sgitg; i < DV4; i += NWG) { + const float4 v = simd_sum(htmp4[i*NWG + iwg]*ms); + + if (iwg == 0) { + dst4[i] = v*S; + } + } + +#undef NWG +#undef DV +} template kernel void kernel_cpy( @@ -4795,12 +5772,14 @@ typedef decltype(kernel_cpy; template [[host_name("kernel_cpy_f32_f16")]] kernel kernel_cpy_t kernel_cpy; -#if defined(GGML_METAL_USE_BF16) +template [[host_name("kernel_cpy_f32_i32")]] kernel kernel_cpy_t kernel_cpy; +template [[host_name("kernel_cpy_i32_f32")]] kernel kernel_cpy_t kernel_cpy; +#if defined(GGML_METAL_HAS_BF16) template [[host_name("kernel_cpy_f32_bf16")]] kernel kernel_cpy_t kernel_cpy; #endif template [[host_name("kernel_cpy_f16_f32")]] kernel kernel_cpy_t kernel_cpy; template [[host_name("kernel_cpy_f16_f16")]] kernel kernel_cpy_t kernel_cpy; -#if defined(GGML_METAL_USE_BF16) +#if defined(GGML_METAL_HAS_BF16) template [[host_name("kernel_cpy_bf16_f32")]] kernel kernel_cpy_t kernel_cpy; template [[host_name("kernel_cpy_bf16_bf16")]] kernel kernel_cpy_t kernel_cpy; #endif @@ -5042,7 +6021,7 @@ kernel void kernel_concat( } } -template +template void kernel_mul_mv_q2_K_f32_impl( args_t args, device const char * src0, @@ -5052,13 +6031,15 @@ void kernel_mul_mv_q2_K_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5142,10 +6123,10 @@ kernel void kernel_mul_mv_q2_K_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q2_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q2_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_q3_K_f32_impl( args_t args, device const char * src0, @@ -5155,6 +6136,7 @@ void kernel_mul_mv_q3_K_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; @@ -5162,7 +6144,7 @@ void kernel_mul_mv_q3_K_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5306,10 +6288,10 @@ kernel void kernel_mul_mv_q3_K_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q3_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q3_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_q4_K_f32_impl( args_t args, device const char * src0, @@ -5319,9 +6301,11 @@ void kernel_mul_mv_q4_K_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { - const uint16_t kmask1 = 0x3f3f; - const uint16_t kmask2 = 0x0f0f; - const uint16_t kmask3 = 0xc0c0; + const short NSG = FC_mul_mv_nsg; + + constexpr uint16_t kmask1 = 0x3f3f; + constexpr uint16_t kmask2 = 0x0f0f; + constexpr uint16_t kmask3 = 0xc0c0; const short ix = tiisg/8; // 0...3 const short it = tiisg%8; // 0...7 @@ -5334,7 +6318,7 @@ void kernel_mul_mv_q4_K_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5380,7 +6364,7 @@ void kernel_mul_mv_q4_K_f32_impl( float4 acc1 = {0.f, 0.f, 0.f, 0.f}; float4 acc2 = {0.f, 0.f, 0.f, 0.f}; - for (short i = 0; i < 4; ++i) { + FOR_UNROLL (short i = 0; i < 4; ++i) { acc1[0] += yl[2*i + 0] * (q1[i] & 0x000F); acc1[1] += yl[2*i + 1] * (q1[i] & 0x0F00); acc1[2] += yl[2*i + 8] * (q1[i] & 0x00F0); @@ -5391,14 +6375,11 @@ void kernel_mul_mv_q4_K_f32_impl( acc2[3] += yh[2*i + 9] * (q2[i] & 0xF000); } - float dall = dh[0]; - float dmin = dh[1]; - - sumf[row] += dall * ((acc1[0] + 1.f/256.f * acc1[1]) * sc8[0] + - (acc1[2] + 1.f/256.f * acc1[3]) * sc8[1] * 1.f/16.f + - (acc2[0] + 1.f/256.f * acc2[1]) * sc8[4] + - (acc2[2] + 1.f/256.f * acc2[3]) * sc8[5] * 1.f/16.f) - - dmin * (sumy[0] * sc8[2] + sumy[1] * sc8[3] + sumy[2] * sc8[6] + sumy[3] * sc8[7]); + sumf[row] += dh[0] * ((acc1[0] + 1.f/256.f * acc1[1]) * sc8[0] + + (acc1[2] + 1.f/256.f * acc1[3]) * sc8[1] * 1.f/16.f + + (acc2[0] + 1.f/256.f * acc2[1]) * sc8[4] + + (acc2[2] + 1.f/256.f * acc2[3]) * sc8[5] * 1.f/16.f) - + dh[1] * (sumy[0] * sc8[2] + sumy[1] * sc8[3] + sumy[2] * sc8[6] + sumy[3] * sc8[7]); q1 += args.nb01/2; sc += args.nb01/2; @@ -5428,10 +6409,10 @@ kernel void kernel_mul_mv_q4_K_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q4_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q4_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_q5_K_f32_impl( args_t args, device const char * src0, @@ -5441,6 +6422,7 @@ void kernel_mul_mv_q5_K_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; @@ -5448,7 +6430,7 @@ void kernel_mul_mv_q5_K_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5463,9 +6445,9 @@ void kernel_mul_mv_q5_K_f32_impl( float yl[16], yh[16]; - const uint16_t kmask1 = 0x3f3f; - const uint16_t kmask2 = 0x0f0f; - const uint16_t kmask3 = 0xc0c0; + constexpr uint16_t kmask1 = 0x3f3f; + constexpr uint16_t kmask2 = 0x0f0f; + constexpr uint16_t kmask3 = 0xc0c0; const short tid = tiisg/4; const short ix = tiisg%4; @@ -5511,7 +6493,7 @@ void kernel_mul_mv_q5_K_f32_impl( float4 acc1 = {0.f}; float4 acc2 = {0.f}; - for (short l = 0; l < 8; ++l) { + FOR_UNROLL (short l = 0; l < 8; ++l) { uint8_t h = qh[l]; acc1[0] += yl[l+0] * (q1[l] & 0x0F); acc1[1] += yl[l+8] * (q1[l] & 0xF0); @@ -5522,13 +6504,12 @@ void kernel_mul_mv_q5_K_f32_impl( acc2[2] += h & hm3 ? yh[l+0] : 0.f; acc2[3] += h & hm4 ? yh[l+8] : 0.f; } - const float dall = dh[0]; - const float dmin = dh[1]; - sumf[row] += dall * (sc8[0] * (acc1[0] + 16.f*acc2[0]) + - sc8[1] * (acc1[1]/16.f + 16.f*acc2[1]) + - sc8[4] * (acc1[2] + 16.f*acc2[2]) + - sc8[5] * (acc1[3]/16.f + 16.f*acc2[3])) - - dmin * (sumy[0] * sc8[2] + sumy[1] * sc8[3] + sumy[2] * sc8[6] + sumy[3] * sc8[7]); + + sumf[row] += dh[0] * (sc8[0] * (acc1[0] + 16.f*acc2[0]) + + sc8[1] * (acc1[1]/16.f + 16.f*acc2[1]) + + sc8[4] * (acc1[2] + 16.f*acc2[2]) + + sc8[5] * (acc1[3]/16.f + 16.f*acc2[3])) - + dh[1] * (sumy[0] * sc8[2] + sumy[1] * sc8[3] + sumy[2] * sc8[6] + sumy[3] * sc8[7]); q1 += args.nb01; qh += args.nb01; @@ -5559,10 +6540,10 @@ kernel void kernel_mul_mv_q5_K_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q5_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q5_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_q6_K_f32_impl( args_t args, device const char * src0, @@ -5572,11 +6553,12 @@ void kernel_mul_mv_q6_K_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; - const uint8_t kmask1 = 0x03; - const uint8_t kmask2 = 0x0C; - const uint8_t kmask3 = 0x30; - const uint8_t kmask4 = 0xC0; + constexpr uint8_t kmask1 = 0x03; + constexpr uint8_t kmask2 = 0x0C; + constexpr uint8_t kmask3 = 0x30; + constexpr uint8_t kmask4 = 0xC0; const int nb = args.ne00/QK_K; @@ -5584,7 +6566,7 @@ void kernel_mul_mv_q6_K_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5627,18 +6609,16 @@ void kernel_mul_mv_q6_K_f32_impl( } for (short row = 0; row < nr0; ++row) { - const float dall = dh[0]; - float4 sums = {0.f, 0.f, 0.f, 0.f}; - for (short l = 0; l < 4; ++l) { + FOR_UNROLL (short l = 0; l < 4; ++l) { sums[0] += yl[4*l + 0] * ((int8_t)((q1[l] & 0xF) | ((qh[l] & kmask1) << 4)) - 32); sums[1] += yl[4*l + 1] * ((int8_t)((q2[l] & 0xF) | ((qh[l] & kmask2) << 2)) - 32); sums[2] += yl[4*l + 2] * ((int8_t)((q1[l] >> 4) | ((qh[l] & kmask3) << 0)) - 32); sums[3] += yl[4*l + 3] * ((int8_t)((q2[l] >> 4) | ((qh[l] & kmask4) >> 2)) - 32); } - sumf[row] += dall * (sums[0] * sc[0] + sums[1] * sc[2] + sums[2] * sc[4] + sums[3] * sc[6]); + sumf[row] += dh[0] * (sums[0] * sc[0] + sums[1] * sc[2] + sums[2] * sc[4] + sums[3] * sc[6]); q1 += args.nb01; q2 += args.nb01; @@ -5668,12 +6648,12 @@ kernel void kernel_mul_mv_q6_K_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_q6_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_q6_K_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } // ======================= "True" 2-bit -template +template void kernel_mul_mv_iq2_xxs_f32_impl( args_t args, device const char * src0, @@ -5683,13 +6663,15 @@ void kernel_mul_mv_iq2_xxs_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5776,10 +6758,10 @@ kernel void kernel_mul_mv_iq2_xxs_f32( uint3 tgpig[[threadgroup_position_in_grid]], ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq2_xxs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq2_xxs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq2_xs_f32_impl( args_t args, device const char * src0, @@ -5789,13 +6771,15 @@ void kernel_mul_mv_iq2_xs_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -5893,10 +6877,10 @@ kernel void kernel_mul_mv_iq2_xs_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq2_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq2_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq3_xxs_f32_impl( args_t args, device const char * src0, @@ -5906,13 +6890,15 @@ void kernel_mul_mv_iq3_xxs_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6003,10 +6989,10 @@ kernel void kernel_mul_mv_iq3_xxs_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq3_xxs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq3_xxs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq3_s_f32_impl( args_t args, device const char * src0, @@ -6016,13 +7002,15 @@ void kernel_mul_mv_iq3_s_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6113,10 +7101,10 @@ kernel void kernel_mul_mv_iq3_s_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq3_s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq3_s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq2_s_f32_impl( args_t args, device const char * src0, @@ -6126,13 +7114,15 @@ void kernel_mul_mv_iq2_s_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6224,10 +7214,10 @@ kernel void kernel_mul_mv_iq2_s_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq2_s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq2_s_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq1_s_f32_impl( args_t args, device const char * src0, @@ -6237,13 +7227,15 @@ void kernel_mul_mv_iq1_s_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6321,10 +7313,10 @@ kernel void kernel_mul_mv_iq1_s_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq1_s_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_iq1_s_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq1_m_f32_impl( args_t args, device const char * src0, @@ -6334,6 +7326,7 @@ void kernel_mul_mv_iq1_m_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; const int nb = args.ne00/QK_K; @@ -6341,7 +7334,7 @@ void kernel_mul_mv_iq1_m_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6429,10 +7422,10 @@ kernel void kernel_mul_mv_iq1_m_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq1_m_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); + kernel_mul_mv_iq1_m_f32_impl(args, src0, src1, dst, nullptr, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq4_nl_f32_impl( args_t args, device const char * src0, @@ -6442,6 +7435,7 @@ void kernel_mul_mv_iq4_nl_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; threadgroup float * shmem_f32 = (threadgroup float *) shmem; const int nb = args.ne00/QK4_NL; @@ -6450,7 +7444,7 @@ void kernel_mul_mv_iq4_nl_f32_impl( const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6535,10 +7529,10 @@ kernel void kernel_mul_mv_iq4_nl_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq4_nl_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq4_nl_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -template +template void kernel_mul_mv_iq4_xs_f32_impl( args_t args, device const char * src0, @@ -6548,13 +7542,15 @@ void kernel_mul_mv_iq4_xs_f32_impl( uint3 tgpig, ushort tiisg, ushort sgitg) { + const short NSG = FC_mul_mv_nsg; threadgroup float * shmem_f32 = (threadgroup float *) shmem; const int nb = args.ne00/QK_K; + const int r0 = tgpig.x; const int r1 = tgpig.y; const int im = tgpig.z; - const int first_row = (r0 * nsg + sgitg) * nr0; + const int first_row = (r0 * NSG + sgitg) * nr0; const uint i12 = im%args.ne12; const uint i13 = im/args.ne12; @@ -6640,7 +7636,97 @@ kernel void kernel_mul_mv_iq4_xs_f32( ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - kernel_mul_mv_iq4_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); + kernel_mul_mv_iq4_xs_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); +} + +template +void kernel_mul_mv_mxfp4_f32_impl( + args_t args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem, + uint3 tgpig, + ushort tiisg, + ushort sgitg) { + const short NSG = FC_mul_mv_nsg; + + threadgroup float * shmem_f32 = (threadgroup float *) shmem; + const int nb = args.ne00/QK_MXFP4; + + const int r0 = tgpig.x; + const int r1 = tgpig.y; + const int im = tgpig.z; + + const int first_row = (r0 * NSG + sgitg) * nr0; + + const uint i12 = im%args.ne12; + const uint i13 = im/args.ne12; + + const uint64_t offset0 = first_row*args.nb01 + (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const uint64_t offset1 = r1*args.nb11 + (i12 )*args.nb12 + (i13 )*args.nb13; + + device const block_mxfp4 * x = (device const block_mxfp4 *) (src0 + offset0); + device const float * y = (device const float *) (src1 + offset1); + + const short ix = tiisg/2; // 0...15 + const short it = tiisg%2; // 0 or 1 + + shmem_f32[tiisg] = kvalues_mxfp4_f[tiisg%16]; + threadgroup_barrier(mem_flags::mem_threadgroup); + + float4 yl[4]; + float sumf[nr0]={0.f}; + + device const float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += 16) { + device const float4 * y4 = (device const float4 *)yb; + yl[0] = y4[0]; + yl[1] = y4[4]; + yl[2] = y4[1]; + yl[3] = y4[5]; + +#pragma unroll(nr0) + for (short row = 0; row < nr0; row++) { + device const block_mxfp4 & xb = x[row*nb + ib]; + device const uint8_t * q2 = (device const uint8_t *)(xb.qs + 8*it); + + float4 acc1 = yl[0]*float4(shmem_f32[q2[0] & 0x0F], shmem_f32[q2[1] & 0x0F], shmem_f32[q2[2] & 0x0F], shmem_f32[q2[3] & 0x0F]); + float4 acc2 = yl[1]*float4(shmem_f32[q2[0] >> 4 ], shmem_f32[q2[1] >> 4 ], shmem_f32[q2[2] >> 4 ], shmem_f32[q2[3] >> 4 ]); + float4 acc3 = yl[2]*float4(shmem_f32[q2[4] & 0x0F], shmem_f32[q2[5] & 0x0F], shmem_f32[q2[6] & 0x0F], shmem_f32[q2[7] & 0x0F]); + float4 acc4 = yl[3]*float4(shmem_f32[q2[4] >> 4 ], shmem_f32[q2[5] >> 4 ], shmem_f32[q2[6] >> 4 ], shmem_f32[q2[7] >> 4 ]); + + acc1 = (acc1 + acc3) + (acc2 + acc4); + + sumf[row] += e8m0_to_fp32(xb.e) * ((acc1[0] + acc1[1]) + (acc1[2] + acc1[3])); + } + + yb += 16 * QK_MXFP4; + } + + device float * dst_f32 = (device float *) dst + (uint64_t)im*args.ne0*args.ne1 + (uint64_t)r1*args.ne0; + + for (int row = 0; row < nr0 && first_row + row < args.ne0; ++row) { + float sum_all = simd_sum(sumf[row]); + if (tiisg == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} + +[[host_name("kernel_mul_mv_mxfp4_f32")]] +kernel void kernel_mul_mv_mxfp4_f32( + constant ggml_metal_kargs_mul_mv & args, + device const char * src0, + device const char * src1, + device char * dst, + threadgroup char * shmem [[threadgroup(0)]], + uint3 tgpig[[threadgroup_position_in_grid]], + ushort tiisg[[thread_index_in_simdgroup]], + ushort sgitg[[simdgroup_index_in_threadgroup]]) { + + kernel_mul_mv_mxfp4_f32_impl(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } template @@ -6709,7 +7795,7 @@ kernel void kernel_get_rows_i32( } } -template +template kernel void kernel_set_rows_q32( constant ggml_metal_kargs_set_rows & args, device const void * src0, @@ -6730,7 +7816,7 @@ kernel void kernel_set_rows_q32( } const int32_t i10 = i01; - const int64_t i1 = ((const device int64_t *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; + const TI i1 = ((const device TI *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; device block_q * dst_row = ( device block_q *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); const device float * src_row = (const device float *) ((const device char *) src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); @@ -6740,7 +7826,7 @@ kernel void kernel_set_rows_q32( } } -template +template kernel void kernel_set_rows_f( constant ggml_metal_kargs_set_rows & args, device const void * src0, @@ -6761,9 +7847,9 @@ kernel void kernel_set_rows_f( } const int32_t i10 = i01; - const int64_t i1 = ((const device int64_t *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; + const TI i1 = ((const device TI *) ((const device char *) src1 + i10*args.nb10 + i11*args.nb11 + i12*args.nb12))[0]; - device T * dst_row = ( device T *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); + device T * dst_row = ( device T *) (( device char *) dst + i1*args.nb1 + i02*args.nb2 + i03*args.nb3); const device float * src_row = (const device float *) ((const device char *) src0 + i01*args.nb01 + i02*args.nb02 + i03*args.nb03); for (int ind = tiitg%tptg.x; ind < args.nk0; ind += tptg.x) { @@ -6771,6 +7857,9 @@ kernel void kernel_set_rows_f( } } +constant bool FC_mul_mm_bc_inp [[function_constant(FC_MUL_MM + 0)]]; +constant bool FC_mul_mm_bc_out [[function_constant(FC_MUL_MM + 1)]]; + #define BLOCK_SIZE_M 64 // 8 simdgroup matrices from matrix A #define BLOCK_SIZE_N 32 // 4 simdgroup matrices from matrix B #define BLOCK_SIZE_K 32 @@ -6783,7 +7872,7 @@ kernel void kernel_set_rows_f( #define SG_MAT_ROW 8 // each block_q contains 16*nl weights -template +template kernel void kernel_mul_mm( constant ggml_metal_kargs_mul_mm & args, device const char * src0, @@ -6794,8 +7883,8 @@ kernel void kernel_mul_mm( ushort tiitg[[thread_index_in_threadgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - threadgroup T * sa = (threadgroup T *)(shmem); - threadgroup float * sb = (threadgroup float *)(shmem + 4096); + threadgroup S0 * sa = (threadgroup S0 *)(shmem); + threadgroup S1 * sb = (threadgroup S1 *)(shmem + 4096); const int r0 = tgpig.y; const int r1 = tgpig.x; @@ -6809,8 +7898,9 @@ kernel void kernel_mul_mm( const short thread_row = ((short)tiitg/THREAD_PER_ROW) < n_rows ? ((short)tiitg/THREAD_PER_ROW) : n_rows - 1; const short thread_col = ((short)tiitg/THREAD_PER_COL) < n_cols ? ((short)tiitg/THREAD_PER_COL) : n_cols - 1; - simdgroup_T8x8 ma[4]; - simdgroup_float8x8 mb[2]; + S0_8x8 ma[4]; + S1_8x8 mb[2]; + simdgroup_float8x8 mc[8]; for (short i = 0; i < 8; i++){ @@ -6828,27 +7918,45 @@ kernel void kernel_mul_mm( device const block_q * x = (device const block_q *)(src0 + args.nb01*(r0*BLOCK_SIZE_M + thread_row) + offset0) + offset1; - device const float * y = (device const float *)(src1 + const short iy = (BLOCK_SIZE_K / THREAD_PER_COL * (tiitg % THREAD_PER_COL)); + + device const T1 * y = (device const T1 *)(src1 + args.nb13*i13 + args.nb12*i12 + args.nb11*(r1*BLOCK_SIZE_N + thread_col) - + args.nb10*(BLOCK_SIZE_K / THREAD_PER_COL * (tiitg % THREAD_PER_COL))); + + args.nb10*iy); for (int loop_k = 0; loop_k < args.ne00; loop_k += BLOCK_SIZE_K) { // load data and store to threadgroup memory - T4x4 temp_a; - dequantize_func(x, il, temp_a); + if (is_same::value && FC_mul_mm_bc_inp) { + threadgroup_barrier(mem_flags::mem_threadgroup); - threadgroup_barrier(mem_flags::mem_threadgroup); + // no need for dequantization + for (short i = 0; i < 16; i++) { + *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ + + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ + + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = loop_k + 16*il + i < args.ne00 ? ((device T0 *) x)[i] : 0; + } + } else { + S0_4x4 temp_a; + dequantize_func(x, il, temp_a); - #pragma unroll(16) - for (short i = 0; i < 16; i++) { - *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ - + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ - + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = temp_a[i/4][i%4]; + threadgroup_barrier(mem_flags::mem_threadgroup); + + FOR_UNROLL (short i = 0; i < 16; i++) { + *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ + + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ + + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = temp_a[i/4][i%4]; + } } - *(threadgroup float2x4 *)(sb + 32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL)) = *((device float2x4 *) y); + if (FC_mul_mm_bc_inp) { + for (short i = 0; i < 8; ++i) { + sb[32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL) + i] = loop_k + iy + i < args.ne00 ? (S1) ((device T1 *) y)[i] : 0; + } + } else { + *(threadgroup S1_2x4 *)(sb + 32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL)) = (S1_2x4)(*((device T1_2x4 *) y)); + } il = (il + 2 < nl) ? il + 2 : il % 2; x = (il < 2) ? x + (2 + nl - 1)/nl : x; @@ -6857,23 +7965,25 @@ kernel void kernel_mul_mm( threadgroup_barrier(mem_flags::mem_threadgroup); // load matrices from threadgroup memory and conduct outer products - threadgroup const T * lsma = (sa + THREAD_MAT_M*SG_MAT_SIZE*(sgitg%2)); - threadgroup const float * lsmb = (sb + THREAD_MAT_N*SG_MAT_SIZE*(sgitg/2)); + threadgroup const S0 * lsma = (sa + THREAD_MAT_M*SG_MAT_SIZE*(sgitg%2)); + threadgroup const S1 * lsmb = (sb + THREAD_MAT_N*SG_MAT_SIZE*(sgitg/2)); #pragma unroll(4) for (short ik = 0; ik < BLOCK_SIZE_K/8; ik++) { + simdgroup_barrier(mem_flags::mem_none); + #pragma unroll(4) for (short i = 0; i < 4; i++) { simdgroup_load(ma[i], lsma + SG_MAT_SIZE * i); } - simdgroup_barrier(mem_flags::mem_none); - #pragma unroll(2) for (short i = 0; i < 2; i++) { simdgroup_load(mb[i], lsmb + SG_MAT_SIZE * i); } + simdgroup_barrier(mem_flags::mem_none); + #pragma unroll(8) for (short i = 0; i < 8; i++){ simdgroup_multiply_accumulate(mc[i], mb[i/4], ma[i%4], mc[i]); @@ -6884,7 +7994,8 @@ kernel void kernel_mul_mm( } } - if ((r0 + 1) * BLOCK_SIZE_M <= args.ne0 && (r1 + 1) * BLOCK_SIZE_N <= args.ne1) { + if (!FC_mul_mm_bc_out || ((r0 + 1) * BLOCK_SIZE_M <= args.ne0 && (r1 + 1) * BLOCK_SIZE_N <= args.ne1)) { + // if no bounds checks on the output are needed, we can directly write to device memory device float * C = (device float *) dst + (BLOCK_SIZE_M * r0 + 32*(sgitg & 1)) + \ (BLOCK_SIZE_N * r1 + 16*(sgitg >> 1)) * args.ne0 + im*args.ne1*args.ne0; @@ -6925,124 +8036,111 @@ kernel void kernel_mul_mm( } } -template +template // n_expert_used kernel void kernel_mul_mm_id_map0( constant ggml_metal_kargs_mul_mm_id_map0 & args, - device const char * src1, device const char * src2, - device char * hsrc1, device char * htpe, device char * hids, - uint3 tgpig[[threadgroup_position_in_grid]], - ushort3 tpitg[[thread_position_in_threadgroup]], - ushort3 ntg[[threads_per_threadgroup]]) { - const int ide = tgpig[0]; // expert id - - int n_all = 0; - - device int32_t * ids_i32 = (device int32_t *) (hids); + threadgroup char * shmem [[threadgroup(0)]], + ushort tpitg[[thread_position_in_threadgroup]], + ushort ntg[[threads_per_threadgroup]]) { + const short ide = tpitg; // expert id - for (int i21 = 0; i21 < args.neh11; i21++) { // n_tokens - device const int32_t * src2_i32 = (device const int32_t *) (src2 + i21*args.nb21); + uint32_t n_all = 0; - for (int i20 = 0; i20 < args.ne20; i20++) { // n_expert_used - if (src2_i32[i20] != ide) { - continue; - } + device int32_t * ids_i32 = (device int32_t *) hids + ide*args.ne21; - device const float4 * src1_f32x4 = (device const float4 *) ( src1 + i21*args.nb12 + (i20%args.ne11)*args.nb11); - device T4 * hsrc1_f32x4 = (device T4 *) (hsrc1 + (ide*args.neh11 + n_all)*args.nbh11); + for (int i21 = 0; i21 < args.ne21; i21 += ntg) { // n_tokens + if (i21 + tpitg < args.ne21) { + device const int32_t * src2_i32 = (device const int32_t *) (src2 + (i21 + tpitg)*args.nb21); - for (int64_t i00 = tpitg.x; i00 < args.ne10/4; i00 += ntg.x) { - hsrc1_f32x4[i00] = (T4) (src1_f32x4[i00]); - } + threadgroup uint16_t * sids = (threadgroup uint16_t *) shmem + tpitg*ne20; - if (tpitg.x == 0) { - ids_i32[i21*args.ne20 + i20] = ide*args.neh11 + n_all; + #pragma unroll(ne20) + for (short i20 = 0; i20 < ne20; i20++) { + sids[i20] = src2_i32[i20]; } - - ++n_all; } - } - - if (tpitg.x == 0) { - device int32_t * tpe_i32 = (device int32_t *) (htpe); - tpe_i32[ide] = n_all; - } -} - -typedef decltype(kernel_mul_mm_id_map0) kernel_mul_mm_id_map0_t; -template [[host_name("kernel_mul_mm_id_map0_f16")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0; + threadgroup_barrier(mem_flags::mem_threadgroup); -template -kernel void kernel_mul_mm_id_map1( - constant ggml_metal_kargs_mul_mm_id_map1 & args, - device const char * hdst, - device const char * hids, - device char * dst, - uint3 tgpig[[threadgroup_position_in_grid]], - ushort3 tpitg[[thread_position_in_threadgroup]], - ushort3 ntg[[threads_per_threadgroup]]) { - const int i20 = tgpig[0]; // used expert - const int i21 = tgpig[1]; // token + for (short t = 0; t < ntg; t++) { + if (i21 + t >= args.ne21) { + break; + } - device const int32_t * ids_i32 = (device const int32_t *) (hids); - device float4 * dst_f32x4 = (device float4 *) (dst + i20*args.nb1 + i21*args.nb2); + threadgroup const uint16_t * sids = (threadgroup const uint16_t *) shmem + t*ne20; - const int id = ids_i32[i21*args.ne20 + i20]; + short sel = 0; + #pragma unroll(ne20) + for (short i20 = 0; i20 < ne20; i20++) { + sel += (sids[i20] == ide)*(i20 + 1); + } - const int ide = id / args.neh1; - const int idt = id % args.neh1; + ids_i32[n_all] = (i21 + t)*ne20 + sel - 1; - device const float4 * hdst_f32x4 = (device const float4 *) (hdst + idt*args.nbh1 + ide*args.nbh2); + n_all += sel > 0; + } - for (int64_t i0 = tpitg.x; i0 < args.neh0/4; i0 += ntg.x) { - dst_f32x4[i0] = hdst_f32x4[i0]; + threadgroup_barrier(mem_flags::mem_threadgroup); } + + device uint32_t * tpe_u32 = (device uint32_t *) (htpe); + tpe_u32[ide] = n_all; } -typedef decltype(kernel_mul_mm_id_map1) kernel_mul_mm_id_map1_t; +typedef decltype(kernel_mul_mm_id_map0<1>) kernel_mul_mm_id_map0_t; -template [[host_name("kernel_mul_mm_id_map1_f32")]] kernel kernel_mul_mm_id_map1_t kernel_mul_mm_id_map1; +template [[host_name("kernel_mul_mm_id_map0_ne20_1" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<1>; +template [[host_name("kernel_mul_mm_id_map0_ne20_2" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<2>; +template [[host_name("kernel_mul_mm_id_map0_ne20_4" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<4>; +template [[host_name("kernel_mul_mm_id_map0_ne20_6" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<6>; +template [[host_name("kernel_mul_mm_id_map0_ne20_8" )]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<8>; +template [[host_name("kernel_mul_mm_id_map0_ne20_10")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<10>; +template [[host_name("kernel_mul_mm_id_map0_ne20_16")]] kernel kernel_mul_mm_id_map0_t kernel_mul_mm_id_map0<16>; -template +template kernel void kernel_mul_mm_id( constant ggml_metal_kargs_mul_mm_id & args, device const char * src0, device const char * src1, - device const char * tpe, + device const char * htpe, + device const char * hids, device char * dst, threadgroup char * shmem [[threadgroup(0)]], uint3 tgpig[[threadgroup_position_in_grid]], ushort tiitg[[thread_index_in_threadgroup]], + ushort tiisg[[thread_index_in_simdgroup]], ushort sgitg[[simdgroup_index_in_threadgroup]]) { - threadgroup T * sa = (threadgroup T *)(shmem); - threadgroup half * sb = (threadgroup half *)(shmem + 4096); + threadgroup S0 * sa = (threadgroup S0 *)(shmem); + threadgroup S1 * sb = (threadgroup S1 *)(shmem + 4096); const int r0 = tgpig.y; const int r1 = tgpig.x; - const int im = tgpig.z; + const int im = tgpig.z; // expert - device const int32_t * tpe_i32 = (device const int32_t *) (tpe); + device const uint32_t * tpe_u32 = (device const uint32_t *) (htpe); + device const int32_t * ids_i32 = (device const int32_t *) (hids); - const int neh1 = tpe_i32[im]; + const int32_t neh1 = tpe_u32[im]; if (r1*BLOCK_SIZE_N >= neh1) { return; } // if this block is of 64x32 shape or smaller - const short n_rows = (args.neh0 - r0*BLOCK_SIZE_M < BLOCK_SIZE_M) ? (args.neh0 - r0*BLOCK_SIZE_M) : BLOCK_SIZE_M; - const short n_cols = ( neh1 - r1*BLOCK_SIZE_N < BLOCK_SIZE_N) ? ( neh1 - r1*BLOCK_SIZE_N) : BLOCK_SIZE_N; + const short n_rows = (args.ne0 - r0*BLOCK_SIZE_M < BLOCK_SIZE_M) ? (args.ne0 - r0*BLOCK_SIZE_M) : BLOCK_SIZE_M; + const short n_cols = ( neh1 - r1*BLOCK_SIZE_N < BLOCK_SIZE_N) ? ( neh1 - r1*BLOCK_SIZE_N) : BLOCK_SIZE_N; // a thread shouldn't load data outside of the matrix const short thread_row = ((short)tiitg/THREAD_PER_ROW) < n_rows ? ((short)tiitg/THREAD_PER_ROW) : n_rows - 1; const short thread_col = ((short)tiitg/THREAD_PER_COL) < n_cols ? ((short)tiitg/THREAD_PER_COL) : n_cols - 1; - simdgroup_T8x8 ma[4]; - simdgroup_half8x8 mb[2]; + S0_8x8 ma[4]; + S1_8x8 mb[2]; + simdgroup_float8x8 mc[8]; for (short i = 0; i < 8; i++){ @@ -7051,36 +8149,57 @@ kernel void kernel_mul_mm_id( short il = (tiitg % THREAD_PER_ROW); - const int i12 = im%args.neh12; - const int i13 = im/args.neh12; + const int id = ids_i32[im*args.ne21 + r1*BLOCK_SIZE_N + thread_col]; - const uint64_t offset0 = (i12/args.r2)*args.nb02 + (i13/args.r3)*args.nb03; + const short i11 = (id % args.ne20) % args.ne11; + const short i12 = (id / args.ne20); + const short i13 = 0; + + const uint64_t offset0 = im*args.nb02 + i13*args.nb03; const short offset1 = il/nl; device const block_q * x = (device const block_q *)(src0 + args.nb01*(r0*BLOCK_SIZE_M + thread_row) + offset0) + offset1; - device const half * y = (device const half *)(src1 - + args.nbh13*i13 - + args.nbh12*i12 - + args.nbh11*(r1*BLOCK_SIZE_N + thread_col) - + args.nbh10*(BLOCK_SIZE_K / THREAD_PER_COL * (tiitg % THREAD_PER_COL))); + const short iy = (BLOCK_SIZE_K / THREAD_PER_COL * (tiitg % THREAD_PER_COL)); + + device const T1 * y = (device const T1 *)(src1 + + args.nb13*i13 + + args.nb12*i12 + + args.nb11*i11 + + args.nb10*iy); for (int loop_k = 0; loop_k < args.ne00; loop_k += BLOCK_SIZE_K) { // load data and store to threadgroup memory - T4x4 temp_a; - dequantize_func(x, il, temp_a); + if (is_same::value && FC_mul_mm_bc_inp) { + threadgroup_barrier(mem_flags::mem_threadgroup); - threadgroup_barrier(mem_flags::mem_threadgroup); + // no need for dequantization + for (short i = 0; i < 16; i++) { + *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ + + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ + + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = loop_k + 16*il + i < args.ne00 ? ((device T0 *) x)[i] : 0; + } + } else { + S0_4x4 temp_a; + dequantize_func(x, il, temp_a); - #pragma unroll(16) - for (short i = 0; i < 16; i++) { - *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ - + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ - + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = temp_a[i/4][i%4]; + threadgroup_barrier(mem_flags::mem_threadgroup); + + FOR_UNROLL (short i = 0; i < 16; i++) { + *(sa + SG_MAT_SIZE * ((tiitg/THREAD_PER_ROW/8) \ + + (tiitg%THREAD_PER_ROW)*16 + (i/8)*8) \ + + (tiitg/THREAD_PER_ROW)%8 + (i&7)*8) = temp_a[i/4][i%4]; + } } - *(threadgroup half2x4 *)(sb + 32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL)) = *((device half2x4 *) y); + if (FC_mul_mm_bc_inp) { + for (short i = 0; i < 8; ++i) { + sb[32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL) + i] = loop_k + iy + i < args.ne00 ? (S1) ((device T1 *) y)[i] : 0; + } + } else { + *(threadgroup S1_2x4 *)(sb + 32*8*(tiitg%THREAD_PER_COL) + 8*(tiitg/THREAD_PER_COL)) = (S1_2x4)(*((device T1_2x4 *) y)); + } il = (il + 2 < nl) ? il + 2 : il % 2; x = (il < 2) ? x + (2 + nl - 1)/nl : x; @@ -7089,8 +8208,8 @@ kernel void kernel_mul_mm_id( threadgroup_barrier(mem_flags::mem_threadgroup); // load matrices from threadgroup memory and conduct outer products - threadgroup const T * lsma = (sa + THREAD_MAT_M*SG_MAT_SIZE*(sgitg%2)); - threadgroup const half * lsmb = (sb + THREAD_MAT_N*SG_MAT_SIZE*(sgitg/2)); + threadgroup const S0 * lsma = (sa + THREAD_MAT_M*SG_MAT_SIZE*(sgitg%2)); + threadgroup const S1 * lsmb = (sb + THREAD_MAT_N*SG_MAT_SIZE*(sgitg/2)); #pragma unroll(4) for (short ik = 0; ik < BLOCK_SIZE_K/8; ik++) { @@ -7116,43 +8235,38 @@ kernel void kernel_mul_mm_id( } } - if ((r0 + 1) * BLOCK_SIZE_M <= args.neh0 && (r1 + 1) * BLOCK_SIZE_N <= neh1) { - device float * C = (device float *) dst + - (BLOCK_SIZE_M * r0 + 32*(sgitg & 1)) + \ - (BLOCK_SIZE_N * r1 + 16*(sgitg >> 1)) * args.neh0 + im*args.neh1*args.neh0; + threadgroup_barrier(mem_flags::mem_threadgroup); - for (short i = 0; i < 8; i++) { - simdgroup_store(mc[i], C + 8 * (i%4) + 8 * args.neh0 * (i/4), args.neh0); - } - } else { - // block is smaller than 64x32, we should avoid writing data outside of the matrix - threadgroup_barrier(mem_flags::mem_threadgroup); - threadgroup float * temp_str = ((threadgroup float *) shmem) \ - + 32*(sgitg&1) + (16*(sgitg >> 1))*BLOCK_SIZE_M; - for (short i = 0; i < 8; i++) { - simdgroup_store(mc[i], temp_str + 8*(i%4) + 8*BLOCK_SIZE_M*(i/4), BLOCK_SIZE_M); - } + threadgroup float * temp_str = ((threadgroup float *) shmem) \ + + 32*(sgitg&1) + (16*(sgitg >> 1))*BLOCK_SIZE_M; - threadgroup_barrier(mem_flags::mem_threadgroup); + #pragma unroll(8) + for (short i = 0; i < 8; i++) { + simdgroup_store(mc[i], temp_str + 8*(i%4) + 8*BLOCK_SIZE_M*(i/4), BLOCK_SIZE_M); + } - if (sgitg == 0) { - for (int j = tiitg; j < n_cols; j += BLOCK_SIZE_N) { - device float * D = (device float *) dst + (r0*BLOCK_SIZE_M) + (r1*BLOCK_SIZE_N + j)*args.neh0 + im*args.neh1*args.neh0; - device float4 * D4 = (device float4 *) D; + threadgroup_barrier(mem_flags::mem_threadgroup); - threadgroup float * C = temp_str + (j*BLOCK_SIZE_M); - threadgroup float4 * C4 = (threadgroup float4 *) C; + for (short j = sgitg; j < n_cols; j += 4) { + const int id = ids_i32[im*args.ne21 + r1*BLOCK_SIZE_N + j]; - int i = 0; - for (; i < n_rows/4; i++) { - *(D4 + i) = *(C4 + i); - } + const short ide = id % args.ne20; + const short idt = id / args.ne20; - i *= 4; - for (; i < n_rows; i++) { - *(D + i) = *(C + i); - } - } + device float * D = (device float *) dst + (r0*BLOCK_SIZE_M) + ide*args.ne0 + idt*args.ne1*args.ne0; + device float4 * D4 = (device float4 *) D; + + threadgroup float * C = (threadgroup float *) shmem + (j*BLOCK_SIZE_M); + threadgroup float4 * C4 = (threadgroup float4 *) C; + + int i = tiisg; + for (; i < n_rows/4; i += 32) { + *(D4 + i) = *(C4 + i); + } + + i = (4*(n_rows/4)) + tiisg; + for (; i < n_rows; i += 32) { + *(D + i) = *(C + i); } } } @@ -7167,7 +8281,7 @@ typedef decltype(kernel_get_rows_f; template [[host_name("kernel_get_rows_f16")]] kernel get_rows_f_t kernel_get_rows_f; -#if defined(GGML_METAL_USE_BF16) +#if defined(GGML_METAL_HAS_BF16) template [[host_name("kernel_get_rows_bf16")]] kernel get_rows_f_t kernel_get_rows_f; #endif @@ -7178,6 +8292,7 @@ template [[host_name("kernel_get_rows_q4 template [[host_name("kernel_get_rows_q5_0")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q5_1")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q8_0")]] kernel get_rows_q_t kernel_get_rows_q; +template [[host_name("kernel_get_rows_mxfp4")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q2_K")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q3_K")]] kernel get_rows_q_t kernel_get_rows_q; template [[host_name("kernel_get_rows_q4_K")]] kernel get_rows_q_t kernel_get_rows_q; @@ -7197,85 +8312,147 @@ template [[host_name("kernel_get_rows_iq // set rows // -typedef decltype(kernel_set_rows_f) set_rows_f_t; +typedef decltype(kernel_set_rows_f) set_rows_f_t; -template [[host_name("kernel_set_rows_f32")]] kernel set_rows_f_t kernel_set_rows_f; -template [[host_name("kernel_set_rows_f16")]] kernel set_rows_f_t kernel_set_rows_f; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_set_rows_bf16")]] kernel set_rows_f_t kernel_set_rows_f; +template [[host_name("kernel_set_rows_f32_i64")]] kernel set_rows_f_t kernel_set_rows_f; +template [[host_name("kernel_set_rows_f32_i32")]] kernel set_rows_f_t kernel_set_rows_f; +template [[host_name("kernel_set_rows_f16_i64")]] kernel set_rows_f_t kernel_set_rows_f; +template [[host_name("kernel_set_rows_f16_i32")]] kernel set_rows_f_t kernel_set_rows_f; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_set_rows_bf16_i64")]] kernel set_rows_f_t kernel_set_rows_f; +template [[host_name("kernel_set_rows_bf16_i32")]] kernel set_rows_f_t kernel_set_rows_f; #endif -typedef decltype(kernel_set_rows_q32) set_rows_q32_t; +typedef decltype(kernel_set_rows_q32) set_rows_q32_t; -template [[host_name("kernel_set_rows_q8_0")]] kernel set_rows_q32_t kernel_set_rows_q32; -template [[host_name("kernel_set_rows_q4_0")]] kernel set_rows_q32_t kernel_set_rows_q32; -template [[host_name("kernel_set_rows_q4_1")]] kernel set_rows_q32_t kernel_set_rows_q32; -template [[host_name("kernel_set_rows_q5_0")]] kernel set_rows_q32_t kernel_set_rows_q32; -template [[host_name("kernel_set_rows_q5_1")]] kernel set_rows_q32_t kernel_set_rows_q32; -template [[host_name("kernel_set_rows_iq4_nl")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q8_0_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q8_0_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q4_0_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q4_0_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q4_1_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q4_1_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q5_0_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q5_0_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q5_1_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_q5_1_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_iq4_nl_i64")]] kernel set_rows_q32_t kernel_set_rows_q32; +template [[host_name("kernel_set_rows_iq4_nl_i32")]] kernel set_rows_q32_t kernel_set_rows_q32; // // matrix-matrix multiplication // -typedef decltype(kernel_mul_mm) mul_mm_t; +typedef decltype(kernel_mul_mm) mul_mm_t; -template [[host_name("kernel_mul_mm_f32_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_f16_f32")]] kernel mul_mm_t kernel_mul_mm; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mm_bf16_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_f32_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_f16_f32")]] kernel mul_mm_t kernel_mul_mm; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mm_bf16_f32")]] kernel mul_mm_t kernel_mul_mm; #endif -template [[host_name("kernel_mul_mm_q4_0_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q4_1_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q5_0_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q5_1_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q8_0_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q2_K_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q3_K_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q4_K_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q5_K_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_q6_K_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq2_xxs_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq2_xs_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq3_xxs_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq3_s_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq2_s_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq1_s_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq1_m_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq4_nl_f32")]] kernel mul_mm_t kernel_mul_mm; -template [[host_name("kernel_mul_mm_iq4_xs_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q4_0_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q4_1_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_0_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_1_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q8_0_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_mxfp4_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q2_K_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q3_K_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q4_K_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_K_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q6_K_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_xxs_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_xs_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq3_xxs_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq3_s_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_s_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq1_s_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq1_m_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq4_nl_f32")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq4_xs_f32")]] kernel mul_mm_t kernel_mul_mm; + +template [[host_name("kernel_mul_mm_f32_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_f16_f16")]] kernel mul_mm_t kernel_mul_mm; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mm_bf16_f16")]] kernel mul_mm_t kernel_mul_mm; +#endif +template [[host_name("kernel_mul_mm_q4_0_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q4_1_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_0_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_1_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q8_0_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_mxfp4_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q2_K_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q3_K_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q4_K_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q5_K_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_q6_K_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_xxs_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_xs_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq3_xxs_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq3_s_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq2_s_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq1_s_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq1_m_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq4_nl_f16")]] kernel mul_mm_t kernel_mul_mm; +template [[host_name("kernel_mul_mm_iq4_xs_f16")]] kernel mul_mm_t kernel_mul_mm; // // indirect matrix-matrix multiplication // -typedef decltype(kernel_mul_mm_id) mul_mm_id; +typedef decltype(kernel_mul_mm_id) mul_mm_id; -template [[host_name("kernel_mul_mm_id_f32_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_f16_f16")]] kernel mul_mm_id kernel_mul_mm_id; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mm_id_bf16_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_f32_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_f16_f32")]] kernel mul_mm_id kernel_mul_mm_id; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mm_id_bf16_f32")]] kernel mul_mm_id kernel_mul_mm_id; #endif -template [[host_name("kernel_mul_mm_id_q4_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q4_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q5_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q5_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q8_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q2_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q3_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q4_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q5_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_q6_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq2_xxs_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq2_xs_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq3_xxs_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq3_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq2_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq1_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq1_m_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq4_nl_f16")]] kernel mul_mm_id kernel_mul_mm_id; -template [[host_name("kernel_mul_mm_id_iq4_xs_f16")]] kernel mul_mm_id kernel_mul_mm_id; - +template [[host_name("kernel_mul_mm_id_q4_0_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q4_1_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_0_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_1_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q8_0_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_mxfp4_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q2_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q3_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q4_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q6_K_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_xxs_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_xs_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq3_xxs_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq3_s_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_s_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq1_s_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq1_m_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq4_nl_f32")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq4_xs_f32")]] kernel mul_mm_id kernel_mul_mm_id; + +template [[host_name("kernel_mul_mm_id_f32_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_f16_f16")]] kernel mul_mm_id kernel_mul_mm_id; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mm_id_bf16_f16")]] kernel mul_mm_id kernel_mul_mm_id; +#endif +template [[host_name("kernel_mul_mm_id_q4_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q4_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_1_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q8_0_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_mxfp4_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q2_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q3_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q4_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q5_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_q6_K_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_xxs_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_xs_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq3_xxs_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq3_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq2_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq1_s_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq1_m_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq4_nl_f16")]] kernel mul_mm_id kernel_mul_mm_id; +template [[host_name("kernel_mul_mm_id_iq4_xs_f16")]] kernel mul_mm_id kernel_mul_mm_id; // // matrix-vector multiplication @@ -7327,7 +8504,7 @@ void mmv_fn( impl_fn(args, src0, src1, dst, shmem, tgpig, tiisg, sgitg); } -typedef decltype(mmv_fn>) mul_mv_impl_fn_t; +typedef decltype(mmv_fn>) mul_mv_impl_fn_t; template kernel void kernel_mul_mv_id( @@ -7392,42 +8569,52 @@ kernel void kernel_mul_mv_id( sgitg); } -typedef decltype(kernel_mul_mv_id>>) kernel_mul_mv_id_t; +typedef decltype(kernel_mul_mv_id>>) kernel_mul_mv_id_t; -template [[host_name("kernel_mul_mv_id_f32_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_f16_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -#if defined(GGML_METAL_USE_BF16) -template [[host_name("kernel_mul_mv_id_bf16_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +typedef decltype(kernel_mul_mv_id>>) kernel_mul_mv_id_4_t; + +template [[host_name("kernel_mul_mv_id_f32_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_f16_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mv_id_bf16_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +#endif +template [[host_name("kernel_mul_mv_id_f32_f32_4")]] kernel kernel_mul_mv_id_4_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_f16_f32_4")]] kernel kernel_mul_mv_id_4_t kernel_mul_mv_id>>; +#if defined(GGML_METAL_HAS_BF16) +template [[host_name("kernel_mul_mv_id_bf16_f32_4")]] kernel kernel_mul_mv_id_4_t kernel_mul_mv_id>>; #endif -template [[host_name("kernel_mul_mv_id_q8_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q4_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q4_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q5_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q5_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; - -template [[host_name("kernel_mul_mv_id_q2_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q3_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q4_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q5_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_q6_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq1_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq1_m_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq2_xxs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq2_xs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq3_xxs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq3_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq2_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq4_nl_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; -template [[host_name("kernel_mul_mv_id_iq4_xs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q8_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; + +template [[host_name("kernel_mul_mv_id_q4_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q4_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q5_0_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q5_1_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; + +template [[host_name("kernel_mul_mv_id_mxfp4_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; + +template [[host_name("kernel_mul_mv_id_q2_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q3_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q4_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q5_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_q6_K_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq1_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq1_m_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq2_xxs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq2_xs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq3_xxs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq3_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq2_s_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq4_nl_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; +template [[host_name("kernel_mul_mv_id_iq4_xs_f32")]] kernel kernel_mul_mv_id_t kernel_mul_mv_id>>; kernel void kernel_pool_2d_max_f32( + constant ggml_metal_kargs_pool_2d & args, device const float * src0, device float * dst, - constant ggml_metal_kargs_pool_2d & args, uint gid[[thread_position_in_grid]]) { - if (gid >= args.parallel_elements) { + if (gid >= args.np) { return; } @@ -7460,12 +8647,12 @@ kernel void kernel_pool_2d_max_f32( } kernel void kernel_pool_2d_avg_f32( + constant ggml_metal_kargs_pool_2d & args, device const float * src0, device float * dst, - constant ggml_metal_kargs_pool_2d & args, uint gid[[thread_position_in_grid]]) { - if (gid >= args.parallel_elements) { + if (gid >= args.np) { return; } diff -pruN 5882+dfsg-2/ggml/src/ggml-musa/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-musa/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-musa/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-musa/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -34,8 +34,12 @@ if (MUSAToolkit_FOUND) list(APPEND GGML_SOURCES_MUSA ${SRCS}) file(GLOB SRCS "../ggml-cuda/template-instances/mmq*.cu") list(APPEND GGML_SOURCES_MUSA ${SRCS}) - file(GLOB SRCS "../ggml-musa/*.cu") - list(APPEND GGML_SOURCES_MUSA ${SRCS}) + + if (GGML_MUSA_MUDNN_COPY) + file(GLOB SRCS "../ggml-musa/*.cu") + list(APPEND GGML_SOURCES_MUSA ${SRCS}) + add_compile_definitions(GGML_MUSA_MUDNN_COPY) + endif() if (GGML_CUDA_FA_ALL_QUANTS) file(GLOB SRCS "../ggml-cuda/template-instances/fattn-vec*.cu") @@ -72,6 +76,10 @@ if (MUSAToolkit_FOUND) add_compile_definitions(GGML_USE_MUSA) add_compile_definitions(GGML_CUDA_PEER_MAX_BATCH_SIZE=${GGML_CUDA_PEER_MAX_BATCH_SIZE}) + if (GGML_MUSA_GRAPHS) + add_compile_definitions(GGML_MUSA_GRAPHS) + endif() + if (GGML_CUDA_FORCE_MMQ) add_compile_definitions(GGML_CUDA_FORCE_MMQ) endif() @@ -88,19 +96,21 @@ if (MUSAToolkit_FOUND) add_compile_definitions(GGML_CUDA_NO_FA) endif() - if (GGML_CUDA_F16 OR GGML_CUDA_DMMV_F16) - add_compile_definitions(GGML_CUDA_F16) - endif() - if (GGML_CUDA_NO_PEER_COPY) add_compile_definitions(GGML_CUDA_NO_PEER_COPY) endif() if (GGML_STATIC) - # TODO: mudnn has not provided static libraries yet target_link_libraries(ggml-musa PRIVATE MUSA::musart_static MUSA::mublas_static) + # TODO: mudnn has not provided static libraries yet + # if (GGML_MUSA_MUDNN_COPY) + # target_link_libraries(ggml-musa PRIVATE mudnn_static) + # endif() else() - target_link_libraries(ggml-musa PRIVATE MUSA::musart MUSA::mublas mudnn) + target_link_libraries(ggml-musa PRIVATE MUSA::musart MUSA::mublas) + if (GGML_MUSA_MUDNN_COPY) + target_link_libraries(ggml-musa PRIVATE mudnn) + endif() endif() if (GGML_CUDA_NO_VMM) diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/CMakeLists.txt 6641+dfsg-2/ggml/src/ggml-opencl/CMakeLists.txt --- 5882+dfsg-2/ggml/src/ggml-opencl/CMakeLists.txt 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/CMakeLists.txt 2025-09-30 07:36:33.000000000 +0000 @@ -55,6 +55,7 @@ endfunction() set(GGML_OPENCL_KERNELS add + add_id argsort clamp cpy @@ -81,7 +82,17 @@ set(GGML_OPENCL_KERNELS mul_mv_q4_0_f32_1d_8x_flat mul_mv_q4_0_f32_1d_16x_flat mul_mv_q6_k + mul_mv_q8_0_f32 + mul_mv_q8_0_f32_flat + mul_mv_mxfp4_f32 + mul_mv_mxfp4_f32_flat mul_mv_id_q4_0_f32_8x_flat + mul_mv_id_q8_0_f32 + mul_mv_id_q8_0_f32_flat + mul_mv_id_mxfp4_f32 + mul_mv_id_mxfp4_f32_flat + mul_mm_f32_f32_l4_lm + mul_mm_f16_f32_l4_lm mul norm relu @@ -105,6 +116,11 @@ set(GGML_OPENCL_KERNELS pad repeat mul_mat_f16_f32 + conv2d + conv2d_f16_f32 + flash_attn_f32_f16 + flash_attn_f16 + flash_attn_f32 ) foreach (K ${GGML_OPENCL_KERNELS}) diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/ggml-opencl.cpp 6641+dfsg-2/ggml/src/ggml-opencl/ggml-opencl.cpp --- 5882+dfsg-2/ggml/src/ggml-opencl/ggml-opencl.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/ggml-opencl.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ #undef MAX #define MIN(a, b) ((a) < (b) ? (a) : (b)) #define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define CEIL_DIV(M, N) (((M) + (N)-1) / (N)) #define UNUSED(x) (void)(x) @@ -331,8 +333,10 @@ struct ggml_backend_opencl_context { cl_int alignment; size_t max_alloc_size; + size_t max_workgroup_size; bool fp16_support; bool has_vector_subgroup_broadcast; + bool disable_fusion; ggml_cl_compiler_version adreno_cl_compiler_version; int adreno_wave_size; @@ -343,6 +347,7 @@ struct ggml_backend_opencl_context { cl_command_queue queue; cl_program program_add; + cl_program program_add_id; cl_program program_clamp; cl_program program_cpy; cl_program program_cvt; @@ -362,6 +367,9 @@ struct ggml_backend_opencl_context { cl_program program_mul_mv_q4_0_f32_1d_8x_flat; cl_program program_mul_mv_q4_0_f32_1d_16x_flat; cl_program program_mul_mv_q6_K; + cl_program program_mul_mv_q8_0_f32, program_mul_mv_q8_0_f32_flat; + cl_program program_mul_mv_mxfp4_f32; + cl_program program_mul_mv_mxfp4_f32_flat; cl_program program_mul_mv_f16_f16; cl_program program_mul_mv_f16_f32_1row; cl_program program_mul_mv_f16_f32_l4; @@ -390,13 +398,22 @@ struct ggml_backend_opencl_context { cl_program program_tanh; cl_program program_upscale; cl_program program_concat; + cl_program program_conv_2d_f16; + cl_program program_conv_2d_f32; + cl_program program_conv_2d_f16_f32; cl_program program_tsembd; cl_program program_mul_mv_id_q4_0_f32_8x_flat; - - cl_kernel kernel_add, kernel_add_row; - cl_kernel kernel_mul, kernel_mul_row; - cl_kernel kernel_div, kernel_div_row; - cl_kernel kernel_sub, kernel_sub_row; + cl_program program_mul_mv_id_q8_0_f32, program_mul_mv_id_q8_0_f32_flat; + cl_program program_mul_mv_id_mxfp4_f32; + cl_program program_mul_mv_id_mxfp4_f32_flat; + cl_program program_mul_mm_f32_f32_l4_lm; + cl_program program_mul_mm_f16_f32_l4_lm; + + cl_kernel kernel_add, kernel_add_row, kernel_add_f16, kernel_add_row_f16; + cl_kernel kernel_mul, kernel_mul_row, kernel_mul_f16, kernel_mul_row_f16; + cl_kernel kernel_div, kernel_div_row, kernel_div_f16, kernel_div_row_f16; + cl_kernel kernel_sub, kernel_sub_row, kernel_sub_f16, kernel_sub_row_f16; + cl_kernel kernel_add_id; cl_kernel kernel_scale; cl_kernel kernel_silu, kernel_silu_4; cl_kernel kernel_gelu, kernel_gelu_4; @@ -405,16 +422,24 @@ struct ggml_backend_opencl_context { cl_kernel kernel_relu; cl_kernel kernel_sigmoid_f32, kernel_sigmoid_f16; cl_kernel kernel_clamp; - cl_kernel kernel_geglu, kernel_reglu, kernel_swiglu, kernel_geglu_erf, kernel_geglu_quick, + cl_kernel kernel_geglu, kernel_reglu, kernel_swiglu, kernel_swiglu_oai, kernel_geglu_erf, kernel_geglu_quick, kernel_geglu_f16, kernel_reglu_f16, kernel_swiglu_f16, kernel_geglu_erf_f16, kernel_geglu_quick_f16; - cl_kernel kernel_norm; - cl_kernel kernel_rms_norm; - cl_kernel kernel_group_norm; + cl_kernel kernel_norm, kernel_norm_mul_add; + cl_kernel kernel_rms_norm, kernel_rms_norm_mul; + cl_kernel kernel_group_norm, kernel_group_norm_mul_add; cl_kernel kernel_diag_mask_inf, kernel_diag_mask_inf_8; cl_kernel kernel_soft_max, kernel_soft_max_4; cl_kernel kernel_soft_max_f16, kernel_soft_max_4_f16; + std::map, cl_kernel> kernels_flash_attn_f16; + std::map, cl_kernel> kernels_flash_attn_f16_q1; + std::map, cl_kernel> kernels_flash_attn_f32; + std::map, cl_kernel> kernels_flash_attn_f32_q1; + std::map, cl_kernel> kernels_flash_attn_f32_f16; + std::map, cl_kernel> kernels_flash_attn_f32_f16_q1; + std::map, int> kernels_flash_attn_bm; + std::map, int> kernels_flash_attn_bn; cl_kernel kernel_get_rows_f32, kernel_get_rows_f16, kernel_get_rows_q4_0; - cl_kernel kernel_set_rows_f32, kernel_set_rows_f16; + cl_kernel kernel_set_rows_f32_i64, kernel_set_rows_f32_i32, kernel_set_rows_f16_i64, kernel_set_rows_f16_i32; cl_kernel kernel_rope_norm_f32, kernel_rope_norm_f16, kernel_rope_neox_f32, kernel_rope_neox_f16; cl_kernel kernel_rope_multi_f32, kernel_rope_multi_f16, kernel_rope_vision_f32, kernel_rope_vision_f16; cl_kernel kernel_cpy_f16_f16, kernel_cpy_f16_f32, kernel_cpy_f32_f16, kernel_cpy_f32_f32; @@ -426,10 +451,14 @@ struct ggml_backend_opencl_context { cl_kernel kernel_mul_mat_f16_f32_tiled; cl_kernel kernel_mul_mat_q4_0_f32, kernel_mul_mat_q4_0_f32_v; cl_kernel kernel_convert_block_q4_0, kernel_restore_block_q4_0; + cl_kernel kernel_convert_block_mxfp4, kernel_restore_block_mxfp4; + cl_kernel kernel_convert_block_q8_0, kernel_restore_block_q8_0; cl_kernel kernel_mul_mat_q4_0_f32_8x_flat; cl_kernel kernel_convert_block_q4_0_noshuffle; cl_kernel kernel_mul_mat_q4_0_f32_1d_8x_flat, kernel_mul_mat_q4_0_f32_1d_16x_flat; cl_kernel kernel_mul_mv_q6_K_f32; + cl_kernel kernel_mul_mv_mxfp4_f32, kernel_mul_mv_mxfp4_f32_flat; + cl_kernel kernel_mul_mv_q8_0_f32, kernel_mul_mv_q8_0_f32_flat; cl_kernel kernel_im2col_f32, kernel_im2col_f16; cl_kernel kernel_argsort_f32_i32; cl_kernel kernel_sum_rows_f32; @@ -441,8 +470,16 @@ struct ggml_backend_opencl_context { cl_kernel kernel_upscale_bilinear; cl_kernel kernel_concat_f32_contiguous; cl_kernel kernel_concat_f32_non_contiguous; + cl_kernel kernel_conv_2d_f16; + cl_kernel kernel_conv_2d_f32; + cl_kernel kernel_conv_2d_f16_f32; cl_kernel kernel_timestep_embedding; cl_kernel kernel_mul_mv_id_q4_0_f32_8x_flat; + cl_kernel kernel_mul_mv_id_q8_0_f32, kernel_mul_mv_id_q8_0_f32_flat; + cl_kernel kernel_mul_mv_id_mxfp4_f32; + cl_kernel kernel_mul_mv_id_mxfp4_f32_flat; + cl_kernel kernel_mul_mm_f32_f32_l4_lm; + cl_kernel kernel_mul_mm_f16_f32_l4_lm; std::vector profiling_info; @@ -563,6 +600,7 @@ struct ggml_backend_opencl_context { cl_kernel kernel_transpose_32; cl_kernel kernel_transpose_32_16; cl_kernel kernel_transpose_16; + cl_kernel kernel_transpose_16_4x1; cl_mem A_s_d_max; // max scale buffer size for transpose cl_mem A_q_d_max; // max weight buffer size for transpose @@ -588,6 +626,7 @@ struct ggml_backend_opencl_context { if (ref_count == 0) { #ifdef GGML_OPENCL_PROFILING write_profiling_info(); + profiling_info.clear(); #endif } } @@ -662,8 +701,26 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_add = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_add = clCreateKernel(backend_ctx->program_add, "kernel_add", &err), err)); - CL_CHECK((backend_ctx->kernel_add_row = clCreateKernel(backend_ctx->program_add, "kernel_add_row", &err), err)); + CL_CHECK((backend_ctx->kernel_add = clCreateKernel(backend_ctx->program_add, "kernel_add", &err), err)); + CL_CHECK((backend_ctx->kernel_add_row = clCreateKernel(backend_ctx->program_add, "kernel_add_row", &err), err)); + CL_CHECK((backend_ctx->kernel_add_f16 = clCreateKernel(backend_ctx->program_add, "kernel_add_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_add_row_f16 = clCreateKernel(backend_ctx->program_add, "kernel_add_row_f16", &err), err)); + GGML_LOG_CONT("."); + } + + // add_id + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "add_id.cl.h" + }; +#else + const std::string kernel_src = read_file("add_id.cl"); +#endif + backend_ctx->program_add_id = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_add_id = clCreateKernel(backend_ctx->program_add_id, "kernel_add_id", &err), err)); GGML_LOG_CONT("."); } @@ -717,6 +774,10 @@ static void load_cl_kernels(ggml_backend CL_CHECK((backend_ctx->kernel_convert_block_q4_0_noshuffle = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q4_0_noshuffle", &err), err)); CL_CHECK((backend_ctx->kernel_convert_block_q4_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q4_0", &err), err)); CL_CHECK((backend_ctx->kernel_restore_block_q4_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q4_0", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_mxfp4 = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_mxfp4", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_mxfp4 = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_mxfp4", &err), err)); + CL_CHECK((backend_ctx->kernel_convert_block_q8_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_convert_block_q8_0", &err), err)); + CL_CHECK((backend_ctx->kernel_restore_block_q8_0 = clCreateKernel(backend_ctx->program_cvt, "kernel_restore_block_q8_0", &err), err)); GGML_LOG_CONT("."); } @@ -773,6 +834,7 @@ static void load_cl_kernels(ggml_backend CL_CHECK((backend_ctx->kernel_geglu = clCreateKernel(backend_ctx->program_glu, "kernel_geglu", &err), err)); CL_CHECK((backend_ctx->kernel_reglu = clCreateKernel(backend_ctx->program_glu, "kernel_reglu", &err), err)); CL_CHECK((backend_ctx->kernel_swiglu = clCreateKernel(backend_ctx->program_glu, "kernel_swiglu", &err), err)); + CL_CHECK((backend_ctx->kernel_swiglu_oai = clCreateKernel(backend_ctx->program_glu, "kernel_swiglu_oai", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_erf = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_erf", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_quick = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_quick", &err), err)); CL_CHECK((backend_ctx->kernel_geglu_f16 = clCreateKernel(backend_ctx->program_glu, "kernel_geglu_f16", &err), err)); @@ -937,6 +999,70 @@ static void load_cl_kernels(ggml_backend GGML_LOG_CONT("."); } + // mul_mv_q8_0_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_q8_0_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_q8_0_f32.cl"); +#endif + backend_ctx->program_mul_mv_q8_0_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32, "kernel_mul_mv_q8_0_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_q8_0_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_q8_0_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_q8_0_f32_flat.cl"); +#endif + backend_ctx->program_mul_mv_q8_0_f32_flat = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_q8_0_f32_flat, "kernel_mul_mv_q8_0_f32_flat", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_mxfp4_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_mxfp4_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_mxfp4_f32.cl"); +#endif + backend_ctx->program_mul_mv_mxfp4_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32, "kernel_mul_mv_mxfp4_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_mxfp4_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_mxfp4_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_mxfp4_f32_flat.cl"); +#endif + backend_ctx->program_mul_mv_mxfp4_f32_flat = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_mxfp4_f32_flat, "kernel_mul_mv_mxfp4_f32_flat", &err), err)); + GGML_LOG_CONT("."); + } + // mul_mv_f16_f16 { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1033,6 +1159,38 @@ static void load_cl_kernels(ggml_backend GGML_LOG_CONT("."); } + // mul_mm_f32_f32_l4_lm + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mm_f32_f32_l4_lm.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mm_f32_f32_l4_lm.cl"); +#endif + backend_ctx->program_mul_mm_f32_f32_l4_lm = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mm_f32_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f32_f32_l4_lm, "kernel_mul_mm_f32_f32_l4_lm", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mm_f16_f32_l4_lm + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mm_f16_f32_l4_lm.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mm_f16_f32_l4_lm.cl"); +#endif + backend_ctx->program_mul_mm_f16_f32_l4_lm = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mm_f16_f32_l4_lm = clCreateKernel(backend_ctx->program_mul_mm_f16_f32_l4_lm, "kernel_mul_mm_f16_f32_l4_lm", &err), err)); + GGML_LOG_CONT("."); + } + // mul { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1045,8 +1203,10 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_mul = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); - CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); + CL_CHECK((backend_ctx->kernel_mul = clCreateKernel(backend_ctx->program_mul, "kernel_mul", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_mul_row_f16 = clCreateKernel(backend_ctx->program_mul, "kernel_mul_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1062,7 +1222,8 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_norm = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_norm = clCreateKernel(backend_ctx->program_norm, "kernel_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_norm = clCreateKernel(backend_ctx->program_norm, "kernel_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_norm_mul_add = clCreateKernel(backend_ctx->program_norm, "kernel_norm_mul_add", &err), err)); GGML_LOG_CONT("."); } @@ -1094,7 +1255,8 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_rms_norm = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_rms_norm_mul = clCreateKernel(backend_ctx->program_rms_norm, "kernel_rms_norm_mul", &err), err)); GGML_LOG_CONT("."); } @@ -1218,6 +1380,73 @@ static void load_cl_kernels(ggml_backend GGML_LOG_CONT("."); } + // flash_attn + { + #ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src_f16 { + #include "flash_attn_f16.cl.h" + }; + const std::string kernel_src_f32 { + #include "flash_attn_f32.cl.h" + }; + const std::string kernel_src_f32_f16 { + #include "flash_attn_f32_f16.cl.h" + }; + #else + const std::string kernel_src_f16 = read_file("flash_attn_f16.cl"); + const std::string kernel_src_f32 = read_file("flash_attn_f32.cl"); + const std::string kernel_src_f32_f16 = read_file("flash_attn_f32_f16.cl"); + #endif + + if (!kernel_src_f16.empty() && !kernel_src_f32.empty() && !kernel_src_f32_f16.empty()) { + const struct { int dk; int dv; int bm; int bn; } fa_dims[] = { + { 40, 40, 32, 32}, { 64, 64, 64, 64}, { 80, 80, 64, 32}, { 96, 96, 64, 32}, + {112, 112, 32, 32}, {128, 128, 32, 32}, {192, 128, 16, 16}, + {192, 192, 16, 16}, {256, 256, 16, 16}, + }; + + for (size_t i = 0; i < sizeof(fa_dims)/sizeof(fa_dims[0]); ++i) { + const int dk = fa_dims[i].dk; + const int dv = fa_dims[i].dv; + const int bm = fa_dims[i].bm; + const int bn = fa_dims[i].bn; + std::string OPTS = compile_opts + + " -D DK=" + std::to_string(dk) + + " -D DV=" + std::to_string(dv) + + " -D BLOCK_M=" + std::to_string(bm) + + " -D BLOCK_N=" + std::to_string(bn); + + cl_program prog_f16 = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src_f16.c_str(), OPTS); + cl_kernel k_f16, k_f16_q1; + CL_CHECK((k_f16 = clCreateKernel(prog_f16, "flash_attn_f16", &err), err)); + CL_CHECK((k_f16_q1 = clCreateKernel(prog_f16, "flash_attn_f16_q1", &err), err)); + backend_ctx->kernels_flash_attn_f16[{dk, dv}] = k_f16; + backend_ctx->kernels_flash_attn_f16_q1[{dk, dv}] = k_f16_q1; + CL_CHECK(clReleaseProgram(prog_f16)); + + cl_program prog_f32 = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src_f32.c_str(), OPTS); + cl_kernel k_f32, k_f32_q1; + CL_CHECK((k_f32 = clCreateKernel(prog_f32, "flash_attn_f32", &err), err)); + CL_CHECK((k_f32_q1 = clCreateKernel(prog_f32, "flash_attn_f32_q1", &err), err)); + backend_ctx->kernels_flash_attn_f32[{dk, dv}] = k_f32; + backend_ctx->kernels_flash_attn_f32_q1[{dk, dv}] = k_f32_q1; + CL_CHECK(clReleaseProgram(prog_f32)); + + cl_program prog_f32_f16 = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src_f32_f16.c_str(), OPTS); + cl_kernel k_f32_f16, k_f32_f16_q1; + CL_CHECK((k_f32_f16 = clCreateKernel(prog_f32_f16, "flash_attn_f32_f16", &err), err)); + CL_CHECK((k_f32_f16_q1 = clCreateKernel(prog_f32_f16, "flash_attn_f32_f16_q1", &err), err)); + backend_ctx->kernels_flash_attn_f32_f16[{dk, dv}] = k_f32_f16; + backend_ctx->kernels_flash_attn_f32_f16_q1[{dk, dv}] = k_f32_f16_q1; + CL_CHECK(clReleaseProgram(prog_f32_f16)); + + backend_ctx->kernels_flash_attn_bm[{dk, dv}] = bm; + backend_ctx->kernels_flash_attn_bn[{dk, dv}] = bn; + } + GGML_LOG_CONT("."); + } + } + // argsort { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1243,11 +1472,16 @@ static void load_cl_kernels(ggml_backend #else const std::string kernel_src = read_file("div.cl"); #endif + std::string compile_opts = std::string("-cl-std=") + opencl_c_std + + " -cl-mad-enable -cl-finite-math-only "; + backend_ctx->program_div = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); - CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); + CL_CHECK((backend_ctx->kernel_div = clCreateKernel(backend_ctx->program_div, "kernel_div", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row = clCreateKernel(backend_ctx->program_div, "kernel_div_row", &err), err)); + CL_CHECK((backend_ctx->kernel_div_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_div_row_f16 = clCreateKernel(backend_ctx->program_div, "kernel_div_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1263,8 +1497,10 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_sub = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); - CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); + CL_CHECK((backend_ctx->kernel_sub = clCreateKernel(backend_ctx->program_sub, "kernel_sub", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_sub_row_f16 = clCreateKernel(backend_ctx->program_sub, "kernel_sub_row_f16", &err), err)); GGML_LOG_CONT("."); } @@ -1313,7 +1549,8 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_group_norm = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_group_norm = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_group_norm = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm", &err), err)); + CL_CHECK((backend_ctx->kernel_group_norm_mul_add = clCreateKernel(backend_ctx->program_group_norm, "kernel_group_norm_mul_add", &err), err)); GGML_LOG_CONT("."); } @@ -1473,11 +1710,54 @@ static void load_cl_kernels(ggml_backend backend_ctx->program_set_rows = build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); - CL_CHECK((backend_ctx->kernel_set_rows_f32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32", &err), err)); - CL_CHECK((backend_ctx->kernel_set_rows_f16 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f32_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f32_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f32_i32", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f16_i64 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i64", &err), err)); + CL_CHECK((backend_ctx->kernel_set_rows_f16_i32 = clCreateKernel(backend_ctx->program_set_rows, "kernel_set_rows_f16_i32", &err), err)); GGML_LOG_CONT("."); } + // conv2d + { + #ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "conv2d.cl.h" + }; + const std::string kernel_src_f16_f32 { + #include "conv2d_f16_f32.cl.h" + }; + #else + const std::string kernel_src = read_file("conv2d.cl"); + const std::string kernel_src_f16_f32 = read_file("conv2d_f16_f32.cl"); + #endif + if (!kernel_src.empty()) { + backend_ctx->program_conv_2d_f16 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), (std::string(compile_opts) + " -DUSE_FP16=1").c_str()); + CL_CHECK((backend_ctx->kernel_conv_2d_f16 = clCreateKernel(backend_ctx->program_conv_2d_f16, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + backend_ctx->program_conv_2d_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f32 = clCreateKernel(backend_ctx->program_conv_2d_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16 = nullptr; + backend_ctx->kernel_conv_2d_f16 = nullptr; + backend_ctx->program_conv_2d_f32 = nullptr; + backend_ctx->kernel_conv_2d_f32 = nullptr; + } + if (!kernel_src_f16_f32.empty()) { + backend_ctx->program_conv_2d_f16_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src_f16_f32.c_str(), compile_opts); + CL_CHECK((backend_ctx->kernel_conv_2d_f16_f32 = clCreateKernel(backend_ctx->program_conv_2d_f16_f32, "kernel_conv_2d", &err), err)); + GGML_LOG_CONT("."); + } else { + GGML_LOG_WARN("ggml_opencl: conv2d_f16_f32 kernel source not found or empty. This op will not be available.\n"); + backend_ctx->program_conv_2d_f16_f32 = nullptr; + backend_ctx->kernel_conv_2d_f16_f32 = nullptr; + } + } + // mul_mv_id_q4_0_f32_8x_flat { #ifdef GGML_OPENCL_EMBED_KERNELS @@ -1494,6 +1774,70 @@ static void load_cl_kernels(ggml_backend GGML_LOG_CONT("."); } + // mul_mv_id_q8_0_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_id_q8_0_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_id_q8_0_f32.cl"); +#endif + backend_ctx->program_mul_mv_id_q8_0_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32, "kernel_mul_mv_id_q8_0_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_id_q8_0_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_id_q8_0_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_id_q8_0_f32_flat.cl"); +#endif + backend_ctx->program_mul_mv_id_q8_0_f32_flat = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_id_q8_0_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_q8_0_f32_flat, "kernel_mul_mv_id_q8_0_f32_flat", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_id_mxfp4_f32 + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_id_mxfp4_f32.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32.cl"); +#endif + backend_ctx->program_mul_mv_id_mxfp4_f32 = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32 = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32, "kernel_mul_mv_id_mxfp4_f32", &err), err)); + GGML_LOG_CONT("."); + } + + // mul_mv_id_mxfp4_f32_flat + { +#ifdef GGML_OPENCL_EMBED_KERNELS + const std::string kernel_src { + #include "mul_mv_id_mxfp4_f32_flat.cl.h" + }; +#else + const std::string kernel_src = read_file("mul_mv_id_mxfp4_f32_flat.cl"); +#endif + backend_ctx->program_mul_mv_id_mxfp4_f32_flat = + build_program_from_source(backend_ctx->context, backend_ctx->device, kernel_src.c_str(), compile_opts); + + CL_CHECK((backend_ctx->kernel_mul_mv_id_mxfp4_f32_flat = clCreateKernel(backend_ctx->program_mul_mv_id_mxfp4_f32_flat, "kernel_mul_mv_id_mxfp4_f32_flat", &err), err)); + GGML_LOG_CONT("."); + } + // Adreno kernels #ifdef GGML_OPENCL_USE_ADRENO_KERNELS // transpose @@ -1511,6 +1855,7 @@ static void load_cl_kernels(ggml_backend CL_CHECK((backend_ctx->kernel_transpose_32_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32_16", &err), err)); CL_CHECK((backend_ctx->kernel_transpose_32 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_32", &err), err)); CL_CHECK((backend_ctx->kernel_transpose_16 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16", &err), err)); + CL_CHECK((backend_ctx->kernel_transpose_16_4x1 = clCreateKernel(backend_ctx->program_transpose, "kernel_transpose_16_4x1", &err), err)); GGML_LOG_CONT("."); } @@ -1949,8 +2294,8 @@ static ggml_backend_opencl_context * ggm backend_ctx->adreno_cl_compiler_version = get_adreno_cl_compiler_version(driver_version); backend_ctx->has_vector_subgroup_broadcast = - backend_ctx->adreno_cl_compiler_version.major >= 47 || - backend_ctx->adreno_cl_compiler_version.major == 17; + (backend_ctx->adreno_cl_compiler_version.type == E031 && backend_ctx->adreno_cl_compiler_version.major >= 47) || + (backend_ctx->adreno_cl_compiler_version.type == DX && backend_ctx->adreno_cl_compiler_version.major >= 17); GGML_LOG_INFO("ggml_opencl: vector subgroup broadcast support: %s\n", backend_ctx->has_vector_subgroup_broadcast ? "true" : "false"); @@ -1987,6 +2332,9 @@ static ggml_backend_opencl_context * ggm clGetDeviceInfo(device, CL_DEVICE_MAX_MEM_ALLOC_SIZE, sizeof(size_t), &backend_ctx->max_alloc_size, NULL); GGML_LOG_INFO("ggml_opencl: max mem alloc size: %zu MB\n", backend_ctx->max_alloc_size/1024/1024); + clGetDeviceInfo(device, CL_DEVICE_MAX_WORK_GROUP_SIZE, sizeof(size_t), &backend_ctx->max_workgroup_size, NULL); + GGML_LOG_INFO("ggml_opencl: device max workgroup size: %lu\n", backend_ctx->max_workgroup_size); + // Check SVM. cl_device_svm_capabilities svm_caps; CL_CHECK(clGetDeviceInfo(device, CL_DEVICE_SVM_CAPABILITIES, sizeof(cl_device_svm_capabilities), &svm_caps, 0)); @@ -2063,6 +2411,8 @@ static ggml_backend_opencl_context * ggm CL_CHECK((backend_ctx->B_d_max = clCreateBuffer(context, 0, max_B_d_bytes, NULL, &err), err)); #endif // GGML_OPENCL_USE_ADRENO_KERNELS + backend_ctx->disable_fusion = getenv("GGML_OPENCL_DISABLE_FUSION") != nullptr; + dev_ctx->backend_ctx = backend_ctx.release(); return dev_ctx->backend_ctx; } @@ -2152,6 +2502,84 @@ struct ggml_tensor_extra_cl_q4_0 { } }; +struct ggml_tensor_extra_cl_mxfp4 { + // Quantized values. + cl_mem q = nullptr; + // Quantized values in image1d_buffer_t. + cl_mem q_img = nullptr; + // Scales in E8M0. + cl_mem e = nullptr; + // Scales in image1d_buffer_t. + cl_mem e_img = nullptr; + // Size of quantized values. + size_t size_q = 0; + // Size of scales. + size_t size_e = 0; + + ~ggml_tensor_extra_cl_mxfp4() { + reset(); + } + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; + } + if (e != nullptr) { + CL_CHECK(clReleaseMemObject(e)); + e = nullptr; + } + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q_img)); + q = nullptr; + } + // Currently, q_img and d_img are not used. They can be image1d_buffer_t + // that wraps around q and d to utilize image access path. + q_img = nullptr; + e_img = nullptr; + size_q = 0; + size_e = 0; + } +}; + +struct ggml_tensor_extra_cl_q8_0 { + cl_mem q = nullptr; + cl_mem q_img = nullptr; + + cl_mem d = nullptr; + cl_mem d_img = nullptr; + + size_t size_q = 0; + size_t size_d = 0; + + ~ggml_tensor_extra_cl_q8_0() { + reset(); + } + + void reset() { + // q and d are subbuffers into the bigger buffer allocated in ggml_backend_buffer. + // They must be properly released so that the original buffer can be + // properly released to avoid memory leak. + if (q != nullptr) { + CL_CHECK(clReleaseMemObject(q)); + q = nullptr; + } + if (d != nullptr) { + CL_CHECK(clReleaseMemObject(d)); + d = nullptr; + } + // Currently, q_img and d_img are not used. They can be image1d_buffer_t + // that wraps around q and d to utilize image access path. + q_img = nullptr; + d_img = nullptr; + size_q = 0; + size_d = 0; + } +}; + //------------------------------------------------------------------------------ // Backend API //------------------------------------------------------------------------------ @@ -2232,7 +2660,80 @@ static void sync_with_other_backends(ggm sync_with_other_backends(backend_ctx); } +static bool ggml_opencl_can_fuse(const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list ops) { + if (!ggml_can_fuse(cgraph, node_idx, ops)) { + return false; + } + + if (ops.size() == 2 && ops.begin()[0] == GGML_OP_RMS_NORM && ops.begin()[1] == GGML_OP_MUL) { + const ggml_tensor *rms_norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + + GGML_ASSERT(rms_norm->src[0]->type == GGML_TYPE_F32); + GGML_ASSERT(rms_norm->type == GGML_TYPE_F32); + + // rms_norm only supports f32 + if (mul->src[0]->type != GGML_TYPE_F32 || + mul->src[1]->type != GGML_TYPE_F32 || + mul->type != GGML_TYPE_F32) { + return false; + } + + // if rms_norm is the B operand, then we don't handle broadcast + if (rms_norm == mul->src[1] && + !ggml_are_same_shape(mul->src[0], rms_norm->src[1])) { + return false; + } + + // rms_norm assumes contiguous rows + if (!ggml_is_contiguous_rows(mul->src[0]) || !ggml_is_contiguous_rows(mul->src[1])) { + return false; + } + } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { + const ggml_tensor *norm = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = cgraph->nodes[node_idx+2]; + const ggml_tensor *w = mul->src[0] == norm ? mul->src[1] : mul->src[0]; + const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; + + // norm fusion only supports F32 + if (norm->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { + return false; + } + + if (norm->src[0]->ne[0] % 4 != 0) { + return false; + } + + if (!ggml_is_contiguous(norm->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { + return false; + } + } else if (ops.size() == 3 && ops.begin()[0] == GGML_OP_GROUP_NORM && ops.begin()[1] == GGML_OP_MUL && ops.begin()[2] == GGML_OP_ADD) { + const ggml_tensor *gn = cgraph->nodes[node_idx]; + const ggml_tensor *mul = cgraph->nodes[node_idx+1]; + const ggml_tensor *add = cgraph->nodes[node_idx+2]; + const ggml_tensor *w = mul->src[0] == gn ? mul->src[1] : mul->src[0]; + const ggml_tensor *b = add->src[0] == mul ? add->src[1] : add->src[0]; + + if (gn->src[0]->type != GGML_TYPE_F32 || w->type != GGML_TYPE_F32 || b->type != GGML_TYPE_F32) { + return false; + } + + if (!ggml_is_contiguous(gn->src[0]) || !ggml_is_contiguous(w) || !ggml_is_contiguous(b)) { + return false; + } + } + + return true; +} + +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor); +static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); +static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor); + static ggml_status ggml_backend_opencl_graph_compute(ggml_backend_t backend, ggml_cgraph * cgraph) { + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + for (int i = 0; i < cgraph->n_nodes; i++) { ggml_tensor * node = cgraph->nodes[i]; @@ -2245,6 +2746,22 @@ static ggml_status ggml_backend_opencl_g continue; } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(cgraph, i, { GGML_OP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { + ggml_opencl_op_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(cgraph, i, { GGML_OP_GROUP_NORM, GGML_OP_MUL, GGML_OP_ADD })) { + ggml_opencl_op_group_norm_fused(backend, node, cgraph->nodes[i+1], cgraph->nodes[i+2]); + i += 2; + continue; + } + if (!backend_ctx->disable_fusion && ggml_opencl_can_fuse(cgraph, i, { GGML_OP_RMS_NORM, GGML_OP_MUL })) { + ggml_opencl_op_rms_norm_fused(backend, node, cgraph->nodes[i+1]); + i++; + continue; + } + bool ok = ggml_cl_compute_forward(backend, node); if (!ok) { GGML_LOG_ERROR("%s: error: op not supported %s (%s)\n", __func__, node->name, ggml_op_name(node->op)); @@ -2256,7 +2773,8 @@ static ggml_status ggml_backend_opencl_g } static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) { - GGML_UNUSED(dev); + ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *)dev->context; + ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx; switch (op->op) { case GGML_OP_NONE: @@ -2280,13 +2798,14 @@ static bool ggml_opencl_supports_op(ggml { // TODO: add support // ref: https://github.com/ggml-org/llama.cpp/pull/14274 +#pragma message("TODO: implement BF16, Q4_0, Q4_1, Q5_0, Q5_1, Q8_0, IQ4_NL support (https://github.com/ggml-org/llama.cpp/pull/14661)") if (op->src[0]->type != GGML_TYPE_F32) { return false; } switch (op->type) { case GGML_TYPE_F16: case GGML_TYPE_F32: - return true; + return (op->src[1]->type == GGML_TYPE_I64 || op->src[1]->type == GGML_TYPE_I32); default: return false; } @@ -2314,11 +2833,23 @@ static bool ggml_opencl_supports_op(ggml default: return false; } - case GGML_OP_ADD: case GGML_OP_SCALE: + return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_ADD: + if (op->type == GGML_TYPE_F16) { + const bool src0_ok = op->src[0]->type == GGML_TYPE_F16 || op->src[0]->type == GGML_TYPE_F32; + const bool src1_ok = op->src[1]->type == GGML_TYPE_F16 || op->src[1]->type == GGML_TYPE_F32; + if (src0_ok && src1_ok) { + return true; + } + } case GGML_OP_MUL: case GGML_OP_DIV: case GGML_OP_SUB: + return (op->src[0]->type == op->src[1]->type) && + (op->src[0]->type == op->type) && + (op->src[0]->type == GGML_TYPE_F32 || op->src[0]->type == GGML_TYPE_F16); + case GGML_OP_ADD_ID: return op->src[0]->type == GGML_TYPE_F32; case GGML_OP_UNARY: switch (ggml_get_unary_op(op)) { @@ -2341,6 +2872,7 @@ static bool ggml_opencl_supports_op(ggml case GGML_GLU_OP_GEGLU: case GGML_GLU_OP_REGLU: case GGML_GLU_OP_SWIGLU: + case GGML_GLU_OP_SWIGLU_OAI: case GGML_GLU_OP_GEGLU_ERF: case GGML_GLU_OP_GEGLU_QUICK: return ggml_is_contiguous_1(op->src[0]) && (op->type == GGML_TYPE_F32 || op->type == GGML_TYPE_F16); @@ -2351,15 +2883,22 @@ static bool ggml_opencl_supports_op(ggml return op->src[0]->type == GGML_TYPE_F32; case GGML_OP_SOFT_MAX: case GGML_OP_NORM: - case GGML_OP_RMS_NORM: return true; + case GGML_OP_RMS_NORM: + return op->ne[0] % 4 == 0 && ggml_is_contiguous_rows(op->src[0]); case GGML_OP_REPEAT: return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; // Assuming F32 for now, can be expanded case GGML_OP_PAD: return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32 && - op->src[0]->ne[3] == 1 && op->ne[3] == 1; + op->src[0]->ne[3] == 1 && op->ne[3] == 1 && + (ggml_get_op_params_i32(op, 0) == 0) && (ggml_get_op_params_i32(op, 2) == 0) && + (ggml_get_op_params_i32(op, 4) == 0) && (ggml_get_op_params_i32(op, 6) == 0); case GGML_OP_UPSCALE: return op->src[0]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + case GGML_OP_CONV_2D: + return (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16) || + (op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32) || + (op->src[0]->type == GGML_TYPE_F16 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32); case GGML_OP_CONCAT: return op->src[0]->type == GGML_TYPE_F32 && op->src[1]->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; case GGML_OP_TIMESTEP_EMBEDDING: @@ -2371,13 +2910,17 @@ static bool ggml_opencl_supports_op(ggml return true; } else if (op->src[0]->type == GGML_TYPE_F32) { return op->src[1]->type == GGML_TYPE_F32; - } else if (op->src[0]->type == GGML_TYPE_Q4_0 || + } else if (op->src[0]->type == GGML_TYPE_Q4_0 || op->src[0]->type == GGML_TYPE_MXFP4 || op->src[0]->type == GGML_TYPE_Q6_K) { return op->src[1]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); + } else if (op->src[0]->type == GGML_TYPE_Q8_0) { + return op->src[1]->type == GGML_TYPE_F32; } return false; case GGML_OP_MUL_MAT_ID: - if (op->src[0]->type == GGML_TYPE_Q4_0) { + if (op->src[0]->type == GGML_TYPE_Q4_0 || + op->src[0]->type == GGML_TYPE_Q8_0 || + op->src[0]->type == GGML_TYPE_MXFP4) { if (op->src[1]->type == GGML_TYPE_F32) { return ggml_is_contiguous(op->src[0]) && ggml_is_contiguous(op->src[1]); } @@ -2412,10 +2955,54 @@ static bool ggml_opencl_supports_op(ggml } case GGML_OP_IM2COL: return true; - case GGML_OP_ARGSORT: - return op->src[0]->type == GGML_TYPE_F32; + case GGML_OP_ARGSORT: { + cl_kernel kernel = backend_ctx->kernel_argsort_f32_i32; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + + int cols = 1; + while (cols < op->ne[0]) { + cols *= 2; + } + + return cols <= max_workgroup_size && op->src[0]->type == GGML_TYPE_F32; + } case GGML_OP_SUM_ROWS: return op->src[0]->type == GGML_TYPE_F32 && ggml_is_contiguous(op->src[0]); + case GGML_OP_FLASH_ATTN_EXT: + { + const ggml_tensor * q = op->src[0]; + const ggml_tensor * k = op->src[1]; + const ggml_tensor * v = op->src[2]; + + const int dk = q->ne[0]; + const int dv = v->ne[0]; + + const struct { int dk; int dv; } supported_dims[] = { + { 40, 40}, { 64, 64}, { 80, 80}, { 96, 96}, + {112, 112}, {128, 128}, {192, 128}, + {192, 192}, {256, 256}, + }; + + bool dims_supported = false; + for (size_t i = 0; i < sizeof(supported_dims)/sizeof(supported_dims[0]); ++i) { + if (supported_dims[i].dk == dk && supported_dims[i].dv == dv) { + dims_supported = true; + break; + } + } + if (!dims_supported) { + return false; + } + + const bool is_f32_f32 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F32 && + v->type == GGML_TYPE_F32 && op->type == GGML_TYPE_F32; + const bool is_f16_f16 = q->type == GGML_TYPE_F16 && k->type == GGML_TYPE_F16 && + v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F16; + const bool is_f32_f16 = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16 && + v->type == GGML_TYPE_F16 && op->type == GGML_TYPE_F32; + + return is_f32_f32 || is_f16_f16 || is_f32_f16; + } default: return false; } @@ -2443,6 +3030,7 @@ static ggml_backend_i ggml_backend_openc /* .graph_compute = */ ggml_backend_opencl_graph_compute, /* .event_record = */ NULL, /* .event_wait = */ NULL, + /* .graph_optimize = */ NULL, }; ggml_backend_t ggml_backend_opencl_init(void) { @@ -2450,10 +3038,10 @@ ggml_backend_t ggml_backend_opencl_init( ggml_backend_opencl_context *backend_ctx = ggml_cl2_init(dev); ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_opencl_guid(), - /* .interface = */ ggml_backend_opencl_i, - /* .device = */ dev, - /* .context = */ backend_ctx + /* .guid = */ ggml_backend_opencl_guid(), + /* .iface = */ ggml_backend_opencl_i, + /* .device = */ dev, + /* .context = */ backend_ctx }; return backend; @@ -2498,6 +3086,18 @@ struct ggml_backend_opencl_buffer_contex for (ggml_tensor_extra_cl_q4_0 * e : temp_tensor_extras_q4_0_in_use) { delete e; } + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4) { + delete e; + } + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { + delete e; + } + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0) { + delete e; + } + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { + delete e; + } } ggml_tensor_extra_cl * ggml_opencl_alloc_temp_tensor_extra() { @@ -2530,6 +3130,36 @@ struct ggml_backend_opencl_buffer_contex return extra; } + ggml_tensor_extra_cl_mxfp4 * ggml_opencl_alloc_temp_tensor_extra_mxfp4() { + ggml_tensor_extra_cl_mxfp4 * extra; + if (temp_tensor_extras_mxfp4.empty()) { + extra = new ggml_tensor_extra_cl_mxfp4(); + } else { + extra = temp_tensor_extras_mxfp4.back(); + temp_tensor_extras_mxfp4.pop_back(); + } + + temp_tensor_extras_mxfp4_in_use.push_back(extra); + + extra->reset(); + return extra; + } + + ggml_tensor_extra_cl_q8_0 * ggml_opencl_alloc_temp_tensor_extra_q8_0() { + ggml_tensor_extra_cl_q8_0 * extra; + if (temp_tensor_extras_q8_0.empty()) { + extra = new ggml_tensor_extra_cl_q8_0(); + } else { + extra = temp_tensor_extras_q8_0.back(); + temp_tensor_extras_q8_0.pop_back(); + } + + temp_tensor_extras_q8_0_in_use.push_back(extra); + + extra->reset(); + return extra; + } + void reset() { for (ggml_tensor_extra_cl * e : temp_tensor_extras_in_use) { temp_tensor_extras.push_back(e); @@ -2540,6 +3170,16 @@ struct ggml_backend_opencl_buffer_contex temp_tensor_extras_q4_0.push_back(e); } temp_tensor_extras_q4_0_in_use.clear(); + + for (ggml_tensor_extra_cl_mxfp4 * e : temp_tensor_extras_mxfp4_in_use) { + temp_tensor_extras_mxfp4.push_back(e); + } + temp_tensor_extras_mxfp4_in_use.clear(); + + for (ggml_tensor_extra_cl_q8_0 * e : temp_tensor_extras_q8_0_in_use) { + temp_tensor_extras_q8_0.push_back(e); + } + temp_tensor_extras_q8_0_in_use.clear(); } // Pools for extras. Available extras are in `temp_tensor_extras`. Extras @@ -2551,6 +3191,10 @@ struct ggml_backend_opencl_buffer_contex std::vector temp_tensor_extras_in_use; std::vector temp_tensor_extras_q4_0; std::vector temp_tensor_extras_q4_0_in_use; + std::vector temp_tensor_extras_mxfp4; + std::vector temp_tensor_extras_mxfp4_in_use; + std::vector temp_tensor_extras_q8_0; + std::vector temp_tensor_extras_q8_0_in_use; // The buffer_context is initially created by ggml_backend_buft_alloc_buffer // before any tensor is initialized (at the beginning of alloc_tensor_range). @@ -2763,7 +3407,10 @@ static void ggml_backend_opencl_buffer_s // cl_mem qT_d = clCreateBuffer(context, CL_MEM_READ_WRITE, q_size_bytes, NULL, &err); CL_CHECK(err); - // size_t d_size_bytes = M * (K / 32) / 2 * sizeof(float); + bool K_tile_trans = true; + if ((K / 32) % 4 != 0){ + K_tile_trans =false; + } size_t d_size_bytes = M * (K / 32) * 2; region.origin = 0; region.size = d_size_bytes; @@ -2804,10 +3451,15 @@ static void ggml_backend_opencl_buffer_s qT_d_image1D = clCreateImage(context, 0, &img_fmt_1d, &img_desc_1d, NULL, &err); CL_CHECK(err); - img_fmt_1d = { CL_RGBA, CL_HALF_FLOAT }; memset(&img_desc_1d, 0, sizeof(img_desc_1d)); + if (K_tile_trans) { + img_fmt_1d = { CL_RGBA, CL_HALF_FLOAT }; + img_desc_1d.image_width = M * K / 32 / 4; + } else { + img_fmt_1d = { CL_R, CL_HALF_FLOAT }; + img_desc_1d.image_width = M * K / 32; + } img_desc_1d.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER; - img_desc_1d.image_width = M * K / 32 / 4; img_desc_1d.buffer = extra->d; d_d_image1D = clCreateImage(context, 0, &img_fmt_1d, &img_desc_1d, NULL, &err); CL_CHECK(err); @@ -2843,6 +3495,10 @@ static void ggml_backend_opencl_buffer_s int width_s = K / 32 / 4; kernel = backend_ctx->kernel_transpose_16; + if (!K_tile_trans) { + kernel = backend_ctx->kernel_transpose_16_4x1; + width_s = K / 32; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &d_d_image1D)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &dT_d_image1D)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(int), &height_s)); @@ -2882,6 +3538,135 @@ static void ggml_backend_opencl_buffer_s #endif // GGML_OPENCL_USE_ADRENO_KERNELS return; + + } + if (tensor->type == GGML_TYPE_MXFP4) { + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tesnors in OpenCL backend should have been allocated and initialized"); + + // Allocate the new extra and create aliases from the original. + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_mxfp4 * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_mxfp4(); + + size_t size_e = ggml_nelements(tensor)/ggml_blck_size(tensor->type)*sizeof(char); + size_t size_q = ggml_nelements(tensor)/ggml_blck_size(tensor->type)*ggml_blck_size(tensor->type)/2; + GGML_ASSERT(size_e + size_q == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + // The original tensor memory is divided into scales and quants, i.e., + // we first store scales, then quants. + cl_buffer_region region; + + // Create subbuffer for scales. + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_e; + extra->e = clCreateSubBuffer( + extra_orig->data_device, CL_MEM_READ_WRITE, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + auto previous_origin = region.origin; + + // Create subbuffer for quants. + region.origin = align_to(previous_origin + size_e, backend_ctx->alignment); + region.size = size_q; + extra->q = clCreateSubBuffer( + extra_orig->data_device, CL_MEM_READ_WRITE, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + + cl_kernel kernel = backend_ctx->kernel_convert_block_mxfp4; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->e)); + + size_t global_work_size[] = {(size_t)ggml_nelements(tensor)/ggml_blck_size(tensor->type), 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseMemObject(data_device)); + + // Create image for Q + cl_image_format img_format_q = {CL_RG, CL_UNSIGNED_INT32}; + cl_image_desc img_desc_q = { + CL_MEM_OBJECT_IMAGE1D_BUFFER, + static_cast(ggml_nelements(tensor)/32*2), + 0, 0, 0, 0, 0, 0, 0, + { extra->q } + }; + extra->q_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_format_q, &img_desc_q, NULL, &err); + + tensor->extra = extra; + + return; + } + if (tensor->type == GGML_TYPE_Q8_0) { + ggml_tensor_extra_cl * extra_orig = (ggml_tensor_extra_cl *)tensor->extra; + GGML_ASSERT(extra_orig && "Tesnors in OpenCL backend should have been allocated and initialized"); + + // Allocate the new extra and create aliases from the original. + ggml_backend_opencl_buffer_context * ctx = (ggml_backend_opencl_buffer_context *) buffer->context; + ggml_tensor_extra_cl_q8_0 * extra = ctx->ggml_opencl_alloc_temp_tensor_extra_q8_0(); + + size_t size_d = ggml_nelements(tensor)/ggml_blck_size(tensor->type)*sizeof(ggml_fp16_t); + size_t size_q = ggml_nelements(tensor)/ggml_blck_size(tensor->type)*(ggml_blck_size(tensor->type)*sizeof(char)); + GGML_ASSERT(size_d + size_q == ggml_nbytes(tensor) && "Incorrect tensor size"); + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + CL_CHECK(clEnqueueWriteBuffer( + queue, data_device, CL_TRUE, 0, + ggml_nbytes(tensor), data, 0, NULL, NULL)); + + // The original tensor memory is divided into scales and quants, i.e., + // we first store scales, then quants. + cl_buffer_region region; + + // Create subbuffer for scales. + region.origin = align_to(extra_orig->offset + tensor->view_offs + offset, backend_ctx->alignment); + region.size = size_d; + extra->d = clCreateSubBuffer( + extra_orig->data_device, CL_MEM_READ_WRITE, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + auto previous_origin = region.origin; + + // Create subbuffer for quants. + region.origin = align_to(previous_origin + size_d, backend_ctx->alignment); + region.size = size_q; + extra->q = clCreateSubBuffer( + extra_orig->data_device, CL_MEM_READ_WRITE, + CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err); + CL_CHECK(err); + + cl_kernel kernel = backend_ctx->kernel_convert_block_q8_0; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra->d)); + + size_t global_work_size[] = {(size_t)ggml_nelements(tensor)/ggml_blck_size(tensor->type), 1, 1}; + size_t local_work_size[] = {64, 1, 1}; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clReleaseMemObject(data_device)); + + tensor->extra = extra; + + return; } #endif // GGML_OPENCL_SOA_Q @@ -2938,6 +3723,57 @@ static void ggml_backend_opencl_buffer_g size, data, 0, NULL, NULL)); CL_CHECK(clReleaseMemObject(data_device)); return; + } else if (tensor->type == GGML_TYPE_MXFP4) { + ggml_tensor_extra_cl_mxfp4 * extra = (ggml_tensor_extra_cl_mxfp4 *)tensor->extra; + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + + cl_kernel kernel = backend_ctx->kernel_restore_block_mxfp4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->e)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &data_device)); + + size_t global_work_size[] = {(size_t)ggml_nelements(tensor)/ggml_blck_size(tensor->type), 1, 1}; + size_t local_work_size[] = {1, 1, 1}; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, + global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clEnqueueReadBuffer( + queue, data_device, CL_TRUE, offset, + size, data, 0, NULL, NULL)); + CL_CHECK(clReleaseMemObject(data_device)); + return; + } + if (tensor->type == GGML_TYPE_Q8_0) { + ggml_tensor_extra_cl_q8_0 * extra = (ggml_tensor_extra_cl_q8_0 *)tensor->extra; + + cl_int err; + cl_mem data_device = clCreateBuffer(context, CL_MEM_READ_WRITE, + ggml_nbytes(tensor), NULL, &err); + CL_CHECK(err); + + cl_kernel kernel = backend_ctx->kernel_restore_block_q8_0; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &data_device)); + + size_t global_work_size[] = {(size_t)ggml_nelements(tensor)/ggml_blck_size(tensor->type), 1, 1}; + size_t local_work_size[] = {1, 1, 1}; + + cl_event evt; + CL_CHECK(clEnqueueNDRangeKernel(queue, kernel, 3, NULL, + global_work_size, local_work_size, 0, NULL, &evt)); + CL_CHECK(clWaitForEvents(1, &evt)); + CL_CHECK(clEnqueueReadBuffer( + queue, data_device, CL_TRUE, offset, + size, data, 0, NULL, NULL)); + CL_CHECK(clReleaseMemObject(data_device)); + return; } #endif // GGML_OPENCL_SOA_Q @@ -3250,6 +4086,19 @@ static void dump_tensor(ggml_backend_t b CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); CL_CHECK(clEnqueueReadBuffer(queue, extra->d, CL_TRUE, 0, size_d, buf_d, 0, NULL, NULL)); CL_CHECK(clFinish(queue)); + } else if (tensor->type == GGML_TYPE_MXFP4) { + ggml_tensor_extra_cl_mxfp4 * extra = (ggml_tensor_extra_cl_mxfp4 *) tensor->extra; + GGML_ASSERT(extra); + + size_t size_q = ggml_nelements(tensor)/QK_MXFP4 * QK_MXFP4/2; + size_t size_e = ggml_nelements(tensor)/QK_MXFP4 * sizeof(char); + GGML_ASSERT(size_q + size_e == ggml_nbytes(tensor)); + buf_q = malloc(size_q); + buf_d = malloc(size_e); + + CL_CHECK(clEnqueueReadBuffer(queue, extra->q, CL_TRUE, 0, size_q, buf_q, 0, NULL, NULL)); + CL_CHECK(clEnqueueReadBuffer(queue, extra->d, CL_TRUE, 0, size_e, buf_d, 0, NULL, NULL)); + CL_CHECK(clFinish(queue)); } else { // Read out the tensor from GPU memory. ggml_tensor_extra_cl * extra = (ggml_tensor_extra_cl *) tensor->extra; @@ -3437,6 +4286,7 @@ static void ggml_cl_set_rows(ggml_backen GGML_ASSERT(src1->extra); GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src1->type == GGML_TYPE_I64 || src1->type == GGML_TYPE_I32); // ne0 = ne00 // ne2 = ne02 @@ -3479,10 +4329,18 @@ static void ggml_cl_set_rows(ggml_backen switch (dst->type) { case GGML_TYPE_F32: - kernel = backend_ctx->kernel_set_rows_f32; + if (src1->type == GGML_TYPE_I64) { + kernel = backend_ctx->kernel_set_rows_f32_i64; + } else { + kernel = backend_ctx->kernel_set_rows_f32_i32; + } break; case GGML_TYPE_F16: - kernel = backend_ctx->kernel_set_rows_f16; + if (src1->type == GGML_TYPE_I64) { + kernel = backend_ctx->kernel_set_rows_f16_i64; + } else { + kernel = backend_ctx->kernel_set_rows_f16_i32; + } break; default: GGML_ABORT("not implemented"); @@ -3543,35 +4401,35 @@ static void ggml_cl_add(ggml_backend_t b GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - const int ne00 = src0 ? src0->ne[0] : 0; - const int ne01 = src0 ? src0->ne[1] : 0; - const int ne02 = src0 ? src0->ne[2] : 0; - const int ne03 = src0 ? src0->ne[3] : 0; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const cl_ulong nb00 = src0 ? src0->nb[0] : 0; - const cl_ulong nb01 = src0 ? src0->nb[1] : 0; - const cl_ulong nb02 = src0 ? src0->nb[2] : 0; - const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const int ne10 = src1 ? src1->ne[0] : 0; - const int ne11 = src1 ? src1->ne[1] : 0; - const int ne12 = src1 ? src1->ne[2] : 0; - const int ne13 = src1 ? src1->ne[3] : 0; UNUSED(ne13); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; - const cl_ulong nb10 = src1 ? src1->nb[0] : 0; - const cl_ulong nb11 = src1 ? src1->nb[1] : 0; - const cl_ulong nb12 = src1 ? src1->nb[2] : 0; - const cl_ulong nb13 = src1 ? src1->nb[3] : 0; UNUSED(nb13); + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; - const int ne0 = dst ? dst->ne[0] : 0; - const int ne1 = dst ? dst->ne[1] : 0; - const int ne2 = dst ? dst->ne[2] : 0; - const int ne3 = dst ? dst->ne[3] : 0; - - const cl_ulong nb0 = dst ? dst->nb[0] : 0; - const cl_ulong nb1 = dst ? dst->nb[1] : 0; - const cl_ulong nb2 = dst ? dst->nb[2] : 0; - const cl_ulong nb3 = dst ? dst->nb[3] : 0; + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -3583,59 +4441,114 @@ static void ggml_cl_add(ggml_backend_t b cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; - bool bcast_row = false; cl_kernel kernel; - if (ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0) { - GGML_ASSERT(ggml_is_contiguous(src0)); + const bool bcast_row = ggml_nelements(src1) == ne10 && ggml_is_contiguous(src1) && ne00 % 4 == 0 && ne10 % 4 == 0; - // src1 is a row + if (bcast_row) { + GGML_ASSERT(ggml_is_contiguous(src0)); GGML_ASSERT(ne11 == 1); + } - bcast_row = true; - int ne = ne00 / 4; - kernel = backend_ctx->kernel_add_row; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + if (dst->type == GGML_TYPE_F32) { + GGML_ASSERT(src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + } else { + kernel = backend_ctx->kernel_add; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + } + } else if (dst->type == GGML_TYPE_F16) { + GGML_ASSERT(src0->type == GGML_TYPE_F16 || src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); + const int type_src0 = (src0->type == GGML_TYPE_F32); + const int type_src1 = (src1->type == GGML_TYPE_F32); + if (bcast_row) { + kernel = backend_ctx->kernel_add_row_f16; + const int ne = ne00 / 4; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &type_src1)); + } else { + kernel = backend_ctx->kernel_add_f16; + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &type_src0)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(int), &type_src1)); + } } else { - kernel = backend_ctx->kernel_add; - - CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); - CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); - CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); - CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne10)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne11)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb10)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne0)); - CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne1)); - CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne2)); - CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne3)); - CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb0)); - CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nb3)); + GGML_ASSERT(false && "unsupported data types for add"); } if (bcast_row) { @@ -3645,19 +4558,88 @@ static void ggml_cl_add(ggml_backend_t b size_t * local_work_size_ptr = local_work_size; if (n % 64 != 0 && !backend_ctx->non_uniform_workgroups) { - local_work_size_ptr = nullptr; // Let driver choose the work-group sizes. + local_work_size_ptr = nullptr; } - backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size_ptr, dst); + backend_ctx->enqueue_ndrange_kernel(kernel, 1, global_work_size, local_work_size_ptr, dst); } else { unsigned int nth = MIN(64, ne0); - size_t global_work_size[] = {ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {nth, 1, 1}; backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } } +static void ggml_cl_add_id(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + const ggml_tensor * src2 = dst->src[2]; + GGML_ASSERT(src2); + GGML_ASSERT(src2->extra); + + GGML_ASSERT(src0->type == GGML_TYPE_F32); + GGML_ASSERT(src1->type == GGML_TYPE_F32); + GGML_ASSERT(src2->type == GGML_TYPE_I32); + GGML_ASSERT(dst->type == GGML_TYPE_F32); + + GGML_ASSERT(ggml_is_contiguous_rows(src0)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + + const cl_ulong nb11 = src1->nb[1]; + + const cl_ulong nb21 = src2->nb[1]; + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + cl_kernel kernel = backend_ctx->kernel_add_id; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne1)); + + int nth = MIN(ne00, (int) backend_ctx->get_kernel_workgroup_size(kernel)); + size_t global_work_size[] = { (size_t)ne01*nth, (size_t)ne02, 1 }; + size_t local_work_size[] = { (size_t)nth, 1, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + static void ggml_cl_mul(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -3666,35 +4648,39 @@ static void ggml_cl_mul(ggml_backend_t b GGML_ASSERT(dst); GGML_ASSERT(dst->extra); - const int ne00 = src0 ? src0->ne[0] : 0; - const int ne01 = src0 ? src0->ne[1] : 0; - const int ne02 = src0 ? src0->ne[2] : 0; - const int ne03 = src0 ? src0->ne[3] : 0; + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); - const cl_ulong nb00 = src0 ? src0->nb[0] : 0; - const cl_ulong nb01 = src0 ? src0->nb[1] : 0; - const cl_ulong nb02 = src0 ? src0->nb[2] : 0; - const cl_ulong nb03 = src0 ? src0->nb[3] : 0; + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; - const int ne10 = src1 ? src1->ne[0] : 0; - const int ne11 = src1 ? src1->ne[1] : 0; - const int ne12 = src1 ? src1->ne[2] : 0; - const int ne13 = src1 ? src1->ne[3] : 0; UNUSED(ne13); + const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; - const cl_ulong nb10 = src1 ? src1->nb[0] : 0; - const cl_ulong nb11 = src1 ? src1->nb[1] : 0; - const cl_ulong nb12 = src1 ? src1->nb[2] : 0; - const cl_ulong nb13 = src1 ? src1->nb[3] : 0; UNUSED(nb13); + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; UNUSED(ne13); - const int ne0 = dst ? dst->ne[0] : 0; - const int ne1 = dst ? dst->ne[1] : 0; - const int ne2 = dst ? dst->ne[2] : 0; - const int ne3 = dst ? dst->ne[3] : 0; - - const cl_ulong nb0 = dst ? dst->nb[0] : 0; - const cl_ulong nb1 = dst ? dst->nb[1] : 0; - const cl_ulong nb2 = dst ? dst->nb[2] : 0; - const cl_ulong nb3 = dst ? dst->nb[3] : 0; + const cl_ulong nb10 = src1->nb[0]; + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; UNUSED(nb13); + + const int ne0 = dst->ne[0]; + const int ne1 = dst->ne[1]; + const int ne2 = dst->ne[2]; + const int ne3 = dst->ne[3]; + + const cl_ulong nb0 = dst->nb[0]; + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -3717,7 +4703,12 @@ static void ggml_cl_mul(ggml_backend_t b bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_mul_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul_row; + } else { + kernel = backend_ctx->kernel_mul_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3727,7 +4718,11 @@ static void ggml_cl_mul(ggml_backend_t b CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_mul; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_mul; + } else { + kernel = backend_ctx->kernel_mul_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3789,6 +4784,10 @@ static void ggml_cl_div(ggml_backend_t b GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; @@ -3837,7 +4836,12 @@ static void ggml_cl_div(ggml_backend_t b bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_div_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div_row; + } else { + kernel = backend_ctx->kernel_div_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3847,7 +4851,11 @@ static void ggml_cl_div(ggml_backend_t b CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_div; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_div; + } else { + kernel = backend_ctx->kernel_div_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3897,6 +4905,10 @@ static void ggml_cl_sub(ggml_backend_t b GGML_ASSERT(dst); GGML_ASSERT(dst->extra); + GGML_ASSERT(src0->type == src1->type); + GGML_ASSERT(src0->type == dst->type); + GGML_ASSERT(src0->type == GGML_TYPE_F32 || src0->type == GGML_TYPE_F16); + const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; const int ne02 = src0->ne[2]; @@ -3945,7 +4957,12 @@ static void ggml_cl_sub(ggml_backend_t b bcast_row = true; int ne = ne00 / 4; - kernel = backend_ctx->kernel_sub_row; + + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub_row; + } else { + kernel = backend_ctx->kernel_sub_row_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -3955,7 +4972,11 @@ static void ggml_cl_sub(ggml_backend_t b CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne)); } else { - kernel = backend_ctx->kernel_sub; + if (src0->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_sub; + } else { + kernel = backend_ctx->kernel_sub_f16; + } CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); @@ -4403,6 +5424,251 @@ static void ggml_cl_rms_norm(ggml_backen backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); } +static void ggml_opencl_op_rms_norm_fused(ggml_backend_t backend, ggml_tensor * rms_norm_tensor, ggml_tensor * mul_tensor) { + GGML_ASSERT(mul_tensor); + GGML_ASSERT(rms_norm_tensor); + + // src0 is the src of rms_norm, src1 is the other src of mul (one being rms_norm) + const ggml_tensor * src0 = rms_norm_tensor->src[0]; + const ggml_tensor * src1; + if (mul_tensor->src[0] == rms_norm_tensor) { + src1 = mul_tensor->src[1]; + } else if (mul_tensor->src[1] == rms_norm_tensor) { + src1 = mul_tensor->src[0]; + } else { + GGML_ASSERT(false && "Invalid args for rms_norm and mul"); + } + const ggml_tensor * dst = mul_tensor; + + GGML_ASSERT(src0); + GGML_ASSERT(src0->extra); + GGML_ASSERT(src1); + GGML_ASSERT(src1->extra); + GGML_ASSERT(dst); + GGML_ASSERT(dst->extra); + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src0->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + float eps; + memcpy(&eps, rms_norm_tensor->op_params, sizeof(float)); + + const int ne00 = src0->ne[0]; + const int ne01 = src0->ne[1]; + const int ne02 = src0->ne[2]; + const int ne03 = src0->ne[3]; + + const cl_ulong nb01 = src0->nb[1]; + const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; + + const int ne10 = src1->ne[0]; + const int ne11 = src1->ne[1]; + const int ne12 = src1->ne[2]; + const int ne13 = src1->ne[3]; + + const cl_ulong nb11 = src1->nb[1]; + const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; + + const cl_ulong nb1 = dst->nb[1]; + const cl_ulong nb2 = dst->nb[2]; + const cl_ulong nb3 = dst->nb[3]; + + GGML_ASSERT(ne00 % 4 == 0); + + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + } else if (backend_ctx->gpu_family == INTEL) { + sgs = 32; + } else { + GGML_ASSERT(false && "Unsupported GPU"); + } + + cl_kernel kernel = backend_ctx->kernel_rms_norm_mul; + + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00 && nth < max_workgroup_size) { + nth *= 2; + } + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00); + + size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t local_work_size[] = {(size_t)nth, 1, 1}; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float)*nth/sgs, NULL)); + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); +} + +static void ggml_opencl_op_norm_fused(ggml_backend_t backend, ggml_tensor * norm_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { + GGML_ASSERT(norm_tensor && mul_tensor && add_tensor); + + const ggml_tensor * src0 = norm_tensor->src[0]; + const ggml_tensor * src1 = mul_tensor->src[0] == norm_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; + const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; + const ggml_tensor * dst = add_tensor; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + float eps; + memcpy(&eps, norm_tensor->op_params, sizeof(float)); + + const int ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; + const cl_ulong nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; + const int ne10 = src1->ne[0], ne11 = src1->ne[1], ne12 = src1->ne[2], ne13 = src1->ne[3]; + const cl_ulong nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; + const int ne20 = src2->ne[0], ne21 = src2->ne[1], ne22 = src2->ne[2], ne23 = src2->ne[3]; + const cl_ulong nb21 = src2->nb[1], nb22 = src2->nb[2], nb23 = src2->nb[3]; + const cl_ulong nbd1 = dst->nb[1], nbd2 = dst->nb[2], nbd3 = dst->nb[3]; + + size_t sgs; + if (backend_ctx->gpu_family == ADRENO) sgs = 64; + else if (backend_ctx->gpu_family == INTEL) sgs = 32; + else GGML_ASSERT(false && "Unsupported GPU"); + + cl_kernel kernel = backend_ctx->kernel_norm_mul_add; + + int nth = sgs; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + while (nth < ne00/4 && nth < max_workgroup_size) nth *= 2; + nth = MIN(nth, max_workgroup_size); + nth = MIN(nth, ne00/4); + + size_t gws[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; + size_t lws[] = {(size_t)nth, 1, 1}; + size_t num_subgroups = (nth + sgs - 1) / sgs; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne10)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &ne22)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(int), &ne23)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(cl_ulong), &nb22)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(cl_ulong), &nb23)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(cl_ulong), &nbd1)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(cl_ulong), &nbd2)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_ulong), &nbd3)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(float), &eps)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_float2) * num_subgroups, NULL)); + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, gws, lws, dst); +} + +static void ggml_opencl_op_group_norm_fused(ggml_backend_t backend, ggml_tensor * gn_tensor, ggml_tensor * mul_tensor, ggml_tensor * add_tensor) { + GGML_ASSERT(gn_tensor && mul_tensor && add_tensor); + + const ggml_tensor * src0 = gn_tensor->src[0]; + const ggml_tensor * src1 = mul_tensor->src[0] == gn_tensor ? mul_tensor->src[1] : mul_tensor->src[0]; + const ggml_tensor * src2 = add_tensor->src[0] == mul_tensor ? add_tensor->src[1] : add_tensor->src[0]; + const ggml_tensor * dst = add_tensor; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offset2 = extra2->offset + src2->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + int groups; + float eps; + memcpy(&groups, gn_tensor->op_params, sizeof(int)); + memcpy(&eps, (char *)gn_tensor->op_params + sizeof(int), sizeof(float)); + + cl_kernel kernel = backend_ctx->kernel_group_norm_mul_add; + int max_workgroup_size = backend_ctx->get_kernel_workgroup_size(kernel); + int ne = ggml_nelements(src0); + int group_size = ne / groups; + + size_t lws[] = { (size_t)MIN(max_workgroup_size, group_size) }; + size_t gws[] = { (size_t)groups * lws[0] }; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &group_size)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(float), &eps)); + + backend_ctx->enqueue_ndrange_kernel(kernel, 1, gws, lws, dst); +} + static void ggml_cl_group_norm(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -4853,12 +6119,12 @@ static void ggml_cl_concat(ggml_backend_ } else { cl_kernel kernel = backend_ctx->kernel_concat_f32_non_contiguous; - long ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; + cl_long ne00 = src0->ne[0], ne01 = src0->ne[1], ne02 = src0->ne[2], ne03 = src0->ne[3]; cl_ulong nb00 = src0->nb[0], nb01 = src0->nb[1], nb02 = src0->nb[2], nb03 = src0->nb[3]; cl_ulong nb10 = src1->nb[0], nb11 = src1->nb[1], nb12 = src1->nb[2], nb13 = src1->nb[3]; - long d_ne0 = dst->ne[0], d_ne1 = dst->ne[1], d_ne2 = dst->ne[2], d_ne3 = dst->ne[3]; + cl_long d_ne0 = dst->ne[0], d_ne1 = dst->ne[1], d_ne2 = dst->ne[2], d_ne3 = dst->ne[3]; cl_ulong d_nb0 = dst->nb[0], d_nb1 = dst->nb[1], d_nb2 = dst->nb[2], d_nb3 = dst->nb[3]; @@ -4869,10 +6135,10 @@ static void ggml_cl_concat(ggml_backend_ CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad_cl->data_device)); CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &off_dst)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(long), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(long), &ne01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(long), &ne02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(long), &ne03)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_long), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_long), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_long), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_long), &ne03)); CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb00)); CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb01)); CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb02)); @@ -4883,10 +6149,10 @@ static void ggml_cl_concat(ggml_backend_ CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb12)); CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(long), &d_ne0)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(long), &d_ne1)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(long), &d_ne2)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(long), &d_ne3)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_long), &d_ne0)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_long), &d_ne1)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_long), &d_ne2)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_long), &d_ne3)); CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &d_nb0)); CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &d_nb1)); CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &d_nb2)); @@ -4945,6 +6211,142 @@ static void ggml_cl_timestep_embedding(g backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, NULL, dst); } +static void ggml_cl_flash_attn(ggml_backend_t backend, const ggml_tensor * q, const ggml_tensor * k, ggml_tensor * dst) { + const ggml_tensor * v = dst->src[2]; + const ggml_tensor * mask = dst->src[3]; + const ggml_tensor * sinks = dst->src[4]; + GGML_ASSERT(q->extra); + GGML_ASSERT(k->extra); + GGML_ASSERT(v->extra); + GGML_ASSERT(dst->extra); + if (mask) { + GGML_ASSERT(mask->extra); + } + if (sinks) { + GGML_ASSERT(sinks->extra); + } + + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + const int n_q = q->ne[1]; + const int n_kv = k->ne[1]; + const int d_head_q = q->ne[0]; + const int d_head_v = v->ne[0]; + const int n_head = q->ne[2]; + const int n_head_kv = k->ne[2]; + const int n_batch = q->ne[3]; + + cl_kernel kernel = NULL; + + const bool is_f16 = q->type == GGML_TYPE_F16; + const bool is_mixed = q->type == GGML_TYPE_F32 && k->type == GGML_TYPE_F16; + const std::pair dk_dv = {d_head_q, d_head_v}; + + if (n_q == 1) { + if (is_mixed) { + kernel = backend_ctx->kernels_flash_attn_f32_f16_q1.at(dk_dv); + } else if (is_f16) { + kernel = backend_ctx->kernels_flash_attn_f16_q1.at(dk_dv); + } else { + kernel = backend_ctx->kernels_flash_attn_f32_q1.at(dk_dv); + } + } else { + if (is_mixed) { + kernel = backend_ctx->kernels_flash_attn_f32_f16.at(dk_dv); + } else if (is_f16) { + kernel = backend_ctx->kernels_flash_attn_f16.at(dk_dv); + } else { + kernel = backend_ctx->kernels_flash_attn_f32.at(dk_dv); + } + } + GGML_ASSERT(kernel != NULL); + + ggml_tensor_extra_cl * extra_q = (ggml_tensor_extra_cl *)q->extra; + ggml_tensor_extra_cl * extra_k = (ggml_tensor_extra_cl *)k->extra; + ggml_tensor_extra_cl * extra_v = (ggml_tensor_extra_cl *)v->extra; + ggml_tensor_extra_cl * extra_o = (ggml_tensor_extra_cl *)dst->extra; + ggml_tensor_extra_cl * extra_mask = mask ? (ggml_tensor_extra_cl *)mask->extra : NULL; + ggml_tensor_extra_cl * extra_sinks = sinks ? (ggml_tensor_extra_cl *)sinks->extra : NULL; + + cl_ulong offset_q = extra_q->offset + q->view_offs; + cl_ulong offset_k = extra_k->offset + k->view_offs; + cl_ulong offset_v = extra_v->offset + v->view_offs; + cl_ulong offset_o = extra_o->offset + dst->view_offs; + cl_mem mask_buffer = extra_mask ? extra_mask->data_device : NULL; + cl_ulong offset_mask = extra_mask ? extra_mask->offset + mask->view_offs : 0; + cl_mem sinks_buffer = extra_sinks ? extra_sinks->data_device : NULL; + cl_ulong offset_sinks = extra_sinks ? extra_sinks->offset + sinks->view_offs : 0; + + const cl_ulong q_nb1 = q->nb[1], q_nb2 = q->nb[2], q_nb3 = q->nb[3]; + const cl_ulong k_nb1 = k->nb[1], k_nb2 = k->nb[2], k_nb3 = k->nb[3]; + const cl_ulong v_nb1 = v->nb[1], v_nb2 = v->nb[2], v_nb3 = v->nb[3]; + const cl_ulong o_nb1 = dst->nb[1], o_nb2 = dst->nb[2], o_nb3 = dst->nb[3]; + const cl_ulong mask_nb1 = mask ? mask->nb[1] : 0; + const cl_ulong mask_nb2 = mask ? mask->nb[2] : 0; + const cl_ulong mask_nb3 = mask ? mask->nb[3] : 0; + const int mask_ne2 = mask ? mask->ne[2] : 0; + const int mask_ne3 = mask ? mask->ne[3] : 0; + + float scale, max_bias, logit_softcap; + const float * params = (const float *)dst->op_params; + scale = params[0]; + max_bias = params[1]; + logit_softcap = params[2]; + + const int is_causal = (mask == NULL && n_q > 1 && n_q == n_kv); + + const int n_head_log2_val = n_head > 0 ? 1u << (int)floorf(log2f((float)n_head)) : 0; + const float n_head_log2_f = n_head_log2_val > 0 ? (float)n_head_log2_val : 1.0f; + const float m0 = powf(2.0f, -(max_bias) / n_head_log2_f); + const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2_f); + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra_q->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset_q)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra_k->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset_k)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra_v->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset_v)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extra_o->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offset_o)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &n_q)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &n_kv)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &is_causal)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &n_head)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &q_nb1)); CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &q_nb2)); CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &q_nb3)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &k_nb1)); CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &k_nb2)); CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &k_nb3)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &v_nb1)); CL_CHECK(clSetKernelArg(kernel, 20, sizeof(cl_ulong), &v_nb2)); CL_CHECK(clSetKernelArg(kernel, 21, sizeof(cl_ulong), &v_nb3)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(cl_ulong), &o_nb1)); CL_CHECK(clSetKernelArg(kernel, 23, sizeof(cl_ulong), &o_nb2)); CL_CHECK(clSetKernelArg(kernel, 24, sizeof(cl_ulong), &o_nb3)); + CL_CHECK(clSetKernelArg(kernel, 25, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(kernel, 26, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(kernel, 27, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(kernel, 28, sizeof(int), &n_head_log2_val)); + CL_CHECK(clSetKernelArg(kernel, 29, sizeof(float), &logit_softcap)); + CL_CHECK(clSetKernelArg(kernel, 30, sizeof(int), &n_head_kv)); + CL_CHECK(clSetKernelArg(kernel, 31, sizeof(cl_mem), &mask_buffer)); + CL_CHECK(clSetKernelArg(kernel, 32, sizeof(cl_ulong), &offset_mask)); + CL_CHECK(clSetKernelArg(kernel, 33, sizeof(cl_ulong), &mask_nb1)); + CL_CHECK(clSetKernelArg(kernel, 34, sizeof(cl_ulong), &mask_nb2)); + CL_CHECK(clSetKernelArg(kernel, 35, sizeof(cl_ulong), &mask_nb3)); + CL_CHECK(clSetKernelArg(kernel, 36, sizeof(int), &mask_ne2)); + CL_CHECK(clSetKernelArg(kernel, 37, sizeof(int), &mask_ne3)); + CL_CHECK(clSetKernelArg(kernel, 38, sizeof(cl_mem), &sinks_buffer)); + CL_CHECK(clSetKernelArg(kernel, 39, sizeof(cl_ulong), &offset_sinks)); + + if (n_q == 1) { + const size_t wg_size = 64; + size_t local_work_size[] = { wg_size, 1 }; + size_t global_work_size[] = { wg_size, (size_t)(n_head * n_batch) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + } else { + const int block_m = backend_ctx->kernels_flash_attn_bm.at(dk_dv); + const size_t wg_size = block_m; + size_t local_work_size[] = { wg_size, 1 }; + size_t global_work_size[] = { (size_t)((n_q + block_m - 1) / block_m) * wg_size, (size_t)(n_head * n_batch) }; + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); + } +} + static void ggml_cl_mul_mat_f16_f32_tiled(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; @@ -4997,6 +6399,82 @@ static void ggml_cl_mul_mat_f16_f32_tile backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); } +static void ggml_cl_conv_2d(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { + GGML_TENSOR_BINARY_OP_LOCALS; + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; + ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; + ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + + cl_ulong offset0 = extra0->offset + src0->view_offs; + cl_ulong offset1 = extra1->offset + src1->view_offs; + cl_ulong offsetd = extrad->offset + dst->view_offs; + + const cl_uint Cout = ne03; const cl_uint Cin = ne02; const cl_uint N = ne13; + const cl_uint KW = ne00; const cl_uint KH = ne01; const cl_uint W = ne10; const cl_uint H = ne11; const cl_uint OW = ne0; const cl_uint OH = ne1; + + const cl_uint s0 = dst->op_params[0]; const cl_uint s1 = dst->op_params[1]; + const cl_uint p0 = dst->op_params[2]; const cl_uint p1 = dst->op_params[3]; + const cl_uint d0 = dst->op_params[4]; const cl_uint d1 = dst->op_params[5]; + + const cl_uint cl_nb01 = nb01/ggml_type_size(src0->type); const cl_uint cl_nb02 = nb02/ggml_type_size(src0->type); const cl_uint cl_nb03 = nb03/ggml_type_size(src0->type); + const cl_uint cl_nb11 = nb11/ggml_type_size(src1->type); const cl_uint cl_nb12 = nb12/ggml_type_size(src1->type); const cl_uint cl_nb13 = nb13/ggml_type_size(src1->type); + const cl_uint cl_nb1 = nb1/ggml_type_size(dst->type); const cl_uint cl_nb2 = nb2/ggml_type_size(dst->type); const cl_uint cl_nb3 = nb3/ggml_type_size(dst->type); + + const int64_t NPQ = (int64_t)N * OW * OH; + + const uint32_t BS_K = 64; + const uint32_t BS_NPQ = 64; + const uint32_t BS_CRS = 16; + const uint32_t VEC_SIZE = 4; + + const uint32_t TS_K = 4; + const uint32_t TS_NPQ = 8; + + const uint32_t WG_K = BS_K / TS_K; + const uint32_t WG_NPQ = BS_NPQ / TS_NPQ; + + auto splitWork = [](uint32_t work_size, uint32_t block_size) { return (block_size + work_size - 1) / block_size; }; + const uint32_t NB_K = splitWork(Cout, BS_K); + const uint32_t NB_NPQ = splitWork(NPQ, BS_NPQ); + + cl_kernel kernel; + size_t shmem_size; + + if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F16) { + kernel = backend_ctx->kernel_conv_2d_f16; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_half4)); + } else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_float) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else if (src0->type == GGML_TYPE_F16 && src1->type == GGML_TYPE_F32) { + kernel = backend_ctx->kernel_conv_2d_f16_f32; + shmem_size = (size_t)(BS_K * BS_CRS * sizeof(cl_half) + BS_CRS * (BS_NPQ / VEC_SIZE) * sizeof(cl_float4)); + } else { + GGML_ASSERT(false && "Unsupported data type combination for conv2d"); + } + + cl_uint idx = 0; + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extra1->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_mem), &extrad->data_device)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, idx++, shmem_size, NULL)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cout)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &Cin)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &N)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KW)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &KH)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &W)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &H)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OW)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &OH)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &s1)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &p1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d0)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &d1)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb01)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb02)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb03)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb11)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb12)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb13)); + CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb1)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb2)); CL_CHECK(clSetKernelArg(kernel, idx++, sizeof(cl_uint), &cl_nb3)); + + size_t global_work_size[] = { (size_t)NB_K * WG_K, (size_t)NB_NPQ * WG_NPQ, 1 }; + size_t local_work_size[] = { (size_t)WG_K, (size_t)WG_NPQ, 1 }; + + backend_ctx->enqueue_ndrange_kernel(kernel, 2, global_work_size, local_work_size, dst); +} + static void ggml_cl_mul_mat(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) { GGML_ASSERT(src0); GGML_ASSERT(src0->extra); @@ -5010,18 +6488,6 @@ static void ggml_cl_mul_mat(ggml_backend ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; - if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && - src0->ne[1] > 32 && // M > 32 - src1->ne[1] > 32 && // N > 32 - src0->ne[0] > 32 && // K > 32 - src0->ne[2] == 1 && src0->ne[3] == 1 && - src1->ne[2] == 1 && src1->ne[3] == 1 && - ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && - backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { - ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); - return; - } - ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; @@ -5032,6 +6498,8 @@ static void ggml_cl_mul_mat(ggml_backend #ifdef GGML_OPENCL_SOA_Q ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; + ggml_tensor_extra_cl_mxfp4 * extra0_mxfp4 = (ggml_tensor_extra_cl_mxfp4 *)src0->extra; + ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)src0->extra; #endif const int ne00 = src0 ? src0->ne[0] : 0; @@ -5368,6 +6836,101 @@ static void ggml_cl_mul_mat(ggml_backend } // if (ne01 && ne1) #endif // GGML_OPENCL_USE_ADRENO_KERNELS + // GEMM using local memory + // Current BK = 16, so ne00 % 16 == 0 + if (ggml_is_contiguous(src0) && + ggml_is_contiguous(src1) && + src1t == GGML_TYPE_F32 && + ne00 % 16 == 0 && + ne11 > 1) { + switch(src0t) { + case GGML_TYPE_F32: { + kernel = backend_ctx->kernel_mul_mm_f32_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + case GGML_TYPE_F16: { + kernel = backend_ctx->kernel_mul_mm_f16_f32_l4_lm; + nth0 = 128; // calculated as (BM*BN)/(TM*TN) + + int batch_stride_a = ne00*ne01; + int batch_stride_b = ne10*ne11; + int batch_stride_d = ne0*ne1; + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10)); // stride_a + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne10)); // stride_b + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne01)); // stride_d + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &batch_stride_a)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &batch_stride_b)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &batch_stride_d)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); + + // 64 is block tile size BM and BN - change here when BM and BN in the kernel are changed. + size_t global_work_size[] = {(size_t)(CEIL_DIV(ne01, 64)*nth0), (size_t)(CEIL_DIV(ne11, 64)), (size_t)ne12*ne13}; + size_t local_work_size[] = {(size_t)nth0, 1, 1}; + + backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst); + return; + } + default: + break; + } + } + + if (src0t == GGML_TYPE_F16 && src1t == GGML_TYPE_F32 && + src0->ne[1] > 32 && // M > 32 + src1->ne[1] > 32 && // N > 32 + src0->ne[0] > 32 && // K > 32 + src0->ne[2] == 1 && src0->ne[3] == 1 && + src1->ne[2] == 1 && src1->ne[3] == 1 && + ggml_is_contiguous(src0) && ggml_is_contiguous(src1) && + backend_ctx->kernel_mul_mat_f16_f32_tiled != NULL) { + ggml_cl_mul_mat_f16_f32_tiled(backend, src0, src1, dst); + return; + } + if (!ggml_is_transposed(src0) && !ggml_is_transposed(src1) && src1t == GGML_TYPE_F32 && @@ -5606,7 +7169,84 @@ static void ggml_cl_mul_mat(ggml_backend #endif // GGML_OPENCL_SOA_Q break; case GGML_TYPE_Q4_1: - case GGML_TYPE_Q8_0: + case GGML_TYPE_Q8_0: { +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_q8_0_f32_flat; + + // nth0 - subgroup size + // nth1 - number of subgroups per workgroup + // ndst - number of output values per workgroup = output per subgroup * number of subgroups + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_q8_0_f32; + + // nth0 - subgroup size + // nth1 - number of subgroups per workgroup + // ndst - number of output values per workgroup = output per subgroup * number of subgroups + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*4; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &r3)); +#endif // GGML_OPENCL_SOA_Q + break; + } case GGML_TYPE_Q2_K: case GGML_TYPE_Q3_K: case GGML_TYPE_Q4_K: @@ -5640,11 +7280,87 @@ static void ggml_cl_mul_mat(ggml_backend CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &r2)); CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &r3)); break; + case GGML_TYPE_MXFP4: { +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_mxfp4_f32_flat; + + cl_mem q; + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*2; + + q = extra0_mxfp4->q; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*2; + + q = extra0_mxfp4->q_img; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_mxfp4->e)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r3)); +#else + kernel = backend_ctx->kernel_mul_mv_mxfp4_f32; + + if (backend_ctx->gpu_family == INTEL) { + nth0 = 16; + nth1 = 2; + ndst = nth1*2; + } else if (backend_ctx->gpu_family == ADRENO) { + nth0 = 64; + nth1 = 2; + ndst = nth1*2; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(float)*nth0,nullptr)); +#endif + break; + } default: GGML_ASSERT(false && "not implemented"); } - if (src0t == GGML_TYPE_Q4_0 || + if (src0t == GGML_TYPE_Q4_0 || src0t == GGML_TYPE_MXFP4 || src0t == GGML_TYPE_Q4_1 || src0t == GGML_TYPE_Q8_0 || src0t == GGML_TYPE_Q2_K) { @@ -5693,16 +7409,22 @@ static void ggml_cl_mul_mat_id(ggml_back ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; + ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra; ggml_tensor_extra_cl * extra2 = (ggml_tensor_extra_cl *)src2->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; + cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offset1 = extra1->offset + src1->view_offs; cl_ulong offset2 = extra2->offset + src2->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; + GGML_UNUSED(offset0); + #ifdef GGML_OPENCL_SOA_Q ggml_tensor_extra_cl_q4_0 * extra0_q4_0 = (ggml_tensor_extra_cl_q4_0 *)src0->extra; + ggml_tensor_extra_cl_mxfp4 * extra0_mxfp4 = (ggml_tensor_extra_cl_mxfp4 *)src0->extra; + ggml_tensor_extra_cl_q8_0 * extra0_q8_0 = (ggml_tensor_extra_cl_q8_0 *)src0->extra; #endif const int ne00 = src0->ne[0]; @@ -5711,7 +7433,9 @@ static void ggml_cl_mul_mat_id(ggml_back const int ne03 = src0->ne[3]; const cl_ulong nb00 = src0->nb[0]; + const cl_ulong nb01 = src0->nb[1]; const cl_ulong nb02 = src0->nb[2]; + const cl_ulong nb03 = src0->nb[3]; const int ne10 = src1->ne[0]; const int ne11 = src1->ne[1]; @@ -5720,6 +7444,7 @@ static void ggml_cl_mul_mat_id(ggml_back const cl_ulong nb11 = src1->nb[1]; const cl_ulong nb12 = src1->nb[2]; + const cl_ulong nb13 = src1->nb[3]; const int ne20 = src2->ne[0]; const int ne21 = src2->ne[1]; @@ -5787,6 +7512,170 @@ static void ggml_cl_mul_mat_id(ggml_back break; } + case GGML_TYPE_Q8_0: { +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_id_q8_0_f32_flat; + + if (backend_ctx->gpu_family == INTEL) { + sgs = 16; + nsg = 2; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + nsg = 2; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q8_0->q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q8_0->d)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne1)); +#else + kernel = backend_ctx->kernel_mul_mv_id_q8_0_f32; + + if (backend_ctx->gpu_family == INTEL) { + sgs = 16; + nsg = 2; + ndst = 4; + } else if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + nsg = 2; + ndst = 4; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(int), &ne01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne1)); +#endif // GGML_OPENCL_SOA_Q + break; + } + case GGML_TYPE_MXFP4: { +#ifdef GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_id_mxfp4_f32_flat; + + cl_mem q; + if (backend_ctx->gpu_family == INTEL) { + sgs = 16; + nsg = 2; + ndst = 2; + + q = extra0_mxfp4->q; + } else if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + nsg = 1; + ndst = 4; + + q = extra0_mxfp4->q_img; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &q)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_mxfp4->e)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); +#else // GGML_OPENCL_SOA_Q + kernel = backend_ctx->kernel_mul_mv_id_mxfp4_f32; + + if (backend_ctx->gpu_family == INTEL) { + sgs = 16; + nsg = 2; + ndst = 2; + } else if (backend_ctx->gpu_family == ADRENO) { + sgs = 64; + nsg = 2; + ndst = 2; + } else { + GGML_ASSERT(false && "TODO: Unknown GPU"); + } + + CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); + CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra1->data_device)); + CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extra2->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne11)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(int), &ne20)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(int), &ne21)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb21)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(int), &ne0)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(int), &ne1)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &r2)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(int), &r3)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(float)*sgs,nullptr)); +#endif // GGML_OPENCL_SOA_Q + break; + } default: GGML_ASSERT(false && "not implemented");; } @@ -6027,17 +7916,24 @@ static void ggml_cl_soft_max(ggml_backen GGML_ASSERT(src1->extra); } + const ggml_tensor * src2 = dst->src[2]; + if (src2) { + GGML_ASSERT(src2->extra); + } + ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context; ggml_tensor_extra_cl * extra0 = (ggml_tensor_extra_cl *)src0->extra; ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra; ggml_tensor_extra_cl * extra1 = src1 ? (ggml_tensor_extra_cl *)src1->extra : nullptr; + ggml_tensor_extra_cl * extra2 = src2 ? (ggml_tensor_extra_cl *)src2->extra : nullptr; cl_ulong offset0 = extra0->offset + src0->view_offs; cl_ulong offsetd = extrad->offset + dst->view_offs; cl_ulong offset1 = extra1 ? extra1->offset + src1->view_offs : offset0; + cl_ulong offset2 = extra2 ? extra2->offset + src2->view_offs : offset0; const int ne00 = src0->ne[0]; const int ne01 = src0->ne[1]; @@ -6105,25 +8001,27 @@ static void ggml_cl_soft_max(ggml_backen CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_ulong), &offset0)); CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), extra1 ? &extra1->data_device : &extra0->data_device)); CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_ulong), &offset1)); - CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &extrad->data_device)); - CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offsetd)); - CL_CHECK(clSetKernelArg(kernel, 6, sizeof(int), &ne00)); - CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &nb01)); - CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_ulong), &nb02)); - CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb03)); - CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne12)); - CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne13)); - CL_CHECK(clSetKernelArg(kernel, 12, sizeof(cl_ulong), &nb11)); - CL_CHECK(clSetKernelArg(kernel, 13, sizeof(cl_ulong), &nb12)); - CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb13)); - CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb1)); - CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb2)); - CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb3)); - CL_CHECK(clSetKernelArg(kernel, 18, sizeof(float), &scale)); - CL_CHECK(clSetKernelArg(kernel, 19, sizeof(float), &max_bias)); - CL_CHECK(clSetKernelArg(kernel, 20, sizeof(float), &m0)); - CL_CHECK(clSetKernelArg(kernel, 21, sizeof(float), &m1)); - CL_CHECK(clSetKernelArg(kernel, 22, sizeof(int), &n_head_log2)); + CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), extra2 ? &extra2->data_device : &extra0->data_device)); + CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_ulong), &offset2)); + CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_mem), &extrad->data_device)); + CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_ulong), &offsetd)); + CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &ne00)); + CL_CHECK(clSetKernelArg(kernel, 9, sizeof(cl_ulong), &nb01)); + CL_CHECK(clSetKernelArg(kernel, 10, sizeof(cl_ulong), &nb02)); + CL_CHECK(clSetKernelArg(kernel, 11, sizeof(cl_ulong), &nb03)); + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(int), &ne12)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(int), &ne13)); + CL_CHECK(clSetKernelArg(kernel, 14, sizeof(cl_ulong), &nb11)); + CL_CHECK(clSetKernelArg(kernel, 15, sizeof(cl_ulong), &nb12)); + CL_CHECK(clSetKernelArg(kernel, 16, sizeof(cl_ulong), &nb13)); + CL_CHECK(clSetKernelArg(kernel, 17, sizeof(cl_ulong), &nb1)); + CL_CHECK(clSetKernelArg(kernel, 18, sizeof(cl_ulong), &nb2)); + CL_CHECK(clSetKernelArg(kernel, 19, sizeof(cl_ulong), &nb3)); + CL_CHECK(clSetKernelArg(kernel, 20, sizeof(float), &scale)); + CL_CHECK(clSetKernelArg(kernel, 21, sizeof(float), &max_bias)); + CL_CHECK(clSetKernelArg(kernel, 22, sizeof(float), &m0)); + CL_CHECK(clSetKernelArg(kernel, 23, sizeof(float), &m1)); + CL_CHECK(clSetKernelArg(kernel, 24, sizeof(int), &n_head_log2)); size_t global_work_size[] = {(size_t)ne01*nth, (size_t)ne02, (size_t)ne03}; size_t local_work_size[] = {(size_t)nth, 1, 1}; @@ -6530,6 +8428,9 @@ static void ggml_cl_glu(ggml_backend_t b kernel = backend_ctx->kernel_swiglu_f16; } break; + case GGML_GLU_OP_SWIGLU_OAI: + kernel = backend_ctx->kernel_swiglu_oai; + break; case GGML_GLU_OP_GEGLU_ERF: if (dst->type == GGML_TYPE_F32) { kernel = backend_ctx->kernel_geglu_erf; @@ -6565,7 +8466,10 @@ static void ggml_cl_glu(ggml_backend_t b const cl_ulong nb1 = dst->nb[1]; - const int swp = ((const int32_t *) dst->op_params)[1]; + const int swp = ggml_get_op_params_i32(dst, 1); + const float alpha = ggml_get_op_params_f32(dst, 2); + const float limit = ggml_get_op_params_f32(dst, 3); + const int ne00_off = src1 ? 0 : (swp ? ne0 : 0); const int ne10_off = src1 ? 0 : (swp ? 0 : ne0); @@ -6582,6 +8486,11 @@ static void ggml_cl_glu(ggml_backend_t b CL_CHECK(clSetKernelArg(kernel, 10, sizeof(int), &ne00_off)); CL_CHECK(clSetKernelArg(kernel, 11, sizeof(int), &ne10_off)); + if (ggml_get_glu_op(dst) == GGML_GLU_OP_SWIGLU_OAI) { + CL_CHECK(clSetKernelArg(kernel, 12, sizeof(float), &limit)); + CL_CHECK(clSetKernelArg(kernel, 13, sizeof(float), &alpha)); + } + const size_t nrows = ggml_nrows(src0); size_t nth = 512; size_t global_work_size[] = {nrows*nth, 1, 1}; @@ -6638,6 +8547,12 @@ bool ggml_cl_compute_forward(ggml_backen } func = ggml_cl_add; break; + case GGML_OP_ADD_ID: + if (!any_on_device) { + return false; + } + func = ggml_cl_add_id; + break; case GGML_OP_MUL: if (!any_on_device) { return false; @@ -6751,6 +8666,12 @@ bool ggml_cl_compute_forward(ggml_backen } ggml_cl_upscale(backend, tensor->src[0], tensor); return true; + case GGML_OP_CONV_2D: + if (!any_on_device) { + return false; + } + func = ggml_cl_conv_2d; + break; case GGML_OP_CONCAT: if (!any_on_device) { return false; @@ -6826,6 +8747,12 @@ bool ggml_cl_compute_forward(ggml_backen } func = ggml_cl_sum_rows; break; + case GGML_OP_FLASH_ATTN_EXT: + if (!any_on_device) { + return false; + } + ggml_cl_flash_attn(backend, tensor->src[0], tensor->src[1], tensor); + return true; default: return false; } diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/add.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/add.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/add.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/add.cl 2025-09-30 07:36:33.000000000 +0000 @@ -81,3 +81,110 @@ kernel void kernel_add_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] + src1[idx1]; } + +kernel void kernel_add_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3, + int type_src0, + int type_src1 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + + half v0, v1; + if (type_src0 == 1) { + v0 = convert_half(*((global float *)(src0_ptr + i0*nb00))); + } else { + v0 = *((global half *)(src0_ptr + i0*nb00)); + } + + if (type_src1 == 1) { + v1 = convert_half(*((global float *)(src1_ptr + i10*nb10))); + } else { + v1 = *((global half *)(src1_ptr + i10*nb10)); + } + + *((global half *)(dst_ptr + i0*nb0)) = v0 + v1; + } +} + +kernel void kernel_add_row_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne, + int type_src0, + int type_src1 +) { + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + + half4 v0, v1; + if (type_src0 == 1) { + global float4* src0_f32 = (global float4*)((global char*)src0 + offset0); + v0 = convert_half4(src0_f32[gid]); + } else { + global half4* src0_f16 = (global half4*)((global char*)src0 + offset0); + v0 = src0_f16[gid]; + } + + if (type_src1 == 1) { + global float4* src1_f32 = (global float4*)((global char*)src1 + offset1); + v1 = convert_half4(src1_f32[idx1]); + } else { + global half4* src1_f16 = (global half4*)((global char*)src1 + offset1); + v1 = src1_f16[idx1]; + } + + dst[gid] = v0 + v1; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/add_id.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/add_id.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/add_id.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/add_id.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,42 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +//------------------------------------------------------------------------------ +// add_id +//------------------------------------------------------------------------------ +kernel void kernel_add_id( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * src2, + ulong offset2, + global char * dst, + ulong offsetd, + ulong nb01, + ulong nb02, + ulong nb11, + ulong nb21, + int ne0, + int ne1 +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + src2 = (global char*)((global char*)src2 + offset2); + dst = (global char*)((global char*)dst + offsetd); + + int i1 = get_group_id(0); + int i2 = get_group_id(1); + + const int i11 = *((global const int *) (src2 + i1*sizeof(int) + i2*nb21)); + + const size_t nb1 = ne0 * sizeof(float); + const size_t nb2 = ne1 * nb1; + + global float * dst_row = (global float *)((global char *)dst + i1*nb1 + i2*nb2); + global float * src0_row = (global float *)((global char *)src0 + i1*nb01 + i2*nb02); + global float * src1_row = (global float *)((global char *)src1 + i11*nb11); + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + dst_row[i0] = src0_row[i0] + src1_row[i0]; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,185 @@ +#ifdef USE_FP16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +#define T_FLOAT half +#define T_FLOAT4 half4 +#define VSTORE_T_FLOAT4(data, offset, p) vstore_half4_rte(data, offset, p) +#else +#define T_FLOAT float +#define T_FLOAT4 float4 +#define VSTORE_T_FLOAT4(data, offset, p) vstore4(data, offset, p) +#endif + +#if defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#else +#define REQD_SUBGROUP_SIZE_128 +#endif + +#define T_ACCUM float4 +#define VEC_SIZE 4 + +#define BS_K 64 +#define BS_NPQ 64 +#define BS_CRS 16 + +#define TS_K 4 +#define TS_NPQ 8 + +#define WG_K (BS_K / TS_K) +#define WG_NPQ (BS_NPQ / TS_NPQ) + +#define BS_NPQ_VEC (BS_NPQ / VEC_SIZE) +#define TS_NPQ_VEC (TS_NPQ / VEC_SIZE) + +static inline uint splitWork(uint work_size, uint block_size){ + return (work_size + block_size - 1) / block_size; +} + +REQD_SUBGROUP_SIZE_128 +kernel void kernel_conv_2d( + global void* p_knl, + ulong off_knl, + global void* p_src, + ulong off_src, + global void* p_dst, + ulong off_dst, + local void* shared, + uint Cout, uint Cin, uint N, + uint KW, uint KH, uint W, uint H, uint OW, uint OH, + uint s0, uint s1, uint p0, uint p1, uint d0, uint d1, + uint nb01, uint nb02, uint nb03, + uint nb11, uint nb12, uint nb13, + uint nb1, uint nb2, uint nb3 +) { + global T_FLOAT* knl_data = (global T_FLOAT*) ((global char*)p_knl + off_knl); + global T_FLOAT* src_data = (global T_FLOAT*) ((global char*)p_src + off_src); + global T_FLOAT* dst_data = (global T_FLOAT*) ((global char*)p_dst + off_dst); + + const uint K = Cout; + const uint CRS = Cin*KH*KW; + const uint NPQ = N*OH*OW; + + const uint lid_k = get_local_id(0); + const uint lid_npq = get_local_id(1); + const uint tid = lid_npq * WG_K + lid_k; + + const uint B_idx_K = get_group_id(0); + const uint B_idx_NPQ = get_group_id(1); + + const uint offset_k = B_idx_K * BS_K; + const uint offset_npq = B_idx_NPQ * BS_NPQ; + + local T_FLOAT* Ash = (local T_FLOAT*)shared; + local T_FLOAT4* Bsh = (local T_FLOAT4*) &Ash[BS_K * BS_CRS]; + + T_ACCUM regC[TS_K][TS_NPQ_VEC]; + for (int i = 0; i < TS_K; ++i) { + for (int j = 0; j < TS_NPQ_VEC; ++j) { + regC[i][j] = (T_ACCUM)(0.0f); + } + } + + const uint NB_CRS = splitWork(CRS, BS_CRS); + + for (uint B_idx_CRS = 0; B_idx_CRS < NB_CRS; ++B_idx_CRS) { + const uint offset_crs = B_idx_CRS * BS_CRS; + + for (int i = tid; i < BS_K * BS_CRS; i += (WG_K * WG_NPQ)) { + const uint k_l = i / BS_CRS; + const uint crs_l = i % BS_CRS; + const uint k_g = offset_k + k_l; + const uint crs_g = offset_crs + crs_l; + + if (k_g < K && crs_g < CRS) { + const uint Cin_idx = crs_g / (KW*KH); + const uint KH_idx = (crs_g - Cin_idx*KW*KH) / KW; + const uint KW_idx = crs_g - Cin_idx*KW*KH - KH_idx*KW; + const uint knl_idx = KW_idx + KH_idx*nb01 + Cin_idx*nb02 + k_g*nb03; + Ash[k_l * BS_CRS + crs_l] = knl_data[knl_idx]; + } else { + Ash[k_l * BS_CRS + crs_l] = (T_FLOAT)0.0f; + } + } + + for (int i = tid; i < BS_CRS * BS_NPQ_VEC; i += (WG_K * WG_NPQ)) { + const uint crs_l = i / BS_NPQ_VEC; + const uint npq_l_vec = i % BS_NPQ_VEC; + const uint crs_g = offset_crs + crs_l; + + T_FLOAT4 val = (T_FLOAT4)(0.0f); + if (crs_g < CRS) { + const uint Cin_idx = crs_g / (KW * KH); + const uint KH_idx = (crs_g - Cin_idx * KW * KH) / KW; + const uint KW_idx = crs_g - Cin_idx * KW * KH - KH_idx * KW; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = offset_npq + npq_l_vec * VEC_SIZE + v; + if (npq_g < NPQ) { + const uint N_idx = npq_g / (OH * OW); + const uint pq_idx = npq_g % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + const int H_idx = (int)(OH_idx * s1 + KH_idx * d1 - p1); + const int W_idx = (int)(OW_idx * s0 + KW_idx * d0 - p0); + + if (H_idx >= 0 && H_idx < H && W_idx >= 0 && W_idx < W) { + const uint src_idx = W_idx + H_idx * nb11 + Cin_idx * nb12 + N_idx * nb13; + ((T_FLOAT*)&val)[v] = src_data[src_idx]; + } + } + } + } + Bsh[crs_l * BS_NPQ_VEC + npq_l_vec] = val; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + #pragma unroll + for (uint crs_l = 0; crs_l < BS_CRS; ++crs_l) { + T_FLOAT regA[TS_K]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regA[k_l_reg] = Ash[(lid_k * TS_K + k_l_reg) * BS_CRS + crs_l]; + } + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + T_FLOAT4 regB = Bsh[crs_l * BS_NPQ_VEC + lid_npq * TS_NPQ_VEC + npq_l_vec_reg]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regC[k_l_reg][npq_l_vec_reg] = mad(convert_float(regA[k_l_reg]), convert_float4(regB), regC[k_l_reg][npq_l_vec_reg]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + const uint k_g = offset_k + lid_k * TS_K + k_l_reg; + if (k_g >= K) continue; + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + const uint npq_g_base = offset_npq + (lid_npq * TS_NPQ_VEC + npq_l_vec_reg) * VEC_SIZE; + + const uint N_idx = npq_g_base / (OH * OW); + const uint pq_idx = npq_g_base % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + + if (nb1 == OW && OW_idx + VEC_SIZE <= OW && npq_g_base + VEC_SIZE <= NPQ) { + const uint dst_idx = OW_idx + OH_idx*nb1 + k_g*nb2 + N_idx*nb3; + VSTORE_T_FLOAT4(regC[k_l_reg][npq_l_vec_reg], 0, &dst_data[dst_idx]); + } else { + T_ACCUM res = regC[k_l_reg][npq_l_vec_reg]; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = npq_g_base + v; + if (npq_g < NPQ) { + const uint N_idx_s = npq_g / (OH*OW); + const uint pq_idx_s = npq_g % (OH*OW); + const uint OH_idx_s = pq_idx_s / OW; + const uint OW_idx_s = pq_idx_s % OW; + const uint dst_idx_s = OW_idx_s + OH_idx_s*nb1 + k_g*nb2 + N_idx_s*nb3; + dst_data[dst_idx_s] = (T_FLOAT)(((float*)&res)[v]); + } + } + } + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/conv2d_f16_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,176 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#if defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#else +#define REQD_SUBGROUP_SIZE_128 +#endif + +#define T_ACCUM float4 +#define VEC_SIZE 4 + +#define BS_K 64 +#define BS_NPQ 64 +#define BS_CRS 16 + +#define TS_K 4 +#define TS_NPQ 8 + +#define WG_K (BS_K / TS_K) +#define WG_NPQ (BS_NPQ / TS_NPQ) + +#define BS_NPQ_VEC (BS_NPQ / VEC_SIZE) +#define TS_NPQ_VEC (TS_NPQ / VEC_SIZE) + +static inline uint splitWork(uint work_size, uint block_size){ + return (work_size + block_size - 1) / block_size; +} + +REQD_SUBGROUP_SIZE_128 +kernel void kernel_conv_2d( + global void* p_knl, + ulong off_knl, + global void* p_src, + ulong off_src, + global void* p_dst, + ulong off_dst, + local void* shared, + uint Cout, uint Cin, uint N, + uint KW, uint KH, uint W, uint H, uint OW, uint OH, + uint s0, uint s1, uint p0, uint p1, uint d0, uint d1, + uint nb01, uint nb02, uint nb03, + uint nb11, uint nb12, uint nb13, + uint nb1, uint nb2, uint nb3 +) { + global half* knl_data = (global half*) ((global char*)p_knl + off_knl); + global float* src_data = (global float*) ((global char*)p_src + off_src); + global float* dst_data = (global float*) ((global char*)p_dst + off_dst); + + const uint K = Cout; + const uint CRS = Cin*KH*KW; + const uint NPQ = N*OH*OW; + + const uint lid_k = get_local_id(0); + const uint lid_npq = get_local_id(1); + const uint tid = lid_npq * WG_K + lid_k; + + const uint B_idx_K = get_group_id(0); + const uint B_idx_NPQ = get_group_id(1); + + const uint offset_k = B_idx_K * BS_K; + const uint offset_npq = B_idx_NPQ * BS_NPQ; + + local half* Ash = (local half*)shared; + local float4* Bsh = (local float4*) &Ash[BS_K * BS_CRS]; + + T_ACCUM regC[TS_K][TS_NPQ_VEC]; + for (int i = 0; i < TS_K; ++i) { + for (int j = 0; j < TS_NPQ_VEC; ++j) { + regC[i][j] = (T_ACCUM)(0.0f); + } + } + + const uint NB_CRS = splitWork(CRS, BS_CRS); + + for (uint B_idx_CRS = 0; B_idx_CRS < NB_CRS; ++B_idx_CRS) { + const uint offset_crs = B_idx_CRS * BS_CRS; + + for (int i = tid; i < BS_K * BS_CRS; i += (WG_K * WG_NPQ)) { + const uint k_l = i / BS_CRS; + const uint crs_l = i % BS_CRS; + const uint k_g = offset_k + k_l; + const uint crs_g = offset_crs + crs_l; + + if (k_g < K && crs_g < CRS) { + const uint Cin_idx = crs_g / (KW*KH); + const uint KH_idx = (crs_g - Cin_idx*KW*KH) / KW; + const uint KW_idx = crs_g - Cin_idx*KW*KH - KH_idx*KW; + const uint knl_idx = KW_idx + KH_idx*nb01 + Cin_idx*nb02 + k_g*nb03; + Ash[k_l * BS_CRS + crs_l] = knl_data[knl_idx]; + } else { + Ash[k_l * BS_CRS + crs_l] = (half)0.0f; + } + } + + for (int i = tid; i < BS_CRS * BS_NPQ_VEC; i += (WG_K * WG_NPQ)) { + const uint crs_l = i / BS_NPQ_VEC; + const uint npq_l_vec = i % BS_NPQ_VEC; + const uint crs_g = offset_crs + crs_l; + + float4 val = (float4)(0.0f); + if (crs_g < CRS) { + const uint Cin_idx = crs_g / (KW * KH); + const uint KH_idx = (crs_g - Cin_idx * KW * KH) / KW; + const uint KW_idx = crs_g - Cin_idx * KW * KH - KH_idx * KW; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = offset_npq + npq_l_vec * VEC_SIZE + v; + if (npq_g < NPQ) { + const uint N_idx = npq_g / (OH * OW); + const uint pq_idx = npq_g % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + const int H_idx = (int)(OH_idx * s1 + KH_idx * d1 - p1); + const int W_idx = (int)(OW_idx * s0 + KW_idx * d0 - p0); + + if (H_idx >= 0 && H_idx < H && W_idx >= 0 && W_idx < W) { + const uint src_idx = W_idx + H_idx * nb11 + Cin_idx * nb12 + N_idx * nb13; + ((float*)&val)[v] = src_data[src_idx]; + } + } + } + } + Bsh[crs_l * BS_NPQ_VEC + npq_l_vec] = val; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + #pragma unroll + for (uint crs_l = 0; crs_l < BS_CRS; ++crs_l) { + half regA[TS_K]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regA[k_l_reg] = Ash[(lid_k * TS_K + k_l_reg) * BS_CRS + crs_l]; + } + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + float4 regB = Bsh[crs_l * BS_NPQ_VEC + lid_npq * TS_NPQ_VEC + npq_l_vec_reg]; + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + regC[k_l_reg][npq_l_vec_reg] = mad(convert_float(regA[k_l_reg]), regB, regC[k_l_reg][npq_l_vec_reg]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + for (uint k_l_reg = 0; k_l_reg < TS_K; ++k_l_reg) { + const uint k_g = offset_k + lid_k * TS_K + k_l_reg; + if (k_g >= K) continue; + + for (uint npq_l_vec_reg = 0; npq_l_vec_reg < TS_NPQ_VEC; ++npq_l_vec_reg) { + const uint npq_g_base = offset_npq + (lid_npq * TS_NPQ_VEC + npq_l_vec_reg) * VEC_SIZE; + + const uint N_idx = npq_g_base / (OH * OW); + const uint pq_idx = npq_g_base % (OH * OW); + const uint OH_idx = pq_idx / OW; + const uint OW_idx = pq_idx % OW; + + if (nb1 == OW && OW_idx + VEC_SIZE <= OW && npq_g_base + VEC_SIZE <= NPQ) { + const uint dst_idx = OW_idx + OH_idx*nb1 + k_g*nb2 + N_idx*nb3; + vstore4(regC[k_l_reg][npq_l_vec_reg], 0, &dst_data[dst_idx]); + } else { + T_ACCUM res = regC[k_l_reg][npq_l_vec_reg]; + for (int v = 0; v < VEC_SIZE; ++v) { + const uint npq_g = npq_g_base + v; + if (npq_g < NPQ) { + const uint N_idx_s = npq_g / (OH*OW); + const uint pq_idx_s = npq_g % (OH*OW); + const uint OH_idx_s = pq_idx_s / OW; + const uint OW_idx_s = pq_idx_s % OW; + const uint dst_idx_s = OW_idx_s + OH_idx_s*nb1 + k_g*nb2 + N_idx_s*nb3; + dst_data[dst_idx_s] = ((float*)&res)[v]; + } + } + } + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/cvt.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/cvt.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/cvt.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/cvt.cl 2025-09-30 07:36:33.000000000 +0000 @@ -116,3 +116,87 @@ kernel void kernel_convert_block_q4_0_no #endif } } + +//------------------------------------------------------------------------------ +// block_mxfp4 +//------------------------------------------------------------------------------ +#define QK_MXFP4 32 +struct block_mxfp4 { + uchar e; // E8M0 + uchar qs[QK_MXFP4 / 2]; +}; + +//------------------------------------------------------------------------------ +// kernel_convert_block_mxfp4 +// Convert the block_mxfp4 format to 2 separate arrays (AOS -> SOA). +// This kernel does not deshuffle the bits. +//------------------------------------------------------------------------------ +kernel void kernel_convert_block_mxfp4( + global struct block_mxfp4 * src0, + global uchar * dst_q, + global uchar * dst_e +) { + global struct block_mxfp4 * b = (global struct block_mxfp4 *) src0 + get_global_id(0); + global uchar * q = (global uchar *) dst_q + QK_MXFP4 / 2 * get_global_id(0); + global uchar * e = (global uchar *) dst_e + get_global_id(0); + + *e = b->e; + + for (int i = 0; i < QK_MXFP4 / 2; ++i) { + q[i] = b->qs[i]; + } +} + +kernel void kernel_restore_block_mxfp4( + global uchar * src_q, + global half * src_e, + global struct block_mxfp4 * dst +) { + global struct block_mxfp4 * b = (global struct block_mxfp4 *) dst + get_global_id(0); + global uchar * q = (global uchar *) src_q + QK_MXFP4 / 2 * get_global_id(0); + global uchar * e = (global uchar *) src_e + get_global_id(0); + + b->e = *e; + for (int i = 0; i < QK_MXFP4 / 2; ++i) { + b->qs[i] = q[i]; + } +} + +//------------------------------------------------------------------------------ +// block_q8_0 +//------------------------------------------------------------------------------ +typedef struct { + half d; // delta + char qs[QK8_0]; // quants +} block_q8_0; + +kernel void kernel_convert_block_q8_0( + global block_q8_0 * src0, + global uchar * dst_q, + global half * dst_d +) { + global block_q8_0 * b = (global block_q8_0 *) src0 + get_global_id(0); + global uchar * q = (global uchar *) dst_q + QK8_0*get_global_id(0); + global half * d = (global half *) dst_d + get_global_id(0); + + *d = b->d; + + for (int i = 0; i < QK8_0; ++i) { + q[i] = b->qs[i]; + } +} + +kernel void kernel_restore_block_q8_0( + global uchar * src_q, + global half * src_d, + global block_q8_0 * dst +) { + global block_q8_0 * b = (global block_q8_0 *) dst + get_global_id(0); + global uchar * q = (global uchar *) src_q + QK8_0*get_global_id(0); + global half * d = (global half *) src_d + get_global_id(0); + + b->d = *d; + for (int i = 0; i < QK8_0; ++i) { + b->qs[i] = q[i]; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/div.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/div.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/div.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/div.cl 2025-09-30 07:36:33.000000000 +0000 @@ -70,3 +70,69 @@ kernel void kernel_div_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] / src1[idx1]; } + +kernel void kernel_div_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) / *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_div_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] / src1[idx1]; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f16.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,370 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ACC_TYPE float +#define ACC_TYPE4 float4 +#define DATA_TYPE half +#define DATA_TYPE4 half4 +#define CONVERT_ACC4(x) convert_float4(x) +#define CONVERT_DATA4(x) convert_half4(x) + +#define DK_VEC (DK/4) +#define DV_VEC (DV/4) +#define WG_SIZE (BLOCK_M) +#define Q1_WG_SIZE 64 + +inline float get_alibi_slope( + const float max_bias, const uint h, const uint n_head_log2, const float m0, const float m1 +) { + if (max_bias <= 0.0f) { + return 1.0f; + } + const float base = h < n_head_log2 ? m0 : m1; + const int exph = h < n_head_log2 ? h + 1 : 2*(h - n_head_log2) + 1; + + return pow(base, exph); +} +__kernel void flash_attn_f16( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int block_q_idx = get_group_id(0); + const int head_batch_idx = get_global_id(1); + + const int my_query_row = block_q_idx * BLOCK_M + tid; + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + if (my_query_row < n_q) { + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2 + my_query_row * q_nb1; + const global DATA_TYPE4* q_ptr = (const global DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_ACC4(q_ptr[i]); + } + } + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = (ACC_TYPE4)(0.0f); + } + ACC_TYPE m_i = -INFINITY; + ACC_TYPE l_i = 0.0f; + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + __local DATA_TYPE4 l_k[BLOCK_N][DK_VEC]; + __local DATA_TYPE4 l_v[BLOCK_N][DV_VEC]; + + for (int k_start = 0; k_start < n_kv; k_start += BLOCK_N) { + for (int i = tid; i < BLOCK_N * DK_VEC; i += WG_SIZE) { + const int row = i / DK_VEC; + const int col = i % DK_VEC; + const int k_row_idx = k_start + row; + if (k_row_idx < n_kv) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_row_idx * k_nb1; + l_k[row][col] = ((__global DATA_TYPE4*)(k_base + k_row_offset))[col]; + } + } + for (int i = tid; i < BLOCK_N * DV_VEC; i += WG_SIZE) { + const int row = i / DV_VEC; + const int col = i % DV_VEC; + const int v_row_idx = k_start + row; + if (v_row_idx < n_kv) { + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + v_row_idx * v_nb1; + l_v[row][col] = ((__global DATA_TYPE4*)(v_base + v_row_offset))[col]; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + + if (my_query_row >= n_q) { + continue; + } + + for (int j = 0; j < BLOCK_N; j += 2) { + const int k_row0 = k_start + j; + const int k_row1 = k_start + j + 1; + + ACC_TYPE4 dot_acc0 = (ACC_TYPE4)(0.0f); + ACC_TYPE4 dot_acc1 = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc0 = mad(q_priv[k], CONVERT_ACC4(l_k[j][k]), dot_acc0); + dot_acc1 = mad(q_priv[k], CONVERT_ACC4(l_k[j+1][k]), dot_acc1); + } + ACC_TYPE score0 = (dot_acc0.s0 + dot_acc0.s1 + dot_acc0.s2 + dot_acc0.s3) * scale; + ACC_TYPE score1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; + + if (is_causal) { + if (k_row0 > (n_kv - n_q + my_query_row)) score0 = -INFINITY; + if (k_row1 > (n_kv - n_q + my_query_row)) score1 = -INFINITY; + } + + if (k_row0 >= n_kv) score0 = -INFINITY; + if (k_row1 >= n_kv) score1 = -INFINITY; + + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base + my_query_row * mask_nb1); + if (k_row0 < n_kv) score0 += slope * (ACC_TYPE)mask_ptr[k_row0]; + if (k_row1 < n_kv) score1 += slope * (ACC_TYPE)mask_ptr[k_row1]; + } + + if (logit_softcap > 0.0f) { + score0 = logit_softcap * tanh(score0 / logit_softcap); + score1 = logit_softcap * tanh(score1 / logit_softcap); + } + + const ACC_TYPE m_new = max(m_i, max(score0, score1)); + const ACC_TYPE p0 = exp(score0 - m_new); + const ACC_TYPE p1 = exp(score1 - m_new); + const ACC_TYPE scale_prev = exp(m_i - m_new); + + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = o_acc[i] * scale_prev + p0 * CONVERT_ACC4(l_v[j][i]) + p1 * CONVERT_ACC4(l_v[j+1][i]); + } + l_i = l_i * scale_prev + p0 + p1; + m_i = m_new; + } + } + + if (my_query_row < n_q) { + if (sinks_void != NULL) { + const global ACC_TYPE* sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + const ACC_TYPE m_sink = sinks_ptr[head_idx]; + const ACC_TYPE m_final = max(m_i, m_sink); + + const ACC_TYPE scale_o = exp(m_i - m_final); + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] *= scale_o; + } + + l_i = l_i * exp(m_i - m_final) + exp(m_sink - m_final); + } + + const ulong o_row_offset = batch_idx * o_nb3 + my_query_row * o_nb2 + head_idx * o_nb1; + global DATA_TYPE4 *o_row = (global DATA_TYPE4 *)(o_base + o_row_offset); + if (l_i > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_i; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = CONVERT_DATA4(o_acc[i] * l_inv); + } + } else { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = (DATA_TYPE4)(0.0f); + } + } + } +} + +__kernel void flash_attn_f16_q1( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int head_batch_idx = get_global_id(1); + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2; + const global DATA_TYPE4* q_ptr = (const global DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_ACC4(q_ptr[i]); + } + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + const global ACC_TYPE* sinks_ptr = NULL; + if (sinks_void != NULL) { + sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + } + + ACC_TYPE m_i = (sinks_ptr != NULL) ? sinks_ptr[head_idx] : -INFINITY; + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const global DATA_TYPE4* k_ptr = (const global DATA_TYPE4*)(k_base + k_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + m_i = max(m_i, score); + } + + __local ACC_TYPE local_m[Q1_WG_SIZE]; + local_m[tid] = m_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_m[tid] = max(local_m[tid], local_m[tid + s]); + barrier(CLK_LOCAL_MEM_FENCE); + } + const ACC_TYPE m_final = local_m[0]; + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_acc[i] = (ACC_TYPE4)(0.0f); + ACC_TYPE l_i = 0.0f; + + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + k_idx * v_nb1; + const global DATA_TYPE4* k_ptr = (const global DATA_TYPE4*)(k_base + k_row_offset); + const global DATA_TYPE4* v_ptr = (const global DATA_TYPE4*)(v_base + v_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + const ACC_TYPE p = exp(score - m_final); + l_i += p; + #pragma unroll + for (int i = 0; i < DV_VEC; i++) { + o_acc[i] = mad(p, CONVERT_ACC4(v_ptr[i]), o_acc[i]); + } + } + + __local ACC_TYPE local_l[Q1_WG_SIZE]; + __local ACC_TYPE4 local_o_comp[Q1_WG_SIZE]; + local_l[tid] = l_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_l[tid] += local_l[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + + const ulong o_row_offset = batch_idx * o_nb3 + head_idx * o_nb1; + global DATA_TYPE4 *o_row = (global DATA_TYPE4 *)(o_base + o_row_offset); + ACC_TYPE l_final = local_l[0]; + + if (sinks_ptr != NULL) { + l_final += exp(sinks_ptr[head_idx] - m_final); + } + + if (l_final > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_final; + for (int i = 0; i < DV_VEC; i++) { + local_o_comp[tid] = o_acc[i]; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_o_comp[tid] += local_o_comp[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + if (tid == 0) { + o_row[i] = CONVERT_DATA4(local_o_comp[0] * l_inv); + } + } + } else if (tid == 0) { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_row[i] = (DATA_TYPE4)(0.0f); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,370 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ACC_TYPE float +#define ACC_TYPE4 float4 +#define DATA_TYPE float +#define DATA_TYPE4 float4 +#define CONVERT_ACC4(x) (x) +#define CONVERT_DATA4(x) (x) + +#define DK_VEC (DK/4) +#define DV_VEC (DV/4) +#define WG_SIZE (BLOCK_M) +#define Q1_WG_SIZE 64 + +inline float get_alibi_slope( + const float max_bias, const uint h, const uint n_head_log2, const float m0, const float m1 +) { + if (max_bias <= 0.0f) { + return 1.0f; + } + const float base = h < n_head_log2 ? m0 : m1; + const int exph = h < n_head_log2 ? h + 1 : 2*(h - n_head_log2) + 1; + + return pow(base, exph); +} +__kernel void flash_attn_f32( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int block_q_idx = get_group_id(0); + const int head_batch_idx = get_global_id(1); + + const int my_query_row = block_q_idx * BLOCK_M + tid; + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + if (my_query_row < n_q) { + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2 + my_query_row * q_nb1; + const global DATA_TYPE4* q_ptr = (const global DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_ACC4(q_ptr[i]); + } + } + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = (ACC_TYPE4)(0.0f); + } + ACC_TYPE m_i = -INFINITY; + ACC_TYPE l_i = 0.0f; + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + __local DATA_TYPE4 l_k[BLOCK_N][DK_VEC]; + __local DATA_TYPE4 l_v[BLOCK_N][DV_VEC]; + + for (int k_start = 0; k_start < n_kv; k_start += BLOCK_N) { + for (int i = tid; i < BLOCK_N * DK_VEC; i += WG_SIZE) { + const int row = i / DK_VEC; + const int col = i % DK_VEC; + const int k_row_idx = k_start + row; + if (k_row_idx < n_kv) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_row_idx * k_nb1; + l_k[row][col] = ((__global DATA_TYPE4*)(k_base + k_row_offset))[col]; + } + } + for (int i = tid; i < BLOCK_N * DV_VEC; i += WG_SIZE) { + const int row = i / DV_VEC; + const int col = i % DV_VEC; + const int v_row_idx = k_start + row; + if (v_row_idx < n_kv) { + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + v_row_idx * v_nb1; + l_v[row][col] = ((__global DATA_TYPE4*)(v_base + v_row_offset))[col]; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + + if (my_query_row >= n_q) { + continue; + } + + for (int j = 0; j < BLOCK_N; j += 2) { + const int k_row0 = k_start + j; + const int k_row1 = k_start + j + 1; + + ACC_TYPE4 dot_acc0 = (ACC_TYPE4)(0.0f); + ACC_TYPE4 dot_acc1 = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc0 = mad(q_priv[k], CONVERT_ACC4(l_k[j][k]), dot_acc0); + dot_acc1 = mad(q_priv[k], CONVERT_ACC4(l_k[j+1][k]), dot_acc1); + } + ACC_TYPE score0 = (dot_acc0.s0 + dot_acc0.s1 + dot_acc0.s2 + dot_acc0.s3) * scale; + ACC_TYPE score1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; + + if (is_causal) { + if (k_row0 > (n_kv - n_q + my_query_row)) score0 = -INFINITY; + if (k_row1 > (n_kv - n_q + my_query_row)) score1 = -INFINITY; + } + + if (k_row0 >= n_kv) score0 = -INFINITY; + if (k_row1 >= n_kv) score1 = -INFINITY; + + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base + my_query_row * mask_nb1); + if (k_row0 < n_kv) score0 += slope * (ACC_TYPE)mask_ptr[k_row0]; + if (k_row1 < n_kv) score1 += slope * (ACC_TYPE)mask_ptr[k_row1]; + } + + if (logit_softcap > 0.0f) { + score0 = logit_softcap * tanh(score0 / logit_softcap); + score1 = logit_softcap * tanh(score1 / logit_softcap); + } + + const ACC_TYPE m_new = max(m_i, max(score0, score1)); + const ACC_TYPE p0 = exp(score0 - m_new); + const ACC_TYPE p1 = exp(score1 - m_new); + const ACC_TYPE scale_prev = exp(m_i - m_new); + + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = o_acc[i] * scale_prev + p0 * CONVERT_ACC4(l_v[j][i]) + p1 * CONVERT_ACC4(l_v[j+1][i]); + } + l_i = l_i * scale_prev + p0 + p1; + m_i = m_new; + } + } + + if (my_query_row < n_q) { + if (sinks_void != NULL) { + const global ACC_TYPE* sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + const ACC_TYPE m_sink = sinks_ptr[head_idx]; + const ACC_TYPE m_final = max(m_i, m_sink); + + const ACC_TYPE scale_o = exp(m_i - m_final); + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] *= scale_o; + } + + l_i = l_i * exp(m_i - m_final) + exp(m_sink - m_final); + } + + const ulong o_row_offset = batch_idx * o_nb3 + my_query_row * o_nb2 + head_idx * o_nb1; + global DATA_TYPE4 *o_row = (global DATA_TYPE4 *)(o_base + o_row_offset); + if (l_i > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_i; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = CONVERT_DATA4(o_acc[i] * l_inv); + } + } else { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = (DATA_TYPE4)(0.0f); + } + } + } +} + +__kernel void flash_attn_f32_q1( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int head_batch_idx = get_global_id(1); + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2; + const global DATA_TYPE4* q_ptr = (const global DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_ACC4(q_ptr[i]); + } + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + const global ACC_TYPE* sinks_ptr = NULL; + if (sinks_void != NULL) { + sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + } + + ACC_TYPE m_i = (sinks_ptr != NULL) ? sinks_ptr[head_idx] : -INFINITY; + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const global DATA_TYPE4* k_ptr = (const global DATA_TYPE4*)(k_base + k_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + m_i = max(m_i, score); + } + + __local ACC_TYPE local_m[Q1_WG_SIZE]; + local_m[tid] = m_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_m[tid] = max(local_m[tid], local_m[tid + s]); + barrier(CLK_LOCAL_MEM_FENCE); + } + const ACC_TYPE m_final = local_m[0]; + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_acc[i] = (ACC_TYPE4)(0.0f); + ACC_TYPE l_i = 0.0f; + + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + k_idx * v_nb1; + const global DATA_TYPE4* k_ptr = (const global DATA_TYPE4*)(k_base + k_row_offset); + const global DATA_TYPE4* v_ptr = (const global DATA_TYPE4*)(v_base + v_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global DATA_TYPE* mask_ptr = (const global DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + const ACC_TYPE p = exp(score - m_final); + l_i += p; + #pragma unroll + for (int i = 0; i < DV_VEC; i++) { + o_acc[i] = mad(p, CONVERT_ACC4(v_ptr[i]), o_acc[i]); + } + } + + __local ACC_TYPE local_l[Q1_WG_SIZE]; + __local ACC_TYPE4 local_o_comp[Q1_WG_SIZE]; + local_l[tid] = l_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_l[tid] += local_l[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + + const ulong o_row_offset = batch_idx * o_nb3 + head_idx * o_nb1; + global DATA_TYPE4 *o_row = (global DATA_TYPE4 *)(o_base + o_row_offset); + ACC_TYPE l_final = local_l[0]; + + if (sinks_ptr != NULL) { + l_final += exp(sinks_ptr[head_idx] - m_final); + } + + if (l_final > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_final; + for (int i = 0; i < DV_VEC; i++) { + local_o_comp[tid] = o_acc[i]; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_o_comp[tid] += local_o_comp[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + if (tid == 0) { + o_row[i] = CONVERT_DATA4(local_o_comp[0] * l_inv); + } + } + } else if (tid == 0) { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_row[i] = (DATA_TYPE4)(0.0f); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/flash_attn_f32_f16.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,373 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define ACC_TYPE float +#define ACC_TYPE4 float4 +#define Q_DATA_TYPE4 float4 +#define KV_DATA_TYPE4 half4 +#define O_DATA_TYPE4 float4 +#define MASK_DATA_TYPE half +#define CONVERT_Q_ACC4(x) (x) +#define CONVERT_KV_ACC4(x) convert_float4(x) +#define CONVERT_O_DATA4(x) (x) + +#define DK_VEC (DK/4) +#define DV_VEC (DV/4) +#define WG_SIZE (BLOCK_M) +#define Q1_WG_SIZE 64 + +inline float get_alibi_slope( + const float max_bias, const uint h, const uint n_head_log2, const float m0, const float m1 +) { + if (max_bias <= 0.0f) { + return 1.0f; + } + const float base = h < n_head_log2 ? m0 : m1; + const int exph = h < n_head_log2 ? h + 1 : 2*(h - n_head_log2) + 1; + + return pow(base, exph); +} +__kernel void flash_attn_f32_f16( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int block_q_idx = get_group_id(0); + const int head_batch_idx = get_global_id(1); + + const int my_query_row = block_q_idx * BLOCK_M + tid; + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + if (my_query_row < n_q) { + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2 + my_query_row * q_nb1; + const global Q_DATA_TYPE4* q_ptr = (const global Q_DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_Q_ACC4(q_ptr[i]); + } + } + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = (ACC_TYPE4)(0.0f); + } + ACC_TYPE m_i = -INFINITY; + ACC_TYPE l_i = 0.0f; + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + __local KV_DATA_TYPE4 l_k[BLOCK_N][DK_VEC]; + __local KV_DATA_TYPE4 l_v[BLOCK_N][DV_VEC]; + + for (int k_start = 0; k_start < n_kv; k_start += BLOCK_N) { + for (int i = tid; i < BLOCK_N * DK_VEC; i += WG_SIZE) { + const int row = i / DK_VEC; + const int col = i % DK_VEC; + const int k_row_idx = k_start + row; + if (k_row_idx < n_kv) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_row_idx * k_nb1; + l_k[row][col] = ((__global KV_DATA_TYPE4*)(k_base + k_row_offset))[col]; + } + } + for (int i = tid; i < BLOCK_N * DV_VEC; i += WG_SIZE) { + const int row = i / DV_VEC; + const int col = i % DV_VEC; + const int v_row_idx = k_start + row; + if (v_row_idx < n_kv) { + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + v_row_idx * v_nb1; + l_v[row][col] = ((__global KV_DATA_TYPE4*)(v_base + v_row_offset))[col]; + } + } + barrier(CLK_LOCAL_MEM_FENCE); + + if (my_query_row >= n_q) { + continue; + } + + for (int j = 0; j < BLOCK_N; j += 2) { + const int k_row0 = k_start + j; + const int k_row1 = k_start + j + 1; + + ACC_TYPE4 dot_acc0 = (ACC_TYPE4)(0.0f); + ACC_TYPE4 dot_acc1 = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc0 = mad(q_priv[k], CONVERT_KV_ACC4(l_k[j][k]), dot_acc0); + dot_acc1 = mad(q_priv[k], CONVERT_KV_ACC4(l_k[j+1][k]), dot_acc1); + } + ACC_TYPE score0 = (dot_acc0.s0 + dot_acc0.s1 + dot_acc0.s2 + dot_acc0.s3) * scale; + ACC_TYPE score1 = (dot_acc1.s0 + dot_acc1.s1 + dot_acc1.s2 + dot_acc1.s3) * scale; + + if (is_causal) { + if (k_row0 > (n_kv - n_q + my_query_row)) score0 = -INFINITY; + if (k_row1 > (n_kv - n_q + my_query_row)) score1 = -INFINITY; + } + + if (k_row0 >= n_kv) score0 = -INFINITY; + if (k_row1 >= n_kv) score1 = -INFINITY; + + if (mask_base != NULL) { + const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base + my_query_row * mask_nb1); + if (k_row0 < n_kv) score0 += slope * (ACC_TYPE)mask_ptr[k_row0]; + if (k_row1 < n_kv) score1 += slope * (ACC_TYPE)mask_ptr[k_row1]; + } + + if (logit_softcap > 0.0f) { + score0 = logit_softcap * tanh(score0 / logit_softcap); + score1 = logit_softcap * tanh(score1 / logit_softcap); + } + + const ACC_TYPE m_new = max(m_i, max(score0, score1)); + const ACC_TYPE p0 = exp(score0 - m_new); + const ACC_TYPE p1 = exp(score1 - m_new); + const ACC_TYPE scale_prev = exp(m_i - m_new); + + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] = o_acc[i] * scale_prev + p0 * CONVERT_KV_ACC4(l_v[j][i]) + p1 * CONVERT_KV_ACC4(l_v[j+1][i]); + } + l_i = l_i * scale_prev + p0 + p1; + m_i = m_new; + } + } + + if (my_query_row < n_q) { + if (sinks_void != NULL) { + const global ACC_TYPE* sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + const ACC_TYPE m_sink = sinks_ptr[head_idx]; + const ACC_TYPE m_final = max(m_i, m_sink); + + const ACC_TYPE scale_o = exp(m_i - m_final); + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_acc[i] *= scale_o; + } + + l_i = l_i * exp(m_i - m_final) + exp(m_sink - m_final); + } + + const ulong o_row_offset = batch_idx * o_nb3 + my_query_row * o_nb2 + head_idx * o_nb1; + global O_DATA_TYPE4 *o_row = (global O_DATA_TYPE4 *)(o_base + o_row_offset); + if (l_i > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_i; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = CONVERT_O_DATA4(o_acc[i] * l_inv); + } + } else { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) { + o_row[i] = (O_DATA_TYPE4)(0.0f); + } + } + } +} + +__kernel void flash_attn_f32_f16_q1( + const global void * q_void, ulong q_offset, + const global void * k_void, ulong k_offset, + const global void * v_void, ulong v_offset, + global void * o_void, ulong o_offset, + const float scale, + const int n_q, + const int n_kv, + const int is_causal, + const int n_head, + const ulong q_nb1, const ulong q_nb2, const ulong q_nb3, + const ulong k_nb1, const ulong k_nb2, const ulong k_nb3, + const ulong v_nb1, const ulong v_nb2, const ulong v_nb3, + const ulong o_nb1, const ulong o_nb2, const ulong o_nb3, + const float max_bias, + const float m0, + const float m1, + const int n_head_log2, + const float logit_softcap, + const int n_head_kv, + const global void* mask_void, + const ulong mask_offset, + const ulong mask_nb1, + const ulong mask_nb2, + const ulong mask_nb3, + const int mask_ne2, + const int mask_ne3, + const global void* sinks_void, + const ulong sinks_offset +) { + const int tid = get_local_id(0); + const int head_batch_idx = get_global_id(1); + + const int batch_idx = head_batch_idx / n_head; + const int head_idx = head_batch_idx % n_head; + + const int gqa_ratio = n_head / n_head_kv; + const int head_kv_idx = head_idx / gqa_ratio; + + const global char* q_base = (const global char*)q_void + q_offset; + const global char* k_base = (const global char*)k_void + k_offset; + const global char* v_base = (const global char*)v_void + v_offset; + global char* o_base = (global char*)o_void + o_offset; + + const global char* mask_base = NULL; + if (mask_void != NULL) { + const int mask_head_idx = head_idx % mask_ne2; + const int mask_batch_idx = batch_idx % mask_ne3; + mask_base = (const global char*)mask_void + mask_offset + mask_batch_idx * mask_nb3 + mask_head_idx * mask_nb2; + } + + ACC_TYPE4 q_priv[DK_VEC]; + const ulong q_row_offset = batch_idx * q_nb3 + head_idx * q_nb2; + const global Q_DATA_TYPE4* q_ptr = (const global Q_DATA_TYPE4*)(q_base + q_row_offset); + #pragma unroll + for (int i = 0; i < DK_VEC; ++i) { + q_priv[i] = CONVERT_Q_ACC4(q_ptr[i]); + } + + float slope = get_alibi_slope(max_bias, head_idx, n_head_log2, m0, m1); + + const global ACC_TYPE* sinks_ptr = NULL; + if (sinks_void != NULL) { + sinks_ptr = (const global ACC_TYPE*)((const global char*)sinks_void + sinks_offset); + } + + ACC_TYPE m_i = (sinks_ptr != NULL) ? sinks_ptr[head_idx] : -INFINITY; + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const global KV_DATA_TYPE4* k_ptr = (const global KV_DATA_TYPE4*)(k_base + k_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + m_i = max(m_i, score); + } + + __local ACC_TYPE local_m[Q1_WG_SIZE]; + local_m[tid] = m_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_m[tid] = max(local_m[tid], local_m[tid + s]); + barrier(CLK_LOCAL_MEM_FENCE); + } + const ACC_TYPE m_final = local_m[0]; + + ACC_TYPE4 o_acc[DV_VEC]; + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_acc[i] = (ACC_TYPE4)(0.0f); + ACC_TYPE l_i = 0.0f; + + for (int k_idx = tid; k_idx < n_kv; k_idx += Q1_WG_SIZE) { + const ulong k_row_offset = batch_idx * k_nb3 + head_kv_idx * k_nb2 + k_idx * k_nb1; + const ulong v_row_offset = batch_idx * v_nb3 + head_kv_idx * v_nb2 + k_idx * v_nb1; + const global KV_DATA_TYPE4* k_ptr = (const global KV_DATA_TYPE4*)(k_base + k_row_offset); + const global KV_DATA_TYPE4* v_ptr = (const global KV_DATA_TYPE4*)(v_base + v_row_offset); + ACC_TYPE4 dot_acc = (ACC_TYPE4)(0.0f); + #pragma unroll + for (int k = 0; k < DK_VEC; k++) { + dot_acc = mad(q_priv[k], CONVERT_KV_ACC4(k_ptr[k]), dot_acc); + } + ACC_TYPE score = (dot_acc.s0 + dot_acc.s1 + dot_acc.s2 + dot_acc.s3) * scale; + if (mask_base != NULL) { + const global MASK_DATA_TYPE* mask_ptr = (const global MASK_DATA_TYPE*)(mask_base); + score += slope * (ACC_TYPE)mask_ptr[k_idx]; + } + if (logit_softcap > 0.0f) { + score = logit_softcap * tanh(score / logit_softcap); + } + const ACC_TYPE p = exp(score - m_final); + l_i += p; + #pragma unroll + for (int i = 0; i < DV_VEC; i++) { + o_acc[i] = mad(p, CONVERT_KV_ACC4(v_ptr[i]), o_acc[i]); + } + } + + __local ACC_TYPE local_l[Q1_WG_SIZE]; + __local ACC_TYPE4 local_o_comp[Q1_WG_SIZE]; + local_l[tid] = l_i; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_l[tid] += local_l[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + + const ulong o_row_offset = batch_idx * o_nb3 + head_idx * o_nb1; + global O_DATA_TYPE4 *o_row = (global O_DATA_TYPE4 *)(o_base + o_row_offset); + ACC_TYPE l_final = local_l[0]; + + if (sinks_ptr != NULL) { + l_final += exp(sinks_ptr[head_idx] - m_final); + } + + if (l_final > 0.0f) { + const ACC_TYPE l_inv = 1.0f / l_final; + for (int i = 0; i < DV_VEC; i++) { + local_o_comp[tid] = o_acc[i]; + barrier(CLK_LOCAL_MEM_FENCE); + #pragma unroll + for (int s = Q1_WG_SIZE / 2; s > 0; s >>= 1) { + if (tid < s) local_o_comp[tid] += local_o_comp[tid + s]; + barrier(CLK_LOCAL_MEM_FENCE); + } + if (tid == 0) { + o_row[i] = CONVERT_O_DATA4(local_o_comp[0] * l_inv); + } + } + } else if (tid == 0) { + #pragma unroll + for (int i = 0; i < DV_VEC; ++i) o_row[i] = (O_DATA_TYPE4)(0.0f); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/glu.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/glu.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/glu.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/glu.cl 2025-09-30 07:36:33.000000000 +0000 @@ -203,6 +203,47 @@ kernel void kernel_swiglu_f16( } //------------------------------------------------------------------------------ +// swiglu_oai +//------------------------------------------------------------------------------ +kernel void kernel_swiglu_oai( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb01, + ulong nb11, + int ne0, + ulong nb1, + int ne00_off, + int ne10_off, + float limit, + float alpha +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + dst = (global char*)((global char*)dst + offsetd); + + global float * src0_row = (global float *) ((global char *) src0 + get_group_id(0)*nb01) + ne00_off; + global float * src1_row = (global float *) ((global char *) src1 + get_group_id(0)*nb11) + ne10_off; + global float * dst_row = (global float *) ((global char *) dst + get_group_id(0)*nb1); + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + float x0 = src0_row[i0]; + float x1 = src1_row[i0]; + + x0 = min(x0, limit); + x1 = max(min(x1, limit), -limit); + + float out_glu = x0 / (1.0f + exp(-x0 * alpha)); + out_glu = out_glu * (1.0f + x1); + + dst_row[i0] = out_glu; + } +} + +//------------------------------------------------------------------------------ // geglu_erf //------------------------------------------------------------------------------ kernel void kernel_geglu_erf( diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/group_norm.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/group_norm.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/group_norm.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/group_norm.cl 2025-09-30 07:36:33.000000000 +0000 @@ -70,3 +70,52 @@ kernel void kernel_group_norm( dst[j] *= scale; } } + +//------------------------------------------------------------------------------ +// group_norm_mul_add +//------------------------------------------------------------------------------ +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_32 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_group_norm_mul_add( + global float * src0, ulong offset0, + global float * src1, ulong offset1, + global float * src2, ulong offset2, + global float * dst, ulong offsetd, + int ne, + int group_size, + float eps +) { + src0 = (global float *)((global char *)src0 + offset0); + src1 = (global float *)((global char *)src1 + offset1); + src2 = (global float *)((global char *)src2 + offset2); + dst = (global float *)((global char *)dst + offsetd); + + int start = get_group_id(0) * group_size; + int end = start + group_size; + if (end > ne) { + end = ne; + } + + float sum = 0.0f; + float sum_sq = 0.0f; + + for (int j = start + get_local_id(0); j < end; j += get_local_size(0)) { + float val = src0[j]; + sum += val; + sum_sq += val*val; + } + + sum = sub_group_reduce_add(sum); + sum_sq = sub_group_reduce_add(sum_sq); + + const float mean = sum / group_size; + const float var = sum_sq / group_size - mean * mean; + const float scale = rsqrt(var + eps); + + for (int j = start + get_local_id(0); j < end; j += get_local_size(0)) { + dst[j] = ((src0[j] - mean) * scale) * src1[j] + src2[j]; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f16.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f16.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f16.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f16.cl 2025-09-30 07:36:33.000000000 +0000 @@ -31,7 +31,7 @@ kernel void kernel_im2col_f16( src1 = (global float*)((global char*)src1 + offset1); dst = (global half*)((global char*)dst + offsetd); - long ksize = OW * (KH > 1 ? KW : 1); + long ksize = OW * KH; long kx = i / ksize; long kd = kx * ksize; long ky = (i - kd) / OW; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f32.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/im2col_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -31,7 +31,7 @@ kernel void kernel_im2col_f32( src1 = (global float*)((global char*)src1 + offset1); dst = (global float*)((global char*)dst + offsetd); - long ksize = OW * (KH > 1 ? KW : 1); + long ksize = OW * KH; long kx = i / ksize; long kd = kx * ksize; long ky = (i - kd) / OW; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul.cl 2025-09-30 07:36:33.000000000 +0000 @@ -77,3 +77,76 @@ kernel void kernel_mul_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] * src1[idx1]; } + +kernel void kernel_mul_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int ne2, + int ne3, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) * *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_mul_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] * src1[idx1]; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f16_f32_l4_lm.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,132 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 16 +#define TM 4 +#define TN 8 + +kernel void kernel_mul_mm_f16_f32_l4_lm( + global half4 * src0, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float*)((global char*)dst + offsetd); + + local half buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + int pos_a = (batch_idx_a * batch_stride_a + ir * BM * stride_a) / LOAD_VEC_A; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + half cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + const int idx = pos_a + (loadc_a + l) * stride_a / LOAD_VEC_A + loadr_a; + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = src0[idx].s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = src0[idx].s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = src0[idx].s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = src0[idx].s3; + } + + for (int l = 0; l < BN; l += loadstride_b) { + const int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK / LOAD_VEC_A; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(convert_float(cache_a[cr]), cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const int offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mm_f32_f32_l4_lm.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,133 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#define LOAD_VEC_A 4 +#define LOAD_VEC_B 4 + +#define BM 64 +#define BN 64 +#define BK 16 +#define TM 4 +#define TN 8 + +kernel void kernel_mul_mm_f32_f32_l4_lm( + global float4 * src0, + ulong offset0, + global float4 * src1, + ulong offset1, + global float * dst, + ulong offsetd, + + int ne00, + int ne01, + int ne02, + int ne11, + int ne12, + + int stride_a, + int stride_b, + int stride_d, + + int batch_stride_a, + int batch_stride_b, + int batch_stride_d, + + int r2, + int r3 +) { + src0 = (global float4*)((global char*)src0 + offset0); + src1 = (global float4*)((global char*)src1 + offset1); + dst = (global float*)((global char*)dst + offsetd); + + local float buf_a[BM * BK]; + local float buf_b[BN * BK]; + + const int batch_idx = get_global_id(2); + + const int i13 = batch_idx / ne12; + const int i12 = batch_idx % ne12; + + const int i03 = i13 / r3; + const int i02 = i12 / r2; + + const int batch_idx_a = i03 * ne02 + i02; + + const int ir = get_group_id(0); + const int ic = get_group_id(1); + + const int tid = get_local_id(0); + const int th_r = tid % (BM / TM); + const int th_c = tid / (BM / TM); + + const int loadr_a = get_local_id(0) % (BK / LOAD_VEC_A); + const int loadc_a = get_local_id(0) / (BK / LOAD_VEC_A); + const int loadr_b = get_local_id(0) % (BK / LOAD_VEC_B); + const int loadc_b = get_local_id(0) / (BK / LOAD_VEC_B); + + const int loadstride_a = get_local_size(0) * LOAD_VEC_A / BK; + const int loadstride_b = get_local_size(0) * LOAD_VEC_B / BK; + + int pos_a = (batch_idx_a * batch_stride_a + ir * BM * stride_a) / LOAD_VEC_A; + int pos_b = (batch_idx * batch_stride_b + ic * BN * stride_b) / LOAD_VEC_B; + + float sums[TM * TN]; + float cache_a[TM]; + float cache_b[TN]; + + for (int i = 0; i < TM * TN; i++) { + sums[i] = 0.0f; + } + + for (int block = 0; block < ne00; block += BK) { + for (int l = 0; l < BM; l += loadstride_a) { + const int idx = pos_a + (loadc_a + l) * stride_a / LOAD_VEC_A + loadr_a; + buf_a[(loadr_a * LOAD_VEC_A + 0) * BM + loadc_a + l] = src0[idx].s0; + buf_a[(loadr_a * LOAD_VEC_A + 1) * BM + loadc_a + l] = src0[idx].s1; + buf_a[(loadr_a * LOAD_VEC_A + 2) * BM + loadc_a + l] = src0[idx].s2; + buf_a[(loadr_a * LOAD_VEC_A + 3) * BM + loadc_a + l] = src0[idx].s3; + } + + for (int l = 0; l < BN; l += loadstride_b) { + const int idx = pos_b + (loadc_b + l) * stride_b / LOAD_VEC_B + loadr_b; + buf_b[(loadr_b * LOAD_VEC_B + 0) * BN + loadc_b + l] = src1[idx].s0; + buf_b[(loadr_b * LOAD_VEC_B + 1) * BN + loadc_b + l] = src1[idx].s1; + buf_b[(loadr_b * LOAD_VEC_B + 2) * BN + loadc_b + l] = src1[idx].s2; + buf_b[(loadr_b * LOAD_VEC_B + 3) * BN + loadc_b + l] = src1[idx].s3; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + pos_a += BK / LOAD_VEC_A; + pos_b += BK / LOAD_VEC_B; + + for (int i = 0; i < BK; i++) { + for (int j = 0; j < TM; j++) { + cache_a[j] = buf_a[(i) * BM + th_r * TM + j]; + } + + for (int j = 0; j < TN; j++) { + cache_b[j] = buf_b[(i) * BN + th_c * TN + j]; + } + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + const int sums_idx = cc*TM + cr; + sums[sums_idx] = mad(cache_a[cr], cache_b[cc], sums[sums_idx]); + } + } + } + barrier(CLK_LOCAL_MEM_FENCE); + } + + const int dr = ir * BM + th_r * TM; + const int dc = ic * BN + th_c * TN; + + const int offsets = batch_idx * batch_stride_d; + + for (int cc = 0; cc < TN; cc++) { + for (int cr = 0; cr < TM; cr++) { + if (dr + cr < ne01 && dc + cc < ne11) { + dst[offsets + (dc + cc) * stride_d + dr + cr] = sums[cc * TM + cr]; + } + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,189 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_MXFP4 32 +typedef struct { + uchar e; // E8M0 + uchar qs[QK_MXFP4/2]; +} block_mxfp4; + +constant static float kvalues_mxfp4_f[16] = { + 0, .5f, 1.f, 1.5f, 2.f, 3.f, 4.f, 6.f, -0, -.5f, -1.f, -1.5f, -2.f, -3.f, -4.f, -6.f +}; + +static inline float e8m0_to_fp32(uchar x) { + int bits; + + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint) x << 23; + } + + return as_float(bits); +} + +#ifdef INTEL_GPU +#define N_R0_MXFP4 2 // number of rows each subgroup works on +#define N_SG_MXFP4 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_MXFP4 2 +#define N_SG_MXFP4 2 +#define N_SIMDWIDTH 64 +#endif + +inline void mul_mv_mxfp4_f32( + global char * src0, + global char * src1, + global char * dst, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3, + local char * shmem +) { + local float * shmem_f32 = (local float *) shmem; + int nb = ne00/QK_MXFP4; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = 0; + + int first_row = (r0 * N_SG_MXFP4 + get_sub_group_id()) * N_R0_MXFP4; + + uint i12 = im%ne12; + uint i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_mxfp4 * x = (global block_mxfp4 *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + const short ix = get_sub_group_local_id()/2; // 0...15 + const short it = get_sub_group_local_id()%2; // 0 or 1 + + shmem_f32[get_sub_group_local_id()] = kvalues_mxfp4_f[get_sub_group_local_id()%16]; + barrier(CLK_LOCAL_MEM_FENCE); + + float4 yl[4]; + float sumf[N_R0_MXFP4] = {0.f}; + + global float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/2) { + global float4 * y4 = (global float4 *)yb; + yl[0] = y4[0]; + yl[1] = y4[4]; + yl[2] = y4[1]; + yl[3] = y4[5]; + + for (short row = 0; row < N_R0_MXFP4; row++) { + global block_mxfp4 * xb = x + row*nb + ib; + global uchar * q2 = (global uchar *)(xb->qs + 8*it); + + float4 acc1 = yl[0]*(float4)(shmem_f32[q2[0] & 0x0F], shmem_f32[q2[1] & 0x0F], shmem_f32[q2[2] & 0x0F], shmem_f32[q2[3] & 0x0F]); + float4 acc2 = yl[1]*(float4)(shmem_f32[q2[0] >> 4 ], shmem_f32[q2[1] >> 4 ], shmem_f32[q2[2] >> 4 ], shmem_f32[q2[3] >> 4 ]); + float4 acc3 = yl[2]*(float4)(shmem_f32[q2[4] & 0x0F], shmem_f32[q2[5] & 0x0F], shmem_f32[q2[6] & 0x0F], shmem_f32[q2[7] & 0x0F]); + float4 acc4 = yl[3]*(float4)(shmem_f32[q2[4] >> 4 ], shmem_f32[q2[5] >> 4 ], shmem_f32[q2[6] >> 4 ], shmem_f32[q2[7] >> 4 ]); + + acc1 = (acc1 + acc3) + (acc2 + acc4); + + sumf[row] += e8m0_to_fp32(xb->e) * ((acc1.s0 + acc1.s1) + (acc1.s2 + acc1.s3)); + } + + yb += (N_SIMDWIDTH/2) * QK_MXFP4; + } + + global float * dst_f32 = (global float *) dst + (ulong)im*ne0*ne1 + (ulong)r1*ne0; + + for (int row = 0; row < N_R0_MXFP4 && first_row + row < ne0; ++row) { + float sum_all = sub_group_reduce_add(sumf[row]); + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_id_mxfp4_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * src2, + ulong offset2, + global char * dst, + ulong offsetd, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne11, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne20, + int ne21, + ulong nb21, + int ne0, + int ne1, + int r2, + int r3, + local char * shmem +) { + src0 = (global char *)((global char *)src0 + offset0); + src1 = (global char *)((global char *)src1 + offset1); + src2 = (global char *)((global char *)src2 + offset2); + dst = (global char *)((global char *)dst + offsetd); + + const int iid1 = get_group_id(2)/ne20; + const int idx = get_group_id(2)%ne20; + + int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + + int i11 = idx % ne11; + int i12 = iid1; + + int i1 = idx; + int i2 = i12; + + global char * src0_cur = src0 + i02*nb02; + global char * src1_cur = src1 + i11*nb11 + i12*nb12; + + global char * dst_cur = dst + (i1*ne0 + i2*ne1*ne0)*sizeof(float); + + mul_mv_mxfp4_f32(src0_cur, src1_cur, dst_cur, + ne00, nb01, nb02, nb03, ne12, nb11, nb12, nb13, ne0, ne1, r2, r3, shmem); +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_mxfp4_f32_flat.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,176 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_MXFP4 32 + +static inline half4 mxfp4_to_fp16_packed(ushort fp4x4) { + ushort2 fp16_packed_a, fp16_packed_b, bias_a, bias_b, sign_a, sign_b; + fp16_packed_a.lo = (fp4x4 << 9) & 0x0E00; + fp16_packed_a.hi = (fp4x4 << 5) & 0x0E00; + fp16_packed_b.lo = (fp4x4 << 1) & 0x0E00; + fp16_packed_b.hi = (fp4x4 >> 3) & 0x0E00; + + bias_a.lo = (fp16_packed_a.lo == 0) ? 0x0 : 0x3800; + bias_a.hi = (fp16_packed_a.hi == 0) ? 0x0 : 0x3800; + bias_b.lo = (fp16_packed_b.lo == 0) ? 0x0 : 0x3800; + bias_b.hi = (fp16_packed_b.hi == 0) ? 0x0 : 0x3800; + + fp16_packed_a.lo = (fp16_packed_a.lo == 0x0200) ? 0x0 : fp16_packed_a.lo; + fp16_packed_a.hi = (fp16_packed_a.hi == 0x0200) ? 0x0 : fp16_packed_a.hi; + fp16_packed_b.lo = (fp16_packed_b.lo == 0x0200) ? 0x0 : fp16_packed_b.lo; + fp16_packed_b.hi = (fp16_packed_b.hi == 0x0200) ? 0x0 : fp16_packed_b.hi; + + sign_a.lo = (fp4x4 << 12) & 0x8000; + sign_a.hi = (fp4x4 << 8) & 0x8000; + sign_b.lo = (fp4x4 << 4) & 0x8000; + sign_b.hi = fp4x4 & 0x8000; + + fp16_packed_a = sign_a + bias_a + fp16_packed_a; + fp16_packed_b = sign_b + bias_b + fp16_packed_b; + + return as_half4((ushort4)(fp16_packed_a, fp16_packed_b)); +} + +static inline float e8m0_to_fp32(uchar x) { + int bits; + bits = (x == 0) ? 0x00400000 : ((uint) x << 23); + return as_float(bits); +} + +#ifdef INTEL_GPU +#define N_R0_MXFP4 2 // number of rows each subgroup works on +#define N_SG_MXFP4 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_MXFP4 4 +#define N_SG_MXFP4 1 +#define N_SIMDWIDTH 64 +#define SRC0Q_IMG +#endif + +kernel void kernel_mul_mv_id_mxfp4_f32_flat( +#ifdef SRC0Q_IMG + __read_only image1d_buffer_t src0_q, +#else + global uchar * src0_q, +#endif + global uchar * src0_e, + global uchar * src1, + ulong offset1, + global uchar * src2, + ulong offset2, + global uchar * dst, + ulong offsetd, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne11, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne20, + int ne21, + ulong nb21, + int ne0, + int ne1, + int r2, + int r3 +) { + dst = dst + offsetd; + + const int iid1 = get_group_id(2) / ne20; + const int idx = get_group_id(2) % ne20; + + uint i02 = ((global uint *) (src2 + offset2 + iid1 * nb21))[idx]; + + int i11 = idx % ne11; + + int nb = ne00 / QK_MXFP4; + + uint src0_off = i02*nb02; + src0_off /= 17; // 17 = sizeof(block_mxfp4) + + src0_e = src0_e + src0_off; + + dst = dst + (idx * ne0 + iid1 * ne1 * ne0) * sizeof(float); + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + + int first_row = (r0 * N_SG_MXFP4 + get_sub_group_id()) * N_R0_MXFP4; + + uint offset_src0 = first_row*nb01; + offset_src0 /= 17; // 17 = sizeof(block_mxfp4) +#ifdef SRC0Q_IMG + ulong offset_q = src0_off + offset_src0; +#else + src0_q = src0_q + src0_off*16; + global uchar16 * x_q = (global uchar16 *)(src0_q) + offset_src0; +#endif + global uchar * x_e = src0_e + offset_src0; + + const short ix = get_sub_group_local_id() >> 1; + const short it = get_sub_group_local_id() & 1; + + float sumf[N_R0_MXFP4] = {0.f}; + + src1 = src1 + offset1 + i11 * nb11 + iid1 * nb12; + global float * y = (global float *) (src1 + r1 * nb11); + global float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH / 2) { + global float4 * y4 = (global float4 *)yb; + + #pragma unroll + for (short row = 0; row < N_R0_MXFP4; row++) { + uchar xb_e = x_e[row * nb + ib]; +#ifdef SRC0Q_IMG + ushort4 xb_q = as_ushort4(read_imageui(src0_q, (offset_q + row * nb + ib) * 2 + it).xy); +#else + ushort4 xb_q = vload4(0, (global ushort *)((global uchar *)(x_q + row * nb + ib) + 8 * it)); +#endif + + half4 fp16x4_0 = mxfp4_to_fp16_packed(xb_q.s0); + half4 fp16x4_1 = mxfp4_to_fp16_packed(xb_q.s1); + float4 acc1 = y4[0] * (float4)(fp16x4_0.s0, fp16x4_0.s2, fp16x4_1.s0, fp16x4_1.s2); + acc1 += y4[4] * (float4)(fp16x4_0.s1, fp16x4_0.s3, fp16x4_1.s1, fp16x4_1.s3); + + fp16x4_0 = mxfp4_to_fp16_packed(xb_q.s2); + fp16x4_1 = mxfp4_to_fp16_packed(xb_q.s3); + acc1 += y4[1] * (float4)(fp16x4_0.s0, fp16x4_0.s2, fp16x4_1.s0, fp16x4_1.s2); + acc1 += y4[5] * (float4)(fp16x4_0.s1, fp16x4_0.s3, fp16x4_1.s1, fp16x4_1.s3); + + sumf[row] += e8m0_to_fp32(xb_e) * ((acc1.s0 + acc1.s1) + (acc1.s2 + acc1.s3)); + } + + yb += (N_SIMDWIDTH / 2) * QK_MXFP4; + } + + global float * dst_f32 = (global float *)dst + (ulong)r1 * ne0; + + for (int row = 0; row < N_R0_MXFP4 && first_row + row < ne0; ++row) { + float sum_all = sub_group_reduce_add(sumf[row]); + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,140 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK8_0 32 +typedef struct { + half d; // delta + char qs[QK8_0]; // quants +} block_q8_0; + +#define NB_Q8_0 8 + +#ifdef INTEL_GPU +#define N_R0_Q8_0 4 // number of rows each subgroup works on +#define N_SG_Q8_0 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_Q8_0 4 +#define N_SG_Q8_0 2 +#define N_SIMDWIDTH 64 +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_id_q8_0_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * src2, + ulong offset2, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + int ne11, + int ne12, + ulong nb11, + ulong nb12, + int ne20, + int ne21, + ulong nb21, + int ne0, + int ne1 +) { + src0 = (global char *)((global char *)src0 + offset0); + src1 = (global char *)((global char *)src1 + offset1); + src2 = (global char *)((global char *)src2 + offset2); + dst = (global char *)((global char *)dst + offsetd); + + int iid1 = get_group_id(2)/ne20; + int idx = get_group_id(2)%ne20; + + int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + + int i11_ = idx % ne11; + int i12_ = iid1; + + int i1 = idx; + int i2 = i12_; + + global char * src0_cur = src0 + i02*nb02; + global char * src1_cur = src1 + i11_*nb11 + i12_*nb12; + + global char * dst_cur = dst + (i1*ne0 + i2*ne1*ne0)*sizeof(float); + + int nb = ne00/QK8_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + + int first_row = (r0*N_SG_Q8_0 + get_sub_group_id()) * N_R0_Q8_0; + + ulong offset_src1 = r1*nb11; + global float * y = (global float *) (src1_cur + offset_src1); + + // pointers to src0 rows + global block_q8_0 * ax[N_R0_Q8_0]; + for (int row = 0; row < N_R0_Q8_0; ++row) { + ulong offset_src0 = (first_row + row)*nb01; + ax[row] = (global block_q8_0 *) ((global char *) src0_cur + offset_src0); + } + + float yl[NB_Q8_0]; + float sumf[N_R0_Q8_0] = { 0.f }; + + const short ix = get_sub_group_local_id()/4; + const short il = get_sub_group_local_id()%4; + + global float * yb = y + ix*QK8_0 + il*NB_Q8_0; + + // each thread handles NB_Q8_0 quants at a time + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/4) { + for (short i = 0; i < NB_Q8_0; ++i) { + yl[i] = yb[i]; + } + + for (short row = 0; row < N_R0_Q8_0; row++) { + global char * qs = ax[row][ib].qs + il*NB_Q8_0; + float sumq = 0.f; + for (short iq = 0; iq < NB_Q8_0; ++iq) { + sumq += qs[iq] * yl[iq]; + } + sumf[row] += sumq*ax[row][ib].d; + } + + yb += N_SIMDWIDTH*NB_Q8_0; + } + + global float * dst_f32 = (global float *) dst_cur + (ulong)r1*ne0; + + for (int row = 0; row < N_R0_Q8_0; ++row) { + float tot = sub_group_reduce_add(sumf[row]); + + if (get_sub_group_local_id() == 0 && first_row + row < ne01) { + dst_f32[first_row + row] = tot; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_id_q8_0_f32_flat.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,222 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK8_0 32 +typedef struct { + half d; // delta + char qs[QK8_0]; // quants +} block_q8_0; + +#define NB_Q8_0 8 + +#ifdef INTEL_GPU +#define N_R0_Q8_0 4 // number of rows each subgroup works on +#define N_SG_Q8_0 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_Q8_0 4 +#define N_SG_Q8_0 2 +#define N_SIMDWIDTH 64 +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_id_q8_0_f32_flat( + global char * src0_q, + global half * src0_d, + global char * src1, + ulong offset1, + global char * src2, + ulong offset2, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + int ne11, + int ne12, + ulong nb11, + ulong nb12, + int ne20, + int ne21, + ulong nb21, + int ne0, + int ne1 +) { + src1 = (global char *)((global char *)src1 + offset1); + src2 = (global char *)((global char *)src2 + offset2); + dst = (global char *)((global char *)dst + offsetd); + + int iid1 = (int)get_group_id(2)/ne20; + int idx = (int)get_group_id(2)%ne20; + + int i02 = ((global int *) (src2 + iid1*nb21))[idx]; + + int i11_ = idx % ne11; + int i12_ = iid1; + + int i1 = idx; + int i2 = i12_; + + // 34 == sizeof(block_q8_0) + uint src0_off = i02*nb02; + src0_off /= 34; + + global char * src0_q_cur = src0_q + src0_off*sizeof(char)*QK8_0; + global half * src0_d_cur = src0_d + src0_off; + global char * src1_cur = src1 + i11_*nb11 + i12_*nb12; + + global char * dst_cur = dst + (i1*ne0 + i2*ne1*ne0)*sizeof(float); + + int nb = ne00/QK8_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + + int first_row = (r0*N_SG_Q8_0 + get_sub_group_id()) * N_R0_Q8_0; + + ulong offset_src1 = r1*nb11; + global float * y = (global float *) (src1_cur + offset_src1); + + // pointers to src0 rows + uint offset_src0_base = first_row*nb01; + + global char * ax0, * ax1, * ax2, * ax3; + global half * ad0, * ad1, * ad2, * ad3; + uint offset_src0; + + offset_src0 = offset_src0_base + 0*nb01; + offset_src0 = offset_src0/34; + ax0 = (global char *) ((global char *) src0_q_cur + offset_src0*sizeof(char)*QK8_0); + ad0 = (global half *) ((global char *) src0_d_cur + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 1*nb01; + offset_src0 = offset_src0/34; + ax1 = (global char *) ((global char *) src0_q_cur + offset_src0*sizeof(char)*QK8_0); + ad1 = (global half *) ((global char *) src0_d_cur + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 2*nb01; + offset_src0 = offset_src0/34; + ax2 = (global char *) ((global char *) src0_q_cur + offset_src0*sizeof(char)*QK8_0); + ad2 = (global half *) ((global char *) src0_d_cur + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 3*nb01; + offset_src0 = offset_src0/34; + ax3 = (global char *) ((global char *) src0_q_cur + offset_src0*sizeof(char)*QK8_0); + ad3 = (global half *) ((global char *) src0_d_cur + offset_src0*sizeof(half)); + + const short ix = get_sub_group_local_id()/4; + const short il = get_sub_group_local_id()%4; + + global float * yb = y + ix*QK8_0 + il*NB_Q8_0; + + float8 yl; + float8 qv; + float4 sumf = 0.f; + float sumq = 0.f; + global char * qs; + + // each thread handles NB_Q8_0 quants at a time + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/4) { + yl = vload8(0, yb); + + qs = ax0 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s0 += sumq*ad0[ib]; + + qs = ax1 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s1 += sumq*ad1[ib]; + + qs = ax2 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s2 += sumq*ad2[ib]; + + qs = ax3 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s3 += sumq*ad3[ib]; + + yb += N_SIMDWIDTH*NB_Q8_0; + } + + global float * dst_f32 = (global float *) dst_cur + (ulong)r1*ne0; + + float4 tot = (float4)( + sub_group_reduce_add(sumf.s0), + sub_group_reduce_add(sumf.s1), + sub_group_reduce_add(sumf.s2), + sub_group_reduce_add(sumf.s3) + ); + + if (get_sub_group_local_id() == 0) { + if (first_row + 0 < ne01) { + dst_f32[first_row + 0] = tot.s0; + } + if (first_row + 1 < ne01) { + dst_f32[first_row + 1] = tot.s1; + } + if (first_row + 2 < ne01) { + dst_f32[first_row + 2] = tot.s2; + } + if (first_row + 3 < ne01) { + dst_f32[first_row + 3] = tot.s3; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,144 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_MXFP4 32 +typedef struct { + uchar e; // E8M0 + uchar qs[QK_MXFP4/2]; +} block_mxfp4; + +constant static float kvalues_mxfp4_f[16] = { + 0, .5f, 1.f, 1.5f, 2.f, 3.f, 4.f, 6.f, -0, -.5f, -1.f, -1.5f, -2.f, -3.f, -4.f, -6.f +}; + +static inline float e8m0_to_fp32(uchar x) { + int bits; + + if (x == 0) { + bits = 0x00400000; + } else { + bits = (uint) x << 23; + } + + return as_float(bits); +} + +#ifdef INTEL_GPU +#define N_R0_MXFP4 2 // number of rows each subgroup works on +#define N_SG_MXFP4 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_MXFP4 2 +#define N_SG_MXFP4 2 +#define N_SIMDWIDTH 64 +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_mxfp4_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3, + local char * shmem +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + dst = (global char*)((global char*)dst + offsetd); + + local float * shmem_f32 = (local float *) shmem; + int nb = ne00/QK_MXFP4; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + + int first_row = (r0 * N_SG_MXFP4 + get_sub_group_id()) * N_R0_MXFP4; + + uint i12 = im%ne12; + uint i13 = im/ne12; + + ulong offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ulong offset_src1 = r1*nb11 + (i12 )*nb12 + (i13 )*nb13; + + global block_mxfp4 * x = (global block_mxfp4 *) (src0 + offset_src0); + global float * y = (global float *) (src1 + offset_src1); + + const short ix = get_sub_group_local_id()/2; // 0...15 + const short it = get_sub_group_local_id()%2; // 0 or 1 + + shmem_f32[get_sub_group_local_id()] = kvalues_mxfp4_f[get_sub_group_local_id()%16]; + barrier(CLK_LOCAL_MEM_FENCE); + + float4 yl[4]; + float sumf[N_R0_MXFP4] = {0.f}; + + global float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/2) { + global float4 * y4 = (global float4 *)yb; + yl[0] = y4[0]; + yl[1] = y4[4]; + yl[2] = y4[1]; + yl[3] = y4[5]; + + for (short row = 0; row < N_R0_MXFP4; row++) { + global block_mxfp4 * xb = x + row*nb + ib; + global uchar * q2 = (global uchar *)(xb->qs + 8*it); + + float4 acc1 = yl[0]*(float4)(shmem_f32[q2[0] & 0x0F], shmem_f32[q2[1] & 0x0F], shmem_f32[q2[2] & 0x0F], shmem_f32[q2[3] & 0x0F]); + float4 acc2 = yl[1]*(float4)(shmem_f32[q2[0] >> 4 ], shmem_f32[q2[1] >> 4 ], shmem_f32[q2[2] >> 4 ], shmem_f32[q2[3] >> 4 ]); + float4 acc3 = yl[2]*(float4)(shmem_f32[q2[4] & 0x0F], shmem_f32[q2[5] & 0x0F], shmem_f32[q2[6] & 0x0F], shmem_f32[q2[7] & 0x0F]); + float4 acc4 = yl[3]*(float4)(shmem_f32[q2[4] >> 4 ], shmem_f32[q2[5] >> 4 ], shmem_f32[q2[6] >> 4 ], shmem_f32[q2[7] >> 4 ]); + + acc1 = (acc1 + acc3) + (acc2 + acc4); + + sumf[row] += e8m0_to_fp32(xb->e) * ((acc1.s0 + acc1.s1) + (acc1.s2 + acc1.s3)); + } + + yb += (N_SIMDWIDTH/2) * QK_MXFP4; + } + + global float * dst_f32 = (global float *) dst + (ulong)im*ne0*ne1 + (ulong)r1*ne0; + + for (int row = 0; row < N_R0_MXFP4 && first_row + row < ne0; ++row) { + float sum_all = sub_group_reduce_add(sumf[row]); + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_mxfp4_f32_flat.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,167 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK_MXFP4 32 + +static inline half4 mxfp4_to_fp16_packed(ushort fp4x4) { + ushort2 fp16_packed_a, fp16_packed_b, bias_a, bias_b, sign_a, sign_b; + fp16_packed_a.lo = (fp4x4 << 9) & 0x0E00; + fp16_packed_a.hi = (fp4x4 << 5) & 0x0E00; + fp16_packed_b.lo = (fp4x4 << 1) & 0x0E00; + fp16_packed_b.hi = (fp4x4 >> 3) & 0x0E00; + + bias_a.lo = (fp16_packed_a.lo == 0) ? 0x0 : 0x3800; + bias_a.hi = (fp16_packed_a.hi == 0) ? 0x0 : 0x3800; + bias_b.lo = (fp16_packed_b.lo == 0) ? 0x0 : 0x3800; + bias_b.hi = (fp16_packed_b.hi == 0) ? 0x0 : 0x3800; + + fp16_packed_a.lo = (fp16_packed_a.lo == 0x0200) ? 0x0 : fp16_packed_a.lo; + fp16_packed_a.hi = (fp16_packed_a.hi == 0x0200) ? 0x0 : fp16_packed_a.hi; + fp16_packed_b.lo = (fp16_packed_b.lo == 0x0200) ? 0x0 : fp16_packed_b.lo; + fp16_packed_b.hi = (fp16_packed_b.hi == 0x0200) ? 0x0 : fp16_packed_b.hi; + + sign_a.lo = (fp4x4 << 12) & 0x8000; + sign_a.hi = (fp4x4 << 8) & 0x8000; + sign_b.lo = (fp4x4 << 4) & 0x8000; + sign_b.hi = fp4x4 & 0x8000; + + fp16_packed_a = sign_a + bias_a + fp16_packed_a; + fp16_packed_b = sign_b + bias_b + fp16_packed_b; + + return as_half4((ushort4)(fp16_packed_a, fp16_packed_b)); +} + +static inline float e8m0_to_fp32(uchar x) { + int bits; + bits = (x == 0) ? 0x00400000 : ((uint) x << 23); + return as_float(bits); +} + +#ifdef INTEL_GPU +#define N_R0_MXFP4 2 // number of rows each subgroup works on +#define N_SG_MXFP4 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_MXFP4 2 +#define N_SG_MXFP4 2 +#define N_SIMDWIDTH 64 +#define SRC0Q_IMG +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_mxfp4_f32_flat( +#ifdef SRC0Q_IMG + __read_only image1d_buffer_t src0_q, +#else + global uchar * src0_q, +#endif + global uchar * src0_e, + global uchar * src1, + ulong offset1, + global uchar * dst, + ulong offsetd, + int ne00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = src1 + offset1; + dst = dst + offsetd; + + int nb = ne00 / QK_MXFP4; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + + int first_row = (r0 * N_SG_MXFP4 + get_sub_group_id()) * N_R0_MXFP4; + + uint i12 = im % ne12; + uint i13 = im / ne12; + + uint offset_src0 = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + // 17 = sizeof(block_mxfp4) + offset_src0 /= 17; +#ifdef SRC0Q_IMG + ulong offset_q = offset_src0; +#else + global uchar16 * x_q = (global uchar16 *)(src0_q) + offset_src0; +#endif + global uchar * x_e = src0_e + offset_src0; + + ulong offset_src1 = r1 * nb11 + i12 * nb12 + i13 * nb13; + global float * y = (global float *)(src1 + offset_src1); + + const short ix = get_sub_group_local_id() >> 1; // 0...15 + const short it = get_sub_group_local_id() & 1; // 0 or 1 + + float sumf[N_R0_MXFP4] = {0.f}; + + global float * yb = y + ix * QK_MXFP4 + it * 8; + + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/2) { + global float4 * y4 = (global float4 *)yb; + + #pragma unroll + for (short row = 0; row < N_R0_MXFP4; row++) { + uchar xb_e = x_e[row * nb + ib]; +#ifdef SRC0Q_IMG + ushort4 xb_q = as_ushort4(read_imageui(src0_q, (offset_q + row * nb + ib) * 2 + it).xy); +#else + ushort4 xb_q = vload4(0, (global ushort *)((global uchar *)(x_q + row * nb + ib) + 8 * it)); +#endif + + half4 fp16x4_0 = mxfp4_to_fp16_packed(xb_q.s0); + half4 fp16x4_1 = mxfp4_to_fp16_packed(xb_q.s1); + float4 acc1 = y4[0] * (float4)(fp16x4_0.s0, fp16x4_0.s2, fp16x4_1.s0, fp16x4_1.s2); + acc1 += y4[4] * (float4)(fp16x4_0.s1, fp16x4_0.s3, fp16x4_1.s1, fp16x4_1.s3); + + fp16x4_0 = mxfp4_to_fp16_packed(xb_q.s2); + fp16x4_1 = mxfp4_to_fp16_packed(xb_q.s3); + acc1 += y4[1] * (float4)(fp16x4_0.s0, fp16x4_0.s2, fp16x4_1.s0, fp16x4_1.s2); + acc1 += y4[5] * (float4)(fp16x4_0.s1, fp16x4_0.s3, fp16x4_1.s1, fp16x4_1.s3); + + sumf[row] += e8m0_to_fp32(xb_e) * ((acc1.s0 + acc1.s1) + (acc1.s2 + acc1.s3)); + } + + yb += (N_SIMDWIDTH/2) * QK_MXFP4; + } + + global float * dst_f32 = (global float *) dst + (ulong)im*ne0*ne1 + (ulong)r1*ne0; + + for (int row = 0; row < N_R0_MXFP4 && first_row + row < ne0; ++row) { + float sum_all = sub_group_reduce_add(sumf[row]); + if (get_sub_group_local_id() == 0) { + dst_f32[first_row + row] = sum_all; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,125 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK8_0 32 +typedef struct { + half d; // delta + char qs[QK8_0]; // quants +} block_q8_0; + +#define NB_Q8_0 8 + +#ifdef INTEL_GPU +#define N_R0_Q8_0 4 // number of rows each subgroup works on +#define N_SG_Q8_0 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_Q8_0 4 +#define N_SG_Q8_0 2 +#define N_SIMDWIDTH 64 +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q8_0_f32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src0 = (global char*)((global char*)src0 + offset0); + src1 = (global char*)((global char*)src1 + offset1); + dst = (global char*)((global char*)dst + offsetd); + + int nb = ne00/QK8_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + + int first_row = (r0*N_SG_Q8_0 + get_sub_group_id()) * N_R0_Q8_0; + + uint i12 = im%ne12; + uint i13 = im/ne12; + + ulong offset_src1 = r1*nb11 + i12*nb12 + i13*nb13; + global float * y = (global float *) (src1 + offset_src1); + + // pointers to src0 rows + global block_q8_0 * ax[N_R0_Q8_0]; + for (int row = 0; row < N_R0_Q8_0; ++row) { + ulong offset_src0 = (first_row + row)*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + ax[row] = (global block_q8_0 *) ((global char *) src0 + offset_src0); + } + + float yl[NB_Q8_0]; + float sumf[N_R0_Q8_0] = { 0.f }; + + const short ix = get_sub_group_local_id()/4; + const short il = get_sub_group_local_id()%4; + + global float * yb = y + ix*QK8_0 + il*NB_Q8_0; + + // each thread handles NB_Q8_0 quants at a time + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/4) { + for (short i = 0; i < NB_Q8_0; ++i) { + yl[i] = yb[i]; + } + + for (short row = 0; row < N_R0_Q8_0; row++) { + global char * qs = ax[row][ib].qs + il*NB_Q8_0; + float sumq = 0.f; + for (short iq = 0; iq < NB_Q8_0; ++iq) { + sumq += qs[iq] * yl[iq]; + } + sumf[row] += sumq*ax[row][ib].d; + } + + yb += N_SIMDWIDTH*NB_Q8_0; + } + + global float * dst_f32 = (global float *) dst + (ulong)im*ne0*ne1 + (ulong)r1*ne0; + + for (int row = 0; row < N_R0_Q8_0; ++row) { + float tot = sub_group_reduce_add(sumf[row]); + + if (get_sub_group_local_id() == 0 && first_row + row < ne01) { + dst_f32[first_row + row] = tot; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32_flat.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32_flat.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32_flat.cl 1970-01-01 00:00:00.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/mul_mv_q8_0_f32_flat.cl 2025-09-30 07:36:33.000000000 +0000 @@ -0,0 +1,202 @@ +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +#ifdef cl_intel_subgroups +#pragma OPENCL EXTENSION cl_intel_subgroups : enable +#else +#pragma OPENCL EXTENSION cl_khr_subgroups : enable +#endif + +#ifdef cl_intel_required_subgroup_size +#pragma OPENCL EXTENSION cl_intel_required_subgroup_size : enable +#define INTEL_GPU 1 +#define REQD_SUBGROUP_SIZE_16 __attribute__((intel_reqd_sub_group_size(16))) +#define REQD_SUBGROUP_SIZE_32 __attribute__((intel_reqd_sub_group_size(32))) +#elif defined(cl_qcom_reqd_sub_group_size) +#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable +#define ADRENO_GPU 1 +#define REQD_SUBGROUP_SIZE_64 __attribute__((qcom_reqd_sub_group_size("half"))) +#define REQD_SUBGROUP_SIZE_128 __attribute__((qcom_reqd_sub_group_size("full"))) +#endif + +#define QK8_0 32 +typedef struct { + half d; // delta + char qs[QK8_0]; // quants +} block_q8_0; + +#define NB_Q8_0 8 + +#ifdef INTEL_GPU +#define N_R0_Q8_0 4 // number of rows each subgroup works on +#define N_SG_Q8_0 2 // number of subgroups in a work group +#define N_SIMDWIDTH 16 // subgroup size +#elif defined (ADRENO_GPU) +#define N_R0_Q8_0 4 +#define N_SG_Q8_0 2 +#define N_SIMDWIDTH 64 +#endif + +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_16 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_mul_mv_q8_0_f32_flat( + global char * src0_q, + global half * src0_d, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne12, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + int ne1, + int r2, + int r3 +) { + src1 = (global char*)((global char*)src1 + offset1); + dst = (global char*)((global char*)dst + offsetd); + + int nb = ne00/QK8_0; + + int r0 = get_group_id(0); + int r1 = get_group_id(1); + int im = get_group_id(2); + + int first_row = (r0*N_SG_Q8_0 + get_sub_group_id()) * N_R0_Q8_0; + + uint i12 = im%ne12; + uint i13 = im/ne12; + + ulong offset_src1 = r1*nb11 + i12*nb12 + i13*nb13; + global float * y = (global float *) (src1 + offset_src1); + + // pointers to src0 rows + uint offset_src0_base = first_row*nb01 + (i12/r2)*nb02 + (i13/r3)*nb03; + + global char * ax0, * ax1, * ax2, * ax3; + global half * ad0, * ad1, * ad2, * ad3; + uint offset_src0; + + offset_src0 = offset_src0_base + 0*nb01; + offset_src0 = offset_src0/34; + ax0 = (global char *) ((global char *) src0_q + offset_src0*sizeof(char)*QK8_0); + ad0 = (global half *) ((global char *) src0_d + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 1*nb01; + offset_src0 = offset_src0/34; + ax1 = (global char *) ((global char *) src0_q + offset_src0*sizeof(char)*QK8_0); + ad1 = (global half *) ((global char *) src0_d + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 2*nb01; + offset_src0 = offset_src0/34; + ax2 = (global char *) ((global char *) src0_q + offset_src0*sizeof(char)*QK8_0); + ad2 = (global half *) ((global char *) src0_d + offset_src0*sizeof(half)); + + offset_src0 = offset_src0_base + 3*nb01; + offset_src0 = offset_src0/34; + ax3 = (global char *) ((global char *) src0_q + offset_src0*sizeof(char)*QK8_0); + ad3 = (global half *) ((global char *) src0_d + offset_src0*sizeof(half)); + + const short ix = get_sub_group_local_id()/4; + const short il = get_sub_group_local_id()%4; + + global float * yb = y + ix*QK8_0 + il*NB_Q8_0; + + float8 yl; + float8 qv; + float4 sumf = 0.f; + float sumq = 0.f; + global char * qs; + + // each thread handles NB_Q8_0 quants at a time + for (int ib = ix; ib < nb; ib += N_SIMDWIDTH/4) { + yl = vload8(0, yb); + + qs = ax0 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s0 += sumq*ad0[ib]; + + qs = ax1 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s1 += sumq*ad1[ib]; + + qs = ax2 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s2 += sumq*ad2[ib]; + + qs = ax3 + ib*sizeof(char)*QK8_0 + il*NB_Q8_0; + qv = convert_float8(vload8(0, qs)); + sumq = 0; + sumq += qv.s0*yl.s0; + sumq += qv.s1*yl.s1; + sumq += qv.s2*yl.s2; + sumq += qv.s3*yl.s3; + sumq += qv.s4*yl.s4; + sumq += qv.s5*yl.s5; + sumq += qv.s6*yl.s6; + sumq += qv.s7*yl.s7; + sumf.s3 += sumq*ad3[ib]; + + yb += N_SIMDWIDTH*NB_Q8_0; + } + + global float * dst_f32 = (global float *) dst + (ulong)im*ne0*ne1 + (ulong)r1*ne0; + + float4 tot = (float4)( + sub_group_reduce_add(sumf.s0), + sub_group_reduce_add(sumf.s1), + sub_group_reduce_add(sumf.s2), + sub_group_reduce_add(sumf.s3) + ); + + if (get_sub_group_local_id() == 0) { + if (first_row + 0 < ne01) { + dst_f32[first_row + 0] = tot.s0; + } + if (first_row + 1 < ne01) { + dst_f32[first_row + 1] = tot.s1; + } + if (first_row + 2 < ne01) { + dst_f32[first_row + 2] = tot.s2; + } + if (first_row + 3 < ne01) { + dst_f32[first_row + 3] = tot.s3; + } + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/norm.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/norm.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/norm.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/norm.cl 2025-09-30 07:36:33.000000000 +0000 @@ -79,3 +79,83 @@ kernel void kernel_norm( y[i00] = y[i00] * scale; } } + +//------------------------------------------------------------------------------ +// norm_mul_add +//------------------------------------------------------------------------------ +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_32 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_norm_mul_add( + global char * src0_ptr, ulong src0_offset, + global char * src1_ptr, ulong src1_offset, + global char * src2_ptr, ulong src2_offset, + global char * dst_ptr, ulong dst_offset, + int ne00, int ne01, int ne02, int ne03, + ulong nb01, ulong nb02, ulong nb03, + int ne10, int ne11, int ne12, int ne13, + ulong nb11, ulong nb12, ulong nb13, + int ne20, int ne21, int ne22, int ne23, + ulong nb21, ulong nb22, ulong nb23, + ulong nbd1, ulong nbd2, ulong nbd3, + float eps, + local float2 * sums +) { + const int i03 = get_group_id(2); + const int i02 = get_group_id(1); + const int i01 = get_group_id(0); + + global float4 * x = (global float4 *)(src0_ptr + src0_offset + i01*nb01 + i02*nb02 + i03*nb03); + global float4 * w = (global float4 *)(src1_ptr + src1_offset + (i01%ne11)*nb11 + (i02%ne12)*nb12 + (i03%ne13)*nb13); + global float4 * b = (global float4 *)(src2_ptr + src2_offset + (i01%ne21)*nb21 + (i02%ne22)*nb22 + (i03%ne23)*nb23); + global float4 * y = (global float4 *)(dst_ptr + dst_offset + i01*nbd1 + i02*nbd2 + i03*nbd3); + + float p_sum = 0.0f; + float p_sum_sq = 0.0f; + + const int n_chunks = ne00 / 4; + for (int i00 = get_local_id(0); i00 < n_chunks; i00 += get_local_size(0)) { + float4 val = x[i00]; + p_sum += val.x + val.y + val.z + val.w; + p_sum_sq += dot(val, val); + } + + p_sum = sub_group_reduce_add(p_sum); + p_sum_sq = sub_group_reduce_add(p_sum_sq); + + if (get_sub_group_local_id() == 0) { + sums[get_sub_group_id()] = (float2)(p_sum, p_sum_sq); + } + barrier(CLK_LOCAL_MEM_FENCE); + + if (get_local_id(0) == 0) { + float sum = 0.0f; + float sum_sq = 0.0f; + for (uint i = 0; i < get_num_sub_groups(); ++i) { + float2 s = sums[i]; + sum += s.x; + sum_sq += s.y; + } + + const float inv_ne00 = 1.0f / (float)ne00; + const float mean = sum * inv_ne00; + const float variance = mad(-mean, mean, sum_sq * inv_ne00); + + sums[0] = (float2)(mean, rsqrt(variance + eps)); + } + barrier(CLK_LOCAL_MEM_FENCE); + + const float2 mean_scale = sums[0]; + const float mean = mean_scale.x; + const float scale = mean_scale.y; + const float neg_mean_scale = -mean * scale; + + for (int i00 = get_local_id(0); i00 < n_chunks; i00 += get_local_size(0)) { + const int w_idx = ne10 > 1 ? i00 : 0; + const int b_idx = ne20 > 1 ? i00 : 0; + const float4 norm_x = mad(x[i00], (float4)scale, (float4)neg_mean_scale); + y[i00] = mad(norm_x, w[w_idx], b[b_idx]); + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/rms_norm.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/rms_norm.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/rms_norm.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/rms_norm.cl 2025-09-30 07:36:33.000000000 +0000 @@ -94,3 +94,82 @@ kernel void kernel_rms_norm( } } } + +//------------------------------------------------------------------------------ +// rms_norm_mul +//------------------------------------------------------------------------------ +#ifdef INTEL_GPU +REQD_SUBGROUP_SIZE_32 +#elif defined (ADRENO_GPU) +REQD_SUBGROUP_SIZE_64 +#endif +kernel void kernel_rms_norm_mul( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne00, + int ne01, + int ne02, + int ne03, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb11, + ulong nb12, + ulong nb13, + ulong nb1, + ulong nb2, + ulong nb3, + float eps, + local float * sum +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + global float4 * x = (global float4 *) (src0 + i03*nb03 + i02*nb02 + i01*nb01); + global float4 * f = (global float4 *) (src1 + (i03%ne13)*nb13 + (i02%ne12)*nb12 + (i01%ne11)*nb11); + + float sumf = 0; + + // parallel sum + for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { + sumf += dot(x[i00], x[i00]); + } + sumf = sub_group_reduce_add(sumf); + if (get_sub_group_local_id() == 0) { + sum[get_sub_group_id()] = sumf; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + for (uint i = get_local_size(0) / get_max_sub_group_size() / 2; i > 0; i /= 2) { + if (get_local_id(0) < i) { + sum[get_local_id(0)] += sum[get_local_id(0) + i]; + } + } + if (get_local_id(0) == 0) { + sum[0] /= ne00; + } + + barrier(CLK_LOCAL_MEM_FENCE); + + float mean = sum[0]; + float scale = 1.0f/sqrt(mean + eps); + + global float4 * y = (global float4 *) (dst + i03*nb3 + i02*nb2 + i01*nb1); + for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { + y[i00] = (x[i00] * scale) * f[i00%(ne10/4)]; + } +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/set_rows.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/set_rows.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/set_rows.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/set_rows.cl 2025-09-30 07:36:33.000000000 +0000 @@ -1,6 +1,6 @@ #pragma OPENCL EXTENSION cl_khr_fp16 : enable -kernel void kernel_set_rows_f32( +kernel void kernel_set_rows_f32_i64( global char * src0, ulong offset0, global char * src1, @@ -47,7 +47,7 @@ kernel void kernel_set_rows_f32( } } -kernel void kernel_set_rows_f16( +kernel void kernel_set_rows_f16_i64( global char * src0, ulong offset0, global char * src1, @@ -88,6 +88,100 @@ kernel void kernel_set_rows_f16( global half * dst_row = (global half *) (dst + i1*nb1 + i02*nb2 + i03*nb3); global float * src_row = (global float *) (src0 + i01*nb01 + i02*nb02 + i03*nb03); + + for (int ind = get_local_id(0); ind < nblk0; ind += get_local_size(0)) { + dst_row[ind] = src_row[ind]; + } +} + +kernel void kernel_set_rows_f32_i32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne11, + int ne12, + ulong nb10, + ulong nb11, + ulong nb12, + int nblk0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0)*get_local_size(1) + get_local_id(1); + + if (i01 >= ne01) { + return; + } + + int i12 = i03%ne12; + int i11 = i02%ne11; + + int i10 = i01; + int i1 = ((global int *)(src1 + i10*nb10 + i11*nb11 + i12*nb12))[0]; + + global float * dst_row = (global float *) (dst + i1*nb1 + i02*nb2 + i03*nb3); + global float * src_row = (global float *) (src0 + i01*nb01 + i02*nb02 + i03*nb03); + + for (int ind = get_local_id(0); ind < nblk0; ind += get_local_size(0)) { + dst_row[ind] = (float)src_row[ind]; + } +} + +kernel void kernel_set_rows_f16_i32( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + int ne01, + ulong nb01, + ulong nb02, + ulong nb03, + int ne11, + int ne12, + ulong nb10, + ulong nb11, + ulong nb12, + int nblk0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0)*get_local_size(1) + get_local_id(1); + + if (i01 >= ne01) { + return; + } + + int i12 = i03%ne12; + int i11 = i02%ne11; + + int i10 = i01; + int i1 = ((global int *)(src1 + i10*nb10 + i11*nb11 + i12*nb12))[0]; + + global half * dst_row = (global half *) (dst + i1*nb1 + i02*nb2 + i03*nb3); + global float * src_row = (global float *) (src0 + i01*nb01 + i02*nb02 + i03*nb03); for (int ind = get_local_id(0); ind < nblk0; ind += get_local_size(0)) { dst_row[ind] = src_row[ind]; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f16.cl 2025-09-30 07:36:33.000000000 +0000 @@ -26,6 +26,8 @@ kernel void kernel_soft_max_4_f16( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_4_f16( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_4_f16( global float4 * psrc4 = (global float4 *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global half4 * pmask = src1 != src0 ? (global half4 *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float4 * pdst4 = (global float4 *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_4_f16( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { lmax4 = fmax(lmax4, psrc4[i00]*scale + slope*(pmask ? convert_float4(pmask[i00]) : 0.0f)); } @@ -92,7 +96,11 @@ kernel void kernel_soft_max_4_f16( } float lsum = lsum4.s0 + lsum4.s1 + lsum4.s2 + lsum4.s3; - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { pdst4[i00] /= sum; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_4_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -26,6 +26,8 @@ kernel void kernel_soft_max_4( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_4( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_4( global float4 * psrc4 = (global float4 *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global float4 * pmask = src1 != src0 ? (global float4 *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float4 * pdst4 = (global float4 *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_4( } // parallel max - float4 lmax4 = -INFINITY; + float4 lmax4 = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { lmax4 = fmax(lmax4, psrc4[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -92,7 +96,11 @@ kernel void kernel_soft_max_4( } float lsum = lsum4.s0 + lsum4.s1 + lsum4.s2 + lsum4.s3; - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00/4; i00 += get_local_size(0)) { pdst4[i00] /= sum; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f16.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f16.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f16.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f16.cl 2025-09-30 07:36:33.000000000 +0000 @@ -26,6 +26,8 @@ kernel void kernel_soft_max_f16( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max_f16( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max_f16( global float * psrc0 = (global float *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global half * pmask = src1 != src0 ? (global half *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float * pdst = (global float *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max_f16( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { lmax = fmax(lmax, psrc0[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -91,7 +95,11 @@ kernel void kernel_soft_max_f16( pdst[i00] = exp_psrc0; } - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { pdst[i00] /= sum; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f32.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f32.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f32.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/softmax_f32.cl 2025-09-30 07:36:33.000000000 +0000 @@ -26,6 +26,8 @@ kernel void kernel_soft_max( ulong offset0, global char * src1, ulong offset1, + global char * src2, + ulong offset2, global char * dst, ulong offsetd, int ne00, @@ -48,6 +50,7 @@ kernel void kernel_soft_max( ) { src0 = src0 + offset0; src1 = src1 + offset1; + src2 = src2 + offset2; dst = dst + offsetd; int i03 = get_group_id(2); @@ -60,6 +63,7 @@ kernel void kernel_soft_max( global float * psrc0 = (global float *)(src0 + i01*nb01 + i02*nb02 + i03*nb03); global float * pmask = src1 != src0 ? (global float *)(src1 + i11*nb11 + i12*nb12 + i13*nb13) : 0; + global float * psrc2 = src2 != src0 ? (global float *)(src2) : 0; global float * pdst = (global float *)(dst + i01*nb1 + i02*nb2 + i03*nb3); float slope = 1.0f; @@ -75,7 +79,7 @@ kernel void kernel_soft_max( } // parallel max - float lmax = -INFINITY; + float lmax = psrc2 ? psrc2[i02] : -INFINITY; for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { lmax = fmax(lmax, psrc0[i00]*scale + (pmask ? slope*pmask[i00] : 0.0f)); } @@ -91,7 +95,11 @@ kernel void kernel_soft_max( pdst[i00] = exp_psrc0; } - const float sum = sub_group_reduce_add(lsum); + float sum = sub_group_reduce_add(lsum); + + if (psrc2) { + sum += exp(psrc2[i02] - max); + } for (int i00 = get_local_id(0); i00 < ne00; i00 += get_local_size(0)) { pdst[i00] /= sum; diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/sub.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/sub.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/sub.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/sub.cl 2025-09-30 07:36:33.000000000 +0000 @@ -70,3 +70,69 @@ kernel void kernel_sub_row( uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne dst[gid] = src0[gid] - src1[idx1]; } + +kernel void kernel_sub_f16( + global char * src0, + ulong offset0, + global char * src1, + ulong offset1, + global char * dst, + ulong offsetd, + ulong nb00, + ulong nb01, + ulong nb02, + ulong nb03, + int ne10, + int ne11, + int ne12, + int ne13, + ulong nb10, + ulong nb11, + ulong nb12, + ulong nb13, + int ne0, + ulong nb0, + ulong nb1, + ulong nb2, + ulong nb3 +) { + src0 = src0 + offset0; + src1 = src1 + offset1; + dst = dst + offsetd; + + int i03 = get_group_id(2); + int i02 = get_group_id(1); + int i01 = get_group_id(0); + + int i13 = i03 % ne13; + int i12 = i02 % ne12; + int i11 = i01 % ne11; + + global char * src0_ptr = src0 + i03*nb03 + i02*nb02 + i01*nb01; + global char * src1_ptr = src1 + i13*nb13 + i12*nb12 + i11*nb11; + global char * dst_ptr = dst + i03*nb3 + i02*nb2 + i01*nb1; + + for (int i0 = get_local_id(0); i0 < ne0; i0 += get_local_size(0)) { + const int i10 = i0 % ne10; + *((global half *)(dst_ptr + i0*nb0)) = *((global half *)(src0_ptr + i0*nb00)) - *((global half *)(src1_ptr + i10*nb10)); + } +} + +kernel void kernel_sub_row_f16( + global half4 * src0, + ulong offset0, + global half4 * src1, + ulong offset1, + global half4 * dst, + ulong offsetd, + int ne +) { + src0 = (global half4*)((global char*)src0 + offset0); + src1 = (global half4*)((global char*)src1 + offset1); + dst = (global half4*)((global char*)dst + offsetd); + + // This performs better than using %. + uint gid = get_global_id(0); + uint idx1 = gid - (gid/ne)*ne; // get_global_id(0) % ne + dst[gid] = src0[gid] - src1[idx1]; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/transpose.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/transpose.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/transpose.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/transpose.cl 2025-09-30 07:36:33.000000000 +0000 @@ -24,6 +24,26 @@ kernel void kernel_transpose_16( write_imageh(output, (i_2+3)*rows+j, (half4)(temp0.s3, temp1.s3, temp2.s3, temp3.s3)); } +// Padded kernel for irregular shape +kernel void kernel_transpose_16_4x1( + __read_only image1d_buffer_t input, + __write_only image1d_buffer_t output, + const uint rows, + const uint cols +) { + + const int i = get_global_id(0); + const int j = get_global_id(1); + const int j_2 = j << 2; + + half temp0 = read_imageh(input, (j_2 + 0) * cols + i).x; + half temp1 = read_imageh(input, (j_2 + 1) * cols + i).x; + half temp2 = read_imageh(input, (j_2 + 2) * cols + i).x; + half temp3 = read_imageh(input, (j_2 + 3) * cols + i).x; + + write_imageh(output, i * rows + j, (half4)(temp0, temp1, temp2, temp3)); +} + // 32-bit transpose, loading/storing a 4x4 tile of elements kernel void kernel_transpose_32( __read_only image1d_buffer_t input, diff -pruN 5882+dfsg-2/ggml/src/ggml-opencl/kernels/tsembd.cl 6641+dfsg-2/ggml/src/ggml-opencl/kernels/tsembd.cl --- 5882+dfsg-2/ggml/src/ggml-opencl/kernels/tsembd.cl 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opencl/kernels/tsembd.cl 2025-09-30 07:36:33.000000000 +0000 @@ -26,8 +26,8 @@ kernel void kernel_timestep_embedding( local_half_dim = logical_dim / 2; local_embed_data_ptr = (global float *)((global char *)local_dst_output_base_ptr + local_i * dst_nb1_bytes); - if (logical_dim % 2 != 0 && local_j == ((logical_dim + 1) / 2)) { - local_embed_data_ptr[logical_dim] = 0.0f; + if (logical_dim % 2 != 0 && local_j == local_half_dim) { + local_embed_data_ptr[2 * local_half_dim] = 0.0f; } if (local_j >= local_half_dim) { diff -pruN 5882+dfsg-2/ggml/src/ggml-opt.cpp 6641+dfsg-2/ggml/src/ggml-opt.cpp --- 5882+dfsg-2/ggml/src/ggml-opt.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-opt.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -64,9 +64,11 @@ struct ggml_opt_context { int32_t opt_i = 0; bool loss_per_datapoint = false; - ggml_opt_get_optimizer_params get_opt_pars = nullptr; - void * get_opt_pars_ud = nullptr; - struct ggml_tensor * adamw_params = nullptr; + ggml_opt_get_optimizer_params get_opt_pars = nullptr; + void * get_opt_pars_ud = nullptr; + struct ggml_tensor * opt_step_params = nullptr; // Stores output of get_opt_pars. + + enum ggml_opt_optimizer_type optimizer = GGML_OPT_OPTIMIZER_TYPE_ADAMW; }; struct ggml_opt_result { @@ -229,9 +231,13 @@ struct ggml_opt_optimizer_params ggml_op result.adamw.eps = 1e-8f; result.adamw.wd = 0.0f; + result.sgd.alpha = 1e-3f; + result.sgd.wd = 0.0f; + return result; } + struct ggml_opt_optimizer_params ggml_opt_get_constant_optimizer_params(void * userdata) { return *((struct ggml_opt_optimizer_params *) userdata); } @@ -249,6 +255,7 @@ struct ggml_opt_params ggml_opt_default_ /*opt_period =*/ 1, /*get_opt_pars =*/ ggml_opt_get_default_optimizer_params, /*get_opt_pars_ud =*/ nullptr, + /*optimizer =*/ GGML_OPT_OPTIMIZER_TYPE_ADAMW, }; } @@ -316,9 +323,14 @@ static void ggml_opt_build(ggml_opt_cont GGML_ASSERT(opt_ctx->ctx_compute && "no compute context set, either use static graphs or set one with ggml_opt_prepare_alloc"); GGML_ASSERT((!opt_ctx->static_graphs || opt_ctx->inputs->data) && "when using static graphs the inputs must be allocated statically"); + const enum ggml_opt_optimizer_type optimizer = opt_ctx->optimizer; + const bool accumulate = opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_GRAD && !(opt_ctx->static_graphs && opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT && opt_ctx->opt_period == 1); + const bool need_momenta = opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT && + opt_ctx->optimizer == GGML_OPT_OPTIMIZER_TYPE_ADAMW; + ggml_set_input(opt_ctx->inputs); ggml_set_output(opt_ctx->outputs); @@ -340,8 +352,7 @@ static void ggml_opt_build(ggml_opt_cont // - pred (if using static graphs) // - ncorrect (if using static graphs, 2 tensors). constexpr size_t n_loss = 1; - const size_t tensors_per_param = (accumulate ? 1 : 0) + - (opt_ctx->build_type_alloc == GGML_OPT_BUILD_TYPE_OPT ? 2 : 0); + const size_t tensors_per_param = (accumulate ? 1 : 0) + (need_momenta ? 2 : 0); const size_t tensors_const = opt_ctx->static_graphs ? 9 : 0; const size_t size_meta = (n_loss + tensors_per_param*n_param + tensors_const) * ggml_tensor_overhead(); struct ggml_init_params params = { @@ -458,7 +469,7 @@ static void ggml_opt_build(ggml_opt_cont } } - if (opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_OPT) { + if (need_momenta && opt_ctx->build_type_alloc >= GGML_OPT_BUILD_TYPE_OPT) { opt_ctx->grad_m.resize(n_nodes); opt_ctx->grad_v.resize(n_nodes); for (int i = 0; i < n_nodes; ++i) { @@ -492,23 +503,36 @@ static void ggml_opt_build(ggml_opt_cont // gb_opt == graph backward optimize, forward pass, then backward pass to calculate gradients, then optimizer step. opt_ctx->gb_opt = ggml_graph_dup(opt_ctx->ctx_compute, opt_ctx->gb_grad, /*force_grads =*/ true); - opt_ctx->adamw_params = ggml_new_tensor_1d(opt_ctx->ctx_cpu, GGML_TYPE_F32, 7); - ggml_set_input(opt_ctx->adamw_params); - ggml_set_name(opt_ctx->adamw_params, "adamw_params"); - + opt_ctx->opt_step_params = ggml_new_tensor_1d(opt_ctx->ctx_cpu, GGML_TYPE_F32, need_momenta ? 7 : 2); + ggml_tensor * adamw_params = opt_ctx->opt_step_params; + ggml_set_input(adamw_params); + const char * optimizer_name = ggml_opt_optimizer_name(opt_ctx->optimizer); + ggml_format_name(adamw_params, "%s_params", optimizer_name); for (int i = opt_ctx->gf->n_nodes-1; i >= 0; --i) { struct ggml_tensor * node = opt_ctx->gb_opt->nodes[i]; struct ggml_tensor * grad = ggml_graph_get_grad(opt_ctx->gb_opt, node); if (grad && (node->flags & GGML_TENSOR_FLAG_PARAM)) { - struct ggml_tensor * m = opt_ctx->grad_m[i]; - struct ggml_tensor * v = opt_ctx->grad_v[i]; - struct ggml_tensor * opt_step = ggml_opt_step_adamw(opt_ctx->ctx_compute, node, grad, m, v, opt_ctx->adamw_params); - - ggml_set_name(m, (std::string("AdamW m for ") + std::string(node->name)).c_str()); - ggml_set_name(v, (std::string("AdamW v for ") + std::string(node->name)).c_str()); - ggml_set_name(opt_step, (std::string("AdamW step for ") + std::string(node->name)).c_str()); - + struct ggml_tensor * m = nullptr; + struct ggml_tensor * v = nullptr; + if (need_momenta) { + m = opt_ctx->grad_m[i]; + v = opt_ctx->grad_v[i]; + ggml_format_name(m, "AdamW m for %s", node->name); + ggml_format_name(v, "AdamW v for %s", node->name); + } + struct ggml_tensor * opt_step; + switch (optimizer) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: + opt_step = ggml_opt_step_adamw(opt_ctx->ctx_compute, node, grad, m, v, adamw_params); + break; + case GGML_OPT_OPTIMIZER_TYPE_SGD: + opt_step = ggml_opt_step_sgd(opt_ctx->ctx_compute, node, grad, adamw_params); + break; + default: + GGML_ABORT("fatal error"); + } + ggml_format_name(opt_step, "%s step for %s", optimizer_name, node->name); ggml_build_forward_expand(opt_ctx->gb_opt, opt_step); } } @@ -534,6 +558,7 @@ ggml_opt_context_t ggml_opt_init(struct result->opt_period = params.opt_period; result->get_opt_pars = params.get_opt_pars; result->get_opt_pars_ud = params.get_opt_pars_ud; + result->optimizer = params.optimizer; GGML_ASSERT(result->opt_period >= 1); @@ -756,29 +781,43 @@ void ggml_opt_alloc(ggml_opt_context_t o void ggml_opt_eval(ggml_opt_context_t opt_ctx, ggml_opt_result_t result) { GGML_ASSERT(opt_ctx->eval_ready); if (opt_ctx->allocated_graph == opt_ctx->gb_opt) { - struct ggml_opt_optimizer_params opt_pars = opt_ctx->get_opt_pars(opt_ctx->get_opt_pars_ud); + const ggml_opt_optimizer_params & opt_pars = opt_ctx->get_opt_pars(opt_ctx->get_opt_pars_ud); - GGML_ASSERT(opt_pars.adamw.alpha > 0.0f); - GGML_ASSERT(opt_pars.adamw.beta1 >= 0.0f); - GGML_ASSERT(opt_pars.adamw.beta1 <= 1.0f); - GGML_ASSERT(opt_pars.adamw.beta2 >= 0.0f); - GGML_ASSERT(opt_pars.adamw.beta2 <= 1.0f); - GGML_ASSERT(opt_pars.adamw.eps >= 0.0f); - GGML_ASSERT(opt_pars.adamw.wd >= 0.0f); - GGML_ASSERT(opt_pars.adamw.wd <= 1.0f); - - // beta1, beta2 after applying warmup - const float beta1h = 1.0f/(1.0f - powf(opt_pars.adamw.beta1, opt_ctx->iter)); - const float beta2h = 1.0f/(1.0f - powf(opt_pars.adamw.beta2, opt_ctx->iter)); - - float * adamw_par_data = ggml_get_data_f32(opt_ctx->adamw_params); - adamw_par_data[0] = opt_pars.adamw.alpha; - adamw_par_data[1] = opt_pars.adamw.beta1; - adamw_par_data[2] = opt_pars.adamw.beta2; - adamw_par_data[3] = opt_pars.adamw.eps; - adamw_par_data[4] = opt_pars.adamw.wd; - adamw_par_data[5] = beta1h; - adamw_par_data[6] = beta2h; + switch (opt_ctx->optimizer) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: { + GGML_ASSERT(opt_pars.adamw.alpha > 0.0f); + GGML_ASSERT(opt_pars.adamw.beta1 >= 0.0f); + GGML_ASSERT(opt_pars.adamw.beta1 <= 1.0f); + GGML_ASSERT(opt_pars.adamw.beta2 >= 0.0f); + GGML_ASSERT(opt_pars.adamw.beta2 <= 1.0f); + GGML_ASSERT(opt_pars.adamw.eps >= 0.0f); + GGML_ASSERT(opt_pars.adamw.wd >= 0.0f); + GGML_ASSERT(opt_pars.adamw.wd <= 1.0f); + + // beta1, beta2 after applying warmup + const float beta1h = 1.0f / (1.0f - powf(opt_pars.adamw.beta1, opt_ctx->iter)); + const float beta2h = 1.0f / (1.0f - powf(opt_pars.adamw.beta2, opt_ctx->iter)); + + float * adamw_par_data = ggml_get_data_f32(opt_ctx->opt_step_params); + adamw_par_data[0] = opt_pars.adamw.alpha; + adamw_par_data[1] = opt_pars.adamw.beta1; + adamw_par_data[2] = opt_pars.adamw.beta2; + adamw_par_data[3] = opt_pars.adamw.eps; + adamw_par_data[4] = opt_pars.adamw.wd; + adamw_par_data[5] = beta1h; + adamw_par_data[6] = beta2h; + } break; + case GGML_OPT_OPTIMIZER_TYPE_SGD: { + GGML_ASSERT(opt_pars.sgd.alpha > 0.0f); + GGML_ASSERT(opt_pars.sgd.wd >= 0.0f); + GGML_ASSERT(opt_pars.sgd.wd <= 1.0f); + float * sgd = ggml_get_data_f32(opt_ctx->opt_step_params); + sgd[0] = opt_pars.sgd.alpha; + sgd[1] = opt_pars.sgd.wd; + } break; + default: + GGML_ABORT("fatal error"); + } } ggml_backend_sched_graph_compute(opt_ctx->backend_sched, opt_ctx->allocated_graph_copy); @@ -963,6 +1002,7 @@ void ggml_opt_fit( ggml_tensor * outputs, ggml_opt_dataset_t dataset, enum ggml_opt_loss_type loss_type, + enum ggml_opt_optimizer_type optimizer, ggml_opt_get_optimizer_params get_opt_pars, int64_t nepoch, int64_t nbatch_logical, @@ -993,6 +1033,7 @@ void ggml_opt_fit( params.opt_period = opt_period; params.get_opt_pars = get_opt_pars; params.get_opt_pars_ud = &epoch; + params.optimizer = optimizer; ggml_opt_context_t opt_ctx = ggml_opt_init(params); // Shuffling the data is generally useful but there is only a point if not all data is used in a single batch. @@ -1035,3 +1076,18 @@ void ggml_opt_fit( ggml_opt_result_free(result_train); ggml_opt_result_free(result_val); } + +enum ggml_opt_optimizer_type ggml_opt_context_optimizer_type(ggml_opt_context_t c) { + return c->optimizer; +} + +GGML_API const char * ggml_opt_optimizer_name(enum ggml_opt_optimizer_type o) { + switch (o) { + case GGML_OPT_OPTIMIZER_TYPE_ADAMW: + return "adamw"; + case GGML_OPT_OPTIMIZER_TYPE_SGD: + return "sgd"; + default: + return "undefined"; + }; +} diff -pruN 5882+dfsg-2/ggml/src/ggml-quants.c 6641+dfsg-2/ggml/src/ggml-quants.c --- 5882+dfsg-2/ggml/src/ggml-quants.c 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-quants.c 2025-09-30 07:36:33.000000000 +0000 @@ -21,6 +21,17 @@ #define UNUSED GGML_UNUSED +static inline int best_index_int8(int n, const int8_t * val, float x) { + if (x <= val[0]) return 0; + if (x >= val[n-1]) return n-1; + int ml = 0, mu = n-1; + while (mu-ml > 1) { + int mav = (ml+mu)/2; + if (x < val[mav]) mu = mav; else ml = mav; + } + return x - val[mu-1] < val[mu] - x ? mu-1 : mu; +} + // reference implementation for deterministic creation of model files void quantize_row_q4_0_ref(const float * GGML_RESTRICT x, block_q4_0 * GGML_RESTRICT y, int64_t k) { static const int qk = QK4_0; @@ -246,6 +257,53 @@ void quantize_row_q8_1_ref(const float * } } +static inline int best_index_mxfp4(float x, float e) { + int best_index = 0; + float best_err = fabsf(kvalues_mxfp4[0]*e - x); + for (int i = 1; i < 16; i++) { + float err = fabsf(kvalues_mxfp4[i]*e - x); + if (err < best_err) { + best_index = i; + best_err = err; + } + } + return best_index; +} + +void quantize_row_mxfp4_ref(const float * GGML_RESTRICT x, block_mxfp4 * GGML_RESTRICT y, int64_t k) { + static const int qk = QK_MXFP4; + + assert(k % qk == 0); + + const int nb = k / qk; + + for (int i = 0; i < nb; i++) { + float amax = 0.0f; // absolute max + + for (int j = 0; j < qk; j++) { + const float v = x[i*qk + j]; + + if (amax < fabsf(v)) { + amax = fabsf(v); + } + } + + const uint8_t e = amax > 0.0f ? (uint8_t) (floorf(log2f(amax)) - 2 + 127) : 0; + + const float d = GGML_E8M0_TO_FP32_HALF(e); + + y[i].e = e; + + for (int j = 0; j < qk/2; ++j) { + const uint8_t x0 = best_index_mxfp4(x[i*qk + 0 + j], d); + const uint8_t x1 = best_index_mxfp4(x[i*qk + qk/2 + j], d); + + y[i].qs[j] = x0; + y[i].qs[j] |= x1 << 4; + } + } +} + void dequantize_row_q4_0(const block_q4_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { static const int qk = QK4_0; @@ -356,6 +414,26 @@ void dequantize_row_q8_0(const block_q8_ } } +void dequantize_row_mxfp4(const block_mxfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k) { + static const int qk = QK_MXFP4; + + assert(k % qk == 0); + + const int nb = k / qk; + + for (int i = 0; i < nb; i++) { + const float d = GGML_E8M0_TO_FP32_HALF(x[i].e); + + for (int j = 0; j < qk/2; ++j) { + const int8_t x0 = kvalues_mxfp4[x[i].qs[j] & 0x0F]; + const int8_t x1 = kvalues_mxfp4[x[i].qs[j] >> 4]; + + y[i*qk + j + 0 ] = x0*d; + y[i*qk + j + qk/2] = x1*d; + } + } +} + // // 2-6 bit quantization in super-blocks // @@ -488,7 +566,7 @@ static float make_q3_quants(int n, int n for (int i = 0; i < n; ++i) { L[i] += nmax; } - return sumlx / suml2; + return suml2 > 0.0f ? sumlx / suml2 : 0.0f; } for (int i = 0; i < n; ++i) { int l = nearest_int(iscale * x[i]); @@ -823,7 +901,7 @@ static float make_qp_quants(int n, int n for (int i = 0; i < n; ++i) { max = MAX(max, x[i]); } - if (!max) { // all zero + if (max < GROUP_MAX_EPS) { // all zero for (int i = 0; i < n; ++i) { L[i] = 0; } return 0.f; } @@ -888,7 +966,7 @@ static float make_qp_quants(int n, int n break; } } - return sumlx/suml2; + return suml2 > 0.0f ? sumlx / suml2 : 0.0f; } static void quantize_row_q2_K_impl(const float * GGML_RESTRICT x, block_q2_K * GGML_RESTRICT y, int k, const float * GGML_RESTRICT quant_weights) { @@ -2014,6 +2092,12 @@ size_t quantize_q8_0(const float * GGML_ return nrow * row_size; } +size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrow, int64_t n_per_row, const float * quant_weights) { + GGML_UNUSED(quant_weights); + quantize_row_mxfp4_ref(src, dst, (int64_t)nrow*n_per_row); + return nrow * ggml_row_size(GGML_TYPE_MXFP4, n_per_row); +} + // ====================== Ternary (de)-quantization (BitNet b1.58 and TriLMs) void quantize_row_tq1_0_ref(const float * GGML_RESTRICT x, block_tq1_0 * GGML_RESTRICT y, int64_t k) { @@ -3637,6 +3721,7 @@ static void quantize_row_iq3_xxs_impl(in } float best = 0; float scale = max/(2*kMaxQ-1); + for (int k = 0; k < 8; ++k) is_on_grid[k] = true; for (int is = -15; is <= 15; ++is) { float id = (2*kMaxQ-1+is*0.2f)/max; float this_scale = 1/id; @@ -4182,7 +4267,7 @@ static void quantize_row_iq1_s_impl(cons sumw[j+1] = sumw[j] + weight[i]; } } - float best_score = -FLT_MIN, scale = max; + float best_score = -FLT_MAX, scale = max; int besti1 = -1, besti2 = -1, best_shift = 0; for (int i1 = 0; i1 <= block_size; ++i1) { for (int i2 = i1; i2 <= block_size; ++i2) { @@ -4358,7 +4443,7 @@ static void quantize_row_iq1_m_impl(cons idx[2*j] = j; } qsort(pairs, block_size, 2*sizeof(float), iq1_sort_helper); - float best_score = -FLT_MIN, scale = max; + float best_score = -FLT_MAX, scale = max; int besti1 = -1, besti2 = -1, best_k = -1; // 0: +, + // 1: +, - @@ -4551,17 +4636,6 @@ size_t quantize_iq1_m(const float * GGML // ============================ 4-bit non-linear quants -static inline int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) return 0; - if (x >= val[n-1]) return n-1; - int ml = 0, mu = n-1; - while (mu-ml > 1) { - int mav = (ml+mu)/2; - if (x < val[mav]) mu = mav; else ml = mav; - } - return x - val[mu-1] < val[mu] - x ? mu-1 : mu; -} - static void quantize_row_iq4_nl_impl(const int super_block_size, const int block_size, const float * GGML_RESTRICT x, ggml_fp16_t * dh, uint8_t * q4, uint16_t * scales_h, uint8_t * scales_l, float * scales, float * weight, uint8_t * L, @@ -4961,6 +5035,15 @@ static bool validate_fp16(ggml_fp16_t f, return true; } +static bool validate_e_e8m0(uint8_t e, size_t i) { + if (e == 0xff) { + fprintf(stderr, "ggml_validate_row_data: found invalid e value %d at block %zu\n", e, i); + return false; + } + + return true; +} + #define VALIDATE_ROW_DATA_D_F16_IMPL(type, data, nb) \ const type * q = (const type *) (data); \ for (size_t i = 0; i < (nb); ++i) { \ @@ -4977,6 +5060,14 @@ static bool validate_fp16(ggml_fp16_t f, } \ } +#define VALIDATE_ROW_DATA_E_E8M0_IMPL(type, data, nb) \ + const type * q = (const type *) (data); \ + for (size_t i = 0; i < (nb); ++i) { \ + if (!validate_e_e8m0(q[i].e, i)) { \ + return false; \ + } \ + } + #define VALIDATE_ROW_DATA_DVEC_F16_IMPL(type, data, nb, nr) \ const type * q = (const type *) (data); \ for (size_t i = 0; i < (nb); ++i) { \ @@ -5130,6 +5221,10 @@ bool ggml_validate_row_data(enum ggml_ty { VALIDATE_ROW_DATA_D_F16_IMPL(block_q8_0, data, nb); } break; + case GGML_TYPE_MXFP4: + { + VALIDATE_ROW_DATA_E_E8M0_IMPL(block_mxfp4, data, nb); + } break; case GGML_TYPE_Q2_K: { VALIDATE_ROW_DATA_DM_F16_IMPL(block_q2_K, data, nb, d, dmin); diff -pruN 5882+dfsg-2/ggml/src/ggml-quants.h 6641+dfsg-2/ggml/src/ggml-quants.h --- 5882+dfsg-2/ggml/src/ggml-quants.h 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-quants.h 2025-09-30 07:36:33.000000000 +0000 @@ -21,6 +21,8 @@ GGML_API void quantize_row_q5_1_ref(cons GGML_API void quantize_row_q8_0_ref(const float * GGML_RESTRICT x, block_q8_0 * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q8_1_ref(const float * GGML_RESTRICT x, block_q8_1 * GGML_RESTRICT y, int64_t k); +GGML_API void quantize_row_mxfp4_ref(const float * GGML_RESTRICT x, block_mxfp4 * GGML_RESTRICT y, int64_t k); + GGML_API void quantize_row_q2_K_ref(const float * GGML_RESTRICT x, block_q2_K * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q3_K_ref(const float * GGML_RESTRICT x, block_q3_K * GGML_RESTRICT y, int64_t k); GGML_API void quantize_row_q4_K_ref(const float * GGML_RESTRICT x, block_q4_K * GGML_RESTRICT y, int64_t k); @@ -45,6 +47,8 @@ GGML_API void dequantize_row_q5_1(const GGML_API void dequantize_row_q8_0(const block_q8_0 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); //GGML_API void dequantize_row_q8_1(const block_q8_1 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); +GGML_API void dequantize_row_mxfp4(const block_mxfp4 * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); + GGML_API void dequantize_row_q2_K(const block_q2_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void dequantize_row_q3_K(const block_q3_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); GGML_API void dequantize_row_q4_K(const block_q4_K * GGML_RESTRICT x, float * GGML_RESTRICT y, int64_t k); @@ -90,6 +94,8 @@ GGML_API size_t quantize_q5_0(const floa GGML_API size_t quantize_q5_1(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); GGML_API size_t quantize_q8_0(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); +GGML_API size_t quantize_mxfp4(const float * GGML_RESTRICT src, void * GGML_RESTRICT dst, int64_t nrows, int64_t n_per_row, const float * imatrix); + GGML_API void iq2xs_init_impl(enum ggml_type type); GGML_API void iq2xs_free_impl(enum ggml_type type); GGML_API void iq3xs_init_impl(int grid_size); diff -pruN 5882+dfsg-2/ggml/src/ggml-rpc/ggml-rpc.cpp 6641+dfsg-2/ggml/src/ggml-rpc/ggml-rpc.cpp --- 5882+dfsg-2/ggml/src/ggml-rpc/ggml-rpc.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-rpc/ggml-rpc.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -29,9 +29,18 @@ #include #include #include +#include + +static const char * RPC_DEBUG = std::getenv("GGML_RPC_DEBUG"); + +#define LOG_DBG(...) \ + do { if (RPC_DEBUG) GGML_LOG_DEBUG(__VA_ARGS__); } while (0) + namespace fs = std::filesystem; +static constexpr size_t MAX_CHUNK_SIZE = 1024ull * 1024ull * 1024ull; // 1 GiB + #ifdef _WIN32 typedef SOCKET sockfd_t; using ssize_t = __int64; @@ -44,7 +53,7 @@ struct socket_t { sockfd_t fd; socket_t(sockfd_t fd) : fd(fd) {} ~socket_t() { - GGML_PRINT_DEBUG("[%s] closing socket %d\n", __func__, this->fd); + LOG_DBG("[%s] closing socket %d\n", __func__, this->fd); #ifdef _WIN32 closesocket(this->fd); #else @@ -262,14 +271,14 @@ static std::shared_ptr socket_ return nullptr; } if (!set_no_delay(sockfd)) { - fprintf(stderr, "Failed to set TCP_NODELAY\n"); + GGML_LOG_ERROR("Failed to set TCP_NODELAY\n"); return nullptr; } addr.sin_family = AF_INET; addr.sin_port = htons(port); struct hostent * server = gethostbyname(host); if (server == NULL) { - fprintf(stderr, "Cannot resolve host '%s'\n", host); + GGML_LOG_ERROR("Cannot resolve host '%s'\n", host); return nullptr; } memcpy(&addr.sin_addr.s_addr, server->h_addr, server->h_length); @@ -286,7 +295,7 @@ static std::shared_ptr socket_ return nullptr; } if (!set_no_delay(client_socket_fd)) { - fprintf(stderr, "Failed to set TCP_NODELAY\n"); + GGML_LOG_ERROR("Failed to set TCP_NODELAY\n"); return nullptr; } return client_socket; @@ -299,11 +308,11 @@ static std::shared_ptr create_ return nullptr; } if (!set_reuse_addr(sockfd)) { - fprintf(stderr, "Failed to set SO_REUSEADDR\n"); + GGML_LOG_ERROR("Failed to set SO_REUSEADDR\n"); return nullptr; } if (inet_addr(host) == INADDR_NONE) { - fprintf(stderr, "Invalid host address: %s\n", host); + GGML_LOG_ERROR("Invalid host address: %s\n", host); return nullptr; } struct sockaddr_in serv_addr; @@ -323,11 +332,14 @@ static std::shared_ptr create_ static bool send_data(sockfd_t sockfd, const void * data, size_t size) { size_t bytes_sent = 0; while (bytes_sent < size) { - ssize_t n = send(sockfd, (const char *)data + bytes_sent, size - bytes_sent, 0); + size_t size_to_send = std::min(size - bytes_sent, MAX_CHUNK_SIZE); + ssize_t n = send(sockfd, (const char *)data + bytes_sent, size_to_send, 0); if (n < 0) { + GGML_LOG_ERROR("send failed (bytes_sent=%zu, size_to_send=%zu)\n", + bytes_sent, size_to_send); return false; } - bytes_sent += n; + bytes_sent += (size_t)n; } return true; } @@ -335,11 +347,18 @@ static bool send_data(sockfd_t sockfd, c static bool recv_data(sockfd_t sockfd, void * data, size_t size) { size_t bytes_recv = 0; while (bytes_recv < size) { - ssize_t n = recv(sockfd, (char *)data + bytes_recv, size - bytes_recv, 0); - if (n <= 0) { + size_t size_to_recv = std::min(size - bytes_recv, MAX_CHUNK_SIZE); + ssize_t n = recv(sockfd, (char *)data + bytes_recv, size_to_recv, 0); + if (n < 0) { + GGML_LOG_ERROR("recv failed (bytes_recv=%zu, size_to_recv=%zu)\n", + bytes_recv, size_to_recv); + return false; + } + if (n == 0) { + LOG_DBG("recv returned 0 (peer closed?)\n"); return false; } - bytes_recv += n; + bytes_recv += (size_t)n; } return true; } @@ -370,7 +389,7 @@ static bool recv_msg(sockfd_t sockfd, st try { input.resize(size); } catch (const std::bad_alloc & e) { - fprintf(stderr, "Failed to allocate input buffer of size %" PRIu64 "\n", size); + GGML_LOG_ERROR("Failed to allocate input buffer of size %" PRIu64 "\n", size); return false; } return recv_data(sockfd, input.data(), size); @@ -430,11 +449,11 @@ static bool check_server_version(const s bool status = send_rpc_cmd(sock, RPC_CMD_HELLO, nullptr, 0, &response, sizeof(response)); RPC_STATUS_ASSERT(status); if (response.major != RPC_PROTO_MAJOR_VERSION || response.minor > RPC_PROTO_MINOR_VERSION) { - fprintf(stderr, "RPC server version mismatch: %d.%d.%d\n", response.major, response.minor, response.patch); + GGML_LOG_ERROR("RPC server version mismatch: %d.%d.%d\n", response.major, response.minor, response.patch); return false; } if (response.minor != RPC_PROTO_MINOR_VERSION || response.patch != RPC_PROTO_PATCH_VERSION) { - fprintf(stderr, "WARNING: RPC server version mismatch: %d.%d.%d\n", response.major, response.minor, response.patch); + GGML_LOG_INFO("WARNING: RPC server version mismatch: %d.%d.%d\n", response.major, response.minor, response.patch); } return true; } @@ -475,7 +494,7 @@ static std::shared_ptr get_soc if (!check_server_version(sock)) { return nullptr; } - GGML_PRINT_DEBUG("[%s] connected to %s, sockfd=%d\n", __func__, endpoint.c_str(), sock->fd); + LOG_DBG("[%s] connected to %s, sockfd=%d\n", __func__, endpoint.c_str(), sock->fd); sockets[endpoint] = sock; return sock; } @@ -782,6 +801,7 @@ static ggml_backend_i ggml_backend_rpc_i /* .graph_compute = */ ggml_backend_rpc_graph_compute, /* .event_record = */ NULL, /* .event_wait = */ NULL, + /* .graph_optimize = */ NULL, }; ggml_backend_buffer_type_t ggml_backend_rpc_buffer_type(const char * endpoint) { @@ -795,7 +815,7 @@ ggml_backend_buffer_type_t ggml_backend_ } auto sock = get_socket(endpoint); if (sock == nullptr) { - fprintf(stderr, "Failed to connect to %s\n", endpoint); + GGML_LOG_ERROR("Failed to connect to %s\n", endpoint); return nullptr; } size_t alignment = get_alignment(sock); @@ -823,10 +843,10 @@ ggml_backend_t ggml_backend_rpc_init(con }; ggml_backend_t backend = new ggml_backend { - /* .guid = */ ggml_backend_rpc_guid(), - /* .interface = */ ggml_backend_rpc_interface, - /* .device = */ ggml_backend_rpc_add_device(endpoint), - /* .context = */ ctx + /* .guid = */ ggml_backend_rpc_guid(), + /* .iface = */ ggml_backend_rpc_interface, + /* .device = */ ggml_backend_rpc_add_device(endpoint), + /* .context = */ ctx }; return backend; } @@ -895,7 +915,7 @@ void rpc_server::hello(rpc_msg_hello_rsp response.major = RPC_PROTO_MAJOR_VERSION; response.minor = RPC_PROTO_MINOR_VERSION; response.patch = RPC_PROTO_PATCH_VERSION; - GGML_PRINT_DEBUG("[%s] version: %d.%d.%d\n", __func__, response.major, response.minor, response.patch); + LOG_DBG("[%s] version: %d.%d.%d\n", __func__, response.major, response.minor, response.patch); } bool rpc_server::get_alloc_size(const rpc_msg_get_alloc_size_req & request, rpc_msg_get_alloc_size_rsp & response) { @@ -915,7 +935,7 @@ bool rpc_server::get_alloc_size(const rp GGML_LOG_ERROR("Null tensor pointer passed to server get_alloc_size function.\n"); return false; } - + LOG_DBG("[%s] buffer: %p, data: %p\n", __func__, (void*)tensor->buffer, tensor->data); if (tensor->buffer == nullptr) { //No buffer allocated. buft = ggml_backend_get_default_buffer_type(backend); @@ -923,7 +943,7 @@ bool rpc_server::get_alloc_size(const rp buft = tensor->buffer->buft; } - response.alloc_size = ggml_backend_buft_get_alloc_size(buft,tensor); + response.alloc_size = ggml_backend_buft_get_alloc_size(buft, tensor); return true; } @@ -936,29 +956,29 @@ void rpc_server::alloc_buffer(const rpc_ if (buffer != nullptr) { response.remote_ptr = reinterpret_cast(buffer); response.remote_size = buffer->size; - GGML_PRINT_DEBUG("[%s] size: %" PRIu64 " -> remote_ptr: %" PRIx64 ", remote_size: %" PRIu64 "\n", __func__, request.size, response.remote_ptr, response.remote_size); + LOG_DBG("[%s] size: %" PRIu64 " -> remote_ptr: %" PRIx64 ", remote_size: %" PRIu64 "\n", __func__, request.size, response.remote_ptr, response.remote_size); buffers.insert(buffer); } else { - GGML_LOG_ERROR("[%s] size: %" PRIu64 " -> failed\n", __func__, request.size); + LOG_DBG("[%s] size: %" PRIu64 " -> failed\n", __func__, request.size); } } void rpc_server::get_alignment(rpc_msg_get_alignment_rsp & response) { ggml_backend_buffer_type_t buft = ggml_backend_get_default_buffer_type(backend); size_t alignment = ggml_backend_buft_get_alignment(buft); - GGML_PRINT_DEBUG("[%s] alignment: %lu\n", __func__, alignment); + LOG_DBG("[%s] alignment: %lu\n", __func__, alignment); response.alignment = alignment; } void rpc_server::get_max_size(rpc_msg_get_max_size_rsp & response) { ggml_backend_buffer_type_t buft = ggml_backend_get_default_buffer_type(backend); size_t max_size = ggml_backend_buft_get_max_size(buft); - GGML_PRINT_DEBUG("[%s] max_size: %lu\n", __func__, max_size); + LOG_DBG("[%s] max_size: %lu\n", __func__, max_size); response.max_size = max_size; } bool rpc_server::buffer_get_base(const rpc_msg_buffer_get_base_req & request, rpc_msg_buffer_get_base_rsp & response) { - GGML_PRINT_DEBUG("[%s] remote_ptr: %" PRIx64 "\n", __func__, request.remote_ptr); + LOG_DBG("[%s] remote_ptr: %" PRIx64 "\n", __func__, request.remote_ptr); ggml_backend_buffer_t buffer = reinterpret_cast(request.remote_ptr); if (buffers.find(buffer) == buffers.end()) { GGML_LOG_ERROR("[%s] buffer not found\n", __func__); @@ -970,7 +990,7 @@ bool rpc_server::buffer_get_base(const r } bool rpc_server::free_buffer(const rpc_msg_free_buffer_req & request) { - GGML_PRINT_DEBUG("[%s] remote_ptr: %" PRIx64 "\n", __func__, request.remote_ptr); + LOG_DBG("[%s] remote_ptr: %" PRIx64 "\n", __func__, request.remote_ptr); ggml_backend_buffer_t buffer = reinterpret_cast(request.remote_ptr); if (buffers.find(buffer) == buffers.end()) { GGML_LOG_ERROR("[%s] buffer not found\n", __func__); @@ -982,7 +1002,7 @@ bool rpc_server::free_buffer(const rpc_m } bool rpc_server::buffer_clear(const rpc_msg_buffer_clear_req & request) { - GGML_PRINT_DEBUG("[%s] remote_ptr: %" PRIx64 ", value: %u\n", __func__, request.remote_ptr, request.value); + LOG_DBG("[%s] remote_ptr: %" PRIx64 ", value: %u\n", __func__, request.remote_ptr, request.value); ggml_backend_buffer_t buffer = reinterpret_cast(request.remote_ptr); if (buffers.find(buffer) == buffers.end()) { GGML_LOG_ERROR("[%s] buffer not found\n", __func__); @@ -1055,11 +1075,11 @@ bool rpc_server::set_tensor(const std::v GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, in_tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } - GGML_PRINT_DEBUG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %zu\n", __func__, (void*)tensor->buffer, tensor->data, offset, size); + LOG_DBG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %zu\n", __func__, (void*)tensor->buffer, tensor->data, offset, size); // sanitize tensor->data { @@ -1082,7 +1102,7 @@ bool rpc_server::set_tensor(const std::v fs::path cache_file = fs::path(cache_dir) / hash_str; std::ofstream ofs(cache_file, std::ios::binary); ofs.write((const char *)data, size); - printf("[%s] saved to '%s'\n", __func__, cache_file.c_str()); + GGML_LOG_INFO("[%s] saved to '%s'\n", __func__, cache_file.c_str()); } ggml_backend_tensor_set(tensor, data, offset, size); return true; @@ -1124,12 +1144,12 @@ bool rpc_server::set_tensor_hash(const r GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, &request.tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } - GGML_PRINT_DEBUG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %zu, hash: %" PRIx64 "\n", - __func__, (void*)tensor->buffer, tensor->data, request.offset, size, request.hash); + LOG_DBG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %zu, hash: %" PRIx64 "\n", + __func__, (void*)tensor->buffer, tensor->data, request.offset, size, request.hash); // sanitize tensor->data { @@ -1163,7 +1183,7 @@ bool rpc_server::init_tensor(const rpc_m GGML_LOG_ERROR("Null tensor pointer passed to server init_tensor function.\n"); return false; } - + LOG_DBG("[%s] buffer: %p, data: %p\n", __func__, (void*)tensor->buffer, tensor->data); // Call the backend's buffer_init_tensor function ggml_backend_buffer_t buffer = tensor->buffer; if (buffer && buffer->iface.init_tensor) { @@ -1192,11 +1212,11 @@ bool rpc_server::get_tensor(const rpc_ms GGML_ASSERT(ctx_ptr != nullptr); ggml_context * ctx = ctx_ptr.get(); ggml_tensor * tensor = deserialize_tensor(ctx, &request.tensor); - if (tensor == nullptr) { + if (tensor == nullptr || tensor->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensor\n", __func__); return false; } - GGML_PRINT_DEBUG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %" PRIu64 "\n", __func__, (void*)tensor->buffer, tensor->data, request.offset, request.size); + LOG_DBG("[%s] buffer: %p, data: %p, offset: %" PRIu64 ", size: %" PRIu64 "\n", __func__, (void*)tensor->buffer, tensor->data, request.offset, request.size); // sanitize tensor->data { @@ -1229,7 +1249,7 @@ bool rpc_server::copy_tensor(const rpc_m ggml_tensor * src = deserialize_tensor(ctx, &request.src); ggml_tensor * dst = deserialize_tensor(ctx, &request.dst); - if (src == nullptr || dst == nullptr) { + if (src == nullptr || dst == nullptr || src->buffer == nullptr || dst->buffer == nullptr) { GGML_LOG_ERROR("[%s] error deserializing tensors\n", __func__); return false; } @@ -1240,7 +1260,7 @@ bool rpc_server::copy_tensor(const rpc_m uint64_t dst_buf_sz = (uint64_t) ggml_backend_buffer_get_size(dst->buffer); if (dst_data + src_size > dst_base + dst_buf_sz) { - GGML_PRINT_DEBUG("[%s] out-of-bounds write in rpc_server::copy_tensor:\n" + GGML_LOG_ERROR("[%s] out-of-bounds write in rpc_server::copy_tensor:\n" " write range : [0x%" PRIx64 ", 0x%" PRIx64 "]\n" " buffer base: [0x%" PRIx64 ", 0x%" PRIx64 "]\n", __func__, @@ -1251,8 +1271,8 @@ bool rpc_server::copy_tensor(const rpc_m return false; } - GGML_PRINT_DEBUG("[%s] src->buffer: %p, dst->buffer: %p\n", - __func__, (void*) src->buffer, (void*) dst->buffer); + LOG_DBG("[%s] src->buffer: %p, dst->buffer: %p\n", + __func__, (void*) src->buffer, (void*) dst->buffer); response.result = ggml_backend_buffer_copy_tensor(src, dst); return true; @@ -1328,7 +1348,7 @@ bool rpc_server::graph_compute(const std return false; } const rpc_tensor * tensors = (const rpc_tensor *)(input.data() + sizeof(n_nodes) + n_nodes*sizeof(uint64_t) + sizeof(n_tensors)); - GGML_PRINT_DEBUG("[%s] n_nodes: %u, n_tensors: %u\n", __func__, n_nodes, n_tensors); + LOG_DBG("[%s] n_nodes: %u, n_tensors: %u\n", __func__, n_nodes, n_tensors); size_t buf_size = ggml_tensor_overhead()*(n_nodes + n_tensors) + ggml_graph_overhead_custom(n_nodes, false); @@ -1380,7 +1400,7 @@ static void rpc_serve_client(ggml_backen } // the first command sent by the client must be HELLO if (cmd != RPC_CMD_HELLO) { - fprintf(stderr, "Expected HELLO command, update client\n"); + GGML_LOG_ERROR("Expected HELLO command, update client\n"); return; } if (!recv_msg(sockfd, nullptr, 0)) { @@ -1397,7 +1417,7 @@ static void rpc_serve_client(ggml_backen } if (cmd >= RPC_CMD_COUNT) { // fail fast if the command is invalid - fprintf(stderr, "Unknown command: %d\n", cmd); + GGML_LOG_ERROR("Unknown command: %d\n", cmd); break; } switch (cmd) { @@ -1585,7 +1605,7 @@ static void rpc_serve_client(ggml_backen break; } default: { - fprintf(stderr, "Unknown command: %d\n", cmd); + GGML_LOG_ERROR("Unknown command: %d\n", cmd); return; } } diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/backend.hpp 6641+dfsg-2/ggml/src/ggml-sycl/backend.hpp --- 5882+dfsg-2/ggml/src/ggml-sycl/backend.hpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/backend.hpp 2025-09-30 07:36:33.000000000 +0000 @@ -28,6 +28,7 @@ #include "mmvq.hpp" #include "norm.hpp" #include "outprod.hpp" +#include "quantize.hpp" #include "quants.hpp" #include "rope.hpp" #include "set_rows.hpp" diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/binbcast.cpp 6641+dfsg-2/ggml/src/ggml-sycl/binbcast.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/binbcast.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/binbcast.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -225,9 +225,9 @@ struct bin_bcast_sycl { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, block_num) * sycl::range<3>(1, 1, block_size), + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, block_num) * + sycl::range<3>(1, 1, block_size), sycl::range<3>(1, 1, block_size)), [=](sycl::nd_item<3> item_ct1) { k_bin_bcast_unravel( @@ -246,8 +246,9 @@ struct bin_bcast_sycl { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { k_bin_bcast(src0_dd, src1_dd, dst_dd, ne0, ne1, ne2, ne3, ne10, ne11, ne12, ne13, s1, s2, s3, s01, s02, s03, s11, s12, s13, @@ -302,6 +303,10 @@ inline void ggml_sycl_op_sub(ggml_backen ggml_sycl_op_bin_bcast>(ctx, dst->src[0], dst->src[1], dst); } +inline void ggml_sycl_op_count_equal(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + ggml_sycl_op_bin_bcast>(ctx, dst->src[0], dst->src[1], dst); +} + inline void ggml_sycl_op_mul(ggml_backend_sycl_context & ctx, ggml_tensor *dst) { ggml_sycl_op_bin_bcast>(ctx, dst->src[0], dst->src[1], dst); @@ -327,6 +332,11 @@ void ggml_sycl_sub(ggml_backend_sycl_con ggml_sycl_op_sub(ctx, dst); } +void ggml_sycl_count_equal(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { + scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); + ggml_sycl_op_count_equal(ctx, dst); +} + void ggml_sycl_mul(ggml_backend_sycl_context & ctx, ggml_tensor * dst) { scope_op_debug_print scope_dbg_print(__func__, dst, /*num_src=*/2); ggml_sycl_op_mul(ctx, dst); diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/binbcast.hpp 6641+dfsg-2/ggml/src/ggml-sycl/binbcast.hpp --- 5882+dfsg-2/ggml/src/ggml-sycl/binbcast.hpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/binbcast.hpp 2025-09-30 07:36:33.000000000 +0000 @@ -16,6 +16,12 @@ static __dpct_inline__ float op_sub(cons return a - b; } +static __dpct_inline__ float op_count_equal(const float a, const float b) { + return (a == b) ? 1.0f : 0.0f; +} + +void ggml_sycl_count_equal(ggml_backend_sycl_context & ctx, ggml_tensor * dst); + static __dpct_inline__ float op_mul(const float a, const float b) { return a * b; } diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/concat.cpp 6641+dfsg-2/ggml/src/ggml-sycl/concat.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/concat.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/concat.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -89,24 +89,33 @@ static void concat_f32_sycl(const float sycl::range<3> gridDim(ne2, ne1, num_blocks); switch (dim) { case 0: - sycl_parallel_for(stream, - sycl::nd_range<3>(gridDim * sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { concat_f32_dim0(x, y, dst, ne0, ne00, item_ct1); }); - break; + stream->parallel_for( + sycl::nd_range<3>(gridDim * + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), + [=](sycl::nd_item<3> item_ct1) { + concat_f32_dim0(x, y, dst, ne0, ne00, item_ct1); + }); + break; case 1: - sycl_parallel_for(stream, - sycl::nd_range<3>(gridDim * sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { concat_f32_dim1(x, y, dst, ne0, ne01, item_ct1); }); - break; + stream->parallel_for( + sycl::nd_range<3>(gridDim * + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), + [=](sycl::nd_item<3> item_ct1) { + concat_f32_dim1(x, y, dst, ne0, ne01, item_ct1); + }); + break; // dim >=2 will be dispatched to the default path default: - sycl_parallel_for(stream, - sycl::nd_range<3>(gridDim * sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { concat_f32_dim2(x, y, dst, ne0, ne02, item_ct1); }); - break; + stream->parallel_for( + sycl::nd_range<3>(gridDim * + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CONCAT_BLOCK_SIZE)), + [=](sycl::nd_item<3> item_ct1) { + concat_f32_dim2(x, y, dst, ne0, ne02, item_ct1); + }); + break; } } @@ -120,7 +129,7 @@ static void concat_f32_sycl_non_cont( int64_t ne2, int64_t ne3, uint64_t nb0, uint64_t nb1, uint64_t nb2, uint64_t nb3, int32_t dim) { sycl::range<3> gridDim(ne3, ne2, ne1); - sycl_parallel_for(stream, sycl::nd_range<3>(gridDim, sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for(sycl::nd_range<3>(gridDim, sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { int64_t i3 = item_ct1.get_group(0); int64_t i2 = item_ct1.get_group(1); int64_t i1 = item_ct1.get_group(2); diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/conv.cpp 6641+dfsg-2/ggml/src/ggml-sycl/conv.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/conv.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/conv.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -59,10 +59,16 @@ static void conv_transpose_1d_f32_f32_sy const int num_blocks = (output_size + SYCL_CONV_TRANPOSE_1D_BLOCK_SIZE - 1) / SYCL_CONV_TRANPOSE_1D_BLOCK_SIZE; const sycl::range<3> block_dims(1, 1, SYCL_CONV_TRANPOSE_1D_BLOCK_SIZE); const sycl::range<3> block_nums(1, 1, num_blocks); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { - conv_transpose_1d_kernel(s0, output_size, src0_ne0, src0_ne1, src0_ne2, src1_ne0, dst_ne0, src0, src1, dst, - item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>( + block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + conv_transpose_1d_kernel( + s0, output_size, + src0_ne0, src0_ne1, src0_ne2, + src1_ne0, dst_ne0, + src0, src1, dst, item_ct1); + }); } void ggml_sycl_op_conv_transpose_1d(ggml_backend_sycl_context & ctx, ggml_tensor *dst) { diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/convert.cpp 6641+dfsg-2/ggml/src/ggml-sycl/convert.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/convert.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/convert.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -33,11 +33,14 @@ static void dequantize_block_sycl(const { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_DEQUANTIZE_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_DEQUANTIZE_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block(vx, y, k, item_ct1); }); + stream->parallel_for( + sycl::nd_range<3>( + sycl::range<3>(1, 1, num_blocks) * + sycl::range<3>(1, 1, SYCL_DEQUANTIZE_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_DEQUANTIZE_BLOCK_SIZE)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block(vx, y, k, item_ct1); + }); } } @@ -50,18 +53,24 @@ static void dequantize_row_q2_K_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q2_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 64), + sycl::range<3>(1, 1, 64)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q2_K(vx, y, item_ct1); + }); } #else { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q2_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q2_K(vx, y, item_ct1); + }); } #endif @@ -76,18 +85,24 @@ static void dequantize_row_q3_K_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q3_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 64), + sycl::range<3>(1, 1, 64)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q3_K(vx, y, item_ct1); + }); } #else { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q3_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q3_K(vx, y, item_ct1); + }); } #endif } @@ -101,9 +116,12 @@ static void dequantize_row_q4_0_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q4_0(vx, y, nb32, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q4_0(vx, y, nb32, item_ct1); + }); } } @@ -117,12 +135,13 @@ static void dequantize_row_q4_0_sycl_reo int constexpr WARP_K = WARP_SIZE * QK4_0; const int n_warp = (k + WARP_K - 1) / WARP_K; GGML_ASSERT(k % 2 == 0); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, n_warp) * sycl::range<3>(1, 1, WARP_SIZE), - sycl::range<3>(1, 1, WARP_SIZE)), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_block_q4_0_reorder(vx, y, k, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, n_warp) * + sycl::range<3>(1, 1, WARP_SIZE), + sycl::range<3>(1, 1, WARP_SIZE)), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]]{ + dequantize_block_q4_0_reorder(vx, y, k, item_ct1); + }); + } template @@ -134,9 +153,12 @@ static void dequantize_row_q4_1_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q4_1(vx, y, nb32, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q4_1(vx, y, nb32, item_ct1); + }); } } @@ -149,13 +171,14 @@ static void dequantize_row_q4_K_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { + stream->submit([&](sycl::handler &cgh) { sycl::local_accessor scale_local_acc(sycl::range<1>(12), cgh); - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_q4_K(vx, y, get_pointer(scale_local_acc), item_ct1); - }); + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q4_K(vx, y, get_pointer(scale_local_acc), item_ct1); + }); }); } } @@ -168,13 +191,13 @@ static void dequantize_row_q4_K_sycl_reo dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_launch(stream, [&](sycl::handler & cgh) { + stream->submit([&](sycl::handler & cgh) { sycl::local_accessor scale_local_acc(sycl::range<1>(12), cgh); - sycl_parallel_for<1>(cgh, sycl::nd_range<1>(sycl::range<1>(global_size), sycl::range<1>(local_size)), - [=](sycl::nd_item<1> item_ct1) { - dequantize_block_q4_K_reorder(vx, y, get_pointer(scale_local_acc), item_ct1, nb); - }); + cgh.parallel_for(sycl::nd_range<1>(sycl::range<1>(global_size), sycl::range<1>(local_size)), + [=](sycl::nd_item<1> item_ct1) { + dequantize_block_q4_K_reorder(vx, y, get_pointer(scale_local_acc), item_ct1, nb); + }); }); } @@ -187,18 +210,24 @@ static void dequantize_row_q5_K_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q5_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 64), + sycl::range<3>(1, 1, 64)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q5_K(vx, y, item_ct1); + }); } #else { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q5_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q5_K(vx, y, item_ct1); + }); } #endif @@ -213,18 +242,24 @@ static void dequantize_row_q6_K_sycl(con dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 64), + sycl::range<3>(1, 1, 64)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q6_K(vx, y, item_ct1); + }); } #else { dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K(vx, y, item_ct1); }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_q6_K(vx, y, item_ct1); + }); } #endif @@ -236,9 +271,9 @@ static void dequantize_row_q6_K_sycl_reo dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K_reorder(vx, y, item_ct1, nb); }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 64), sycl::range<3>(1, 1, 64)), + [=](sycl::nd_item<3> item_ct1) { dequantize_block_q6_K_reorder(vx, y, item_ct1, nb); }); } template @@ -249,10 +284,15 @@ static void dequantize_row_iq1_s_sycl(co dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq1_s(vx, y, item_ct1, iq1s_grid_gpu); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq1_s( + vx, y, item_ct1, iq1s_grid_gpu + ); + }); }); } } @@ -265,10 +305,15 @@ static void dequantize_row_iq1_m_sycl(co dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq1_m(vx, y, item_ct1, iq1s_grid_gpu); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq1_m( + vx, y, item_ct1, iq1s_grid_gpu + ); + }); }); } } @@ -281,12 +326,15 @@ static void dequantize_row_iq2_xxs_sycl( dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_iq2_xxs(vx, y, item_ct1, iq2xxs_grid, ksigns_iq2xs, kmask_iq2xs); - }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq2_xxs( + vx, y, item_ct1, iq2xxs_grid, + ksigns_iq2xs, kmask_iq2xs); + }); }); } } @@ -299,12 +347,15 @@ static void dequantize_row_iq2_xs_sycl(c dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_iq2_xs(vx, y, item_ct1, iq2xs_grid, ksigns_iq2xs, kmask_iq2xs); - }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq2_xs( + vx, y, item_ct1, iq2xs_grid, + ksigns_iq2xs, kmask_iq2xs); + }); }); } } @@ -317,10 +368,13 @@ static void dequantize_row_iq2_s_sycl(co dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq2_s(vx, y, item_ct1); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq2_s(vx, y, item_ct1); + }); }); } } @@ -334,12 +388,15 @@ static void dequantize_row_iq3_xxs_sycl( dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { - dequantize_block_iq3_xxs(vx, y, item_ct1, iq3xxs_grid, ksigns_iq2xs, kmask_iq2xs); - }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq3_xxs( + vx, y, item_ct1, iq3xxs_grid, + ksigns_iq2xs, kmask_iq2xs); + }); }); } } @@ -352,10 +409,14 @@ static void dequantize_row_iq3_s_sycl(co dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq3_s(vx, y, item_ct1, kmask_iq2xs, iq3s_grid); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq3_s( + vx, y, item_ct1, kmask_iq2xs, iq3s_grid); + }); }); } } @@ -371,11 +432,14 @@ static void dequantize_row_iq4_xs_sycl(c dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, - sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq4_xs(vx, y, item_ct1); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq4_xs(vx, y, item_ct1); + }); }); } #endif @@ -389,11 +453,14 @@ static void dequantize_row_iq4_nl_sycl(c dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_launch(stream, [&](sycl::handler & cgh) { - sycl_parallel_for( - cgh, - sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * sycl::range<3>(1, 1, 32), sycl::range<3>(1, 1, 32)), - [=](sycl::nd_item<3> item_ct1) { dequantize_block_iq4_nl(vx, y, item_ct1); }); + stream->submit([&](sycl::handler &cgh) { + cgh.parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, nb) * + sycl::range<3>(1, 1, 32), + sycl::range<3>(1, 1, 32)), + [=](sycl::nd_item<3> item_ct1) { + dequantize_block_iq4_nl(vx, y, item_ct1); + }); }); } } diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/cpy.cpp 6641+dfsg-2/ggml/src/ggml-sycl/cpy.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/cpy.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/cpy.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -1,31 +1,12 @@ #include "cpy.hpp" #include -#include #include "dequantize.hpp" #include "ggml-sycl/common.hpp" #include "ggml-sycl/presets.hpp" #include "ggml.h" -static __dpct_inline__ int best_index_int8(int n, const int8_t * val, float x) { - if (x <= val[0]) { - return 0; - } - if (x >= val[n - 1]) { - return n - 1; - } - int ml = 0, mu = n - 1; - while (mu - ml > 1) { - int mav = (ml + mu) / 2; - if (x < val[mav]) { - mu = mav; - } else { - ml = mav; - } - } - return x - val[mu - 1] < val[mu] - x ? mu - 1 : mu; -} static void cpy_1_f32_f32(const char * cxi, char * cdsti) { const float * xi = (const float *) cxi; @@ -97,28 +78,6 @@ static void cpy_f32_f16(const char * cx, cpy_1(cx + x_offset, cdst + dst_offset); } -static void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q8_0 * dsti = (block_q8_0 *) cdsti; - - float amax = 0.0f; // absolute max - - for (int j = 0; j < QK8_0; j++) { - const float v = xi[j]; - amax = sycl::fmax(amax, sycl::fabs((float) v)); - } - - const float d = amax / ((1 << 7) - 1); - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK8_0; ++j) { - const float x0 = xi[j] * id; - - dsti->qs[j] = sycl::round((float) x0); - } -} /* quantized type same copy */ template @@ -140,178 +99,7 @@ static void cpy_blck_q8_0_f32(const char } } -static void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_0 * dsti = (block_q4_0 *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_0; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - - const float d = vmax / -8; - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - for (int j = 0; j < QK4_0 / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK4_0 / 2 + j] * id; - - const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 8.5f)); - const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 8.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q4_1 * dsti = (block_q4_1 *) cdsti; - - float vmin = FLT_MAX; - float vmax = -FLT_MAX; - - for (int j = 0; j < QK4_1; ++j) { - const float v = xi[j]; - - if (v < vmin) { - vmin = v; - } - if (v > vmax) { - vmax = v; - } - } - - const float d = (vmax - vmin) / ((1 << 4) - 1); - const float id = d ? 1.0f / d : 0.0f; - - dsti->dm.x() = d; - dsti->dm.y() = vmin; - - for (int j = 0; j < QK4_1 / 2; ++j) { - const float x0 = (xi[0 + j] - vmin) * id; - const float x1 = (xi[QK4_1 / 2 + j] - vmin) * id; - - const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 0.5f)); - const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 0.5f)); - - dsti->qs[j] = xi0; - dsti->qs[j] |= xi1 << 4; - } -} - -static void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_0 * dsti = (block_q5_0 *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK5_0; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - const float d = vmax / -16; - const float id = d ? 1.0f / d : 0.0f; - - dsti->d = d; - - uint32_t qh = 0; - for (int j = 0; j < QK5_0 / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK5_0 / 2 + j] * id; - - const uint8_t xi0 = dpct::min(31, (int8_t) (x0 + 16.5f)); - const uint8_t xi1 = dpct::min(31, (int8_t) (x1 + 16.5f)); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0 / 2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - -static void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_q5_1 * dsti = (block_q5_1 *) cdsti; - - float min = xi[0]; - float max = xi[0]; - - for (int j = 1; j < QK5_1; ++j) { - const float v = xi[j]; - min = v < min ? v : min; - max = v > max ? v : max; - } - - const float d = (max - min) / 31; - const float id = d ? 1.0f / d : 0.0f; - - dsti->dm.x() = d; - dsti->dm.y() = min; - - uint32_t qh = 0; - for (int j = 0; j < QK5_1 / 2; ++j) { - const float x0 = (xi[0 + j] - min) * id; - const float x1 = (xi[QK5_1 / 2 + j] - min) * id; - - const uint8_t xi0 = (uint8_t) (x0 + 0.5f); - const uint8_t xi1 = (uint8_t) (x1 + 0.5f); - - dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); - qh |= ((xi0 & 0x10u) >> 4) << (j + 0); - qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1 / 2); - } - memcpy(dsti->qh, &qh, sizeof(qh)); -} - -static void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { - const float * xi = (const float *) cxi; - block_iq4_nl * dsti = (block_iq4_nl *) cdsti; - - float amax = 0.0f; - float vmax = 0.0f; - - for (int j = 0; j < QK4_NL; ++j) { - const float v = xi[j]; - if (amax < sycl::fabs((float) v)) { - amax = sycl::fabs((float) v); - vmax = v; - } - } - - float d = vmax / kvalues_iq4nl[0]; - const float id = d ? 1.0f / d : 0.0f; - - float sumqx = 0, sumq2 = 0; - for (int j = 0; j < QK4_NL / 2; ++j) { - const float x0 = xi[0 + j] * id; - const float x1 = xi[QK4_NL / 2 + j] * id; - const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); - const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); - dsti->qs[j] = xi0 | (xi1 << 4); - const float v0 = kvalues_iq4nl[xi0]; - const float v1 = kvalues_iq4nl[xi1]; - const float w0 = xi[0 + j] * xi[0 + j]; - const float w1 = xi[QK4_NL / 2 + j] * xi[QK4_NL / 2 + j]; - sumqx += w0 * v0 * xi[j] + w1 * v1 * xi[QK4_NL / 2 + j]; - sumq2 += w0 * v0 * v0 + w1 * v1 * v1; - } - - dsti->d = sumq2 > 0 ? sumqx / sumq2 : d; -} template static void cpy_blck_q_f32(const char * cxi, char * cdsti) { float * cdstf = (float *) (cdsti); @@ -413,8 +201,7 @@ static void ggml_cpy_f16_f32_sycl(const { dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -432,8 +219,7 @@ static void ggml_cpy_f32_f32_sycl(const { dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -451,8 +237,7 @@ static void ggml_cpy_f32_f16_sycl(const { dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -468,11 +253,11 @@ static void ggml_cpy_f32_q8_0_sycl(const const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK8_0 == 0); const int num_blocks = ne / QK8_0; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_q8_0_f32_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -480,11 +265,11 @@ static void ggml_cpy_q8_0_f32_sycl(const const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ne; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_f32(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_q_f32(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_f32_q4_0_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -493,11 +278,11 @@ static void ggml_cpy_f32_q4_0_sycl(const const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK4_0 == 0); const int num_blocks = ne / QK4_0; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_q4_0_f32_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -505,9 +290,8 @@ static void ggml_cpy_q4_0_f32_sycl(const const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ne; - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { cpy_q_f32, QK4_0>(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); @@ -520,11 +304,11 @@ static void ggml_cpy_f32_q4_1_sycl(const const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK4_1 == 0); const int num_blocks = ne / QK4_1; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_q4_1_f32_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -532,9 +316,8 @@ static void ggml_cpy_q4_1_f32_sycl(const const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ne; - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { cpy_q_f32, QK4_1>(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); @@ -547,11 +330,11 @@ static void ggml_cpy_f32_q5_0_sycl(const const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK5_0 == 0); const int num_blocks = ne / QK5_0; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_q5_0_f32_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -559,9 +342,8 @@ static void ggml_cpy_q5_0_f32_sycl(const const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ne; - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { cpy_q_f32, QK5_0>(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); @@ -574,11 +356,11 @@ static void ggml_cpy_f32_q5_1_sycl(const const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK5_1 == 0); const int num_blocks = ne / QK5_1; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), + [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, + ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_q5_1_f32_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -586,9 +368,8 @@ static void ggml_cpy_q5_1_f32_sycl(const const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ne; - sycl_parallel_for( - stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { cpy_q_f32, QK5_1>(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); @@ -601,11 +382,11 @@ static void ggml_cpy_f32_iq4_nl_sycl(con const int nb12, const int nb13, queue_ptr stream) { GGML_ASSERT(ne % QK4_NL == 0); const int num_blocks = ne / QK4_NL; - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), - [=](sycl::nd_item<3> item_ct1) { - cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, - ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks), sycl::range<3>(1, 1, 1)), [=](sycl::nd_item<3> item_ct1) { + cpy_f32_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, + ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } static void ggml_cpy_f16_f16_sycl(const char * cx, char * cdst, const int ne, const int ne00, const int ne01, @@ -616,8 +397,7 @@ static void ggml_cpy_f16_f16_sycl(const { dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -636,8 +416,7 @@ static void ggml_cpy_i16_i16_sycl(const // dpct::has_capability_or_fail(stream->get_device(), // {sycl::aspect::fp16}); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -656,8 +435,7 @@ static void ggml_cpy_i32_i32_sycl(const // dpct::has_capability_or_fail(stream->get_device(), // {sycl::aspect::fp16}); - sycl_parallel_for( - stream, + stream->parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { @@ -672,13 +450,11 @@ static void ggml_cpy_q8_0_q8_0(const cha const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ceil_div(ne, SYCL_CPY_BLOCK_SIZE); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, - ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { + cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } @@ -687,13 +463,11 @@ static void ggml_cpy_q5_0_q5_0(const cha const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ceil_div(ne, SYCL_CPY_BLOCK_SIZE); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, - ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { + cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } @@ -703,13 +477,11 @@ static void ggml_cpy_q5_1_q5_1(const cha const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ceil_div(ne, SYCL_CPY_BLOCK_SIZE); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, - ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), + sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { + cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } @@ -718,13 +490,10 @@ static void ggml_cpy_q4_0_q4_0(const cha const int ne10, const int ne11, const int ne12, const int nb10, const int nb11, const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ceil_div(ne, SYCL_CPY_BLOCK_SIZE); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, - ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { + cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } @@ -734,13 +503,10 @@ static void ggml_cpy_q4_1_q4_1(const cha const int nb12, const int nb13, queue_ptr stream) { const int num_blocks = ceil_div(ne, SYCL_CPY_BLOCK_SIZE); - sycl_parallel_for(stream, - sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), - sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), - [=](sycl::nd_item<3> item_ct1) { - cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, - ne12, nb10, nb11, nb12, nb13, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, num_blocks) * sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_CPY_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { + cpy_q_q(cx, cdst, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, item_ct1); + }); } void ggml_sycl_cpy(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1) try { diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/cpy.hpp 6641+dfsg-2/ggml/src/ggml-sycl/cpy.hpp --- 5882+dfsg-2/ggml/src/ggml-sycl/cpy.hpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/cpy.hpp 2025-09-30 07:36:33.000000000 +0000 @@ -2,10 +2,222 @@ #define GGML_SYCL_CPY_HPP #include "common.hpp" +#include typedef void (*cpy_kernel_t)(const char * cx, char * cdst); +__dpct_inline__ int best_index_int8(int n, const int8_t * val, float x) { + if (x <= val[0]) { + return 0; + } + if (x >= val[n - 1]) { + return n - 1; + } + int ml = 0, mu = n - 1; + while (mu - ml > 1) { + int mav = (ml + mu) / 2; + if (x < val[mav]) { + mu = mav; + } else { + ml = mav; + } + } + return x - val[mu - 1] < val[mu] - x ? mu - 1 : mu; +} + +inline void cpy_blck_f32_q8_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q8_0 * dsti = (block_q8_0 *) cdsti; + + float amax = 0.0f; // absolute max + + for (int j = 0; j < QK8_0; j++) { + const float v = xi[j]; + amax = sycl::fmax(amax, sycl::fabs((float) v)); + } + + const float d = amax / ((1 << 7) - 1); + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + for (int j = 0; j < QK8_0; ++j) { + const float x0 = xi[j] * id; + + dsti->qs[j] = sycl::round((float) x0); + } +} + +inline void cpy_blck_f32_q4_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q4_0 * dsti = (block_q4_0 *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_0; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + const float d = vmax / -8; + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + for (int j = 0; j < QK4_0 / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK4_0 / 2 + j] * id; + + const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 8.5f)); + const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 8.5f)); + + dsti->qs[j] = xi0; + dsti->qs[j] |= xi1 << 4; + } +} + +inline void cpy_blck_f32_q4_1(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q4_1 * dsti = (block_q4_1 *) cdsti; + + float vmin = FLT_MAX; + float vmax = -FLT_MAX; + + for (int j = 0; j < QK4_1; ++j) { + const float v = xi[j]; + + vmin = sycl::min(v, vmin); + vmax = sycl::max(v, vmax); + } + + const float d = (vmax - vmin) / ((1 << 4) - 1); + const float id = d ? 1.0f / d : 0.0f; + + dsti->dm.x() = d; + dsti->dm.y() = vmin; + + for (int j = 0; j < QK4_1 / 2; ++j) { + const float x0 = (xi[0 + j] - vmin) * id; + const float x1 = (xi[QK4_1 / 2 + j] - vmin) * id; + + const uint8_t xi0 = dpct::min(15, (int8_t) (x0 + 0.5f)); + const uint8_t xi1 = dpct::min(15, (int8_t) (x1 + 0.5f)); + + dsti->qs[j] = xi0; + dsti->qs[j] |= xi1 << 4; + } +} + +inline void cpy_blck_f32_q5_0(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q5_0 * dsti = (block_q5_0 *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK5_0; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + const float d = vmax / -16; + const float id = d ? 1.0f / d : 0.0f; + + dsti->d = d; + + uint32_t qh = 0; + for (int j = 0; j < QK5_0 / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK5_0 / 2 + j] * id; + + const uint8_t xi0 = dpct::min(31, (int8_t) (x0 + 16.5f)); + const uint8_t xi1 = dpct::min(31, (int8_t) (x1 + 16.5f)); + + dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_0 / 2); + } + memcpy(dsti->qh, &qh, sizeof(qh)); +} + +inline void cpy_blck_f32_q5_1(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_q5_1 * dsti = (block_q5_1 *) cdsti; + + float min = xi[0]; + float max = xi[0]; + + for (int j = 1; j < QK5_1; ++j) { + const float v = xi[j]; + min = v < min ? v : min; + max = v > max ? v : max; + } + + const float d = (max - min) / 31; + const float id = d ? 1.0f / d : 0.0f; + + dsti->dm.x() = d; + dsti->dm.y() = min; + + uint32_t qh = 0; + for (int j = 0; j < QK5_1 / 2; ++j) { + const float x0 = (xi[0 + j] - min) * id; + const float x1 = (xi[QK5_1 / 2 + j] - min) * id; + + const uint8_t xi0 = (uint8_t) (x0 + 0.5f); + const uint8_t xi1 = (uint8_t) (x1 + 0.5f); + + dsti->qs[j] = (xi0 & 0xf) | ((xi1 & 0xf) << 4); + qh |= ((xi0 & 0x10u) >> 4) << (j + 0); + qh |= ((xi1 & 0x10u) >> 4) << (j + QK5_1 / 2); + } + memcpy(dsti->qh, &qh, sizeof(qh)); +} + +inline void cpy_blck_f32_iq4_nl(const char * cxi, char * cdsti) { + const float * xi = (const float *) cxi; + block_iq4_nl * dsti = (block_iq4_nl *) cdsti; + + float amax = 0.0f; + float vmax = 0.0f; + + for (int j = 0; j < QK4_NL; ++j) { + const float v = xi[j]; + if (amax < sycl::fabs((float) v)) { + amax = sycl::fabs((float) v); + vmax = v; + } + } + + float d = vmax / kvalues_iq4nl[0]; + const float id = d ? 1.0f / d : 0.0f; + + float sumqx = 0, sumq2 = 0; + for (int j = 0; j < QK4_NL / 2; ++j) { + const float x0 = xi[0 + j] * id; + const float x1 = xi[QK4_NL / 2 + j] * id; + const uint8_t xi0 = best_index_int8(16, kvalues_iq4nl, x0); + const uint8_t xi1 = best_index_int8(16, kvalues_iq4nl, x1); + dsti->qs[j] = xi0 | (xi1 << 4); + const float v0 = kvalues_iq4nl[xi0]; + const float v1 = kvalues_iq4nl[xi1]; + const float w0 = xi[0 + j] * xi[0 + j]; + const float w1 = xi[QK4_NL / 2 + j] * xi[QK4_NL / 2 + j]; + sumqx += w0 * v0 * xi[j] + w1 * v1 * xi[QK4_NL / 2 + j]; + sumq2 += w0 * v0 * v0 + w1 * v1 * v1; + } + + dsti->d = sumq2 > 0 ? sumqx / sumq2 : d; +} + void ggml_sycl_cpy(ggml_backend_sycl_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1); void ggml_sycl_dup(ggml_backend_sycl_context & ctx, ggml_tensor * dst); -#endif // GGML_SYCL_CPY_HPP +#endif // GGML_SYCL_CPY_HPP diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/dmmv.cpp 6641+dfsg-2/ggml/src/ggml-sycl/dmmv.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/dmmv.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/dmmv.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -208,10 +208,12 @@ static void convert_mul_mat_vec_f16_sycl dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec<1, 1, convert_f16>(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec<1, 1, convert_f16>(vx, y, dst, ncols, + nrows, item_ct1); + }); } } @@ -875,11 +877,12 @@ static void dequantize_mul_mat_vec_q4_0_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec_reorder(vx, y, dst, ncols, - nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec_reorder( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -897,10 +900,12 @@ static void dequantize_mul_mat_vec_q4_0_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -916,10 +921,12 @@ static void dequantize_mul_mat_vec_q4_1_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -935,10 +942,12 @@ static void dequantize_mul_mat_vec_q5_0_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -954,10 +963,12 @@ static void dequantize_mul_mat_vec_q5_1_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -973,10 +984,12 @@ static void dequantize_mul_mat_vec_q8_0_ dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - dequantize_mul_mat_vec(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { + dequantize_mul_mat_vec( + vx, y, dst, ncols, nrows, item_ct1); + }); } } @@ -989,10 +1002,11 @@ static void dequantize_mul_mat_vec_q2_K_ const int block_num_y = (nrows + ny - 1) / ny; const sycl::range<3> block_nums(1, 1, block_num_y); const sycl::range<3> block_dims(1, ny, QK_WARP_SIZE); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { - dequantize_mul_mat_vec_q2_k(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { + dequantize_mul_mat_vec_q2_k(vx, y, dst, ncols, nrows, item_ct1); + }); } static void dequantize_mul_mat_vec_q3_K_sycl(const void *vx, const float *y, @@ -1004,10 +1018,11 @@ static void dequantize_mul_mat_vec_q3_K_ const int block_num_y = (nrows + ny - 1) / ny; const sycl::range<3> block_nums(1, 1, block_num_y); const sycl::range<3> block_dims(1, ny, QK_WARP_SIZE); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { - dequantize_mul_mat_vec_q3_k(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { + dequantize_mul_mat_vec_q3_k(vx, y, dst, ncols, nrows, item_ct1); + }); } static void dequantize_mul_mat_vec_q4_K_sycl(const void *vx, const float *y, @@ -1019,10 +1034,11 @@ static void dequantize_mul_mat_vec_q4_K_ const int block_num_y = (nrows + ny - 1) / ny; const sycl::range<3> block_nums(1, 1, block_num_y); const sycl::range<3> block_dims(1, ny, QK_WARP_SIZE); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { - dequantize_mul_mat_vec_q4_k(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { + dequantize_mul_mat_vec_q4_k(vx, y, dst, ncols, nrows, item_ct1); + }); } static void dequantize_mul_mat_vec_q5_K_sycl(const void *vx, const float *y, @@ -1031,10 +1047,11 @@ static void dequantize_mul_mat_vec_q5_K_ dpct::queue_ptr stream) { GGML_ASSERT(ncols % QK_K == 0); const sycl::range<3> block_dims(1, 1, QK_WARP_SIZE); - sycl_parallel_for(stream, sycl::nd_range<3>(sycl::range<3>(1, 1, nrows) * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { - dequantize_mul_mat_vec_q5_k(vx, y, dst, ncols, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(sycl::range<3>(1, 1, nrows) * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { + dequantize_mul_mat_vec_q5_k(vx, y, dst, ncols, item_ct1); + }); } static void dequantize_mul_mat_vec_q6_K_sycl(const void *vx, const float *y, @@ -1046,10 +1063,11 @@ static void dequantize_mul_mat_vec_q6_K_ const int block_num_y = (nrows + ny - 1) / ny; const sycl::range<3> block_nums(1, 1, block_num_y); const sycl::range<3> block_dims(1, ny, QK_WARP_SIZE); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { - dequantize_mul_mat_vec_q6_k(vx, y, dst, ncols, nrows, item_ct1); - }); + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(QK_WARP_SIZE)]] { + dequantize_mul_mat_vec_q6_k(vx, y, dst, ncols, nrows, item_ct1); + }); } void ggml_sycl_op_dequantize_mul_mat_vec( diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/dpct/helper.hpp 6641+dfsg-2/ggml/src/ggml-sycl/dpct/helper.hpp --- 5882+dfsg-2/ggml/src/ggml-sycl/dpct/helper.hpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/dpct/helper.hpp 2025-09-30 07:36:33.000000000 +0000 @@ -13,10 +13,10 @@ #ifndef GGML_SYCL_DPCT_HELPER_HPP #define GGML_SYCL_DPCT_HELPER_HPP -#include #include #include #include +#include #ifdef GGML_SYCL_USE_INTEL_ONEMKL #include @@ -118,36 +118,6 @@ inline auto get_onemath_backend(sycl::qu #endif } -#ifdef SYCL_EXT_ONEAPI_ENQUEUE_FUNCTIONS - namespace syclex = sycl::ext::oneapi::experimental; -#endif - -template -__dpct_inline__ void sycl_parallel_for(sycl::handler & cgh, sycl::nd_range nd_range, Func && func) { -#ifdef SYCL_EXT_ONEAPI_ENQUEUE_FUNCTIONS - syclex::nd_launch(cgh, nd_range, func); -#else - cgh.parallel_for(nd_range, func); -#endif -} - -template -__dpct_inline__ void sycl_parallel_for(sycl::queue * q, sycl::nd_range nd_range, Func && func) { -#ifdef SYCL_EXT_ONEAPI_ENQUEUE_FUNCTIONS - syclex::nd_launch(*q, nd_range, func); -#else - q->parallel_for(nd_range, func); -#endif -} - -template __dpct_inline__ void sycl_launch(sycl::queue * stream, Func && func) { -#ifdef SYCL_EXT_ONEAPI_ENQUEUE_FUNCTIONS - syclex::submit(*stream, func); -#else - stream->submit(func); -#endif -} - namespace dpct { typedef sycl::queue *queue_ptr; diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/element_wise.cpp 6641+dfsg-2/ggml/src/ggml-sycl/element_wise.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/element_wise.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/element_wise.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -407,7 +407,7 @@ static void acc_f32_sycl(const float *x, const int ne12, const int nb1, const int nb2, const int offset, queue_ptr stream) { int num_blocks = ceil_div(n_elements, SYCL_ACC_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_ACC_BLOCK_SIZE), sycl::range<1>(SYCL_ACC_BLOCK_SIZE)), @@ -425,8 +425,8 @@ static void upscale_sycl(const T *x, T * int dst_size = ne10 * ne11 * ne12 * ne13; int num_blocks = ceil_div(dst_size, SYCL_UPSCALE_BLOCK_SIZE); sycl::range<1> gridDim(num_blocks * SYCL_UPSCALE_BLOCK_SIZE); - sycl_parallel_for<1>( - stream, sycl::nd_range<1>(gridDim, sycl::range<1>(SYCL_UPSCALE_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { + stream->parallel_for( + sycl::nd_range<1>(gridDim, sycl::range<1>(SYCL_UPSCALE_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { upscale(x, dst, nb00, nb01, nb02, nb03, ne10, ne11, ne12, ne13, sf0, sf1, sf2, sf3, item_ct1); }); } @@ -437,7 +437,7 @@ static void pad_sycl(const T *x, T *dst, const int ne1, const int ne2, queue_ptr stream) { int num_blocks = ceil_div(ne0, SYCL_PAD_BLOCK_SIZE); sycl::range<3> gridDim(ne2, ne1, num_blocks); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<3>(gridDim * sycl::range<3>(1, 1, SYCL_PAD_BLOCK_SIZE), sycl::range<3>(1, 1, SYCL_PAD_BLOCK_SIZE)), [=](sycl::nd_item<3> item_ct1) { pad(x, dst, ne0, ne00, ne01, ne02, item_ct1); }); @@ -639,7 +639,7 @@ static inline void ggml_sycl_op_sgn(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, 256); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(256), sycl::range<1>(256)), [=](sycl::nd_item<1> item_ct1) { @@ -652,7 +652,7 @@ static inline void ggml_sycl_op_abs(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, 256); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(256), sycl::range<1>(256)), [=](sycl::nd_item<1> item_ct1) { @@ -665,7 +665,7 @@ static inline void ggml_sycl_op_elu(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, 256); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(256), sycl::range<1>(256)), [=](sycl::nd_item<1> item_ct1) { @@ -678,7 +678,7 @@ static inline void ggml_sycl_op_silu(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SILU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SILU_BLOCK_SIZE), sycl::range<1>(SYCL_SILU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -691,7 +691,7 @@ static inline void ggml_sycl_op_gelu(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_GELU_BLOCK_SIZE), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -704,7 +704,7 @@ static inline void ggml_sycl_op_gelu_qui ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_GELU_BLOCK_SIZE), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -717,7 +717,7 @@ static inline void ggml_sycl_op_gelu_erf ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_GELU_BLOCK_SIZE), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -730,7 +730,7 @@ static inline void ggml_sycl_op_tanh(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_TANH_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_TANH_BLOCK_SIZE), sycl::range<1>(SYCL_TANH_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -743,7 +743,7 @@ static inline void ggml_sycl_op_relu(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_RELU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_RELU_BLOCK_SIZE), sycl::range<1>(SYCL_RELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -756,7 +756,7 @@ static inline void ggml_sycl_op_hardsigm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_HARDSIGMOID_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_HARDSIGMOID_BLOCK_SIZE), sycl::range<1>(SYCL_HARDSIGMOID_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -769,7 +769,7 @@ static inline void ggml_sycl_op_hardswis ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_HARDSWISH_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_HARDSWISH_BLOCK_SIZE), sycl::range<1>(SYCL_HARDSWISH_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -782,7 +782,7 @@ static inline void ggml_sycl_op_exp(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_EXP_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_EXP_BLOCK_SIZE), sycl::range<1>(SYCL_EXP_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -795,7 +795,7 @@ static inline void ggml_sycl_op_log(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_EXP_BLOCK_SIZE); // Using EXP block size - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_EXP_BLOCK_SIZE), sycl::range<1>(SYCL_EXP_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -808,7 +808,7 @@ static inline void ggml_sycl_op_neg(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_NEG_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_NEG_BLOCK_SIZE), sycl::range<1>(SYCL_NEG_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -821,7 +821,7 @@ static inline void ggml_sycl_op_step(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_NEG_BLOCK_SIZE); // Using NEG block size - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_NEG_BLOCK_SIZE), sycl::range<1>(SYCL_NEG_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -834,7 +834,7 @@ static inline void ggml_sycl_op_sigmoid( ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SIGMOID_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SIGMOID_BLOCK_SIZE), sycl::range<1>(SYCL_SIGMOID_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -847,7 +847,7 @@ static inline void ggml_sycl_op_sqrt(ggm ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SQRT_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SQRT_BLOCK_SIZE), sycl::range<1>(SYCL_SQRT_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -860,7 +860,7 @@ static inline void ggml_sycl_op_sin(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SIN_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SIN_BLOCK_SIZE), sycl::range<1>(SYCL_SIN_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -873,7 +873,7 @@ static inline void ggml_sycl_op_cos(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SIN_BLOCK_SIZE); // Using SIN block size - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SIN_BLOCK_SIZE), sycl::range<1>(SYCL_SIN_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -888,7 +888,7 @@ static inline void ggml_sycl_op_leaky_re ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream, float slope) { const int num_blocks = ceil_div(k_elements, SYCL_RELU_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_RELU_BLOCK_SIZE), sycl::range<1>(SYCL_RELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -901,7 +901,7 @@ static inline void ggml_sycl_op_sqr(ggml ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream) { const int num_blocks = ceil_div(k_elements, SYCL_SQR_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_SQR_BLOCK_SIZE), sycl::range<1>(SYCL_SQR_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -935,7 +935,7 @@ static inline void ggml_sycl_op_clamp(gg ggml_sycl_detail::dispatch_ggml_sycl_op_unary(ctx, dst, [](const auto* src, auto* dst_ptr, int k_elements, queue_ptr stream, float min_arg, float max_arg) { const int num_blocks = ceil_div(k_elements, SYCL_CLAMP_BLOCK_SIZE); - sycl_parallel_for(stream, + stream->parallel_for( sycl::nd_range<1>(sycl::range<1>(num_blocks) * sycl::range<1>(SYCL_CLAMP_BLOCK_SIZE), sycl::range<1>(SYCL_CLAMP_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { @@ -967,7 +967,7 @@ static inline void ggml_sycl_op_geglu(gg ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst, [](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) { const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(main_stream, + main_stream->parallel_for( sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { gated_op_fused_geglu(x_ptr, g_ptr, dst_ptr, k, n, o0, o1, item_ct1); }); @@ -978,7 +978,7 @@ static inline void ggml_sycl_op_reglu(gg ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst, [](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) { const uint32_t num_blocks = ceil_div((uint32_t)k, SYCL_RELU_BLOCK_SIZE); // Using RELU block size for reglu - sycl_parallel_for(main_stream, + main_stream->parallel_for( sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_RELU_BLOCK_SIZE)), sycl::range<1>(SYCL_RELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { gated_op_fused_reglu(x_ptr, g_ptr, dst_ptr, k, n, o0, o1, item_ct1); }); @@ -989,7 +989,7 @@ static inline void ggml_sycl_op_swiglu(g ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst, [](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) { const uint32_t num_blocks = ceil_div((uint32_t)k, SYCL_SILU_BLOCK_SIZE); // Using SILU block size for swiglu - sycl_parallel_for(main_stream, + main_stream->parallel_for( sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_SILU_BLOCK_SIZE)), sycl::range<1>(SYCL_SILU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { gated_op_fused_swiglu(x_ptr, g_ptr, dst_ptr, k, n, o0, o1, item_ct1); }); @@ -1000,7 +1000,7 @@ static inline void ggml_sycl_op_geglu_er ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst, [](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) { const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(main_stream, + main_stream->parallel_for( sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { gated_op_fused_geglu_erf(x_ptr, g_ptr, dst_ptr, k, n, o0, o1, item_ct1); }); @@ -1011,7 +1011,7 @@ static inline void ggml_sycl_op_geglu_qu ggml_sycl_detail::dispatch_ggml_sycl_op_fused_glu(ctx, dst, [](const auto* x_ptr, const auto* g_ptr, auto* dst_ptr, uint64_t k, uint64_t n, uint64_t o0, uint64_t o1, queue_ptr main_stream) { const uint32_t num_blocks = ceil_div(k, SYCL_GELU_BLOCK_SIZE); - sycl_parallel_for(main_stream, + main_stream->parallel_for( sycl::nd_range<1>((num_blocks * sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), sycl::range<1>(SYCL_GELU_BLOCK_SIZE)), [=](sycl::nd_item<1> item_ct1) { gated_op_fused_geglu_quick(x_ptr, g_ptr, dst_ptr, k, n, o0, o1, item_ct1); }); diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/gemm.hpp 6641+dfsg-2/ggml/src/ggml-sycl/gemm.hpp --- 5882+dfsg-2/ggml/src/ggml-sycl/gemm.hpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/gemm.hpp 2025-09-30 07:36:33.000000000 +0000 @@ -32,39 +32,28 @@ public: else static_assert(0); } - // matrix A has m rows, k columns - // matrix B has k rows, n columns - // nra - number of elements to skip when moving into next row in A - // nrb - number of elements to skip when moving into next row in B - // nca - number of elements to skip when moving into next column in A - // ncb - number of elements to skip when moving into next column in B - // stride_a - number of elements to skip when moving to next A matrix - // stride_b - number of elements to skip when moving to next B matrix - // batches_a - number of A matrices - // batches_b - number of B matrices static void gemm(ggml_backend_sycl_context & ctx, int m, int n, int k, - const void * a, dt at, dnnl_dim_t nra, dnnl_dim_t nca, dnnl_dim_t stride_a, - const void * b, dt bt, dnnl_dim_t nrb, dnnl_dim_t ncb, dnnl_dim_t stride_b, + const void * a, dt at, dnnl_dim_t stra0, dnnl_dim_t stra1, dnnl_dim_t stra2, + const void * b, dt bt, dnnl_dim_t strb0, dnnl_dim_t strb1, dnnl_dim_t strb2, void * c, dt ct, const queue_ptr & q, dnnl_dim_t batches_a, dnnl_dim_t batches_b) { auto stream = ctx.stream_dnnl(q); auto eng = ctx.engine_dnnl(q); - // { # strides, # rows, # columns } - dnnl::memory::dims a_dims = { batches_a, m, k }; - dnnl::memory::dims b_dims = { batches_b, k, n }; - dnnl::memory::dims c_dims = { std::max(batches_a, batches_b), m, n }; - - // { # elements to skip to next stride, # elements to skip to next row, # elements to skip to next column } - dnnl::memory::dims a_strides = { stride_a, nra, nca }; - dnnl::memory::dims b_strides = { stride_b, nrb, ncb }; - + dnnl::memory::dims a_dims = {batches_a, m, k }; + dnnl::memory::dims a_strides = {stra2, stra1, stra0}; const auto a_in_md = dnnl::memory::desc(a_dims, at, a_strides); + + dnnl::memory::dims b_dims = {batches_b, k, n }; + dnnl::memory::dims b_strides = {strb2, strb0, strb1}; const auto b_in_md = dnnl::memory::desc(b_dims, bt, b_strides); - const auto c_md = dnnl::memory::desc(c_dims, ct, tag::abc); + dnnl::memory::dims c_dims = { std::max(batches_a, batches_b), m, n}; + dnnl::memory::dims c_strides = {m*n, 1, m }; + const auto c_md = dnnl::memory::desc(c_dims, ct, c_strides); dnnl::primitive_attr primitive_attr; primitive_attr.set_scratchpad_mode(dnnl::scratchpad_mode::user); + #ifdef GGML_SYCL_F16 primitive_attr.set_fpmath_mode(dnnl::fpmath_mode::f16); #endif @@ -76,24 +65,23 @@ public: auto scratchpad_md = matmul_pd.scratchpad_desc(); auto scratchpad_mem = ctx.get_scratchpad_mem(scratchpad_md, eng, q); + auto matmul_prim = dnnl::matmul(matmul_pd); std::unordered_map matmul_args; matmul_args.insert({ DNNL_ARG_SRC, a_mem }); matmul_args.insert({ DNNL_ARG_WEIGHTS, b_mem }); + matmul_args.insert({ DNNL_ARG_DST, c_mem }); matmul_args.insert({ DNNL_ARG_SCRATCHPAD, scratchpad_mem }); matmul_prim.execute(stream, matmul_args); } - // matrices A and B are column major, both having k rows - // matrix A has m column, matrix B has n columns - // output: column major matrix C = A transposed * B static void row_gemm(ggml_backend_sycl_context & ctx, int m, int n, int k, const void * a, dt at, const void * b, dt bt, void * c, dt ct, const queue_ptr & q) { - gemm(ctx, m, n, k, a, at, k, 1, k * m, b, bt, 1, k, n * k, c, ct, q, 1, 1); + gemm(ctx, m, n, k, a, at, 1, k, k * m, b, bt, 1, k, n * k, c, ct, q, 1, 1); } }; diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/getrows.cpp 6641+dfsg-2/ggml/src/ggml-sycl/getrows.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/getrows.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/getrows.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -118,10 +118,12 @@ static void get_rows_sycl(ggml_backend_s GGML_ASSERT(ne00 % 2 == 0); - sycl_parallel_for(stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { - k_get_rows(src0_dd, src1_dd, dst_dd, ne00, ne12, s1, s2, s3, nb01, nb02, nb03, s10, s11, s12, - item_ct1); - }); + stream->parallel_for(sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + k_get_rows( + src0_dd, src1_dd, dst_dd, ne00, ne12, s1, s2, + s3, nb01, nb02, nb03, s10, s11, s12, item_ct1); + }); GGML_UNUSED(dst); GGML_UNUSED(ctx); @@ -154,8 +156,9 @@ static void get_rows_sycl_float(ggml_bac dpct::has_capability_or_fail(stream->get_device(), {sycl::aspect::fp16}); - sycl_parallel_for( - stream, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { + stream->parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { k_get_rows_float(src0_dd, src1_dd, dst_dd, ne00, ne12, s1, s2, s3, nb01, nb02, nb03, s10, s11, s12, item_ct1); }); diff -pruN 5882+dfsg-2/ggml/src/ggml-sycl/ggml-sycl.cpp 6641+dfsg-2/ggml/src/ggml-sycl/ggml-sycl.cpp --- 5882+dfsg-2/ggml/src/ggml-sycl/ggml-sycl.cpp 2025-07-12 13:31:38.000000000 +0000 +++ 6641+dfsg-2/ggml/src/ggml-sycl/ggml-sycl.cpp 2025-09-30 07:36:33.000000000 +0000 @@ -44,6 +44,7 @@ #include "ggml-sycl/set_rows.hpp" #include "ggml-sycl/sycl_hw.hpp" #include "ggml-sycl/getrows.hpp" +#include "ggml-sycl/quantize.hpp" #include "ggml.h" static bool g_sycl_loaded = false; @@ -1373,120 +1374,6 @@ typedef void (*ggml_sycl_op_mul_mat_t)( -template -static void quantize_q8_1(const float * __restrict__ x, void * __restrict__ vy, const int kx, const int kx_padded, - const sycl::nd_item<3> &item_ct1) { - const int ix = (item_ct1.get_local_range(2) * item_ct1.get_group(2) + - item_ct1.get_local_id(2)) * QUANT_BLOCK_TILE; - - if (ix >= kx_padded) { - return; - } - - const int iy = item_ct1.get_local_range(1) * item_ct1.get_group(1) + - item_ct1.get_local_id(1); - - const int i_padded = iy*kx_padded + ix; - - block_q8_1 * y = (block_q8_1 *) vy; - - const int ib = i_padded / QK8_1; // block index - const int iqs = i_padded % QK8_1; // quant index - typedef sycl::vec TC; - typedef sycl::vec TQ; - TC zeros; - TQ qzeros; -#pragma unroll - for (int i = 0; i < QUANT_BLOCK_TILE; i++) - { - zeros[i] = 0.f; - qzeros[i] = 0; - } - const TC xi = ix < kx ? *(const TC *)&x[iy * kx + ix] : zeros; - float sum = xi[0]; - float amax = sycl::fabs(xi[0]); -#pragma unroll - for (int i = 1; i < QUANT_BLOCK_TILE; i++) - { - sum += xi[i]; - amax = sycl::fmax(sycl::fabs(xi[i]), amax); - } - sum = warp_reduce_sum(sum, item_ct1); - amax = warp_reduce_max(amax, item_ct1); - - const float d = amax / 127; - TQ q = qzeros; - if (amax != 0.0f) - { -#pragma unroll - for (int i = 0; i < QUANT_BLOCK_TILE; i++) { - q[i] = sycl::round(xi[i] / d); - } - } - - *(TQ *)&y[ib].qs[iqs] = q; - - if (iqs > 0) { - return; - } - - reinterpret_cast(y[ib].ds.x()) = d; - reinterpret_cast(y[ib].ds.y()) = sum; -} - -template -static __dpct_inline__ void quantize_and_reorder_q8_1(const float * __restrict__ x, void * reordered_q8_tensor, - const int kx, const int kx_padded, const sycl::nd_item<1> & it) { - /* - Quantizes and reorders the resultant q8 tensor in a per row fashion - Each sub-group calculates one quant block. i.e. QK8_1 quant values and the d and sum values - */ - - auto subgroup_id = it.get_group(0); - auto wi_id = it.get_local_id(0); - - const int num_blocks_per_row = kx / QK8_1; - auto row = subgroup_id / num_blocks_per_row; - auto col = subgroup_id % num_blocks_per_row; - - auto row_offset = row * (kx_padded / QK8_1) * sizeof(block_q8_1); - auto col_offset = QK8_1 * col + wi_id * ElementsPerWI; - - auto quant_ptr = (int8_t *) ((char *) reordered_q8_tensor + row_offset + col_offset); - auto ds_ptr = (sycl::half2 *) ((char *) reordered_q8_tensor + row_offset + kx + col * sizeof(sycl::half2)); - - sycl::vec wi_f32_vals; - sycl::vec quantized_values; - - auto float_ptr_offset = subgroup_id * QK8_1 + ElementsPerWI * wi_id; - wi_f32_vals = *reinterpret_cast *>(x + float_ptr_offset); - - float sum = 0.0f; - float amax = 0.0f; - -#pragma unroll(ElementsPerWI) - for (int i = 0; i < ElementsPerWI; i++) { - sum += wi_f32_vals[i]; - amax = sycl::fmax(amax, sycl::fabs(wi_f32_vals[i])); - quantized_values[i] = 0; - } - sum = sycl::reduce_over_group(it.get_group(), sum, sycl::plus()); - amax = sycl::reduce_over_group(it.get_group(), amax, sycl::maximum()); - float d = amax == 0 ? 1 : amax / 127; - -#pragma unroll(ElementsPerWI) - for (int i = 0; i < ElementsPerWI; i++) { - quantized_values[i] = sycl::round(wi_f32_vals[i] / d); - } - - d = amax == 0 ? 0 : d; - - *reinterpret_cast *>(quant_ptr) = quantized_values; - if (wi_id == 0) { - *ds_ptr = sycl::half2(sycl::half(d), sycl::half(sum)); - } -} - static void mul_mat_p021_f16_f32( const void * __restrict__ vx, const float * __restrict__ y, float * __restrict__ dst, const int ncols_x, const int nrows_x, const int nchannels_x, const int nchannels_y, @@ -1546,7 +1433,7 @@ static void mul_mat_p021_f16_f32( static void mul_mat_vec_nc_f16_f32( // nc == non-contiguous const void * __restrict__ vx, const float * __restrict__ y, float * __restrict__ dst, const int ncols_x, const int nrows_x, - const int row_stride_x, const int channel_stride_x, const int channel_x_divisor, + const int row_stride_x, const int channel_stride_x,const int channel_stride_y, const int channel_x_divisor, const sycl::nd_item<3> &item_ct1) { const sycl::half *x = (const sycl::half *)vx; @@ -1557,7 +1444,6 @@ static void mul_mat_vec_nc_f16_f32( // n item_ct1.get_local_id(0); const int channel_x = channel / channel_x_divisor; - const int nrows_y = ncols_x; const int nrows_dst = nrows_x; const int row_dst = row_x; @@ -1576,7 +1462,7 @@ static void mul_mat_vec_nc_f16_f32( // n const int row_y = col_x; const int ix = channel_x*channel_stride_x + row_x*row_stride_x + col_x; - const int iy = channel*nrows_y + row_y; + const int iy = channel * channel_stride_y + row_y; const float xi = sycl::vec(x[ix]) @@ -1771,32 +1657,6 @@ static void pool2d_nchw_kernel( o_ptr[cur_oh * ow + cur_ow] = res; } -static void quantize_row_q8_1_sycl(const float * x, void * vy, const int kx, const int ky, const int kx_padded, - bool reorder_q8_tensor, queue_ptr stream) { - if (reorder_q8_tensor) { - auto local_range = std::size_t(WARP_SIZE); - auto num_quant_blocks = ky * (kx / QK8_1); - auto global_range = num_quant_blocks * local_range; - stream->parallel_for(sycl::nd_range<1>({ global_range }, { local_range }), - [=](sycl::nd_item<1> it) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - quantize_and_reorder_q8_1(x, vy, kx, kx_padded, it); - }); - } else { - const int block_num_x = (kx_padded + SYCL_QUANTIZE_BLOCK_SIZE - 1) / SYCL_QUANTIZE_BLOCK_SIZE; - const sycl::range<3> num_blocks(1, ky, block_num_x); - int constexpr QUANT_BLOCK_TILE = QK8_1 / WARP_SIZE; - static_assert(QK8_1 % WARP_SIZE == 0); - const sycl::range<3> block_size(1, 1, SYCL_QUANTIZE_BLOCK_SIZE / QUANT_BLOCK_TILE); - { - dpct::has_capability_or_fail(stream->get_device(), { sycl::aspect::fp16 }); - - stream->parallel_for(sycl::nd_range<3>(num_blocks * block_size, block_size), - [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { - quantize_q8_1(x, vy, kx, kx_padded, item_ct1); - }); - } - } -} static void ggml_mul_mat_p021_f16_f32_sycl(const void *vx, const float *y, float *dst, const int ncols_x, @@ -1823,7 +1683,7 @@ static void ggml_mul_mat_p021_f16_f32_sy static void ggml_mul_mat_vec_nc_f16_f32_sycl( const void *vx, const float *y, float *dst, const int ncols_x, const int nrows_x, const int row_stride_x, const int nchannels_x, - const int nchannels_y, const int channel_stride_x, queue_ptr stream) { + const int nchannels_y, const int channel_stride_x, const int channel_stride_y, queue_ptr stream) { const sycl::range<3> block_nums(nchannels_y, nrows_x, 1); const sycl::range<3> block_dims(1, 1, WARP_SIZE); @@ -1835,7 +1695,7 @@ static void ggml_mul_mat_vec_nc_f16_f32_ sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) [[sycl::reqd_sub_group_size(WARP_SIZE)]] { mul_mat_vec_nc_f16_f32(vx, y, dst, ncols_x, nrows_x, - row_stride_x, channel_stride_x, + row_stride_x, channel_stride_x, channel_stride_y, nchannels_y / nchannels_x, item_ct1); }); } @@ -1886,12 +1746,13 @@ static void argsort_f32_i32_sycl(const f const size_t shared_mem = ncols_pad * sizeof(int); if (order == GGML_SORT_ORDER_ASC) { - sycl_launch(stream, [&](sycl::handler & cgh) { + stream->submit([&](sycl::handler &cgh) { sycl::local_accessor dpct_local_acc_ct1( sycl::range<1>(shared_mem), cgh); - sycl_parallel_for( - cgh, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { k_argsort_f32_i32( x, dst, ncols, ncols_pad, item_ct1, dpct_local_acc_ct1.get_multi_ptr() @@ -1899,12 +1760,13 @@ static void argsort_f32_i32_sycl(const f }); }); } else if (order == GGML_SORT_ORDER_DESC) { - sycl_launch(stream, [&](sycl::handler & cgh) { + stream->submit([&](sycl::handler &cgh) { sycl::local_accessor dpct_local_acc_ct1( sycl::range<1>(shared_mem), cgh); - sycl_parallel_for( - cgh, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { k_argsort_f32_i32( x, dst, ncols, ncols_pad, item_ct1, dpct_local_acc_ct1.get_multi_ptr() @@ -1922,47 +1784,50 @@ static void argmax_f32_i32_sycl(const fl const sycl::range<3> block_nums(1, nrows, 1); const size_t shared_mem = 256 * sizeof(float); - sycl_launch(stream, [&](sycl::handler & cgh) { + stream->submit([&](sycl::handler &cgh) { sycl::local_accessor shared_data( sycl::range<1>(shared_mem/sizeof(float)), cgh); sycl::local_accessor shared_indices( sycl::range<1>(shared_mem/sizeof(float)), cgh); - sycl_parallel_for(cgh, sycl::nd_range<3>(block_nums * block_dims, block_dims), [=](sycl::nd_item<3> item_ct1) { - const int tid = item_ct1.get_local_id(2); - const int row = item_ct1.get_global_id(1); - - float max_val = -INFINITY; - int max_idx = -1; - - for (int col = tid; col < ncols; col += 256) { - float val = x[row * ncols + col]; - if (val > max_val) { - max_val = val; - max_idx = col; + cgh.parallel_for( + sycl::nd_range<3>(block_nums * block_dims, block_dims), + [=](sycl::nd_item<3> item_ct1) { + const int tid = item_ct1.get_local_id(2); + const int row = item_ct1.get_global_id(1); + + float max_val = -INFINITY; + int max_idx = -1; + + for (int col = tid; col < ncols; col += 256) { + float val = x[row * ncols + col]; + if (val > max_val) { + max_val = val; + max_idx = col; + } } - } - shared_data[tid] = max_val; - shared_indices[tid] = max_idx; - item_ct1.barrier(sycl::access::fence_space::local_space); + shared_data[tid] = max_val; + shared_indices[tid] = max_idx; + item_ct1.barrier(sycl::access::fence_space::local_space); - for (int stride = 256 / 2; stride > 0; stride >>= 1) { - if (tid < stride) { - float val1 = shared_data[tid]; - float val2 = shared_data[tid + stride]; - if (val2 > val1) { - shared_data[tid] = val2; - shared_indices[tid] = shared_indices[tid + stride]; + for (int stride = 256/2; stride > 0; stride >>= 1) { + if (tid < stride) { + float val1 = shared_data[tid]; + float val2 = shared_data[tid + stride]; + if (val2 > val1) { + shared_data[tid] = val2; + shared_indices[tid] = shared_indices[tid + stride]; + } } + item_ct1.barrier(sycl::access::fence_space::local_space); } - item_ct1.barrier(sycl::access::fence_space::local_space); - } - if (tid == 0) { - dst[row] = shared_indices[0]; - } - }); + + if (tid == 0) { + dst[row] = shared_indices[0]; + } + }); }); } static void diag_mask_inf_f32_sycl(const float *x, float *dst, @@ -2124,8 +1989,8 @@ inline void ggml_sycl_op_mul_mat_sycl( #if GGML_SYCL_DNNL if (!g_ggml_sycl_disable_dnn) { - DnnlGemmWrapper::row_gemm(ctx, src1_ncols, row_diff, ne10, src1_ptr, - DnnlGemmWrapper::to_dt(), src0_ptr, DnnlGemmWrapper::to_dt(), + DnnlGemmWrapper::row_gemm(ctx,row_diff, src1_ncols , ne10, src0_ptr, + DnnlGemmWrapper::to_dt(), src1_ptr, DnnlGemmWrapper::to_dt(), dst_dd_i, DnnlGemmWrapper::to_dt(), stream); } else @@ -2171,8 +2036,8 @@ inline void ggml_sycl_op_mul_mat_sycl( #if GGML_SYCL_DNNL if (!g_ggml_sycl_disable_dnn) { - DnnlGemmWrapper::row_gemm(ctx, src1_ncols, row_diff, ne10, src1_ddf1_i, - DnnlGemmWrapper::to_dt(), src0_ddf_i, DnnlGemmWrapper::to_dt(), + DnnlGemmWrapper::row_gemm(ctx, row_diff, src1_ncols, ne10, src0_ddf_i, + DnnlGemmWrapper::to_dt(), src1_ddf1_i, DnnlGemmWrapper::to_dt(), dst_dd_i, DnnlGemmWrapper::to_dt(), stream); } else @@ -2373,10 +2238,10 @@ static void ggml_sycl_set_peer_access(co peer_access_enabled = enable_peer_access; } +template