diff -pruN 2.6+dfsg-1/bl1/aarch32/bl1_exceptions.S 2.7.0+dfsg-2/bl1/aarch32/bl1_exceptions.S --- 2.6+dfsg-1/bl1/aarch32/bl1_exceptions.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl1/aarch32/bl1_exceptions.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -118,6 +118,14 @@ func smc_handler mov r0, #DISABLE_DCACHE bl enable_mmu_svc_mon + /* + * Invalidate `smc_ctx_t` in data cache to prevent dirty data being + * used. + */ + mov r0, r6 + mov r1, #SMC_CTX_SIZE + bl inv_dcache_range + /* Enable the data cache. */ ldcopr r9, SCTLR orr r9, r9, #SCTLR_C_BIT diff -pruN 2.6+dfsg-1/bl1/aarch64/bl1_exceptions.S 2.7.0+dfsg-2/bl1/aarch64/bl1_exceptions.S --- 2.6+dfsg-1/bl1/aarch64/bl1_exceptions.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl1/aarch64/bl1_exceptions.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,7 +224,7 @@ smc_handler: * TODO: Revisit to store only SMCCC specified registers. * ----------------------------------------------------- */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* ----------------------------------------------------- diff -pruN 2.6+dfsg-1/bl1/bl1_main.c 2.7.0+dfsg-2/bl1/bl1_main.c --- 2.6+dfsg-1/bl1/bl1_main.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl1/bl1_main.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -121,10 +122,10 @@ void bl1_main(void) /* Perform remaining generic architectural setup from EL3 */ bl1_arch_setup(); -#if TRUSTED_BOARD_BOOT + crypto_mod_init(); + /* Initialize authentication module */ auth_mod_init(); -#endif /* TRUSTED_BOARD_BOOT */ /* Initialize the measured boot */ bl1_plat_mboot_init(); diff -pruN 2.6+dfsg-1/bl2/bl2_el3.ld.S 2.7.0+dfsg-2/bl2/bl2_el3.ld.S --- 2.6+dfsg-1/bl2/bl2_el3.ld.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl2/bl2_el3.ld.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,11 @@ MEMORY { #else RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE #endif +#if SEPARATE_BL2_NOLOAD_REGION + RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START +#else +#define RAM_NOLOAD RAM +#endif } #if !BL2_IN_XIP_MEM @@ -106,9 +111,18 @@ SECTIONS __DATA_RAM_END__ = __DATA_END__; RELA_SECTION >RAM - STACK_SECTION >RAM - BSS_SECTION >RAM - XLAT_TABLE_SECTION >RAM +#if SEPARATE_BL2_NOLOAD_REGION + SAVED_ADDR = .; + . = BL2_NOLOAD_START; + __BL2_NOLOAD_START__ = .; +#endif + STACK_SECTION >RAM_NOLOAD + BSS_SECTION >RAM_NOLOAD + XLAT_TABLE_SECTION >RAM_NOLOAD +#if SEPARATE_BL2_NOLOAD_REGION + __BL2_NOLOAD_END__ = .; + . = SAVED_ADDR; +#endif #if USE_COHERENT_MEM /* diff -pruN 2.6+dfsg-1/bl2/bl2_image_load_v2.c 2.7.0+dfsg-2/bl2/bl2_image_load_v2.c --- 2.6+dfsg-1/bl2/bl2_image_load_v2.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl2/bl2_image_load_v2.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,17 +7,16 @@ #include #include -#include - #include #include +#include "bl2_private.h" #include #include #include #include #include -#include "bl2_private.h" +#include /******************************************************************************* * This function loads SCP_BL2/BL3x images and returns the ep_info for @@ -66,16 +65,16 @@ struct entry_point_info *bl2_load_images if ((bl2_node_info->image_info->h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U) { - INFO("BL2: Loading image id %d\n", bl2_node_info->image_id); + INFO("BL2: Loading image id %u\n", bl2_node_info->image_id); err = load_auth_image(bl2_node_info->image_id, bl2_node_info->image_info); if (err != 0) { - ERROR("BL2: Failed to load image id %d (%i)\n", + ERROR("BL2: Failed to load image id %u (%i)\n", bl2_node_info->image_id, err); plat_error_handler(err); } } else { - INFO("BL2: Skip loading image id %d\n", bl2_node_info->image_id); + INFO("BL2: Skip loading image id %u\n", bl2_node_info->image_id); } /* Allow platform to handle image information. */ diff -pruN 2.6+dfsg-1/bl2/bl2_main.c 2.7.0+dfsg-2/bl2/bl2_main.c --- 2.6+dfsg-1/bl2/bl2_main.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl2/bl2_main.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -89,10 +90,10 @@ void bl2_main(void) fwu_init(); #endif /* PSA_FWU_SUPPORT */ -#if TRUSTED_BOARD_BOOT + crypto_mod_init(); + /* Initialize authentication module */ auth_mod_init(); -#endif /* TRUSTED_BOARD_BOOT */ /* Initialize the Measured Boot backend */ bl2_plat_mboot_init(); diff -pruN 2.6+dfsg-1/bl31/aarch64/bl31_entrypoint.S 2.7.0+dfsg-2/bl31/aarch64/bl31_entrypoint.S --- 2.6+dfsg-1/bl31/aarch64/bl31_entrypoint.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl31/aarch64/bl31_entrypoint.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,6 +67,7 @@ func bl31_entrypoint _exception_vectors=runtime_exceptions \ _pie_fixup_size=BL31_LIMIT - BL31_BASE +#if !RESET_TO_BL31_WITH_PARAMS /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so * there's no argument to relay from a previous bootloader. Zero the @@ -77,6 +78,7 @@ func bl31_entrypoint mov x21, 0 mov x22, 0 mov x23, 0 +#endif /* RESET_TO_BL31_WITH_PARAMS */ #endif /* RESET_TO_BL31 */ /* -------------------------------------------------------------------- diff -pruN 2.6+dfsg-1/bl31/aarch64/ea_delegate.S 2.7.0+dfsg-2/bl31/aarch64/ea_delegate.S --- 2.6+dfsg-1/bl31/aarch64/ea_delegate.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl31/aarch64/ea_delegate.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -92,8 +92,9 @@ func enter_lower_el_sync_ea * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + * Also set the PSTATE to a known state. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ @@ -139,8 +140,9 @@ handle_lower_el_async_ea: * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + * Also set the PSTATE to a known state. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ diff -pruN 2.6+dfsg-1/bl31/aarch64/runtime_exceptions.S 2.7.0+dfsg-2/bl31/aarch64/runtime_exceptions.S --- 2.6+dfsg-1/bl31/aarch64/runtime_exceptions.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl31/aarch64/runtime_exceptions.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,8 +71,9 @@ * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + * Also set the PSTATE to a known state. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry bl handle_lower_el_ea_esb @@ -209,8 +210,9 @@ exp_from_EL3: * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + * Also set the PSTATE to a known state. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ @@ -462,8 +464,9 @@ smc_handler64: * Save general purpose and ARMv8.3-PAuth registers (if enabled). * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. + * Also set the PSTATE to a known state. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ diff -pruN 2.6+dfsg-1/bl31/bl31_main.c 2.7.0+dfsg-2/bl31/bl31_main.c --- 2.6+dfsg-1/bl31/bl31_main.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl31/bl31_main.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,11 @@ void bl31_main(void) NOTICE("BL31: %s\n", version_string); NOTICE("BL31: %s\n", build_message); +#if FEATURE_DETECTION + /* Detect if features enabled during compilation are supported by PE. */ + detect_arch_features(); +#endif /* FEATURE_DETECTION */ + #ifdef SUPPORT_UNKNOWN_MPID if (unsupported_mpid_flag == 0) { NOTICE("Unsupported MPID detected!\n"); @@ -253,7 +259,16 @@ void __init bl31_prepare_next_image_entr (image_type == SECURE) ? "secure" : "normal"); print_entry_point_info(next_image_info); cm_init_my_context(next_image_info); - cm_prepare_el3_exit(image_type); + + /* + * If we are entering the Non-secure world, use + * 'cm_prepare_el3_exit_ns' to exit. + */ + if (image_type == NON_SECURE) { + cm_prepare_el3_exit_ns(); + } else { + cm_prepare_el3_exit(image_type); + } } /******************************************************************************* diff -pruN 2.6+dfsg-1/bl31/bl31.mk 2.7.0+dfsg-2/bl31/bl31.mk --- 2.6+dfsg-1/bl31/bl31.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl31/bl31.mk 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -18,12 +18,21 @@ ifeq (${SPM_MM},1) $(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support) else $(info Including SPM Management Mode (MM) makefile) - include services/std_svc/spm_mm/spm_mm.mk + include services/std_svc/spm/common/spm.mk + include services/std_svc/spm/spm_mm/spm_mm.mk endif endif include lib/extensions/amu/amu.mk include lib/mpmm/mpmm.mk + +ifeq (${SPMC_AT_EL3},1) + $(warning "EL3 SPMC is an experimental feature") + $(info Including EL3 SPMC makefile) + include services/std_svc/spm/common/spm.mk + include services/std_svc/spm/el3_spmc/spmc.mk +endif + include lib/psci/psci_lib.mk BL31_SOURCES += bl31/bl31_main.c \ @@ -40,6 +49,8 @@ BL31_SOURCES += bl31/bl31_main.c \ services/std_svc/std_svc_setup.c \ ${PSCI_LIB_SOURCES} \ ${SPMD_SOURCES} \ + ${SPM_MM_SOURCES} \ + ${SPMC_SOURCES} \ ${SPM_SOURCES} ifeq (${DISABLE_MTPMU},1) @@ -104,6 +115,10 @@ ifeq (${ENABLE_TRBE_FOR_NS},1) BL31_SOURCES += lib/extensions/trbe/trbe.c endif +ifeq (${ENABLE_BRBE_FOR_NS},1) +BL31_SOURCES += lib/extensions/brbe/brbe.c +endif + ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1) BL31_SOURCES += lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c endif @@ -128,6 +143,10 @@ BL31_SOURCES += ${GPT_LIB_SRCS} \ ${RMMD_SOURCES} endif +ifeq ($(FEATURE_DETECTION),1) +BL31_SOURCES += common/feat_detect.c +endif + BL31_LINKERFILE := bl31/bl31.ld.S # Flag used to indicate if Crash reporting via console should be included diff -pruN 2.6+dfsg-1/bl32/sp_min/sp_min.mk 2.7.0+dfsg-2/bl32/sp_min/sp_min.mk --- 2.6+dfsg-1/bl32/sp_min/sp_min.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl32/sp_min/sp_min.mk 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -35,6 +35,10 @@ endif ifeq (${WORKAROUND_CVE_2017_5715},1) BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_bpiall.S \ bl32/sp_min/wa_cve_2017_5715_icache_inv.S +else +ifeq (${WORKAROUND_CVE_2022_23960},1) +BL32_SOURCES += bl32/sp_min/wa_cve_2017_5715_icache_inv.S +endif endif ifeq (${TRNG_SUPPORT},1) diff -pruN 2.6+dfsg-1/bl32/tsp/tsp_main.c 2.7.0+dfsg-2/bl32/tsp/tsp_main.c --- 2.6+dfsg-1/bl32/tsp/tsp_main.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/bl32/tsp/tsp_main.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -370,6 +370,7 @@ tsp_args_t *tsp_smc_handler(uint64_t fun uint64_t service_arg1; uint64_t results[2]; uint32_t linear_id = plat_my_core_pos(); + u_register_t dit; /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; @@ -424,6 +425,23 @@ tsp_args_t *tsp_smc_handler(uint64_t fun results[0] /= service_arg0 ? service_arg0 : 1; results[1] /= service_arg1 ? service_arg1 : 1; break; + case TSP_CHECK_DIT: + if (!is_armv8_4_dit_present()) { +#if LOG_LEVEL >= LOG_LEVEL_ERROR + spin_lock(&console_lock); + ERROR("DIT not supported\n"); + spin_unlock(&console_lock); +#endif + results[0] = 0; + results[1] = 0xffff; + break; + } + dit = read_dit(); + results[0] = dit == service_arg0; + results[1] = dit; + /* Toggle the dit bit */ + write_dit(service_arg0 != 0U ? 0 : DIT_BIT); + break; default: break; } diff -pruN 2.6+dfsg-1/changelog.yaml 2.7.0+dfsg-2/changelog.yaml --- 2.6+dfsg-1/changelog.yaml 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/changelog.yaml 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,1140 @@ +# +# Copyright (c) 2021-2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# +# The following block describes the top-level sections of the changelog. Commits are categorized +# into these top-level sections based on the commit message "type": +# +# feat(xyz): add the xyz feature +# ^^^^ +# + +sections: + - title: New Features + description: A new feature + type: feat + + - title: Resolved Issues + description: A bug fix + type: fix + + - title: Build System + description: Changes that affect the build system or external dependencies + type: build + hidden: true + + - title: Continuous Integration + description: Changes to our CI configuration files and scripts + type: ci + hidden: true + + - title: Build System + description: Documentation-only changes + type: docs + hidden: true + + - title: Performance Improvements + description: A code change that improves performance + type: perf + hidden: true + + - title: Code Refactoring + description: A code change that neither fixes a bug nor adds a feature + type: refactor + hidden: true + + - title: Reverted Changes + description: Changes that revert a previous change + type: revert + hidden: true + + - title: Style + description: Changes that do not affect the meaning of the code (white-space, formatting, missing semi-colons, etc.) + type: style + hidden: true + + - title: Tests + description: Adding missing tests or correcting existing tests + type: test + hidden: true + + - title: Miscellaneous + description: Any other change + type: chore + hidden: true + +# +# The following block describes the sub-sections of the changelog. These sub-sections may appear in +# any of the top-level sections, and describe the individual components that a change may relate to. +# +# Sub-sections have an optional associated commit message "scope": +# +# feat(xyz): add the xyz feature +# ^^^ +# +# This file also describes deprecated scopes, which are scopes that were used before we introduced +# scope enforcement. These will not pass CI checks when used, but they will be used to generate the +# changelog. +# +# Please note that new scopes should be kebab-case: https://en.wiktionary.org/wiki/kebab_case +# + +subsections: + - title: Architecture + + subsections: + - title: Activity Monitors Extension (FEAT_AMU) + scope: amu + + - title: Support for the `HCRX_EL2` register (FEAT_HCX) + scope: hcx + + - title: Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM) + scope: mpam + + - title: Scalable Matrix Extension (FEAT_SME) + scope: sme + + - title: Scalable Vector Extension (FEAT_SVE) + scope: sve + + - title: System Register Trace Extensions (FEAT_ETMv4, FEAT_ETE and FEAT_ETEv1.1) + scope: sys-reg-trace + + deprecated: + - sys_reg_trace + + - title: Trace Buffer Extension (FEAT_TRBE) + scope: trbe + + - title: Self-hosted Trace Extensions (FEAT_TRF) + scope: trf + + - title: Statistical profiling Extension (FEAT_SPE) + scope: spe + + - title: Branch Record Buffer Extension (FEAT_BRBE) + scope: brbe + + - title: Extended Cache Index (FEAT_CCIDX) + scope: ccidx + + - title: Platforms + + subsections: + - title: Allwinner + scope: allwinner + + deprecated: + - plat/allwinner + + - title: Arm + scope: arm + + deprecated: + - plat/arm + + subsections: + - title: FPGA + scope: fpga + + deprecated: + - arm_fgpa + - arm_fpga + - plat/arm_fpga + + - title: FVP + scope: fvp + + deprecated: + - plat/fvp + + - title: FVP-R + scope: fvp-r + + deprecated: + - fvp_r + + - title: Juno + scope: juno + + - title: Morello + scope: morello + + - title: N1SDP + scope: n1sdp + + - title: RD + scope: rd + + subsections: + - title: RD-N2 + scope: rdn2 + + deprecated: + - board/rdn2 + + - title: SGI + scope: sgi + + deprecated: + - plat/sgi + - plat/arm/sgi + + - title: TC + scope: tc + + subsections: + - title: TC0 + scope: tc0 + + deprecated: + - plat/tc0 + + - title: Corstone-1000 + scope: corstone-1000 + + - title: Broadcom + scope: brcm + + - title: Intel + scope: intel + + subsections: + - title: SoC + scope: soc + + - title: Marvell + scope: marvell + + deprecated: + - plat/marvell + + subsections: + - title: Armada + scope: armada + + deprecated: + - plat/marvell/armada + + subsections: + - title: A3K + scope: a3k + + deprecated: + - plat/marvell/a3k + + - title: A8K + scope: a8k + + deprecated: + - plat/marvell/a8k + + - title: MediaTek + scope: mediatek + + deprecated: + - plat/mediatek/common + - plat/mediatek + + subsections: + - title: MT8183 + scope: mt8183 + + deprecated: + - plat/mediatek/mt8183 + + - title: MT8192 + scope: mt8192 + + deprecated: + - plat/mdeiatek/mt8192 + + - title: MT8195 + scope: mt8195 + + deprecated: + - plat/mediatek/me8195 + - plat/mediatek/mt8195 + - plat/mdeiatek/mt8195 + + - title: MT8186 + scope: mt8186 + + deprecated: + - plat/mediatek/mt8186 + + - title: NVIDIA + scope: nvidia + + subsections: + - title: Tegra + scope: tegra + + deprecated: + - plat/tegra + + subsections: + - title: Tegra 132 + scope: tegra132 + + - title: Tegra 194 + scope: tegra194 + + - title: NXP + scope: nxp + + deprecated: + - plat/nxp + - plat/nxp/common + + subsections: + - title: i.MX + scope: imx + + deprecated: + - plat/imx + - plat/imx/imx + + subsections: + - title: i.MX 8M + scope: imx8m + + deprecated: + - plat/imx8m + - plat/imx/imx8m + + subsections: + - title: i.MX 8M Nano + scope: imx8mn + + deprecated: + - plat/imx/imx8m/imx8mn + + - title: i.MX 8M Mini + scope: imx8mm + + deprecated: + - plat/imx/imx8m/imx8mm + + - title: i.MX 8M Plus + scope: imx8mp + + deprecated: + - plat/imx/imx8m/imx8mp + + - title: i.MX 8Q + scope: imx8mq + + deprecated: + - plat/imx/imx8m/imx8mq + + - title: Layerscape + scope: layerscape + + deprecated: + - docs/nxp/layerscape + + subsections: + - title: LS1028A + scope: ls1028a + + deprecated: + - plat/nxp/ls1028a + + subsections: + - title: LS1028ARDB + scope: ls1028ardb + + deprecated: + - plat/nxp/ls1028ardb + + - title: LS1043A + scope: ls1043a + + deprecated: + - plat/nxp/ls1043a + + subsections: + - title: LS1043ARDB + scope: ls1043ardb + + deprecated: + - plat/nxp/ls1043ardb + + - title: LX2 + scope: lx2 + + deprecated: + - plat/nxp/lx2 + + subsections: + - title: LX216 + scope: lx216 + + deprecated: + - plat/nxp/lx216x + + subsections: + - title: LX2160 + scope: lx2160 + + deprecated: + - plat/soc-lx2160 + + - title: LS1046A + scope: ls1046a + + subsections: + - title: LS1046ARDB + scope: ls1046ardb + + - title: LS1046AFRWY + scope: ls1046afrwy + + - title: LS1046AQDS + scope: ls1046aqds + + - title: LS1088A + scope: ls1088a + + subsections: + - title: LS1088ARDB + scope: ls1088ardb + + - title: LS1088AQDS + scope: ls1088aqds + + - title: QEMU + scope: qemu + + deprecated: + - plat/qemu + + - title: QTI + scope: qti + + subsections: + - title: SC1780 + scope: sc7180 + + deprecated: + - plat/qti/sc7180 + + - title: SC7280 + scope: sc7280 + + deprecated: + - plat/qti/sc7280 + + - title: MSM8916 + scope: msm8916 + + - title: Raspberry Pi + scope: rpi + + subsections: + - title: Raspberry Pi 4 + scope: rpi4 + + - title: Renesas + scope: renesas + + subsections: + - title: R-Car + scope: rcar + + deprecated: + - plat/rcar + + subsections: + - title: R-Car 3 + scope: rcar3 + + deprecated: + - plat/rcar3 + + - title: Rockchip + scope: rockchip + + subsections: + - title: RK3399 + scope: rk3399 + + deprecated: + - rockchip/rk3399 + - rk3399/suspend + + - title: Socionext + scope: socionext + + subsections: + - title: Synquacer + scope: synquacer + + deprecated: + - plat/synquacer + + - title: ST + scope: st + + deprecated: + - plat/st + + subsections: + - title: ST32MP1 + scope: stm32mp1 + + deprecated: + - plat/st/stm32mp1 + + - title: Texas Instruments + scope: ti + + subsections: + - title: K3 + scope: k3 + + - title: Xilinx + scope: xilinx + + deprecated: + - plat/xilinx + + subsections: + - title: Versal + scope: versal + + deprecated: + - plat/xilinx/versal/include + - plat/xilinx/versal + - plat/versal + + - title: ZynqMP + scope: zynqmp + + deprecated: + - plat/zynqmp + - plat/xilinx/zynqmp + + - title: Bootloader Images + scope: bl + + deprecated: + - bl_common + + subsections: + - title: BL1 + scope: bl1 + + - title: BL2 + scope: bl2 + + - title: BL31 + scope: bl31 + + - title: Services + scope: services + + subsections: + - title: FF-A + scope: ff-a + + deprecated: + - ffa + + - title: RME + scope: rme + + subsections: + - title: TRP + scope: trp + + - title: SPM + scope: spm + + subsections: + - title: EL3 SPMC + scope: el3-spmc + + - title: SPMD + scope: spmd + + - title: SPM MM + scope: spm-mm + + - title: Libraries + + subsections: + - title: CPU Support + scope: cpus + + deprecated: + - cpu + - errata + - errata_report + + - title: EL3 Runtime + scope: el3-runtime + + deprecated: + - el3_runtime + + subsections: + - title: Context Management + scope: cm + + - title: FCONF + scope: fconf + + - title: MPMM + scope: mpmm + + - title: OP-TEE + scope: optee + + deprecated: + - lib/optee + + - title: PSCI + scope: psci + + - title: GPT + scope: gpt + + deprecated: + - gpt_rme + + - title: SMCCC + scope: smccc + + - title: Translation Tables + scope: xlat + + - title: C Standard Library + scope: libc + + - title: Locks + scope: locks + + - title: PSA + scope: psa + + - title: Drivers + + subsections: + - title: Authentication + scope: auth + + deprecated: + - driver/auth + + subsections: + - title: CryptoCell-713 + scope: cc-713 + + - title: Generic Clock + scope: clk + + - title: FWU + scope: fwu + + deprecated: + - fwu_metadata + + - title: I/O + scope: io + + subsections: + - title: MTD + scope: mtd + + deprecated: + - io_mtd + + - title: Measured Boot + scope: measured-boot + + deprecated: + - measured boot + - measured_boot + + - title: MMC + scope: mmc + + deprecated: + - drivers/mmc + + - title: MTD + scope: mtd + + deprecated: + - drivers/mtd + + subsections: + - title: NAND + scope: nand + + subsections: + - title: SPI NAND + scope: spi-nand + + deprecated: + - spi_nand + + - title: GUID Partition Tables Support + scope: guid-partition + + - title: SCMI + scope: scmi + + deprecated: + - scmi_common + - drivers/scmi-msg + + - title: UFS + scope: ufs + + - title: Arm + scope: arm-drivers + + subsections: + - title: Ethos-N + scope: ethos-n + + deprecated: + - drivers/arm/ethosn + + - title: GIC + scope: gic + + subsections: + - title: GICv3 + scope: gicv3 + + subsections: + - title: GIC-600AE + scope: gic600ae + + - title: SMMU + scope: smmu + + - title: MHU + scope: mhu + + deprecated: + - drivers/arm/mhu + + - title: RSS + scope: rss + + deprecated: + - drivers/arm/rss + + - title: TZC + scope: tzc + + subsections: + - title: TZC-400 + scope: tzc400 + + deprecated: + - drivers/tzc400 + + - title: TZC-380 + scope: tzc380 + + deprecated: + - drivers/tzc380 + + - title: Marvell + scope: marvell-drivers + + subsections: + - title: COMPHY + scope: marvell-comphy + + deprecated: + - drivers/marvell/comphy + + subsections: + - title: Armada 3700 + scope: marvell-comphy-3700 + + deprecated: + - drivers/marvell/comphy-3700 + + - title: CP110 + scope: marvell-comphy-cp110 + + deprecated: + - drivers/marvell/comphy-cp110 + + - title: UART + scope: marvell-uart + + deprecated: + - plat/marvell/uart + + - title: Armada + scope: armada-drivers + + subsections: + - title: A3K + scope: a3k-drivers + + subsections: + - title: A3720 + scope: a3720-uart + + deprecated: + - plat/marvell/a3720/uart + + - title: MediaTek + scope: mediatek-drivers + + subsections: + - title: APU + scope: mediatek-apu + + deprecated: + - plat/mediatek/apu + + - title: EMI MPU + scope: mediatek-emi-mpu + + deprecated: + - plat/mediatek/mpu + + - title: PMIC Wrapper + scope: mediatek-pmic-wrapper + + deprecated: + - plat/mediatek/pmic_wrap + + - title: MT8192 + scope: mt8192-drivers + + subsections: + - title: SPM + scope: mt8192-spm + + deprecated: + - mediatek/mt8192/spm + + - title: NXP + scope: nxp-drivers + + subsections: + - title: DCFG + scope: nxp-dcfg + + deprecated: + - driver/nxp/dcfg + + - title: FLEXSPI + scope: flexspi + + deprecated: + - include/drivers/flexspi + - driver/nxp/xspi + + - title: SCFG + scope: nxp-scfg + + deprecated: + - nxp/scfg + + - title: SFP + scope: nxp-sfp + + deprecated: + - drivers/nxp/sfp + + - title: QSPI + scope: nxp-qspi + + - title: NXP Crypto + scope: nxp-crypto + + - title: DDR + scope: nxp-ddr + + - title: GIC + scope: nxp-gic + + - title: CSU + scope: nxp-csu + + - title: IFC NAND + scope: nxp-ifc-nand + + - title: IFC NOR + scope: nxp-ifc-nor + + - title: TZC-380 + scope: nxp-tzc380 + + - title: Renesas + scope: renesas-drivers + + subsections: + - title: R-Car3 + scope: rcar3-drivers + + deprecated: + - drivers/rcar3 + + - title: ST + scope: st-drivers + + deprecated: + - drivers/st + + subsections: + - title: BSEC + scope: st-bsec + + - title: Clock + scope: st-clock + + deprecated: + - stm32mp_clk + - drivers/st/clk + - stm32mp1_clk + + - title: Crypto + scope: st-crypto + + - title: DDR + scope: st-ddr + + - title: I/O + scope: st-io-drivers + + subsections: + - title: STM32 Image + scope: st-io-stm32image + + deprecated: + - io-stm32image + - io_stm32image + + - title: I2C + scope: st-i2c + + - title: FMC + scope: st-fmc + + - title: GPIO + scope: st-gpio + + - title: SDMMC2 + scope: st-sdmmc2 + + deprecated: + - stm32_sdmmc2 + + - title: ST PMIC + scope: st-pmic + + deprecated: + - drivers/st/pmic + + - title: STPMIC1 + scope: stpmic1 + + - title: Regulator + scope: st-regulator + + - title: Reset + scope: st-reset + + - title: SPI + scope: st-spi + + - title: UART + scope: st-uart + + subsections: + - title: STM32 Console + scope: stm32-console + + deprecated: + - stm32_console + + - title: USB + scope: st-usb + + deprecated: + - drivers/st/usb + + - title: Watchdog + scope: st-iwdg + + - title: USB + scope: usb + + deprecated: + - drivers/usb + + - title: Miscellaneous + + subsections: + - title: AArch64 + scope: aarch64 + + - title: Debug + scope: debug + + deprecated: + - common/debug + + - title: CRC32 + scope: crc32 + + subsections: + - title: Hardware CRC32 + scope: hw-crc32 + + deprecated: + - hw_crc + - hw_crc32 + + - title: Software CRC32 + scope: sw-crc32 + + deprecated: + - sw_crc32 + + - title: DT Bindings + scope: dt-bindings + + - title: FDT Wrappers + scope: fdt-wrappers + + - title: FDTs + scope: fdts + + deprecated: + - fdt + + subsections: + - title: Morello + scope: morello-fdts + + deprecated: + - fdts/morello + + - title: STM32MP1 + scope: stm32mp1-fdts + + deprecated: + - fdts stm32mp1 + + - title: PIE + scope: pie + + - title: Security + scope: security + + - title: SDEI + scope: sdei + + - title: TBBR + scope: tbbr + + - title: NXP + + subsections: + - title: OCRAM + scope: nxp-ocram + + deprecated: + - nxp/common/ocram + + - title: PSCI + scope: nxp-psci + + deprecated: + - plat/nxp/common/psci + + - title: Documentation + scope: docs + + deprecated: + - doc + + subsections: + - title: Changelog + scope: changelog + + - title: Commit Style + scope: commit-style + + - title: Contribution Guidelines + scope: contributing + + deprecated: + - contribution-guidelines + - docs-contributing.rst + + - title: Maintainers + scope: maintainers + + - title: Prerequisites + scope: prerequisites + + - title: Threat Model + scope: threat-model + + - title: Build System + scope: build + + deprecated: + - makefile + - Makefile + + subsections: + - title: Git Hooks + scope: hooks + + - title: Tools + + subsections: + - title: STM32 Image + scope: stm32image + + deprecated: + - tools/stm32image + + - title: NXP Tools + scope: nxp-tools + + - title: Firmware Image Package Tool + scope: fiptool + + - title: Secure Partition Tool + scope: sptool + + - title: Certificate Creation Tool + scope: cert-create + + - title: Dependencies + scope: deps + + subsections: + - title: checkpatch + scope: checkpatch + + - title: commitlint + scope: commitlint + + - title: libfdt + scope: libfdt + + - title: Node Package Manager (NPM) + scope: npm diff -pruN 2.6+dfsg-1/.commitlintrc.js 2.7.0+dfsg-2/.commitlintrc.js --- 2.6+dfsg-1/.commitlintrc.js 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/.commitlintrc.js 2022-06-01 15:02:46.000000000 +0000 @@ -8,26 +8,44 @@ "use strict"; -const cz = require("./.cz.json"); +const fs = require("fs"); +const yaml = require("js-yaml"); + const { "trailer-exists": trailerExists } = require("@commitlint/rules").default; /* - * Recursively fetch the project's supported scopes from the Commitizen configuration file. We use - * permit only the blessed scope for each section to encourage developers to use a consistent scope - * scheme. + * The types and scopes accepted by both Commitlint and Commitizen are defined by the changelog + * configuration file - `changelog.yaml` - as they decide which section of the changelog commits + * with a given type and scope are placed in. */ -function getScopes(sections) { - return sections.flatMap(section => { - const scopes = section.scopes; - const subscopes = getScopes(section.sections || []); - const scope = scopes ? [ scopes[0] ] : []; /* Only use the blessed scope */ +let changelog; + +try { + const contents = fs.readFileSync("changelog.yaml", "utf8"); + + changelog = yaml.load(contents); +} catch (err) { + console.log(err); + + throw err; +} + +function getTypes(sections) { + return sections.map(section => section.type) +} + +function getScopes(subsections) { + return subsections.flatMap(subsection => { + const scope = subsection.scope ? [ subsection.scope ] : []; + const subscopes = getScopes(subsection.subsections || []); return scope.concat(subscopes); }) }; -const scopes = getScopes(cz.sections); /* Contains every blessed scope */ +const types = getTypes(changelog.sections).sort(); /* Sort alphabetically */ +const scopes = getScopes(changelog.subsections).sort(); /* Sort alphabetically */ module.exports = { extends: ["@commitlint/config-conventional"], @@ -40,13 +58,16 @@ module.exports = { }, ], rules: { - "body-max-line-length": [1, "always", cz.maxLineWidth], /* Warning */ - "header-max-length": [1, "always", cz.maxHeaderWidth], /* Warning */ + "header-max-length": [1, "always", 50], /* Warning */ + "body-max-line-length": [1, "always", 72], /* Warning */ "change-id-exists": [1, "always", "Change-Id:"], /* Warning */ "signed-off-by-exists": [1, "always", "Signed-off-by:"], /* Warning */ - "scope-case": [2, "always", "kebab-case"], /* Error */ + "type-case": [2, "always", "lower-case" ], /* Error */ + "type-enum": [2, "always", types], /* Error */ + + "scope-case": [2, "always", "lower-case"], /* Error */ "scope-enum": [1, "always", scopes] /* Warning */ }, }; diff -pruN 2.6+dfsg-1/common/bl_common.c 2.7.0+dfsg-2/common/bl_common.c --- 2.6+dfsg-1/common/bl_common.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/common/bl_common.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -143,25 +143,6 @@ exit: return io_result; } -/* - * Load an image and flush it out to main memory so that it can be executed - * later by any CPU, regardless of cache and MMU state. - */ -static int load_image_flush(unsigned int image_id, - image_info_t *image_data) -{ - int rc; - - rc = load_image(image_id, image_data); - if (rc == 0) { - flush_dcache_range(image_data->image_base, - image_data->image_size); - } - - return rc; -} - - #if TRUSTED_BOARD_BOOT /* * This function uses recursion to authenticate the parent images up to the root @@ -202,30 +183,6 @@ static int load_auth_image_recursive(uns return -EAUTH; } - if (is_parent_image == 0) { - /* - * Measure the image. - * We do not measure its parents because these only play a role - * in authentication, which is orthogonal to measured boot. - * - * TODO: Change this code if we change our minds about measuring - * certificates. - */ - rc = plat_mboot_measure_image(image_id, image_data); - if (rc != 0) { - return rc; - } - - /* - * Flush the image to main memory so that it can be executed - * later by any CPU, regardless of cache and MMU state. This - * is only needed for child images, not for the parents - * (certificates). - */ - flush_dcache_range(image_data->image_base, - image_data->image_size); - } - return 0; } #endif /* TRUSTED_BOARD_BOOT */ @@ -239,7 +196,7 @@ static int load_auth_image_internal(unsi } #endif - return load_image_flush(image_id, image_data); + return load_image(image_id, image_data); } /******************************************************************************* @@ -266,6 +223,25 @@ int load_auth_image(unsigned int image_i } while ((err != 0) && (plat_try_next_boot_source() != 0)); #endif /* PSA_FWU_SUPPORT */ + if (err == 0) { + /* + * If loading of the image gets passed (along with its + * authentication in case of Trusted-Boot flow) then measure + * it (if MEASURED_BOOT flag is enabled). + */ + err = plat_mboot_measure_image(image_id, image_data); + if (err != 0) { + return err; + } + + /* + * Flush the image to main memory so that it can be executed + * later by any CPU, regardless of cache and MMU state. + */ + flush_dcache_range(image_data->image_base, + image_data->image_size); + } + return err; } diff -pruN 2.6+dfsg-1/common/fdt_fixup.c 2.7.0+dfsg-2/common/fdt_fixup.c --- 2.6+dfsg-1/common/fdt_fixup.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/common/fdt_fixup.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -394,6 +394,110 @@ int fdt_add_cpus_node(void *dtb, unsigne return offs; } +/******************************************************************************* + * fdt_add_cpu_idle_states() - add PSCI CPU idle states to cpu nodes in the DT + * @dtb: pointer to the device tree blob in memory + * @states: array of idle state descriptions, ending with empty element + * + * Add information about CPU idle states to the devicetree. This function + * assumes that CPU idle states are not already present in the devicetree, and + * that all CPU states are equally applicable to all CPUs. + * + * See arm/idle-states.yaml and arm/psci.yaml in the (Linux kernel) DT binding + * documentation for more details. + * + * Return: 0 on success, a negative error value otherwise. + ******************************************************************************/ +int fdt_add_cpu_idle_states(void *dtb, const struct psci_cpu_idle_state *state) +{ + int cpu_node, cpus_node, idle_states_node, ret; + uint32_t count, phandle; + + ret = fdt_find_max_phandle(dtb, &phandle); + phandle++; + if (ret < 0) { + return ret; + } + + cpus_node = fdt_path_offset(dtb, "/cpus"); + if (cpus_node < 0) { + return cpus_node; + } + + /* Create the idle-states node and its child nodes. */ + idle_states_node = fdt_add_subnode(dtb, cpus_node, "idle-states"); + if (idle_states_node < 0) { + return idle_states_node; + } + + ret = fdt_setprop_string(dtb, idle_states_node, "entry-method", "psci"); + if (ret < 0) { + return ret; + } + + for (count = 0U; state->name != NULL; count++, phandle++, state++) { + int idle_state_node; + + idle_state_node = fdt_add_subnode(dtb, idle_states_node, + state->name); + if (idle_state_node < 0) { + return idle_state_node; + } + + fdt_setprop_string(dtb, idle_state_node, "compatible", + "arm,idle-state"); + fdt_setprop_u32(dtb, idle_state_node, "arm,psci-suspend-param", + state->power_state); + if (state->local_timer_stop) { + fdt_setprop_empty(dtb, idle_state_node, + "local-timer-stop"); + } + fdt_setprop_u32(dtb, idle_state_node, "entry-latency-us", + state->entry_latency_us); + fdt_setprop_u32(dtb, idle_state_node, "exit-latency-us", + state->exit_latency_us); + fdt_setprop_u32(dtb, idle_state_node, "min-residency-us", + state->min_residency_us); + if (state->wakeup_latency_us) { + fdt_setprop_u32(dtb, idle_state_node, + "wakeup-latency-us", + state->wakeup_latency_us); + } + fdt_setprop_u32(dtb, idle_state_node, "phandle", phandle); + } + + if (count == 0U) { + return 0; + } + + /* Link each cpu node to the idle state nodes. */ + fdt_for_each_subnode(cpu_node, dtb, cpus_node) { + const char *device_type; + fdt32_t *value; + + /* Only process child nodes with device_type = "cpu". */ + device_type = fdt_getprop(dtb, cpu_node, "device_type", NULL); + if (device_type == NULL || strcmp(device_type, "cpu") != 0) { + continue; + } + + /* Allocate space for the list of phandles. */ + ret = fdt_setprop_placeholder(dtb, cpu_node, "cpu-idle-states", + count * sizeof(phandle), + (void **)&value); + if (ret < 0) { + return ret; + } + + /* Fill in the phandles of the idle state nodes. */ + for (uint32_t i = 0U; i < count; ++i) { + value[i] = cpu_to_fdt32(phandle - count + i); + } + } + + return 0; +} + /** * fdt_adjust_gic_redist() - Adjust GICv3 redistributor size * @dtb: Pointer to the DT blob in memory diff -pruN 2.6+dfsg-1/common/fdt_wrappers.c 2.7.0+dfsg-2/common/fdt_wrappers.c --- 2.6+dfsg-1/common/fdt_wrappers.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/common/fdt_wrappers.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -618,3 +618,24 @@ int fdtw_for_each_cpu(const void *dtb, return ret; } + +/* + * Find a given node in device tree. If not present, add it. + * Returns offset of node found/added on success, and < 0 on error. + */ +int fdtw_find_or_add_subnode(void *fdt, int parentoffset, const char *name) +{ + int offset; + + offset = fdt_subnode_offset(fdt, parentoffset, name); + + if (offset == -FDT_ERR_NOTFOUND) { + offset = fdt_add_subnode(fdt, parentoffset, name); + } + + if (offset < 0) { + ERROR("%s: %s: %s\n", __func__, name, fdt_strerror(offset)); + } + + return offset; +} diff -pruN 2.6+dfsg-1/common/feat_detect.c 2.7.0+dfsg-2/common/feat_detect.c --- 2.6+dfsg-1/common/feat_detect.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/common/feat_detect.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/******************************************************************************* + * This section lists the wrapper modules for each feature to evaluate the + * feature states (FEAT_STATE_1 and FEAT_STATE_2) and perform necessary action + * as below: + * + * It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not. + * Without this check an exception would occur during context save/restore + * routines, if the feature is enabled but not supported by PE. + ******************************************************************************/ + +/****************************************** + * Feature : FEAT_SB (Speculation Barrier) + *****************************************/ +static void read_feat_sb(void) +{ +#if (ENABLE_FEAT_SB == FEAT_STATE_1) + feat_detect_panic(is_armv8_0_feat_sb_present(), "SB"); +#endif +} + +/****************************************************** + * Feature : FEAT_CSV2_2 (Cache Speculation Variant 2) + *****************************************************/ +static void read_feat_csv2_2(void) +{ +#if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_1) + feat_detect_panic(is_armv8_0_feat_csv2_2_present(), "CSV2_2"); +#endif +} + +/*********************************************** + * Feature : FEAT_PAN (Privileged Access Never) + **********************************************/ +static void read_feat_pan(void) +{ +#if (ENABLE_FEAT_PAN == FEAT_STATE_1) + feat_detect_panic(is_armv8_1_pan_present(), "PAN"); +#endif +} + +/****************************************************** + * Feature : FEAT_VHE (Virtualization Host Extensions) + *****************************************************/ +static void read_feat_vhe(void) +{ +#if (ENABLE_FEAT_VHE == FEAT_STATE_1) + feat_detect_panic(is_armv8_1_vhe_present(), "VHE"); +#endif +} + +/******************************************************************************* + * Feature : FEAT_RAS (Reliability, Availability, and Serviceability Extension) + ******************************************************************************/ +static void read_feat_ras(void) +{ +#if (RAS_EXTENSION == FEAT_STATE_1) + feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS"); +#endif +} + +/************************************************ + * Feature : FEAT_PAUTH (Pointer Authentication) + ***********************************************/ +static void read_feat_pauth(void) +{ +#if (ENABLE_PAUTH == FEAT_STATE_1) || (CTX_INCLUDE_PAUTH_REGS == FEAT_STATE_1) + feat_detect_panic(is_armv8_3_pauth_present(), "PAUTH"); +#endif +} + +/************************************************************ + * Feature : FEAT_DIT (Data Independent Timing Instructions) + ***********************************************************/ +static void read_feat_dit(void) +{ +#if (ENABLE_FEAT_DIT == FEAT_STATE_1) + feat_detect_panic(is_armv8_4_feat_dit_present(), "DIT"); +#endif +} + +/********************************************************* + * Feature : FEAT_AMUv1 (Activity Monitors Extensions v1) + ********************************************************/ +static void read_feat_amuv1(void) +{ +#if (ENABLE_FEAT_AMUv1 == FEAT_STATE_1) + feat_detect_panic(is_armv8_4_feat_amuv1_present(), "AMUv1"); +#endif +} + +/**************************************************************************** + * Feature : FEAT_MPAM (Memory Partitioning and Monitoring (MPAM) Extension) + ***************************************************************************/ +static void read_feat_mpam(void) +{ +#if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_1) + feat_detect_panic(get_mpam_version() != 0U, "MPAM"); +#endif +} + +/************************************************************** + * Feature : FEAT_NV2 (Enhanced Nested Virtualization Support) + *************************************************************/ +static void read_feat_nv2(void) +{ +#if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_1) + unsigned int nv = get_armv8_4_feat_nv_support(); + + feat_detect_panic((nv == ID_AA64MMFR2_EL1_NV2_SUPPORTED), "NV2"); +#endif +} + +/*********************************** + * Feature : FEAT_SEL2 (Secure EL2) + **********************************/ +static void read_feat_sel2(void) +{ +#if (ENABLE_FEAT_SEL2 == FEAT_STATE_1) + feat_detect_panic(is_armv8_4_sel2_present(), "SEL2"); +#endif +} + +/**************************************************** + * Feature : FEAT_TRF (Self-hosted Trace Extensions) + ***************************************************/ +static void read_feat_trf(void) +{ +#if (ENABLE_TRF_FOR_NS == FEAT_STATE_1) + feat_detect_panic(is_arm8_4_feat_trf_present(), "TRF"); +#endif +} + +/************************************************ + * Feature : FEAT_MTE (Memory Tagging Extension) + ***********************************************/ +static void read_feat_mte(void) +{ +#if (CTX_INCLUDE_MTE_REGS == FEAT_STATE_1) + unsigned int mte = get_armv8_5_mte_support(); + + feat_detect_panic((mte != MTE_UNIMPLEMENTED), "MTE"); +#endif +} + +/*********************************************** + * Feature : FEAT_RNG (Random Number Generator) + **********************************************/ +static void read_feat_rng(void) +{ +#if (ENABLE_FEAT_RNG == FEAT_STATE_1) + feat_detect_panic(is_armv8_5_rng_present(), "RNG"); +#endif +} + +/**************************************************** + * Feature : FEAT_BTI (Branch Target Identification) + ***************************************************/ +static void read_feat_bti(void) +{ +#if (ENABLE_BTI == FEAT_STATE_1) + feat_detect_panic(is_armv8_5_bti_present(), "BTI"); +#endif +} + +/**************************************** + * Feature : FEAT_FGT (Fine Grain Traps) + ***************************************/ +static void read_feat_fgt(void) +{ +#if (ENABLE_FEAT_FGT == FEAT_STATE_1) + feat_detect_panic(is_armv8_6_fgt_present(), "FGT"); +#endif +} + +/*********************************************** + * Feature : FEAT_AMUv1p1 (AMU Extensions v1.1) + **********************************************/ +static void read_feat_amuv1p1(void) +{ +#if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_1) + feat_detect_panic(is_armv8_6_feat_amuv1p1_present(), "AMUv1p1"); +#endif +} + +/******************************************************* + * Feature : FEAT_ECV (Enhanced Counter Virtualization) + ******************************************************/ +static void read_feat_ecv(void) +{ +#if (ENABLE_FEAT_ECV == FEAT_STATE_1) + unsigned int ecv = get_armv8_6_ecv_support(); + + feat_detect_panic(((ecv == ID_AA64MMFR0_EL1_ECV_SUPPORTED) || + (ecv == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH)), "ECV"); +#endif +} + +/*********************************************************** + * Feature : FEAT_TWED (Delayed Trapping of WFE Instruction) + **********************************************************/ +static void read_feat_twed(void) +{ +#if (ENABLE_FEAT_TWED == FEAT_STATE_1) + feat_detect_panic(is_armv8_6_twed_present(), "TWED"); +#endif +} + +/****************************************************************** + * Feature : FEAT_HCX (Extended Hypervisor Configuration Register) + *****************************************************************/ +static void read_feat_hcx(void) +{ +#if (ENABLE_FEAT_HCX == FEAT_STATE_1) + feat_detect_panic(is_feat_hcx_present(), "HCX"); +#endif +} + +/************************************************** + * Feature : FEAT_RME (Realm Management Extension) + *************************************************/ +static void read_feat_rme(void) +{ +#if (ENABLE_RME == FEAT_STATE_1) + feat_detect_panic((get_armv9_2_feat_rme_support() != + ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME"); +#endif +} + +/*********************************************************************************** + * TF-A supports many Arm architectural features starting from arch version + * (8.0 till 8.7+). These features are mostly enabled through build flags. This + * mechanism helps in validating these build flags in the early boot phase + * either in BL1 or BL31 depending on the platform and assists in identifying + * and notifying the features which are enabled but not supported by the PE. + * + * It reads all the enabled features ID-registers and ensures the features + * are supported by the PE. + * In case if they aren't it stops booting at an early phase and logs the error + * messages, notifying the platforms about the features that are not supported. + * + * Further the procedure is implemented with a tri-state approach for each feature: + * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time + * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. + * There will be panic if feature is not present at cold boot. + * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime + * depending on hardware capability. + * + * For better readability, state values are defined with macros namely: + * { FEAT_STATE_0, FEAT_STATE_1, FEAT_STATE_2 } taking values as their naming. + **********************************************************************************/ +void detect_arch_features(void) +{ + /* v8.0 features */ + read_feat_sb(); + read_feat_csv2_2(); + + /* v8.1 features */ + read_feat_pan(); + read_feat_vhe(); + + /* v8.2 features */ + read_feat_ras(); + + /* v8.3 features */ + read_feat_pauth(); + + /* v8.4 features */ + read_feat_dit(); + read_feat_amuv1(); + read_feat_mpam(); + read_feat_nv2(); + read_feat_sel2(); + read_feat_trf(); + + /* v8.5 features */ + read_feat_mte(); + read_feat_rng(); + read_feat_bti(); + + /* v8.6 features */ + read_feat_amuv1p1(); + read_feat_fgt(); + read_feat_ecv(); + read_feat_twed(); + + /* v8.7 features */ + read_feat_hcx(); + + /* v9.2 features */ + read_feat_rme(); +} diff -pruN 2.6+dfsg-1/common/uuid.c 2.7.0+dfsg-2/common/uuid.c --- 2.6+dfsg-1/common/uuid.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/common/uuid.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -132,3 +132,27 @@ int read_uuid(uint8_t *dest, char *uuid) return 0; } +/* + * Helper function to check if 2 UUIDs match. + */ +bool uuid_match(uint32_t *uuid1, uint32_t *uuid2) +{ + return !memcmp(uuid1, uuid2, sizeof(uint32_t) * 4); +} + +/* + * Helper function to copy from one UUID struct to another. + */ +void copy_uuid(uint32_t *to_uuid, uint32_t *from_uuid) +{ + to_uuid[0] = from_uuid[0]; + to_uuid[1] = from_uuid[1]; + to_uuid[2] = from_uuid[2]; + to_uuid[3] = from_uuid[3]; +} + +bool is_null_uuid(uint32_t *uuid) +{ + return (uuid[0] == 0 && uuid[1] == 0 && + uuid[2] == 0 && uuid[3] == 0); +} diff -pruN 2.6+dfsg-1/.cz.json 2.7.0+dfsg-2/.cz.json --- 2.6+dfsg-1/.cz.json 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/.cz.json 2022-06-01 15:02:46.000000000 +0000 @@ -1,826 +1,3 @@ { - "path": "./node_modules/cz-conventional-changelog", - "maxHeaderWidth": 50, - "maxLineWidth": 72, - "types": [ - { - "type": "feat", - "title": "New Features", - "description": "A new feature" - }, - { - "type": "fix", - "title": "Resolved Issues", - "description": "A bug fix" - }, - { - "type": "build", - "title": "Build System", - "description": "Changes that affect the build system or external dependencies", - "hidden": true - }, - { - "type": "ci", - "title": "Continuous Integration", - "description": "Changes to our CI configuration files and scripts", - "hidden": true - }, - { - "type": "docs", - "title": "Build System", - "description": "Documentation-only changes", - "hidden": true - }, - { - "type": "perf", - "title": "Performance Improvements", - "description": "A code change that improves performance", - "hidden": true - }, - { - "type": "refactor", - "title": "Code Refactoring", - "description": "A code change that neither fixes a bug nor adds a feature", - "hidden": true - }, - { - "type": "revert", - "title": "Reverted Changes", - "description": "Changes that revert a previous change", - "hidden": true - }, - { - "type": "style", - "title": "Style", - "description": "Changes that do not affect the meaning of the code (white-space, formatting, missing semi-colons, etc.)", - "hidden": true - }, - { - "type": "test", - "title": "Tests", - "description": "Adding missing tests or correcting existing tests", - "hidden": true - }, - { - "type": "chore", - "title": "Miscellaneous", - "description": "Any other change", - "hidden": true - } - ], - "sections": [ - { - "title": "Architecture", - "sections": [ - { - "title": "Activity Monitors Extension (FEAT_AMU)", - "scopes": ["amu"] - }, - { - "title": "Support for the `HCRX_EL2` register (FEAT_HCX)", - "scopes": ["hcx"] - }, - { - "title": "Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)", - "scopes": ["mpam"] - }, - { - "title": "Scalable Matrix Extension (FEAT_SME)", - "scopes": ["sme"] - }, - { - "title": "Scalable Vector Extension (FEAT_SVE)", - "scopes": ["sve"] - }, - { - "title": "Trace Buffer Extension (FEAT_TRBE)", - "scopes": ["trbe"] - }, - { - "title": "Self-hosted Trace Extensions (FEAT_TRF)", - "scopes": ["trf", "sys_reg_trace"] - } - ] - }, - { - "title": "Platforms", - "sections": [ - { - "title": "Allwinner", - "scopes": ["allwinner", "plat/allwinner"] - }, - { - "title": "Arm", - "scopes": ["arm", "plat/arm"], - "sections": [ - { - "title": "FPGA", - "scopes": ["fpga", "arm_fgpa", "arm_fpga", "plat/arm_fpga"] - }, - { - "title": "FVP", - "scopes": ["fvp", "plat/fvp"] - }, - { - "title": "FVP-R", - "scopes": ["fvp-r", "fvp_r"] - }, - { - "title": "Juno", - "scopes": ["juno"] - }, - { - "title": "Morello", - "scopes": ["morello"] - }, - { - "title": "RD", - "scopes": ["rd"], - "sections": [ - { - "title": "RD-N2", - "scopes": ["rdn2", "board/rdn2"] - } - ] - }, - { - "title": "SGI", - "scopes": ["sgi", "plat/sgi", "plat/arm/sgi" ] - }, - { - "title": "TC", - "scopes": ["tc"], - "sections": [ - { - "title": "TC0", - "scopes": ["tc0", "plat/tc0"] - } - ] - } - ] - }, - { - "title": "Marvell", - "scopes": ["marvell", "plat/marvell"], - "sections": [ - { - "title": "Armada", - "scopes": ["armada", "plat/marvell/armada"], - "sections": [ - { - "title": "A3K", - "scopes": ["a3k", "plat/marvell/a3k"] - }, - { - "title": "A8K", - "scopes": ["a8k", "plat/marvell/a8k"] - } - ] - } - ] - }, - { - "title": "MediaTek", - "scopes": ["mediatek", "plat/mediatek/common", "plat/mediatek"], - "sections": [ - { - "title": "MT8183", - "scopes": ["mt8183", "plat/mediatek/mt8183"] - }, - { - "title": "MT8192", - "scopes": ["mt8192", "plat/mdeiatek/mt8192"] - }, - { - "title": "MT8195", - "scopes": ["mt8195", "plat/mediatek/me8195", "plat/mediatek/mt8195", "plat/mdeiatek/mt8195"] - } - ] - }, - { - "title": "NVIDIA", - "scopes": ["nvidia"], - "sections": [ - { - "title": "Tegra", - "scopes": ["tegra", "plat/tegra"], - "sections": [ - { - "title": "Tegra 132", - "scopes": ["tegra132"] - } - ] - } - ] - }, - { - "title": "NXP", - "scopes": ["nxp", "plat/nxp", "plat/nxp/common"], - "sections": [ - { - "title": "i.MX", - "scopes": ["imx", "plat/imx", "plat/imx/imx"], - "sections": [ - { - "title": "i.MX 8M", - "scopes": ["imx8m", "plat/imx8m", "plat/imx/imx8m"], - "sections": [ - { - "title": "i.MX 8M Mini", - "scopes": ["imx8mm", "plat/imx/imx8m/imx8mm"] - }, - { - "title": "i.MX 8M Plus", - "scopes": ["imx8mp", "plat/imx/imx8m/imx8mp"] - } - ] - } - ] - }, - { - "title": "Layerscape", - "scopes": ["layerscape", "docs/nxp/layerscape"], - "sections": [ - { - "title": "LX2", - "scopes": ["lx2", "plat/nxp/lx2"], - "sections": [ - { - "title": "LX216", - "scopes": ["lx216", "plat/nxp/lx216x"], - "sections": [ - { - "title": "LX2160", - "scopes": ["lx2160", "plat/soc-lx2160"] - } - ] - }, - { - "title": "LS1028A", - "scopes": ["ls1028a", "plat/nxp/ls1028a"], - "sections": [ - { - "title": "LS1028ARDB", - "scopes": ["ls1028ardb", "plat/nxp/ls1028ardb"] - } - ] - } - ] - } - ] - } - ] - }, - { - "title": "QEMU", - "scopes": ["qemu", "plat/qemu"] - }, - { - "title": "QTI", - "scopes": ["qti"], - "sections": [ - { - "title": "SC1780", - "scopes": ["sc7180", "plat/qti/sc7180"] - }, - { - "title": "SC7280", - "scopes": ["sc7280", "plat/qti/sc7280"] - } - ] - }, - { - "title": "Raspberry Pi", - "scopes": ["rpi"], - "sections": [ - { - "title": "Raspberry Pi 4", - "scopes": ["rpi4"] - } - ] - }, - { - "title": "Renesas", - "scopes": ["renesas"], - "sections": [ - { - "title": "R-Car", - "scopes": ["rcar", "plat/rcar"], - "sections": [ - { - "title": "R-Car 3", - "scopes": ["rcar3", "plat/rcar3"] - } - ] - } - ] - }, - { - "title": "Rockchip", - "scopes": ["rockchip"], - "sections": [ - { - "title": "RK3399", - "scopes": ["rk3399", "rockchip/rk3399", "rk3399/suspend"] - } - ] - }, - { - "title": "Socionext", - "scopes": ["socionext"], - "sections": [ - { - "title": "Synquacer", - "scopes": ["synquacer", "plat/synquacer"] - } - ] - }, - { - "title": "ST", - "scopes": ["st", "plat/st"], - "sections": [ - { - "title": "ST32MP1", - "scopes": ["stm32mp1", "plat/st/stm32mp1"] - } - ] - }, - { - "title": "Xilinx", - "scopes": ["xilinx", "plat/xilinx"], - "sections": [ - { - "title": "Versal", - "scopes": ["versal", "plat/xilinx/versal/include", "plat/xilinx/versal", "plat/versal"] - }, - { - "title": "ZynqMP", - "scopes": ["zynqmp", "plat/zynqmp", "plat/xilinx/zynqmp"] - } - ] - } - ] - }, - { - "title": "Bootloader Images", - "scopes": ["bl", "bl_common"], - "sections": [ - { - "title": "BL1", - "scopes": ["bl1"] - }, - { - "title": "BL2", - "scopes": ["bl2"] - } - ] - }, - { - "title": "Services", - "scopes": ["services"], - "sections": [ - { - "title": "FF-A", - "scopes": ["ffa", "ff-a"] - }, - { - "title": "RME", - "scopes": ["rme"] - }, - { - "title": "SPM", - "scopes": ["spm", "spmc", "spmd", "SPMD", "spm_mm"] - } - ] - }, - { - "title": "Libraries", - "sections": [ - { - "title": "CPU Support", - "scopes": ["cpus", "cpu", "errata", "errata_report"] - }, - { - "title": "EL3 Runtime", - "scopes": ["el3-runtime", "el3_runtime"] - }, - { - "title": "FCONF", - "scopes": ["fconf"] - }, - { - "title": "MPMM", - "scopes": ["mpmm"] - }, - { - "title": "OP-TEE", - "scopes": ["optee", "lib/optee"] - }, - { - "title": "PSCI", - "scopes": ["psci"] - }, - { - "title": "GPT", - "scopes": ["gpt", "gpt_rme"] - }, - { - "title": "SMCCC", - "scopes": ["smccc"] - }, - { - "title": "Translation Tables", - "scopes": ["xlat"] - } - ] - }, - { - "title": "Drivers", - "sections": [ - { - "title": "Authentication", - "scopes": ["auth", "driver/auth"], - "sections": [ - { - "title": "CryptoCell-713", - "scopes": ["cc-713"] - } - ] - }, - { - "title": "FWU", - "scopes": ["fwu", "fwu_metadata"] - }, - { - "title": "I/O", - "scopes": ["io"], - "sections": [ - { - "title": "MTD", - "scopes": ["mtd", "io_mtd"] - } - ] - }, - { - "title": "Measured Boot", - "scopes": ["measured-boot", "measured boot", "measured_boot"] - }, - { - "title": "MMC", - "scopes": ["mmc", "drivers/mmc"] - }, - { - "title": "MTD", - "scopes": ["mtd", "drivers/mtd"], - "sections": [ - { - "title": "NAND", - "scopes": ["nand"], - "sections": [ - { - "title": "SPI NAND", - "scopes": ["spi-nand", "spi_nand"] - } - ] - } - ] - }, - { - "title": "SCMI", - "scopes": ["scmi", "scmi_common", "drivers/scmi-msg"] - }, - { - "title": "UFS", - "scopes": ["ufs"] - }, - { - "title": "Arm", - "scopes": ["arm-drivers"], - "sections": [ - { - "title": "Ethos-N", - "scopes": ["ethos-n", "drivers/arm/ethosn"] - }, - { - "title": "GIC", - "scopes": ["gic"], - "sections": [ - { - "title": "GICv3", - "scopes": ["gicv3"], - "sections": [ - { - "title": "GIC-600AE", - "scopes": ["gic600ae"] - } - ] - } - ] - }, - { - "title": "TZC", - "scopes": ["tzc"], - "sections": [ - { - "title": "TZC-400", - "scopes": ["tzc400", "drivers/tzc400"] - } - ] - } - ] - }, - { - "title": "Marvell", - "scopes": ["marvell-drivers"], - "sections": [ - { - "title": "COMPHY", - "scopes": ["marvell-comphy", "drivers/marvell/comphy"], - "sections": [ - { - "title": "Armada 3700", - "scopes": ["marvell-comphy-3700", "drivers/marvell/comphy-3700"] - }, - { - "title": "CP110", - "scopes": ["marvell-comphy-cp110", "drivers/marvell/comphy-cp110"] - } - ] - }, - { - "title": "UART", - "scopes": ["marvell-uart", "plat/marvell/uart"] - }, - { - "title": "Armada", - "scopes": ["armada-drivers"], - "sections": [ - { - "title": "A3K", - "scopes": ["a3k-drivers"], - "sections": [ - { - "title": "A3720", - "scopes": ["a3720-uart", "plat/marvell/a3720/uart"] - } - ] - } - ] - } - ] - }, - { - "title": "MediaTek", - "scopes": ["mediatek-drivers"], - "sections": [ - { - "title": "APU", - "scopes": ["mediatek-apu", "plat/mediatek/apu"] - }, - { - "title": "EMI MPU", - "scopes": ["mediatek-emi-mpu", "plat/mediatek/mpu"] - }, - { - "title": "PMIC Wrapper", - "scopes": ["mediatek-pmic-wrapper", "plat/mediatek/pmic_wrap"] - }, - { - "title": "MT8192", - "scopes": ["mt8192-drivers"], - "sections": [ - { - "title": "SPM", - "scopes": ["mt8192-spm", "mediatek/mt8192/spm"] - } - ] - } - ] - }, - { - "title": "NXP", - "scopes": ["nxp-drivers"], - "sections": [ - { - "title": "DCFG", - "scopes": ["nxp-dcfg", "driver/nxp/dcfg"] - }, - { - "title": "FLEXSPI", - "scopes": ["flexspi", "include/drivers/flexspi", "driver/nxp/xspi"] - }, - { - "title": "SCFG", - "scopes": ["nxp-scfg", "nxp/scfg"] - }, - { - "title": "SFP", - "scopes": ["nxp-sfp", "drivers/nxp/sfp"] - } - ] - }, - { - "title": "Renesas", - "scopes": ["renesas-drivers"], - "sections": [ - { - "title": "R-Car3", - "scopes": ["rcar3-drivers", "drivers/rcar3"] - } - ] - }, - { - "title": "ST", - "scopes": ["st-drivers", "drivers/st"], - "sections": [ - { - "title": "Clock", - "scopes": ["st-clock", "stm32mp_clk", "drivers/st/clk", "stm32mp1_clk"] - }, - { - "title": "I/O", - "scopes": ["st-io-drivers"], - "sections": [ - { - "title": "STM32 Image", - "scopes": ["st-io-stm32image", "io-stm32image", "io_stm32image"] - } - ] - }, - { - "title": "SDMMC2", - "scopes": ["st-sdmmc2", "stm32_sdmmc2"] - }, - { - "title": "ST PMIC", - "scopes": ["st-pmic", "drivers/st/pmic"] - }, - { - "title": "STPMIC1", - "scopes": ["stpmic1"] - }, - { - "title": "UART", - "scopes": ["st-uart"], - "sections": [ - { - "title": "STM32 Console", - "scopes": ["stm32-console", "stm32_console"] - } - ] - }, - { - "title": "USB", - "scopes": ["st-usb", "drivers/st/usb"] - } - ] - }, - { - "title": "USB", - "scopes": ["usb", "drivers/usb"] - } - ] - }, - { - "title": "Miscellaneous", - "sections": [ - { - "title": "AArch64", - "scopes": ["aarch64"] - }, - { - "title": "Debug", - "scopes": ["debug", "common/debug"] - }, - { - "title": "CRC32", - "scopes": ["crc32"], - "sections": [ - { - "title": "Hardware CRC32", - "scopes": ["hw-crc32", "hw_crc", "hw_crc32"] - }, - { - "title": "Software CRC32", - "scopes": ["sw-crc32", "sw_crc32"] - } - ] - }, - { - "title": "DT Bindings", - "scopes": ["dt-bindings"] - }, - { - "title": "FDT Wrappers", - "scopes": ["fdt-wrappers"] - }, - { - "title": "FDTs", - "scopes": ["fdts", "fdt"], - "sections": [ - { - "title": "Morello", - "scopes": ["morello-fdts", "fdts/morello"] - }, - { - "title": "STM32MP1", - "scopes": ["stm32mp1-fdts", "fdts stm32mp1"] - } - ] - }, - { - "title": "PIE", - "scopes": ["pie"] - }, - { - "title": "Security", - "scopes": ["security"] - }, - { - "title": "SDEI", - "scopes": ["sdei"] - }, - { - "title": "TBBR", - "scopes": ["tbbr"] - }, - { - "title": "NXP", - "sections": [ - { - "title": "OCRAM", - "scopes": ["nxp-ocram", "nxp/common/ocram"] - }, - { - "title": "PSCI", - "scopes": ["nxp-psci", "plat/nxp/common/psci"] - } - ] - } - ] - }, - { - "title": "Documentation", - "scopes": ["docs", "doc"], - "sections": [ - { - "title": "Changelog", - "scopes": ["changelog"] - }, - { - "title": "Commit Style", - "scopes": ["commit-style"] - }, - { - "title": "Contribution Guidelines", - "scopes": ["contributing", "contribution-guidelines", "docs-contributing.rst"] - }, - { - "title": "Maintainers", - "scopes": ["maintainers"] - }, - { - "title": "Prerequisites", - "scopes": ["prerequisites"] - } - ] - }, - { - "title": "Build System", - "scopes": ["build", "makefile", "Makefile"], - "sections": [ - { - "title": "Git Hooks", - "scopes": ["hooks"] - } - ] - }, - { - "title": "Tools", - "sections": [ - { - "title": "STM32 Image", - "scopes": ["stm32image", "tools/stm32image"] - } - ] - }, - { - "title": "Dependencies", - "scopes": ["deps"], - "sections": [ - { - "title": "checkpatch", - "scopes": ["checkpatch"] - }, - { - "title": "libfdt", - "scopes": ["libfdt"] - }, - { - "title": "Node Package Manager (NPM)", - "scopes": ["npm"] - } - ] - } - ] + "path": "@commitlint/cz-commitlint" } diff -pruN 2.6+dfsg-1/debian/arm-trusted-firmware.lintian-overrides 2.7.0+dfsg-2/debian/arm-trusted-firmware.lintian-overrides --- 2.6+dfsg-1/debian/arm-trusted-firmware.lintian-overrides 2021-09-20 01:37:45.000000000 +0000 +++ 2.7.0+dfsg-2/debian/arm-trusted-firmware.lintian-overrides 2022-08-06 03:27:13.000000000 +0000 @@ -1,5 +1,5 @@ # This is boot firmware that needs to be statically linked. -arm-trusted-firmware binary: statically-linked-binary usr/lib/arm-trusted-firmware/*/bl31.elf +arm-trusted-firmware binary: statically-linked-binary *usr/lib/arm-trusted-firmware/*/bl31.elf* # Intended for U-Boot, not linux. -wrong-section-according-to-package-name arm-trusted-firmware => kernel +arm-trusted-firmware binary: wrong-section-according-to-package-name admin => kernel diff -pruN 2.6+dfsg-1/debian/changelog 2.7.0+dfsg-2/debian/changelog --- 2.6+dfsg-1/debian/changelog 2021-11-27 01:26:17.000000000 +0000 +++ 2.7.0+dfsg-2/debian/changelog 2022-08-06 03:28:37.000000000 +0000 @@ -1,3 +1,34 @@ +arm-trusted-firmware (2.7.0+dfsg-2) unstable; urgency=medium + + * debian/rules: Fix build failure by ignoring warnings for RWX segments. + * debian/rules: Work around gcc-12 bug by passing --param=min-pagesize=0 + in CFLAGS. + * debian/patches: Use LDFLAGS with fiptool and cert_create. + * debian/rules: Enable hardening options. + * Update lintian override for statically-linked-binary. + * Update lintian override for wrong-section-according-to-package-name. + + -- Vagrant Cascadian Fri, 05 Aug 2022 20:28:37 -0700 + +arm-trusted-firmware (2.7.0+dfsg-1) experimental; urgency=medium + + * New upstream release. + + [ Vagrant Cascadian ] + * debian/rules: Add imx8mq platform. + * debian/copyright: Update for 2.7.0. + * debian/control: Update Standards Version to 4.6.1. + + [ Ariel D'Alessandro ] + * d/rules: Enable imx8mn target + * d/rules: Unify build rule for both debug and release platforms + * d/rules: Add imx8mn_uart4 target subplatform + + [ Jelmer Vernooij ] + * Set upstream Repository/Repository-Browse fields. + + -- Vagrant Cascadian Wed, 08 Jun 2022 20:58:51 -0700 + arm-trusted-firmware (2.6+dfsg-1) unstable; urgency=medium * New upstream release. diff -pruN 2.6+dfsg-1/debian/control 2.7.0+dfsg-2/debian/control --- 2.6+dfsg-1/debian/control 2021-11-17 17:40:59.000000000 +0000 +++ 2.7.0+dfsg-2/debian/control 2022-08-01 03:01:47.000000000 +0000 @@ -2,7 +2,7 @@ Source: arm-trusted-firmware Section: admin Priority: optional Maintainer: Vagrant Cascadian -Standards-Version: 4.6.0 +Standards-Version: 4.6.1 Build-Depends: debhelper-compat (= 13), gcc-arm-none-eabi [arm64], binutils-arm-none-eabi [arm64], diff -pruN 2.6+dfsg-1/debian/copyright 2.7.0+dfsg-2/debian/copyright --- 2.6+dfsg-1/debian/copyright 2021-09-20 01:37:45.000000000 +0000 +++ 2.7.0+dfsg-2/debian/copyright 2022-06-09 03:17:15.000000000 +0000 @@ -10,7 +10,7 @@ Files-Excluded: Files: * Copyright: - 2013-2021, Arm Limited and Contributors. + 2013-2022, Arm Limited and Contributors. License: BSD-3-clause Files: debian/* @@ -20,7 +20,7 @@ License: BSD-3-clause Files: drivers/brcm/* Copyright: - 2016-2020, Broadcom + 2016-2021, Broadcom License: BSD-3-clause Files: drivers/imx/uart/* @@ -34,15 +34,15 @@ Copyright: License: BSD-3-clause Files: drivers/renesas/* -Copyright: - 2015-2020, Renesas Electronics Corporation. +Copyright: + 2015-2021, Renesas Electronics Corporation. License: BSD-3-clause Files: drivers/st/* Copyright: - 2016-2020, STMicroelectronics - 2018-2020, ARM Limited and Contributors. + 2016-2022, STMicroelectronics + 2018-2022, ARM Limited and Contributors. License: BSD-3-clause Files: @@ -51,12 +51,12 @@ Files: drivers/st/ddr/stm32mp1_ram.c drivers/st/fmc/stm32_fmc2_nand.c drivers/st/spi/stm32_qspi.c -Copyright: 2018-2021, STMicroelectronics +Copyright: 2018-2022, STMicroelectronics License: GPL-2+ or BSD-3-clause Files: fdts/stm32* Copyright: - 2017-2020, STMicroelectronics + 2017-2022, STMicroelectronics 2019, Arrow Electronics 2019, Linaro Ltd 2020 Ahmad Fatoum, Pengutronix @@ -65,15 +65,19 @@ License: GPL-2+ or BSD-3-clause Files: include/dt-bindings/* Copyright: - 2017-2020, STMicroelectronics + 2017-2022, STMicroelectronics License: GPL-2+ or BSD-3-clause -Files: include/dt-bindings/reset/stm32mp1-resets.h +Files: + include/dt-bindings/reset/stm32mp13-resets.h + include/dt-bindings/reset/stm32mp15-resets.h Copyright: - 2018 STMicroelectronics + 2018-2022 STMicroelectronics License: GPL-2 or BSD-3-clause -Files: include/dt-bindings/interrupt-controller/arm-gic.h +Files: + include/dt-bindings/interrupt-controller/arm-gic.h + include/dt-bindings/interrupt-controller/irq.h Copyright: 2019-2021, ARM Limited and Contributors. License: MIT @@ -96,12 +100,14 @@ Copyright: License: BSD-3-clause Files: - include/drivers/st/stm32mp1_ddr.h - include/drivers/st/stm32mp1_ddr_regs.h include/drivers/st/stm32_fmc2_nand.h include/drivers/st/stm32_qspi.h + include/drivers/st/stm32mp1_ddr.h + include/drivers/st/stm32mp1_ddr_regs.h + include/drivers/st/stm32mp_ddr.h + include/drivers/st/stm32mp_ddrctrl_regs.h Copyright: - 2017-2021, STMicroelectronics + 2017-2022, STMicroelectronics License: GPL-2+ or BSD-3-clause Files: @@ -130,17 +136,18 @@ Copyright: 1995-2017 Jean-loup Gailly License: Zlib -Files: lib/zlib/tf_gunzip.c +Files: lib/zlib/tf_gunzip.c lib/zlib/zlib.mk Copyright: - 2018, ARM Limited and Contributors. + 2018-2021, ARM Limited and Contributors. License: BSD-3-clause Files: plat/allwinner/* Copyright: - 2017-2021, ARM Limited and Contributors. + 2017-2022, ARM Limited and Contributors. 2018, Andre Przywara 2018, Icenowy Zheng + 2021 Sipeed License: BSD-3-clause Files: plat/marvell/* @@ -150,41 +157,45 @@ Copyright: 2016-2020, ARM Limited and Contributors. 2019 Repk repk@triplefau.lt 2020-2021 Marek Behun, CZ.NIC - 2020 Sartura Ltd. + 2020-2021 Sartura Ltd. + 2021 Globalscale technologies, Inc. + 2021 Semihalf. License: BSD-3-clause Files: plat/ti/* Copyright: - 2018 Texas Instruments Incorporated - 2017-2020, ARM Limited and Contributors. + 2018-2022 Texas Instruments Incorporated + 2017-2022, ARM Limited and Contributors. License: BSD-3-clause Files: plat/renesas/* Copyright: 2013-2020, ARM Limited and Contributors. - 2015-2021, Renesas Electronics Corporation. + 2015-2022, Renesas Electronics Corporation. License: BSD-3-clause Files: plat/st/* Copyright: - 2015-2021, ARM Limited and Contributors. - 2014-2020, STMicroelectronics + 2015-2022, ARM Limited and Contributors. + 2014-2022, STMicroelectronics + 2021, Linaro Limited License: BSD-3-clause Files: plat/imx/* Copyright: 2018-2019 Linaro Limited and Contributors. 2016 Freescale Semiconductor, Inc. - 2015-2021 ARM Limited and Contributors. - 2017-2021 NXP + 2015-2022 ARM Limited and Contributors. + 2017-2022 NXP 2021 Arm + 2922 Linaro License: BSD-3-clause Files: services/spd/* Copyright: - 2013-2021, ARM Limited and Contributors. + 2013-2022, ARM Limited and Contributors. 2020, NVIDIA Corporation. - 2014, Linaro Limited. + 2014, Linaro Limited. License: BSD-3-clause Files: tools/marvell/* @@ -194,17 +205,17 @@ License: BSD-3-clause Files: tools/renesas/* Copyright: - 2015-2020, Renesas Electronics Corporation. + 2015-2021, Renesas Electronics Corporation. License: BSD-3-clause Files: tools/stm32image/* Copyright: - 2017-2018, ARM Limited and Contributors. - 2017-2018, STMicroelectronics + 2017-2018, ARM Limited and Contributors. + 2017-2022, STMicroelectronics License: BSD-3-clause Files: - lib/libfdt/* + lib/libfdt/* include/lib/libfdt/* Copyright: 2006-2012 David Gibson, IBM Corporation. @@ -216,7 +227,7 @@ Copyright: License: BSD-2-clause or GPL-2+ Files: lib/libfdt/libfdt.mk -Copyright: 2016, ARM Limited and Contributors. +Copyright: 2016, ARM Limited and Contributors. License: BSD-3-clause Files: include/lib/libc/* @@ -227,6 +238,7 @@ Copyright: 2012-2021 Roberto E. Vargas Caballero 2018-2020, ARM Limited and Contributors. 2021 ARM Limited + 2020 Broadcom License: BSD-3-clause Files: include/lib/libc/endian.h diff -pruN 2.6+dfsg-1/debian/patches/series 2.7.0+dfsg-2/debian/patches/series --- 2.6+dfsg-1/debian/patches/series 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/debian/patches/series 2022-08-04 22:57:09.000000000 +0000 @@ -0,0 +1 @@ +use-ldflags-with-fiptool-and-cert-create diff -pruN 2.6+dfsg-1/debian/patches/use-ldflags-with-fiptool-and-cert-create 2.7.0+dfsg-2/debian/patches/use-ldflags-with-fiptool-and-cert-create --- 2.6+dfsg-1/debian/patches/use-ldflags-with-fiptool-and-cert-create 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/debian/patches/use-ldflags-with-fiptool-and-cert-create 2022-08-04 22:52:07.000000000 +0000 @@ -0,0 +1,28 @@ +Use LDFLAGS when building fiptool and cert_create. + +diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile +index ca548b836..a823f0dcc 100644 +--- a/tools/cert_create/Makefile ++++ b/tools/cert_create/Makefile +@@ -83,7 +83,7 @@ ${BINARY}: ${OBJECTS} Makefile + @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \ + const char platform_msg[] = "${PLAT_MSG}";' | \ + ${HOSTCC} -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o +- ${Q}${HOSTCC} src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@ ++ ${Q}${HOSTCC} src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} ${LDFLAGS} -o $@ + + %.o: %.c + @echo " HOSTCC $<" +diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile +index e6aeba95b..68a5b2acb 100644 +--- a/tools/fiptool/Makefile ++++ b/tools/fiptool/Makefile +@@ -57,7 +57,7 @@ all: ${PROJECT} + + ${PROJECT}: ${OBJECTS} Makefile + @echo " HOSTLD $@" +- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} ++ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} ${LDFLAGS} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} diff -pruN 2.6+dfsg-1/debian/rules 2.7.0+dfsg-2/debian/rules --- 2.6+dfsg-1/debian/rules 2021-11-27 01:01:20.000000000 +0000 +++ 2.7.0+dfsg-2/debian/rules 2022-08-04 23:33:20.000000000 +0000 @@ -5,6 +5,7 @@ include /usr/share/dpkg/buildtools.mk export DH_VERBOSE=1 export TF_CFLAGS += -ffile-prefix-map=$(CURDIR)=. +export DEB_BUILD_MAINT_OPTIONS=hardening=+all # Enable verbose build by default, disable when terse is specified. ifneq (,$(filter terse,$(DEB_BUILD_OPTIONS))) @@ -13,8 +14,33 @@ else VERBOSE=1 endif -platforms := g12a gxbb sun50i_a64 sun50i_h6 rk3328 rk3399 rpi3 rpi4 -target = $(if $(filter rk3328 rk3399,$@),bl31/bl31.elf,bl31.bin) +platforms := g12a gxbb sun50i_a64 sun50i_h6 rk3328 rk3399 rpi3 rpi4 imx8mn +platforms_nodebug := imx8mq + +# By default, iMX8MN uses UART2 console. However, other boards supported +# upstream (e.g. Variscite VAR-SOM-MX8M-NANO board) uses UART4. +# Add two subplatforms for imx8mn platform: +# * imx8mn: default configuration +# * imx8mn_uart4: console set to UART4 +imx8mn_subplatforms := imx8mn imx8mn_uart4 +imx8mn_uart4_assigns := IMX_BOOT_UART_BASE=0x30a60000 + +# Always set CROSS_COMPILE, which also works for native builds. +define build_platform + $(eval platform := $(1)) + $(eval debug := $(2)) + $(eval buildtype := $(3)) + $(eval subplatforms := $(if $($(platform)_subplatforms), $($(platform)_subplatforms), $(platform))) + $(eval target := $(if $(filter rk3328 rk3399,$(platform)),bl31/bl31.elf,bl31.bin)) + $(foreach subplatform, $(subplatforms), \ + CROSS_COMPILE=aarch64-linux-gnu- CFLAGS=--param=min-pagesize=0 LDFLAGS= TF_LDFLAGS=--no-warn-rwx-segments dh_auto_build -- V=$(VERBOSE) DEBUG=$(debug) $($(subplatform)_assigns) PLAT=$(platform) bl31 ; \ + install -m644 build/$(platform)/$(buildtype)/$(target) -Dt build/renamed/$(subplatform) ; \ + # For each subplatform, make is called using the same PLAT variable. If + # the build is not cleaned between each call, objects will remain the + # same, without rebuilding them. + make DEBUG=$(debug) PLAT=$(platform) clean ; \ + ) +endef %: dh $@ @@ -27,11 +53,11 @@ ifeq ($(filter pkg.arm-trusted-firmware. endif # Only build firmware on arm64. ifeq ($(DEB_HOST_ARCH),arm64) - override_dh_auto_build: $(platforms) + override_dh_auto_build: $(platforms) $(platforms_nodebug) $(platforms): - # Always set CROSS_COMPILE, which also works for native builds. - CROSS_COMPILE=aarch64-linux-gnu- CFLAGS= LDFLAGS= dh_auto_build -- V=$(VERBOSE) DEBUG=1 PLAT=$@ bl31 - install -m644 build/$@/debug/$(target) -Dt build/renamed/$@ + $(call build_platform,$@,1,debug) + $(platforms_nodebug): + $(call build_platform,$@,0,release) endif override_dh_installchangelogs: diff -pruN 2.6+dfsg-1/debian/salsa-ci.yml 2.7.0+dfsg-2/debian/salsa-ci.yml --- 2.6+dfsg-1/debian/salsa-ci.yml 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/debian/salsa-ci.yml 2022-08-04 23:00:04.000000000 +0000 @@ -0,0 +1,12 @@ +--- +include: + - https://salsa.debian.org/salsa-ci-team/pipeline/raw/master/recipes/debian.yml + +variables: + # no autopkgtest tests + SALSA_CI_DISABLE_AUTOPKGTEST: 1 + # No arch:all packages + SALSA_CI_DISABLE_BUILD_PACKAGE_ALL: 1 + +test-crossbuild-arm64: + allow_failure: false diff -pruN 2.6+dfsg-1/debian/upstream/metadata 2.7.0+dfsg-2/debian/upstream/metadata --- 2.6+dfsg-1/debian/upstream/metadata 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/debian/upstream/metadata 2022-04-05 20:59:47.000000000 +0000 @@ -0,0 +1,2 @@ +Repository-Browse: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git +Repository: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git diff -pruN 2.6+dfsg-1/docs/about/contact.rst 2.7.0+dfsg-2/docs/about/contact.rst --- 2.6+dfsg-1/docs/about/contact.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/about/contact.rst 2022-06-01 15:02:46.000000000 +0000 @@ -47,10 +47,10 @@ Arm licensees have an additional support via their partner managers. .. _`issue tracker`: https://developer.trustedfirmware.org -.. _`TF-A development`: https://lists.trustedfirmware.org/pipermail/tf-a/ -.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/pipermail/tf-a-tests/ -.. _`summary of all the lists`: https://lists.trustedfirmware.org +.. _`TF-A development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ +.. _`TF-A-Tests development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a-tests.lists.trustedfirmware.org/ +.. _`summary of all the lists`: https://lists.trustedfirmware.org/mailman3/lists/ -------------- -*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/about/maintainers.rst 2.7.0+dfsg-2/docs/about/maintainers.rst --- 2.6+dfsg-1/docs/about/maintainers.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/about/maintainers.rst 2022-06-01 15:02:46.000000000 +0000 @@ -75,8 +75,6 @@ Software Delegated Exception Interface ( ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Mark Dykes :|G|: `mardyk01`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|F|: services/std_svc/sdei/ Trusted Boot @@ -89,8 +87,14 @@ Trusted Boot :|G|: `ManishVB-Arm`_ :|F|: drivers/auth/ -Secure Partition Manager (SPM) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Secure Partition Manager Core (EL3 FF-A SPMC) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Marc Bonnici +:|G|: `marcbonnici`_ +:|F|: services/std_svc/spm/el3_spmc/\* + +Secure Partition Manager Dispatcher (SPMD) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Olivier Deprez :|G|: `odeprez`_ :|M|: Manish Pandey @@ -99,14 +103,12 @@ Secure Partition Manager (SPM) :|G|: `max-shvetsov`_ :|M|: Joao Alves :|G|: `J-Alves`_ -:|F|: services/std_svc/spm\* +:|F|: services/std_svc/spmd/\* Exception Handling Framework (EHF) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Manish Badarkhe :|G|: `ManishVB-Arm`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|F|: bl31/ehf.c Realm Management Extension (RME) @@ -115,8 +117,6 @@ Realm Management Extension (RME) :|G|: `bipinravi-arm`_ :|M|: Mark Dykes :|G|: `mardyk01`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|M|: Zelalem Aweke :|G|: `zelalem-aweke`_ @@ -193,16 +193,12 @@ Performance Measurement Framework (PMF) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Joao Alves :|G|: `J-Alves`_ -:|M|: Jimmy Brisson -:|G|: `theotherjimmy`_ :|F|: lib/pmf/ Arm CPU libraries ^^^^^^^^^^^^^^^^^ :|M|: Lauren Wehrmeister :|G|: `laurenw-arm`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|F|: lib/cpus/ Reliability Availability Serviceabilty (RAS) framework @@ -225,8 +221,6 @@ Memory Partitioning And Monitoring (MPAM ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Zelalem Aweke :|G|: `zelalem-aweke`_ -:|M|: Jimmy Brisson -:|G|: `theotherjimmy`_ :|F|: lib/extensions/mpam/ Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions @@ -241,22 +235,12 @@ Statistical Profiling Extension (SPE) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Zelalem Aweke :|G|: `zelalem-aweke`_ -:|M|: Jimmy Brisson -:|G|: `theotherjimmy`_ :|F|: lib/extensions/spe/ -Scalable Vector Extension (SVE) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Jimmy Brisson -:|G|: `theotherjimmy`_ -:|F|: lib/extensions/sve/ - Standard C library ^^^^^^^^^^^^^^^^^^ :|M|: Alexei Fedorov :|G|: `AlexeiFedorov`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|F|: lib/libc/ Library At ROM (ROMlib) @@ -293,6 +277,20 @@ GIC driver :|G|: `odeprez`_ :|F|: drivers/arm/gic/ +Message Handling Unit (MHU) driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: David Vincze +:|G|: `davidvincze`_ +:|F|: include/drivers/arm/mhu.h +:|F|: drivers/arm/mhu + +Runtime Security Subsystem (RSS) comms driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: David Vincze +:|G|: `davidvincze`_ +:|F|: include/drivers/arm/rss_comms.h +:|F|: drivers/arm/rss + Libfdt wrappers ^^^^^^^^^^^^^^^ :|M|: Madhukar Pappireddy @@ -315,9 +313,28 @@ Measured Boot :|G|: `AlexeiFedorov`_ :|M|: Javier Almansa Sobrino :|G|: `javieralso-arm`_ +:|M|: Sandrine Bailleux +:|G|: `sandrine-bailleux-arm`_ :|F|: drivers/measured_boot :|F|: include/drivers/measured_boot -:|F|: plat/arm/board/fvp/fvp_measured_boot.c +:|F|: docs/components/measured_boot +:|F|: plat/arm/board/fvp/fvp\*_measured_boot.c + +PSA Firmware Update +^^^^^^^^^^^^^^^^^^^ +:|M|: Manish Badarkhe +:|G|: `ManishVB-Arm`_ +:|M|: Sandrine Bailleux +:|G|: `sandrine-bailleux-arm`_ +:|F|: drivers/fwu +:|F|: include/drivers/fwu + +Platform Security Architecture (PSA) APIs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Sandrine Bailleux +:|G|: `sandrine-bailleux-arm`_ +:|F|: include/lib/psa +:|F|: lib/psa System Control and Management Interface (SCMI) Server ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -339,8 +356,6 @@ Granule Protection Tables Library (GPT-R ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Mark Dykes :|G|: `mardyk01`_ -:|M|: John Powell -:|G|: `john-powell-arm`_ :|F|: lib/gpt_rme :|F|: include/lib/gpt_rme @@ -427,7 +442,7 @@ Arm Rich IoT Platform ports :|G|: `vishnu-banavath`_ :|F|: plat/arm/board/corstone700 :|F|: plat/arm/board/a5ds -:|F|: plat/arm/board/diphda +:|F|: plat/arm/board/corstone1000 Arm Reference Design platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -469,17 +484,20 @@ HiSilicon Poplar platform port Intel SocFPGA platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Tien Hock Loh -:|G|: `thloh85-intel`_ -:|M|: Hadi Asyrafi -:|G|: mabdulha -:|F|: plat/intel/soc +:|M|: Sieu Mun Tang +:|G|: `sieumunt`_ +:|M|: Benjamin Jit Loon Lim +:|G|: `BenjaminLimJL`_ +:|F|: plat/intel/soc/ :|F|: drivers/intel/soc/ MediaTek platform ports ^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Rex-BC Chen :|G|: `mtk-rex-bc-chen`_ +:|M|: Leon Chen +:|G|: `leon-chen-mtk`_ +:|F|: docs/plat/mt\*.rst :|F|: plat/mediatek/ Marvell platform ports and SoC drivers @@ -500,13 +518,6 @@ NVidia platform ports :|F|: lib/cpus/aarch64/denver.S :|F|: plat/nvidia/ -NXP QorIQ Layerscape platform ports -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Jiafei Pan -:|G|: `qoriq-open-source`_ -:|F|: docs/plat/ls1043a.rst -:|F|: plat/layerscape/ - NXP i.MX 7 WaRP7 platform port and SoC drivers ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Bryan O'Donoghue @@ -538,6 +549,8 @@ NXP QorIQ Layerscape common code for pla ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Pankaj Gupta :|G|: `pangupta`_ +:|M|: Jiafei Pan +:|G|: `JiafeiPan`_ :|F|: docs/plat/nxp/ :|F|: plat/nxp/ :|F|: drivers/nxp/ @@ -552,6 +565,37 @@ NXP SoC Part LX2160A and its platform po :|F|: plat/nxp/soc-lx2160a/lx2160aqds :|F|: plat/nxp/soc-lx2160a/lx2160ardb +NXP SoC Part LS1028A and its platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jiafei Pan +:|G|: `JiafeiPan`_ +:|F|: plat/nxp/soc-ls1028a +:|F|: plat/nxp/soc-ls1028a/ls1028ardb + +NXP SoC Part LS1043A and its platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jiafei Pan +:|G|: `JiafeiPan`_ +:|F|: plat/nxp/soc-ls1043a +:|F|: plat/nxp/soc-ls1043a/ls1043ardb + +NXP SoC Part LS1046A and its platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jiafei Pan +:|G|: `JiafeiPan`_ +:|F|: plat/nxp/soc-ls1046a +:|F|: plat/nxp/soc-ls1046a/ls1046ardb +:|F|: plat/nxp/soc-ls1046a/ls1046afrwy +:|F|: plat/nxp/soc-ls1046a/ls1046aqds + +NXP SoC Part LS1088A and its platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jiafei Pan +:|G|: `JiafeiPan`_ +:|F|: plat/nxp/soc-ls1088a +:|F|: plat/nxp/soc-ls1088a/ls1088ardb +:|F|: plat/nxp/soc-ls1088a/ls1088aqds + QEMU platform port ^^^^^^^^^^^^^^^^^^ :|M|: Jens Wiklander @@ -571,6 +615,15 @@ QTI platform port :|F|: docs/plat/qti.rst :|F|: plat/qti/ +QTI MSM8916 platform port +^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Stephan Gerhold +:|G|: `stephan-gh`_ +:|M|: Nikita Travkin +:|G|: `TravMurav`_ +:|F|: docs/plat/qti-msm8916.rst +:|F|: plat/qti/msm8916/ + Raspberry Pi 3 platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Ying-Chun Liu (PaulLiu) @@ -682,16 +735,26 @@ OP-TEE dispatcher :|F|: docs/components/spd/optee-dispatcher.rst :|F|: services/spd/opteed/ -TLK/Trusty secure payloads +TLK ^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Varun Wadekar :|G|: `vwadekar`_ :|F|: docs/components/spd/tlk-dispatcher.rst -:|F|: docs/components/spd/trusty-dispatcher.rst :|F|: include/bl32/payloads/tlk.h :|F|: services/spd/tlkd/ + +Trusty secure payloads +^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Arve Hjønnevåg +:|G|: `arve-android`_ +:|M|: Marco Nelissen +:|G|: `marcone`_ +:|M|: Varun Wadekar +:|G|: `vwadekar`_ +:|F|: docs/components/spd/trusty-dispatcher.rst :|F|: services/spd/trusty/ + Test Secure Payload (TSP) ^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Manish Badarkhe @@ -724,6 +787,8 @@ Sptool ^^^^^^ :|M|: Manish Pandey :|G|: `manish-pandey-arm`_ +:|M|: Joao Alves +:|G|: `J-Alves`_ :|F|: tools/sptool/ Build system @@ -761,6 +826,7 @@ Conventional Changelog Extensions .. _b49020: https://github.com/b49020 .. _carlocaione: https://github.com/carlocaione .. _danh-arm: https://github.com/danh-arm +.. _davidvincze: https://github.com/davidvincze .. _etienne-lms: https://github.com/etienne-lms .. _glneo: https://github.com/glneo .. _grandpaul: https://github.com/grandpaul @@ -777,10 +843,10 @@ Conventional Changelog Extensions .. _mmind: https://github.com/mmind .. _MrVan: https://github.com/MrVan .. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen +.. _leon-chen-mtk: https://github.com/leon-chen-mtk .. _niej: https://github.com/niej .. _npoushin: https://github.com/npoushin .. _prabhakarlad: https://github.com/prabhakarlad -.. _qoriq-open-source: https://github.com/qoriq-open-source .. _remi-triplefault: https://github.com/repk .. _rockchip-linux: https://github.com/rockchip-linux .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm @@ -789,9 +855,12 @@ Conventional Changelog Extensions .. _smaeul: https://github.com/smaeul .. _soby-mathew: https://github.com/soby-mathew .. _sreekare: https://github.com/sreekare -.. _thloh85-intel: https://github.com/thloh85-intel +.. _stephan-gh: https://github.com/stephan-gh +.. _sieumunt: https://github.com/sieumunt +.. _BenjaminLimJL: https://github.com/BenjaminLimJL .. _thomas-arm: https://github.com/thomas-arm .. _TonyXie06: https://github.com/TonyXie06 +.. _TravMurav: https://github.com/TravMurav .. _vwadekar: https://github.com/vwadekar .. _venkatesh: https://github.com/vabbarap .. _Yann-lms: https://github.com/Yann-lms @@ -805,10 +874,8 @@ Conventional Changelog Extensions .. _javieralso-arm: https://github.com/javieralso-arm .. _laurenw-arm: https://github.com/laurenw-arm .. _zelalem-aweke: https://github.com/zelalem-aweke -.. _theotherjimmy: https://github.com/theotherjimmy .. _J-Alves: https://github.com/J-Alves .. _madhukar-Arm: https://github.com/madhukar-Arm -.. _john-powell-arm: https://github.com/john-powell-arm .. _raghuncstate: https://github.com/raghuncstate .. _CJKay: https://github.com/cjkay .. _nmenon: https://github.com/nmenon @@ -820,5 +887,9 @@ Conventional Changelog Extensions .. _arugan02: https://github.com/arugan02 .. _uarif1: https://github.com/uarif1 .. _pangupta: https://github.com/pangupta +.. _JiafeiPan: https://github.com/JiafeiPan +.. _arve-android: https://github.com/arve-android +.. _marcone: https://github.com/marcone +.. _marcbonnici: https://github.com/marcbonnici .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ diff -pruN 2.6+dfsg-1/docs/about/release-information.rst 2.7.0+dfsg-2/docs/about/release-information.rst --- 2.6+dfsg-1/docs/about/release-information.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/about/release-information.rst 2022-06-01 15:02:46.000000000 +0000 @@ -48,6 +48,10 @@ depending on project requirement and par +-----------------+---------------------------+------------------------------+ | v2.6 | 4th week of Nov '21 | 2nd week of Nov '21 | +-----------------+---------------------------+------------------------------+ +| v2.7 | 5th week of May '22 | 3rd week of May '22 | ++-----------------+---------------------------+------------------------------+ +| v2.8 | 5th week of Nov '22 | 3rd week of Nov '22 | ++-----------------+---------------------------+------------------------------+ Removal of Deprecated Interfaces -------------------------------- @@ -61,7 +65,7 @@ Release version after which it will be r | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| | | | | +| STM32MP_USE_STM32IMAGE macro | Dec '21 | 2.7 | FIP is the recommended boot method for STM32MP | +--------------------------------+-------------+---------+---------------------------------------------------------+ -------------- diff -pruN 2.6+dfsg-1/docs/change-log.md 2.7.0+dfsg-2/docs/change-log.md --- 2.6+dfsg-1/docs/change-log.md 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/change-log.md 2022-06-01 15:02:46.000000000 +0000 @@ -3,7 +3,1197 @@ This document contains a summary of the new features, changes, fixes and known issues in each release of Trusted Firmware-A. -## 2.6 (2021-11-22) +## [2.7.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.6.0..refs/tags/v2.7.0) (2022-05-20) + +### New Features + +- **Architecture** + + - **Statistical profiling Extension (FEAT_SPE)** + + - add support for FEAT_SPEv1p2 ([f20eb89](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f20eb893a072bb9b404eedb886e8c65fe76ffb45)) + + - **Branch Record Buffer Extension (FEAT_BRBE)** + + - add BRBE support for NS world ([744ad97](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/744ad97445ce7aa65adaef376d0b5bafc12a90d3)) + + - **Extended Cache Index (FEAT_CCIDX)** + + - update the do_dcsw_op function to support FEAT_CCIDX ([d0ec1cc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0ec1cc437c59e64ecba44710dbce82a04ff892d)) + +- **Platforms** + + - add SZ_* macros ([1af59c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1af59c457010e6e3e6536752736eb02115bca543)) + + - **Allwinner** + + - add SMCCC SOCID support ([436cd75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/436cd754f2b0f9c0ce3094961bd1e179eeff2fc1)) + - allow to skip PMIC regulator setup ([67412e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67412e4d7ae3defaac78ef5e351c63e06cfd907a)) + - apx803: add aldo1 regulator ([a29f6e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a29f6e76cbf76d509c00f84f068b59864d210dfd)) + - choose PSCI states to avoid translation ([159c36f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/159c36fd2fc5afbe979e5028b9e845ed4b7a40f1)) + - provide CPU idle states to the rich OS ([e2b1877](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2b18771fc2a0528dda18dbdaac08dd8530df25a)) + - simplify CPU_SUSPEND power state encoding ([52466ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52466ec38ef312da62ad062720a03a183329f831)) + + - **Arm** + + - **FVP** + + - measure critical data ([cf21064](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf21064ec8a1889f64de48e30e38285227d27745)) + - update HW_CONFIG DT loading mechanism ([39f0b86](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39f0b86a76534d0b7c71dd0c8b34f1a74480386b)) + - enable RSS backend based measured boot ([c44e50b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c44e50b72567205650c6455f3a258f36af0c84dd)) + + - **Morello** + + - add changes to enable TBBR boot ([4af5397](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4af53977533bee7b5763d3efad1448545c2ebef7)) + - add DTS for Morello SoC platform ([572c8ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/572c8ce255397f7cff9640676e510817a8e4c6a3)) + - add support for nt_fw_config ([6ad6465](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ad6465e5ce452688cac079f16d26f64e9f4ce3c)) + - add TARGET_PLATFORM flag ([8840711](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8840711f33131969ec6b62ca3da079cf0573ac8b)) + - configure DMC-Bing mode ([9b8c431](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b8c431e2b2d656da7f8c4158e3d32e104446fec)) + - expose scmi protocols in fdts ([87639aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/87639aab0b6a30d4f49d069c0ea06900b11072a6)) + - split platform_info sds struct ([4a7a9da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a7a9dafbc953089957a0cc1a7183731a5b003e1)) + - zero out the DDR memory space ([2d39b39](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d39b39704c1e4f2a189543ac4ff05ae58e5f5c8)) + + - **N1SDP** + + - add support for nt_fw_config ([cf85030](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf85030efe73439e06295f8185b0a6bebf7b5eae)) + - enable trusted board boot on n1sdp ([fe2b37f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe2b37f6858168a56c3d393bc72f560468d02165)) + + - **RD** + + - **RD-N2** + + - add board support for rdn2cfg2 variant ([efeb438](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/efeb43808d2e3ed23e1d51d5e86460db92971e96)) + - add support for rdedmunds variant ([ef515f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef515f0d3466a8beded4fd662718abbd97391b13)) + + - **SGI** + + - add page table translation entry for secure uart ([33d10ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33d10ac8bf134519f303fd7ce5fb5d583be2f515)) + - deviate from arm css common uart related definitions ([f2cccca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f2ccccaa81ec14a80fedb48c37226e5d852ada7a)) + - enable fpregs context save and restore ([18fa43f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18fa43f753b79cfc3cc5426a3ef50b04efbf6206)) + - route TF-A logs via secure uart ([987e2b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/987e2b7c20eb4ab4215ff5289b715300f5cec054)) + + - **TC** + + - add reserved memory region for Gralloc ([ad60a42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad60a42cd79713984065dca8540c091c49755f32)) + - enable CI-700 PMU for profiling ([fbfc598](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbfc59840f9cd0ea53921c7f6fb9f4850a3b42ee)) + - enable GPU ([82117bb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82117bb48180175c25936b0ff9e33563e25e18f4)) + - enable SMMU for DPU ([4a6ebee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a6ebeeca37ece34a58982c8b6ebdc8cfd70814b)) + - enable tracing ([59da207](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59da207e2f2f028c9051c89bc5a05e95d996c18c)) + + - **Corstone-1000** + + - identify bank to load fip ([cf89fd5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf89fd57ed3286d7842eef41cd72a3977eb6d317)) + - implement platform specific psci reset ([a599c80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a599c80d063975cbeedbc86cfb619fca8545c487)) + - made changes to accommodate 3MB for optee ([854d1c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/854d1c103a9b73bbde7ef1b89b06b29e3cc053bb)) + + - **Intel** + + - add macro to switch between different UART PORT ([447e699](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/447e699f70f1a1d1b85a8136b445eba689166c5d)) + - add RSU 'Max Retry' SiP SMC services ([4c26957](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c26957be253a7ab3acb316f42bf3ee10c409ed2)) + - add SiP service for DCMF status ([984e236](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/984e236e0dee46708534a23c637271a931ceb67e)) + - add SMC for enquiring firmware version ([c34b2a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c34b2a7a1a38dba88b6b668a81bd07c757525830)) + - add SMC support for Get USERCODE ([93a5b97](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93a5b97ec9e97207769db18ae34886e6b8bf2ea4)) + - add SMC support for HWMON voltage and temp sensor ([52cf9c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52cf9c2cd4882534d02e8996e4ff1143ee59290e)) + - add SMC support for ROM Patch SHA384 mailbox ([77902fc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77902fca8fe7449473b09198e1fe197f7b4765d7)) + - add SMC/PSCI services for DCMF version support ([44eb782](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44eb782e15c9af532f2455b37bd53ca93830f6e2)) + - add SMPLSEL and DRVSEL setup for Stratix 10 MMC ([bb0fcc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb0fcc7e011ec4319a79734ba44353015860e39f)) + - add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge ([11f4f03](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11f4f03043ef05762f4d6337804c39dc8f9af54f)) + - allow to access all register addresses if DEBUG=1 ([7e954df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e954dfc2ba83262f7596dd0f17de75163e49e5e)) + - create source file for firewall configuration ([afa0b1a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afa0b1a82a404c616da2da8f52cdcd587938955f)) + - enable firewall for OCRAM in BL31 ([ae19fef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae19fef33707700a91b0b672aa784e084a6ca500)) + - enable SMC SoC FPGA bridges enable/disable ([b7f3044](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7f3044e8725d9af997999547630892cf9e2f0ad)) + - extend attestation service to Agilex family ([581182c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/581182c1916df03860744d8e32941c72b2cc3fda)) + - implement timer init divider via cpu frequency. ([#1](https://review.trustedfirmware.org:29418/TF-A/trusted-firmware-a/issues/1)) ([f65bdf3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f65bdf3a54eed8f7651761c25bf6cc7437f4474b)) + - initial commit for attestation service ([d174083](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d17408316db10db611e23716e8a5b9b9f53ad509)) + - single certificate feature enablement ([7facace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7facacec6328e505b243a4974d045d45fe068afd)) + - support AES Crypt Service ([6726390](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6726390eb02e9659cfaf2d3598be9bf12fbc5901)) + - support crypto service key operation ([342a061](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/342a0618c7ff89327ac5b34dc0713509ffae609b)) + - support crypto service session ([6dc00c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dc00c24ab0100a2aae0f416c72470f8ed17e149)) + - support ECDH request ([4944686](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49446866a515c2db855d456f39df3d586b2084b7)) + - support ECDSA Get Public Key ([d2fee94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2fee94afa6ba7e76508e6bead7eb2936c5eafb8)) + - support ECDSA HASH Signing ([6925410](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/692541051b8cb0f435ae46c5d7351231ee292319)) + - support ECDSA HASH Verification ([7e25eb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e25eb87016ba8355cf0a3a5f71fb8b8785de044)) + - support ECDSA SHA-2 Data Signature Verification ([5830506](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/583050607e43cef8b544a5700386a019e54c422f)) + - support ECDSA SHA-2 Data Signing ([07912da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07912da1b7663451493fb5e40e4c33deeb18a639)) + - support extended random number generation ([24f9dc8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24f9dc8a43fea350416ca9312a78ab4e786da8ad)) + - support HMAC SHA-2 MAC verify request ([c05ea29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c05ea2969070be90a7dbb2d0344c66d89401edf6)) + - support session based SDOS encrypt and decrypt ([537ff05](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/537ff052579862a4865d36d06940feaa796d16da)) + - support SHA-2 hash digest generation on a blob ([7e8249a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e8249a2dbacfa751990c47644f0403311c6e260)) + - support SiP SVC version ([f0c40b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0c40b897f8a25bc50c53239dcf750dd395ebabf)) + - support version 2 SiP SVC SMC function ID for mailbox commands ([c436707](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c436707bc6eed31ab61408ef40db6063d05f0912)) + - support version 2 SiP SVC SMC function ID for non-mailbox commands ([ad47f14](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad47f1422f3f9aa4a622e08b71fc8f5caab98a98)) + - update to support maximum response data size ([b703fac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b703facaaae1e3fe5afa4742b436bb07e065b5e9)) + + - **Marvell** + + - **Armada** + + - **A3K** + + - add north and south bridge reset registers ([a4d35ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4d35ff381c625d61bcc22f9f9a1a45d8663b19d)) + + - **MediaTek** + + - introduce mtk makefile ([500d40d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/500d40d877617653d347fb6308144973d4297ab9)) + + - **MT8195** + + - apply erratas of CA78 for MT8195 ([c21a736](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c21a736d6f3fa9fb0647bff404b0174ebf1acd91)) + - add EMI MPU surppot for SCP and DSP ([690cb12](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/690cb1265ea84851bd6405a0a6a57d2f1c9f03a3)) + - dump EMI MPU configurations ([20ef588](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20ef588e86ad8f3cf13382c164463046db261feb)) + - improve SPM wakeup log ([ab45305](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab45305062f50f81e5c3f800ef4c6cef5097cb04)) + + - **MT8186** + + - add DFD control in SiP service ([e46e9df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e46e9df0d0e05f2aaee613fc4f697fcc8d79c0b3)) + - add SPM suspend driver ([7ac6a76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ac6a76c47d429778723aa804b64c48220a10f11)) + - add Vcore DVFS driver ([635e6b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/635e6b108e773daf37c00f46e6fbb1cae4e78f96)) + - disable 26MHz clock while suspending ([9457cec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9457cec8c02f78ba56fd9298dd795766c89281a2)) + - initialize platform for MediaTek MT8186 ([27132f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/27132f13ca871dc3cf1aa6938995284cf5016e00)) + - add power-off function for PSCI ([a68346a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a68346a772859ee6971ec14c6473d2a853e9c66f)) + - add CPU hotplug ([1da57e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1da57e54b2270b3b49710afa6fd947b01d61b261)) + - add DCM driver ([95ea87f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95ea87ffc2445c77f070e6a2f78ffa424810faed)) + - add EMI MPU basic driver ([1b17e34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b17e34c5d7740a357b2027d88aef7760b346616)) + - add MCDI drivers ([06cb65e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06cb65ef079941d0525dca75dd0e110e9330906d)) + - add pinctrl support ([af5a0c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af5a0c40aff21c4b8771365f19dcb01d6086b30d)) + - add pwrap and pmic driver ([5bc88ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bc88ec61c75ed42b41d84817aa4d6ee68a2efc8)) + - add reboot function for PSCI ([24dd5a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24dd5a7b71544c503446e58cb23c0cfd09245a3c)) + - add RTC drivers ([6e5d76b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e5d76bac8786120d037953f5a6fd67aaff035c1)) + - add SiP service ([5aab27d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5aab27dc4294110a6c0b69bf5ec5343e7df883a7)) + - add sys_cirq support ([109b91e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/109b91e38c8d4f73941c8574759560a1f1636d05)) + - apply erratas for MT8186 ([572f8ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/572f8adbb062c36835fbb82944dd2ed772134bfd)) + - initialize delay_timer ([d73e15e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d73e15e66a33398c8fc51c83f975a3f35494faf5)) + - initialize GIC ([206f125](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/206f125cc177bc110eb87d40ffc7fa18b28c01ce)) + - initialize systimer ([a6a0af5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6a0af57c3369dfc6fc2f25877d812a24e9be311)) + + - **NXP** + + - add SoC erratum a008850 ([3d14a30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d14a30b88762e901e134acc89c6ac4fa9e3f321)) + - add ifc nor and nand as io devices ([b759727](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b759727f5936a687314168dd8912d30897a8c6be)) + - add RCPM2 registers definition ([d374060](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d374060abe9b63296f63f1e3c811aeeddb7a093c)) + - add CORTEX A53 helper functions ([3ccc8ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ccc8ac3e5da48819a2fc90ec48a175515de38cb)) + + - **i.MX** + + - **i.MX 8M** + + - add a simple csu driver for imx8m family ([71c40d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71c40d3bb7c90a6c36d5c49d0830ca95aba65a2f)) + - add imx csu/rdc enum type defines for imx8m ([0c6dfc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c6dfc47847608b6ade0c00716e93afc6725362c)) + - enable conditional build for SDEI ([d2a339d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2a339dfa1665edf87a30a4318af954e764c205c)) + - enable the coram_s tz by default on imx8mn/mp ([d5ede92](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5ede92d78c829d8a3adad0759219b79e0dc0707)) + - enable the csu init on imx8m ([0a76495](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a76495bc2cb0c5291027020a3cd2d3adf31c8ed)) + - do not release JR0 to NS if HAB is using it ([77850c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77850c96f23bcdc76ecb0ecd27a982c00fde5d9d)) + - switch to xlat_tables_v2 ([4f8d5b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f8d5b018efc42d1ffa76fca8efb0d16a57f5edd)) + + - **i.MX 8M Mini** + + - enable optee fdt overlay support ([9d0eed1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9d0eed111cb1294605b6d82291fef16a51d35e46)) + - enable Trusty OS on imx8mm ([ff3acfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff3acfe3cc1658917376152913a9d1b5b9b8de34)) + - add support for measured boot ([cb2c4f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb2c4f93c18b948fbfde9d50ab7d30362be0e00a)) + + - **i.MX 8M Plus** + + - add trusty for imx8mp ([8b9c21b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b9c21b480dd5c3265be1105a9462b3f5657a6b1)) + - enable BL32 fdt overlay support on imx8mp ([aeff146](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aeff14640a91f6d33bfdbc0dc7b0e920f6d14b91)) + + - **i.MX 8M Nano** + + - enable optee fdt overlay support ([2612891](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26128912884b26fab67bce9d87ba0e1c85a0be1e)) + - enable Trusty OS for imx8mn ([99349c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99349c8ecba910dabbaa72b9be91f3ed762036f5)) + + - **i.MX 8M Q** + + - enable optee fdt overlay support ([023750c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/023750c6a898e77c185839f5e56f8e23538f718a)) + - enable trusty for imx8mq ([a18e393](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a18e393339e1d481f4fdf0d621fe4f39ce93a4fe)) + + - **Layerscape** + + - add CHASSIS 3 support for tbbr ([9550ce9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9550ce9ddd7729a961f51ed61ea4b2030e284dcb)) + - add new soc errata a009660 support ([785ee93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/785ee93cc3bd9b43d88fee5acefbd131bf6f2756)) + - add new soc errata a010539 support ([85bd092](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85bd0929433875e0b84fdc2046d9ec2cf0164903)) + - add soc helper macro definition for chassis 3 ([602cf53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/602cf53b6f507cea88f4af5c07bed9325bc7a9b8)) + - define more chassis 3 hardware address ([0d396d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d396d6455a659c4e679f02fae1f9043713474b0)) + - print DDR errata information ([3412716](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3412716b30260958b30d1fa2e1c6d8cce195cd7d)) + + - **LS1043A** + + - add ls1043a soc support ([3b0de91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b0de9182501fae9de372efd1faaf35a7bf74f68)) + + - **LS1043ARDB** + + - add ls1043ardb board support ([e4bd65f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4bd65fed8a12d06181c1343cf786ac91badb6b0) + + - **LX2** + + - enable DDR erratas for lx2 platforms ([cd960f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd960f5009ee062bba9c479505caee6bbe644649)) + + - **LS1046A** + + - add new SoC platform ls1046a ([cc70859](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc708597fa72094c5a01df60e6538e4a7429c2a0)) + + - **LS1046ARDB** + + - add ls1046ardb board support ([bb52f75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb52f7560b62043ed08a753f399dc80e8c1582d3)) + + - **LS1046AFRWY** + + - add ls1046afrwy board support ([b51dc56](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b51dc56ab9ea79e4709f0d0ce965525d0d3da918)) + + - **LS1046AQDS** + + - add board ls1046aqds support ([16662dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16662dc40dd2578d3000528ece090ed39ed18b9c)) + + - **LS1088A** + + - add new SoC platform ls1088a ([9df5ba0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9df5ba05b4fe4cd44157363a897b73553ba6e2f1)) + + - **LS1088ARDB** + + - add ls1088ardb board support ([2771dd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2771dd0293b6cda6811e8bed95f2354a3ee0124e)) + + - **LS1088AQDS** + + - add ls1088aqds board support ([0b0e676](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b0e67669814139c6818e61e03d0d0e3314fdc99)) + + - **QEMU** + + - add SPMD support with SPMC at S-EL1 ([f58237c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f58237ccd9fd2350730d60ab7de59b5c376bfb35)) + - add support for measured boot ([5e69026](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e690269d579d9461be3c5f5e3f59d4c666863a0)) + + - **QTI** + + - **MSM8916** + + - allow booting secondary CPU cores ([a758c0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a758c0b65c6730fb07846899d6436ba257484d34)) + - initial platform port ([dddba19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dddba19a6a3cb7a1039beaffc3169c4eb3291afd)) + - setup hardware for non-secure world ([af64473](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af6447315c8534331513ca6b6556af661e0ba88b)) + + - **Renesas** + + - **R-Car** + + - **R-Car 3** + + - modify sequence for update value for WUPMSKCA57/53 ([d9912cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d9912cf3d1022fc6d38a6059290040985de56e63)) + - modify type for Internal function argument ([ffb725b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ffb725be98ffd010c851629a6da75bf57f770c7f)) + - update IPL and Secure Monitor Rev.3.0.3 ([14d9727](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14d9727e334300b3f5f57e76a9f6e21431e6c6b5)) + + - **ST** + + - add a function to configure console ([53612f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53612f72938f37244a5f10ae7c57abe7358c221f)) + - add STM32CubeProgrammer support on UART ([fb3e798](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb3e7985c9b657c535c02b722ecc413f643e671e)) + - add STM32MP_UART_PROGRAMMER target ([9083fa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9083fa11ead67272b94329e8f84257de6658620d)) + - add early console in BL2 ([c768b2b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c768b2b22f4fb16cf8be8b4815a1984b29918c20)) + - disable authentication based on part_number ([49abdfd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49abdfd8cececb91a4bc7e7b29a30c09dce461c7)) + - get pin_count from the gpio-ranges property ([d0f2cf3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0f2cf3b148df75d5cbbd42dfa18012043e5d1f4)) + - map 2MB for ROM code ([1697ad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1697ad8cc81307972d31cec3b27d58f589eeeb3f)) + - protect UART during platform init ([acf28c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/acf28c267b3679a0770b2010f2ec3fb3c2d19975)) + - update stm32image tool for header v2 ([2d8886a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d8886aceed613b9be25f20900914cacc8bb0fb9)) + - update the security based on new compatible ([812daf9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/812daf916c9c977a4f6d7d745d22b90c8492fc71)) + - use newly introduced clock framework ([33667d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33667d299bd5398ca549f542345e0f321b483d17)) + + - **ST32MP1** + + - adaptations for STM32MP13 image header ([a530874](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5308745ee3ab3b77ca942052e60968bcc01340d)) + - add "Boot mode" management for STM32MP13 ([296ac80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/296ac8012b77ea84079b38cc60ee786a5f91857f)) + - add a second fixed regulator ([225ce48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/225ce4822ccf2e7c7c1fca6cf3918d4399158613)) + - add GUID values for updatable images ([8d6b476](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d6b4764f3e54431c3d01342d39d1efa70c3dbf9)) + - add GUID's for identifying firmware images to be booted ([41bd8b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41bd8b9e2ad3b755505684601f07d4f7f8ec04c4)) + - add helper to enable high speed mode in low voltage ([dea02f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dea02f4eaed855c2f05d8a1d7eefca313e98e5b4)) + - add logic to pass the boot index to the Update Agent ([ba02add](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba02add9ea8fb9a8b0a533c1065a77c7dda4f2a6)) + - add logic to select the images to be booted ([8dd7553](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dd755314fdfa077465bd6cd5e248be392d90378)) + - add NVMEM layout compatibility definition ([dfbdbd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dfbdbd0625990267c6742268118ea748e77c6123)) + - add part numbers for STM32MP13 ([30eea11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30eea116cdd66b3fa1e1208e185eb7285a83d898)) + - add regulator framework compilation ([bba9fde](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bba9fdee589fb9a7aca5963f53b7ce67c30520b3)) + - add sdmmc compatible in platform define ([3331d36](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3331d3637c295993a78f22afe7463cf1c334d329)) + - add sign-compare warning ([c10f3a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c10f3a4559ebf7a654a9719fec619e81e6ee1d69)) + - add stm32_get_boot_interface function ([a6bfa75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6bfa75cf25241a486ab371ae105ea7ebf2d34d8)) + - add support for building the FWU feature ([ad216c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad216c106682f1d2565b2a08e11a601b418dc8a4)) + - add support for reading the metadata partition ([0ca180f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ca180f6416160a523ff442f1ad0b768a9a3a948)) + - add timeout in IO compensation ([de02e9b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de02e9b0ec29548b8ce5ef6ee9adcd9c5edb0518)) + - allow configuration of DDR AXI ports number ([88f4fb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88f4fb8fa759b1761954067346ee674b454bdfde)) + - call pmic_voltages_init() in platform init ([ffd1b88](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ffd1b889225a8aec124df9e330f41dc638fd7180)) + - chip rev. Z is 0x1001 on STM32MP13 ([ef0b8a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef0b8a6c1b1a0eab3626041f3168f82bdb410836)) + - enable BL2_IN_XIP_MEM to remove relocation sections ([d958d10](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d958d10eb360024e15f3c921dc3863a0cee98830)) + - enable format-signedness warning ([cff26c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cff26c19169dd94857e8180cc46b7aa4ccac574a)) + - get CPU info from SYSCFG on STM32MP13 ([6512c3a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6512c3a62a4a7baaf32597284b242bc7172b7e26)) + - introduce new flag for STM32MP13 ([bdec516](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdec516ee862bfadc25a4d0c02a3b8d859c1fa25)) + - manage HSLV on STM32MP13 ([fca10a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fca10a8f1b47231ef92634a0adf1a26cbfc97c2a)) + - manage monotonic counter ([f5a3688](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5a3688b8608df0f269a0b6df18632ebb9e26a01)) + - new way to access platform OTP ([ae3ce8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae3ce8b28eac73e9a41fdb28424d9f0f4b5f200e)) + - preserve the PLL4 settings for USB boot ([bf1af15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf1af154db2c89028a8a551c18885add35d38966)) + - register fixed regulator ([967a8e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/967a8e63c33822680e3a4631430dcd9a4a64becd)) + - remove unsupported features on STM32MP13 ([111a384](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/111a384c90afc629e644e7a8284abbd4311cc6b3)) + - retry 3 times FWU trial boot ([f87de90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f87de907c87e5b2091592c131c4d3d2f737bef01)) + - select platform compilation either by flag or DT ([99a5d8d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99a5d8d01d38474b056766651bd746a4fe93ab20)) + - skip TOS_FW_CONFIG if not in FIP ([b706608](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7066086424c2f6fd04880db852306d6f487962e)) + - stm32mp_is_single_core() for STM32MP13 ([7b48a9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b48a9f3286b8f174acf8821fec48fd2e4771514)) + - update BACKUP_BOOT_MODE for STM32MP13 ([4b031ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b031ab4c50d0b9f7127daa7f4eec634f39de970)) + - update boot API for header v2.0 ([5f52eb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f52eb15970e57d2777d114948fc1110e3dd3f6c)) + - update CFG0 OTP for STM32MP13 ([1c37d0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c37d0c1d378769249c797de5b13d73cf6f17a53)) + - update console management for SP_min ([aafff04](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aafff0435448c8409935132be41758e0031f0822)) + - update IO compensation on STM32MP13 ([8e07ab5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e07ab5f705b213af28831f7c3e9878154e07df0)) + - update IP addresses for STM32MP13 ([52ac998](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52ac9983d67522b6b821391941c8b0d01fd68941)) + - update memory mapping for STM32MP13 ([48ede66](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48ede6615168118c674288f2e4f8ee1b11d2fa02)) + - updates for STM32MP13 device tree compilation ([d38eaf9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d38eaf99d327bc1400f51c87b6d8a2f92cd828c6)) + - usb descriptor update for STM32MP13 ([d59b9d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d59b9d53b9cfb2443575c62c6716eb5508374a7b)) + - use clk_enable/disable functions ([c7a66e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7a66e720ae1a1a5ef98eaf9ff327cd352549010)) + - use only one filter for TZC400 on STM32MP13 ([b7d0058](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7d0058a3a9153a3863cf76a6763ea751b3ab48d)) + - warn when debug enabled on secure chip ([ac4b8b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac4b8b06eb23134d2a9002834541d33f8d43661b)) + + - **Texas Instruments** + + - add enter sleep method ([cf5868b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf5868b8cd7239dee69bdf6ba3ab87bd06bf15f5)) + - add gic save and restore calls ([b40a467](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b40a467783e5911f97d6e92ebdeb34ca2f005552)) + - add PSCI handlers for system suspend ([2393c27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2393c27680a1ec636e413051e87e986df5a866fe)) + - allow build config of low power mode support ([a9f46fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a9f46fad82b807a9f0a967245e3ac10ee8dd0ef1)) + - increase SEC_SRAM_SIZE to 128k ([38164e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38164e64bd853a8329475e9168c5fcb94ecc528b)) + + - **Xilinx** + + - **Versal** + + - add SPP/EMU platform support for versal ([be73459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be73459a945d8fa781fcc864943ccd0a8d92421c)) + - add common interfaces to handle EEMI commands ([1397967](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1397967490c9f0ebff0d20a566260d1475fe065e)) + - add SMCCC call TF_A_PM_REGISTER_SGI ([fcf6f46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf6f469318d693a024d42ae2d0f4afb26c1e85d)) + - add support to reset SGI ([bf70449](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf70449ba2d1ffd20b01741c491dc0f565009b3d)) + - add UART1 as console ([2c79149](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c791499c26b40c31ce7f68c3bf0dca777fc62de)) + - enhance PM_IOCTL EEMI API to support additional arg ([d34a5db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d34a5db8a76abdfc8fa68f43b24b971699086a06)) + - get version for ATF related EEMI APIs ([da6e654](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da6e654bc8b03ee784d0e96a71c4e591e63930f2)) + - remove the time stamp configuration ([18e2a79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18e2a79f8a5eaa72a2a7e641c2481beb9f827dce)) + + - **ZynqMP** + + - disable the -mbranch-protection flag ([67abd47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67abd4762bd563be94e734bb0fe4087e88d5d446)) + - fix section `coherent_ram' will not fit in region `RAM' ([9b4ed0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b4ed0af02a8ff1fd9a81af5213fde16d3eb8d92)) + - add feature check support ([223a628](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/223a6284b8a0a3ead884a7f0cf333a464d32e319)) + - add support to get info of xilfpga ([cc077c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc077c22273075db328bd30fa12c28abf9eef052)) + - add uart1 as console ([ea66e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea66e4af0baf5d5b905e72f824a672f16a6e0f98)) + - increase the max xlat tables when debug build is enabled ([4c4b961](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c4b9615b1d9512a4a89aa08e722547cc491a07b)) + - pass ioctl calls to firmware ([76ff8c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/76ff8c459e9e6d105e614d68648bd6680806f93e)) + - pm_api_clock_get_num_clocks cleanup ([e682d38](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e682d38b56854e1586b25d929dbc83543b4c66e4)) + +- **Bootloader Images** + + - add XLAT tables symbols in linker script ([bb5b942](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb5b942e6f133198daedcca0b74ec598af260a54)) + + - **BL2** + + - add support to separate no-loadable sections ([96a8ed1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96a8ed14b74cca33a8caf567d0f0a2d3b2483a3b)) + + - **BL31** + + - aarch64: RESET_TO_BL31_WITH_PARAMS ([25844ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25844ff728e4a0e5430ba2032457aba7b780a701)) + +- **Services** + + - **RME** + + - add dummy platform token to RMMD ([0f9159b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f9159b7ebb7e784a8ed998869ff21095fa105b1)) + - add dummy realm attestation key to RMMD ([a043510](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0435105f229a65c7861b5997793f905cf90b823)) + + - **SPM** + + - update ff-a boot protocol documentation ([573ac37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/573ac37373d3e8b2c31b3aaeed759e4656e060ec)) + + - **EL3 SPMC** + + - allow BL32 specific defines to be used by SPMC_AT_EL3 ([2d65ea1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d65ea1930d4ce26cc176a8c60e9401d0b4f862a)) + - add plat hook for memory transactions ([a8be4cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8be4cd057bce5f0b4ac6af396c0c870474d1ef4)) + - add EL3 SPMC #defines ([44639ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44639ab73e43e0b79da834dff8c85266d68e5066)) + - introduce accessor function to obtain datastore ([6a0788b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a0788bc0e704283e52c80990aa2bb6e047a0cc2)) + - add FF-A secure partition manager core ([5096aeb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5096aeb2ba646548a7a6ab59e975b996e6c9026a)) + - add FFA_FEATURES handler ([55a2963](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55a296387b9720855df429a08c886f47a4a45057)) + - add FFA_PARTITION_INFO_GET handler ([f74e277](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f74e27723bb54ad1318fa462fbcff70af555b2e6)) + - add FFA_RUN handler ([aad20c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aad20c85cb6f4bc91318d3c6488cf72a20fdbe96)) + - add FFA_RX_RELEASE handler ([f0c25a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0c25a082fc8b891d4d21518028118561caa4735)) + - add function to determine the return path from the SPMC ([20fae0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20fae0a7ce7fd407cd3efb7745017ee6ab605159)) + - add helper function to obtain endpoint mailbox ([f16b6ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f16b6ee3deac93706efe465f399c9542e12d5eeb)) + - add helper function to obtain hyp structure ([a7c0050](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7c00505f85684326a223535a319c170d14826f6)) + - add helper to obtain a partitions FF-A version ([c2b1434](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c2b1434369292081f907c548e496f59e197eb2f1)) + - add partition mailbox structs ([e1df600](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1df6008d9b4a00da25ec08fbdcbd3a5967fdb54)) + - add support for direct req/resp ([9741327](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9741327df577c3f43db42b26bda607429e62af0b)) + - add support for FF-A power mgmt. messages in the EL3 SPMC ([59bd2ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59bd2ad83c13ed3c84bb9b841032c95927358890)) + - add support for FFA_MSG_WAIT ([c4db76f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4db76f066f236fe490ebc7a50833a04e08f5151)) + - add support for FFA_SPM_ID_GET ([46872e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46872e01f5efb555fef8367595b59e5d2f75cec0)) + - add support for forwarding a secure interrupt to the SP ([729d779](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/729d7793f830781ff8ed44d144c3346c6e4251a3)) + - add support for handling FFA_ERROR ABI ([d663fe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d663fe7a3002ff028c190eb732278b878e78b7b7)) + - add support for v1.1 FF-A boot protocol ([2e21921](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e21921502b1317031cf2a2f69c5d47ac88a505d)) + - add support for v1.1 FF-A memory data structures ([7e804f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e804f9695c48681c91e9e6fc6175eb6997df867)) + - enable building of the SPMC at EL3 ([1d63ae4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d63ae4d0d8374a732113565be90d58861506e39)) + - enable checking of execution ctx count ([5b0219d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b0219ddd5da42413f4c2be9302224b5b71295ff)) + - enable handling FF-A RX/TX Mapping ABIs ([1a75224](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a752245ecae6487844c57667e24b704e6df8079)) + - enable handling FFA_VERSION ABI ([0c7707f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c7707fdf21fc2a8658f5a4bdfd2f8883d02ada5)) + - enable handling of the NS bit ([0560b53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0560b53e71ab6daefa8e75665a718605478746a4)) + - enable parsing of messaging methods from manifest ([3de378f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3de378ff8c9430c964cbe9b0c58fa5afc4d237ce)) + - enable parsing of UUID from SP Manifest ([857f579](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/857f5790da3770a9ca52416274eec4e545c9be53)) + - enable the SPMC to pass the linear core ID in a register ([f014300](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0143004e548582760aacd6f15f5499b18081a69)) + - prevent read only xlat tables with the EL3 SPMC ([70d986d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70d986ddbbf56a20c7550c079dd4dc9462332594)) + - support FFA_ID_GET ABI ([d5fe923](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5fe92350cb018ae7083ed26a6a16508ccd82a86)) + - allow forwarding of FFA_FRAG_RX/TX calls ([642db98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/642db9840712044b9c496e04a7acd60580e54117)) + - enable handling of FF-A SMCs with the SPMC at EL3 ([bb01a67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb01a67306f47271adde051e541c760028c1a0f1)) + - update SPMC init flow to use EL3 implementation ([6da7607](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6da76075bf4b953d621aa15c379e62a5f785de3f)) + - add logical partition framework ([7affa25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7affa25cad400101c016082be2d102be0f4fce80)) + - add FF-A memory management code ([e0b1a6d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0b1a6d59e57c0dbe87f5b8f8166f1123664f058)) + - prevent duplicated sharing of memory regions ([fef85e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fef85e1e53fcf44e8d9ed50c89d8a764bf1b7738)) + - support multiple endpoints in memory transactions ([f0244e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0244e5dd1b8cbab75ef00c1b9b56eed5b3cad4b)) + + - **SPMD** + + - forward FFA_VERSION from SPMD to SPMC ([9944f55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9944f55761c4d5cc1feefaf5e33bf7fb83d8f5f3)) + - enable SPMD to forward FFA_VERSION to EL3 SPMC ([9576fa9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9576fa93a2effc23a533b80dce41d7104a8d200b)) + - add FFA_MSG_SEND2 forwarding in SPMD ([c2eba07](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c2eba07c47f8d831629104eeffcec11ed7d3b0a5)) + - add FFA_RX_ACQUIRE forwarding in SPMD ([d555233](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d555233fe5a04dfd99fd6ac30bacc5284285c131)) + + - **SPM MM** + + - add support to save and restore fp regs ([15dd6f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15dd6f19da8ee4b20ba525e0a742d0df9e46e071)) + +- **Libraries** + + - **CPU Support** + + - add library support for Poseidon CPU ([1471475](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1471475516cbf1b4a411d5ef853bd92d0edd542e)) + - add support for Cortex-X1 ([6e8eca7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e8eca78e5db966e10e2fa2737e9be4d5af51fa9)) + - add L1PCTL macro definiton for CPUACTLR_EL1 ([8bbb1d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8bbb1d80a58dbdf96fcabbdebbfbd21d2d5344a4)) + + - **EL3 Runtime** + + - add arch-features detection mechanism ([6a0da73](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a0da73647546aea1d10b4b2347bac9d532bcb43)) + - replace ARM_ARCH_AT_LEAST macro with FEAT flags ([0ce220a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ce220afb24f0511332b251952019d7011ccc282)) + + - **FCONF** + + - add a helper to get image index ([9e3f409](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9e3f409398af447b1d03001dd981007a9bb1617e)) + - add NS load address in configuration DTB nodes ([ed4bf52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed4bf52c33b6860d58a2ffc946bd293ec76bbdaa)) + + - **Standard C Library** + + - add support for length specifiers ([701e94b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/701e94b08f382691b0deabd4df882abd87e17ab5)) + + - **PSA** + + - add initial attestation API ([0848565](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/084856513d6730a50a3d65ac9c3bdae465117c40)) + - add measured boot API ([758c647](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/758c64715b691be92de623f81032494e38a43cc8)) + - mock PSA APIs ([0ce2072](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ce2072d9b9f419bb19595454395a33a5857ca2f)) + +- **Drivers** + + - **Generic Clock** + + - add a minimal clock framework ([847c6bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/847c6bc8e6d55b1c0f31a52407aa61515cd6c612)) + + - **FWU** + + - add a function to pass metadata structure to platforms ([9adce87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9adce87efc8acc947b8b49d700c9773a7f071e02)) + - add basic definitions for GUID handling ([19d63df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19d63df1af72b312109b827cca793625ba6fcd16)) + - add platform hook for getting the boot index ([40c175e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40c175e75bc442674a5dc793c601b09681158ab9)) + - pass a const metadata structure to platform routines ([6aaf257](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aaf257de4a4070ebc233f35a09bce4c39ea038c)) + - simplify the assert to check for fwu init ([40b085b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40b085bddf60cf8c533b379ccb41e6668c5080dd)) + + - **Measured Boot** + + - add RSS backend ([0442ebd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0442ebd2e9bcf5fa4344d8fa8ef4b69a3b249e33)) + + - **GUID Partition Tables Support** + + - add a function to identify a partition by GUID ([3cb1065](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cb1065581f6d9a8507af8dbca3779d139aa0ca7)) + - cleanup partition and gpt headers ([2029f93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2029f930097b0c3b1b1faa660032d16ed01a5c86)) + - copy the partition GUID into the partition structure ([7585ec4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7585ec4d36ebb7e286cfec959b2de084eded8201)) + - make provision to store partition GUID value ([938e8a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/938e8a500a25a949cfd25f0cb79f6c1359c9b40c)) + - verify crc while loading gpt header ([a283d19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a283d19f82ddb635d9d9fa061e7fd956167ebe60)) + + - **Arm** + + - **GIC** + + - allow overriding GICD_PIDR2_GICV2 address ([a7521bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7521bd5d887bfd69d99a55a81416e38ba9ebc97)) + + - **GIC-600AE** + + - disable SMID for unavailable blocks ([3f0094c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f0094c15d433cd3de413a4633a4ac2b8e1d1f2e)) + - enable all GICD, PPI, ITS SMs ([6a1c17c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a1c17c770139c00395783e7568220d61264c247)) + - introduce support for RAS error handling ([308dce4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/308dce40679f63db504cd3d746a0c37a2a05f473)) + + - **SMMU** + + - add SMMU abort transaction function ([6c5c532](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c5c5320511ab8202fb9eccce9e66b4e4e0d9a33)) + - configure SMMU Root interface ([52a314a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52a314af254966a604e192fcc3326737354f217a)) + + - **MHU** + + - add MHU driver ([af26d7d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af26d7d6f01068809f17cc2d49a9b3d573c640a9)) + + - **RSS** + + - add RSS communication driver ([ce0c40e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce0c40edc93aa403cdd2eb6c630ad23e28b01c3e)) + + - **TZC** + + - **TZC-380** + + - add sub-region register definition ([fdafe2b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fdafe2b5ead66a1b5175db77bcc7cedafa14a059)) + + - **Marvell** + + - **Armada** + + - **A3K** + + - **A3720** + + - preserve x1/x2 regs in console_a3700_core_init() ([7c85a75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c85a7572960efbaabe20c9db037bcec66be3e98)) + + - **MediaTek** + + - **APU** + + - add mt8195 APU clock and pll SiP call ([296b590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/296b590206aa6db51e5c82b1a97a4f9707b49c4d)) + - add mt8195 APU iommap regions ([339e492](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/339e4924a7a3fd11bc176e0bf3e01d76133d364c)) + - add mt8195 APU mcu boot and stop SiP call ([88906b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88906b443734399be5c07a5bd690b63d3d82cefa)) + + - **NXP** + + - **DCFG** + + - add Chassis 3 support ([df02aee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df02aeeec640d2358301e903d9c8c473d455be9e)) + - add gic address align register definition ([3a8c9d7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a8c9d78d4c65544d789bd64bd005ac10b5b352d)) + - add some macro definition ([1b29fe5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b29fe534b8732193850fced2da1dc449450bd3b)) + + - **NXP Crypto** + + - add chassis 3 support ([d60364d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d60364d48e31b33b57049d848b7462eb0e0de612)) + + - **DDR** + + - add rawcard 1F support ([f2de48c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f2de48cb143c20ccd7a9c141df3d34cae74049de)) + - add workaround for errata A050958 ([291adf5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/291adf521a54a365e54964bff4dae53d51c65936)) + + - **GIC** + + - add some macros definition for gicv3 ([9755fd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9755fd2ec2894323136715848910b13053cfe0ce)) + + - **CSU** + + - add bypass bit mask definition ([ec5fc50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec5fc501f15922967bf5d8260072ba1f9aec9640)) + + - **IFC NAND** + + - add IFC NAND flash driver ([28279cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28279cf2c141caf5e4e7156f874cde6f5a0d271b)) + + - **IFC NOR** + + - add IFC nor flash driver ([e2fdc77](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2fdc77ba4eee91f0d1490e34f0fff552fc55dc9)) + + - **TZC-380** + + - add tzc380 platform driver support ([de9e57f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de9e57ff1f3769e770eac44b94127eb7239a63f2)) + + - **ST** + + - introduce fixed regulator driver ([5d6a264](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d6a2646f7759a5a2b3daed0d8aef4588c552ba4)) + + - **Clock** + + - add clock driver for STM32MP13 ([9be88e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9be88e75c198b08c508d8e470964720a781294b3)) + - assign clocks to the correct BL ([7418cf3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7418cf397916c97cb4ecf159b1f497a84299b695)) + - check HSE configuration in serial boot ([31e9750](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31e9750bc17bd472d4f2a3db297461efc301be51)) + - define secure and non-secure gate clocks ([aaa09b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aaa09b713c6f539fb5b2ee7e2dfd75f2d46875f5)) + - do not refcount on non-secure clocks in bl32 ([3d69149](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d69149a7e9e9a899d57f48bee26f98614f88935)) + - manage disabled oscillator ([bcccdac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcccdacc7e7b7b985df942b3fae26cb9038a2574)) + + - **DDR** + + - add read valid training support ([5def13e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5def13eb01ebac5656031bdc388a215d012fdaf8)) + + - **GPIO** + + - allow to set a gpio in output mode ([53584e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53584e1d5b2b843ea3bb9e01e3f01ea7c364ee6a)) + - do not apply secure config in BL2 ([fc0aa10](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc0aa10a2cd3cab887a8baa602891d1f45db2537)) + - add a function to reset a pin ([737ad29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/737ad29bf992a7a79d538d1e0b47c7f38d9a4b9d)) + + - **SDMMC2** + + - allow compatible to be defined in platform code ([6481a8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6481a8f1e045ac80f0325b8bfe7089ba23deaf7b)) + - manage cards power cycle ([258bef9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/258bef913aa76ead1b10c257d1695d9c0ef1c79d)) + + - **ST PMIC** + + - add pmic_voltages_init() function ([5278ec3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5278ec3faf2010fd6aea1d8cd4294dd229c5c21d)) + - register the PMIC to regulator framework ([85fb175](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85fb175b5ef854bc4607db98a4cfb5f35d822cee)) + + - **STPMIC1** + + - add new services ([ea552bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea552bf5a57b573a6b09e396e3466b3c4af727f0)) + - add USB OTG regulators ([13fbfe0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13fbfe046e71393961d2c70a4f748a15f9c15f77)) + + - **Regulator** + + - add support for regulator-always-on ([9b4ca70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b4ca70d97d9a2556752b511ff9fe52012faff02)) + - add a regulator framework ([d5b4a2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5b4a2c4e7fd0bcb9f08584b242e69a2e591fb71)) + + - **UART** + + - manage oversampling by 8 ([1f60d1b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f60d1bd33d434b0c82a74e276699ee5a2f63833)) + - add uart driver for STM32MP1 ([165ad55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/165ad5561ef598ea6261ba082610eeff3f208df7)) + +- **Miscellaneous** + + - **Debug** + + - update print_memory_map.py ([d16bfe0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d16bfe0feffe6a20399fb91d86fd8f7282b941dd)) + + - **DT Bindings** + + - add bindings for STM32MP13 ([1b8898e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b8898eb32c3872a34fc59f4216736f23af0c6ea)) + - add TZC400 bindings for STM32MP13 ([24d3da7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24d3da76d221390bb47d501c2ed77a1a7d2b42e7)) + + - **FDT Wrappers** + + - add function to find or add a sudnode ([dea8ee0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dea8ee0d3f13f8d1638745b76e86bd7617bf92e7)) + + - **FDTs** + + - add the ability to supply idle state information ([2b2b565](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b2b565717cc0299e75e8806004d1a3548e9fbf7)) + + - **STM32MP1** + + - add DDR support for STM32MP13 ([e6fddbc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6fddbc995947d4e5a5dc6607c76cd46fdd840e2)) + - add DT files for STM32MP13 ([3b99ab6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b99ab6e370a01caec14bc5422a86001eaf291b8)) + - add nvmem_layout node and OTP definitions ([ff8767c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff8767cbfc2bb851a2f6cc32fbe3693ddbfb7d12)) + - add st-io_policies node for STM32MP13 ([2bea351](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bea35122d102492f18c427535ce6c9b7016e356)) + - add support for STM32MP13 DK board ([2b7f7b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b7f7b751f4b0f7a8a0f4a35407af22cc269e529)) + - update NVMEM nodes ([375b79b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/375b79bb4a773fe6a5dd971272c72bf12155050e)) + +- **Documentation** + + - context management refactor proposal ([3274226](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/327422633bef112a10579d4daeca0f596cd02911)) + + - **Threat Model** + + - Threat Model for TF-A v8-R64 Support ([dc66922](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dc669220d5666c2c808bc11ba81c86a9b071271a)) + +- **Tools** + + - **Secure Partition Tool** + + - add python SpSetupActions framework ([b1e6a41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b1e6a41572240839e62099aa00298174b18c696a)) + - delete c version of the sptool ([f4ec476](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4ec47613fef8db8037195147dc2ac6fb6f154ff)) + - python version of the sptool ([2e82874](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e82874cc9b7922e000dd4d7718e3153e347b1d7) + - use python version of sptool ([822c727](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/822c72791f791d26e233df0c15a655c3dbd8b117)) + +### Resolved Issues + +- **Architecture** + + - **Activity Monitors Extension (FEAT_AMU)** + + - add default value for ENABLE_FEAT_FGT and ENABLE_FEAT_ECV flags ([820371b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/820371b13028a6f620a62cf73a951883d051666b)) + - fault handling on EL2 context switch ([f74cb0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f74cb0be8ac80eb3072555cb04eb09375d4cb31f)) + - limit virtual offset register access to NS world ([a4c3945](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4c394561af31ae0417ed9ff3b3152adb7cd5355)) + + - **Scalable Vector Extension (FEAT_SVE)** + + - disable ENABLE_SVE_FOR_NS for AARCH32 ([24ab2c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24ab2c0af74be174acf755a36b3ebba867184e60)) + +- **Platforms** + + - **Allwinner** + + - improve DTB patching error handling ([79808f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79808f10c32d441572666551b1545846079af15b)) + + - **Arm** + + - fix fvp and juno build with USE_ROMLIB option ([861250c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/861250c3b26d64f859f5f37686e453d5074fa976)) + - increase ARM_BL_REGIONS count ([dcb1959](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcb1959161935aa58d2bb852f3cef0b96458a4e1)) + - remove reclamation of functions starting with "init" ([6c87abd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c87abdda400354ebf4f5351086c32a4620475c9)) + - use PLAT instead of TARGET_PLATFORM ([c5f3de8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c5f3de8dabc9b955b6051a6c6116d40b10a84f5d)) + - fix SP count limit without dual root CoT ([9ce15fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ce15fe8910580efca46b9f102e117402ce769db)) + + - **FVP** + + - FCONF Trace Not Shown ([0c55c10](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c55c10305df6217fd978d58ce203dbad3edd4d5)) + - disable reclaiming init code by default ([fdb9166](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fdb9166b9494402eb2da7e0b004c121b322725e0)) + - extend memory map to include all DRAM memory regions ([e803542](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e80354212f591c8813dec27353e8241e03155b4c)) + - fix NULL pointer dereference issue ([a42b426](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a42b426b8548e3304e995f1a49d2470d71072949)) + - op-tee sp manifest doesn't map gicd ([69cde5c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/69cde5cd9563f0c665862f1e405ae8e8d2818c6e)) + + - **Morello** + + - change the AP runtime UART address ([07302a2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07302a23ec1af856b3d4de0439161a8c23414f84)) + - fix SoC reference clock frequency ([e8b7a80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8b7a80436c2bc81c61fc4703d6580f2fe9226a9)) + - include errata workaround for 1868343 ([f94c84b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f94c84baa2a2bad75397b0ec6a0922fe8a475847)) + + - **SGI** + + - disable SVE for NS to support SPM_MM builds ([78d7e81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78d7e819798ace643b6e22025dc76aedb199bbd5)) + + - **TC** + + - remove the bootargs node ([68fe3ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68fe3cec25bc9ea4e1bafdb1d9f5315e245d650b)) + + - **Corstone-1000** + + - change base address of FIP in the flash ([1559450](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1559450132c5e712f4d6896e53e4f1cb521fa465)) + + - **Broadcom** + + - allow build to specify mbedTLS absolute path ([903d574](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/903d5742953d9d4b224e71d8b1e62635e83f44a9)) + - fix the build failure with mbedTLS config ([95b5c01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95b5c0126b802b894ea0177d973978e06b6a254d)) + + - **Intel** + + - add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD ([ac097fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac097fdf07ad63b567ca751dc518f8445a0baef6)) + - allow non-secure access to FPGA Crypto Services (FCS) ([4837a64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4837a640934630f8034ceec1bb84cc40673d8a6b)) + - always set doorbell to SDM after sending command ([e93551b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e93551bb3bd8ac43779fa70c7363ee2568da45ca)) + - assert if bl_mem_params is NULL pointer ([35fe7f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35fe7f400a7f1d65ff2fee5531d20f6c2f3e6f39)) + - bit-wise configuration flag handling ([276a436](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/276a43663e8e315fa1bf0aa4824051d88705858b)) + - change SMC return arguments for INTEL_SIP_SMC_MBOX_SEND_CMD ([108514f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/108514ff7160a86efb791449a4635ffe0f9fdf2c)) + - configuration status based on start request ([e40910e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e40910e2dc3fa59bcce83ec1cf9a33b3e85012c4)) + - define macros to handle buffer entries ([7db1895](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7db1895f0be2f8c6710bf51d8441d5e53e3ef0fe)) + - enable HPS QSPI access by default ([000267b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/000267be22d3c0077c0fd0a8377ceeed5aada4c3)) + - extend SDM command to return the SDM firmware version ([c026dfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c026dfe38cfae379457a6ef53130bd5ebc9d7808)) + - extending to support large file size for AES encryption and decryption ([dcb144f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcb144f1fbcef73ddcc448d5ed6134aa279069b6)) + - extending to support large file size for SHA-2 ECDSA data signing and signature verifying ([1d97dd7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d97dd74cd128edd7ad45b725603444333c7b262)) + - extending to support large file size for SHA2/HMAC get digest and verifying ([70a7e6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70a7e6af958f3541476a8de6baac8e376fcc67f9)) + - fix bit masking issue in intel_secure_reg_update ([c9c0709](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9c070994caedf123212aad23b6942122c5dd793)) + - fix configuration status based on start request ([673afd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/673afd6f8e7266900b00a7cbeb275fe1a3d69cce)) + - fix ddr address range checker ([12d71ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12d71ac6627bb6822a0314e737794a8503df79dd)) + - fix ECC Double Bit Error handling ([c703d75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c703d752cce4fd101599378e72db66ccf53644fa)) + - fix fpga config write return mechanism ([ef51b09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef51b097bfa906bf1cee8ee641a1b7bcc8c5f3c0)) + - flush dcache before sending certificate to mailbox ([49d44ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d44ec5f357b1bcf8eae9e91fbd72aef09e00dd)) + - get config status OK status ([07915a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07915a4fd5848fbac69dcbf28f00353eed10a942)) + - introduce a generic response error code ([651841f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/651841f20110ce6fac650e3ac47b0a9cce18e6f3)) + - make FPGA memory configurations platform specific ([f571183](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f571183b066b1a91b7fb178c3aad9d6360d1918c)) + - modify how configuration type is handled ([ec4f28e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec4f28ecec8887a685d6119c096ad346da1ea53e)) + - null pointer handling for resp_len ([a250c04](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a250c04b0cc807f626df92a7091ff13b3a3aa9ed)) + - refactor NOC header ([bc1a573](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc1a573d5519f121cb872fce1d88fe2e0db07b2c)) + - reject non 4-byte align request size for FPGA Crypto Service (FCS) ([52ed157](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52ed157fd66812debb13a792c21f763de01aef70)) + - remove redundant NOC header declarations ([58690cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/58690cd629b4ccdefe5313f805219598074a3501)) + - remove unused printout ([0d19eda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d19eda0dd2ffae27d0551b1f0a06a2b8f96c853)) + - update certificate mask for FPGA Attestation ([fe5637f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe5637f27aebfdab42915c2ced2c34d8685ee2bb)) + - update encryption and decryption command logic ([02d3ef3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02d3ef333d4a0a07a3e40defb12a8cde3a7cba03)) + - use macro as return value ([e0fc2d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0fc2d1907b1c8a062c44a435be77a12ffeed84b)) + + - **Marvell** + + - **Armada** + + - **A3K** + + - change fatal error to warning when CM3 reset is not implemented ([30cdbe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30cdbe7043832f7bd96b40294ac062a8fc9c540f)) + - fix comment about BootROM address range ([5a60efa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5a60efa12a57cde98240f861e45609cb9b94d58d)) + + - **Mediatek** + + - **MT8186** + + - remove unused files in drivers/mcdi ([bc714ba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc714bafe7ae8ca29075ba9bf3985c0e15ae0f64)) + - extend MMU region size ([0fe7ae9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe7ae9c64aa6f6d5b06a80de9c88081057d5dbe)) + + - **NVIDIA** + + - **Tegra** + + - **Tegra 194** + + - remove incorrect erxctlr assert ([e272c61](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e272c61ce8185deb397dcf168ec72bdaa5926a33)) + + - **NXP** + + - fix total dram size checking ([0259a3e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0259a3e8282ed17c1d378a27f820f44b3bebab07)) + - increase soc name maximum length ([3ccd7e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ccd7e45a2c3ff9fa7794f0284c9d0298e7cb982)) + + - **i.MX** + + - **i.MX 8M** + + - check the validation of domain id ([eb7fb93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb7fb938c3ce34ccfb143ae8ba695df899098436)) + + - **i.MX 8M Plus** + + - change the BL31 physical load address ([32d5042](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d5042204e8b41caa4c0c1ed5b48bad9f1cb1b5)) + + - **Layerscape** + + - fix build issue of mmap_add_ddr_region_dynamically ([e2818d0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2818d0afc20a60d302f85f4c915e4ae4cc3cb9c)) + - fix coverity issue ([5161cfd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5161cfde9bfaa3a715d160fcd4870f276adad332)) + - update WA for Errata A-050426 ([72feaad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72feaad980cdc472868bc95914202bf57ed51b2d)) + + - **LX2** + + - drop erratum A-009810 ([e36b0e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e36b0e4910aea56f90a6ab9b8cf3dc4008220031)) + + - **Renesas** + + - **R-Car** + + - **R-Car 3** + + - change stack size of BL31 ([d544dfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d544dfcc4959d203b06dbfb85fb0ad895178b379)) + - fix SYSTEM_OFF processing for R-Car D3 ([1b49ba0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b49ba0fde5eb9e47fe50152c192579101feb718)) + - fix to bit operation for WUPMSKCA57/53 ([82bb6c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82bb6c2e88314a5b3f2326c95095c3b20a389947)) + + - **Socionext** + + - **Synquacer** + + - initialise CNTFRQ in Non Secure CNTBaseN ([4d4911d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d4911d77d4d59c7dd18d7fc3724ddb1fa3582b7)) + + - **ST** + + - add missing header include ([b1391b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b1391b294ca7803f46bc47048b4a02a15dda9a16)) + - don't try to read boot partition on SD cards ([9492b39](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9492b391a35c66e1e7630e95347259191b28314d)) + - fix NULL pointer dereference issues ([2deff90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2deff904a953c6a87331ab6830ab80e3889d9e23)) + - manage UART clock and reset only in BL2 ([9e52d45](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9e52d45fdf619561e0a7a833b77aaacc947a4dfd)) + - remove extra chars from dtc version ([03d2077](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03d20776efc20a04a5191a4f39965079a4d60b3c)) + + - **ST32MP1** + + - add missing debug.h ([356ed96](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/356ed961184847dcd088cfcda44b71eeb0ef2377)) + - correct dtc version check ([429f10e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/429f10e3367748abd33b4f6f9ee362c0ba74dd95)) + - correct include order ([ff7675e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff7675ebf94999618dbde14bb59741cefb2b2edd)) + - correct types in messages ([43bbdca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43bbdca04f5a20bb4e648e18fc63061b6a6e4ecf)) + - deconfigure UART RX pins ([d7176f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7176f0319cd399aae9a906e5d78e67b32e183f5)) + - do not reopen debug features ([21cfa45](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21cfa4531a76a7c3cad00e874400b97e2f68723c)) + - fix enum prints ([ceab2fc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ceab2fc3442dbda1c4beaff3c4fe708a04c02303)) + - include assert.h to fix build failure ([570c71b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/570c71b20a195ade510f5d584c69325d2634c50b)) + - remove interrupt_provider warning for dtc ([ca88c76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca88c761d34854ed3e0b16b9c5f39b0790d320ab)) + - restrict DEVICE2 mapping in BL2 ([db3e0ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db3e0ece7157181a3529d14172368003eb63dc30)) + - rework switch/case for MISRA ([f7130e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f7130e81cf9c3682232bb9319b1798184b44920f)) + - set reset pulse duration to 31ms ([9a73a56](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a73a56c353d32742e03b828647562bdbe2ddbb2)) + + - **Xilinx** + + - fix coding style violations ([bb1768c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb1768c67ea06ac466e2cdc7e5338c3d23dac79d)) + - fix mismatching function prototype ([81333ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81333eac716b25a9fd112cc4f5990e069f3bdb40)) + + - **Versal** + + - resolve misra R10.1 in pm services ([775bf1b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/775bf1bbd32c2df47f4ff597eb8a452d2983e590)) + - resolve misra R10.3 ([b2bb3ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2bb3efb8f590f31b1205c51d56be1dd6f473fbb)) + - resolve misra R10.3 in pm services ([5d1c211](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d1c211e225d40d2926bf34483c90f907a6c5dc3)) + - resolve misra R10.6 ([93d4625](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93d462562727f4f428e6f975a972226dafbfd305)) + - resolve misra R10.6 in pm services ([fa98d7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa98d7f2f8752e37f740b43f533547288552a393)) + - resolve misra R14.4 ([a62c40d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a62c40d42703d5f60a8d80938d2cff721ee131bd)) + - resolve misra R15.6 ([b9fa2d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9fa2d9fc154feffe78e677ace54b0e34f011439)) + - resolve misra R15.6 in pm services ([4156719](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4156719550ceddf5b1b4a47464fb32f7506e0dca)) + - resolve misra R15.7 ([bc2637e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc2637e3799dbc9642447ddb719e0262347b1309)) + - resolve misra R16.3 in pm services ([27ae531](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/27ae5310883b0db7d4e2dd4fbc1fd58e675f75b5)) + - resolve misra R17.7 ([526a1fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/526a1fd1472874561988777f8ecd8b87734a0671)) + - resolve misra R20.7 in pm services ([5dada62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5dada6227b949ef702bfab7986bc083689afdaf7)) + - resolve misra R7.2 ([0623dce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0623dcea0f6e7a5c9d65413445df8a96a2b40d42)) + - fix coverity scan warnings ([0b15187](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b15187225a9134e3acbc7693646b21d43617b3b)) + - fix the incorrect log message ([ea04b3f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea04b3fe183b6661f656b4cc38cb93a73d9bc202)) + + - **ZynqMP** + + - define and enable ARM_XLAT_TABLES_LIB_V1 ([c884c9a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c884c9a55b167383ff3d96d2d0a30ac6842bcc86)) + - query node status to power up APU ([b35b556](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b35b556718b60b78cb5d96b0c137e2fe82eb0086)) + - resolve misra 7.2 warnings ([5bcbd2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bcbd2de127292f3ad076217e08468388c6844b0)) + - resolve misra 8.3 warnings ([944e7ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/944e7ea94f2594e2b128c671cf7415265302596b)) + - resolve misra R10.3 ([2b57da6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b57da6c91ebe14588e63e5a24f31ef32711eca2)) + - resolve misra R14.4 warnings ([dd1fe71](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd1fe7178b578916b1e133b7c65c183e1f994371)) + - resolve misra R15.6 warnings ([eb0d2b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb0d2b17722c01a22bf3ec1123f7bed2bf891b09)) + - resolve misra R15.7 warnings ([16de22d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16de22d037644359ef2a04058134f9c326b36633)) + - resolve misra R16.3 warnings ([e7e5d30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7e5d30308ccfb931f7b6d0afa6c5c23971e95c0)) + - resolve misra R8.4 warnings ([610eeac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/610eeac89438d603435bde694eb4ddab07f46e45)) + - update the log message to verbose ([1277af9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1277af9bacca36b46d7aa341187bb3abef84332f)) + - use common interface for eemi apis ([a469c1e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a469c1e1f4c1cd69f98ce45d6e0709de091b8cb3)) + +- **Bootloader Images** + + - **BL1** + + - invalidate SP in data cache during secure SMC ([f1cbbd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1cbbd6332bb85672dc72cbcc4ac7023323c6936)) + + - **BL2** + + - correct messages with image_id ([e4c77db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4c77db9c80d87009611a3079454877e6ce45a04)) + - define RAM_NOLOAD for XIP ([cc562e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc562e74101d800b0b0ee3422fb7f4f8321ae2b7)) + +- **Services** + + - **RME** + + - enable/disable SVE/FPU for Realms ([a4cc85c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4cc85c129d031d9c887cf59b1baeaef18a43010)) + - align RMI and GTSI FIDs with SMCCC ([b9fd2d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9fd2d3ce3d4e543a2e04dc237cd4e7ff7765c7a)) + - preserve x4-x7 as per SMCCCv1.1 ([1157830](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11578303fd04a8da36fddb5e6de44f026bf4d24c)) + + - **TRP** + + - Distinguish between cold and warm boot ([00e8113](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00e8113145aa12d89db72068bdd3157f08575d14)) + + - **SPM** + + - **EL3 SPMC** + + - fix incorrect FF-A version usage ([25eb2d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25eb2d41a6d2ede1e945bbc67ae3f740b92a40bb)) + - fix FF-A memory transaction validation ([3954bc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3954bc3c03439dbdc7029cf2418c79a037918ce4)) + +- **Libraries** + + - **CPU Support** + + - workaround for Cortex-A710 2282622 ([ef934cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef934cd17c30dcc39cd9022a1c4e9523ec8ba617)) + - workaround for Cortex-A710 erratum 2267065 ([cfe1a8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfe1a8f7123f0dc8376b2075cc6e8e32b13739b2)) + - workaround for Cortex A78 AE erratum 2376748 ([92e8708](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92e870843e9bd654fd1041d66f284c19ca9c0d4f)) + - workaround for Cortex A78 AE erratum 2395408 ([3f4d81d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f4d81dfd26649fbcbbbe993a9f0236f5bb07c8a)) + - workaround for Cortex X2 erratum 2002765 ([34ee76d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34ee76dbdfeee85f123cb903ea95dbee5e9a44a5)) + - workaround for Cortex X2 erratum 2058056 ([e16045d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e16045de50e8b430e6601ba0e1e47097d8310f3d)) + - workaround for Cortex X2 erratum 2083908 ([1db6cd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1db6cd60279e2d082876692a65cf9c532f506a69)) + - workaround for Cortex-A510 erratum 1922240 ([8343563](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83435637bfafbf1ce642a5fabb52e8d7b2819e36)) + - workaround for Cortex-A510 erratum 2041909 ([e72bbe4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e72bbe47ba7f2a0087654fd99ae24b5b7b444943)) + - workaround for Cortex-A510 erratum 2042739 ([d48088a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d48088acbe400133037ae74acf1b722b059119bb)) + - workaround for Cortex-A510 erratum 2172148 ([c0959d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0959d2c460cbf7c14e7ba2a57d69ecddae80fd8)) + - workaround for Cortex-A510 erratum 2218950 ([cc79018](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc79018b71e45acb524fc5d429d394497ad53646)) + - workaround for Cortex-A510 erratum 2250311 ([7f304b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f304b02a802b7293d7a8b4f4030c5ff00158404)) + - workaround for Cortex-A510 erratum 2288014 ([d5e2512](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5e2512c6b86409686f5d1282922ebdf72459fc2)) + - workaround for Cortex-A710 erratum 2008768 ([af220eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af220ebbe467aa580e6b9ba554676f78ffec930f)) + - workaround for Cortex-A710 erratum 2136059 ([8a855bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a855bd24329e081cf13a257c7d2dc3ab4e5dcca)) + - workaround for Cortex-A78 erratum 2376745 ([5d796b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d796b3a25150faff68013880f5a9350cbc53889)) + - workaround for Cortex-A78 erratum 2395406 ([3b577ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b577ed53d104cfb324390b7519da5e7744d1001)) + - workaround for Cortex-X2 errata 2017096 ([e7ca443](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7ca4433fa591233e7e2912b689ab56e531f9775)) + - workaround for Cortex-X2 errata 2081180 ([c060b53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c060b5337a43cd42f55b99d83096bb44b51b5335)) + - workaround for Cortex-X2 erratum 2147715 ([63446c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63446c27d11453faacfddecffa44d3880615d412)) + - workaround for Cortex-X2 erratum 2216384 ([4dff759](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4dff7594f94f1e788aef709cc5b3d079693b6242)) + - workaround for DSU-110 erratum 2313941 ([7e3273e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e3273e8e4dca44e7cb88a827b94e662fa8f83e9)) + - workaround for Rainier erratum 1868343 ([a72144f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a72144fb7a30c2782a583a3b0064e741d1fe2c9f)) + - workarounds for cortex-x1 errata ([7b76c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b76c20d8eb4271b381371ce0d510fbe6ad825bf)) + - use CPU_NO_EXTRA3_FUNC for all variants ([b2ed998](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2ed99894d326993961680fb8e786c267a712400)) + + - **EL3 Runtime** + + - set unset pstate bits to default ([7d33ffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d33ffe4c116506ed63e820d5b6edad81680cd11)) + + - **Context Management** + + - add barrier before el3 ns exit ([0482503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04825031b2384a08504821f39e98e23bb6f93f11)) + - remove registers accessible only from secure state from EL2 context ([7f41bcc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f41bcc76d8857b4678c90796ebd85794ff3ee5f)) + - refactor the cm_setup_context function ([2bbad1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bbad1d126248435e26f9d0d9f5920d8806148d7)) + - remove initialization of EL2 registers when EL2 is used ([fd5da7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd5da7a84731e9687f56c263ff3aa8ebed75075a)) + - add cm_prepare_el3_exit_ns function ([8b95e84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b95e8487006ff77a7d84fba5bd20ba7e68d8330)) + - refactor initialization of EL1 context registers ([b515f54](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b515f5414b00a8b7ca9b21363886ea976bd19914)) + + - **FCONF** + + - correct image_id type in messages ([cec2fb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cec2fb2b1a8359bf1f349a5b8c8a91a1845f4ca1)) + + - **PSCI** + + - correct parent_node type in messages ([b9338ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9338eee7fbcac7f4b55f27b064572e847810422)) + + - **GPT** + + - rework delegating/undelegating sequence ([6a00e9b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a00e9b0c8c37fc446f83ef63e95a75353e31e8b)) + + - **Translation Tables** + + - fix bug on VERBOSE trace ([956d76f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/956d76f69d0c96829784c5a6d16aa79e4e0ecab1)) + + - **Standard C Library** + + - correct some messages ([a211fde](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a211fde940d4dbd8e95e4f352af2a066a4f89f30)) + - fix snprintf corner cases ([c1f5a09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1f5a0925ddf84981d9e176d146bfddb48eb45d1)) + - limit snprintf radix value ([b30dd40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b30dd4030dcef950eac05393013ee019c3cb3205)) + - snprintf: include stdint.h ([410c925](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/410c925ab31693dc74d654ff9167c8eed3ec5a62)) + + - **Locks** + + - add __unused for clang ([5a030ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5a030ce4aed271344087bca723903e10fef59ac9)) + +- **Drivers** + + - **FWU** + + - rename is_fwu_initialized ([aae7c96](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aae7c96de63914c954f0fc64cd795844832483fc)) + + - **I/O** + + - **MTD** + + - correct types in messages ([6e86b46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e86b462490429fee6db877338a649b0e199b0ec)) + + - **Measured Boot** + + - add RMM entry to event_log_metadata ([f4e3e1e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4e3e1e85f64d8930e89c1396bc9785512f656bd)) + + - **MTD** + + - correct types in messages ([6e86b46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e86b462490429fee6db877338a649b0e199b0ec)) + + - **SCMI** + + - add missing \n in ERROR message ([0dc9f52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0dc9f52a2a9f0b9686c65dd60c84e0bcca552144)) + - make msg_header variable volatile ([99477f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99477f051ef857a1e0600cb98858fc74c007e1ff)) + - use same type for message_id ([2355ebf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2355ebff6f6312086868f44b8ad7f821f6385208)) + + - **UFS** + + - delete call to inv_dcache_range for utrd ([c5ee858](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c5ee8588bf9a36075723e5aacceefa93fd2de8c9)) + - disables controller if enabled ([b3f03b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b3f03b20135fc5fcd5e6ec7e5ca49f1e59b5602e)) + - don't zero out buf before ufs read ([2ef6b8d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ef6b8d378e7f7c1b1eb7abe176989c3f996f2dc)) + - don't zero out the write buffer ([cd3ea90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd3ea90b200534b8c9d81619731c9ce198478a3c)) + - fix cache maintenance issues ([38a5ecb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38a5ecb756e217a80ed951747797ab150449ee9b)) + - move nutrs assignment to ufs_init ([0956319](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0956319b580726029ddc4e00cde6c5a348b99052)) + - read and write attribute based on spec ([a475518](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a475518337e15935469543b1cce353e5b337ef52)) + + - **Arm** + + - **GIC** + + - **GICv3** + + - fix iroute value wrong issue ([65bc2d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/65bc2d224b836c230888796c4eda455997dccd8b)) + + - **TZC** + + - **TZC-400** + + - correct message with filter ([bdc88d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdc88d2154448957f452cb472ff95ccec5808ca1)) + + - **Marvell** + + - **COMPHY** + + - change reg_set() / reg_set16() to update semantics ([95c26d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95c26d6489bd8b2fc8b8e14bc2da5d2918055acc)) + + - **Armada 3700** + + - drop MODE_REFDIV constant ([9fdecc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9fdecc72f0fce17ca2cd8e4c3b26c01262166d10)) + - fix comment about COMPHY status register ([4bcfd8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bcfd8c02e3e3aa27b55dedeed11fb16bac991a9)) + - fix comments about selector register values ([71183ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71183ef6654c2a485458307a84ce7c473524689a)) + - fix Generation Setting registers names ([e5a2aac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5a2aac5bbc6dedb20edcc8e7850be2813cb668b)) + - fix PIN_PU_IVREF register name ([c9f138e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9f138ebfef90d5b7b5651f06efd81bcbc55366b)) + - fix reference clock selection value names ([6ba97f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ba97f83dbb314b076588b97415a4078924e1903)) + - fix SerDes frequency register value name ([bdcf44f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdcf44f1af496e06b693b781fe16bbc2a05fa365)) + - use reg_set() according to update semantics ([4d01bfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d01bfe66522b13f0d9042206e986551c94fc01e)) + + - **Armada** + + - **A3K** + + - **A3720** + + - configure UART after TX FIFO reset ([15546db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15546dbf40e5ea81a982a1e6d1e5ba729b06ae51)) + - do external reset during initialization ([0ee80f3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ee80f35a28d651d243a6d56678800f9697d14c0)) + + - **NXP** + + - ddr: corrects mapping of HNFs nodes ([e3a2349](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e3a234971abb2402cbf376eca6fcb657a7709fae)) + + - **QSPI** + + - fix include path for QSPI driver ([ae95b17](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae95b1782b7a3ab9bbe46ae9ab31f48fb6ebe137)) + + - **NXP Crypto** + + - refine code to avoid hang issue for some of toolchain ([fa7fdfa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa7fdfabf07d91439b0869ffd8e805f0166294bf)) + + - **DDR** + + - fix coverity issue ([f713e59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f713e5954e0906443cd20ae97e229ddbb9ab7005)) + + - **ST** + + - **Clock** + + - check _clk_stm32_get_parent return ([b8eab51](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b8eab512bf9d253f96b0333ee0f1bffa1afc3170)) + - correct stm32_clk_parse_fdt_by_name ([7417cda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7417cda6aeaf6abf48dfbe22dc965b626f61c613)) + - correct types in error messages ([44fb470](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44fb470b7f298645ac31ada4491553824d77d934)) + - initialize pllcfg table ([175758b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/175758b2777eb6df3c4aefd79448e97e76a15272)) + - print enums as unsigned ([9fa9a0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9fa9a0c55cc830e609415d2cedd2d34fcbec1008)) + + - **DDR** + + - add missing debug.h ([15ca2c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15ca2c5e14abe415e70d08fb595973dd3e3b0af9)) + - correct DDR warnings ([a078134](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a078134e2305ca5695731bc275a5ca892cc38880)) + + - **FMC** + + - fix type in message ([afcdc9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afcdc9d8d71e2b60071d3d34704f0e598e67a514)) + + - **SDMMC2** + + - check regulator enable/disable return ([d50e7a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d50e7a71cb5f8ecfbe2eb69c163d532bab82cbf0)) + - correct cmd_idx type in messages ([bc1c98a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc1c98a8c79b6f72395123ea8ed857a488746d4b)) + + - **ST PMIC** + + - add static const to pmic_ops ([57e6018](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57e6018305a97f4e3627d16d8b1886419f274b4a)) + - correct verbose message ([47065ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47065ffe44c701b231322ec7160c8624d50a9deb)) + + - **SPI** + + - always check SR_TCF flags in stm32_qspi_wait_cmd() ([55de583](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55de58323e458b38b455439a8846cb663deb5508)) + - remove SR_BUSY bit check before sending command ([5993b91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5993b9157fd049d06194083032771ffcf73da086)) + + - **UART** + + - correctly fill BRR register ([af7775a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af7775ab535138ff49643f749110dca143d4122c)) + + - **USB** + + - correct type in message ([bd9cd63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd9cd63ba096cb16161efa4df40f957421660df1)) + +- **Miscellaneous** + + - **AArch64** + + - fix encodings for MPAMVPM* registers ([e926558](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e92655849d0a9e5893eb2d7e5f42cf8b931d4db6)) + + - **FDTs** + + - **STM32MP1** + + - correct memory mapping for STM32MP13 ([99605fb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99605fb1166794db1dedf1b7280cb184945c229c)) + - remove mmc1 alias if not needed ([a0e9724](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0e972438b99012da422411c8e504a19bdad44a2)) + + - **PIE** + + - align fixup_gdt_reloc() for aarch64 ([5ecde2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ecde2a271ac0f3762c16f5a277a70e55e172f0b)) + - do not skip __RW_END__ address during relocation ([4f1a658](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f1a658f899a169e702b1c7146b59f7c04b0338b)) + + - **Security** + + - apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 ([9b2510b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b2510b69de26cc7f571731b415f6dec82669b6c)) + - loop workaround for CVE-2022-23960 for Cortex-A76 ([a10a5cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a10a5cb609045de216c01111ec3fcf09a092da0b)) + - report CVE 2022 23960 missing for aarch32 A57 and A72 ([2e5d7a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e5d7a4b6b26d9d8b6c8e580c33d877e591b1fb3)) + - update Cortex-A15 CPU lib files for CVE-2022-23960 ([187a617](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/187a61761ef5d59bed0c94cca725bd6f116f64d0)) + - workaround for CVE-2022-23960 ([c2a1521](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c2a15217c3053117f4d39233002cb1830fa96670)) + - workaround for CVE-2022-23960 ([1fe4a9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1fe4a9d181ead0dcb2bc494e90552d3e7f0aaf4c)) + - workaround for CVE-2022-23960 for A76AE, A78AE, A78C ([5f802c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f802c8832f3c5824ca6de17593205ebbf8bf585)) + - workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72 ([be9121f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be9121fd311ff48c94f3d90fe7efcf84586119e4)) + - workaround for CVE-2022-23960 for Cortex-X1 ([e81e999](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e81e999b9da33ab5d2d3e5185b1ad7c46046329c)) + +- **Tools** + + - **NXP Tools** + + - fix create_pbl print log ([31af441](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31af441a0445d4a5e88ddcc371c51b3701c25839)) + - fix tool location path for byte_swape ([a89412a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a89412a649020367a3ed0f87658ee131cd3dcd18)) + + - **Firmware Image Package Tool** + + - avoid packing the zero size images in the FIP ([ab556c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab556c9c646f1b5f1b500449a5813a4eecdc0302)) + - respect OPENSSL_DIR ([0a956f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a956f81805b46b1530f30dd79d16950dc491a7b) + + - **Secure Partition Tool** + + - add leading zeroes in UUID conversion ([b06344a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b06344a3f2c5a0fede3646627f37d1fce3d3d585)) + - update Optee FF-A manifest ([ca0fdbd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca0fdbd8e0d625ece0f87ca16eacabf13db70921)) + + - **Certificate Creation Tool** + + - let distclean Makefile target remove the cert_create tool ([e15591a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e15591aaf47ab45941f0d7a03abf3e4a830ac1d9)) + +- **Dependencies** + + - **commitlint** + + - change scope-case to lower-case ([804e52e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/804e52e9a770de72913f27b5bc9e7dd965e114c5)) + +## [2.6.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.5..refs/tags/v2.6) (2021-11-22) ### ⚠ BREAKING CHANGES @@ -63,15 +1253,18 @@ issues in each release of Trusted Firmwa - enable SVE for the secure world ([0c5e7d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c5e7d1ce376cabcebebc43dbf238fe4482ab2dc)) + - **System Register Trace Extensions (FEAT_ETMv4, FEAT_ETE and FEAT_ETEv1.1)** + + - enable trace system registers access from lower NS ELs ([d4582d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d4582d30885673987240cf01fd4f5d2e6780e84c)) + - initialize trap settings of trace system registers access ([2031d61](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2031d6166a58623ae59034bc2353fcd2fabe9c30)) + - **Trace Buffer Extension (FEAT_TRBE)** - enable access to trace buffer control registers from lower NS EL ([813524e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/813524ea9d2e4138246b8f77a772299e52fb33bc)) - initialize trap settings of trace buffer control registers access ([40ff907](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40ff90747098ed9d2a09894d1a886c10ca76cee6)) - - **Self-hosted Trace Extensions (FEAT_TRF)** + - **Self-hosted Trace Extension (FEAT_TRF)** - - enable trace system registers access from lower NS ELs ([d4582d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d4582d30885673987240cf01fd4f5d2e6780e84c)) - - initialize trap settings of trace system registers access ([2031d61](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2031d6166a58623ae59034bc2353fcd2fabe9c30)) - enable trace filter control register access from lower NS EL ([8fcd3d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8fcd3d9600bb2cb6809c6fc68f945ce3ad89633d)) - initialize trap settings of trace filter control registers access ([5de20ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de20ece38f782c8459f546a08c6a97b9e0f5bc5)) @@ -324,6 +1517,7 @@ issues in each release of Trusted Firmwa - add support for Hayes CPU ([7bd8dfb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7bd8dfb85a8bf5c22d6a39f4538b89cc748090d1)) - add support for Hunter CPU ([fb9e5f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb9e5f7bb76e9764b3ecd7973668c851015fa1b4)) + - add support for Demeter CPU ([f4616ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4616efafbc1004f1330f515b898e7617e338875)) - workaround for Cortex A78 AE erratum 1941500 ([47d6f5f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47d6f5ff16d1f2ad009d630a381054b10fa0a06f)) - workaround for Cortex A78 AE erratum 1951502 ([8913047](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8913047a52e646877812617a2d98cff99494487b)) @@ -979,7 +2173,7 @@ issues in each release of Trusted Firmwa - do not check merge commits ([77a0a7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77a0a7f1d96b188849d1d8d8884b3c93857d3f69)) -## 2.5.0 (2021-05-17) +## [2.5.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.4..refs/tags/v2.5) (2021-05-17) ### New Features @@ -1543,7 +2737,7 @@ issues in each release of Trusted Firmwa - Optimized the code to avoid unnecessary attempts to create non-requested certificates -## 2.4.0 (2020-11-17) +## [2.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.3..refs/tags/v2.4) (2020-11-17) ### New Features @@ -1968,7 +3162,7 @@ issues in each release of Trusted Firmwa being worked around by disabling the warning for the platform until the underlying issue is resolved in libfdt -## 2.3 (2020-04-20) +## [2.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.2..refs/tags/v2.3) (2020-04-20) ### New Features @@ -2343,7 +3537,7 @@ issues in each release of Trusted Firmwa - mediatek/mt6795: This platform does not build in this release -## 2.2 (2019-10-22) +## [2.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.1..refs/tags/v2.2) (2019-10-22) ### New Features @@ -2654,7 +3848,7 @@ issues in each release of Trusted Firmwa - mediatek/mt6795: This platform does not build in this release -## 2.1 (2019-03-29) +## [2.1.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.0..refs/tags/v2.1) (2019-03-29) ### New Features @@ -3056,7 +4250,7 @@ issues in each release of Trusted Firmwa - mediatek/mt6795: This platform does not build in this release -## 2.0 (2018-10-02) +## [2.0.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.6..refs/tags/v2.0) (2018-10-02) ### New Features @@ -3087,7 +4281,7 @@ issues in each release of Trusted Firmwa to be working after the removal of the deprecated interfaces although they do build. -## 1.6 (2018-09-21) +## [1.6.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.5..refs/tags/v1.6) (2018-09-21) ### New Features @@ -3294,7 +4488,7 @@ issues in each release of Trusted Firmwa build process is skipped when running on a Windows host. Known issue from 1.5 version. -## 1.5 (2018-03-20) +## [1.5.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.4..refs/tags/v1.5) (2018-03-20) ### New features @@ -3551,7 +4745,7 @@ issues in each release of Trusted Firmwa - DTB creation not supported when building on a Windows host. This step in the build process is skipped when running on a Windows host. -## 1.4 (2017-07-07) +## [1.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.3..refs/tags/v1.4) (2017-07-07) ### New features @@ -3818,7 +5012,7 @@ issues in each release of Trusted Firmwa platform, please use GCC compiler version of at least 5.0. See [PR#1002] for more details. -## 1.3 (2016-10-13) +## [1.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.2..refs/tags/v1.3) (2016-10-13) ### New features @@ -4017,7 +5211,7 @@ issues in each release of Trusted Firmwa the TF-A build system interprets as errors. - TBBR is not currently supported when running TF-A in AArch32 state. -## 1.2 (2015-12-22) +## [1.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.1..refs/tags/v1.2) (2015-12-22) ### New features @@ -4154,7 +5348,7 @@ issues in each release of Trusted Firmwa incomplete for PSCI, the TSP(D) and the Juno platform. - Building TF-A with compiler optimisations disabled (`-O0`) fails. -## 1.1 (2015-02-04) +## [1.1.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v1.0..refs/tags/v1.1) (2015-02-04) ### New features @@ -4293,7 +5487,7 @@ issues in each release of Trusted Firmwa its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. - The Juno-specific firmware design documentation is incomplete. -## 1.0 (2014-08-28) +## [1.0.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.4..refs/tags/v1.0) (2014-08-28) ### New features @@ -4439,7 +5633,7 @@ issues in each release of Trusted Firmwa A similar change can be made to the other Cortex-A57-A53 Base FVP variants. -## 0.4 (2014-06-03) +## [0.4.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.3..refs/tags/v0.4) (2014-06-03) ### New features @@ -4548,7 +5742,7 @@ issues in each release of Trusted Firmwa - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. -## 0.3 (2014-02-28) +## [0.3.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v0.2..refs/tags/v0.3) (2014-02-28) ### New features @@ -4685,7 +5879,7 @@ releases of TF-A. - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. -## 0.2 (2013-10-25) +## [0.2.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b825dc642cb6eb9a060e54bf8d69288fbee4904..refs/tags/v0.2) (2013-10-25) ### New features @@ -4734,7 +5928,7 @@ releases of TF-A. ______________________________________________________________________ -*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.* [mbed tls releases]: https://tls.mbed.org/tech-updates/releases [pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193 diff -pruN 2.6+dfsg-1/docs/components/fconf/fconf_properties.rst 2.7.0+dfsg-2/docs/components/fconf/fconf_properties.rst --- 2.6+dfsg-1/docs/components/fconf/fconf_properties.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/components/fconf/fconf_properties.rst 2022-06-01 15:02:46.000000000 +0000 @@ -30,3 +30,10 @@ contains, and must be formed with the fo - value type: - Image ID of the configuration. +- ns-load-address [optional] + - value type: + - Physical loading base address of the configuration in the non-secure + memory. + Only needed by those configuration files which require being loaded + in secure memory (at load-address) as well as in non-secure memory + e.g. HW_CONFIG diff -pruN 2.6+dfsg-1/docs/components/ffa-manifest-binding.rst 2.7.0+dfsg-2/docs/components/ffa-manifest-binding.rst --- 2.6+dfsg-1/docs/components/ffa-manifest-binding.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/components/ffa-manifest-binding.rst 2022-06-01 15:02:46.000000000 +0000 @@ -4,11 +4,8 @@ FF-A manifest binding to device tree This document defines the nodes and properties used to define a partition, according to the FF-A specification. -Version 1.0 ------------ - Partition Properties -^^^^^^^^^^^^^^^^^^^^ +-------------------- - compatible [mandatory] - value type: @@ -137,20 +134,30 @@ Partition Properties - gp-register-num - value type: - - Presence of this field indicates that the partition expects the - ffa_init_info structure to be passed in via the specified general purpose - register. - The field specifies the general purpose register number but not its width. + - The field specifies the general purpose register number but not its width. The width is derived from the partition's execution state, as specified in the partition properties. For example, if the number value is 1 then the general-purpose register used will be x1 in AArch64 state and w1 in AArch32 state. + Presence of this field indicates that the partition expects the address of + the FF-A boot information blob to be passed in the specified general purpose + register. - stream-endpoint-ids - value type: - List of tuples, identifying the IDs this partition is acting as proxy for. +- power-management-messages + - value type: + - Specifies which power management messages a partition subscribes to. + A set bit means the partition should be informed of the power event, clear + bit - should not be informed of event: + + - Bit[0]: CPU_OFF + - Bit[1]: CPU_SUSPEND + - Bit[2]: CPU_SUSPEND_RESUME + Memory Regions -------------- @@ -174,13 +181,14 @@ Memory Regions - 0x1: Read - 0x2: Write - 0x4: Execute + - 0x8: Security state - base-address - value type: - Base address of the region. The address must be aligned to the translation granule size. The address given may be a Physical Address (PA), Virtual Address (VA), or - Intermediate Physical Address (IPA). Refer to the FFA specification for + Intermediate Physical Address (IPA). Refer to the FF-A specification for more information on the restrictions around the address type. If the base address is omitted then the partition manager must map a memory region of the specified size into the partition's translation regime and @@ -198,14 +206,10 @@ Device Regions - value type: - Name of the device region e.g. for debugging purposes. -- reg [mandatory] - - value type: - - A (address, num-pages) pair describing the device, where: - - - address: The physical base address value of the device MMIO - region. - - num-pages: The number of pages of the region. The total size of - the region is this value multiplied by the translation granule size. +- pages-count [mandatory] + - value type: + - Count of pages of memory region as a multiple of the translation granule + size - attributes [mandatory] - value type: @@ -214,6 +218,15 @@ Device Regions - 0x1: Read - 0x2: Write - 0x4: Execute + - 0x8: Security state + +- base-address [mandatory] + - value type: + - Base address of the region. The address must be aligned to the translation + granule size. + The address given may be a Physical Address (PA), Virtual Address (VA), or + Intermediate Physical Address (IPA). Refer to the FF-A specification for + more information on the restrictions around the address type. - smmu-id - value type: @@ -233,14 +246,32 @@ Device Regions - A list of (id, attributes) pair describing the device interrupts, where: - id: The interrupt IDs. - - attributes: A value, - containing the attributes for each interrupt ID: + - attributes: A value, containing attributes for each interrupt ID: - - Interrupt type: SPI, PPI, SGI - - Interrupt configuration: Edge triggered, Level triggered - - Interrupt security state: Secure, Non-secure - - Interrupt priority value - - Target execution context/vCPU for each SPI + +----------------------+----------+ + |Field | Bit(s) | + +----------------------+----------+ + | Priority | 7:0 | + +----------------------+----------+ + | Security state | 8 | + +----------------------+----------+ + | Config(Edge/Level) | 9 | + +----------------------+----------+ + | Type(SPI/PPI/SGI) | 11:10 | + +----------------------+----------+ + + Security state: + - Secure: 1 + - Non-secure: 0 + + Configuration: + - Edge triggered: 0 + - Level triggered: 1 + + Type: + - SPI: 0b10 + - PPI: 0b01 + - SGI: 0b00 - exclusive-access - value type: @@ -249,4 +280,4 @@ Device Regions -------------- -*Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/components/index.rst 2.7.0+dfsg-2/docs/components/index.rst --- 2.6+dfsg-1/docs/components/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/components/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -21,7 +21,6 @@ Components sdei secure-partition-manager secure-partition-manager-mm - ffa-manifest-binding xlat-tables-lib-v2-design cot-binding realm-management-extension diff -pruN 2.6+dfsg-1/docs/components/realm-management-extension.rst 2.7.0+dfsg-2/docs/components/realm-management-extension.rst --- 2.6+dfsg-1/docs/components/realm-management-extension.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/components/realm-management-extension.rst 2022-06-01 15:02:46.000000000 +0000 @@ -154,6 +154,8 @@ You can find instructions on how to get git clone --recurse-submodules https://git.trustedfirmware.org/hafnium/hafnium.git cd hafnium + # Use the default prebuilt LLVM/clang toolchain + PATH=$PWD/prebuilts/linux-x64/clang/bin:$PWD/prebuilts/linux-x64/dtc:$PATH make PROJECT=reference The Hafnium binary should be located at @@ -254,6 +256,8 @@ The bottom of the output from *uart0* sh Passed > Test suite 'Realm payload tests' Passed + > Test suite 'Invalid memory access' + Passed ... diff -pruN 2.6+dfsg-1/docs/components/secure-partition-manager.rst 2.7.0+dfsg-2/docs/components/secure-partition-manager.rst --- 2.6+dfsg-1/docs/components/secure-partition-manager.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/components/secure-partition-manager.rst 2022-06-01 15:02:46.000000000 +0000 @@ -3,6 +3,9 @@ Secure Partition Manager .. contents:: +.. toctree:: + ffa-manifest-binding + Acronyms ======== @@ -23,6 +26,8 @@ Acronyms +--------+--------------------------------------+ | IPA | Intermediate Physical Address | +--------+--------------------------------------+ +| JOP | Jump-Oriented Programming | ++--------+--------------------------------------+ | NWd | Normal World | +--------+--------------------------------------+ | ODM | Original Design Manufacturer | @@ -37,6 +42,8 @@ Acronyms +--------+--------------------------------------+ | PVM | Primary VM | +--------+--------------------------------------+ +| ROP | Return-Oriented Programming | ++--------+--------------------------------------+ | SMMU | System Memory Management Unit | +--------+--------------------------------------+ | SP | Secure Partition | @@ -63,24 +70,25 @@ Acronyms Foreword ======== -Two implementations of a Secure Partition Manager co-exist in the TF-A codebase: +Three implementations of a Secure Partition Manager co-exist in the TF-A +codebase: -- SPM based on the FF-A specification `[1]`_. -- SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_. +#. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in + the secure world, managing multiple S-EL1 or S-EL0 partitions. +#. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition + without virtualization in the secure world. +#. EL3 SPM based on the MM specification, legacy implementation managing a + single S-EL0 partition `[2]`_. -Both implementations differ in their architectures and only one can be selected -at build time. +These implementations differ in their respective SW architecture and only one +can be selected at build time. This document: -This document: - -- describes the FF-A implementation where the Secure Partition Manager - resides at EL3 and S-EL2 (or EL3 and S-EL1). +- describes the implementation from bullet 1. when the SPMC resides at S-EL2. - is not an architecture specification and it might provide assumptions on sections mandated as implementation-defined in the specification. -- covers the implications to TF-A used as a bootloader, and Hafnium - used as a reference code base for an S-EL2 secure firmware on - platforms implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) - architecture extension. +- covers the implications to TF-A used as a bootloader, and Hafnium used as a + reference code base for an S-EL2/SPMC secure firmware on platforms + implementing the FEAT_SEL2 architecture extension. Terminology ----------- @@ -98,20 +106,23 @@ Terminology Support for legacy platforms ---------------------------- -In the implementation, the SPM is split into SPMD and SPMC components. -The SPMD is located at EL3 and mainly relays FF-A messages from -NWd (Hypervisor or OS kernel) to SPMC located either at S-EL1 or S-EL2. +The SPM is split into a dispatcher and a core component (respectively SPMD and +SPMC) residing at different exception levels. To permit the FF-A specification +adoption and a smooth migration, the SPMD supports an SPMC residing either at +S-EL1 or S-EL2: + +- The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd + (Hypervisor or OS kernel) to the SPMC. +- The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations. +- The SPMC exception level is a build time choice. -Hence TF-A supports both cases where the SPMC is located either at: +TF-A supports both cases: -- S-EL1 supporting platforms not implementing the FEAT_SEL2 architecture +- S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture extension. The SPMD relays the FF-A protocol from EL3 to S-EL1. -- or S-EL2 supporting platforms implementing the FEAT_SEL2 architecture +- S-EL2 SPMC for platforms implementing the FEAT_SEL2 architecture extension. The SPMD relays the FF-A protocol from EL3 to S-EL2. -The same TF-A SPMD component is used to support both configurations. -The SPMC exception level is a build time choice. - Sample reference stack ====================== @@ -127,14 +138,18 @@ TF-A build options This section explains the TF-A build options involved in building with support for an FF-A based SPM where the SPMD is located at EL3 and the -SPMC located at S-EL1 or S-EL2: +SPMC located at S-EL1, S-EL2 or EL3: - **SPD=spmd**: this option selects the SPMD component to relay the FF-A protocol from NWd to SWd back and forth. It is not possible to enable another Secure Payload Dispatcher when this option is chosen. - **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception - level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when + level to being at S-EL2. It defaults to enabled (value 1) when SPD=spmd is chosen. +- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being + at EL3. +- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC + exception level is set to S-EL1. - **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp. restoring) the EL2 system register context before entering (resp. after leaving) the SPMC. It is mandatorily enabled when @@ -144,16 +159,18 @@ SPMC located at S-EL1 or S-EL2: providing paths to SP binary images and manifests in DTS format (see `Describing secure partitions`_). It is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple - secure partitions are to be loaded on behalf of the SPMC. + secure partitions are to be loaded by BL2 on behalf of the SPMC. -+---------------+----------------------+------------------+ -| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 | -+---------------+----------------------+------------------+ -| SPMC at S-EL1 | 0 | 0 | -+---------------+----------------------+------------------+ -| SPMC at S-EL2 | 1 | 1 (default when | -| | | SPD=spmd) | -+---------------+----------------------+------------------+ ++---------------+----------------------+------------------+-------------+ +| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 | ++---------------+----------------------+------------------+-------------+ +| SPMC at S-EL1 | 0 | 0 | 0 | ++---------------+----------------------+------------------+-------------+ +| SPMC at S-EL2 | 1 | 1 (default when | 0 | +| | | SPD=spmd) | | ++---------------+----------------------+------------------+-------------+ +| SPMC at EL3 | 0 | 0 | 1 | ++---------------+----------------------+------------------+-------------+ Other combinations of such build options either break the build or are not supported. @@ -162,9 +179,8 @@ Notes: - Only Arm's FVP platform is supported to use with the TF-A reference software stack. -- The reference software stack uses FEAT_PAuth (formerly Armv8.3-PAuth) and - FEAT_BTI (formerly Armv8.5-BTI) architecture extensions by default at EL3 - and S-EL2. +- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement + of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions. - The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for barely saving/restoring EL2 registers from an Arm arch perspective. As such it is decoupled from the ``SPD=spmd`` option. @@ -172,10 +188,10 @@ Notes: the Hafnium binary path (built for the secure world) or the path to a TEE binary implementing FF-A interfaces. - BL33 option can specify the TFTF binary or a normal world loader - such as U-Boot or the UEFI framework. + such as U-Boot or the UEFI framework payload. -Sample TF-A build command line when SPMC is located at S-EL1 -(e.g. when the FEAT_EL2 architecture extension is not implemented): +Sample TF-A build command line when the SPMC is located at S-EL1 +(e.g. when the FEAT_SEL2 architecture extension is not implemented): .. code:: shell @@ -188,9 +204,8 @@ Sample TF-A build command line when SPMC PLAT=fvp \ all fip -Sample TF-A build command line for a FEAT_SEL2 enabled system where the SPMC is -located at S-EL2: - +Sample TF-A build command line when FEAT_SEL2 architecture extension is +implemented and the SPMC is located at S-EL2: .. code:: shell make \ @@ -201,13 +216,14 @@ located at S-EL2: ARM_ARCH_MINOR=5 \ BRANCH_PROTECTION=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ + CTX_INCLUDE_MTE_REGS=1 \ BL32= \ BL33= \ SP_LAYOUT_FILE=sp_layout.json \ all fip -Same as above with enabling secure boot in addition: - +Sample TF-A build command line when FEAT_SEL2 architecture extension is +implemented, the SPMC is located at S-EL2, and enabling secure boot: .. code:: shell make \ @@ -218,6 +234,7 @@ Same as above with enabling secure boot ARM_ARCH_MINOR=5 \ BRANCH_PROTECTION=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ + CTX_INCLUDE_MTE_REGS=1 \ BL32= \ BL33= \ SP_LAYOUT_FILE=sp_layout.json \ @@ -229,6 +246,20 @@ Same as above with enabling secure boot GENERATE_COT=1 \ all fip +Sample TF-A build command line when the SPMC is located at EL3: + +.. code:: shell + + make \ + CROSS_COMPILE=aarch64-none-elf- \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + SPMC_AT_EL3=1 \ + BL32= \ + BL33= \ + PLAT=fvp \ + all fip + FVP model invocation ==================== @@ -250,29 +281,33 @@ The FVP command line needs the following | - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. | | - cluster1.has_branch_target_exception=1 | | +---------------------------------------------------+------------------------------------+ -| - cluster0.restriction_on_speculative_execution=2 | Required by the EL2 context | -| - cluster1.restriction_on_speculative_execution=2 | save/restore routine. | +| - cluster0.has_pointer_authentication=2 | Implements FEAT_PAuth | +| - cluster1.has_pointer_authentication=2 | | ++---------------------------------------------------+------------------------------------+ +| - cluster0.memory_tagging_support_level=2 | Implements FEAT_MTE2 | +| - cluster1.memory_tagging_support_level=2 | | +| - bp.dram_metadata.is_enabled=1 | | +---------------------------------------------------+------------------------------------+ Sample FVP command line invocation: .. code:: shell - /FVP_Base_RevC-2xAEMv8A -C pctl.startup=0.0.0.0 + /FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \ -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \ -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \ -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \ -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \ -C bp.pl011_uart2.out_file=fvp-uart2.log \ - -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \ - -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \ - -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 \ - -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \ - -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 \ - -C cluster0.has_branch_target_exception=1 \ - -C cluster1.has_branch_target_exception=1 \ - -C cluster0.restriction_on_speculative_execution=2 \ - -C cluster1.restriction_on_speculative_execution=2 + -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 \ + -C cluster0.has_pointer_authentication=2 -C cluster1.has_pointer_authentication=2 \ + -C cluster0.has_branch_target_exception=1 -C cluster1.has_branch_target_exception=1 \ + -C cluster0.memory_tagging_support_level=2 -C cluster1.memory_tagging_support_level=2 \ + -C bp.dram_metadata.is_enabled=1 \ + -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ + -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ + -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ + -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 Boot process ============ @@ -338,11 +373,23 @@ Describing secure partitions A json-formatted description file is passed to the build flow specifying paths to the SP binary image and associated DTS partition manifest file. The latter is processed by the dtc compiler to generate a DTB fed into the SP package. +Optionally, the partition's json description can contain offsets for both +the image and partition manifest within the SP package. Both offsets need to be +4KB aligned, because it is the translation granule supported by Hafnium SPMC. +These fields can be leveraged to support SPs with S1 translation granules that +differ from 4KB, and to configure the regions allocated within the SP package, +as well as to comply with the requirements for the implementation of the boot +information protocol (see `Passing boot data to the SP`_ for more details). In +case the offsets are absent in their json node, they default to 0x1000 and +0x4000 for the manifest offset and image offset respectively. This file also specifies the SP owner (as an optional field) identifying the signing domain in case of dual root CoT. The SP owner can either be the silicon or the platform provider. The corresponding "owner" field value can either take the value of "SiP" or "Plat". In absence of "owner" field, it defaults to "SiP" owner. +The UUID of the partition can be specified as a field in the description file or +if it does not exist there the UUID is extracted from the DTS partition +manifest. .. code:: shell @@ -350,14 +397,27 @@ In absence of "owner" field, it defaults "tee1" : { "image": "tee1.bin", "pm": "tee1.dts", - "owner": "SiP" + "owner": "SiP", + "uuid": "1b1820fe-48f7-4175-8999-d51da00b7c9f" }, "tee2" : { "image": "tee2.bin", "pm": "tee2.dts", "owner": "Plat" - } + }, + + "tee3" : { + "image": { + "file": "tee3.bin", + "offset":"0x2000" + }, + "pm": { + "file": "tee3.dts", + "offset":"0x6000" + }, + "owner": "Plat" + }, } SPMC manifest @@ -379,7 +439,7 @@ two different cases: attribute { spmc_id = <0x8000>; maj_ver = <0x1>; - min_ver = <0x0>; + min_ver = <0x1>; exec_state = <0x0>; load_address = <0x0 0x6000000>; entrypoint = <0x0 0x6000000>; @@ -398,13 +458,13 @@ two different cases: SPMD (currently matches ``BL32_BASE``) to enter the SPMC. Other nodes in the manifest are consumed by Hafnium in the secure world. -A sample can be found at [7]: +A sample can be found at `[7]`_: - The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute indicates a FF-A compliant SP. The *load_address* field specifies the load - address at which TF-A loaded the SP package. + address at which BL2 loaded the SP package. - *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping. - Note the primary core is declared first, then secondary core are declared + Note the primary core is declared first, then secondary cores are declared in reverse order. - The *memory* node provides platform information on the ranges of memory available to the SPMC. @@ -436,7 +496,7 @@ below: Note this boot flow is an implementation sample on Arm's FVP platform. Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a -different implementation. +different boot flow. The flow restricts to a maximum of 8 secure partitions. Secure boot ~~~~~~~~~~~ @@ -451,6 +511,8 @@ the use of two root keys namely S-ROTPK - SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK. - BL33 may be signed by the OEM using NS-ROTPK. - An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK). +- A maximum of 4 partitions can be signed with the S-ROTPK key and 4 partitions + signed with the NS-ROTPK key. Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections. @@ -467,20 +529,23 @@ In the Hafnium reference implementation the secure world. Such portions are isolated in architecture specific files and/or enclosed by a ``SECURE_WORLD`` macro. -Secure partitions CPU scheduling -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Secure partitions scheduling +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The FF-A v1.0 specification `[1]`_ provides two ways to relinquinsh CPU time to +The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of: - the FFA_MSG_SEND_DIRECT_REQ interface. - the FFA_RUN interface. +Additionally a secure interrupt can pre-empt the normal world execution and give +CPU cycles by transitioning to EL3 and S-EL2. + Platform topology ~~~~~~~~~~~~~~~~~ The *execution-ctx-count* SP manifest field can take the value of one or the -total number of PEs. The FF-A v1.0 specification `[1]`_ recommends the +total number of PEs. The FF-A specification `[1]`_ recommends the following SP types: - Pinned MP SPs: an execution context matches a physical PE. MP SPs must @@ -520,20 +585,56 @@ non-secure EL1&0 Stage-2 table if it exi Passing boot data to the SP --------------------------- -In `[1]`_ , the "Protocol for passing data" section defines a method for passing -boot data to SPs (not currently implemented). +In `[1]`_ , the section "Boot information protocol" defines a method for passing +data to the SPs at boot time. It specifies the format for the boot information +descriptor and boot information header structures, which describe the data to be +exchanged between SPMC and SP. +The specification also defines the types of data that can be passed. +The aggregate of both the boot info structures and the data itself is designated +the boot information blob, and is passed to a Partition as a contiguous memory +region. + +Currently, the SPM implementation supports the FDT type which is used to pass the +partition's DTB manifest. + +The region for the boot information blob is allocated through the SP package. + +.. image:: ../resources/diagrams/partition-package.png + +To adjust the space allocated for the boot information blob, the json description +of the SP (see section `Describing secure partitions`_) shall be updated to contain +the manifest offset. If no offset is provided the manifest offset defaults to 0x1000, +which is the page size in the Hafnium SPMC. + +The configuration of the boot protocol is done in the SPs manifest. As defined by +the specification, the manifest field 'gp-register-num' configures the GP register +which shall be used to pass the address to the partitions boot information blob when +booting the partition. +In addition, the Hafnium SPMC implementation requires the boot information arguments +to be listed in a designated DT node: + +.. code:: shell -Provided that the whole secure partition package image (see -`Secure Partition packages`_) is mapped to the SP secure EL1&0 Stage-2 -translation regime, an SP can access its own manifest DTB blob and extract its -partition manifest properties. + boot-info { + compatible = "arm,ffa-manifest-boot-info"; + ffa_manifest; + }; + +The whole secure partition package image (see `Secure Partition packages`_) is +mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can +retrieve the address for the boot information blob in the designated GP register, +process the boot information header and descriptors, access its own manifest +DTB blob and extract its partition manifest properties. SP Boot order ------------- SP manifests provide an optional boot order attribute meant to resolve dependencies such as an SP providing a service required to properly boot -another SP. +another SP. SPMC boots the SPs in accordance to the boot order attribute, +lowest to the highest value. If the boot order attribute is absent from the FF-A +manifest, the SP is treated as if it had the highest boot order value +(i.e. lowest booting priority). It is possible for an SP to call into another SP through a direct request provided the latter SP has already been booted. @@ -630,28 +731,29 @@ called and informed by the FF-A driver, receiver. There are two types of notifications supported: + - Global, which are targeted to a FF-A endpoint and can be handled within any of -its execution contexts, as determined by the scheduler of the system. + its execution contexts, as determined by the scheduler of the system. - Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a -a specific execution context, as determined by the sender. + a specific execution context, as determined by the sender. The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give permissions to the sender. Notification signaling resorts to two interrupts: -- Schedule Receiver Interrupt: Non-secure physical interrupt to be handled by -the FF-A 'transport' driver within the receiver scheduler. At initialization -the SPMC (as suggested by the spec) configures a secure SGI, as non-secure, and -triggers it when there are pending notifications, and the respective receivers -need CPU cycles to handle them. -- Notifications Pending Interrupt: Virtual Interrupt to be handled by the -receiver of the notification. Set when there are pending notifications. For -per-vCPU the NPI is pended at the handling of FFA_NOTIFICATION_SET interface. -The notifications receipt support is enabled in the partition FF-A manifest. +- Schedule Receiver Interrupt: non-secure physical interrupt to be handled by + the FF-A driver within the receiver scheduler. At initialization the SPMC + donates a SGI ID chosen from the secure SGI IDs range and configures it as + non-secure. The SPMC triggers this SGI on the currently running core when + there are pending notifications, and the respective receivers need CPU cycles + to handle them. +- Notifications Pending Interrupt: virtual interrupt to be handled by the + receiver of the notification. Set when there are pending notifications for the + given secure partition. The NPI is pended when the NWd relinquishes CPU cycles + to an SP. -The subsequent section provides more details about the each one of the -FF-A interfaces for notifications support. +The notifications receipt support is enabled in the partition FF-A manifest. Mandatory interfaces -------------------- @@ -674,9 +776,12 @@ The following interfaces are exposed to - ``FFA_MEM_RETRIEVE_REQ`` - ``FFA_MEM_RETRIEVE_RESP`` - ``FFA_MEM_RELINQUISH`` +- ``FFA_MEM_FRAG_RX`` +- ``FFA_MEM_FRAG_TX`` - ``FFA_MEM_RECLAIM`` +- ``FFA_RUN`` -As part of the support of FF-A v1.1, the following interfaces were added: +As part of the FF-A v1.1 support, the following interfaces were added: - ``FFA_NOTIFICATION_BITMAP_CREATE`` - ``FFA_NOTIFICATION_BITMAP_DESTROY`` @@ -687,6 +792,8 @@ As part of the support of FF-A v1.1, the - ``FFA_NOTIFICATION_INFO_GET`` - ``FFA_SPM_ID_GET`` - ``FFA_SECONDARY_EP_REGISTER`` + - ``FFA_MEM_PERM_GET`` + - ``FFA_MEM_PERM_SET`` FFA_VERSION ~~~~~~~~~~~ @@ -814,24 +921,21 @@ notifications. FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -If the notifications set are per-vCPU, the NPI interrupt is set as pending -for a given receiver partition. - -The FFA_NOTIFICATION_GET will retrieve all pending global notifications and all -pending per-vCPU notifications targeted to the current vCPU. +FFA_NOTIFICATION_GET retrieves all pending global notifications and +per-vCPU notifications targeted to the current vCPU. -Hafnium keeps the global counting of the pending notifications, which is -incremented and decremented at the handling of FFA_NOTIFICATION_SET and -FFA_NOTIFICATION_GET, respectively. If the counter reaches zero, prior to SPMC -triggering the SRI, it won't be triggered. +Hafnium maintains a global count of pending notifications which gets incremented +and decremented when handling FFA_NOTIFICATION_SET and FFA_NOTIFICATION_GET +respectively. A delayed SRI is triggered if the counter is non-zero when the +SPMC returns to normal world. FFA_NOTIFICATION_INFO_GET ~~~~~~~~~~~~~~~~~~~~~~~~~ -Hafnium keeps the global counting of pending notifications whose info has been -retrieved by this interface. The counting is incremented and decremented at the -handling of FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET, respectively. -It also tracks the notifications whose info has been retrieved individually, +Hafnium maintains a global count of pending notifications whose information +has been retrieved by this interface. The count is incremented and decremented +when handling FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET respectively. +It also tracks notifications whose information has been retrieved individually, such that it avoids duplicating returned information for subsequent calls to FFA_NOTIFICATION_INFO_GET. For each notification, this state information is reset when receiver called FFA_NOTIFICATION_GET to retrieve them. @@ -839,18 +943,18 @@ reset when receiver called FFA_NOTIFICAT FFA_SPM_ID_GET ~~~~~~~~~~~~~~ -Returns the FF-A ID allocated to the SPM component (which includes SPMC + SPMD). -At initialization, the SPMC queries the SPMD for the SPM ID, using this -same interface, and saves it. +Returns the FF-A ID allocated to an SPM component which can be one of SPMD +or SPMC. -The call emitted at NS and secure physical FF-A instances returns the SPM ID -specified in the SPMC manifest. +At initialization, the SPMC queries the SPMD for the SPMC ID, using the +FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using +the FFA_SPM_ID_GET interface at the secure physical FF-A instance. -Secure partitions call this interface at the virtual instance, to which the SPMC -shall return the priorly retrieved SPM ID. +Secure partitions call this interface at the virtual FF-A instance, to which +the SPMC returns the priorly retrieved SPMC ID. -The Hypervisor or OS kernel can issue an FFA_SPM_ID_GET call handled by the -SPMD, which returns the SPM ID. +The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the +SPMD, which returns the SPMC ID. FFA_SECONDARY_EP_REGISTER ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -858,7 +962,7 @@ FFA_SECONDARY_EP_REGISTER When the SPMC boots, all secure partitions are initialized on their primary Execution Context. -The interface FFA_SECONDARY_EP_REGISTER is to be used by a secure partitions +The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition from its first execution context, to provide the entry point address for secondary execution contexts. @@ -875,26 +979,35 @@ permits SPMD to SPMC communication and e - SPMC to SPMD direct request/response uses SMC conduit. - SPMD to SPMC direct request/response uses ERET conduit. +This is used in particular to convey power management messages. + PE MMU configuration -------------------- -With secure virtualization enabled, two IPA spaces are output from the secure -EL1&0 Stage-1 translation (secure and non-secure). The EL1&0 Stage-2 translation -hardware is fed by: - -- A single secure IPA space when the SP EL1&0 Stage-1 MMU is disabled. -- Two IPA spaces (secure and non-secure) when the SP EL1&0 Stage-1 MMU is - enabled. +With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1 +partitions, two IPA spaces (secure and non-secure) are output from the +secure EL1&0 Stage-1 translation. +The EL1&0 Stage-2 translation hardware is fed by: + +- A secure IPA when the SP EL1&0 Stage-1 MMU is disabled. +- One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled. ``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the -NS/S IPA translations. -``VSTCR_EL2.SW`` = 0, ``VSTCR_EL2.SA`` = 0,``VTCR_EL2.NSW`` = 0, ``VTCR_EL2.NSA`` = 1: +NS/S IPA translations. The following controls are set up: +``VSTCR_EL2.SW = 0`` , ``VSTCR_EL2.SA = 0``, ``VTCR_EL2.NSW = 0``, +``VTCR_EL2.NSA = 1``: - Stage-2 translations for the NS IPA space access the NS PA space. - Stage-2 translation table walks for the NS IPA space are to the secure PA space. -Secure and non-secure IPA regions use the same set of Stage-2 page tables within -a SP. +Secure and non-secure IPA regions (rooted to by ``VTTBR_EL2`` and ``VSTTBR_EL2``) +use the same set of Stage-2 page tables within a SP. + +The ``VTCR_EL2/VSTCR_EL2/VTTBR_EL2/VSTTBR_EL2`` virtual address space +configuration is made part of a vCPU context. + +For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation +regime is used for both Hafnium and the partition. Interrupt management -------------------- @@ -1091,16 +1204,46 @@ When using the SPMD as a Secure Payload (svc_off) hooks are registered. - The behavior for the cpu on event is described in `Secondary cores boot-up`_. The SPMC is entered through its secondary physical core entry point. -- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The method by which - the PM event is conveyed to the SPMC is implementation-defined in context of - FF-A v1.0 (`SPMC-SPMD direct requests/responses`_). It consists in a SPMD-to-SPMC - direct request/response conveying the PM event details and SPMC response. +- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The PM event is + signaled to the SPMC through a power management framework message. + It consists in a SPMD-to-SPMC direct request/response (`SPMC-SPMD direct + requests/responses`_) conveying the event details and SPMC response. The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and updates its internal state to reflect the physical core is being turned off. In the current implementation no SP is resumed as a consequence. This behavior ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux userspace. +Arm architecture extensions for security hardening +================================================== + +Hafnium supports the following architecture extensions for security hardening: + +- Pointer authentication (FEAT_PAuth): the extension permits detection of forged + pointers used by ROP type of attacks through the signing of the pointer + value. Hafnium is built with the compiler branch protection option to permit + generation of a pointer authentication code for return addresses (pointer + authentication for instructions). The APIA key is used while Hafnium runs. + A random key is generated at boot time and restored upon entry into Hafnium + at run-time. APIA and other keys (APIB, APDA, APDB, APGA) are saved/restored + in vCPU contexts permitting to enable pointer authentication in VMs/SPs. +- Branch Target Identification (FEAT_BTI): the extension permits detection of + unexpected indirect branches used by JOP type of attacks. Hafnium is built + with the compiler branch protection option, inserting land pads at function + prologues that are reached by indirect branch instructions (BR/BLR). + Hafnium code pages are marked as guarded in the EL2 Stage-1 MMU descriptors + such that an indirect branch must always target a landpad. A fault is + triggered otherwise. VMs/SPs can (independently) mark their code pages as + guarded in the EL1&0 Stage-1 translation regime. +- Memory Tagging Extension (FEAT_MTE): the option permits detection of out of + bound memory array accesses or re-use of an already freed memory region. + Hafnium enables the compiler option permitting to leverage MTE stack tagging + applied to core stacks. Core stacks are marked as normal tagged memory in the + EL2 Stage-1 translation regime. A synchronous data abort is generated upon tag + check failure on load/stores. A random seed is generated at boot time and + restored upon entry into Hafnium. MTE system registers are saved/restored in + vCPU contexts permitting MTE usage from VMs/SPs. + SMMUv3 support in Hafnium ========================= @@ -1210,7 +1353,7 @@ streams. - No support for independent peripheral devices. S-EL0 Partition support -========================= +======================= The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world with ARMv8.4 and FEAT_SEL2). @@ -1273,7 +1416,7 @@ Client & Zelalem Aweke +:Status: RFC + +.. contents:: Table of Contents + +Introduction +------------ +The context management library in TF-A provides the basic CPU context +initialization and management routines for use by different components +in EL3 firmware. The original design of the library was done keeping in +mind the 2 world switch and hence this design pattern has been extended to +keep up with growing requirements of EL3 firmware. With the introduction +of a new Realm world and a separate Root world for EL3 firmware, it is clear +that this library needs to be refactored to cater for future enhancements and +reduce chances of introducing error in code. This also aligns with the overall +goal of reducing EL3 firmware complexity and footprint. + +It is expected that the suggestions below could have legacy implications and +hence we are mainly targeting SPM/RMM based systems. It is expected that these +legacy issues will need to be sorted out as part of implementation on a case +by case basis. + +Design Principles +----------------- +The below section lays down the design principles for re-factoring the context +management library : + +(1) **Decentralized model for context mgmt** + + Both the Secure and Realm worlds have associated dispatcher component in + EL3 firmware to allow management of their respective worlds. Allowing the + dispatcher to own the context for their respective world and moving away + from a centralized policy management by context management library will + remove the world differentiation code in the library. This also means that + the library will not be responsible for CPU feature enablement for + Secure and Realm worlds. See point 3 and 4 for more details. + + The Non Secure world does not have a dispatcher component and hence EL3 + firmware (BL31)/context management library needs to have routines to help + initialize the Non Secure world context. + +(2) **EL3 should only initialize immediate used lower EL** + + Due to the way TF-A evolved, from EL3 interacting with an S-EL1 payload to + SPM in S-EL2, there is some code initializing S-EL1 registers which is + probably redundant when SPM is present in S-EL2. As a principle, EL3 + firmware should only initialize the next immediate lower EL in use. + If EL2 needs to be skipped and is not to be used at runtime, then + EL3 can do the bare minimal EL2 init and init EL1 to prepare for EL3 exit. + It is expected that this skip EL2 configuration is only needed for NS + world to support legacy Android deployments. It is worth removing this + `skip EL2 for Non Secure` config support if this is no longer used. + +(3) **Maintain EL3 sysregs which affect lower EL within CPU context** + + The CPU context contains some EL3 sysregs and gets applied on a per-world + basis (eg: cptr_el3, scr_el3, zcr_el3 is part of the context + because different settings need to be applied between each world). + But this design pattern is not enforced in TF-A. It is possible to directly + modify EL3 sysreg dynamically during the transition between NS and Secure + worlds. Having multiple ways of manipulating EL3 sysregs for different + values between the worlds is flaky and error prone. The proposal is to + enforce the rule that any EL3 sysreg which can be different between worlds + is maintained in the CPU Context. Once the context is initialized the + EL3 sysreg values corresponding to the world being entered will be restored. + +(4) **Allow more flexibility for Dispatchers to select feature set to save and restore** + + The current functions for EL2 CPU context save and restore is a single + function which takes care of saving and restoring all the registers for + EL2. This method is inflexible and it does not allow to dynamically detect + CPU features to select registers to save and restore. It also assumes that + both Realm and Secure world will have the same feature set enabled from + EL3 at runtime and makes it hard to enable different features for each + world. The framework should cater for selective save and restore of CPU + registers which can be controlled by the dispatcher. + + For the implementation, this could mean that there is a separate assembly + save and restore routine corresponding to Arch feature. The memory allocation + within the CPU Context for each set of registers will be controlled by a + FEAT_xxx build option. It is a valid configuration to have + context memory allocated but not used at runtime based on feature detection + at runtime or the platform owner has decided not to enable the feature + for the particular world. + +Context Allocation and Initialization +------------------------------------- + +|context_mgmt_abs| + +.. |context_mgmt_abs| image:: + ../resources/diagrams/context_management_abs.png + +The above figure shows how the CPU context is allocated within TF-A. The +allocation for Secure and Realm world is by the respective dispatcher. In the case +of NS world, the context is allocated by the PSCI lib. This scheme allows TF-A +to be built in various configurations (with or without Secure/Realm worlds) and +will result in optimal memory footprint. The Secure and Realm world contexts are +initialized by invoking context management library APIs which then initialize +each world based on conditional evaluation of the security state of the +context. The proposal here is to move the conditional initialization +of context for Secure and Realm worlds to their respective dispatchers and +have the library do only the common init needed. The library can export +helpers to initialize registers corresponding to certain features but +should not try to do different initialization between the worlds. The library +can also export helpers for initialization of NS CPU Context since there is no +dispatcher for that world. + +This implies that any world specific code in context mgmt lib should now be +migrated to the respective "owners". To maintain compatibility with legacy, the +current functions can be retained in the lib and perhaps define new ones for +use by SPMD and RMMD. The details of this can be worked out during +implementation. + +Introducing Root Context +------------------------ +Till now, we have been ignoring the fact that Root world (or EL3) itself could +have some settings which are distinct from NS/S/Realm worlds. In this case, +Root world itself would need to maintain some sysregs settings for its own +execution and would need to use sysregs of lower EL (eg: PAuth, pmcr) to enable +some functionalities in EL3. The current sequence for context save and restore +in TF-A is as given below: + +|context_mgmt_existing| + +.. |context_mgmt_existing| image:: + ../resources/diagrams/context_mgmt_existing.png + +Note1: The EL3 CPU context is not a homogenous collection of EL3 sysregs but +a collection of EL3 and some other lower EL registers. The save and restore +is also not done homogenously but based on the objective of using the +particular register. + +Note2: The EL1 context save and restore can possibly be removed when switching +to S-EL2 as SPM can take care of saving the incoming NS EL1 context. + +It can be seen that the EL3 sysreg values applied while the execution is in Root +world corresponds to the world it came from (eg: if entering EL3 from NS world, +the sysregs correspond to the values in NS context). There is a case that EL3 +itself may have some settings to apply for various reasons. A good example for +this is the cptr_el3 regsiter. Although FPU traps need to be disabled for +Non Secure, Secure and Realm worlds, the EL3 execution itself may keep the trap +enabled for the sake of robustness. Another example is, if the MTE feature +is enabled for a particular world, this feature will be enabled for Root world +as well when entering EL3 from that world. The firmware at EL3 may not +be expecting this feature to be enabled and may cause unwanted side-effects +which could be problematic. Thus it would be more robust if Root world is not +subject to EL3 sysreg values from other worlds but maintains its own values +which is stable and predictable throughout root world execution. + +There is also the case that when EL3 would like to make use of some +Architectural feature(s) or do some security hardening, it might need +programming of some lower EL sysregs. For example, if EL3 needs to make +use of Pointer Authentication (PAuth) feature, it needs to program +its own PAuth Keys during execution at EL3. Hence EL3 needs its +own copy of PAuth registers which needs to be restored on every +entry to EL3. A similar case can be made for DIT bit in PSTATE, +or use of SP_EL0 for C Runtime Stack at EL3. + +The proposal here is to maintain a separate root world CPU context +which gets applied for Root world execution. This is not the full +CPU_Context, but subset of EL3 sysregs (`el3_sysreg`) and lower EL +sysregs (`root_exc_context`) used by EL3. The save and restore +sequence for this Root context would need to be done in +an optimal way. The `el3_sysreg` does not need to be saved +on EL3 Exit and possibly only some registers in `root_exc_context` +of Root world context would need to be saved on EL3 exit (eg: SP_EL0). + +The new sequence for world switch including Root world context would +be as given below : + +|context_mgmt_proposed| + +.. |context_mgmt_proposed| image:: + ../resources/diagrams/context_mgmt_proposed.png + +Having this framework in place will allow Root world to make use of lower EL +registers easily for its own purposes and also have a fixed EL3 sysreg setting +which is not affected by the settings of other worlds. This will unify the +Root world register usage pattern for its own execution and remove some +of the adhoc usages in code. + +Conclusion +---------- +Of all the proposals, the introduction of Root world context would likely need +further prototyping to confirm the design and we will need to measure the +performance and memory impact of this change. Other changes are incremental +improvements which are thought to have negligible impact on EL3 performance. + +-------------- + +*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/design_documents/index.rst 2.7.0+dfsg-2/docs/design_documents/index.rst --- 2.6+dfsg-1/docs/design_documents/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/design_documents/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -7,6 +7,7 @@ Design Documents :numbered: cmake_framework + context_mgmt_rework measured_boot_poc -------------- diff -pruN 2.6+dfsg-1/docs/getting_started/build-options.rst 2.7.0+dfsg-2/docs/getting_started/build-options.rst --- 2.6+dfsg-1/docs/getting_started/build-options.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/getting_started/build-options.rst 2022-06-01 15:02:46.000000000 +0000 @@ -174,14 +174,23 @@ Common build options registers to be included when saving and restoring the CPU context. Default is 0. -- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the - Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 - execution context. Default value is 0. - -- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables - Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth - registers to be included when saving and restoring the CPU context as - part of world switch. Default value is 0. +- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension + registers in cpu context. This must be enabled, if the platform wants to use + this feature in the Secure world and MTE is enabled at ELX. This flag can + take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. + Default value is 0. + +- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV + registers to be saved/restored when entering/exiting an EL2 execution + context. This flag can take values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. Default value is 0. + +- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer + Authentication for Secure world. This will cause the ARMv8.3-PAuth registers + to be included when saving and restoring the CPU context as part of world + switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` + mechanism. Default value is 0. + Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this flag if the CPU supports it. @@ -246,24 +255,109 @@ Common build options builds, but this behaviour can be overridden in each platform's Makefile or in the build command line. -- ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow - access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as - adding HCRX_EL2 to the EL2 context save/restore operations. +- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2 + (Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2 + to EL3 context save/restore operations. This flag can take the values 0 to 2, + to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature + available on v8.4 and onwards and must be set to either 1 or 2 alongside + ``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register. + Default value is ``0``. + +- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` + extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 + onwards. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` + extension. It allows access to the SCXTNUM_EL2 (Software Context Number) + register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an + optional feature available on Arm v8.0 onwards. This flag can take values + 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. + Default value is ``0``. + +- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent + Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. + ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 + and upwards. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter + Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer + Physical Offset register) during EL2 to EL3 context save/restore operations. + Its a mandatory architectural feature and is enabled from v8.6 and upwards. + This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) + feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained + Read Trap Register) during EL2 to EL3 context save/restore operations. + Its a mandatory architectural feature and is enabled from v8.6 and upwards. + This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to + allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as + well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a + mandatory architectural feature and is enabled from v8.7 and upwards. This + flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged + Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a + permission fault for any privileged data access from EL1/EL2 to virtual + memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a + mandatory architectural feature and is enabled from v8.1 and upwards. This + flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default value is ``0``. + +- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. + ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This + flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default is ``0``. + +- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation + Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an + optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory + for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with + ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if + needed could be overidden from platforms explicitly. Default value is ``0``. + +- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) + extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. + This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default is ``0``. + +- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed + trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature + available on Arm v8.6. This flag can take values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. Default is ``0``. + + When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets + delayed by the amount of value in ``TWED_DELAY``. + +- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization + Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register + during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory + architectural feature and is enabled from v8.1 and upwards. It can take + values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. + Default value is ``0``. - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0. -- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM +- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their performance aspects. - When this option is set to ``1``, EL3 allows lower ELs to access their own - MPAM registers without trapping into EL3. This option doesn't make use of - partitioning in EL3, however. Platform initialisation code should configure - and use partitions in EL3 as required. This option defaults to ``0``. + This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to + access their own MPAM registers without trapping into EL3. This option + doesn't make use of partitioning in EL3, however. Platform initialisation + code should configure and use partitions in EL3 as required. This option + defaults to ``0``. - ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC @@ -289,9 +383,10 @@ Common build options be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in software. -- ``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm - Management Extension. Default value is 0. This is currently an experimental - feature. +- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm + Management Extension. This flag can take the values 0 to 2, to align with + the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently + an experimental feature. - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to @@ -334,8 +429,8 @@ Common build options - ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option - requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is - automatically disabled when the target architecture is AArch32. + requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it + is automatically disabled when the target architecture is AArch32. - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The @@ -381,6 +476,43 @@ Common build options This feature is intended for testing purposes only, and is advisable to keep disabled for production images. +- ``FEATURE_DETECTION``: Boolean option to enable the architectural features + detection mechanism. It detects whether the Architectural features enabled + through feature specific build flags are supported by the PE or not by + validating them either at boot phase or at runtime based on the value + possessed by the feature flag (0 to 2) and report error messages at an early + stage. + + This prevents and benefits us from EL3 runtime exceptions during context save + and restore routines guarded by these build flags. Henceforth validating them + before their usage provides more control on the actions taken under them. + + The mechanism permits the build flags to take values 0, 1 or 2 and + evaluates them accordingly. + + Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: + + :: + + ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. + ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. + ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. + + In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to + 0, feature is disabled statically during compilation. If it is defined as 1, + feature is validated, wherein FEAT_HCX is detected at boot time. In case not + implemented by the PE, a hard panic is generated. Finally, if the flag is set + to 2, feature is validated at runtime. + + Note that the entire implementation is divided into two phases, wherein as + as part of phase-1 we are supporting the values 0,1. Value 2 is currently not + supported and is planned to be handled explicilty in phase-2 implementation. + + FEATURE_DETECTION macro is disabled by default, and is currently an + experimental procedure. Platforms can explicitly make use of this by + mechanism, by enabling it to validate whether they have set their build flags + properly at an early phase. + - ``FIP_NAME``: This is an optional build option which specifies the FIP filename for the ``fip`` target. Default is ``fip.bin``. @@ -511,9 +643,18 @@ Common build options the build. The default value is 40 in debug builds and 20 in release builds. - ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot - feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well - in order to provide trust that the code taking the measurements and recording - them has not been tampered with. + feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to + provide trust that the code taking the measurements and recording them has + not been tampered with. + + This option defaults to 0. + +- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust + for Measurement (DRTM). This feature has trust dependency on BL31 for taking + the measurements and recording them as per `PSA DRTM specification`_. For + platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can + be used and for the platforms which use ``RESET_TO_BL31`` platform owners + should have mechanism to authenticate BL31. This option defaults to 0. @@ -570,9 +711,10 @@ Common build options enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well. -- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features +- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 - or later CPUs. + or later CPUs. This flag can take the values 0 to 2, to align with the + ``FEATURE_DETECTION`` mechanism. When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be set to ``1``. @@ -584,6 +726,11 @@ Common build options entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0. +- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting + this additional option guarantees that the input registers are not cleared + therefore allowing parameters to be passed to the BL31 entrypoint. + The default value is 0. + - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 @@ -629,6 +776,13 @@ Common build options ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS sections are placed in RAM immediately following the loaded firmware image. +- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the + NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM + discontiguous from loaded firmware images. When set, the platform need to + provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This + flag is disabled by default and NOLOAD sections are placed in RAM immediately + following the loaded firmware image. + - ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration access requests via a standard SMCCC defined in `DEN0115`_. When combined with UEFI+ACPI this can provide a certain amount of OS forward compatibility @@ -648,13 +802,20 @@ Common build options firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details. -- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM +- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC - component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 + component runs at the EL3 exception level. The default value is ``0`` ( + disabled). This configuration supports pre-Armv8.4 platforms (aka not + implementing the ``FEAT_SEL2`` extension). This is an experimental feature. + +- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM + Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC + component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` extension. This is the default when enabling the SPM Dispatcher. When disabled (0) it indicates the SPMC component runs at the S-EL1 execution - state. This latter configuration supports pre-Armv8.4 platforms (aka not - implementing the Armv8.4-SecEL2 extension). + state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations + support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` + extension). - ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure Partition Manager (SPM) implementation. The default value is ``0`` @@ -706,6 +867,12 @@ Common build options When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` must also be set to ``1``. +- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of + WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set + this delay. It can take values in the range (0-15). Default value is ``0`` + and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. + Platforms need to explicitly update this value based on their requirements. + - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM linker. When the ``LINKER`` build variable points to the armlink linker, this flag is enabled automatically. To enable support for armlink, platforms @@ -815,6 +982,11 @@ Common build options functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0. +- ``ENABLE_BRBE_FOR_NS``: This flag enables access to the branch record buffer + registers from NS ELs when FEAT_BRBE is implemented. BRBE is an optional + architectural feature for AArch64. The default is 0 and it is automatically + disabled when the target architecture is AArch32. + - ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural @@ -826,9 +998,15 @@ Common build options but unused). This feature is available if trace unit such as ETMv4.x, and ETE(extending ETM feature) is implemented. This flag is disabled by default. -- ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers +- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), - if FEAT_TRF is implemented. This flag is disabled by default. + if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align + with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. + +- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA + APIs on platforms that doesn't support RSS (providing Arm CCA HES + functionalities). When enabled (``1``), a mocked version of the APIs are used. + The default value is 0. GICv3 driver options -------------------- @@ -873,11 +1051,11 @@ To compile a debug version and make the make PLAT= DEBUG=1 V=1 all -AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for -example DS-5) might not support this and may need an older version of DWARF -symbols to be emitted by GCC. This can be achieved by using the -``-gdwarf-`` flag, with the version being set to 2 or 3. Setting the -version to 2 is recommended for DS-5 versions older than 5.16. +AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools +(for example Arm-DS) might not support this and may need an older version of +DWARF symbols to be emitted by GCC. This can be achieved by using the +``-gdwarf-`` flag, with the version being set to 2, 3, 4 or 5. Setting +the version to 4 is recommended for Arm-DS. When debugging logic problems it might also be useful to disable all compiler optimizations by using ``-O0``. @@ -902,7 +1080,7 @@ It is also possible to introduce an infi post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` section. In this case, the developer may take control of the target using a -debugger when indicated by the console output. When using DS-5, the following +debugger when indicated by the console output. When using Arm-DS, the following commands can be used: :: @@ -943,7 +1121,8 @@ Firmware update options -------------- -*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* .. _DEN0115: https://developer.arm.com/docs/den0115/latest .. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ +.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a diff -pruN 2.6+dfsg-1/docs/getting_started/initial-build.rst 2.7.0+dfsg-2/docs/getting_started/initial-build.rst --- 2.6+dfsg-1/docs/getting_started/initial-build.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/getting_started/initial-build.rst 2022-06-01 15:02:46.000000000 +0000 @@ -18,16 +18,12 @@ Performing an Initial Build It is possible to build TF-A using Clang or Arm Compiler 6. To do so ``CC`` needs to point to the clang or armclang binary, which will - also select the clang or armclang assembler. Be aware that for Arm Compiler, - the GNU linker is used by default. However for Clang LLVM linker (LLD) - is used by default. In case of being needed the linker can be overridden - using the ``LD`` variable. LLVM linker (LLD) version 9 is - known to work with TF-A. - - In both cases ``CROSS_COMPILE`` should be set as described above. - - Arm Compiler 6 will be selected when the base name of the path assigned - to ``CC`` matches the string 'armclang'. + also select the clang or armclang assembler. Arm Compiler 6 will be selected + when the base name of the path assigned to ``CC`` matches the string + 'armclang'. GNU binutils are required since the TF-A build system doesn't + currently support Arm Scatter files. Meaning the GNU linker is used by + default for Arm Compiler 6. Because of this dependency, ``CROSS_COMPILE`` + should be set as described above. For AArch64 using Arm Compiler 6: @@ -36,6 +32,11 @@ Performing an Initial Build export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/armclang PLAT= all + On the other hand, Clang uses LLVM linker (LLD) and other LLVM binutils by + default instead of GNU utilities (LLVM linker (LLD) 14.0.0 is known to + work with TF-A). ``CROSS_COMPILE`` need not be set for Clang. Please note, + that the default linker may be manually overridden using the ``LD`` variable. + Clang will be selected when the base name of the path assigned to ``CC`` contains the string 'clang'. This is to allow both clang and clang-X.Y to work. @@ -44,7 +45,6 @@ Performing an Initial Build .. code:: shell - export CROSS_COMPILE=/bin/aarch64-none-elf- make CC=/bin/clang PLAT= all - Change to the root directory of the TF-A source tree and build. @@ -115,4 +115,4 @@ Performing an Initial Build -------------- -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/getting_started/porting-guide.rst 2.7.0+dfsg-2/docs/getting_started/porting-guide.rst --- 2.6+dfsg-1/docs/getting_started/porting-guide.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/getting_started/porting-guide.rst 2022-06-01 15:02:46.000000000 +0000 @@ -889,7 +889,7 @@ Function : plat_fwu_set_images_source() :: - Argument : struct fwu_metadata *metadata + Argument : const struct fwu_metadata *metadata Return : void This function is mandatory when PSA_FWU_SUPPORT is enabled. @@ -932,6 +932,25 @@ It returns '0' on success, otherwise a n Alongside, returns device handle and image specification from the I/O policy of the requested FWU metadata image. +Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : void + Return : uint32_t + +This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the +means to retrieve the boot index value from the platform. The boot index is the +bank from which the platform has booted the firmware images. + +By default, the platform will read the metadata structure and try to boot from +the active bank. If the platform fails to boot from the active bank due to +reasons like an Authentication failure, or on crossing a set number of watchdog +resets while booting from the active bank, the platform can then switch to boot +from a different bank. This function then returns the bank that the platform +should boot its images from. + Common optional modifications ----------------------------- @@ -1195,7 +1214,7 @@ Function : plat_mboot_measure_image() :: Argument : unsigned int, image_info_t * - Return : void + Return : int When the MEASURED_BOOT flag is enabled: @@ -1204,7 +1223,25 @@ When the MEASURED_BOOT flag is enabled: - On the Arm FVP port, this function measures the given image using its passed id and information and then records that measurement in the Event Log buffer. -- This function must return 0 on success, a negative error code otherwise. +- This function must return 0 on success, a signed integer error code + otherwise. + +When the MEASURED_BOOT flag is disabled, this function doesn't do anything. + +Function : plat_mboot_measure_critical_data() +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : unsigned int, const void *, size_t + Return : int + +When the MEASURED_BOOT flag is enabled: + +- This function measures the given critical data structure and records its + measurement using the measured boot backend driver. +- This function must return 0 on success, a signed integer error code + otherwise. When the MEASURED_BOOT flag is disabled, this function doesn't do anything. @@ -1980,6 +2017,58 @@ state. This function must return a point (that was copied during ``bl31_early_platform_setup()``) if the image exists. It should return NULL otherwise. +Function : plat_get_cca_attest_token() [mandatory when ENABLE_RME == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uintptr_t, size_t *, uintptr_t, size_t + Return : int + +This function returns the Platform attestation token. + +The parameters of the function are: + + arg0 - A pointer to the buffer where the Platform token should be copied by + this function. The buffer must be big enough to hold the Platform + token. + + arg1 - Contains the size (in bytes) of the buffer passed in arg0. The + function returns the platform token length in this parameter. + + arg2 - A pointer to the buffer where the challenge object is stored. + + arg3 - The length of the challenge object in bytes. Possible values are 32, + 48 and 64. + +The function returns 0 on success, -EINVAL on failure. + +Function : plat_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +:: + + Argument : uintptr_t, size_t *, unsigned int + Return : int + +This function returns the delegated realm attestation key which will be used to +sign Realm attestation token. The API currently only supports P-384 ECC curve +key. + +The parameters of the function are: + + arg0 - A pointer to the buffer where the attestation key should be copied + by this function. The buffer must be big enough to hold the + attestation key. + + arg1 - Contains the size (in bytes) of the buffer passed in arg0. The + function returns the attestation key length in this parameter. + + arg2 - The type of the elliptic curve to which the requested attestation key + belongs. + +The function returns 0 on success, -EINVAL on failure. + Function : bl31_plat_enable_mmu [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -2029,21 +2118,6 @@ frequency for the CPU's generic timer. T of the system counter, which is retrieved from the first entry in the frequency modes table. -Function : plat_arm_set_twedel_scr_el3() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : uint32_t - -This function is used in v8.6+ systems to set the WFE trap delay value in -SCR_EL3. If this function returns TWED_DISABLED or is left unimplemented, this -feature is not enabled. The only hook provided is to set the TWED fields in -SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to adjust -the WFE trap delays in lower ELs and these fields should be set by the -appropriate EL2 or EL1 code depending on the platform configuration. - #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -3117,7 +3191,7 @@ amount of open resources per driver. -------------- -*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.* .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html diff -pruN 2.6+dfsg-1/docs/getting_started/prerequisites.rst 2.7.0+dfsg-2/docs/getting_started/prerequisites.rst --- 2.6+dfsg-1/docs/getting_started/prerequisites.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/getting_started/prerequisites.rst 2022-06-01 15:02:46.000000000 +0000 @@ -7,7 +7,6 @@ AArch32 and AArch64 target platforms. It may possible to build |TF-A| with combinations of software packages that are different from those listed below, however only the software described in this document can be officially supported. - Build Host ---------- @@ -26,9 +25,9 @@ Toolchain |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 10.3-2021.07 (from the `Arm Developer website`_) -- Clang >= 4.0 -- Arm Compiler >= 6.0 +- GCC >= 11.2-2022.02 (from the `Arm Developer website`_) +- Clang >= 14.0.0 +- Arm Compiler >= 6.18 In addition, a native compiler is required to build the supporting tools. @@ -54,13 +53,14 @@ The following tools are required to obta The following libraries must be available to build one or more components or supporting tools: -- OpenSSL >= 1.0.1 +- OpenSSL >= 3.0 Required to build the cert_create tool. -The following libraries are required for Trusted Board Boot support: +The following libraries are required for Trusted Board Boot and Measured Boot +support: -- mbed TLS == 2.26.0 (tag: ``mbedtls-2.26.0``) +- mbed TLS == 2.28.0 (tag: ``mbedtls-2.28.0``) These tools are optional: @@ -70,7 +70,7 @@ These tools are optional: source files (``.dts`` files). DTC is available for Linux through the package repositories of most distributions. -- Arm `Development Studio 5 (DS-5)`_ +- Arm `Development Studio (Arm-DS)`_ The standard software package used for debugging software on Arm development platforms and |FVP| models. @@ -159,11 +159,11 @@ documentation, available `here DEBUG=1 -To build for machines with an H616 or H313 SoC: +So for instance to build for a board with the Allwinner A64 SoC:: -.. code:: shell + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 - make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31 +Platform-specific build options +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The default build options should generate a working firmware image. There are +some build options that allow to fine-tune the firmware, or to disable support +for optional features. + +- ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown + and powerup sequence by BL31. This requires either support for a code snippet + to be loaded into the ARISC SCP (A64, H5), or the power sequence control + registers to be programmed directly (H6, H616). This supports only basic + control, like core on/off and system off/reset. + This option defaults to 1. If an active SCP supporting the SCPI protocol + is detected at runtime, this control scheme will be ignored, and SCPI + will be used instead, unless support has been explicitly disabled. + +- ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and + powerup sequence by talking to the SCP processor via the SCPI protocol. + This allows more advanced power saving techniques, like suspend to RAM. + This option defaults to 1 on SoCs that feature an SCP. If no SCP firmware + using the SCPI protocol is detected, the native sequence will be used + instead. If both native and SCPI methods are included, SCPI will be favoured + if SCP support is detected. + +- ``SUNXI_SETUP_REGULATORS`` : On SoCs that typically ship with a PMIC + power management controller, BL31 tries to set up all needed power rails, + programming them to their respective voltages. That allows bootloader + software like U-Boot to ignore power control via the PMIC. + This setting defaults to 1. In some situations that enables too many + regulators, or some regulators need to be enabled in a very specific + sequence. To avoid problems with those boards, ``SUNXI_SETUP_REGULATORS`` + can bet set to ``0`` on the build command line, to skip the PMIC setup + entirely. Any bootloader or OS would need to setup the PMIC on its own then. Installation ------------ diff -pruN 2.6+dfsg-1/docs/plat/arm/corstone1000/index.rst 2.7.0+dfsg-2/docs/plat/arm/corstone1000/index.rst --- 2.6+dfsg-1/docs/plat/arm/corstone1000/index.rst 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/arm/corstone1000/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,61 @@ +Corstone1000 Platform +========================== + +Some of the features of the Corstone1000 platform referenced in TF-A include: + +- Cortex-A35 application processor (64-bit mode) +- Secure Enclave +- GIC-400 +- Trusted Board Boot + +Boot Sequence +------------- + +The board boot relies on CoT (chain of trust). The trusted-firmware-a +BL2 is extracted from the FIP and verified by the Secure Enclave +processor. BL2 verification relies on the signature area at the +beginning of the BL2 image. This area is needed by the SecureEnclave +bootloader. + +Then, the application processor is released from reset and starts by +executing BL2. + +BL2 performs the actions described in the trusted-firmware-a TBB design +document. + +Build Procedure (TF-A only) +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Obtain AArch64 ELF bare-metal target `toolchain `_. + Set the CROSS_COMPILE environment variable to point to the toolchain folder. + +- Build TF-A: + + .. code:: shell + + make LD=aarch64-none-elf-ld \ + CC=aarch64-none-elf-gcc \ + V=1 \ + BUILD_BASE= \ + PLAT=corstone1000 \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + DEBUG=1 \ + MBEDTLS_DIR=mbedtls \ + OPENSSL_DIR= \ + RUNTIME_SYSROOT= \ + ARCH=aarch64 \ + TARGET_PLATFORM= \ + ENABLE_PIE=1 \ + BL2_AT_EL3=1 \ + CREATE_KEYS=1 \ + GENERATE_COT=1 \ + TRUSTED_BOARD_BOOT=1 \ + COT=tbbr \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL32= \ + BL33= \ + bl2 + +*Copyright (c) 2021, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/plat/arm/diphda/index.rst 2.7.0+dfsg-2/docs/plat/arm/diphda/index.rst --- 2.6+dfsg-1/docs/plat/arm/diphda/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/arm/diphda/index.rst 1970-01-01 00:00:00.000000000 +0000 @@ -1,61 +0,0 @@ -Diphda Platform -========================== - -Some of the features of the Diphda platform referenced in TF-A include: - -- Cortex-A35 application processor (64-bit mode) -- Secure Enclave -- GIC-400 -- Trusted Board Boot - -Boot Sequence -------------- - -The board boot relies on CoT (chain of trust). The trusted-firmware-a -BL2 is extracted from the FIP and verified by the Secure Enclave -processor. BL2 verification relies on the signature area at the -beginning of the BL2 image. This area is needed by the SecureEnclave -bootloader. - -Then, the application processor is released from reset and starts by -executing BL2. - -BL2 performs the actions described in the trusted-firmware-a TBB design -document. - -Build Procedure (TF-A only) -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- Obtain AArch64 ELF bare-metal target `toolchain `_. - Set the CROSS_COMPILE environment variable to point to the toolchain folder. - -- Build TF-A: - - .. code:: shell - - make LD=aarch64-none-elf-ld \ - CC=aarch64-none-elf-gcc \ - V=1 \ - BUILD_BASE= \ - PLAT=diphda \ - SPD=spmd \ - SPMD_SPM_AT_SEL2=0 \ - DEBUG=1 \ - MBEDTLS_DIR=mbedtls \ - OPENSSL_DIR= \ - RUNTIME_SYSROOT= \ - ARCH=aarch64 \ - TARGET_PLATFORM= \ - ENABLE_PIE=1 \ - BL2_AT_EL3=1 \ - CREATE_KEYS=1 \ - GENERATE_COT=1 \ - TRUSTED_BOARD_BOOT=1 \ - COT=tbbr \ - ARM_ROTPK_LOCATION=devel_rsa \ - ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ - BL32= \ - BL33= \ - bl2 - -*Copyright (c) 2021, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/plat/arm/fvp/index.rst 2.7.0+dfsg-2/docs/plat/arm/fvp/index.rst --- 2.6+dfsg-1/docs/plat/arm/fvp/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/arm/fvp/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -12,7 +12,7 @@ Arm FVPs without shifted affinities, and (64-bit host machine only). .. note:: - The FVP models used are Version 11.16 Build 16, unless otherwise stated. + The FVP models used are Version 11.17 Build 21, unless otherwise stated. - ``Foundation_Platform`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` @@ -48,12 +48,12 @@ Arm FVPs without shifted affinities, and - ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38) - ``FVP_Base_Neoverse-V1x4`` - ``FVP_Base_RevC-2xAEMvA`` (For certain configurations also uses 0.0/6557) -- ``FVP_CSS_SGI-575`` (Version 11.15/26) -- ``FVP_Morello`` (Version 0.11/19) -- ``FVP_RD_E1_edge`` (Version 11.15/26) -- ``FVP_RD_N1_edge_dual`` (Version 11.15/26) -- ``FVP_RD_N1_edge`` (Version 11.15/26) -- ``FVP_RD_V1`` (Version 11.15/26) +- ``FVP_CSS_SGI-575`` (Version 11.17/33) +- ``FVP_Morello`` (Version 0.11/33) +- ``FVP_RD_E1_edge`` (Version 11.17/33) +- ``FVP_RD_N1_edge_dual`` (Version 11.17/33) +- ``FVP_RD_N1_edge`` (Version 11.17/33) +- ``FVP_RD_V1`` (Version 11.17/33) - ``FVP_TC0`` - ``FVP_TC1`` @@ -392,7 +392,8 @@ Notes: - BL1 is loaded at the start of the Trusted ROM. - The Firmware Image Package is loaded at the start of NOR FLASH0. - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address - is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. + is specified via the ``load-address`` property in the ``hw-config`` node of + `FW_CONFIG for FVP`_. - The default use-case for the Foundation FVP is to use the ``--gicv3`` option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which @@ -643,9 +644,9 @@ boot Linux with 4 CPUs using the AArch32 -------------- -*Copyright (c) 2019-2021, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* -.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts +.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts .. _Arm's website: `FVP models`_ .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms .. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01 diff -pruN 2.6+dfsg-1/docs/plat/arm/index.rst 2.7.0+dfsg-2/docs/plat/arm/index.rst --- 2.6+dfsg-1/docs/plat/arm/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/arm/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -13,7 +13,7 @@ Arm Development Platforms arm_fpga/index arm-build-options morello/index - diphda/index + corstone1000/index This chapter holds documentation related to Arm's development platforms, including both software models (FVPs) and hardware development boards diff -pruN 2.6+dfsg-1/docs/plat/imx8m.rst 2.7.0+dfsg-2/docs/plat/imx8m.rst --- 2.6+dfsg-1/docs/plat/imx8m.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/imx8m.rst 2022-06-01 15:02:46.000000000 +0000 @@ -60,3 +60,11 @@ BL2 will be in the FIT image and SPL wil All of the BL3x will be put in the FIP image. BL2 will verify them. In U-boot we turn on the UEFI secure boot features so it can verify grub. And we use grub to verify linux kernel. + +Measured Boot +------------- + +When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs +with a DTB overlay. The overlay will be put at PLAT_IMX8M_DTO_BASE with +maximum size PLAT_IMX8M_DTO_MAX_SIZE. Then in U-boot we can apply the DTB +overlay and let U-boot to parse the event log and update the PCRs. diff -pruN 2.6+dfsg-1/docs/plat/index.rst 2.7.0+dfsg-2/docs/plat/index.rst --- 2.6+dfsg-1/docs/plat/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -20,18 +20,19 @@ Platform Ports intel-stratix10 marvell/index mt8183 + mt8186 mt8192 mt8195 nvidia-tegra warp7 imx8 imx8m - ls1043a nxp/index poplar qemu qemu-sbsa qti + qti-msm8916 rpi3 rpi4 rcar-gen3 diff -pruN 2.6+dfsg-1/docs/plat/ls1043a.rst 2.7.0+dfsg-2/docs/plat/ls1043a.rst --- 2.6+dfsg-1/docs/plat/ls1043a.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/ls1043a.rst 1970-01-01 00:00:00.000000000 +0000 @@ -1,91 +0,0 @@ -NXP QorIQ® LS1043A -================== - -The QorIQ® LS1043A processor is NXP's first quad-core, 64-bit Arm®-based -processor for embedded networking. The LS1023A (two core version) and the -LS1043A (four core version) deliver greater than 10 Gbps of performance -in a flexible I/O package supporting fanless designs. This SoC is a -purpose-built solution for small-form-factor networking and industrial -applications with BOM optimizations for economic low layer PCB, lower cost -power supply and single clock design. The new 0.9V versions of the LS1043A -and LS1023A deliver addition power savings for applications such as Wireless -LAN and to Power over Ethernet systems. - -LS1043ARDB Specification: -------------------------- -Memory subsystem: - * 2GByte DDR4 SDRAM (32bit bus) - * 128 Mbyte NOR flash single-chip memory - * 512 Mbyte NAND flash - * 16 Mbyte high-speed SPI flash - * SD connector to interface with the SD memory card - -Ethernet: - * XFI 10G port - * QSGMII with 4x 1G ports - * Two RGMII ports - -PCIe: - * PCIe2 (Lanes C) to mini-PCIe slot - * PCIe3 (Lanes D) to PCIe slot - -USB 3.0: two super speed USB 3.0 type A ports - -UART: supports two UARTs up to 115200 bps for console - -More information are listed in `ls1043`_. - -Boot Sequence -------------- - - -Bootrom --> TF-A BL1 --> TF-A BL2 --> TF-A BL1 --> TF-A BL31 ---> BL32(Tee OS) --> TF-A BL31 --> BL33(u-boot) --> Linux kernel - - -How to build ------------- - -Build Procedure -~~~~~~~~~~~~~~~ - -- Prepare AARCH64 toolchain. - -- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin - -- Build TF-A for Nor boot - - Build bl1: - - .. code:: shell - - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 bl1 - - Build fip: - - .. code:: shell - - CROSS_COMPILE=aarch64-linux-gnu- make PLAT=ls1043 fip \ - BL33=u-boot.bin NEED_BL32=yes BL32=tee.bin SPD=opteed - -Deploy TF-A Images -~~~~~~~~~~~~~~~~~~ - -- Deploy TF-A images on Nor flash Alt Bank. - - .. code:: shell - - => tftp 82000000 bl1.bin - => pro off all;era 64100000 +$filesize;cp.b 82000000 64100000 $filesize - - => tftp 82000000 fip.bin - => pro off all;era 64120000 +$filesize;cp.b 82000000 64120000 $filesize - - Then change to Alt bank and boot up TF-A: - - .. code:: shell - - => cpld reset altbank - - -.. _ls1043: https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/qoriq-layerscape-arm-processors/qoriq-layerscape-1043a-and-1023a-multicore-communications-processors:LS1043A?lang_cd=en diff -pruN 2.6+dfsg-1/docs/plat/marvell/armada/build.rst 2.7.0+dfsg-2/docs/plat/marvell/armada/build.rst --- 2.6+dfsg-1/docs/plat/marvell/armada/build.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/marvell/armada/build.rst 2022-06-01 15:02:46.000000000 +0000 @@ -68,8 +68,9 @@ There are several build options: - DEBUG Default is without debug information (=0). in order to enable it use ``DEBUG=1``. - Must be disabled when building UART recovery images due to current console driver - implementation that is not compatible with Xmodem protocol used for boot image download. + Can be enabled also when building UART recovery images, there is no issue with it. + + Production TF-A images should be built without this debug option! - LOG_LEVEL @@ -258,7 +259,7 @@ Armada37x0 specific build options for `` Image needs to be stored at disk LBA 0 or at disk partition with MBR type 0x4d (ASCII 'M' as in Marvell) or at disk partition with - GPT name ``MARVELL BOOT PARTITION``. + GPT partition type GUID ``6828311A-BA55-42A4-BCDE-A89BB5EDECAE``. - PARTNUM @@ -317,11 +318,19 @@ Armada37x0 specific build options for `` Use this parameter to point to the directory with compiled Crypto++ library. By default it points to the CRYPTOPP_PATH. + On Debian systems it is possible to install system-wide Crypto++ library + via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_LIBDIR + to ``/usr/lib/``. + - CRYPTOPP_INCDIR Use this parameter to point to the directory with header files of Crypto++ library. By default it points to the CRYPTOPP_PATH. + On Debian systems it is possible to install system-wide Crypto++ library + via command ``apt install libcrypto++-dev`` and specify CRYPTOPP_INCDIR + to ``/usr/include/crypto++/``. + For example, in order to build the image in debug mode with log level up to 'notice' level run diff -pruN 2.6+dfsg-1/docs/plat/mt8186.rst 2.7.0+dfsg-2/docs/plat/mt8186.rst --- 2.6+dfsg-1/docs/plat/mt8186.rst 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/mt8186.rst 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,21 @@ +MediaTek 8186 +============= + +MediaTek 8186 (MT8186) is a 64-bit ARM SoC introduced by MediaTek in 2021. +The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A76. +Cortex-A76 can operate at up to 2.05 GHz. +Cortex-A55 can operate at up to 2.0 GHz. + +Boot Sequence +------------- + +:: + + Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel + +How to Build +------------ + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8186 DEBUG=1 COREBOOT=1 diff -pruN 2.6+dfsg-1/docs/plat/nxp/nxp-layerscape.rst 2.7.0+dfsg-2/docs/plat/nxp/nxp-layerscape.rst --- 2.6+dfsg-1/docs/plat/nxp/nxp-layerscape.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/nxp/nxp-layerscape.rst 2022-06-01 15:02:46.000000000 +0000 @@ -40,7 +40,7 @@ The integrated GPU and LCD controller en Details about LS1028A can be found at `ls1028a`_. -- LS1028ARDB Boards: +- LS1028ARDB Board: The LS1028A reference design board (RDB) is a computing, evaluation, and development platform that supports industrial IoT applications, human @@ -48,6 +48,105 @@ machine interface solutions, and industr Details about LS1028A RDB board can be found at `ls1028ardb`_. +3. LS1043A + +- SoC Overview: + +The Layerscape LS1043A processor is NXP's first quad-core, 64-bit Arm®-based +processor for embedded networking. The LS1023A (two core version) and the +LS1043A (four core version) deliver greater than 10 Gbps of performance +in a flexible I/O package supporting fanless designs. This SoC is a +purpose-built solution for small-form-factor networking and industrial +applications with BOM optimizations for economic low layer PCB, lower cost +power supply and single clock design. The new 0.9V versions of the LS1043A +and LS1023A deliver addition power savings for applications such as Wireless +LAN and to Power over Ethernet systems. + +Details about LS1043A can be found at `ls1043a`_. + +- LS1043ARDB Board: + +The LS1043A reference design board (RDB) is a computing, evaluation, and +development platform that supports the Layerscape LS1043A architecture +processor. The LS1043A-RDB can help shorten your time to market by providing +the following features: + +Memory subsystem: + * 2GByte DDR4 SDRAM (32bit bus) + * 128 Mbyte NOR flash single-chip memory + * 512 Mbyte NAND flash + * 16 Mbyte high-speed SPI flash + * SD connector to interface with the SD memory card + +Ethernet: + * XFI 10G port + * QSGMII with 4x 1G ports + * Two RGMII ports + +PCIe: + * PCIe2 (Lanes C) to mini-PCIe slot + * PCIe3 (Lanes D) to PCIe slot + +USB 3.0: two super speed USB 3.0 type A ports + +UART: supports two UARTs up to 115200 bps for console + +Details about LS1043A RDB board can be found at `ls1043ardb`_. + +4. LS1046A + +- SoC Overview: + +The LS1046A is a cost-effective, power-efficient, and highly integrated +system-on-chip (SoC) design that extends the reach of the NXP value-performance +line of QorIQ communications processors. Featuring power-efficient 64-bit +Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high +reliability, running up to 1.8 GHz. + +Details about LS1046A can be found at `ls1046a`_. + +- LS1046ARDB Board: + +The LS1046A reference design board (RDB) is a high-performance computing, +evaluation, and development platform that supports the Layerscape LS1046A +architecture processor. The LS1046ARDB board supports the Layerscape LS1046A +processor and is optimized to support the DDR4 memory and a full complement +of high-speed SerDes ports. + +Details about LS1046A RDB board can be found at `ls1046ardb`_. + +- LS1046AFRWY Board: + +The LS1046A Freeway board (FRWY) is a high-performance computing, evaluation, +and development platform that supports the LS1046A architecture processor +capable of support more than 32,000 CoreMark performance. The FRWY-LS1046A +board supports the LS1046A processor, onboard DDR4 memory, multiple Gigabit +Ethernet, USB3.0 and M2_Type_E interfaces for Wi-Fi, FRWY-LS1046A-AC includes +the Wi-Fi card. + +Details about LS1046A FRWY board can be found at `ls1046afrwy`_. + +5. LS1088A + +- SoC Overview: + +The LS1088A family of multicore communications processors combines up to and eight +Arm Cortex-A53 cores with the advanced, high-performance data path and network +peripheral interfaces required for wireless access points, networking infrastructure, +intelligent edge access, including virtual customer premise equipment (vCPE) and +high-performance industrial applications. + +Details about LS1088A can be found at `ls1088a`_. + +- LS1088ARDB Board: + +The LS1088A reference design board provides a comprehensive platform that +enables design and evaluation of the product (LS1088A processor). This RDB +comes pre-loaded with a board support package (BSP) based on a standard +Linux kernel. + +Details about LS1088A RDB board can be found at `ls1088ardb`_. + Table of supported boot-modes by each platform & platform that needs FIP-DDR: ----------------------------------------------------------------------------- @@ -60,6 +159,14 @@ Table of supported boot-modes by each pl +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ | ls1028ardb | yes | | | | yes | yes | | no | +---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ +| ls1043ardb | yes | | yes | yes | | | | no | ++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ +| ls1046ardb | yes | yes | | | yes | | | no | ++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ +| ls1046afrwy | yes | yes | | | | | | no | ++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ +| ls1088ardb | yes | yes | | | | | | no | ++---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ Boot Sequence @@ -228,30 +335,42 @@ Deploy ATF Images Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd should be modified based on the binary size of the image to be copied. -- Deploy ATF images on flexspi-Nor flash Alt Bank from U-Boot prompt. - -- Commands to flash images for bl2_xxx.pbl and fip.bin. +- Deploy ATF images on flexspi-Nor or QSPI flash Alt Bank from U-Boot prompt. + + -- Commands to flash images for bl2_xxx.pbl and fip.bin + + Notes: ls1028ardb has no flexspi-Nor Alt Bank, so use "sf probe 0:0" for current bank. .. code:: shell - tftp 82000000 $path/bl2_flexspi_nor.pbl; - i2c mw 66 50 20;sf probe 0:0; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize; + tftp 82000000 $path/bl2_xxx.pbl; + + i2c mw 66 50 20;sf probe 0:1; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize; tftp 82000000 $path/fip.bin; - i2c mw 66 50 20;sf probe 0:0; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize; + i2c mw 66 50 20;sf probe 0:1; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize; -- Next step is valid for platform where FIP-DDR is needed. .. code:: shell tftp 82000000 $path/ddr_fip.bin; - i2c mw 66 50 20;sf probe 0:0; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize; + i2c mw 66 50 20;sf probe 0:1; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize; -- Then reset to alternate bank to boot up ATF. + Command for lx2160a, ls1088a and ls1028a platforms: + .. code:: shell qixisreset altbank; + Command for ls1046a platforms: + + .. code:: shell + + cpld reset altbank; + - Deploy ATF images on SD/eMMC from U-Boot prompt. -- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512) @@ -274,10 +393,56 @@ should be modified based on the binary s -- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source. + Command for lx2160A, ls1088a and ls1028a platforms: + .. code:: shell qixisreset ; + Command for ls1043a and ls1046a platform: + + .. code:: shell + + cpld reset ; + +- Deploy ATF images on IFC nor flash from U-Boot prompt. + + .. code:: shell + + tftp 82000000 $path/bl2_nor.pbl; + protect off 64000000 +$filesize; erase 64000000 +$filesize; cp.b 82000000 64000000 $filesize; + + tftp 82000000 $path/fip.bin; + protect off 64100000 +$filesize; erase 64100000 +$filesize; cp.b 82000000 64100000 $filesize; + + -- Then reset to alternate bank to boot up ATF. + + Command for ls1043a platform: + + .. code:: shell + + cpld reset altbank; + +- Deploy ATF images on IFC nand flash from U-Boot prompt. + + .. code:: shell + + tftp 82000000 $path/bl2_nand.pbl; + nand erase 0x0 $filesize; nand write 82000000 0x0 $filesize; + + tftp 82000000 $path/fip.bin; + nand erase 0x100000 $filesize;nand write 82000000 0x100000 $filesize; + + -- Then reset to nand flash to boot up ATF. + + Command for ls1043a platform: + + .. code:: shell + + cpld reset nand; + + + Trusted Board Boot: =================== @@ -298,4 +463,11 @@ Refer `nxp-ls-tbbr.rst`_ for detailed us .. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A .. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A .. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB +.. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A +.. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB +.. _ls1046a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1046a-and-1026a-processors:LS1046A +.. _ls1046ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB +.. _ls1046afrwy: https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A +.. _ls1088a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1088a-and-1048a-processor:LS1088A +.. _ls1088ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1088a-reference-design-board:LS1088A-RDB .. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst diff -pruN 2.6+dfsg-1/docs/plat/qti-msm8916.rst 2.7.0+dfsg-2/docs/plat/qti-msm8916.rst --- 2.6+dfsg-1/docs/plat/qti-msm8916.rst 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/qti-msm8916.rst 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,116 @@ +Qualcomm Snapdragon 410 (MSM8916/APQ8016) +========================================= + +The `Qualcomm Snapdragon 410`_ is Qualcomm's first 64-bit SoC, released in 2014 +with four ARM Cortex-A53 cores. There are differents variants (MSM8916, +APQ8016(E), ...) that are all very similar. A popular device based on APQ8016E +is the `DragonBoard 410c`_ single-board computer, but the SoC is also used in +various mid-range smartphones/tablets. + +The TF-A/BL31 port for MSM8916 provides a minimal, community-maintained +EL3 firmware. It is primarily based on information from the public +`Snapdragon 410E Technical Reference Manual`_ combined with a lot of +trial and error to actually make it work. + +.. note:: + Unlike the :doc:`QTI SC7180/SC7280 ` ports, this port does **not** + make use of a proprietary binary components (QTISECLIB). It is fully + open-source but therefore limited to publicly documented hardware + components. + +Functionality +------------- + +The BL31 port is much more minimal compared to the original firmware and +therefore expects the non-secure world (e.g. Linux) to manage more hardware, +such as the SMMUs and all remote processors (RPM, WCNSS, Venus, Modem). +Everything except modem is currently functional with a slightly modified version +of mainline Linux. + +.. warning:: + This port is **not secure**. There is no special secure memory and the + used DRAM is available from both the non-secure and secure worlds. + Unfortunately, the hardware used for memory protection is not described + in the APQ8016E documentation. + +The port is primarily intended as a minimal PSCI implementation (without a +separate secure world) where this limitation is not a big problem. Booting +secondary CPU cores (PSCI ``CPU_ON``) is supported. Basic CPU core power +management (``CPU_SUSPEND``) is functional but still work-in-progress and +will be added later once ready. + +Boot Flow +--------- +BL31 replaces the original ``tz`` firmware in the boot flow:: + + Boot ROM (PBL) -> SBL -> BL31 (EL3) -> U-Boot (EL2) -> Linux (EL2) + +By default, BL31 enters the non-secure world in EL2 AArch64 state at address +``0x8f600000``. The original hypervisor firmware (``hyp``) is not used, you can +use KVM or another hypervisor. The entry address is fixed in the BL31 binary +but can be changed using the ``PRELOADED_BL33_BASE`` make file parameter. + +Using an AArch64 bootloader (such as `U-Boot for DragonBoard 410c`_) is +recommended. AArch32 bootloaders (such as the original Little Kernel bootloader +from Qualcomm) are not directly supported, although it is possible to use an EL2 +shim loader to temporarily switch to AArch32 state. + +Installation +------------ +First, setup the cross compiler for AArch64 and build TF-A for ``msm8916``:: + + $ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=msm8916 + +The BL31 ELF image is generated in ``build/msm8916/release/bl31/bl31.elf``. +This image must be "signed" before flashing it, even if the board has secure +boot disabled. In this case the signature does not provide any security, +but it provides the firmware with required metadata. + +The `DragonBoard 410c`_ does not have secure boot enabled by default. In this +case you can simply sign the ELF image using a randomly generated key. You can +use e.g. `qtestsign`_:: + + $ ./qtestsign.py tz build/msm8916/release/bl31/bl31.elf + +Then install the resulting ``build/msm8916/release/bl31/bl31-test-signed.mbn`` +to the ``tz`` partition on the device. BL31 should be running after a reboot. + +.. warning:: + Do not flash incorrectly signed firmware on devices that have secure + boot enabled! Make sure that you have a way to recover the board in case + of problems (e.g. using EDL). + +Boot Trace +---------- +BL31 prints some lines on the debug console UART2, which will usually look like +this (with ``DEBUG=1``, otherwise only the ``NOTICE`` lines are shown):: + + ... + S - DDR Frequency, 400 MHz + NOTICE: BL31: v2.6(debug):v2.6 + NOTICE: BL31: Built : 20:00:00, Dec 01 2021 + INFO: BL31: Platform setup start + INFO: ARM GICv2 driver initialized + INFO: BL31: Platform setup done + INFO: BL31: Initializing runtime services + INFO: BL31: cortex_a53: CPU workaround for 819472 was applied + INFO: BL31: cortex_a53: CPU workaround for 824069 was applied + INFO: BL31: cortex_a53: CPU workaround for 826319 was applied + INFO: BL31: cortex_a53: CPU workaround for 827319 was applied + INFO: BL31: cortex_a53: CPU workaround for 835769 was applied + INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied + INFO: BL31: cortex_a53: CPU workaround for 843419 was applied + INFO: BL31: cortex_a53: CPU workaround for 1530924 was applied + INFO: BL31: Preparing for EL3 exit to normal world + INFO: Entry point address = 0x8f600000 + INFO: SPSR = 0x3c9 + + U-Boot 2021.10 (Dec 01 2021 - 20:00:00 +0000) + Qualcomm-DragonBoard 410C + ... + +.. _Qualcomm Snapdragon 410: https://www.qualcomm.com/products/snapdragon-processors-410 +.. _DragonBoard 410c: https://www.96boards.org/product/dragonboard410c/ +.. _Snapdragon 410E Technical Reference Manual: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf +.. _U-Boot for DragonBoard 410c: https://u-boot.readthedocs.io/en/latest/board/qualcomm/dragonboard410c.html +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign diff -pruN 2.6+dfsg-1/docs/plat/stm32mp1.rst 2.7.0+dfsg-2/docs/plat/stm32mp1.rst --- 2.6+dfsg-1/docs/plat/stm32mp1.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/stm32mp1.rst 2022-06-01 15:02:46.000000000 +0000 @@ -2,15 +2,34 @@ STMicroelectronics STM32MP1 =========================== STM32MP1 is a microprocessor designed by STMicroelectronics -based on a dual Arm Cortex-A7. +based on Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. -The STM32MP1 chip also embeds a Cortex-M4. More information can be found on `STM32MP1 Series`_ page. STM32MP1 Versions ----------------- -The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: + +There are 2 variants for STM32MP1: STM32MP13 and STM32MP15 + +STM32MP13 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP131: Single Cortex-A7 core +- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 +- STM32MP135: STM32MP133 + DCMIPP, LTDC + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Cortex-A7 @ 900 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz + +STM32MP15 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD @@ -115,6 +134,28 @@ Available storage medias are: - ``STM32MP_SPI_NAND`` - ``STM32MP_SPI_NOR`` +Serial boot devices: + +- ``STM32MP_UART_PROGRAMMER`` +- ``STM32MP_USB_PROGRAMMER`` + + +Other configuration flags: + +- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. + | Default: stm32mp157c-ev1.dtb +- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. + | Default: 0 (disabled) +- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. + | Default: 115200 +- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. + | Default: 0 +- | ``STM32MP13``: to select STM32MP13 variant configuration. + | Default: 0 +- | ``STM32MP15``: to select STM32MP15 variant configuration. + | Default: 1 + + Boot with FIP ~~~~~~~~~~~~~ You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary. diff -pruN 2.6+dfsg-1/docs/plat/xilinx-versal.rst 2.7.0+dfsg-2/docs/plat/xilinx-versal.rst --- 2.6+dfsg-1/docs/plat/xilinx-versal.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/xilinx-versal.rst 2022-06-01 15:02:46.000000000 +0000 @@ -43,6 +43,8 @@ Xilinx Versal platform specific build op * `VERSAL_PLATFORM`: Select the platform. Options: - `versal_virt` : Versal Virtual platform + - `spp_itr6` : SPP ITR6 + - `emu_itr6` : EMU ITR6 # PLM->TF-A Parameter Passing ------------------------------ diff -pruN 2.6+dfsg-1/docs/plat/xilinx-zynqmp.rst 2.7.0+dfsg-2/docs/plat/xilinx-zynqmp.rst --- 2.6+dfsg-1/docs/plat/xilinx-zynqmp.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/plat/xilinx-zynqmp.rst 2022-06-01 15:02:46.000000000 +0000 @@ -14,13 +14,13 @@ To build: .. code:: bash - make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 + make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 To build bl32 TSP you have to rebuild bl31 too: .. code:: bash - make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 + make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32 To build TF-A for JTAG DCC console: diff -pruN 2.6+dfsg-1/docs/process/commit-style.rst 2.7.0+dfsg-2/docs/process/commit-style.rst --- 2.6+dfsg-1/docs/process/commit-style.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/process/commit-style.rst 2022-06-01 15:02:46.000000000 +0000 @@ -79,11 +79,10 @@ The following `types` are permissible an +--------------+---------------------------------------------------------------+ The permissible `scopes` are more flexible, and we maintain a list of them in -our :download:`Commitizen configuration file <../../.cz.json>`. Scopes in this -file are organized by their changelog section, each of which may have one or -more accepted scopes, but only the first of which is considered to be "blessed". -Scopes that are not blessed exist for changes submitted before scope enforcement -came into effect, and are considered deprecated. +our :download:`changelog configuration file <../../changelog.yaml>`. Scopes in +this file are organized by their changelog section, where each changelog section +has a single scope that is considered to be blessed, and possibly several +deprecated scopes. Please avoid using deprecated scopes. While we don't enforce scopes strictly, we do ask that commits use these if they can, or add their own if no appropriate one exists (see :ref:`Adding Scopes`). diff -pruN 2.6+dfsg-1/docs/process/contributing.rst 2.7.0+dfsg-2/docs/process/contributing.rst --- 2.6+dfsg-1/docs/process/contributing.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/process/contributing.rst 2022-06-01 15:02:46.000000000 +0000 @@ -1,8 +1,8 @@ Contributor's Guide -=================== +******************* Getting Started ---------------- +=============== - Make sure you have a Github account and you are logged on both `developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_. @@ -24,7 +24,7 @@ Getting Started branch. Making Changes --------------- +============== - Ensure commits adhere to the the project's :ref:`Commit Style`. @@ -91,7 +91,7 @@ Making Changes block a patch, depending on how critical they are. Submitting Changes ------------------- +================== - Submit your changes for review at https://review.trustedfirmware.org targeting the ``integration`` branch. @@ -164,13 +164,17 @@ Submitting Changes revert your patches and ask you to resubmit a reworked version of them or they may ask you to provide a fix-up patch. -Add Build Configurations ------------------------- +Add CI Configurations +===================== - TF-A uses Jenkins tool for Continuous Integration and testing activities. Various CI Jobs are deployed which run tests on every patch before being merged. So each of your patches go through a series of checks before they - get merged on to the master branch. + get merged on to the master branch. Kindly ensure, that everytime you add + new files under your platform, they are covered under the following two sections: + +Coverity Scan +------------- - ``Coverity Scan analysis`` is one of the tests we perform on our source code at regular intervals. We maintain a build script ``tf-cov-make`` which contains the @@ -182,7 +186,7 @@ Add Build Configurations respective build configurations in the ``tf-cov-make`` build script. - In this section you find the details on how to append your new build - configurations for Coverity Scan analysis: + configurations for Coverity scan analysis illustrated with examples: #. We maintain a separate repository named `tf-a-ci-scripts repository`_ for placing all the test scripts which will be executed by the CI Jobs. @@ -223,8 +227,51 @@ Add Build Configurations of various other platforms listed in the ``tf-cov-make`` script. Kindly refer them and append your build configurations respectively. +Test Build Configuration (``tf-l1-build-plat``) +----------------------------------------------- + +- Coverity Scan analysis, runs on a daily basis and will not be triggered for + every individual trusted-firmware patch. + +- Considering this, we have other distinguished CI jobs which run a set of test + configurations on every patch, before they are being passed to ``Coverity scan analysis``. + +- ``tf-l1-build-plat`` is the test group, which holds the test configurations + to build all the platforms. So be kind enough to verify that your newly added + files are built as part of one of the existing platform configurations present + in ``tf-l1-build-plat`` test group. + +- In this section you find the details on how to add the appropriate files, + needed to build your newly introduced platform as part of ``tf-l1-build-plat`` + test group, illustrated with an example: + +- Lets consider ``Hikey`` platform: + In the `tf-a-ci-scripts repository`_ we need to add a build configuration file ``hikey-default`` + under tf_config folder, ``tf_config/hikey-default`` listing all the build parameters + relevant to it. + +.. code:: shell + + #Hikey Build Parameters + CROSS_COMPILE=aarch64-none-elf- + PLAT=hikey + +- Further a test-configuration file ``hikey-default:nil`` need to be added under the + test group, ``tf-l1-build-plat`` located at ``tf-a-ci-scripts/group/tf-l1-build-plat``, + to allow the platform to be built as part of this group. + +.. code:: shell + + # + # Copyright (c) 2019-2022 Arm Limited. All rights reserved. + # + # SPDX-License-Identifier: BSD-3-Clause + # + +- As illustrated above, you need to add the similar files supporting your platform. + Binary Components ------------------ +================= - Platforms may depend on binary components submitted to the `Trusted Firmware binary repository`_ if they require code that the contributor is unable or @@ -242,7 +289,7 @@ Binary Components -------------- -*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.* .. _developer.trustedfirmware.org: https://developer.trustedfirmware.org .. _review.trustedfirmware.org: https://review.trustedfirmware.org @@ -252,6 +299,6 @@ Binary Components .. _TF-A Tests: https://trustedfirmware-a-tests.readthedocs.io .. _Trusted Firmware binary repository: https://review.trustedfirmware.org/admin/repos/tf-binaries .. _tf-binaries-readme: https://git.trustedfirmware.org/tf-binaries.git/tree/readme.rst -.. _TF-A mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a +.. _TF-A mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ .. _tf-a-ci-scripts repository: https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/ .. _tf-cov-make: https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/tf-coverity/tf-cov-make diff -pruN 2.6+dfsg-1/docs/process/platform-compatibility-policy.rst 2.7.0+dfsg-2/docs/process/platform-compatibility-policy.rst --- 2.6+dfsg-1/docs/process/platform-compatibility-policy.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/process/platform-compatibility-policy.rst 2022-06-01 15:02:46.000000000 +0000 @@ -31,6 +31,6 @@ the deprecated interface. -------------- -*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.* -.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a +.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ diff -pruN 2.6+dfsg-1/docs/process/security.rst 2.7.0+dfsg-2/docs/process/security.rst --- 2.6+dfsg-1/docs/process/security.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/process/security.rst 2022-06-01 15:02:46.000000000 +0000 @@ -71,7 +71,7 @@ Security Advisories +-----------+------------------------------------------------------------------+ .. _issue tracker: https://developer.trustedfirmware.org/project/board/1/ -.. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a +.. _mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ .. |TFV-1| replace:: :ref:`Advisory TFV-1 (CVE-2016-10319)` .. |TFV-2| replace:: :ref:`Advisory TFV-2 (CVE-2017-7564)` @@ -86,4 +86,4 @@ Security Advisories -------------- -*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* Binary files 2.6+dfsg-1/docs/resources/diagrams/context_management_abs.png and 2.7.0+dfsg-2/docs/resources/diagrams/context_management_abs.png differ Binary files 2.6+dfsg-1/docs/resources/diagrams/context_mgmt_existing.png and 2.7.0+dfsg-2/docs/resources/diagrams/context_mgmt_existing.png differ Binary files 2.6+dfsg-1/docs/resources/diagrams/context_mgmt_proposed.png and 2.7.0+dfsg-2/docs/resources/diagrams/context_mgmt_proposed.png differ Binary files 2.6+dfsg-1/docs/resources/diagrams/partition-package.png and 2.7.0+dfsg-2/docs/resources/diagrams/partition-package.png differ diff -pruN 2.6+dfsg-1/docs/security_advisories/index.rst 2.7.0+dfsg-2/docs/security_advisories/index.rst --- 2.6+dfsg-1/docs/security_advisories/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/security_advisories/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -14,3 +14,4 @@ Security Advisories security-advisory-tfv-6.rst security-advisory-tfv-7.rst security-advisory-tfv-8.rst + security-advisory-tfv-9.rst diff -pruN 2.6+dfsg-1/docs/security_advisories/security-advisory-tfv-9.rst 2.7.0+dfsg-2/docs/security_advisories/security-advisory-tfv-9.rst --- 2.6+dfsg-1/docs/security_advisories/security-advisory-tfv-9.rst 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/docs/security_advisories/security-advisory-tfv-9.rst 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,104 @@ +Advisory TFV-9 (CVE-2022-23960) +============================================================ + ++----------------+-------------------------------------------------------------+ +| Title | Trusted Firmware-A exposure to speculative processor | +| | vulnerabilities with branch prediction target reuse | ++================+=============================================================+ +| CVE ID | `CVE-2022-23960`_ | ++----------------+-------------------------------------------------------------+ +| Date | 08 Mar 2022 | ++----------------+-------------------------------------------------------------+ +| Versions | All, up to and including v2.6 | +| Affected | | ++----------------+-------------------------------------------------------------+ +| Configurations | All | +| Affected | | ++----------------+-------------------------------------------------------------+ +| Impact | Potential leakage of secure world data to normal world | +| | if an attacker is able to find a TF-A exfiltration primitive| +| | that can be predicted as a valid branch target, and somehow | +| | induce misprediction onto that primitive. There are | +| | currently no known exploits. | ++----------------+-------------------------------------------------------------+ +| Fix Version | `Gerrit topic #spectre_bhb`_ | ++----------------+-------------------------------------------------------------+ +| Credit | Systems and Network Security Group at Vrije Universiteit | +| | Amsterdam for CVE-2022-23960, Arm for patches | ++----------------+-------------------------------------------------------------+ + +This security advisory describes the current understanding of the Trusted +Firmware-A exposure to the new speculative processor vulnerability. +To understand the background and wider impact of these vulnerabilities on Arm +systems, please refer to the `Arm Processor Security Update`_. The whitepaper +referred to below describes the Spectre attack and mitigation in more detail +including implementation specific mitigation details for all impacted Arm CPUs. + + +`CVE-2022-23960`_ +----------------- + +Where possible on vulnerable CPUs that implement FEAT_CSV2, Arm recommends +inserting a loop workaround with implementation specific number of iterations +that will discard the branch history on exception entry to a higher exception +level for the given CPU. This is done as early as possible on entry into EL3, +before any branch instruction is executed. This is sufficient to mitigate +Spectre-BHB on behalf of all secure world code, assuming that no secure world +code is under attacker control. + +The below table lists the CPUs that mitigate against this vulnerability in +TF-A using the loop workaround(all cores that implement FEAT_CSV2 except the +revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2). + ++----------------------+ +| Core | ++----------------------+ +| Cortex-A72(from r1p0)| ++----------------------+ +| Cortex-A76 | ++----------------------+ +| Cortex-A77 | ++----------------------+ +| Cortex-A78 | ++----------------------+ +| Cortex-X2 | ++----------------------+ +| Cortex-A710 | ++----------------------+ +| Neoverse-N1 | ++----------------------+ +| Neoverse-N2 | ++----------------------+ +| Neoverse-V1 | ++----------------------+ + +For all other cores impacted by Spectre-BHB, some of which that do not implement +FEAT_CSV2 and some that do e.g. Cortex-A73, the recommended mitigation is to +flush all branch predictions via an implementation specific route. + +In case local workaround is not feasible, the Rich OS can invoke the SMC +(``SMCCC_ARCH_WORKAROUND_3``) to apply the workaround. Refer to `SMCCC Calling +Convention specification`_ for more details. + +`Gerrit topic #spectre_bhb`_ This patchset implements the Spectre-BHB loop +workaround for CPUs mentioned in the above table. It also mitigates against +this vulnerability for Cortex-A72 CPU versions that support the CSV2 feature +(from r1p0). The patch stack also includes an implementation for a specified +`CVE-2022-23960`_ workaround SMC(``SMCCC_ARCH_WORKAROUND_3``) for use by normal +world privileged software. Details of ``SMCCC_ARCH_WORKAROUND_3`` can be found +in the `SMCCC Calling Convention specification`_. The specification and +implementation also enables the normal world to discover the presence of this +firmware service. This patch also implements ``SMCCC_ARCH_WORKAROUND_3`` for +Cortex-A57, Coxtex-A72, Cortex-A73 and Cortex-A75 using the existing workaround. +for CVE-2017-5715. + +The above workaround is enabled by default (on vulnerable CPUs only). Platforms +can choose to disable them at compile time if they do not require them. + +For more information about non-Arm CPUs, please contact the CPU vendor. + +.. _Arm Processor Security Update: http://www.arm.com/security-update +.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 +.. _Gerrit topic #spectre_bhb: https://review.trustedfirmware.org/q/topic:"spectre_bhb"+(status:open%20OR%20status:merged) +.. _CVE-2022-23960 mitigation specification: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability +.. _SMCCC Calling Convention specification: https://developer.arm.com/documentation/den0028/latest diff -pruN 2.6+dfsg-1/docs/threat_model/index.rst 2.7.0+dfsg-2/docs/threat_model/index.rst --- 2.6+dfsg-1/docs/threat_model/index.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/threat_model/index.rst 2022-06-01 15:02:46.000000000 +0000 @@ -15,6 +15,7 @@ based on the data flow diagram and poten threat_model threat_model_spm + threat_model_fvp_r -------------- diff -pruN 2.6+dfsg-1/docs/threat_model/threat_model_fvp_r.rst 2.7.0+dfsg-2/docs/threat_model/threat_model_fvp_r.rst --- 2.6+dfsg-1/docs/threat_model/threat_model_fvp_r.rst 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/docs/threat_model/threat_model_fvp_r.rst 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,97 @@ +fvp_r-Platform Threat Model +*************************** + +************************ +Introduction +************************ +This document provides a threat model for TF-A fvp_r platform. + +************************ +Target of Evaluation +************************ +In this threat model, the target of evaluation is the fvp_r platform of Trusted +Firmware for A-class Processors (TF-A). The fvp_r platform provides limited +support of AArch64 R-class Processors (v8-R64). + +This is a delta document, only pointing out differences from the general TF-A +threat-model document, :ref:`Generic Threat Model` + +BL1 Only +======== +The most fundamental difference between the threat model for the current fvp_r +implementation compared to the general TF-A threat model, is that fvp_r is +currently limited to BL1 only. Any threats from the general TF-A threat model +unrelated to BL1 are therefore not relevant to the fvp_r implementation. + +The fvp_r BL1 implementation directly loads a customer/partner-defined runtime +system. The threat model for that runtime system, being partner-defined, is +out-of-scope for this threat-model. + +Relatedly, all exceptions, synchronous and asynchronous, are disabled during BL1 +execution. So, any references to exceptions are not relevant. + +EL3 is Unsupported and All Secure +================================= +v8-R64 cores do not support EL3, and (essentially) all operation is defined as +Secure-mode. Therefore: + + - Any threats regarding NS operation are not relevant. + + - Any mentions of SMCs are also not relevant. + + - Anything otherwise-relevant code running in EL3 is instead run in EL2. + +MPU instead of MMU +================== +v8-R64 cores, running in EL2, use an MPU for memory management, rather than an +MMU. The MPU in the fvp_r implementation is configured to function effectively +identically with the MMU for the usual BL1 implementation. There are +memory-map differences, but the MPU configuration is functionally equivalent. + +No AArch32 Support +================== +Another substantial difference between v8-A and v8-R64 cores is that v8-R64 does +not support AArch32. However, this is not believed to have any threat-modeling +ramifications. + + +Threat Assessment +================= +For this section, please reference the Threat Assessment under the general TF-A +threat-model document, :ref:`Generic Threat Model` + +The following threats from that document are still relevant to the fvp_r +implementation: + + - ID 01: An attacker can mangle firmware images to execute arbitrary code. + + - ID 03: An attacker can use Time-of-Check-Time-of-Use (TOCTOU) attack to + bypass image authentication during the boot process. + + - ID 04: An attacker with physical access can execute arbitrary image by + bypassing the signature verification stage using clock- or power-glitching + techniques. + + - ID 05: Information leak via UART logs such as crashes + + - ID 06: An attacker can read sensitive data and execute arbitrary code + through the external debug and trace interface. + + - ID 08: Memory corruption due to memory overflows and lack of boundary + checking when accessing resources could allow an attacker to execute + arbitrary code, modify some state variable to change the normal flow of + the program, or leak sensitive. + + - ID 11: Misconfiguration of the Memory Protection Unit (MPU) may allow + normal world software to access sensitive data or execute arbitrary code. + Arguably, MPUs having fewer memory regions, there may be a temptation to + share memory regions, making this a greater threat. However, since the + fvp_r implementation is limited to BL1, since BL1's regions are fixed, + and since the MPU configuration is equivalent with that for the fvp + platform and others, this is not expected to be a concern. + + + +-------------- + +*Copyright (c) 2021, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/docs/threat_model/threat_model.rst 2.7.0+dfsg-2/docs/threat_model/threat_model.rst --- 2.6+dfsg-1/docs/threat_model/threat_model.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/threat_model/threat_model.rst 2022-06-01 15:02:46.000000000 +0000 @@ -1,9 +1,10 @@ -Generic threat model +Generic Threat Model ******************** -************************ +************ Introduction -************************ +************ + This document provides a generic threat model for TF-A firmware. .. note:: @@ -11,9 +12,10 @@ This document provides a generic threat This threat model doesn't consider Root and Realm worlds introduced by :ref:`Realm Management Extension (RME)`. -************************ +******************** Target of Evaluation -************************ +******************** + In this threat model, the target of evaluation is the Trusted Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1), the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as @@ -34,8 +36,15 @@ assumptions: - There is no Secure-EL2. We don't consider threats that may come with Secure-EL2 software. +- Measured boot is disabled. We do not consider the threats nor the mitigations + that may come with it. + +- No experimental features are enabled. We do not consider threats that may come + from them. + Data Flow Diagram -====================== +================= + Figure 1 shows a high-level data flow diagram for TF-A. The diagram shows a model of the different components of a TF-A-based system and their interactions with TF-A. A description of each diagram element @@ -51,26 +60,26 @@ are considered untrusted by TF-A. +-----------------+--------------------------------------------------------+ | Diagram Element | Description | +=================+========================================================+ - | ``DF1`` | | At boot time, images are loaded from non-volatile | + | DF1 | | At boot time, images are loaded from non-volatile | | | memory and verified by TF-A boot firmware. These | | | images include TF-A BL2 and BL31 images, as well as | | | other secure and non-secure images. | +-----------------+--------------------------------------------------------+ - | ``DF2`` | | TF-A log system framework outputs debug messages | + | DF2 | | TF-A log system framework outputs debug messages | | | over a UART interface. | +-----------------+--------------------------------------------------------+ - | ``DF3`` | | Debug and trace IP on a platform can allow access | + | DF3 | | Debug and trace IP on a platform can allow access | | | to registers and memory of TF-A. | +-----------------+--------------------------------------------------------+ - | ``DF4`` | | Secure world software (e.g. trusted OS) interact | + | DF4 | | Secure world software (e.g. trusted OS) interact | | | with TF-A through SMC call interface and/or shared | | | memory. | +-----------------+--------------------------------------------------------+ - | ``DF5`` | | Non-secure world software (e.g. rich OS) interact | + | DF5 | | Non-secure world software (e.g. rich OS) interact | | | with TF-A through SMC call interface and/or shared | | | memory. | +-----------------+--------------------------------------------------------+ - | ``DF6`` | | This path represents the interaction between TF-A and| + | DF6 | | This path represents the interaction between TF-A and| | | various hardware IPs such as TrustZone controller | | | and GIC. At boot time TF-A configures/initializes the| | | IPs and interacts with them at runtime through | @@ -78,9 +87,10 @@ are considered untrusted by TF-A. +-----------------+--------------------------------------------------------+ -********************* +*************** Threat Analysis -********************* +*************** + In this section we identify and provide assessment of potential threats to TF-A firmware. The threats are identified for each diagram element on the data flow diagram above. @@ -91,7 +101,8 @@ that represents the impact and likelihoo potential mitigations. Assets -================== +====== + We have identified the following assets for TF-A: .. table:: Table 2: TF-A Assets @@ -99,21 +110,22 @@ We have identified the following assets +--------------------+---------------------------------------------------+ | Asset | Description | +====================+===================================================+ - | ``Sensitive Data`` | | These include sensitive data that an attacker | + | Sensitive Data | | These include sensitive data that an attacker | | | must not be able to tamper with (e.g. the Root | | | of Trust Public Key) or see (e.g. secure logs, | | | debugging information such as crash reports). | +--------------------+---------------------------------------------------+ - | ``Code Execution`` | | This represents the requirement that the | + | Code Execution | | This represents the requirement that the | | | platform should run only TF-A code approved by | | | the platform provider. | +--------------------+---------------------------------------------------+ - | ``Availability`` | | This represents the requirement that TF-A | + | Availability | | This represents the requirement that TF-A | | | services should always be available for use. | +--------------------+---------------------------------------------------+ Threat Agents -===================== +============= + To understand the attack surface, it is important to identify potential attackers, i.e. attack entry points. The following threat agents are in scope of this threat model. @@ -123,16 +135,16 @@ in scope of this threat model. +-------------------+-------------------------------------------------------+ | Threat Agent | Description | +===================+=======================================================+ - | ``NSCode`` | | Malicious or faulty code running in the Non-secure | + | NSCode | | Malicious or faulty code running in the Non-secure | | | world, including NS-EL0 NS-EL1 and NS-EL2 levels | +-------------------+-------------------------------------------------------+ - | ``SecCode`` | | Malicious or faulty code running in the secure | + | SecCode | | Malicious or faulty code running in the secure | | | world, including S-EL0 and S-EL1 levels | +-------------------+-------------------------------------------------------+ - | ``AppDebug`` | | Physical attacker using debug signals to access | + | AppDebug | | Physical attacker using debug signals to access | | | TF-A resources | +-------------------+-------------------------------------------------------+ - | ``PhysicalAccess``| | Physical attacker having access to external device | + | PhysicalAccess | | Physical attacker having access to external device | | | communication bus and to external flash | | | communication bus using common hardware | +-------------------+-------------------------------------------------------+ @@ -145,7 +157,8 @@ in scope of this threat model. considered out-of-scope. Threat Types -======================== +============ + In this threat model we categorize threats using the `STRIDE threat analysis technique`_. In this technique a threat is categorized as one or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``, @@ -153,7 +166,8 @@ or more of these types: ``Spoofing``, `` ``Elevation of privilege``. Threat Risk Ratings -======================== +=================== + For each threat identified, a risk rating that ranges from *informational* to *critical* is given based on the likelihood of the threat occuring if a mitigation is not in place, and the impact of the @@ -165,7 +179,7 @@ rating in terms of score, impact and lik +-----------------------+-------------------------+---------------------------+ | **Rating (Score)** | **Impact** | **Likelihood** | +=======================+=========================+===========================+ - | ``Critical (5)`` | | Extreme impact to | | Threat is almost | + | Critical (5) | | Extreme impact to | | Threat is almost | | | entire organization | certain to be exploited.| | | if exploited. | | | | | | Knowledge of the threat | @@ -173,17 +187,17 @@ rating in terms of score, impact and lik | | | are in the public | | | | domain. | +-----------------------+-------------------------+---------------------------+ - | ``High (4)`` | | Major impact to entire| | Threat is relatively | + | High (4) | | Major impact to entire| | Threat is relatively | | | organization or single| easy to detect and | | | line of business if | exploit by an attacker | | | exploited | with little skill. | +-----------------------+-------------------------+---------------------------+ - | ``Medium (3)`` | | Noticeable impact to | | A knowledgeable insider | + | Medium (3) | | Noticeable impact to | | A knowledgeable insider | | | line of business if | or expert attacker could| | | exploited. | exploit the threat | | | | without much difficulty.| +-----------------------+-------------------------+---------------------------+ - | ``Low (2)`` | | Minor damage if | | Exploiting the threat | + | Low (2) | | Minor damage if | | Exploiting the threat | | | exploited or could | would require | | | be used in conjunction| considerable expertise | | | with other | and resources | @@ -191,7 +205,7 @@ rating in terms of score, impact and lik | | perform a more serious| | | | attack | | +-----------------------+-------------------------+---------------------------+ - | ``Informational (1)`` | | Poor programming | | Threat is not likely | + | Informational (1) | | Poor programming | | Threat is not likely | | | practice or poor | to be exploited on its | | | design decision that | own, but may be used to | | | may not represent an | gain information for | @@ -235,14 +249,27 @@ In this threat model we consider three t ``Internet of Things(IoT)``, ``Mobile`` and ``Server``. Threat Assessment -============================ +================= + The following threats were identified by applying STRIDE analysis on each diagram element of the data flow diagram. +For each threat, we strive to indicate whether the mitigations are currently +implemented or not. However, the answer to this question is not always straight +forward. Some mitigations are partially implemented in the generic code but also +rely on the platform code to implement some bits of it. This threat model aims +to be platform-independent and it is important to keep in mind that such threats +only get mitigated if the platform code properly fulfills its responsibilities. + +Also, some mitigations require enabling specific features, which must be +explicitly turned on via a build flag. + +These are highlighted in the ``Mitigations implemented?`` box. + +------------------------+----------------------------------------------------+ | ID | 01 | +========================+====================================================+ -| ``Threat`` | | **An attacker can mangle firmware images to | +| Threat | | **An attacker can mangle firmware images to | | | execute arbitrary code** | | | | | | | Some TF-A images are loaded from external | @@ -252,79 +279,89 @@ each diagram element of the data flow di | | updating mechanism to modify the non-volatile | | | images to execute arbitrary code. | +------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF4, DF5 | +| Diagram Elements | DF1, DF4, DF5 | +------------------------+----------------------------------------------------+ -| ``Affected TF-A | BL2, BL31 | -| Components`` | | +| Affected TF-A | BL2, BL31 | +| Components | | +------------------------+----------------------------------------------------+ -| ``Assets`` | Code Execution | +| Assets | Code Execution | +------------------------+----------------------------------------------------+ -| ``Threat Agent`` | PhysicalAccess, NSCode, SecCode | +| Threat Agent | PhysicalAccess, NSCode, SecCode | +------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Elevation of Privilege | +| Threat Type | Tampering, Elevation of Privilege | +------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Critical (5) | Critical (5) | Critical (5) | +| Impact | Critical (5) | Critical (5) | Critical (5) | +------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) | +| Likelihood | Critical (5) | Critical (5) | Critical (5) | +------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) | +| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | +------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | | TF-A implements the `Trusted Board Boot (TBB)`_ | +| Mitigations | | 1) Implement the `Trusted Board Boot (TBB)`_ | | | feature which prevents malicious firmware from | | | running on the platform by authenticating all | -| | firmware images. In addition to this, the TF-A | -| | boot firmware performs extra checks on | -| | unauthenticated data, such as FIP metadata, prior| -| | to use. | +| | firmware images. | +| | | +| | | 2) Perform extra checks on unauthenticated data, | +| | such as FIP metadata, prior to use. | ++------------------------+----------------------------------------------------+ +| Mitigations | | 1) Yes, provided that the ``TRUSTED_BOARD_BOOT`` | +| implemented? | build option is set to 1. | +| | | +| | | 2) Yes. | +------------------------+----------------------------------------------------+ +------------------------+----------------------------------------------------+ | ID | 02 | +========================+====================================================+ -| ``Threat`` | | **An attacker may attempt to boot outdated, | +| Threat | | **An attacker may attempt to boot outdated, | | | potentially vulnerable firmware image** | | | | | | | When updating firmware, an attacker may attempt | | | to rollback to an older version that has unfixed | | | vulnerabilities. | +------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF4, DF5 | +| Diagram Elements | DF1, DF4, DF5 | +------------------------+----------------------------------------------------+ -| ``Affected TF-A | BL2, BL31 | -| Components`` | | +| Affected TF-A | BL2, BL31 | +| Components | | +------------------------+----------------------------------------------------+ -| ``Assets`` | Code Execution | +| Assets | Code Execution | +------------------------+----------------------------------------------------+ -| ``Threat Agent`` | PhysicalAccess, NSCode, SecCode | +| Threat Agent | PhysicalAccess, NSCode, SecCode | +------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | +| Threat Type | Tampering | +------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Critical (5) | Critical (5) | Critical (5) | +| Impact | Critical (5) | Critical (5) | Critical (5) | +------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) | +| Likelihood | Critical (5) | Critical (5) | Critical (5) | +------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) | +| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | +------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | | TF-A supports anti-rollback protection using | -| | non-volatile counters (NV counters) as required | -| | by `TBBR-Client specification`_. After a firmware| -| | image is validated, the image revision number | -| | taken from a certificate extension field is | -| | compared with the corresponding NV counter stored| -| | in hardware to make sure the new counter value is| -| | larger or equal to the current counter value. | -| | Platforms must implement this protection using | -| | platform specific hardware NV counters. | +| Mitigations | Implement anti-rollback protection using | +| | non-volatile counters (NV counters) as required | +| | by `TBBR-Client specification`_. | ++------------------------+----------------------------------------------------+ +| Mitigations | | Yes / Platform specific. | +| implemented? | | +| | | After a firmware image is validated, the image | +| | revision number taken from a certificate | +| | extension field is compared with the | +| | corresponding NV counter stored in hardware to | +| | make sure the new counter value is larger than | +| | the current counter value. | +| | | +| | | **Platforms must implement this protection using | +| | platform specific hardware NV counters.** | +------------------------+----------------------------------------------------+ +------------------------+-------------------------------------------------------+ | ID | 03 | +========================+=======================================================+ -| ``Threat`` | | **An attacker can use Time-of-Check-Time-of-Use | +| Threat | | **An attacker can use Time-of-Check-Time-of-Use | | | (TOCTOU) attack to bypass image authentication | | | during the boot process** | | | | @@ -336,33 +373,39 @@ each diagram element of the data flow di | | after the integrity and authentication check has | | | been performed. | +------------------------+-------------------------------------------------------+ -| ``Diagram Elements`` | DF1 | +| Diagram Elements | DF1 | +------------------------+-------------------------------------------------------+ -| ``Affected TF-A | BL1, BL2 | -| Components`` | | +| Affected TF-A | BL1, BL2 | +| Components | | +------------------------+-------------------------------------------------------+ -| ``Assets`` | Code Execution, Sensitive Data | +| Assets | Code Execution, Sensitive Data | +------------------------+-------------------------------------------------------+ -| ``Threat Agent`` | PhysicalAccess | +| Threat Agent | PhysicalAccess | +------------------------+-------------------------------------------------------+ -| ``Threat Type`` | Elevation of Privilege | +| Threat Type | Elevation of Privilege | +------------------------+---------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+---------------------+-----------------+---------------+ -| ``Impact`` | N/A | Critical (5) | Critical (5) | +| Impact | N/A | Critical (5) | Critical (5) | +------------------------+---------------------+-----------------+---------------+ -| ``Likelihood`` | N/A | Medium (3) | Medium (3) | +| Likelihood | N/A | Medium (3) | Medium (3) | +------------------------+---------------------+-----------------+---------------+ -| ``Total Risk Rating`` | N/A | High (15) | High (15) | +| Total Risk Rating | N/A | High (15) | High (15) | +------------------------+---------------------+-----------------+---------------+ -| ``Mitigations`` | | TF-A boot firmware copies image to on-chip | -| | memory before authenticating an image. | +| Mitigations | Copy image to on-chip memory before authenticating | +| | it. | ++------------------------+-------------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | The list of images to load and their location is | +| | platform specific. Platforms are responsible for | +| | arranging images to be loaded in on-chip memory. | +------------------------+-------------------------------------------------------+ +------------------------+-------------------------------------------------------+ | ID | 04 | +========================+=======================================================+ -| ``Threat`` | | **An attacker with physical access can execute | +| Threat | | **An attacker with physical access can execute | | | arbitrary image by bypassing the signature | | | verification stage using glitching techniques** | | | | @@ -381,31 +424,38 @@ each diagram element of the data flow di | | points where the image is validated against the | | | signature. | +------------------------+-------------------------------------------------------+ -| ``Diagram Elements`` | DF1 | +| Diagram Elements | DF1 | +------------------------+-------------------------------------------------------+ -| ``Affected TF-A | BL1, BL2 | -| Components`` | | +| Affected TF-A | BL1, BL2 | +| Components | | +------------------------+-------------------------------------------------------+ -| ``Assets`` | Code Execution | +| Assets | Code Execution | +------------------------+-------------------------------------------------------+ -| ``Threat Agent`` | PhysicalAccess | +| Threat Agent | PhysicalAccess | +------------------------+-------------------------------------------------------+ -| ``Threat Type`` | Tampering, Elevation of Privilege | +| Threat Type | Tampering, Elevation of Privilege | +------------------------+---------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+---------------------+-----------------+---------------+ -| ``Impact`` | N/A | Critical (5) | Critical (5) | +| Impact | N/A | Critical (5) | Critical (5) | +------------------------+---------------------+-----------------+---------------+ -| ``Likelihood`` | N/A | Medium (3) | Medium (3) | +| Likelihood | N/A | Medium (3) | Medium (3) | +------------------------+---------------------+-----------------+---------------+ -| ``Total Risk Rating`` | N/A | High (15) | High (15) | +| Total Risk Rating | N/A | High (15) | High (15) | +------------------------+---------------------+-----------------+---------------+ -| ``Mitigations`` | | The most effective mitigation is adding glitching | +| Mitigations | Mechanisms to detect clock glitch and power | +| | variations. | ++------------------------+-------------------------------------------------------+ +| Mitigations | | No. | +| implemented? | | +| | | The most effective mitigation is adding glitching | | | detection and mitigation circuit at the hardware | -| | level. However, software techniques, | -| | such as adding redundant checks when performing | -| | conditional branches that are security sensitive, | -| | can be used to harden TF-A against such attacks. | +| | level. | +| | | +| | | However, software techniques, such as adding | +| | redundant checks when performing conditional | +| | branches that are security sensitive, can be used | +| | to harden TF-A against such attacks. | | | **At the moment TF-A doesn't implement such | | | mitigations.** | +------------------------+-------------------------------------------------------+ @@ -413,49 +463,76 @@ each diagram element of the data flow di +------------------------+---------------------------------------------------+ | ID | 05 | +========================+===================================================+ -| ``Threat`` | | **Information leak via UART logs such as | -| | crashes** | +| Threat | | **Information leak via UART logs** | | | | | | | During the development stages of software it is | -| | common to include crash reports with detailed | -| | information of the CPU state including current | -| | values of the registers, privilege level and | -| | stack dumps. This information is useful when | -| | debugging problems before releasing the | -| | production version, but it could be used by an | -| | attacker to develop a working exploit if left | -| | in the production version. | +| | common to print all sorts of information on the | +| | console, including sensitive or confidential | +| | information such as crash reports with detailed | +| | information of the CPU state, current registers | +| | values, privilege level or stack dumps. | +| | | +| | | This information is useful when debugging | +| | problems before releasing the production | +| | version but it could be used by an attacker | +| | to develop a working exploit if left enabled in | +| | the production version. | +| | | +| | | This happens when directly logging sensitive | +| | information and more subtly when logging | +| | side-channel information that can be used by an | +| | attacker to learn about sensitive information. | +------------------------+---------------------------------------------------+ -| ``Diagram Elements`` | DF2 | +| Diagram Elements | DF2 | +------------------------+---------------------------------------------------+ -| ``Affected TF-A | BL1, BL2, BL31 | -| Components`` | | +| Affected TF-A | BL1, BL2, BL31 | +| Components | | +------------------------+---------------------------------------------------+ -| ``Assets`` | Sensitive Data | +| Assets | Sensitive Data | +------------------------+---------------------------------------------------+ -| ``Threat Agent`` | AppDebug | +| Threat Agent | AppDebug | +------------------------+---------------------------------------------------+ -| ``Threat Type`` | Information Disclosure | +| Threat Type | Information Disclosure | +------------------------+------------------+----------------+---------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+------------------+----------------+---------------+ -| ``Impact`` | N/A | Low (2) | Low (2) | +| Impact | N/A | Low (2) | Low (2) | +------------------------+------------------+----------------+---------------+ -| ``Likelihood`` | N/A | High (4) | High (4) | +| Likelihood | N/A | High (4) | High (4) | +------------------------+------------------+----------------+---------------+ -| ``Total Risk Rating`` | N/A | Medium (8) | Medium (8) | +| Total Risk Rating | N/A | Medium (8) | Medium (8) | +------------------------+------------------+----------------+---------------+ -| ``Mitigations`` | | In TF-A, crash reporting is only enabled for | -| | debug builds by default. Alternatively, the log | -| | level can be tuned at build time (from verbose | -| | to no output at all), independently of the | -| | build type. | +| Mitigations | | Remove sensitive information logging in | +| | production releases. | +| | | +| | | Do not conditionally log information depending | +| | on potentially sensitive data. | +| | | +| | | Do not log high precision timing information. | ++------------------------+---------------------------------------------------+ +| Mitigations | | Yes / Platform Specific. | +| implemented? | Requires the right build options to be used. | +| | | +| | | Crash reporting is only enabled for debug | +| | builds by default, see ``CRASH_REPORTING`` | +| | build option. | +| | | +| | | The log level can be tuned at build time, from | +| | very verbose to no output at all. See | +| | ``LOG_LEVEL`` build option. By default, release | +| | builds are a lot less verbose than debug ones | +| | but still produce some output. | +| | | +| | | Messages produced by the platform code should | +| | use the appropriate level of verbosity so as | +| | not to leak sensitive information in production | +| | builds. | +------------------------+---------------------------------------------------+ +------------------------+----------------------------------------------------+ | ID | 06 | +========================+====================================================+ -| ``Threat`` | | **An attacker can read sensitive data and | +| Threat | | **An attacker can read sensitive data and | | | execute arbitrary code through the external | | | debug and trace interface** | | | | @@ -468,37 +545,40 @@ each diagram element of the data flow di | | attacker to read sensitive data and execute | | | arbitrary code. | +------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF3 | +| Diagram Elements | DF3 | +------------------------+----------------------------------------------------+ -| ``Affected TF-A | BL1, BL2, BL31 | -| Components`` | | +| Affected TF-A | BL1, BL2, BL31 | +| Components | | +------------------------+----------------------------------------------------+ -| ``Assets`` | Code Execution, Sensitive Data | +| Assets | Code Execution, Sensitive Data | +------------------------+----------------------------------------------------+ -| ``Threat Agent`` | AppDebug | +| Threat Agent | AppDebug | +------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Information Disclosure, | +| Threat Type | Tampering, Information Disclosure, | | | Elevation of privilege | +------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+------------------+---------------+-----------------+ -| ``Impact`` | N/A | High (4) | High (4) | +| Impact | N/A | High (4) | High (4) | +------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | N/A | Critical (5) | Critical (5) | +| Likelihood | N/A | Critical (5) | Critical (5) | +------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | N/A | Critical (20) | Critical (20) | +| Total Risk Rating | N/A | Critical (20) | Critical (20) | +------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | | Configuration of debug and trace capabilities is | -| | platform specific. Therefore, platforms must | -| | disable the debug and trace capability for | -| | production releases or enable proper debug | -| | authentication as recommended by [`DEN0034`_]. | +| Mitigations | Disable the debug and trace capability for | +| | production releases or enable proper debug | +| | authentication as recommended by [`DEN0034`_]. | ++------------------------+----------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | Configuration of debug and trace capabilities is | +| | entirely platform specific. | +------------------------+----------------------------------------------------+ +------------------------+------------------------------------------------------+ | ID | 07 | +========================+======================================================+ -| ``Threat`` | | **An attacker can perform a denial-of-service | +| Threat | | **An attacker can perform a denial-of-service | | | attack by using a broken SMC call that causes the | | | system to reboot or enter into unknown state.** | | | | @@ -508,48 +588,48 @@ each diagram element of the data flow di | | by calling unimplemented SMC call or by passing | | | invalid arguments. | +------------------------+------------------------------------------------------+ -| ``Diagram Elements`` | DF4, DF5 | +| Diagram Elements | DF4, DF5 | +------------------------+------------------------------------------------------+ -| ``Affected TF-A | BL31 | -| Components`` | | +| Affected TF-A | BL31 | +| Components | | +------------------------+------------------------------------------------------+ -| ``Assets`` | Availability | +| Assets | Availability | +------------------------+------------------------------------------------------+ -| ``Threat Agent`` | NSCode, SecCode | +| Threat Agent | NSCode, SecCode | +------------------------+------------------------------------------------------+ -| ``Threat Type`` | Denial of Service | +| Threat Type | Denial of Service | +------------------------+-------------------+----------------+-----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+-------------------+----------------+-----------------+ -| ``Impact`` | Medium (3) | Medium (3) | Medium (3) | +| Impact | Medium (3) | Medium (3) | Medium (3) | +------------------------+-------------------+----------------+-----------------+ -| ``Likelihood`` | High (4) | High (4) | High (4) | +| Likelihood | High (4) | High (4) | High (4) | +------------------------+-------------------+----------------+-----------------+ -| ``Total Risk Rating`` | High (12) | High (12) | High (12) | +| Total Risk Rating | High (12) | High (12) | High (12) | +------------------------+-------------------+----------------+-----------------+ -| ``Mitigations`` | | The generic TF-A code validates SMC function ids | -| | and arguments before using them. | -| | Platforms that implement SiP services must also | +| Mitigations | Validate SMC function ids and arguments before using | +| | them. | ++------------------------+------------------------------------------------------+ +| Mitigations | | Yes / Platform specific. | +| implemented? | | +| | | For standard services, all input is validated. | +| | | +| | | Platforms that implement SiP services must also | | | validate SMC call arguments. | +------------------------+------------------------------------------------------+ +------------------------+------------------------------------------------------+ | ID | 08 | +========================+======================================================+ -| ``Threat`` | | **Memory corruption due to memory overflows and | +| Threat | | **Memory corruption due to memory overflows and | | | lack of boundary checking when accessing resources | | | could allow an attacker to execute arbitrary code, | | | modify some state variable to change the normal | | | flow of the program, or leak sensitive | | | information** | | | | -| | | Like in other software, the Trusted Firmware has | -| | multiple points where memory corruption security | -| | errors can arise. Memory corruption is a dangerous | -| | security issue since it could allow an attacker | -| | to execute arbitrary code, modify some state | -| | variable to change the normal flow of the program, | -| | or leak sensitive information. | +| | | Like in other software, TF-A has multiple points | +| | where memory corruption security errors can arise. | | | | | | | Some of the errors include integer overflow, | | | buffer overflow, incorrect array boundary checks, | @@ -558,37 +638,32 @@ each diagram element of the data flow di | | validations might also result in these kinds of | | | errors in release builds. | +------------------------+------------------------------------------------------+ -| ``Diagram Elements`` | DF4, DF5 | +| Diagram Elements | DF4, DF5 | +------------------------+------------------------------------------------------+ -| ``Affected TF-A | BL1, BL2, BL31 | -| Components`` | | +| Affected TF-A | BL1, BL2, BL31 | +| Components | | +------------------------+------------------------------------------------------+ -| ``Assets`` | Code Execution, Sensitive Data | +| Assets | Code Execution, Sensitive Data | +------------------------+------------------------------------------------------+ -| ``Threat Agent`` | NSCode, SecCode | +| Threat Agent | NSCode, SecCode | +------------------------+------------------------------------------------------+ -| ``Threat Type`` | Tampering, Information Disclosure, | +| Threat Type | Tampering, Information Disclosure, | | | Elevation of Privilege | +------------------------+-------------------+-----------------+----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+-------------------+-----------------+----------------+ -| ``Impact`` | Critical (5) | Critical (5) | Critical (5) | +| Impact | Critical (5) | Critical (5) | Critical (5) | +------------------------+-------------------+-----------------+----------------+ -| ``Likelihood`` | Medium (3 | Medium (3) | Medium (3) | +| Likelihood | Medium (3 | Medium (3) | Medium (3) | +------------------------+-------------------+-----------------+----------------+ -| ``Total Risk Rating`` | High (15) | High (15) | High (15) | +| Total Risk Rating | High (15) | High (15) | High (15) | +------------------------+-------------------+-----------------+----------------+ -| ``Mitigations`` | | TF-A uses a combination of manual code reviews and | -| | automated program analysis and testing to detect | -| | and fix memory corruption bugs. All TF-A code | -| | including platform code go through manual code | -| | reviews. Additionally, static code analysis is | -| | performed using Coverity Scan on all TF-A code. | -| | The code is also tested with | -| | `Trusted Firmware-A Tests`_ on Juno and FVP | -| | platforms. | +| Mitigations | | 1) Use proper input validation. | | | | -| | | Data received from normal world, such as addresses | +| | | 2) Code reviews, testing. | ++------------------------+------------------------------------------------------+ +| Mitigations | | 1) Yes. | +| implemented? | Data received from normal world, such as addresses | | | and sizes identifying memory regions, are | | | sanitized before being used. These security checks | | | make sure that the normal world software does not | @@ -602,48 +677,62 @@ each diagram element of the data flow di | | option to use *asserts* in release builds, however | | | we recommend using proper runtime checks instead | | | of relying on asserts in release builds. | +| | | +| | | 2) Yes. | +| | TF-A uses a combination of manual code reviews | +| | and automated program analysis and testing to | +| | detect and fix memory corruption bugs. All TF-A | +| | code including platform code go through manual | +| | code reviews. Additionally, static code analysis | +| | is performed using Coverity Scan on all TF-A code. | +| | The code is also tested with | +| | `Trusted Firmware-A Tests`_ on Juno and FVP | +| | platforms. | +------------------------+------------------------------------------------------+ +------------------------+------------------------------------------------------+ | ID | 09 | +========================+======================================================+ -| ``Threat`` | | **Improperly handled SMC calls can leak register | +| Threat | | **Improperly handled SMC calls can leak register | | | contents** | | | | -| | | When switching between secure and non-secure | -| | states, register contents of Secure world or | -| | register contents of other normal world clients | -| | can be leaked. | +| | | When switching between worlds, TF-A register state | +| | can leak to software in different security | +| | contexts. | +------------------------+------------------------------------------------------+ -| ``Diagram Elements`` | DF5 | +| Diagram Elements | DF4, DF5 | +------------------------+------------------------------------------------------+ -| ``Affected TF-A | BL31 | -| Components`` | | +| Affected TF-A | BL31 | +| Components | | +------------------------+------------------------------------------------------+ -| ``Assets`` | Sensitive Data | +| Assets | Sensitive Data | +------------------------+------------------------------------------------------+ -| ``Threat Agent`` | NSCode | +| Threat Agent | NSCode, SecCode | +------------------------+------------------------------------------------------+ -| ``Threat Type`` | Information Disclosure | +| Threat Type | Information Disclosure | +------------------------+-------------------+----------------+-----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+-------------------+----------------+-----------------+ -| ``Impact`` | Medium (3) | Medium (3) | Medium (3) | +| Impact | Medium (3) | Medium (3) | Medium (3) | +------------------------+-------------------+----------------+-----------------+ -| ``Likelihood`` | High (4) | High (4) | High (4) | +| Likelihood | High (4) | High (4) | High (4) | +------------------------+-------------------+----------------+-----------------+ -| ``Total Risk Rating`` | High (12) | High (12) | High (12) | +| Total Risk Rating | High (12) | High (12) | High (12) | +------------------------+-------------------+----------------+-----------------+ -| ``Mitigations`` | | TF-A saves and restores registers | -| | by default when switching contexts. Build options | -| | are also provided to save/restore additional | -| | registers such as floating-point registers. | +| Mitigations | Save and restore registers when switching contexts. | ++------------------------+------------------------------------------------------+ +| Mitigations | | Yes. | +| implemented? | | +| | | This is the default behaviour in TF-A. | +| | Build options are also provided to save/restore | +| | additional registers such as floating-point | +| | registers. These should be enabled if required. | +------------------------+------------------------------------------------------+ +------------------------+-----------------------------------------------------+ | ID | 10 | +========================+=====================================================+ -| ``Threat`` | | **SMC calls can leak sensitive information from | +| Threat | | **SMC calls can leak sensitive information from | | | TF-A memory via microarchitectural side channels**| | | | | | | Microarchitectural side-channel attacks such as | @@ -652,36 +741,42 @@ each diagram element of the data flow di | | use this kind of attack to leak sensitive | | | data from TF-A memory. | +------------------------+-----------------------------------------------------+ -| ``Diagram Elements`` | DF4, DF5 | +| Diagram Elements | DF4, DF5 | +------------------------+-----------------------------------------------------+ -| ``Affected TF-A | BL31 | -| Components`` | | +| Affected TF-A | BL31 | +| Components | | +------------------------+-----------------------------------------------------+ -| ``Assets`` | Sensitive Data | +| Assets | Sensitive Data | +------------------------+-----------------------------------------------------+ -| ``Threat Agent`` | SecCode, NSCode | +| Threat Agent | SecCode, NSCode | +------------------------+-----------------------------------------------------+ -| ``Threat Type`` | Information Disclosure | +| Threat Type | Information Disclosure | +------------------------+-------------------+----------------+----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+-------------------+----------------+----------------+ -| ``Impact`` | Medium (3) | Medium (3) | Medium (3) | +| Impact | Medium (3) | Medium (3) | Medium (3) | +------------------------+-------------------+----------------+----------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | Medium (3) | +| Likelihood | Medium (3) | Medium (3) | Medium (3) | +------------------------+-------------------+----------------+----------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | Medium (9) | +| Total Risk Rating | Medium (9) | Medium (9) | Medium (9) | +------------------------+-------------------+----------------+----------------+ -| ``Mitigations`` | | TF-A implements software mitigations for Spectre | +| Mitigations | Enable appropriate side-channel protections. | ++------------------------+-----------------------------------------------------+ +| Mitigations | | Yes / Platform specific. | +| implemented? | | +| | | TF-A implements software mitigations for Spectre | | | type attacks as recommended by `Cache Speculation | -| | Side-channels`_ for the generic code. SiPs should | -| | implement similar mitigations for code that is | -| | deemed to be vulnerable to such attacks. | +| | Side-channels`_ for the generic code. | +| | | +| | | SiPs should implement similar mitigations for | +| | code that is deemed to be vulnerable to such | +| | attacks. | +------------------------+-----------------------------------------------------+ +------------------------+----------------------------------------------------+ | ID | 11 | +========================+====================================================+ -| ``Threat`` | | **Misconfiguration of the Memory Management Unit | +| Threat | | **Misconfiguration of the Memory Management Unit | | | (MMU) may allow a normal world software to | | | access sensitive data or execute arbitrary | | | code** | @@ -692,44 +787,50 @@ each diagram element of the data flow di | | execute code if the proper security mechanisms | | | are not in place. | +------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF5, DF6 | +| Diagram Elements | DF5, DF6 | +------------------------+----------------------------------------------------+ -| ``Affected TF-A | BL1, BL2, BL31 | -| Components`` | | +| Affected TF-A | BL1, BL2, BL31 | +| Components | | +------------------------+----------------------------------------------------+ -| ``Assets`` | Sensitive Data, Code execution | +| Assets | Sensitive Data, Code execution | +------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NSCode | +| Threat Agent | NSCode | +------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information Disclosure, Elevation of Privilege | +| Threat Type | Information Disclosure, Elevation of Privilege | +------------------------+-----------------+-----------------+----------------+ -| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` | +| Application | Server | IoT | Mobile | +------------------------+-----------------+-----------------+----------------+ -| ``Impact`` | Critical (5) | Critical (5) | Critical (5) | +| Impact | Critical (5) | Critical (5) | Critical (5) | +------------------------+-----------------+-----------------+----------------+ -| ``Likelihood`` | High (4) | High (4) | High (4) | +| Likelihood | High (4) | High (4) | High (4) | +------------------------+-----------------+-----------------+----------------+ -| ``Total Risk Rating`` | Critical (20) | Critical (20) | Critical (20) | +| Total Risk Rating | Critical (20) | Critical (20) | Critical (20) | +------------------------+-----------------+-----------------+----------------+ -| ``Mitigations`` | | In TF-A, configuration of the MMU is done | -| | through a translation tables library. The | -| | library provides APIs to define memory regions | -| | and assign attributes including memory types and | -| | access permissions. Memory configurations are | -| | platform specific, therefore platforms need make | -| | sure the correct attributes are assigned to | -| | memory regions. When assigning access | -| | permissions, principle of least privilege ought | -| | to be enforced, i.e. we should not grant more | -| | privileges than strictly needed, e.g. code | -| | should be read-only executable, RO data should | -| | be read-only XN, and so on. | +| Mitigations | When configuring access permissions, the | +| | principle of least privilege ought to be | +| | enforced. This means we should not grant more | +| | privileges than strictly needed, e.g. code | +| | should be read-only executable, read-only data | +| | should be read-only execute-never, and so on. | ++------------------------+----------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | MMU configuration is platform specific, | +| | therefore platforms need to make sure that the | +| | correct attributes are assigned to memory | +| | regions. | +| | | +| | | TF-A provides a library which abstracts the | +| | low-level details of MMU configuration. It | +| | provides well-defined and tested APIs. | +| | Platforms are encouraged to use it to limit the | +| | risk of misconfiguration. | +------------------------+----------------------------------------------------+ +------------------------+-----------------------------------------------------+ | ID | 12 | +========================+=====================================================+ -| ``Threat`` | | **Incorrect configuration of Performance Monitor | +| Threat | | **Incorrect configuration of Performance Monitor | | | Unit (PMU) counters can allow an attacker to | | | mount side-channel attacks using information | | | exposed by the counters** | @@ -738,43 +839,50 @@ each diagram element of the data flow di | | to count events at any exception level and in | | | both Secure and Non-secure states. This allows | | | a Non-secure software (or a lower-level Secure | -| | software) to potentially carry out | +| | software) to potentially carry out | | | side-channel timing attacks against TF-A. | +------------------------+-----------------------------------------------------+ -| ``Diagram Elements`` | DF5, DF6 | +| Diagram Elements | DF5, DF6 | +------------------------+-----------------------------------------------------+ -| ``Affected TF-A | BL31 | -| Components`` | | +| Affected TF-A | BL31 | +| Components | | +------------------------+-----------------------------------------------------+ -| ``Assets`` | Sensitive Data | +| Assets | Sensitive Data | +------------------------+-----------------------------------------------------+ -| ``Threat Agent`` | NSCode | +| Threat Agent | NSCode | +------------------------+-----------------------------------------------------+ -| ``Threat Type`` | Information Disclosure | +| Threat Type | Information Disclosure | +------------------------+-------------------+----------------+----------------+ -| ``Impact`` | Medium (3) | Medium (3) | Medium (3) | +| Impact | Medium (3) | Medium (3) | Medium (3) | +------------------------+-------------------+----------------+----------------+ -| ``Likelihood`` | Low (2) | Low (2) | Low (2) | +| Likelihood | Low (2) | Low (2) | Low (2) | +------------------------+-------------------+----------------+----------------+ -| ``Total Risk Rating`` | Medium (6) | Medium (6) | Medium (6) | +| Total Risk Rating | Medium (6) | Medium (6) | Medium (6) | +------------------------+-------------------+----------------+----------------+ -| ``Mitigations`` | | TF-A follows mitigation strategies as described | -| | in `Secure Development Guidelines`_. General | -| | events and cycle counting in the Secure world is | -| | prohibited by default when applicable. However, | -| | on some implementations (e.g. PMUv3) Secure world | -| | event counting depends on external debug interface| -| | signals, i.e. Secure world event counting is | -| | enabled if external debug is enabled. | -| | Configuration of debug signals is platform | +| Mitigations | Follow mitigation strategies as described in | +| | `Secure Development Guidelines`_. | ++------------------------+-----------------------------------------------------+ +| Mitigations | | Yes / platform specific. | +| implemented? | | +| | | General events and cycle counting in the Secure | +| | world is prohibited by default when applicable. | +| | | +| | | However, on some implementations (e.g. PMUv3) | +| | Secure world event counting depends on external | +| | debug interface signals, i.e. Secure world event | +| | counting is enabled if external debug is enabled. | +| | | +| | | Configuration of debug signals is platform | | | specific, therefore platforms need to make sure | | | that external debug is disabled in production or | -| | proper debug authentication is in place. | +| | proper debug authentication is in place. This | +| | should be the case if threat #06 is properly | +| | mitigated. | +------------------------+-----------------------------------------------------+ -------------- -*Copyright (c) 2021, Arm Limited. All rights reserved.* +*Copyright (c) 2021-2022, Arm Limited. All rights reserved.* .. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model diff -pruN 2.6+dfsg-1/docs/threat_model/threat_model_spm.rst 2.7.0+dfsg-2/docs/threat_model/threat_model_spm.rst --- 2.6+dfsg-1/docs/threat_model/threat_model_spm.rst 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/docs/threat_model/threat_model_spm.rst 2022-06-01 15:02:46.000000000 +0000 @@ -1,4 +1,4 @@ -SPMC threat model +SPMC Threat Model ***************** ************************ @@ -36,7 +36,8 @@ The scope for this threat model is: running in the secure world of TrustZone (at S-EL2 exception level). The threat model is not related to the normal world Hypervisor or VMs. The S-EL1 SPMC solution is not covered. -- The implementation complies with the FF-A v1.0 specification. +- The implementation complies with the FF-A v1.0 specification, and a few + features of FF-A v1.1 specification. - Secure partitions are statically provisioned at boot time. - Focus on the run-time part of the life-cycle (no specific emphasis on boot time, factory firmware provisioning, firmware udpate etc.) @@ -477,7 +478,7 @@ element of the data flow diagram. +------------------------+------------------+---------------+-----------------+ | ``Total Risk Rating`` | Medium (6) | Medium (6) | | +------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | For the specific case of direct requests targetting| +| ``Mitigations`` | For the specific case of direct requests targeting | | | the SPMC, the latter is hardened to prevent | | | its internal state or the state of an SP to be | | | revealed through a direct message response. | @@ -572,7 +573,7 @@ element of the data flow diagram. | ID | 11 | +========================+====================================================+ | ``Threat`` | **A malicious endpoint may attempt flooding the | -| | SPMC with requests targetting a service within an | +| | SPMC with requests targeting a service within an | | | endpoint such that it denies another endpoint to | | | access this service.** | | | Similarly, the malicious endpoint may target a | @@ -607,7 +608,281 @@ element of the data flow diagram. | | in a limited timeframe. | +------------------------+----------------------------------------------------+ --------------- ++------------------------+----------------------------------------------------+ +| ID | 12 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint may attempt to allocate | +| | notifications bitmaps in the SPMC, through the | +| | FFA_NOTIFICATION_BITMAP_CREATE.** | +| | This might be an attempt to exhaust SPMC's memory, | +| | or to allocate a bitmap for a VM that was not | +| | intended to receive notifications from SPs. Thus | +| | creating the possibility for a channel that was not| +| | meant to exist. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Denial of service, Spoofing | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Medium(3) | Medium(3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium(3) | Medium(3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium(9) | Medium(9) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this threat by defining a | +| | a fixed size pool for bitmap allocation. | +| | It also limits the designated FF-A calls to be used| +| | from NWd endpoints. | +| | In the NWd the hypervisor is supposed to limit the | +| | access to the designated FF-A call. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 13 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint may attempt to destroy the | +| | notifications bitmaps in the SPMC, through the | +| | FFA_NOTIFICATION_BITMAP_DESTROY.** | +| | This might be an attempt to tamper with the SPMC | +| | state such that a partition isn't able to receive | +| | notifications. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Low(4) | Low(4) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this issue by limiting the | +| | designated FF-A call to be issued by the NWd. | +| | Also, the notifications bitmap can't be destroyed | +| | if there are pending notifications. | +| | In the NWd, the hypervisor must restrict the | +| | NS-endpoints that can issue the designated call. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 14 | ++========================+====================================================+ +| ``Threat`` | **A malicious endpoint might attempt to give | +| | permissions to an unintended sender to set | +| | notifications targeting another receiver using the | +| | FF-A call FFA_NOTIFICATION_BIND.** | +| | This might be an attempt to tamper with the SPMC | +| | state such that an unintended, and possibly | +| | malicious, communication channel is established. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Tampering, Spoofing | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium(3) | Medium(3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium(6) | Medium(6) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this by restricting | +| | designated FFA_NOTIFICATION_BIND call to be issued | +| | by the receiver only. The receiver is responsible | +| | for allocating the notifications IDs to one | +| | specific partition. | +| | Also, receivers that are not meant to receive | +| | notifications, must have notifications receipt | +| | disabled in the respective partition's manifest. | +| | As for calls coming from NWd, if the NWd VM has had| +| | its bitmap allocated at initialization, the TF-A | +| | SPMC can't guarantee this threat won't happen. | +| | The Hypervisor must mitigate in the NWd, similarly | +| | to SPMC for calls in SWd. Though, if the Hypervisor| +| | has been compromised, the SPMC won't be able to | +| | mitigate it for calls forwarded from NWd. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 15 | ++========================+====================================================+ +| ``Threat`` | **A malicious partition endpoint might attempt to | +| | set notifications that are not bound to it.** | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Spoofing | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Low(4) | Low(4) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this by checking the | +| | sender's ID provided in the input to the call | +| | FFA_NOTIFICATION_SET. The SPMC keeps track of which| +| | notifications are bound to which sender, for a | +| | given receiver. If the sender is an SP, the | +| | provided sender ID must match the ID of the | +| | currently running partition. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 16 | ++========================+====================================================+ +| ``Threat`` | **A malicious partition endpoint might attempt to | +| | get notifications that are not targeted to it.** | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Spoofing | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Informational(1) | Informational(1)| | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this by checking the | +| | receiver's ID provided in the input to the call | +| | FFA_NOTIFICATION_GET. The SPMC keeps track of which| +| | notifications are pending for each receiver. | +| | The provided receiver ID must match the ID of the | +| | currently running partition, if it is an SP. | +| | For calls forwarded from NWd, the SPMC will return | +| | the pending notifications if the receiver had its | +| | bitmap created, and has pending notifications. | +| | If Hypervisor or OS kernel are compromised, the | +| | SPMC won't be able to mitigate calls from rogue NWd| +| | endpoints. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 17 | ++========================+====================================================+ +| ``Threat`` | **A malicious partition endpoint might attempt to | +| | get the information about pending notifications, | +| | through the FFA_NOTIFICATION_INFO_GET call.** | +| | This call is meant to be used by the NWd FF-A | +| | driver. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | Information disclosure | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium(3) | Medium(3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium(6) | Medium(6) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC mitigates this by returning error to | +| | calls made by SPs to FFA_NOTIFICATION_INFO_GET. | +| | If Hypervisor or OS kernel are compromised, the | +| | SPMC won't be able mitigate calls from rogue NWd | +| | endpoints. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 18 | ++========================+====================================================+ +| ``Threat`` | **A malicious partition endpoint might attempt to | +| | flood another partition endpoint with notifications| +| | hindering its operation.** | +| | The intent of the malicious endpoint could be to | +| | interfere with both the receiver's and/or primary | +| | endpoint execution, as they can both be preempted | +| | by the NPI and SRI, respectively. | ++------------------------+----------------------------------------------------+ +| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | ++------------------------+----------------------------------------------------+ +| ``Affected TF-A | SPMC | +| Components`` | | ++------------------------+----------------------------------------------------+ +| ``Assets`` | SPMC state, SP state, CPU cycles | ++------------------------+----------------------------------------------------+ +| ``Threat Agent`` | NS-Endpoint, S-Endpoint | ++------------------------+----------------------------------------------------+ +| ``Threat Type`` | DoS | ++------------------------+------------------+-----------------+---------------+ +| ``Application`` | ``Server`` | ``Mobile`` | | ++------------------------+------------------+-----------------+---------------+ +| ``Impact`` | Low(2) | Low(2) | | ++------------------------+------------------+-----------------+---------------+ +| ``Likelihood`` | Medium(3) | Medium(3) | | ++------------------------+------------------+-----------------+---------------+ +| ``Total Risk Rating`` | Medium(6) | Medium(6) | | ++------------------------+------------------+-----------------+---------------+ +| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. | +| | However, the impact is limited due to the | +| | architecture: | +| | - Notifications are not queued, one that has been | +| | signaled needs to be retrieved by the receiver, | +| | until it can be sent again. | +| | - Both SRI and NPI can't be pended until handled | +| | which limits the amount of spurious interrupts. | +| | - A given receiver could only bind a maximum number| +| | of notifications to a given sender, within a given | +| | execution context. | ++------------------------+----------------------------------------------------+ + +--------------- *Copyright (c) 2021, Arm Limited. All rights reserved.* diff -pruN 2.6+dfsg-1/drivers/allwinner/axp/axp803.c 2.7.0+dfsg-2/drivers/allwinner/axp/axp803.c --- 2.6+dfsg-1/drivers/allwinner/axp/axp803.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/allwinner/axp/axp803.c 2022-06-01 15:02:46.000000000 +0000 @@ -9,7 +9,9 @@ const uint8_t axp_chip_id = AXP803_CHIP_ID; const char *const axp_compatible = "x-powers,axp803"; +#if SUNXI_SETUP_REGULATORS == 1 const struct axp_regulator axp_regulators[] = { + {"aldo1", 700, 3300, 100, NA, 0x28, 0x13, 5}, {"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0}, {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4}, {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5}, @@ -20,3 +22,4 @@ const struct axp_regulator axp_regulator {"fldo1", 700, 1450, 50, NA, 0x1c, 0x13, 2}, {} }; +#endif diff -pruN 2.6+dfsg-1/drivers/allwinner/axp/axp805.c 2.7.0+dfsg-2/drivers/allwinner/axp/axp805.c --- 2.6+dfsg-1/drivers/allwinner/axp/axp805.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/allwinner/axp/axp805.c 2022-06-01 15:02:46.000000000 +0000 @@ -9,6 +9,7 @@ const uint8_t axp_chip_id = AXP805_CHIP_ID; const char *const axp_compatible = "x-powers,axp805"; +#if SUNXI_SETUP_REGULATORS == 1 /* * The "dcdcd" split changes the step size by a factor of 5, not 2; * disallow values above the split to maintain accuracy. @@ -31,3 +32,4 @@ const struct axp_regulator axp_regulator {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6}, {} }; +#endif diff -pruN 2.6+dfsg-1/drivers/allwinner/axp/common.c 2.7.0+dfsg-2/drivers/allwinner/axp/common.c --- 2.6+dfsg-1/drivers/allwinner/axp/common.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/allwinner/axp/common.c 2022-06-01 15:02:46.000000000 +0000 @@ -48,6 +48,7 @@ void axp_power_off(void) axp_setbits(0x32, BIT(7)); } +#if SUNXI_SETUP_REGULATORS == 1 /* * Retrieve the voltage from a given regulator DTB node. * Both the regulator-{min,max}-microvolt properties must be present and @@ -208,3 +209,4 @@ void axp_setup_regulators(const void *fd axp_setbits(0x11, BIT(7)); } } +#endif /* SUNXI_SETUP_REGULATORS */ diff -pruN 2.6+dfsg-1/drivers/arm/css/scmi/scmi_private.h 2.7.0+dfsg-2/drivers/arm/css/scmi/scmi_private.h --- 2.6+dfsg-1/drivers/arm/css/scmi/scmi_private.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/css/scmi/scmi_private.h 2022-06-01 15:02:46.000000000 +0000 @@ -136,7 +136,7 @@ typedef struct mailbox_mem { uint64_t res_b; /* Reserved */ uint32_t flags; volatile uint32_t len; - uint32_t msg_header; + volatile uint32_t msg_header; uint32_t payload[]; } mailbox_mem_t; diff -pruN 2.6+dfsg-1/drivers/arm/gic/v3/gic600ae_fmu.c 2.7.0+dfsg-2/drivers/arm/gic/v3/gic600ae_fmu.c --- 2.6+dfsg-1/drivers/arm/gic/v3/gic600ae_fmu.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/gic/v3/gic600ae_fmu.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ */ #include +#include #include #include @@ -112,6 +113,135 @@ static char *wkrqst_sm_info[] = { "Wake-GICD AXI4-Stream interface error" }; +/* Helper function to find detailed information for a specific IERR */ +static char __unused *ras_ierr_to_str(unsigned int blkid, unsigned int ierr) +{ + char *str = NULL; + + /* Find the correct record */ + switch (blkid) { + case FMU_BLK_GICD: + assert(ierr < ARRAY_SIZE(gicd_sm_info)); + str = gicd_sm_info[ierr]; + break; + + case FMU_BLK_SPICOL: + assert(ierr < ARRAY_SIZE(spicol_sm_info)); + str = spicol_sm_info[ierr]; + break; + + case FMU_BLK_WAKERQ: + assert(ierr < ARRAY_SIZE(wkrqst_sm_info)); + str = wkrqst_sm_info[ierr]; + break; + + case FMU_BLK_ITS0...FMU_BLK_ITS7: + assert(ierr < ARRAY_SIZE(its_sm_info)); + str = its_sm_info[ierr]; + break; + + case FMU_BLK_PPI0...FMU_BLK_PPI31: + assert(ierr < ARRAY_SIZE(ppi_sm_info)); + str = ppi_sm_info[ierr]; + break; + + default: + assert(false); + break; + } + + return str; +} + +/* + * Probe for error in memory-mapped registers containing error records. + * Upon detecting an error, set probe data to the index of the record + * in error, and return 1; otherwise, return 0. + */ +int gic600_fmu_probe(uint64_t base, int *probe_data) +{ + uint64_t gsr; + + assert(base != 0UL); + + /* + * Read ERR_GSR to find the error record 'M' + */ + gsr = gic_fmu_read_errgsr(base); + if (gsr == U(0)) { + return 0; + } + + /* Return the index of the record in error */ + if (probe_data != NULL) { + *probe_data = (int)__builtin_ctzll(gsr); + } + + return 1; +} + +/* + * The handler function to read RAS records and find the safety + * mechanism with the error. + */ +int gic600_fmu_ras_handler(uint64_t base, int probe_data) +{ + uint64_t errstatus; + unsigned int blkid = (unsigned int)probe_data, ierr, serr; + + assert(base != 0UL); + + /* + * FMU_ERRGSR indicates the ID of the GIC + * block that faulted. + */ + assert(blkid <= FMU_BLK_PPI31); + + /* + * Find more information by reading FMU_ERRSTATUS + * register + */ + errstatus = gic_fmu_read_errstatus(base, blkid); + + /* + * If FMU_ERRSTATUS.V is set to 0, no RAS records + * need to be scanned. + */ + if ((errstatus & FMU_ERRSTATUS_V_BIT) == U(0)) { + return 0; + } + + /* + * FMU_ERRSTATUS.IERR indicates which Safety Mechanism + * reported the error. + */ + ierr = (errstatus >> FMU_ERRSTATUS_IERR_SHIFT) & + FMU_ERRSTATUS_IERR_MASK; + + /* + * FMU_ERRSTATUS.SERR indicates architecturally + * defined primary error code. + */ + serr = errstatus & FMU_ERRSTATUS_SERR_MASK; + + ERROR("**************************************\n"); + ERROR("RAS %s Error detected by GIC600 AE FMU\n", + ((errstatus & FMU_ERRSTATUS_UE_BIT) != 0U) ? + "Uncorrectable" : "Corrected"); + ERROR("\tStatus = 0x%lx \n", errstatus); + ERROR("\tBlock ID = 0x%x\n", blkid); + ERROR("\tSafety Mechanism ID = 0x%x (%s)\n", ierr, + ras_ierr_to_str(blkid, ierr)); + ERROR("\tArchitecturally defined primary error code = 0x%x\n", + serr); + ERROR("**************************************\n"); + + /* Clear FMU_ERRSTATUS */ + gic_fmu_write_errstatus(base, probe_data, errstatus); + + return 0; +} + /* * Initialization sequence for the FMU * @@ -138,8 +268,12 @@ void gic600_fmu_init(uint64_t base, uint /* Enable error detection for all error records */ for (unsigned int i = 0U; i < num_blk; i++) { - /* Skip next steps if the block is not present */ + /* + * Disable all safety mechanisms for blocks that are not + * present and skip the next steps. + */ if ((blk_present_mask & BIT(i)) == 0U) { + gic_fmu_disable_all_sm_blkid(base, i); continue; } @@ -168,22 +302,26 @@ void gic600_fmu_init(uint64_t base, uint */ if ((blk_present_mask & BIT(FMU_BLK_GICD)) != 0U) { smen = (GICD_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) | - (FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT); + (FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); smen = (GICD_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) | - (FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT); + (FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); } for (unsigned int i = FMU_BLK_PPI0; i < FMU_BLK_PPI31; i++) { if ((blk_present_mask & BIT(i)) != 0U) { smen = (PPI_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) | - (i << FMU_SMEN_BLK_SHIFT); + (i << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); smen = (PPI_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) | - (i << FMU_SMEN_BLK_SHIFT); + (i << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); } } @@ -191,11 +329,13 @@ void gic600_fmu_init(uint64_t base, uint for (unsigned int i = FMU_BLK_ITS0; i < FMU_BLK_ITS7; i++) { if ((blk_present_mask & BIT(i)) != 0U) { smen = (ITS_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) | - (i << FMU_SMEN_BLK_SHIFT); + (i << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); smen = (ITS_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) | - (i << FMU_SMEN_BLK_SHIFT); + (i << FMU_SMEN_BLK_SHIFT) | + FMU_SMEN_EN_BIT; gic_fmu_write_smen(base, smen); } } diff -pruN 2.6+dfsg-1/drivers/arm/gic/v3/gic600ae_fmu_helpers.c 2.7.0+dfsg-2/drivers/arm/gic/v3/gic600ae_fmu_helpers.c --- 2.6+dfsg-1/drivers/arm/gic/v3/gic600ae_fmu_helpers.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/gic/v3/gic600ae_fmu_helpers.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -258,3 +258,47 @@ void gic_fmu_write_pingmask(uintptr_t ba { GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val); } + +/* + * Helper function to disable all safety mechanisms for a given block + */ +void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid) +{ + uint32_t smen, max_smid = U(0); + + /* Sanity check block ID */ + assert((blkid >= FMU_BLK_GICD) && (blkid <= FMU_BLK_PPI31)); + + /* Find the max safety mechanism ID for the block */ + switch (blkid) { + case FMU_BLK_GICD: + max_smid = FMU_SMID_GICD_MAX; + break; + + case FMU_BLK_SPICOL: + max_smid = FMU_SMID_SPICOL_MAX; + break; + + case FMU_BLK_WAKERQ: + max_smid = FMU_SMID_WAKERQ_MAX; + break; + + case FMU_BLK_ITS0...FMU_BLK_ITS7: + max_smid = FMU_SMID_ITS_MAX; + break; + + case FMU_BLK_PPI0...FMU_BLK_PPI31: + max_smid = FMU_SMID_PPI_MAX; + break; + + default: + assert(false); + break; + } + + /* Disable all Safety Mechanisms for a given block id */ + for (unsigned int i = 0U; i < max_smid; i++) { + smen = (blkid << FMU_SMEN_BLK_SHIFT) | (i << FMU_SMEN_SMID_SHIFT); + gic_fmu_write_smen(base, smen); + } +} diff -pruN 2.6+dfsg-1/drivers/arm/gic/v3/gicv3_private.h 2.7.0+dfsg-2/drivers/arm/gic/v3/gicv3_private.h --- 2.6+dfsg-1/drivers/arm/gic/v3/gicv3_private.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/gic/v3/gicv3_private.h 2022-06-01 15:02:46.000000000 +0000 @@ -171,7 +171,7 @@ static inline u_register_t gicd_irouter_val_from_mpidr(u_register_t mpidr, unsigned int irm) { - return (mpidr & ~(U(0xff) << 24)) | + return (mpidr & MPIDR_AFFINITY_MASK) | ((irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT); } diff -pruN 2.6+dfsg-1/drivers/arm/mhu/mhu_v2_x.c 2.7.0+dfsg-2/drivers/arm/mhu/mhu_v2_x.c --- 2.6+dfsg-1/drivers/arm/mhu/mhu_v2_x.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/mhu/mhu_v2_x.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "mhu_v2_x.h" + +#define MHU_V2_X_MAX_CHANNELS 124 +#define MHU_V2_1_MAX_CHCOMB_INT 4 +#define ENABLE 0x1 +#define DISABLE 0x0 +#define CLEAR_INTR 0x1 +#define CH_PER_CH_COMB 0x20 +#define SEND_FRAME(p_mhu) ((struct mhu_v2_x_send_frame_t *)p_mhu) +#define RECV_FRAME(p_mhu) ((struct mhu_v2_x_recv_frame_t *)p_mhu) + +#define MHU_MAJOR_REV_V2 0x1u +#define MHU_MINOR_REV_2_0 0x0u +#define MHU_MINOR_REV_2_1 0x1u + +struct mhu_v2_x_send_ch_window_t { + /* Offset: 0x00 (R/ ) Channel Status */ + volatile uint32_t ch_st; + /* Offset: 0x04 (R/ ) Reserved */ + volatile uint32_t reserved_0; + /* Offset: 0x08 (R/ ) Reserved */ + volatile uint32_t reserved_1; + /* Offset: 0x0C ( /W) Channel Set */ + volatile uint32_t ch_set; + /* Offset: 0x10 (R/ ) Channel Interrupt Status (Reserved in 2.0) */ + volatile uint32_t ch_int_st; + /* Offset: 0x14 ( /W) Channel Interrupt Clear (Reserved in 2.0) */ + volatile uint32_t ch_int_clr; + /* Offset: 0x18 (R/W) Channel Interrupt Enable (Reserved in 2.0) */ + volatile uint32_t ch_int_en; + /* Offset: 0x1C (R/ ) Reserved */ + volatile uint32_t reserved_2; +}; + +struct mhu_v2_x_send_frame_t { + /* Offset: 0x000 ( / ) Sender Channel Window 0 -123 */ + struct mhu_v2_x_send_ch_window_t send_ch_window[MHU_V2_X_MAX_CHANNELS]; + /* Offset: 0xF80 (R/ ) Message Handling Unit Configuration */ + volatile uint32_t mhu_cfg; + /* Offset: 0xF84 (R/W) Response Configuration */ + volatile uint32_t resp_cfg; + /* Offset: 0xF88 (R/W) Access Request */ + volatile uint32_t access_request; + /* Offset: 0xF8C (R/ ) Access Ready */ + volatile uint32_t access_ready; + /* Offset: 0xF90 (R/ ) Interrupt Status */ + volatile uint32_t int_st; + /* Offset: 0xF94 ( /W) Interrupt Clear */ + volatile uint32_t int_clr; + /* Offset: 0xF98 (R/W) Interrupt Enable */ + volatile uint32_t int_en; + /* Offset: 0xF9C (R/ ) Reserved */ + volatile uint32_t reserved_0; + /* Offset: 0xFA0 (R/W) Channel Combined IRQ Stat (Reserved in 2.0) */ + volatile uint32_t ch_comb_int_st[MHU_V2_1_MAX_CHCOMB_INT]; + /* Offset: 0xFC4 (R/ ) Reserved */ + volatile uint32_t reserved_1[6]; + /* Offset: 0xFC8 (R/ ) Implementer Identification Register */ + volatile uint32_t iidr; + /* Offset: 0xFCC (R/ ) Architecture Identification Register */ + volatile uint32_t aidr; + /* Offset: 0xFD0 (R/ ) */ + volatile uint32_t pid_1[4]; + /* Offset: 0xFE0 (R/ ) */ + volatile uint32_t pid_0[4]; + /* Offset: 0xFF0 (R/ ) */ + volatile uint32_t cid[4]; +}; + +struct mhu_v2_x_rec_ch_window_t { + /* Offset: 0x00 (R/ ) Channel Status */ + volatile uint32_t ch_st; + /* Offset: 0x04 (R/ ) Channel Status Masked */ + volatile uint32_t ch_st_msk; + /* Offset: 0x08 ( /W) Channel Clear */ + volatile uint32_t ch_clr; + /* Offset: 0x0C (R/ ) Reserved */ + volatile uint32_t reserved_0; + /* Offset: 0x10 (R/ ) Channel Mask Status */ + volatile uint32_t ch_msk_st; + /* Offset: 0x14 ( /W) Channel Mask Set */ + volatile uint32_t ch_msk_set; + /* Offset: 0x18 ( /W) Channel Mask Clear */ + volatile uint32_t ch_msk_clr; + /* Offset: 0x1C (R/ ) Reserved */ + volatile uint32_t reserved_1; +}; + +struct mhu_v2_x_recv_frame_t { + /* Offset: 0x000 ( / ) Receiver Channel Window 0 -123 */ + struct mhu_v2_x_rec_ch_window_t rec_ch_window[MHU_V2_X_MAX_CHANNELS]; + /* Offset: 0xF80 (R/ ) Message Handling Unit Configuration */ + volatile uint32_t mhu_cfg; + /* Offset: 0xF84 (R/ ) Reserved */ + volatile uint32_t reserved_0[3]; + /* Offset: 0xF90 (R/ ) Interrupt Status (Reserved in 2.0) */ + volatile uint32_t int_st; + /* Offset: 0xF94 (R/ ) Interrupt Clear (Reserved in 2.0) */ + volatile uint32_t int_clr; + /* Offset: 0xF98 (R/W) Interrupt Enable (Reserved in 2.0) */ + volatile uint32_t int_en; + /* Offset: 0xF9C (R/ ) Reserved */ + volatile uint32_t reserved_1; + /* Offset: 0xFA0 (R/ ) Channel Combined IRQ Stat (Reserved in 2.0) */ + volatile uint32_t ch_comb_int_st[MHU_V2_1_MAX_CHCOMB_INT]; + /* Offset: 0xFB0 (R/ ) Reserved */ + volatile uint32_t reserved_2[6]; + /* Offset: 0xFC8 (R/ ) Implementer Identification Register */ + volatile uint32_t iidr; + /* Offset: 0xFCC (R/ ) Architecture Identification Register */ + volatile uint32_t aidr; + /* Offset: 0xFD0 (R/ ) */ + volatile uint32_t pid_1[4]; + /* Offset: 0xFE0 (R/ ) */ + volatile uint32_t pid_0[4]; + /* Offset: 0xFF0 (R/ ) */ + volatile uint32_t cid[4]; +}; + +union mhu_v2_x_frame { + struct mhu_v2_x_send_frame_t send_frame; + struct mhu_v2_x_recv_frame_t recv_frame; +}; + +enum mhu_v2_x_error_t mhu_v2_x_driver_init(struct mhu_v2_x_dev_t *dev, + enum mhu_v2_x_supported_revisions rev) +{ + uint32_t AIDR = 0; + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (dev->is_initialized) { + return MHU_V_2_X_ERR_ALREADY_INIT; + } + + if (rev == MHU_REV_READ_FROM_HW) { + /* Read revision from HW */ + if (dev->frame == MHU_V2_X_RECEIVER_FRAME) { + AIDR = p_mhu->recv_frame.aidr; + } else { + AIDR = p_mhu->send_frame.aidr; + } + + /* Get bits 7:4 to read major revision */ + if (((AIDR >> 4) & 0b1111) != MHU_MAJOR_REV_V2) { + /* Unsupported MHU version */ + return MHU_V_2_X_ERR_UNSUPPORTED_VERSION; + } /* No need to save major version, driver only supports MHUv2 */ + + /* Get bits 3:0 to read minor revision */ + dev->subversion = AIDR & 0b1111; + + if (dev->subversion != MHU_MINOR_REV_2_0 && + dev->subversion != MHU_MINOR_REV_2_1) { + /* Unsupported subversion */ + return MHU_V_2_X_ERR_UNSUPPORTED_VERSION; + } + } else { + /* Revisions were provided by caller */ + if (rev == MHU_REV_2_0) { + dev->subversion = MHU_MINOR_REV_2_0; + } else if (rev == MHU_REV_2_1) { + dev->subversion = MHU_MINOR_REV_2_1; + } else { + /* Unsupported subversion */ + return MHU_V_2_X_ERR_UNSUPPORTED_VERSION; + } /* No need to save major version, driver only supports MHUv2 */ + } + + dev->is_initialized = true; + + return MHU_V_2_X_ERR_NONE; +} + +uint32_t mhu_v2_x_get_num_channel_implemented(const struct mhu_v2_x_dev_t *dev) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_SENDER_FRAME) { + return (SEND_FRAME(p_mhu))->mhu_cfg; + } else { + assert(dev->frame == MHU_V2_X_RECEIVER_FRAME); + return (RECV_FRAME(p_mhu))->mhu_cfg; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_send(const struct mhu_v2_x_dev_t *dev, + uint32_t channel, uint32_t val) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_SENDER_FRAME) { + (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_poll(const struct mhu_v2_x_dev_t *dev, + uint32_t channel, uint32_t *value) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_SENDER_FRAME) { + *value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_clear(const struct mhu_v2_x_dev_t *dev, + uint32_t channel) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_RECEIVER_FRAME) { + (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_receive( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_RECEIVER_FRAME) { + *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_mask_set( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_RECEIVER_FRAME) { + (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} + +enum mhu_v2_x_error_t mhu_v2_x_channel_mask_clear( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame == MHU_V2_X_RECEIVER_FRAME) { + (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_clr = mask; + return MHU_V_2_X_ERR_NONE; + } else { + return MHU_V_2_X_ERR_INVALID_ARG; + } +} +enum mhu_v2_x_error_t mhu_v2_x_initiate_transfer( + const struct mhu_v2_x_dev_t *dev) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame != MHU_V2_X_SENDER_FRAME) { + return MHU_V_2_X_ERR_INVALID_ARG; + } + + (SEND_FRAME(p_mhu))->access_request = ENABLE; + + while (!((SEND_FRAME(p_mhu))->access_ready)) { + /* Wait in a loop for access ready signal to be high */ + ; + } + + return MHU_V_2_X_ERR_NONE; +} + +enum mhu_v2_x_error_t mhu_v2_x_close_transfer(const struct mhu_v2_x_dev_t *dev) +{ + union mhu_v2_x_frame *p_mhu; + + assert(dev != NULL); + + p_mhu = (union mhu_v2_x_frame *)dev->base; + + if (!(dev->is_initialized)) { + return MHU_V_2_X_ERR_NOT_INIT; + } + + if (dev->frame != MHU_V2_X_SENDER_FRAME) { + return MHU_V_2_X_ERR_INVALID_ARG; + } + + (SEND_FRAME(p_mhu))->access_request = DISABLE; + + return MHU_V_2_X_ERR_NONE; +} diff -pruN 2.6+dfsg-1/drivers/arm/mhu/mhu_v2_x.h 2.7.0+dfsg-2/drivers/arm/mhu/mhu_v2_x.h --- 2.6+dfsg-1/drivers/arm/mhu/mhu_v2_x.h 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/mhu/mhu_v2_x.h 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MHU_V2_X_H +#define MHU_V2_X_H + +#include +#include + +#define MHU_2_X_INTR_NR2R_OFF (0x0u) +#define MHU_2_X_INTR_R2NR_OFF (0x1u) +#define MHU_2_1_INTR_CHCOMB_OFF (0x2u) + +#define MHU_2_X_INTR_NR2R_MASK (0x1u << MHU_2_X_INTR_NR2R_OFF) +#define MHU_2_X_INTR_R2NR_MASK (0x1u << MHU_2_X_INTR_R2NR_OFF) +#define MHU_2_1_INTR_CHCOMB_MASK (0x1u << MHU_2_1_INTR_CHCOMB_OFF) + +enum mhu_v2_x_frame_t { + MHU_V2_X_SENDER_FRAME = 0x0u, + MHU_V2_X_RECEIVER_FRAME = 0x1u, +}; + +enum mhu_v2_x_supported_revisions { + MHU_REV_READ_FROM_HW = 0, + MHU_REV_2_0, + MHU_REV_2_1, +}; + +struct mhu_v2_x_dev_t { + uintptr_t base; + enum mhu_v2_x_frame_t frame; + uint32_t subversion; /*!< Hardware subversion: v2.X */ + bool is_initialized; /*!< Indicates if the MHU driver + * is initialized and enabled + */ +}; + +/** + * MHU v2 error enumeration types. + */ +enum mhu_v2_x_error_t { + MHU_V_2_X_ERR_NONE = 0, + MHU_V_2_X_ERR_NOT_INIT = -1, + MHU_V_2_X_ERR_ALREADY_INIT = -2, + MHU_V_2_X_ERR_UNSUPPORTED_VERSION = -3, + MHU_V_2_X_ERR_INVALID_ARG = -4, + MHU_V_2_X_ERR_GENERAL = -5 +}; + +/** + * Initializes the driver. + * + * dev MHU device struct mhu_v2_x_dev_t. + * rev MHU revision (if can't be identified from HW). + * + * Reads the MHU hardware version. + * + * Returns mhu_v2_x_error_t error code. + * + * MHU revision only has to be specified when versions can't be read + * from HW (ARCH_MAJOR_REV reg reads as 0x0). + * + * This function doesn't check if dev is NULL. + */ +enum mhu_v2_x_error_t mhu_v2_x_driver_init(struct mhu_v2_x_dev_t *dev, + enum mhu_v2_x_supported_revisions rev); + +/** + * Returns the number of channels implemented. + * + * dev MHU device struct mhu_v2_x_dev_t. + * + * This function doesn't check if dev is NULL. + */ +uint32_t mhu_v2_x_get_num_channel_implemented( + const struct mhu_v2_x_dev_t *dev); + +/** + * Sends the value over a channel. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Channel to send the value over. + * val Value to send. + * + * Sends the value over a channel. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_send(const struct mhu_v2_x_dev_t *dev, + uint32_t channel, uint32_t val); + +/** + * Polls sender channel status. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Channel to poll the status of. + * value Pointer to variable that will store the value. + * + * Polls sender channel status. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_poll(const struct mhu_v2_x_dev_t *dev, + uint32_t channel, uint32_t *value); + +/** + * Clears the channel after the value is send over it. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Channel to clear. + * + * Clears the channel after the value is send over it. + * + * Returns mhu_v2_x_error_t error code.. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_clear(const struct mhu_v2_x_dev_t *dev, + uint32_t channel); + +/** + * Receives the value over a channel. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Channel to receive the value from. + * value Pointer to variable that will store the value. + * + * Receives the value over a channel. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_receive( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value); + +/** + * Sets bits in the Channel Mask. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Which channel's mask to set. + * mask Mask to be set over a receiver frame. + * + * Sets bits in the Channel Mask. + * + * Returns mhu_v2_x_error_t error code.. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_mask_set( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); + +/** + * Clears bits in the Channel Mask. + * + * dev MHU device struct mhu_v2_x_dev_t. + * channel Which channel's mask to clear. + * mask Mask to be clear over a receiver frame. + * + * Clears bits in the Channel Mask. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + * This function doesn't check if channel is implemented. + */ +enum mhu_v2_x_error_t mhu_v2_x_channel_mask_clear( + const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); + +/** + * Initiates a MHU transfer with the handshake signals. + * + * dev MHU device struct mhu_v2_x_dev_t. + * + * Initiates a MHU transfer with the handshake signals in a blocking mode. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + */ +enum mhu_v2_x_error_t mhu_v2_x_initiate_transfer( + const struct mhu_v2_x_dev_t *dev); + +/** + * Closes a MHU transfer with the handshake signals. + * + * dev MHU device struct mhu_v2_x_dev_t. + * + * Closes a MHU transfer with the handshake signals in a blocking mode. + * + * Returns mhu_v2_x_error_t error code. + * + * This function doesn't check if dev is NULL. + */ +enum mhu_v2_x_error_t mhu_v2_x_close_transfer( + const struct mhu_v2_x_dev_t *dev); + +#endif /* MHU_V2_X_H */ diff -pruN 2.6+dfsg-1/drivers/arm/mhu/mhu_wrapper_v2_x.c 2.7.0+dfsg-2/drivers/arm/mhu/mhu_wrapper_v2_x.c --- 2.6+dfsg-1/drivers/arm/mhu/mhu_wrapper_v2_x.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/mhu/mhu_wrapper_v2_x.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include + +#include "mhu_v2_x.h" + +#define MHU_NOTIFY_VALUE (1234u) + +/* + * MHU devices for host: + * HSE: Host to Secure Enclave (sender device) + * SEH: Secure Enclave to Host (receiver device) + */ +struct mhu_v2_x_dev_t MHU1_HSE_DEV = {0, MHU_V2_X_SENDER_FRAME}; +struct mhu_v2_x_dev_t MHU1_SEH_DEV = {0, MHU_V2_X_RECEIVER_FRAME}; + +static enum mhu_error_t error_mapping_to_mhu_error_t(enum mhu_v2_x_error_t err) +{ + switch (err) { + case MHU_V_2_X_ERR_NONE: + return MHU_ERR_NONE; + case MHU_V_2_X_ERR_NOT_INIT: + return MHU_ERR_NOT_INIT; + case MHU_V_2_X_ERR_ALREADY_INIT: + return MHU_ERR_ALREADY_INIT; + case MHU_V_2_X_ERR_UNSUPPORTED_VERSION: + return MHU_ERR_UNSUPPORTED_VERSION; + case MHU_V_2_X_ERR_INVALID_ARG: + return MHU_ERR_INVALID_ARG; + case MHU_V_2_X_ERR_GENERAL: + return MHU_ERR_GENERAL; + default: + return MHU_ERR_GENERAL; + } +} + +static enum mhu_v2_x_error_t signal_and_wait_for_clear(void) +{ + enum mhu_v2_x_error_t err; + struct mhu_v2_x_dev_t *dev = &MHU1_HSE_DEV; + uint32_t val = MHU_NOTIFY_VALUE; + /* Using the last channel for notifications */ + uint32_t channel_notify = mhu_v2_x_get_num_channel_implemented(dev) - 1; + + err = mhu_v2_x_channel_send(dev, channel_notify, val); + if (err != MHU_V_2_X_ERR_NONE) { + return err; + } + + do { + err = mhu_v2_x_channel_poll(dev, channel_notify, &val); + if (err != MHU_V_2_X_ERR_NONE) { + break; + } + } while (val != 0); + + return err; +} + +static enum mhu_v2_x_error_t wait_for_signal(void) +{ + enum mhu_v2_x_error_t err; + struct mhu_v2_x_dev_t *dev = &MHU1_SEH_DEV; + uint32_t val = 0; + /* Using the last channel for notifications */ + uint32_t channel_notify = mhu_v2_x_get_num_channel_implemented(dev) - 1; + + do { + err = mhu_v2_x_channel_receive(dev, channel_notify, &val); + if (err != MHU_V_2_X_ERR_NONE) { + break; + } + } while (val != MHU_NOTIFY_VALUE); + + return err; +} + +static enum mhu_v2_x_error_t clear_and_wait_for_next_signal(void) +{ + enum mhu_v2_x_error_t err; + struct mhu_v2_x_dev_t *dev = &MHU1_SEH_DEV; + uint32_t num_channels = mhu_v2_x_get_num_channel_implemented(dev); + uint32_t i; + + /* Clear all channels */ + for (i = 0; i < num_channels; ++i) { + err = mhu_v2_x_channel_clear(dev, i); + if (err != MHU_V_2_X_ERR_NONE) { + return err; + } + } + + return wait_for_signal(); +} + +enum mhu_error_t mhu_init_sender(uintptr_t mhu_sender_base) +{ + enum mhu_v2_x_error_t err; + + assert(mhu_sender_base != (uintptr_t)NULL); + + MHU1_HSE_DEV.base = mhu_sender_base; + + err = mhu_v2_x_driver_init(&MHU1_HSE_DEV, MHU_REV_READ_FROM_HW); + return error_mapping_to_mhu_error_t(err); +} + +enum mhu_error_t mhu_init_receiver(uintptr_t mhu_receiver_base) +{ + enum mhu_v2_x_error_t err; + uint32_t num_channels, i; + + assert(mhu_receiver_base != (uintptr_t)NULL); + + MHU1_SEH_DEV.base = mhu_receiver_base; + + err = mhu_v2_x_driver_init(&MHU1_SEH_DEV, MHU_REV_READ_FROM_HW); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + + num_channels = mhu_v2_x_get_num_channel_implemented(&MHU1_SEH_DEV); + + /* Mask all channels except the notifying channel */ + for (i = 0; i < (num_channels - 1); ++i) { + err = mhu_v2_x_channel_mask_set(&MHU1_SEH_DEV, i, UINT32_MAX); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + } + + /* The last channel is used for notifications */ + err = mhu_v2_x_channel_mask_clear( + &MHU1_SEH_DEV, (num_channels - 1), UINT32_MAX); + return error_mapping_to_mhu_error_t(err); +} + +/* + * Public function. See mhu.h + * + * The basic steps of transferring a message: + * 1. Initiate MHU transfer. + * 2. Send over the size of the payload on Channel 1. It is the very first + * 4 Bytes of the transfer. Continue with Channel 2. + * 3. Send over the payload, writing the channels one after the other + * (4 Bytes each). The last available channel is reserved for controlling + * the transfer. + * When the last channel is reached or no more data is left, STOP. + * 4. Notify the receiver using the last channel and wait for acknowledge. + * If there is still data to transfer, jump to step 3. Otherwise, proceed. + * 5. Close MHU transfer. + * + */ +enum mhu_error_t mhu_send_data(const uint8_t *send_buffer, size_t size) +{ + enum mhu_v2_x_error_t err; + struct mhu_v2_x_dev_t *dev = &MHU1_HSE_DEV; + uint32_t num_channels = mhu_v2_x_get_num_channel_implemented(dev); + uint32_t chan = 0; + uint32_t i; + uint32_t *p; + + /* For simplicity, require the send_buffer to be 4-byte aligned */ + if ((uintptr_t)send_buffer & 0x3U) { + return MHU_ERR_INVALID_ARG; + } + + err = mhu_v2_x_initiate_transfer(dev); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + + /* First send over the size of the actual message */ + err = mhu_v2_x_channel_send(dev, chan, (uint32_t)size); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + chan++; + + p = (uint32_t *)send_buffer; + for (i = 0; i < size; i += 4) { + err = mhu_v2_x_channel_send(dev, chan, *p++); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + if (++chan == (num_channels - 1)) { + err = signal_and_wait_for_clear(); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + chan = 0; + } + } + + /* Signal the end of transfer. + * It's not required to send a signal when the message was + * perfectly-aligned (num_channels - 1 channels were used in the last + * round) preventing it from signaling twice at the end of transfer. + */ + if (chan != 0) { + err = signal_and_wait_for_clear(); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + } + + err = mhu_v2_x_close_transfer(dev); + return error_mapping_to_mhu_error_t(err); +} + +/* + * Public function. See mhu.h + * + * The basic steps of receiving a message: + * 1. Read the size of the payload from Channel 1. It is the very first + * 4 Bytes of the transfer. Continue with Channel 2. + * 2. Receive the payload, read the channels one after the other + * (4 Bytes each). The last available channel is reserved for controlling + * the transfer. + * When the last channel is reached clear all the channels + * (also sending an acknowledge on the last channel). + * 3. If there is still data to receive wait for a notification on the last + * channel and jump to step 2 as soon as it arrived. Otherwise, proceed. + * 4. End of transfer. + * + */ +enum mhu_error_t mhu_receive_data(uint8_t *receive_buffer, size_t *size) +{ + enum mhu_v2_x_error_t err; + struct mhu_v2_x_dev_t *dev = &MHU1_SEH_DEV; + uint32_t num_channels = mhu_v2_x_get_num_channel_implemented(dev); + uint32_t chan = 0; + uint32_t message_len; + uint32_t i; + uint32_t *p; + + /* For simplicity, require: + * - the receive_buffer to be 4-byte aligned, + * - the buffer size to be a multiple of 4. + */ + if (((uintptr_t)receive_buffer & 0x3U) || (*size & 0x3U)) { + return MHU_ERR_INVALID_ARG; + } + + /* Busy wait for incoming reply */ + err = wait_for_signal(); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + + /* The first word is the length of the actual message */ + err = mhu_v2_x_channel_receive(dev, chan, &message_len); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + chan++; + + if (message_len > *size) { + /* Message buffer too small */ + *size = message_len; + return MHU_ERR_BUFFER_TOO_SMALL; + } + + p = (uint32_t *)receive_buffer; + for (i = 0; i < message_len; i += 4) { + err = mhu_v2_x_channel_receive(dev, chan, p++); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + + /* Only wait for next transfer if there is still missing data */ + if (++chan == (num_channels - 1) && (message_len - i) > 4) { + /* Busy wait for next transfer */ + err = clear_and_wait_for_next_signal(); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + chan = 0; + } + } + + /* Clear all channels */ + for (i = 0; i < num_channels; ++i) { + err = mhu_v2_x_channel_clear(dev, i); + if (err != MHU_V_2_X_ERR_NONE) { + return error_mapping_to_mhu_error_t(err); + } + } + + *size = message_len; + + return MHU_ERR_NONE; +} diff -pruN 2.6+dfsg-1/drivers/arm/rss/rss_comms.c 2.7.0+dfsg-2/drivers/arm/rss/rss_comms.c --- 2.6+dfsg-1/drivers/arm/rss/rss_comms.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/rss/rss_comms.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define TYPE_OFFSET U(16) +#define TYPE_MASK (0xFFFFUL << TYPE_OFFSET) +#define IN_LEN_OFFSET U(8) +#define IN_LEN_MASK (0xFFUL << IN_LEN_OFFSET) +#define OUT_LEN_OFFSET U(0) +#define OUT_LEN_MASK (0xFFUL << OUT_LEN_OFFSET) + +#define PARAM_PACK(type, in_len, out_len) \ + (((((uint32_t)type) << TYPE_OFFSET) & TYPE_MASK) | \ + ((((uint32_t)in_len) << IN_LEN_OFFSET) & IN_LEN_MASK) | \ + ((((uint32_t)out_len) << OUT_LEN_OFFSET) & OUT_LEN_MASK)) + +#define PARAM_UNPACK_IN_LEN(ctrl_param) \ + ((size_t)(((ctrl_param) & IN_LEN_MASK) >> IN_LEN_OFFSET)) + +/* Message types */ +struct __packed packed_psa_call_t { + uint8_t protocol_ver; + uint8_t seq_num; + uint16_t client_id; + psa_handle_t handle; + uint32_t ctrl_param; /* type, in_len, out_len */ + uint16_t io_size[4]; +}; + +struct __packed packed_psa_reply_t { + uint8_t protocol_ver; + uint8_t seq_num; + uint16_t client_id; + int32_t return_val; + uint16_t out_size[4]; +}; + +/* + * In the current implementation the RoT Service request that requires the + * biggest message buffer is the RSS_ATTEST_GET_TOKEN. The maximum required + * buffer size is calculated based on the platform-specific needs of + * this request. + */ +#define MAX_REQUEST_PAYLOAD_SIZE (PSA_INITIAL_ATTEST_CHALLENGE_SIZE_64 \ + + PLAT_ATTEST_TOKEN_MAX_SIZE) + +/* Buffer to store the messages to be sent/received. */ +static uint8_t message_buf[MAX_REQUEST_PAYLOAD_SIZE] __aligned(4); + +static int32_t pack_params(const psa_invec *invecs, + size_t in_len, + uint8_t *buf, + size_t *buf_len) +{ + uint32_t i; + size_t payload_size = 0U; + + for (i = 0U; i < in_len; ++i) { + if (invecs[i].len > *buf_len - payload_size) { + return -1; + } + memcpy(buf + payload_size, invecs[i].base, invecs[i].len); + payload_size += invecs[i].len; + } + + *buf_len = payload_size; + return 0; +} + +static int serialise_message(const struct packed_psa_call_t *msg, + const psa_invec *invecs, + uint8_t *payload_buf, + size_t *payload_len) +{ + size_t message_len = 0U; + size_t len; + + /* Copy the message header into the payload buffer. */ + len = sizeof(*msg); + if (len > *payload_len) { + ERROR("[RSS-COMMS] Message buffer too small.\n"); + return -1; + } + memcpy(payload_buf, (const void *)msg, len); + message_len += len; + + /* The input data will follow the message header in the payload buffer. */ + len = *payload_len - message_len; + if (pack_params(invecs, PARAM_UNPACK_IN_LEN(msg->ctrl_param), + payload_buf + message_len, &len) != 0) { + ERROR("[RSS-COMMS] Message buffer too small.\n"); + return -1; + } + message_len += len; + + *payload_len = message_len; + return 0; +} + +static void unpack_params(const uint8_t *buf, + psa_outvec *outvecs, + size_t out_len) +{ + size_t i; + + for (i = 0U; i < out_len; ++i) { + memcpy(outvecs[i].base, buf, outvecs[i].len); + buf += outvecs[i].len; + } +} + +static void deserialise_reply(struct packed_psa_reply_t *reply, + psa_outvec *outvecs, + size_t outlen, + const uint8_t *message, + size_t message_len) +{ + uint32_t i; + + memcpy(reply, message, sizeof(*reply)); + + /* Outvecs */ + for (i = 0U; i < outlen; ++i) { + outvecs[i].len = reply->out_size[i]; + } + + unpack_params(message + sizeof(*reply), outvecs, outlen); +} + +psa_status_t psa_call(psa_handle_t handle, int32_t type, + const psa_invec *in_vec, size_t in_len, + psa_outvec *out_vec, size_t out_len) +{ + enum mhu_error_t err; + static uint32_t seq_num = 1U; + struct packed_psa_call_t msg = { + .protocol_ver = 0U, + .seq_num = seq_num, + /* No need to distinguish callers (currently concurrent calls are not supported). */ + .client_id = 1U, + .handle = handle, + .ctrl_param = PARAM_PACK(type, in_len, out_len), + }; + + struct packed_psa_reply_t reply = {0}; + size_t message_size; + uint32_t i; + + /* Fill msg iovec lengths */ + for (i = 0U; i < in_len; ++i) { + msg.io_size[i] = in_vec[i].len; + } + for (i = 0U; i < out_len; ++i) { + msg.io_size[in_len + i] = out_vec[i].len; + } + + message_size = sizeof(message_buf); + if (serialise_message(&msg, in_vec, message_buf, &message_size)) { + /* Local buffer is probably too small. */ + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + err = mhu_send_data(message_buf, message_size); + if (err != MHU_ERR_NONE) { + return PSA_ERROR_COMMUNICATION_FAILURE; + } + + message_size = sizeof(message_buf); +#if DEBUG + /* + * Poisoning the message buffer (with a known pattern). + * Helps in detecting hypothetical RSS communication bugs. + */ + memset(message_buf, 0xA5, message_size); +#endif + err = mhu_receive_data(message_buf, &message_size); + if (err != MHU_ERR_NONE) { + return PSA_ERROR_COMMUNICATION_FAILURE; + } + + deserialise_reply(&reply, out_vec, out_len, message_buf, message_size); + + seq_num++; + + VERBOSE("[RSS-COMMS] Received reply\n"); + VERBOSE("protocol_ver=%d\n", reply.protocol_ver); + VERBOSE("seq_num=%d\n", reply.seq_num); + VERBOSE("client_id=%d\n", reply.client_id); + VERBOSE("return_val=%d\n", reply.return_val); + VERBOSE("out_size[0]=%d\n", reply.out_size[0]); + + return reply.return_val; +} + +int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base) +{ + enum mhu_error_t err; + + err = mhu_init_sender(mhu_sender_base); + if (err != MHU_ERR_NONE) { + ERROR("[RSS-COMMS] Host to RSS MHU driver initialization failed: %d\n", err); + return -1; + } + + err = mhu_init_receiver(mhu_receiver_base); + if (err != MHU_ERR_NONE) { + ERROR("[RSS-COMMS] RSS to Host MHU driver initialization failed: %d\n", err); + return -1; + } + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/arm/smmu/smmu_v3.c 2.7.0+dfsg-2/drivers/arm/smmu/smmu_v3.c --- 2.6+dfsg-1/drivers/arm/smmu/smmu_v3.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/smmu/smmu_v3.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,11 +9,12 @@ #include #include #include +#include /* SMMU poll number of retries */ #define SMMU_POLL_TIMEOUT_US U(1000) -static int __init smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, +static int smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, uint32_t value) { uint32_t reg_val; @@ -79,14 +80,74 @@ int __init smmuv3_init(uintptr_t smmu_ba if (smmuv3_security_init(smmu_base) != 0) return -1; - /* Check if the SMMU supports secure state */ - if ((mmio_read_32(smmu_base + SMMU_S_IDR1) & - SMMU_S_IDR1_SECURE_IMPL) == 0U) - return 0; +#if ENABLE_RME + + if (get_armv9_2_feat_rme_support() != 0U) { + if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) & + SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) { + WARN("Skip SMMU GPC configuration.\n"); + } else { + uint64_t gpccr_el3 = read_gpccr_el3(); + uint64_t gptbr_el3 = read_gptbr_el3(); + + /* SMMU_ROOT_GPT_BASE_CFG[16] is RES0. */ + gpccr_el3 &= ~(1UL << 16); + + /* + * TODO: SMMU_ROOT_GPT_BASE_CFG is 64b in the spec, + * but SMMU model only accepts 32b access. + */ + mmio_write_32(smmu_base + SMMU_ROOT_GPT_BASE_CFG, + gpccr_el3); + + /* + * pa_gpt_table_base[51:12] maps to GPTBR_EL3[39:0] + * whereas it maps to SMMU_ROOT_GPT_BASE[51:12] + * hence needs a 12 bit left shit. + */ + mmio_write_64(smmu_base + SMMU_ROOT_GPT_BASE, + gptbr_el3 << 12); + + /* + * ACCESSEN=1: SMMU- and client-originated accesses are + * not terminated by this mechanism. + * GPCEN=1: All clients and SMMU-originated accesses, + * except GPT-walks, are subject to GPC. + */ + mmio_setbits_32(smmu_base + SMMU_ROOT_CR0, + SMMU_ROOT_CR0_GPCEN | + SMMU_ROOT_CR0_ACCESSEN); + + /* Poll for ACCESSEN and GPCEN ack bits. */ + if (smmuv3_poll(smmu_base + SMMU_ROOT_CR0ACK, + SMMU_ROOT_CR0_GPCEN | + SMMU_ROOT_CR0_ACCESSEN, + SMMU_ROOT_CR0_GPCEN | + SMMU_ROOT_CR0_ACCESSEN) != 0) { + WARN("Failed enabling SMMU GPC.\n"); + + /* + * Do not return in error, but fall back to + * invalidating all entries through the secure + * register file. + */ + } + } + } + +#endif /* ENABLE_RME */ + /* * Initiate invalidation of secure caches and TLBs if the SMMU * supports secure state. If not, it's implementation defined * as to how SMMU_S_INIT register is accessed. + * Arm SMMU Arch RME supplement, section 3.4: all SMMU registers + * specified to be accessible only in secure physical address space are + * additionally accessible in root physical address space in an SMMU + * with RME. + * Section 3.3: as GPT information is permitted to be cached in a TLB, + * the SMMU_S_INIT.INV_ALL mechanism also invalidates GPT information + * cached in TLBs. */ mmio_write_32(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL); @@ -94,3 +155,28 @@ int __init smmuv3_init(uintptr_t smmu_ba return smmuv3_poll(smmu_base + SMMU_S_INIT, SMMU_S_INIT_INV_ALL, 0U); } + +int smmuv3_ns_set_abort_all(uintptr_t smmu_base) +{ + /* Attribute update has completed when SMMU_GBPA.Update bit is 0 */ + if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) { + return -1; + } + + /* + * Set GBPA's ABORT bit. Other GBPA fields are presumably ignored then, + * so simply preserve their value. + */ + mmio_setbits_32(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE | SMMU_GBPA_ABORT); + if (smmuv3_poll(smmu_base + SMMU_GBPA, SMMU_GBPA_UPDATE, 0U) != 0U) { + return -1; + } + + /* Disable the SMMU to engage the GBPA fields previously configured. */ + mmio_clrbits_32(smmu_base + SMMU_CR0, SMMU_CR0_SMMUEN); + if (smmuv3_poll(smmu_base + SMMU_CR0ACK, SMMU_CR0_SMMUEN, 0U) != 0U) { + return -1; + } + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/arm/tzc/tzc400.c 2.7.0+dfsg-2/drivers/arm/tzc/tzc400.c --- 2.6+dfsg-1/drivers/arm/tzc/tzc400.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/arm/tzc/tzc400.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -306,8 +306,8 @@ void tzc400_enable_filters(void) * See the 'ARM (R) CoreLink TM TZC-400 TrustZone (R) * Address Space Controller' Technical Reference Manual. */ - ERROR("TZC-400 : Filter %d Gatekeeper already" - " enabled.\n", filter); + ERROR("TZC-400 : Filter %u Gatekeeper already enabled.\n", + filter); panic(); } _tzc400_set_gate_keeper(tzc400.base, filter, 1); diff -pruN 2.6+dfsg-1/drivers/auth/auth_mod.c 2.7.0+dfsg-2/drivers/auth/auth_mod.c --- 2.6+dfsg-1/drivers/auth/auth_mod.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/auth_mod.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -339,9 +339,6 @@ void auth_mod_init(void) /* Check we have a valid CoT registered */ assert(cot_desc_ptr != NULL); - /* Crypto module */ - crypto_mod_init(); - /* Image parser module */ img_parser_init(); } diff -pruN 2.6+dfsg-1/drivers/auth/crypto_mod.c 2.7.0+dfsg-2/drivers/auth/crypto_mod.c --- 2.6+dfsg-1/drivers/auth/crypto_mod.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/crypto_mod.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,8 +46,13 @@ void crypto_mod_init(void) { assert(crypto_lib_desc.name != NULL); assert(crypto_lib_desc.init != NULL); +#if TRUSTED_BOARD_BOOT assert(crypto_lib_desc.verify_signature != NULL); assert(crypto_lib_desc.verify_hash != NULL); +#endif /* TRUSTED_BOARD_BOOT */ +#if MEASURED_BOOT + assert(crypto_lib_desc.calc_hash != NULL); +#endif /* MEASURED_BOOT */ /* Initialize the cryptographic library */ crypto_lib_desc.init(); @@ -114,8 +119,9 @@ int crypto_mod_verify_hash(void *data_pt * data_ptr, data_len: data to be hashed * output: resulting hash */ -int crypto_mod_calc_hash(unsigned int alg, void *data_ptr, - unsigned int data_len, unsigned char *output) +int crypto_mod_calc_hash(enum crypto_md_algo alg, void *data_ptr, + unsigned int data_len, + unsigned char output[CRYPTO_MD_MAX_SIZE]) { assert(data_ptr != NULL); assert(data_len != 0); diff -pruN 2.6+dfsg-1/drivers/auth/dualroot/cot.c 2.7.0+dfsg-2/drivers/auth/dualroot/cot.c --- 2.6+dfsg-1/drivers/auth/dualroot/cot.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/dualroot/cot.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ #include -#include +#include MBEDTLS_CONFIG_FILE #include #include diff -pruN 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_common.c 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_common.c --- 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_common.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_common.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,7 +13,7 @@ #include #include -#include +#include MBEDTLS_CONFIG_FILE #include static void cleanup(void) diff -pruN 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_common.mk 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_common.mk --- 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_common.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_common.mk 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2020, Arm Limited. All rights reserved. +# Copyright (c) 2015-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -16,7 +16,7 @@ endif MBEDTLS_INC = -I${MBEDTLS_DIR}/include # Specify mbed TLS configuration file -MBEDTLS_CONFIG_FILE := "" +MBEDTLS_CONFIG_FILE ?= "" $(eval $(call add_define,MBEDTLS_CONFIG_FILE)) MBEDTLS_SOURCES += drivers/auth/mbedtls/mbedtls_common.c @@ -48,6 +48,7 @@ LIBMBEDTLS_SRCS := $(addprefix ${MBEDTL rsa_internal.c \ x509.c \ x509_crt.c \ + constant_time.c \ ) # The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key @@ -96,6 +97,18 @@ else TF_MBEDTLS_USE_AES_GCM := 0 endif +ifeq ($(MEASURED_BOOT),1) + ifeq (${TPM_HASH_ALG}, sha256) + TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA256 + else ifeq (${TPM_HASH_ALG}, sha384) + TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA384 + else ifeq (${TPM_HASH_ALG}, sha512) + TF_MBEDTLS_TPM_HASH_ALG_ID := TF_MBEDTLS_SHA512 + else + $(error "TPM_HASH_ALG not defined.") + endif +endif + # Needs to be set to drive mbed TLS configuration correctly $(eval $(call add_defines,\ $(sort \ @@ -105,6 +118,10 @@ $(eval $(call add_defines,\ TF_MBEDTLS_USE_AES_GCM \ ))) +ifeq ($(MEASURED_BOOT),1) + $(eval $(call add_define,TF_MBEDTLS_TPM_HASH_ALG_ID)) +endif + $(eval $(call MAKE_LIB,mbedtls)) endif diff -pruN 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_crypto.c 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_crypto.c --- 2.6+dfsg-1/drivers/auth/mbedtls/mbedtls_crypto.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/mbedtls/mbedtls_crypto.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,16 @@ #define LIB_NAME "mbed TLS" +#if MEASURED_BOOT +/* + * CRYPTO_MD_MAX_SIZE value is as per current stronger algorithm available + * so make sure that mbed TLS MD maximum size must be lesser than this. + */ +CASSERT(CRYPTO_MD_MAX_SIZE >= MBEDTLS_MD_MAX_SIZE, + assert_mbedtls_md_size_overflow); + +#endif /* MEASURED_BOOT */ + /* * AlgorithmIdentifier ::= SEQUENCE { * algorithm OBJECT IDENTIFIER, @@ -50,6 +60,7 @@ static void init(void) mbedtls_init(); } +#if TRUSTED_BOARD_BOOT /* * Verify a signature. * @@ -208,24 +219,49 @@ static int verify_hash(void *data_ptr, u return CRYPTO_SUCCESS; } +#endif /* TRUSTED_BOARD_BOOT */ #if MEASURED_BOOT /* + * Map a generic crypto message digest algorithm to the corresponding macro used + * by Mbed TLS. + */ +static inline mbedtls_md_type_t md_type(enum crypto_md_algo algo) +{ + switch (algo) { + case CRYPTO_MD_SHA512: + return MBEDTLS_MD_SHA512; + case CRYPTO_MD_SHA384: + return MBEDTLS_MD_SHA384; + case CRYPTO_MD_SHA256: + return MBEDTLS_MD_SHA256; + default: + /* Invalid hash algorithm. */ + return MBEDTLS_MD_NONE; + } +} + +/* * Calculate a hash * * output points to the computed hash */ -int calc_hash(unsigned int alg, void *data_ptr, - unsigned int data_len, unsigned char *output) +static int calc_hash(enum crypto_md_algo md_algo, void *data_ptr, + unsigned int data_len, + unsigned char output[CRYPTO_MD_MAX_SIZE]) { const mbedtls_md_info_t *md_info; - md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg); + md_info = mbedtls_md_info_from_type(md_type(md_algo)); if (md_info == NULL) { return CRYPTO_ERR_HASH; } - /* Calculate the hash of the data */ + /* + * Calculate the hash of the data, it is safe to pass the + * 'output' hash buffer pointer considering its size is always + * bigger than or equal to MBEDTLS_MD_MAX_SIZE. + */ return mbedtls_md(md_info, data_ptr, data_len, output); } #endif /* MEASURED_BOOT */ @@ -332,7 +368,7 @@ static int auth_decrypt(enum crypto_dec_ /* * Register crypto library descriptor */ -#if MEASURED_BOOT +#if MEASURED_BOOT && TRUSTED_BOARD_BOOT #if TF_MBEDTLS_USE_AES_GCM REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, auth_decrypt); @@ -340,11 +376,13 @@ REGISTER_CRYPTO_LIB(LIB_NAME, init, veri REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, NULL); #endif -#else /* MEASURED_BOOT */ +#elif TRUSTED_BOARD_BOOT #if TF_MBEDTLS_USE_AES_GCM REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, auth_decrypt); #else REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL); #endif -#endif /* MEASURED_BOOT */ +#elif MEASURED_BOOT +REGISTER_CRYPTO_LIB(LIB_NAME, init, calc_hash); +#endif /* MEASURED_BOOT && TRUSTED_BOARD_BOOT */ diff -pruN 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl1.c 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl1.c --- 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl1.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl1.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include MBEDTLS_CONFIG_FILE #include #include diff -pruN 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl1_r64.c 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl1_r64.c --- 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl1_r64.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl1_r64.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include MBEDTLS_CONFIG_FILE #include #if USE_TBBR_DEFS diff -pruN 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl2.c 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl2.c --- 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_bl2.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_bl2.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include MBEDTLS_CONFIG_FILE #include #include diff -pruN 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_common.c 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_common.c --- 2.6+dfsg-1/drivers/auth/tbbr/tbbr_cot_common.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/auth/tbbr/tbbr_cot_common.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ #include #include -#include +#include MBEDTLS_CONFIG_FILE #include #include diff -pruN 2.6+dfsg-1/drivers/clk/clk.c 2.7.0+dfsg-2/drivers/clk/clk.c --- 2.6+dfsg-1/drivers/clk/clk.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/clk/clk.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Author(s): Ludovic Barre, for STMicroelectronics. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +static const struct clk_ops *ops; + +int clk_enable(unsigned long id) +{ + assert((ops != NULL) && (ops->enable != NULL)); + + return ops->enable(id); +} + +void clk_disable(unsigned long id) +{ + assert((ops != NULL) && (ops->disable != NULL)); + + ops->disable(id); +} + +unsigned long clk_get_rate(unsigned long id) +{ + assert((ops != NULL) && (ops->get_rate != NULL)); + + return ops->get_rate(id); +} + +int clk_get_parent(unsigned long id) +{ + assert((ops != NULL) && (ops->get_parent != NULL)); + + return ops->get_parent(id); +} + +bool clk_is_enabled(unsigned long id) +{ + assert((ops != NULL) && (ops->is_enabled != NULL)); + + return ops->is_enabled(id); +} + +/* + * Initialize the clk. The fields in the provided clk + * ops pointer must be valid. + */ +void clk_register(const struct clk_ops *ops_ptr) +{ + assert((ops_ptr != NULL) && + (ops_ptr->enable != NULL) && + (ops_ptr->disable != NULL) && + (ops_ptr->get_rate != NULL) && + (ops_ptr->get_parent != NULL) && + (ops_ptr->is_enabled != NULL)); + + ops = ops_ptr; +} diff -pruN 2.6+dfsg-1/drivers/fwu/fwu.c 2.7.0+dfsg-2/drivers/fwu/fwu.c --- 2.6+dfsg-1/drivers/fwu/fwu.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/fwu/fwu.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ CASSERT((offsetof(struct fwu_metadata, c crc_32_must_be_first_member_of_structure); static struct fwu_metadata metadata; -static bool is_fwu_initialized; +static bool is_metadata_initialized __unused; /******************************************************************************* * Compute CRC32 of the FWU metadata, and check it against the CRC32 value @@ -142,7 +142,7 @@ bool fwu_is_trial_run_state(void) { bool trial_run = false; - assert(is_fwu_initialized == true); + assert(is_metadata_initialized); for (unsigned int i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) { struct fwu_image_entry *entry = &metadata.img_entry[i]; @@ -157,6 +157,13 @@ bool fwu_is_trial_run_state(void) return trial_run; } +const struct fwu_metadata *fwu_get_metadata(void) +{ + assert(is_metadata_initialized); + + return &metadata; +} + /******************************************************************************* * Load verified copy of FWU metadata image kept in the platform NV storage * into local FWU metadata structure. @@ -181,7 +188,7 @@ void fwu_init(void) } } - plat_fwu_set_images_source(&metadata); + is_metadata_initialized = true; - is_fwu_initialized = true; + plat_fwu_set_images_source(&metadata); } diff -pruN 2.6+dfsg-1/drivers/io/io_mtd.c 2.7.0+dfsg-2/drivers/io/io_mtd.c --- 2.6+dfsg-1/drivers/io/io_mtd.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/io/io_mtd.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,13 +8,13 @@ #include #include -#include - #include #include #include #include +#include + typedef struct { io_mtd_dev_spec_t *dev_spec; uintptr_t base; @@ -214,7 +214,7 @@ static int mtd_read(io_entity_t *entity, ops = &cur->dev_spec->ops; assert(ops->read != NULL); - VERBOSE("Read at %llx into %lx, length %zi\n", + VERBOSE("Read at %llx into %lx, length %zu\n", cur->base + cur->pos, buffer, length); if ((cur->base + cur->pos + length) > cur->dev_spec->device_size) { return -EINVAL; diff -pruN 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-3700.c 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-3700.c --- 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-3700.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-3700.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2021 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -301,7 +301,7 @@ static int mvebu_a3700_comphy_sata_power } /* Clear phy isolation mode to make it work in normal mode */ - offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; + offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE); /* 0. Check the Polarity invert bits */ @@ -310,21 +310,21 @@ static int mvebu_a3700_comphy_sata_power if (invert & COMPHY_POLARITY_RXD_INVERT) data |= RXD_INVERT_BIT; - offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET; + offset = COMPHY_SYNC_PATTERN + SATAPHY_LANE2_REG_BASE_OFFSET; comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT | RXD_INVERT_BIT); /* 1. Select 40-bit data width width */ - offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET; + offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET; comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK); /* 2. Select reference clock(25M) and PHY mode (SATA) */ offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; if (get_ref_clk() == 40) - ref_clk = REF_CLOCK_SPEED_40M; + ref_clk = REF_FREF_SEL_SERDES_40MHZ; else - ref_clk = REF_CLOCK_SPEED_25M; + ref_clk = REF_FREF_SEL_SERDES_25MHZ; comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, REF_FREF_SEL_MASK | PHY_MODE_MASK); @@ -352,7 +352,7 @@ static int mvebu_a3700_comphy_sata_power /* Polling status */ mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, - COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); + COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET); ret = polling_with_timeout(comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET, @@ -401,8 +401,8 @@ static int mvebu_a3700_comphy_sgmii_powe * PHY TXP/TXN output to idle state during PHY initialization * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. */ - data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; - mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | + data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; + mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index); reg_set(offset, data, mask); @@ -422,8 +422,8 @@ static int mvebu_a3700_comphy_sgmii_powe data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET; } else if (mode == COMPHY_2500BASEX_MODE) { /* 2500Base-X, SerDes speed 3.125G */ - data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET; - data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET; + data |= SD_SPEED_3_125_G << GEN_RX_SEL_OFFSET; + data |= SD_SPEED_3_125_G << GEN_TX_SEL_OFFSET; } else { /* Other rates are not supported */ ERROR("unsupported SGMII speed on comphy lane%d\n", @@ -450,16 +450,16 @@ static int mvebu_a3700_comphy_sgmii_powe */ data = 0; mask = PHY_REF_CLK_SEL; - reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask); + reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask); /* * 9. Set correct reference clock frequency in COMPHY register * REF_FREF_SEL. */ if (get_ref_clk() == 40) - data = REF_CLOCK_SPEED_50M; + data = REF_FREF_SEL_SERDES_50MHZ; else - data = REF_CLOCK_SPEED_25M; + data = REF_FREF_SEL_SERDES_25MHZ; mask = REF_FREF_SEL_MASK; reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask); @@ -477,7 +477,8 @@ static int mvebu_a3700_comphy_sgmii_powe */ data = DATA_WIDTH_10BIT; mask = SEL_DATA_WIDTH_MASK; - reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask); + reg_set16(SGMIIPHY_ADDR(COMPHY_DIG_LOOPBACK_EN, sd_ip_addr), + data, mask); /* * 12. As long as DFE function needs to be enabled in any mode, @@ -523,7 +524,7 @@ static int mvebu_a3700_comphy_sgmii_powe if (invert & COMPHY_POLARITY_RXD_INVERT) data |= RXD_INVERT_BIT; mask = TXD_INVERT_BIT | RXD_INVERT_BIT; - reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask); + reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN, sd_ip_addr), data, mask); /* * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to @@ -645,68 +646,68 @@ static int mvebu_a3700_comphy_usb3_power */ mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | CFG_TX_ALIGN_POS_MASK; - usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK, - mask); + usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask); /* * 2. Set BIT0: enable transmitter in high impedance mode * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency * Set BIT6: Tx detect Rx at HiZ mode * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db - * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register + * together with bit 0 of COMPHY_LANE_CFG0 register */ mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | TX_ELEC_IDLE_MODE_EN; data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; - usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask); + usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask); /* * 3. Set Spread Spectrum Clock Enabled */ - usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR, + usb3_reg_set(reg_base, COMPHY_LANE_CFG4, SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); /* * 4. Set Override Margining Controls From the MAC: * Use margining signals from lane configuration */ - usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR, + usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL, MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK); /* * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles * set Mode Clock Source = PCLK is generated from REFCLK */ - usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0, - (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | - BUNDLE_SAMPLE_CTRL | PLL_READY_DLY)); + usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0, + (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | + BUNDLE_PERIOD_SCALE_MASK | BUNDLE_SAMPLE_CTRL | + PLL_READY_DLY_MASK)); /* * 6. Set G2 Spread Spectrum Clock Amplitude at 4K */ - usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2, - G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK); + usb3_reg_set(reg_base, COMPHY_GEN2_SET2, + GS2_TX_SSC_AMP_VALUE_20, GS2_TX_SSC_AMP_MASK); /* * 7. Unset G3 Spread Spectrum Clock Amplitude * set G3 TX and RX Register Master Current Select */ - mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK | - RSVD_PH03FH_6_0_MASK; - usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3, - G3_VREG_RXTX_MAS_ISET_60U, mask); + mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | + GS2_RSVD_6_0_MASK; + usb3_reg_set(reg_base, COMPHY_GEN3_SET2, + GS2_VREG_RXTX_MAS_ISET_60U, mask); /* * 8. Check crystal jumper setting and program the Power and PLL Control * accordingly Change RX wait */ if (get_ref_clk() == 40) { - ref_clk = REF_CLOCK_SPEED_40M; + ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; } else { /* 25 MHz */ - ref_clk = USB3_REF_CLOCK_SPEED_25M; + ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; } @@ -720,24 +721,24 @@ static int mvebu_a3700_comphy_usb3_power mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | CFG_PM_RXDLOZ_WAIT_MASK; data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; - usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask); + usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask); /* * 9. Enable idle sync */ - data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN; - usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK); + data = IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN; + usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK); /* * 10. Enable the output of 500M clock */ - data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN; - usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK); + data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN; + usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK); /* * 11. Set 20-bit data width */ - usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT, + usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT, REG_16_BIT_MASK); /* @@ -758,32 +759,31 @@ static int mvebu_a3700_comphy_usb3_power data |= RXD_INVERT_BIT; } mask = TXD_INVERT_BIT | RXD_INVERT_BIT; - usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask); + usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask); /* * 14. Set max speed generation to USB3.0 5Gbps */ - usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G, + usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN, PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK); /* * 15. Set capacitor value for FFE gain peaking to 0xF */ - usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3, - COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK); + usb3_reg_set(reg_base, COMPHY_GEN2_SET3, + GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); /* * 16. Release SW reset */ data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; - usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data, - REG_16_BIT_MASK); + usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); if (comphy_index == COMPHY_LANE2) { - data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET; + data = COMPHY_LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET; mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET, data); @@ -791,7 +791,7 @@ static int mvebu_a3700_comphy_usb3_power ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, COMPHY_PLL_TIMEOUT, REG_32BIT); } else { - ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base, + ret = polling_with_timeout(LANE_STAT1_ADDR(USB3) + reg_base, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, COMPHY_PLL_TIMEOUT, REG_16BIT); } @@ -826,11 +826,11 @@ static int mvebu_a3700_comphy_pcie_power USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); /* 2. Select 20 bit SERDES interface. */ - reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, + reg_set16(CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, CFG_SEL_20B, CFG_SEL_20B); /* 3. Force to use reg setting for PCIe mode */ - reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR, + reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR, SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); /* 4. Change RX wait */ @@ -840,12 +840,12 @@ static int mvebu_a3700_comphy_pcie_power CFG_PM_RXDLOZ_WAIT_MASK)); /* 5. Enable idle sync */ - reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, - UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); + reg_set16(IDLE_SYNC_EN_ADDR(PCIE) + COMPHY_SD_ADDR, + IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK); /* 6. Enable the output of 100M/125M/500M clock */ - reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR, - MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, + reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, + MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN, REG_16_BIT_MASK); /* @@ -859,9 +859,9 @@ static int mvebu_a3700_comphy_pcie_power */ if (get_ref_clk() == 40) - ref_clk = REF_CLOCK_SPEED_40M; + ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; else - ref_clk = PCIE_REF_CLOCK_SPEED_25M; + ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | @@ -881,17 +881,17 @@ static int mvebu_a3700_comphy_pcie_power data |= RXD_INVERT_BIT; } mask = TXD_INVERT_BIT | RXD_INVERT_BIT; - reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); + reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* 11. Release SW reset */ - reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, - MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32, - SOFT_RESET | MODE_REFDIV); + data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; + mask = data | SOFT_RESET | MODE_REFDIV_MASK; + reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); /* Wait for > 55 us to allow PCLK be enabled */ udelay(PLL_SET_DELAY_US); - ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR, + ret = polling_with_timeout(LANE_STAT1_ADDR(PCIE) + COMPHY_SD_ADDR, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN, COMPHY_PLL_TIMEOUT, REG_16BIT); if (ret) { @@ -961,7 +961,7 @@ static int mvebu_a3700_comphy_sata_power debug_enter(); /* Set phy isolation mode */ - offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET; + offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET; comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE, PHY_ISOLATE_MODE); @@ -1025,7 +1025,7 @@ static int mvebu_a3700_comphy_sata_is_pl /* Polling status */ mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET, - COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET); + COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET); addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET; data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT, COMPHY_PLL_TIMEOUT, REG_32BIT); diff -pruN 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-3700.h 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-3700.h --- 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-3700.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-3700.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2021 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -13,11 +13,11 @@ #define REG_16_BIT_MASK 0xFFFF #define COMPHY_SELECTOR_PHY_REG 0xFC -/* bit0: 0: Lane0 is GBE0; 1: Lane1 is PCIE */ +/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIE */ #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) -/* bit4: 0: Lane1 is GBE1; 1: Lane1 is USB3 */ +/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) -/* bit8: 0: Lane1 is USB, Lane2 is SATA; 1: Lane2 is USB3 */ +/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) /* SATA PHY register offset */ @@ -53,12 +53,11 @@ enum { #define PLL_LOCK_BIT BIT(8) #define REF_FREF_SEL_OFFSET 0 #define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET) -#define REF_CLOCK_SPEED_25M (0x1 << REF_FREF_SEL_OFFSET) -#define REF_CLOCK_SPEED_30M (0x2 << REF_FREF_SEL_OFFSET) -#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M -#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M -#define REF_CLOCK_SPEED_40M (0x3 << REF_FREF_SEL_OFFSET) -#define REF_CLOCK_SPEED_50M (0x4 << REF_FREF_SEL_OFFSET) +#define REF_FREF_SEL_SERDES_25MHZ (0x1 << REF_FREF_SEL_OFFSET) +#define REF_FREF_SEL_SERDES_40MHZ (0x3 << REF_FREF_SEL_OFFSET) +#define REF_FREF_SEL_SERDES_50MHZ (0x4 << REF_FREF_SEL_OFFSET) +#define REF_FREF_SEL_PCIE_USB3_25MHZ (0x2 << REF_FREF_SEL_OFFSET) +#define REF_FREF_SEL_PCIE_USB3_40MHZ (0x3 << REF_FREF_SEL_OFFSET) #define PHY_MODE_OFFSET 5 #define PHY_MODE_MASK (7 << PHY_MODE_OFFSET) #define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET) @@ -73,11 +72,9 @@ enum { #define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET) #define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET) -#define COMPHY_RESERVED_REG 0x0E -#define PHYCTRL_FRM_PIN_BIT BIT(13) - -#define COMPHY_LOOPBACK_REG0 0x23 -#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit)) +#define COMPHY_DIG_LOOPBACK_EN 0x23 +#define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \ + PHY_SHFT(unit)) #define SEL_DATA_WIDTH_OFFSET 10 #define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET) #define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET) @@ -85,80 +82,71 @@ enum { #define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET) #define PLL_READY_TX_BIT BIT(4) -#define COMPHY_SYNC_PATTERN_REG 0x24 -#define SYNC_PATTERN_REG_ADDR(unit) (COMPHY_SYNC_PATTERN_REG * \ - PHY_SHFT(unit)) +#define COMPHY_SYNC_PATTERN 0x24 +#define SYNC_PATTERN_ADDR(unit) (COMPHY_SYNC_PATTERN * PHY_SHFT(unit)) #define TXD_INVERT_BIT BIT(10) #define RXD_INVERT_BIT BIT(11) -#define COMPHY_SYNC_MASK_GEN_REG 0x25 +#define COMPHY_SYNC_MASK_GEN 0x25 #define PHY_GEN_MAX_OFFSET 10 #define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET) -#define PHY_GEN_USB3_5G (1 << PHY_GEN_MAX_OFFSET) +#define PHY_GEN_MAX_USB3_5G (1 << PHY_GEN_MAX_OFFSET) -#define COMPHY_ISOLATION_CTRL_REG 0x26 -#define ISOLATION_CTRL_REG_ADDR(unit) (COMPHY_ISOLATION_CTRL_REG * \ - PHY_SHFT(unit)) +#define COMPHY_ISOLATION_CTRL 0x26 +#define ISOLATION_CTRL_ADDR(unit) (COMPHY_ISOLATION_REG * PHY_SHFT(unit)) #define PHY_ISOLATE_MODE BIT(15) -#define COMPHY_MISC_REG0_ADDR 0x4F -#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit)) +#define COMPHY_GEN2_SET2 0x3e +#define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit)) +#define GS2_TX_SSC_AMP_VALUE_20 BIT(14) +#define GS2_TX_SSC_AMP_OFF 9 +#define GS2_TX_SSC_AMP_LEN 7 +#define GS2_TX_SSC_AMP_MASK (((1 << GS2_TX_SSC_AMP_LEN) - 1) << \ + GS2_TX_SSC_AMP_OFF) +#define GS2_VREG_RXTX_MAS_ISET_OFF 7 +#define GS2_VREG_RXTX_MAS_ISET_60U (0 << GS2_VREG_RXTX_MAS_ISET_OFF) +#define GS2_VREG_RXTX_MAS_ISET_80U (1 << GS2_VREG_RXTX_MAS_ISET_OFF) +#define GS2_VREG_RXTX_MAS_ISET_100U (2 << GS2_VREG_RXTX_MAS_ISET_OFF) +#define GS2_VREG_RXTX_MAS_ISET_120U (3 << GS2_VREG_RXTX_MAS_ISET_OFF) +#define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8)) +#define GS2_RSVD_6_0_OFF 0 +#define GS2_RSVD_6_0_LEN 7 +#define GS2_RSVD_6_0_MASK (((1 << GS2_RSVD_6_0_LEN) - 1) << \ + GS2_RSVD_6_0_OFF) + +#define COMPHY_GEN3_SET2 0x3f +#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit)) + +#define COMPHY_IDLE_SYNC_EN 0x48 +#define IDLE_SYNC_EN_ADDR(unit) (COMPHY_IDLE_SYNC_EN * PHY_SHFT(unit)) +#define IDLE_SYNC_EN BIT(12) +#define IDLE_SYNC_EN_DEFAULT_VALUE 0x60 + +#define COMPHY_MISC_CTRL0 0x4F +#define MISC_CTRL0_ADDR(unit) (COMPHY_MISC_CTRL0 * PHY_SHFT(unit)) #define CLK100M_125M_EN BIT(4) #define TXDCLK_2X_SEL BIT(6) #define CLK500M_EN BIT(7) #define PHY_REF_CLK_SEL BIT(10) -#define MISC_REG0_DEFAULT_VALUE 0xA00D - -#define COMPHY_REG_GEN2_SET_2 0x3e -#define GEN2_SETTING_2_ADDR(unit) (COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit)) -#define G2_TX_SSC_AMP_VALUE_20 BIT(14) -#define G2_TX_SSC_AMP_OFF 9 -#define G2_TX_SSC_AMP_LEN 7 -#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \ - G2_TX_SSC_AMP_OFF) - -#define COMPHY_REG_GEN2_SET_3 0x3f -#define GEN2_SETTING_3_ADDR(unit) (COMPHY_REG_GEN2_SET_3 * PHY_SHFT(unit)) -#define G3_TX_SSC_AMP_OFF 9 -#define G3_TX_SSC_AMP_LEN 7 -#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \ - G2_TX_SSC_AMP_OFF) -#define G3_VREG_RXTX_MAS_ISET_OFF 7 -#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF) -#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF) -#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF) -#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF) -#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8)) -#define RSVD_PH03FH_6_0_OFF 0 -#define RSVD_PH03FH_6_0_LEN 7 -#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \ - RSVD_PH03FH_6_0_OFF) - -#define COMPHY_REG_UNIT_CTRL_ADDR 0x48 -#define UNIT_CTRL_ADDR(unit) (COMPHY_REG_UNIT_CTRL_ADDR * \ - PHY_SHFT(unit)) -#define IDLE_SYNC_EN BIT(12) -#define UNIT_CTRL_DEFAULT_VALUE 0x60 +#define MISC_CTRL0_DEFAULT_VALUE 0xA00D -#define COMPHY_MISC_REG1_ADDR 0x73 -#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit)) +#define COMPHY_MISC_CTRL1 0x73 +#define MISC_CTRL1_ADDR(unit) (COMPHY_MISC_CTRL1 * PHY_SHFT(unit)) #define SEL_BITS_PCIE_FORCE BIT(15) -#define COMPHY_REG_GEN3_SETTINGS_3 0x112 -#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF -#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF +#define COMPHY_GEN2_SET3 0x112 +#define GS3_FFE_CAP_SEL_MASK 0xF +#define GS3_FFE_CAP_SEL_VALUE 0xF -#define COMPHY_REG_LANE_CFG0_ADDR 0x180 -#define LANE_CFG0_ADDR(unit) (COMPHY_REG_LANE_CFG0_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_LANE_CFG0 0x180 +#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit)) #define PRD_TXDEEMPH0_MASK BIT(0) #define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3)) #define PRD_TXSWING_MASK BIT(4) #define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8)) -#define COMPHY_REG_LANE_CFG1_ADDR 0x181 -#define LANE_CFG1_ADDR(unit) (COMPHY_REG_LANE_CFG1_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_LANE_CFG1 0x181 +#define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1 * PHY_SHFT(unit)) #define PRD_TXDEEMPH1_MASK BIT(15) #define USE_MAX_PLL_RATE_EN BIT(9) #define TX_DET_RX_MODE BIT(6) @@ -166,21 +154,17 @@ enum { #define GEN2_TX_DATA_DLY_DEFT (2 << 3) #define TX_ELEC_IDLE_MODE_EN BIT(0) -#define COMPHY_REG_LANE_STATUS1_ADDR 0x183 -#define LANE_STATUS1_ADDR(unit) (COMPHY_REG_LANE_STATUS1_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_LANE_STAT1 0x183 +#define LANE_STAT1_ADDR(unit) (COMPHY_LANE_STAT1 * PHY_SHFT(unit)) #define TXDCLK_PCLK_EN BIT(0) -#define COMPHY_REG_LANE_CFG4_ADDR 0x188 -#define LANE_CFG4_ADDR(unit) (COMPHY_REG_LANE_CFG4_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_LANE_CFG4 0x188 +#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit)) #define SPREAD_SPECTRUM_CLK_EN BIT(7) -#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR 0x1C1 -#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_RST_CLK_CTRL 0x1C1 +#define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit)) #define SOFT_RESET BIT(0) -#define MODE_REFDIV 0x30 #define MODE_CORE_CLK_FREQ_SEL BIT(9) #define MODE_PIPE_WIDTH_32 BIT(3) #define MODE_REFDIV_OFFSET 4 @@ -188,24 +172,21 @@ enum { #define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET) #define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET) -#define COMPHY_REG_TEST_MODE_CTRL_ADDR 0x1C2 -#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_REG_TEST_MODE_CTRL_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_TEST_MODE_CTRL 0x1C2 +#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit)) #define MODE_MARGIN_OVERRIDE BIT(2) -#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR 0x1C3 -#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_CLK_SRC_LO 0x1C3 +#define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit)) #define MODE_CLK_SRC BIT(0) #define BUNDLE_PERIOD_SEL BIT(1) -#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3)) +#define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3)) #define BUNDLE_SAMPLE_CTRL BIT(4) -#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7)) +#define PLL_READY_DLY_MASK (BIT(5) | BIT(6) | BIT(7)) #define CFG_SEL_20B BIT(15) -#define COMPHY_REG_PWR_MGM_TIM1_ADDR 0x1D0 -#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_REG_PWR_MGM_TIM1_ADDR * \ - PHY_SHFT(unit)) +#define COMPHY_PWR_MGM_TIM1 0x1D0 +#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1 * PHY_SHFT(unit)) #define CFG_PM_OSCCLK_WAIT_OFF 12 #define CFG_PM_OSCCLK_WAIT_LEN 4 #define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \ @@ -222,9 +203,18 @@ enum { #define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF) #define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF) +/* + * This register is not from PHY lane register space. It only exists in the + * indirect register space, before the actual PHY lane 2 registers. So the + * offset is absolute, not relative to SATAPHY_LANE2_REG_BASE_OFFSET. + * It is used only for SATA PHY initialization. + */ +#define COMPHY_RESERVED_REG 0x0E +#define PHYCTRL_FRM_PIN_BIT BIT(13) + /* SGMII */ #define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28) -#define PIN_PU_IVEREF_BIT BIT(1) +#define PIN_PU_IVREF_BIT BIT(1) #define PIN_RESET_CORE_BIT BIT(11) #define PIN_RESET_COMPHY_BIT BIT(12) #define PIN_PU_PLL_BIT BIT(16) @@ -237,11 +227,11 @@ enum { #define GEN_TX_SEL_MASK (0xF << GEN_TX_SEL_OFFSET) #define PHY_RX_INIT_BIT BIT(30) #define SD_SPEED_1_25_G 0x6 -#define SD_SPEED_2_5_G 0x8 +#define SD_SPEED_3_125_G 0x8 /* COMPHY status reg: - * lane0: PCIe/GbE0 PHY Status 1 - * lane1: USB3/GbE1 PHY Status 1 + * lane0: USB3/GbE1 PHY Status 1 + * lane1: PCIe/GbE0 PHY Status 1 */ #define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28) #define PHY_RX_INIT_DONE_BIT BIT(0) diff -pruN 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-common.h 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-common.h --- 2.6+dfsg-1/drivers/marvell/comphy/phy-comphy-common.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/marvell/comphy/phy-comphy-common.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2021 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -147,7 +147,7 @@ static inline void reg_set(uintptr_t add debug(": WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", addr, data, mask); debug("old value = 0x%x ==> ", mmio_read_32(addr)); - mmio_clrsetbits_32(addr, mask, data); + mmio_clrsetbits_32(addr, mask, data & mask); debug("new val 0x%x\n", mmio_read_32(addr)); } @@ -159,7 +159,7 @@ static inline void __unused reg_set16(ui debug(": WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ", addr, data, mask); debug("old value = 0x%x ==> ", mmio_read_16(addr)); - mmio_clrsetbits_16(addr, mask, data); + mmio_clrsetbits_16(addr, mask, data & mask); debug("new val 0x%x\n", mmio_read_16(addr)); } diff -pruN 2.6+dfsg-1/drivers/marvell/uart/a3700_console.S 2.7.0+dfsg-2/drivers/marvell/uart/a3700_console.S --- 2.6+dfsg-1/drivers/marvell/uart/a3700_console.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/marvell/uart/a3700_console.S 2022-06-01 15:02:46.000000000 +0000 @@ -34,7 +34,7 @@ * w1 - Uart clock in Hz * w2 - Baud rate * Out: return 1 on success - * Clobber list : x1, x2, x3 + * Clobber list : x1, x2, x3, x4 * ----------------------------------------------- */ func console_a3700_core_init @@ -44,24 +44,11 @@ func console_a3700_core_init cbz w1, init_fail cbz w2, init_fail - /* Program the baudrate */ - /* Divisor = Round(Uartclock / (16 * baudrate)) */ - lsl w2, w2, #4 - add w1, w1, w2, lsr #1 - udiv w2, w1, w2 - and w2, w2, #0x3ff /* clear all other bits to use default clock */ - - str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */ - - /* Set UART to default 16X scheme */ - mov w3, #0 - str w3, [x0, #UART_POSSR_REG] - /* * Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is * still not empty, TX FIFO will reset by all means. */ - mov w1, #30 /* max time out 30 * 100 us */ + mov w4, #30 /* max time out 30 * 100 us */ 2: /* Check whether TX (THR and TSR) is empty */ ldr w3, [x0, #UART_STATUS_REG] @@ -70,30 +57,51 @@ func console_a3700_core_init b.ne 4f /* Delay */ - mov w2, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */ + mov w3, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */ 3: - sub w2, w2, #1 - cmp w2, #0 + sub w3, w3, #1 + cmp w3, #0 b.ne 3b /* Check whether wait timeout expired */ - sub w1, w1, #1 - cmp w1, #0 + sub w4, w4, #1 + cmp w4, #0 b.ne 2b 4: + /* Reset UART via North Bridge Peripheral */ + mov_imm x4, MVEBU_NB_RESET_REG + ldr w3, [x4] + bic w3, w3, #MVEBU_NB_RESET_UART_N + str w3, [x4] + orr w3, w3, #MVEBU_NB_RESET_UART_N + str w3, [x4] + /* Reset FIFO */ mov w3, #UART_CTRL_RXFIFO_RESET orr w3, w3, #UART_CTRL_TXFIFO_RESET str w3, [x0, #UART_CTRL_REG] /* Delay */ - mov w2, #2000 + mov w3, #2000 1: - sub w2, w2, #1 - cmp w2, #0 + sub w3, w3, #1 + cmp w3, #0 b.ne 1b + /* Program the baudrate */ + /* Divisor = Round(Uartclock / (16 * baudrate)) */ + lsl w2, w2, #4 + add w1, w1, w2, lsr #1 + udiv w2, w1, w2 + and w2, w2, #0x3ff /* clear all other bits to use default clock */ + + str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */ + + /* Set UART to default 16X scheme */ + mov w3, #0 + str w3, [x0, #UART_POSSR_REG] + /* No Parity, 1 Stop */ mov w3, #0 str w3, [x0, #UART_CTRL_REG] @@ -118,7 +126,7 @@ endfunc console_a3700_core_init * w2 - Baud rate * x3 - pointer to empty console_t struct * Out: return 1 on success, 0 on error - * Clobber list : x0, x1, x2, x6, x7, x14 + * Clobber list : x0, x1, x2, x3, x4, x6, x7, x14 * ----------------------------------------------- */ func console_a3700_register diff -pruN 2.6+dfsg-1/drivers/measured_boot/event_log/event_log.c 2.7.0+dfsg-2/drivers/measured_boot/event_log/event_log.c --- 2.6+dfsg-1/drivers/measured_boot/event_log/event_log.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/measured_boot/event_log/event_log.c 2022-06-01 15:02:46.000000000 +0000 @@ -13,10 +13,19 @@ #include #include #include -#include #include +#if TPM_ALG_ID == TPM_ALG_SHA512 +#define CRYPTO_MD_ID CRYPTO_MD_SHA512 +#elif TPM_ALG_ID == TPM_ALG_SHA384 +#define CRYPTO_MD_ID CRYPTO_MD_SHA384 +#elif TPM_ALG_ID == TPM_ALG_SHA256 +#define CRYPTO_MD_ID CRYPTO_MD_SHA256 +#else +# error Invalid TPM algorithm. +#endif /* TPM_ALG_ID */ + /* Running Event Log Pointer */ static uint8_t *log_ptr; @@ -245,20 +254,20 @@ void event_log_write_header(void) int event_log_measure_and_record(uintptr_t data_base, uint32_t data_size, uint32_t data_id) { - unsigned char hash_data[MBEDTLS_MD_MAX_SIZE]; + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; int rc; const event_log_metadata_t *metadata_ptr = plat_metadata_ptr; /* Get the metadata associated with this image. */ - while ((metadata_ptr->id != INVALID_ID) && + while ((metadata_ptr->id != EVLOG_INVALID_ID) && (metadata_ptr->id != data_id)) { metadata_ptr++; } - assert(metadata_ptr->id != INVALID_ID); + assert(metadata_ptr->id != EVLOG_INVALID_ID); /* Calculate hash */ - rc = crypto_mod_calc_hash((unsigned int)MBEDTLS_MD_ID, - (void *)data_base, data_size, hash_data); + rc = crypto_mod_calc_hash(CRYPTO_MD_ID, + (void *)data_base, data_size, hash_data); if (rc != 0) { return rc; } diff -pruN 2.6+dfsg-1/drivers/measured_boot/event_log/event_log.mk 2.7.0+dfsg-2/drivers/measured_boot/event_log/event_log.mk --- 2.6+dfsg-1/drivers/measured_boot/event_log/event_log.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/measured_boot/event_log/event_log.mk 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2021, Arm Limited. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -12,39 +12,25 @@ EVENT_LOG_LEVEL ?= 40 TPM_HASH_ALG := sha256 ifeq (${TPM_HASH_ALG}, sha512) - MBEDTLS_MD_ID := MBEDTLS_MD_SHA512 TPM_ALG_ID := TPM_ALG_SHA512 TCG_DIGEST_SIZE := 64U else ifeq (${TPM_HASH_ALG}, sha384) - MBEDTLS_MD_ID := MBEDTLS_MD_SHA384 TPM_ALG_ID := TPM_ALG_SHA384 TCG_DIGEST_SIZE := 48U else - MBEDTLS_MD_ID := MBEDTLS_MD_SHA256 TPM_ALG_ID := TPM_ALG_SHA256 TCG_DIGEST_SIZE := 32U -endif +endif #TPM_HASH_ALG - -# Set definitions for mbed TLS library and Measured Boot driver +# Set definitions for Measured Boot driver. $(eval $(call add_defines,\ $(sort \ - MBEDTLS_MD_ID \ TPM_ALG_ID \ TCG_DIGEST_SIZE \ EVENT_LOG_LEVEL \ ))) -ifeq (${HASH_ALG}, sha256) - ifneq (${TPM_HASH_ALG}, sha256) - $(eval $(call add_define,MBEDTLS_SHA512_C)) - endif -endif - -MEASURED_BOOT_SRC_DIR := drivers/measured_boot/event_log/ - -MEASURED_BOOT_SOURCES := ${MEASURED_BOOT_SRC_DIR}event_log.c \ - ${MEASURED_BOOT_SRC_DIR}event_print.c +EVENT_LOG_SRC_DIR := drivers/measured_boot/event_log/ -BL2_SOURCES += ${MEASURED_BOOT_SOURCES} -BL1_SOURCES += ${MEASURED_BOOT_SOURCES} +EVENT_LOG_SOURCES := ${EVENT_LOG_SRC_DIR}event_log.c \ + ${EVENT_LOG_SRC_DIR}event_print.c diff -pruN 2.6+dfsg-1/drivers/measured_boot/rss/rss_measured_boot.c 2.7.0+dfsg-2/drivers/measured_boot/rss/rss_measured_boot.c --- 2.6+dfsg-1/drivers/measured_boot/rss/rss_measured_boot.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/measured_boot/rss/rss_measured_boot.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define MBOOT_ALG_SHA512 0 +#define MBOOT_ALG_SHA384 1 +#define MBOOT_ALG_SHA256 2 + +#if MBOOT_ALG_ID == MBOOT_ALG_SHA512 +#define CRYPTO_MD_ID CRYPTO_MD_SHA512 +#define PSA_CRYPTO_MD_ID PSA_ALG_SHA_512 +#elif MBOOT_ALG_ID == MBOOT_ALG_SHA384 +#define CRYPTO_MD_ID CRYPTO_MD_SHA384 +#define PSA_CRYPTO_MD_ID PSA_ALG_SHA_384 +#elif MBOOT_ALG_ID == MBOOT_ALG_SHA256 +#define CRYPTO_MD_ID CRYPTO_MD_SHA256 +#define PSA_CRYPTO_MD_ID PSA_ALG_SHA_256 +#else +# error Invalid Measured Boot algorithm. +#endif /* MBOOT_ALG_ID */ + +/* Pointer to struct rss_mboot_metadata */ +static struct rss_mboot_metadata *plat_metadata_ptr; + +/* Functions' declarations */ +void rss_measured_boot_init(void) +{ + /* At this point it is expected that communication channel over MHU + * is already initialised by platform init. + */ + + /* Get pointer to platform's struct rss_mboot_metadata structure */ + plat_metadata_ptr = plat_rss_mboot_get_metadata(); + assert(plat_metadata_ptr != NULL); +} + +int rss_mboot_measure_and_record(uintptr_t data_base, uint32_t data_size, + uint32_t data_id) +{ + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; + int rc; + psa_status_t ret; + const struct rss_mboot_metadata *metadata_ptr = plat_metadata_ptr; + + /* Get the metadata associated with this image. */ + while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) && + (metadata_ptr->id != data_id)) { + metadata_ptr++; + } + + /* If image is not present in metadata array then skip */ + if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) { + return 0; + } + + /* Calculate hash */ + rc = crypto_mod_calc_hash(CRYPTO_MD_ID, + (void *)data_base, data_size, hash_data); + if (rc != 0) { + return rc; + } + + ret = rss_measured_boot_extend_measurement( + metadata_ptr->slot, + metadata_ptr->signer_id, + metadata_ptr->signer_id_size, + metadata_ptr->version, + metadata_ptr->version_size, + PSA_CRYPTO_MD_ID, + metadata_ptr->sw_type, + metadata_ptr->sw_type_size, + hash_data, + MBOOT_DIGEST_SIZE, + metadata_ptr->lock_measurement); + if (ret != PSA_SUCCESS) { + return ret; + } + + return 0; +} + +int rss_mboot_set_signer_id(unsigned int img_id, + const void *pk_ptr, + size_t pk_len) +{ + unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; + struct rss_mboot_metadata *metadata_ptr = plat_metadata_ptr; + int rc; + + /* Get the metadata associated with this image. */ + while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) && + (metadata_ptr->id != img_id)) { + metadata_ptr++; + } + + /* If image is not present in metadata array then skip */ + if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) { + return 0; + } + + /* Calculate public key hash */ + rc = crypto_mod_calc_hash(CRYPTO_MD_ID, (void *)pk_ptr, + pk_len, hash_data); + if (rc != 0) { + return rc; + } + + /* Update metadata struct with the received signer_id */ + (void)memcpy(metadata_ptr->signer_id, hash_data, MBOOT_DIGEST_SIZE); + metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE; + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/measured_boot/rss/rss_measured_boot.mk 2.7.0+dfsg-2/drivers/measured_boot/rss/rss_measured_boot.mk --- 2.6+dfsg-1/drivers/measured_boot/rss/rss_measured_boot.mk 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/measured_boot/rss/rss_measured_boot.mk 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,35 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Hash algorithm for measured boot +# SHA-256 (or stronger) is required. +# TODO: The measurement algorithm incorrectly suggests that the TPM backend +# is used which may not be the case. It is currently being worked on and +# soon TPM_HASH_ALG will be replaced by a more generic name. +TPM_HASH_ALG := sha256 + +ifeq (${TPM_HASH_ALG}, sha512) + MBOOT_ALG_ID := MBOOT_ALG_SHA512 + MBOOT_DIGEST_SIZE := 64U +else ifeq (${TPM_HASH_ALG}, sha384) + MBOOT_ALG_ID := MBOOT_ALG_SHA384 + MBOOT_DIGEST_SIZE := 48U +else + MBOOT_ALG_ID := MBOOT_ALG_SHA256 + MBOOT_DIGEST_SIZE := 32U +endif #TPM_HASH_ALG + +# Set definitions for Measured Boot driver. +$(eval $(call add_defines,\ + $(sort \ + MBOOT_ALG_ID \ + MBOOT_DIGEST_SIZE \ + MBOOT_RSS_BACKEND \ +))) + +MEASURED_BOOT_SRC_DIR := drivers/measured_boot/rss/ + +MEASURED_BOOT_SOURCES += ${MEASURED_BOOT_SRC_DIR}rss_measured_boot.c diff -pruN 2.6+dfsg-1/drivers/mtd/nand/raw_nand.c 2.7.0+dfsg-2/drivers/mtd/nand/raw_nand.c --- 2.6+dfsg-1/drivers/mtd/nand/raw_nand.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/mtd/nand/raw_nand.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,13 +8,13 @@ #include #include -#include - #include #include #include #include +#include + #define ONFI_SIGNATURE_ADDR 0x20U /* CRC calculation */ @@ -24,9 +24,6 @@ /* Status register */ #define NAND_STATUS_READY BIT(6) -#define SZ_128M 0x08000000U -#define SZ_512 0x200U - static struct rawnand_device rawnand_dev; #pragma weak plat_get_raw_nand_data diff -pruN 2.6+dfsg-1/drivers/mtd/nand/spi_nand.c 2.7.0+dfsg-2/drivers/mtd/nand/spi_nand.c --- 2.6+dfsg-1/drivers/mtd/nand/spi_nand.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/mtd/nand/spi_nand.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,13 +8,13 @@ #include #include -#include - #include #include #include #include +#include + #define SPI_NAND_MAX_ID_LEN 4U #define DELAY_US_400MS 400000U #define MACRONIX_ID 0xC2U @@ -246,7 +246,7 @@ static int spi_nand_mtd_block_is_bad(uns if ((bbm_marker[0] != GENMASK_32(7, 0)) || (bbm_marker[1] != GENMASK_32(7, 0))) { - WARN("Block %i is bad\n", block); + WARN("Block %u is bad\n", block); return 1; } @@ -312,7 +312,7 @@ int spi_nand_init(unsigned long long *si VERBOSE("SPI_NAND Detected ID 0x%x\n", id[1]); - VERBOSE("Page size %i, Block size %i, size %lli\n", + VERBOSE("Page size %u, Block size %u, size %llu\n", spinand_dev.nand_dev->page_size, spinand_dev.nand_dev->block_size, spinand_dev.nand_dev->size); diff -pruN 2.6+dfsg-1/drivers/mtd/nor/spi_nor.c 2.7.0+dfsg-2/drivers/mtd/nor/spi_nor.c --- 2.6+dfsg-1/drivers/mtd/nor/spi_nor.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/mtd/nor/spi_nor.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -284,7 +284,7 @@ int spi_nor_read(unsigned int offset, ui nor_dev.read_op.addr.val = offset; nor_dev.read_op.data.buf = (void *)buffer; - VERBOSE("%s offset %i length %zu\n", __func__, offset, length); + VERBOSE("%s offset %u length %zu\n", __func__, offset, length); while (length != 0U) { if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) { diff -pruN 2.6+dfsg-1/drivers/mtd/spi-mem/spi_mem.c 2.7.0+dfsg-2/drivers/mtd/spi-mem/spi_mem.c --- 2.6+dfsg-1/drivers/mtd/spi-mem/spi_mem.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/mtd/spi-mem/spi_mem.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,10 +8,9 @@ #include #include -#include - #include #include +#include #define SPI_MEM_DEFAULT_SPEED_HZ 100000U @@ -258,7 +257,7 @@ int spi_mem_init_slave(void *fdt, int bu mode |= SPI_TX_QUAD; break; default: - WARN("spi-tx-bus-width %d not supported\n", + WARN("spi-tx-bus-width %u not supported\n", fdt32_to_cpu(*cuint)); return -EINVAL; } @@ -276,7 +275,7 @@ int spi_mem_init_slave(void *fdt, int bu mode |= SPI_RX_QUAD; break; default: - WARN("spi-rx-bus-width %d not supported\n", + WARN("spi-rx-bus-width %u not supported\n", fdt32_to_cpu(*cuint)); return -EINVAL; } diff -pruN 2.6+dfsg-1/drivers/nxp/crypto/caam/src/jobdesc.c 2.7.0+dfsg-2/drivers/nxp/crypto/caam/src/jobdesc.c --- 2.6+dfsg-1/drivers/nxp/crypto/caam/src/jobdesc.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/crypto/caam/src/jobdesc.c 2022-06-01 15:02:46.000000000 +0000 @@ -60,8 +60,8 @@ void desc_add_ptr(uint32_t *desc, phys_a #ifdef CONFIG_PHYS_64BIT ptr_addr_t *ptr_addr = (ptr_addr_t *) last; - ptr_addr->m_halves.high = PHYS_ADDR_HI(ptr); - ptr_addr->m_halves.low = PHYS_ADDR_LO(ptr); + ptr_addr->high = PHYS_ADDR_HI(ptr); + ptr_addr->low = PHYS_ADDR_LO(ptr); #else *last = ptr; #endif diff -pruN 2.6+dfsg-1/drivers/nxp/dcfg/dcfg.c 2.7.0+dfsg-2/drivers/nxp/dcfg/dcfg.c --- 2.6+dfsg-1/drivers/nxp/dcfg/dcfg.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/dcfg/dcfg.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright 2020-2021 NXP + * Copyright 2020-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -74,14 +74,11 @@ const devdisr5_info_t *get_devdisr5_info reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET); -#if defined(CONFIG_CHASSIS_3_2) devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; +#if defined(CONFIG_CHASSIS_3_2) devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1; - devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; -#elif defined(CONFIG_CHASSIS_2) - devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1; - devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; #endif + devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1; devdisr5_info.is_populated = true; return (const devdisr5_info_t *) &devdisr5_info; diff -pruN 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/ddr.mk 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/ddr.mk --- 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/ddr.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/ddr.mk 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ # -# Copyright 2021 NXP +# Copyright 2021-2022 NXP # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,6 +19,10 @@ ifeq (${ERRATA_DDR_A050450}, 1) $(eval $(call add_define,ERRATA_DDR_A050450)) endif +ifeq (${ERRATA_DDR_A050958}, 1) +$(eval $(call add_define,ERRATA_DDR_A050958)) +endif + endif ifeq ($(PLAT_DDR_PHY), PHY_GEN1) diff -pruN 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/dimm.c 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/dimm.c --- 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/dimm.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/dimm.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2021-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -194,7 +194,7 @@ int cal_dimm_params(const struct ddr4_sp case DDR4_SPD_MINI_RDIMM: case DDR4_SPD_72B_SO_RDIMM: pdimm->rdimm = 1; - pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x8f; + pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x9f; if ((spd->mod_section.registered.reg_map & 0x1) != 0) { pdimm->mirrored_dimm = 1; } @@ -223,7 +223,7 @@ int cal_dimm_params(const struct ddr4_sp case DDR4_SPD_72B_SO_UDIMM: case DDR4_SPD_16B_SO_DIMM: case DDR4_SPD_32B_SO_DIMM: - pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x8f; + pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x9f; if ((spd->mod_section.unbuffered.addr_mapping & 0x1) != 0) { pdimm->mirrored_dimm = 1; } diff -pruN 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/utility.c 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/utility.c --- 2.6+dfsg-1/drivers/nxp/ddr/nxp-ddr/utility.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ddr/nxp-ddr/utility.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2021-2022 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,10 @@ #define CCN_HN_F_SAM_NODEID_DDR0 0x4 #define CCN_HN_F_SAM_NODEID_DDR1 0xe #elif defined(NXP_HAS_CCN508) -#define CCN_HN_F_SAM_NODEID_DDR0 0x8 -#define CCN_HN_F_SAM_NODEID_DDR1 0x18 +#define CCN_HN_F_SAM_NODEID_DDR0_0 0x3 +#define CCN_HN_F_SAM_NODEID_DDR0_1 0x8 +#define CCN_HN_F_SAM_NODEID_DDR1_0 0x13 +#define CCN_HN_F_SAM_NODEID_DDR1_1 0x18 #endif unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num) @@ -166,10 +168,21 @@ int disable_unused_ddrc(struct ddr_info for (i = 0; i < num_hnf_nodes; i++) { val = mmio_read_64((uintptr_t)hnf_sam_ctrl); +#ifdef NXP_HAS_CCN504 nodeid = disable_ddrc == 1 ? CCN_HN_F_SAM_NODEID_DDR1 : - (disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 : - (i < 4 ? CCN_HN_F_SAM_NODEID_DDR0 - : CCN_HN_F_SAM_NODEID_DDR1)); + (disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 : + 0x0); /*Failure condition. never hit */ +#elif defined(NXP_HAS_CCN508) + if (disable_ddrc == 1) { + nodeid = (i < 2 || i >= 6) ? CCN_HN_F_SAM_NODEID_DDR1_1 : + CCN_HN_F_SAM_NODEID_DDR1_0; + } else if (disable_ddrc == 2) { + nodeid = (i < 2 || i >= 6) ? CCN_HN_F_SAM_NODEID_DDR0_0 : + CCN_HN_F_SAM_NODEID_DDR0_1; + } else { + nodeid = 0; /* Failure condition. never hit */ + } +#endif if (nodeid != (val & CCN_HN_F_SAM_NODEID_MASK)) { debug("Setting HN-F node %d\n", i); debug("nodeid = 0x%x\n", nodeid); diff -pruN 2.6+dfsg-1/drivers/nxp/ddr/phy-gen2/phy.c 2.7.0+dfsg-2/drivers/nxp/ddr/phy-gen2/phy.c --- 2.6+dfsg-1/drivers/nxp/ddr/phy-gen2/phy.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ddr/phy-gen2/phy.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright 2021 NXP + * Copyright 2021-2022 NXP * SPDX-License-Identifier: BSD-3-Clause * */ @@ -1673,6 +1673,10 @@ static void prog_dq_dqs_rcv_cntrl(uint16 int sel_analog_vref = 1; uint32_t addr; +#ifdef ERRATA_DDR_A050958 + gain_curr_adj_defval = 0x1f; +#endif + dq_dqs_rcv_cntrl = gain_curr_adj_defval << csr_gain_curr_adj_lsb | major_mode_dbyte << csr_major_mode_dbyte_lsb | dfe_ctrl_defval << csr_dfe_ctrl_lsb | @@ -2212,10 +2216,14 @@ static int load_fw(uint16_t **phy_ptr, size = PHY_GEN2_MAX_IMAGE_SIZE; image_buf = (uintptr_t)phy_gen2_fw_img_buf; - mmap_add_dynamic_region(phy_gen2_fw_img_buf, + ret = mmap_add_dynamic_region(phy_gen2_fw_img_buf, phy_gen2_fw_img_buf, PHY_GEN2_MAX_IMAGE_SIZE, MT_MEMORY | MT_RW | MT_SECURE); + if (ret != 0) { + ERROR("Failed to add dynamic memory region.\n"); + return ret; + } ret = img_loadr(imem_id, &image_buf, &size); if (ret != 0) { ERROR("Failed to load %d firmware.\n", imem_id); diff -pruN 2.6+dfsg-1/drivers/nxp/drivers.mk 2.7.0+dfsg-2/drivers/nxp/drivers.mk --- 2.6+dfsg-1/drivers/nxp/drivers.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/drivers.mk 2022-06-01 15:02:46.000000000 +0000 @@ -89,3 +89,11 @@ endif ifeq (${GPIO_NEEDED},yes) include ${PLAT_DRIVERS_PATH}/gpio/gpio.mk endif + +ifeq (${IFC_NOR_NEEDED},yes) +include ${PLAT_DRIVERS_PATH}/ifc/nor/ifc_nor.mk +endif + +ifeq (${IFC_NAND_NEEDED},yes) +include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk +endif diff -pruN 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc.h 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc.h --- 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc.h 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc.h 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,329 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IFC_H +#define IFC_H + +#include + +#include + +#define NXP_IFC_RUN_TIME_ADDR U(0x1000) + +/* CPSR - Chip Select Property Register Offset */ +#define EXT_CSPR(n) (U(0x000C) + (n * 0xC)) +#define CSPR(n) (U(0x0010) + (n * 0xC)) +#define CSOR(n) (U(0x0130) + (n * 0xC)) +#define EXT_CSOR(n) (U(0x0134) + (n * 0xC)) +#define IFC_AMASK_CS0 U(0x00A0) + +/* NAND specific Registers Offset */ +#define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000)) +#define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014)) + +#define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C)) +#define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C)) +#define COL0 (NXP_IFC_RUN_TIME_ADDR + U(0x0044)) +#define COL1 (NXP_IFC_RUN_TIME_ADDR + U(0x0054)) + +#define NAND_BC (NXP_IFC_RUN_TIME_ADDR + U(0x0108)) +#define NAND_FIR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0110)) +#define NAND_FIR1 (NXP_IFC_RUN_TIME_ADDR + U(0x0114)) +#define NAND_FIR2 (NXP_IFC_RUN_TIME_ADDR + U(0x0118)) +#define NAND_CSEL (NXP_IFC_RUN_TIME_ADDR + U(0x015C)) +#define NANDSEQ_STRT (NXP_IFC_RUN_TIME_ADDR + U(0x0164)) +#define NAND_EVTER_STAT (NXP_IFC_RUN_TIME_ADDR + U(0x016C)) +#define NAND_AUTOBOOT_TRGR (NXP_IFC_RUN_TIME_ADDR + U(0x0284)) + +/* Size of SRAM Buffer */ +#define CSPR_PS U(0x00000180) +#define CSPR_PS_SHIFT 7 +#define CSPR_PS_8 0x1 // Port Size 8 bit +#define CSPR_PS_16 0x2 // Port Size 16 bit +#define CSPR_PS_32 0x3 // Port Size 32 bit + +/* Chip Select Option Register NAND Machine */ +#define CSOR_NAND_PGS U(0x00380000) +#define CSOR_NAND_PGS_SHIFT 19 +#define CSOR_NAND_PGS_512 U(0x00000000) +#define CSOR_NAND_PGS_2K U(0x00080000) +#define CSOR_NAND_PGS_4K U(0x00100000) +#define CSOR_NAND_PGS_8K U(0x00180000) +#define CSOR_NAND_PGS_16K U(0x00200000) + + +#define CSOR_NAND_PB U(0x00000700) +#define CSOR_NAND_PB_32 U(0x00000000) +#define CSOR_NAND_PB_64 U(0x00000100) +#define CSOR_NAND_PB_128 U(0x00000200) +#define CSOR_NAND_PB_256 U(0x00000300) +#define CSOR_NAND_PB_512 U(0x00000400) +#define CSOR_NAND_PB_1024 U(0x00000500) +#define CSOR_NAND_PB_2048 U(0x00000600) +#define CSOR_NAND_PPB_32 32 +#define CSOR_NAND_PPB_64 64 +#define CSOR_NAND_PPB_128 128 +#define CSOR_NAND_PPB_256 256 +#define CSOR_NAND_PPB_512 512 +#define CSOR_NAND_PPB_1024 1024 +#define CSOR_NAND_PPB_2048 2048 + +/* NAND Chip select register */ +#define NAND_CSEL_SHIFT 26 +#define NAND_COL_MS_SHIFT 31 + +/* FCR - Flash Command Register */ +#define FCR_CMD0 U(0xFF000000) +#define FCR_CMD0_SHIFT 24 +#define FCR_CMD1 U(0x00FF0000) +#define FCR_CMD1_SHIFT 16 +#define FCR_CMD2 U(0x0000FF00) +#define FCR_CMD2_SHIFT 8 +#define FCR_CMD3 U(0x000000FF) +#define FCR_CMD3_SHIFT 0 + +/* FIR - Flash Instruction Register Opcode */ +#define FIR_OP0 U(0xFC000000) +#define FIR_OP0_SHIFT 26 +#define FIR_OP1 U(0x03F00000) +#define FIR_OP1_SHIFT 20 +#define FIR_OP2 U(0x000FC000) +#define FIR_OP2_SHIFT 14 +#define FIR_OP3 U(0x00003F00) +#define FIR_OP3_SHIFT 8 +#define FIR_OP4 U(0x000000FC) +#define FIR_OP4_SHIFT 2 +#define FIR_OP5 U(0xFC000000) +#define FIR_OP5_SHIFT 26 +#define FIR_OP6 U(0x03F00000) +#define FIR_OP6_SHIFT 20 + +/* Instruction Opcode - 6 bits */ +#define FIR_OP_NOP 0x00 +#define FIR_OP_CA0 0x01 /* Issue current column address */ +#define FIR_OP_CA1 0x02 /* Issue current column address */ +#define FIR_OP_RA0 0x05 /* Issue current column address */ +#define FIR_OP_RA1 0x06 /* Issue current column address */ +#define FIR_OP_CMD0 0x09 /* Issue command from FCR[CMD0] */ +#define FIR_OP_CMD1 0x0a /* Issue command from FCR[CMD1] */ +#define FIR_OP_CMD2 0x0b /* Issue command from FCR[CMD2] */ +#define FIR_OP_CMD3 0x0c /* Issue command from FCR[CMD3] */ +#define FIR_OP_CW0 0x11 /* Wait then issue FCR[CMD0] */ +#define FIR_OP_CW1 0x12 /* Wait then issue FCR[CMD1] */ +#define FIR_OP_CW2 0x13 /* Wait then issue FCR[CMD1] */ +#define FIR_OP_CW3 0x14 /* Wait then issue FCR[CMD1] */ +#define FIR_OP_WBCD 0x19 /* Wait then read FBCR bytes */ +#define FIR_OP_RBCD 0x1a /* Wait then read 1 or 2 bytes */ +#define FIR_OP_BTRD 0x1b /* Wait then read 1 or 2 bytes */ +#define FIR_OP_RDSTAT 0x1c /* Wait then read 1 or 2 bytes */ +#define FIR_OP_NWAIT 0x1d /* Wait then read 1 or 2 bytes */ +#define FIR_OP_WFR 0x1e /* Wait then read 1 or 2 bytes */ + +#define NAND_SEQ_STRT_FIR_STRT U(0x80000000) +#define NAND_SEQ_STRT_FIR_STRT_SHIFT 31 + +#define NAND_EVTER_STAT_FTOER U(0x08000000) +#define NAND_EVTER_STAT_WPER U(0x04000000) +#define NAND_EVTER_STAT_ECCER U(0x02000000) +#define NAND_EVTER_STAT_DQSER U(0x01000000) +#define NAND_EVTER_STAT_RCW_DN U(0x00008000) +#define NAND_EVTER_STAT_BOOT_DN U(0x00004000) +#define NAND_EVTER_STAT_RCW_DN U(0x00008000) +#define NAND_EVTER_STAT_OPC_DN U(0x80000000) +#define NAND_EVTER_STAT_BBI_SRCH_SEL U(0x00000800) +#define NCFGR_BOOT U(0x80000000) +#define NAND_AUTOBOOT_TRGR_RCW_LD U(0x80000000) +#define NAND_AUTOBOOT_TRGR_BOOT_LD U(0x20000000) + +/* ECC ERROR STATUS Registers */ +#define NAND_RCW_LD U(0x80000000) +#define NAND_BOOT_LD U(0x20000000) + +/*Other Temp Defines */ +/*256 bad Blocks supported */ +#define BBT_SIZE 256 + +/*Standard NAND flash commands */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_READOOB 0x50 + +/*Extended commands for large page devices */ +#define NAND_CMD_READSTART 0x30 + +#define NAND_TIMEOUT_MS 40 + +#define EMPTY_VAL_CHECK U(0xFFFFFFFF) +#define EMPTY_VAL 0xFF + + +#define MAIN 0 +#define SPARE 1 + +#define GOOD_BLK 1 +#define BAD_BLK 0 +#define DIV_2 2 + +#define ATTRIBUTE_PGSZ 0xa +#define ATTRIBUTE_PPB 0xb + +#define CSPR_PORT_SIZE_8 (0x1 << 7) +#define CSPR_PORT_SIZE_16 (0x2 << 7) +#define CSPR_PORT_SIZE_32 (0x3 << 7) + +/* NAND specific */ +#define RCW_SRC_NAND_PORT_MASK U(0x00000080) + +#define NAND_DEFAULT_CSPR U(0x00000053) +#define NAND_DEFAULT_CSOR U(0x0180C00C) +#define NAND_DEFAULT_EXT_CSPR U(0x00000000) +#define NAND_DEFAULT_EXT_CSOR U(0x00000000) +#define NAND_DEFAULT_FTIM0 U(0x181c0c10) +#define NAND_DEFAULT_FTIM1 U(0x5454141e) +#define NAND_DEFAULT_FTIM2 U(0x03808034) +#define NAND_DEFAULT_FTIM3 U(0x2c000000) + +#define NAND_CSOR_ECC_MODE_DISABLE U(0x00000000) +#define NAND_CSOR_ECC_MODE0 U(0x84000000) +#define NAND_CSOR_ECC_MODE1 U(0x94000000) +#define NAND_CSOR_ECC_MODE2 U(0xa4000000) +#define NAND_CSOR_ECC_MODE3 U(0xb4000000) +#define NAND_CSOR_PAGE_SIZE_2K (0x1 << 19) +#define NAND_CSOR_PAGE_SIZE_4K (0x2 << 19) +#define NAND_CSOR_PAGE_SIZE_8K (0x3 << 19) +#define NAND_CSOR_PAGE_SIZE_16K (0x4 << 19) +#define NAND_CSOR_PPB_64 (0x1 << 8) +#define NAND_CSOR_PPB_128 (0x2 << 8) +#define NAND_CSOR_PPB_256 (0x3 << 8) +#define NAND_CSOR_PPB_512 (0x4 << 8) + +/* BBI INDICATOR for NAND_2K(CFG_RCW_SRC[1]) for + * devices greater than 2K page size(CFG_RCW_SRC[3]) + */ +#define RCW_SRC_NAND_BBI_MASK U(0x00000008) +#define RCW_SRC_NAND_BBI_MASK_NAND_2K U(0x00000002) +#define NAND_BBI_ONFI_2K (0x1 << 1) +#define NAND_BBI_ONFI (0x1 << 3) + +#define RCW_SRC_NAND_PAGE_MASK U(0x00000070) +#define RCW_SRC_NAND_PAGE_MASK_NAND_2K U(0x0000000C) +#define NAND_2K_XXX 0x00 +#define NAND_2K_64 0x04 +#define NAND_2K_128 0x08 +#define NAND_4K_128 0x10 +#define NAND_4K_256 0x20 +#define NAND_4K_512 0x30 +#define NAND_8K_128 0x40 +#define NAND_8K_256 0x50 +#define NAND_8K_512 0x60 +#define NAND_16K_512 0x70 +#define BLOCK_LEN_2K 2048 + +#define RCW_SRC_NAND_ECC_MASK U(0x00000007) +#define RCW_SRC_NAND_ECC_MASK_NAND_2K U(0x00000001) +#define NAND_ECC_DISABLE 0x0 +#define NAND_ECC_4_520 0x1 +#define NAND_ECC_8_528 0x5 +#define NAND_ECC_24_1K 0x6 +#define NAND_ECC_40_1K 0x7 + +#define NAND_SPARE_2K U(0x00000040) +#define NAND_SPARE_4K_ECC_M0 U(0x00000080) +#define NAND_SPARE_4K_ECC_M1 U(0x000000D2) +#define NAND_SPARE_4K_ECC_M2 U(0x000000B0) +#define NAND_SPARE_4K_ECC_M3 U(0x00000120) +#define NAND_SPARE_8K_ECC_M0 U(0x00000088) +#define NAND_SPARE_8K_ECC_M1 U(0x00000108) +#define NAND_SPARE_8K_ECC_M2 U(0x00000158) +#define NAND_SPARE_8K_ECC_M3 U(0x00000238) +#define NAND_SPARE_16K_ECC_M0 U(0x00000108) +#define NAND_SPARE_16K_ECC_M1 U(0x00000208) +#define NAND_SPARE_16K_ECC_M2 U(0x000002A8) +#define NAND_SPARE_16K_ECC_M3 U(0x00000468) + +struct nand_info { + uintptr_t ifc_register_addr; + uintptr_t ifc_region_addr; + uint32_t page_size; + uint32_t port_size; + uint32_t blk_size; + uint32_t ppb; + uint32_t pi_width; /* Bits Required to index a page in block */ + uint32_t ral; + uint32_t ibr_flow; + uint32_t bbt[BBT_SIZE]; + uint32_t lgb; /* Last Good Block */ + uint32_t bbt_max; /* Total entries in bbt */ + uint32_t bzero_good; + uint8_t bbs; + uint8_t bad_marker_loc; + uint8_t onfi_dev_flag; + uint8_t init_time_boot_flag; + uint8_t *buf; +}; + +struct ifc_regs { + uint32_t ext_cspr; + uint32_t cspr; + uint32_t csor; + uint32_t ext_csor; +}; + +struct sec_nand_info { + uint32_t cspr_port_size; + uint32_t csor_ecc_mode; + uint32_t csor_page_size; + uint32_t csor_ppb; + uint32_t ext_csor_spare_size; + uint32_t onfi_flag; +}; + +struct sec_nor_info { + uint32_t cspr_port_size; + uint32_t csor_nor_mode; + uint32_t csor_adm_shift; + uint32_t port_size; + uint32_t addr_bits; +}; + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +#ifdef NXP_IFC_BE +#define nand_in32(a) bswap32(mmio_read_32((uintptr_t)a)) +#define nand_out32(a, v) mmio_write_32((uintptr_t)a, bswap32(v)) +#else +#define nand_in32(a) mmio_read_32((uintptr_t)a) +#define nand_out32(a, v) mmio_write_32((uintptr_t)a, v) +#endif + +/* Read Write on IFC registers */ +static inline void write_reg(struct nand_info *nand, uint32_t reg, uint32_t val) +{ + nand_out32(nand->ifc_register_addr + reg, val); +} + +static inline uint32_t read_reg(struct nand_info *nand, uint32_t reg) +{ + return nand_in32(nand->ifc_register_addr + reg); +} + +#endif /* IFC_H */ diff -pruN 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc_nand.c 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc_nand.c --- 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc_nand.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc_nand.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,658 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include "ifc.h" +#include +#include + +/* Private structure for NAND driver data */ +static struct nand_info nand_drv_data; + +static int update_bbt(uint32_t idx, uint32_t blk, uint32_t *updated, + struct nand_info *nand); + +static int nand_wait(struct nand_info *nand) +{ + int timeout = 1; + uint32_t neesr; + unsigned long start_time; + + start_time = get_timer_val(0); + + while (get_timer_val(start_time) < NAND_TIMEOUT_MS) { + /* clear the OPC event */ + neesr = read_reg(nand, NAND_EVTER_STAT); + if (neesr & NAND_EVTER_STAT_OPC_DN) { + write_reg(nand, NAND_EVTER_STAT, neesr); + timeout = 0; + + /* check for other errors */ + if (neesr & NAND_EVTER_STAT_FTOER) { + ERROR("%s NAND_EVTER_STAT_FTOER occurs\n", + __func__); + return -1; + } else if (neesr & NAND_EVTER_STAT_ECCER) { + ERROR("%s NAND_EVTER_STAT_ECCER occurs\n", + __func__); + return -1; + } else if (neesr & NAND_EVTER_STAT_DQSER) { + ERROR("%s NAND_EVTER_STAT_DQSER occurs\n", + __func__); + return -1; + } + + break; + } + } + + if (timeout) { + ERROR("%s ERROR_NAND_TIMEOUT occurs\n", __func__); + return -1; + } + + return 0; +} + +static uint32_t nand_get_port_size(struct nand_info *nand) +{ + uint32_t port_size = U(0); + uint32_t cs_reg; + uint32_t cur_cs; + + cur_cs = U(0); + cs_reg = CSPR(cur_cs); + port_size = (read_reg(nand, cs_reg) & CSPR_PS) >> CSPR_PS_SHIFT; + switch (port_size) { + case CSPR_PS_8: + port_size = U(8); + break; + case CSPR_PS_16: + port_size = U(16); + break; + case CSPR_PS_32: + port_size = U(32); + break; + default: + port_size = U(8); + } + + return port_size; +} + +static uint32_t nand_get_page_size(struct nand_info *nand) +{ + uint32_t pg_size; + uint32_t cs_reg; + uint32_t cur_cs; + + cur_cs = 0; + cs_reg = CSOR(cur_cs); + pg_size = read_reg(nand, cs_reg) & CSOR_NAND_PGS; + switch (pg_size) { + case CSOR_NAND_PGS_2K: + pg_size = U(2048); + break; + case CSOR_NAND_PGS_4K: + pg_size = U(4096); + break; + case CSOR_NAND_PGS_8K: + pg_size = U(8192); + break; + case CSOR_NAND_PGS_16K: + pg_size = U(16384); + break; + default: + pg_size = U(512); + } + + return pg_size; +} + +static uint32_t nand_get_pages_per_blk(struct nand_info *nand) +{ + uint32_t pages_per_blk; + uint32_t cs_reg; + uint32_t cur_cs; + + cur_cs = 0; + cs_reg = CSOR(cur_cs); + pages_per_blk = (read_reg(nand, cs_reg) & CSOR_NAND_PB); + switch (pages_per_blk) { + case CSOR_NAND_PB_32: + pages_per_blk = U(32); + break; + case CSOR_NAND_PB_64: + pages_per_blk = U(64); + break; + case CSOR_NAND_PB_128: + pages_per_blk = U(128); + break; + case CSOR_NAND_PB_256: + pages_per_blk = U(256); + break; + case CSOR_NAND_PB_512: + pages_per_blk = U(512); + break; + case CSOR_NAND_PB_1024: + pages_per_blk = U(1024); + break; + case CSOR_NAND_PB_2048: + pages_per_blk = U(2048); + break; + default: + pages_per_blk = U(0); + } + + return pages_per_blk; +} + +static uint32_t get_page_index_width(uint32_t ppb) +{ + switch (ppb) { + case CSOR_NAND_PPB_32: + return U(5); + case CSOR_NAND_PPB_64: + return U(6); + case CSOR_NAND_PPB_128: + return U(7); + case CSOR_NAND_PPB_256: + return U(8); + case CSOR_NAND_PPB_512: + return U(9); + case CSOR_NAND_PPB_1024: + return U(10); + case CSOR_NAND_PPB_2048: + return U(11); + default: + return U(5); + } +} + +static void nand_get_params(struct nand_info *nand) +{ + nand->port_size = nand_get_port_size(nand); + + nand->page_size = nand_get_page_size(nand); + + /* + * Set Bad marker Location for LP / SP + * Small Page : 8 Bit : 0x5 + * Small Page : 16 Bit : 0xa + * Large Page : 8 /16 Bit : 0x0 + */ + nand->bad_marker_loc = (nand->page_size == 512) ? + ((nand->port_size == 8) ? 0x5 : 0xa) : 0; + + /* check for the device is ONFI compliant or not */ + nand->onfi_dev_flag = + (read_reg(nand, NAND_EVTER_STAT) & NAND_EVTER_STAT_BBI_SRCH_SEL) + ? 1 : 0; + + /* NAND Blk serached count for incremental Bad block search cnt */ + nand->bbs = 0; + + /* pages per Block */ + nand->ppb = nand_get_pages_per_blk(nand); + + /* Blk size */ + nand->blk_size = nand->page_size * nand->ppb; + + /* get_page_index_width */ + nand->pi_width = get_page_index_width(nand->ppb); + + /* bad block table init */ + nand->lgb = 0; + nand->bbt_max = 0; + nand->bzero_good = 0; + memset(nand->bbt, EMPTY_VAL, BBT_SIZE * sizeof(nand->bbt[0])); +} + +static int nand_init(struct nand_info *nand) +{ + uint32_t ncfgr = 0; + + /* Get nand Parameters from IFC */ + nand_get_params(nand); + + /* Clear all errors */ + write_reg(nand, NAND_EVTER_STAT, U(0xffffffff)); + + /* + * Disable autoboot in NCFGR. Mapping will change from + * physical to logical for SRAM buffer + */ + ncfgr = read_reg(nand, NCFGR); + write_reg(nand, NCFGR, (ncfgr & ~NCFGR_BOOT)); + + return 0; +} + +static int nand_read_data( + uintptr_t ifc_region_addr, + uint32_t row_add, + uint32_t col_add, + uint32_t byte_cnt, + uint8_t *data, + uint32_t main_spare, + struct nand_info *nand) +{ + uint32_t page_size_add_bits = U(0); + uint32_t page_add_in_actual, page_add; + uintptr_t sram_addr_calc; + int ret; + uint32_t col_val; + + /* Programming MS bit to read from spare area.*/ + col_val = (main_spare << NAND_COL_MS_SHIFT) | col_add; + + write_reg(nand, NAND_BC, byte_cnt); + + write_reg(nand, ROW0, row_add); + write_reg(nand, COL0, col_val); + + /* Program FCR for small Page */ + if (nand->page_size == U(512)) { + if (byte_cnt == 0 || + (byte_cnt != 0 && main_spare == 0 && col_add <= 255)) { + write_reg(nand, NAND_FCR0, + (NAND_CMD_READ0 << FCR_CMD0_SHIFT)); + } else if (main_spare == 0) { + write_reg(nand, NAND_FCR0, + (NAND_CMD_READ1 << FCR_CMD0_SHIFT)); + } else { + write_reg(nand, NAND_FCR0, + (NAND_CMD_READOOB << FCR_CMD0_SHIFT)); + } + + } else { + /* Program FCR for Large Page */ + write_reg(nand, NAND_FCR0, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); + } + if (nand->page_size == U(512)) { + write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA0 << FIR_OP1_SHIFT) | + (FIR_OP_RA0 << FIR_OP2_SHIFT) | + (FIR_OP_BTRD << FIR_OP3_SHIFT) | + (FIR_OP_NOP << FIR_OP4_SHIFT))); + write_reg(nand, NAND_FIR1, U(0x00000000)); + } else { + write_reg(nand, NAND_FIR0, ((FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA0 << FIR_OP1_SHIFT) | + (FIR_OP_RA0 << FIR_OP2_SHIFT) | + (FIR_OP_CMD1 << FIR_OP3_SHIFT) | + (FIR_OP_BTRD << FIR_OP4_SHIFT))); + + write_reg(nand, NAND_FIR1, (FIR_OP_NOP << FIR_OP5_SHIFT)); + } + write_reg(nand, NANDSEQ_STRT, NAND_SEQ_STRT_FIR_STRT); + + ret = nand_wait(nand); + if (ret != 0) + return ret; + + /* calculate page_size_add_bits i.e bits + * in sram address corresponding to area + * within a page for sram + */ + if (nand->page_size == U(512)) + page_size_add_bits = U(10); + else if (nand->page_size == U(2048)) + page_size_add_bits = U(12); + else if (nand->page_size == U(4096)) + page_size_add_bits = U(13); + else if (nand->page_size == U(8192)) + page_size_add_bits = U(14); + else if (nand->page_size == U(16384)) + page_size_add_bits = U(15); + + page_add = row_add; + + page_add_in_actual = (page_add << page_size_add_bits) & U(0x0000FFFF); + + if (byte_cnt == 0) + col_add = U(0); + + /* Calculate SRAM address for main and spare area */ + if (main_spare == 0) + sram_addr_calc = ifc_region_addr | page_add_in_actual | col_add; + else + sram_addr_calc = ifc_region_addr | page_add_in_actual | + (col_add + nand->page_size); + + /* Depending Byte_count copy full page or partial page from SRAM */ + if (byte_cnt == 0) + memcpy(data, (void *)sram_addr_calc, + nand->page_size); + else + memcpy(data, (void *)sram_addr_calc, byte_cnt); + + return 0; +} + +static int nand_read(struct nand_info *nand, int32_t src_addr, + uintptr_t dst, uint32_t size) +{ + uint32_t log_blk = U(0); + uint32_t pg_no = U(0); + uint32_t col_off = U(0); + uint32_t row_off = U(0); + uint32_t byte_cnt = U(0); + uint32_t read_cnt = U(0); + uint32_t i = U(0); + uint32_t updated = U(0); + + int ret = 0; + uint8_t *out = (uint8_t *)dst; + + uint32_t pblk; + + /* loop till size */ + while (size) { + log_blk = (src_addr / nand->blk_size); + pg_no = ((src_addr - (log_blk * nand->blk_size)) / + nand->page_size); + pblk = log_blk; + + // iterate the bbt to find the block + for (i = 0; i <= nand->bbt_max; i++) { + if (nand->bbt[i] == EMPTY_VAL_CHECK) { + ret = update_bbt(i, pblk, &updated, nand); + + if (ret != 0) + return ret; + /* + * if table not updated and we reached + * end of table + */ + if (!updated) + break; + } + + if (pblk < nand->bbt[i]) + break; + else if (pblk >= nand->bbt[i]) + pblk++; + } + + col_off = (src_addr % nand->page_size); + if (col_off) { + if ((col_off + size) < nand->page_size) + byte_cnt = size; + else + byte_cnt = nand->page_size - col_off; + + row_off = (pblk << nand->pi_width) | pg_no; + + ret = nand_read_data( + nand->ifc_region_addr, + row_off, + col_off, + byte_cnt, out, MAIN, nand); + + if (ret != 0) + return ret; + } else { + /* + * fullpage/Partial Page + * if byte_cnt = 0 full page + * else partial page + */ + if (size < nand->page_size) { + byte_cnt = size; + read_cnt = size; + } else { + byte_cnt = nand->page_size; + read_cnt = 0; + } + row_off = (pblk << nand->pi_width) | pg_no; + + ret = nand_read_data( + nand->ifc_region_addr, + row_off, + 0, + read_cnt, out, MAIN, nand); + + if (ret != 0) { + ERROR("Error from nand-read_data %d\n", ret); + return ret; + } + } + src_addr += byte_cnt; + out += byte_cnt; + size -= byte_cnt; + } + return 0; +} + +static int isgoodblock(uint32_t blk, uint32_t *gb, struct nand_info *nand) +{ + uint8_t buf[2]; + int ret; + uint32_t row_add; + + *gb = 0; + + /* read Page 0 of blk */ + ret = nand_read_data( + nand->ifc_region_addr, + blk << nand->pi_width, + nand->bad_marker_loc, + 0x2, buf, 1, nand); + + if (ret != 0) + return ret; + + /* For ONFI devices check Page 0 and Last page of block for + * Bad Marker and for NON-ONFI Page 0 and 1 for Bad Marker + */ + row_add = (blk << nand->pi_width); + if (nand->port_size == 8) { + /* port size is 8 Bit */ + /* check if page 0 has 0xff */ + if (buf[0] == 0xff) { + /* check page 1 */ + if (nand->onfi_dev_flag) + ret = nand_read_data( + nand->ifc_region_addr, + row_add | (nand->ppb - 1), + nand->bad_marker_loc, + 0x2, buf, SPARE, nand); + else + ret = nand_read_data( + nand->ifc_region_addr, + row_add | 1, + nand->bad_marker_loc, + 0x2, buf, SPARE, nand); + + if (ret != 0) + return ret; + + if (buf[0] == 0xff) + *gb = GOOD_BLK; + else + *gb = BAD_BLK; + } else { + /* no, so it is bad blk */ + *gb = BAD_BLK; + } + } else { + /* Port size 16-Bit */ + /* check if page 0 has 0xffff */ + if ((buf[0] == 0xff) && + (buf[1] == 0xff)) { + /* check page 1 for 0xffff */ + if (nand->onfi_dev_flag) { + ret = nand_read_data( + nand->ifc_region_addr, + row_add | (nand->ppb - 1), + nand->bad_marker_loc, + 0x2, buf, SPARE, nand); + } else { + ret = nand_read_data( + nand->ifc_region_addr, + row_add | 1, + nand->bad_marker_loc, + 0x2, buf, SPARE, nand); + } + + if (ret != 0) + return ret; + + if ((buf[0] == 0xff) && + (buf[1] == 0xff)) { + *gb = GOOD_BLK; + } else { + *gb = BAD_BLK; + } + } else { + /* no, so it is bad blk */ + *gb = BAD_BLK; + } + } + return 0; +} + +static int update_bbt(uint32_t idx, uint32_t blk, + uint32_t *updated, struct nand_info *nand) +{ + uint32_t sblk; + uint32_t lgb; + int ret; + + if (nand->bzero_good && blk == 0) + return 0; + + /* special case for lgb == 0 */ + /* if blk <= lgb retrun */ + if (nand->lgb != 0 && blk <= nand->lgb) + return 0; + + *updated = 0; + + /* if blk is more than lgb, iterate from lgb till a good block + * is found for blk + */ + + if (nand->lgb < blk) + sblk = nand->lgb; + else + /* this is when lgb = 0 */ + sblk = blk; + + + lgb = nand->lgb; + + /* loop from blk to find a good block */ + while (1) { + while (lgb <= sblk) { + uint32_t gb = 0; + + ret = isgoodblock(lgb, &gb, nand); + if (ret != 0) + return ret; + + /* special case block 0 is good then set this flag */ + if (lgb == 0 && gb == GOOD_BLK) + nand->bzero_good = 1; + + if (gb == BAD_BLK) { + if (idx >= BBT_SIZE) { + ERROR("NAND BBT Table full\n"); + return -1; + } + *updated = 1; + nand->bbt[idx] = lgb; + idx++; + blk++; + sblk++; + if (idx > nand->bbt_max) + nand->bbt_max = idx; + } + lgb++; + } + /* the access block found */ + if (sblk == blk) { + /* when good block found update lgb */ + nand->lgb = blk; + break; + } + sblk++; + } + + return 0; +} + +static size_t ifc_nand_read(int lba, uintptr_t buf, size_t size) +{ + int ret; + uint32_t page_size; + uint32_t src_addr; + struct nand_info *nand = &nand_drv_data; + + page_size = nand_get_page_size(nand); + src_addr = lba * page_size; + ret = nand_read(nand, src_addr, buf, size); + return ret ? 0 : size; +} + +static struct io_block_dev_spec ifc_nand_spec = { + .buffer = { + .offset = 0, + .length = 0, + }, + .ops = { + .read = ifc_nand_read, + }, + /* + * Default block size assumed as 2K + * Would be updated based on actual size + */ + .block_size = UL(2048), +}; + +int ifc_nand_init(uintptr_t *block_dev_spec, + uintptr_t ifc_region_addr, + uintptr_t ifc_register_addr, + size_t ifc_sram_size, + uintptr_t ifc_nand_blk_offset, + size_t ifc_nand_blk_size) +{ + struct nand_info *nand = NULL; + int ret; + + nand = &nand_drv_data; + memset(nand, 0, sizeof(struct nand_info)); + + nand->ifc_region_addr = ifc_region_addr; + nand->ifc_register_addr = ifc_register_addr; + + VERBOSE("nand_init\n"); + ret = nand_init(nand); + if (ret) { + ERROR("nand init failed\n"); + return ret; + } + + ifc_nand_spec.buffer.offset = ifc_nand_blk_offset; + ifc_nand_spec.buffer.length = ifc_nand_blk_size; + + ifc_nand_spec.block_size = nand_get_page_size(nand); + + VERBOSE("Page size is %ld\n", ifc_nand_spec.block_size); + + *block_dev_spec = (uintptr_t)&ifc_nand_spec; + + /* Adding NAND SRAM< Buffer in XLAT Table */ + mmap_add_region(ifc_region_addr, ifc_region_addr, + ifc_sram_size, MT_DEVICE | MT_RW); + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc_nand.mk 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc_nand.mk --- 2.6+dfsg-1/drivers/nxp/ifc/nand/ifc_nand.mk 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ifc/nand/ifc_nand.mk 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,29 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${NAND_ADDED},) + +NAND_ADDED := 1 + +NAND_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ifc/nand + +NAND_SOURCES := $(NAND_DRIVERS_PATH)/ifc_nand.c \ + drivers/io/io_block.c + +PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc + +ifeq (${BL_COMM_IFC_NAND_NEEDED},yes) +BL_COMMON_SOURCES += ${NAND_SOURCES} +else +ifeq (${BL2_IFC_NAND_NEEDED},yes) +BL2_SOURCES += ${NAND_SOURCES} +endif +ifeq (${BL31_IFC_NAND_NEEDED},yes) +BL31_SOURCES += ${NAND_SOURCES} +endif +endif + +endif diff -pruN 2.6+dfsg-1/drivers/nxp/ifc/nor/ifc_nor.c 2.7.0+dfsg-2/drivers/nxp/ifc/nor/ifc_nor.c --- 2.6+dfsg-1/drivers/nxp/ifc/nor/ifc_nor.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ifc/nor/ifc_nor.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,18 @@ +/* + * Copyright 2020-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include + +#include + +int ifc_nor_init(uintptr_t flash_addr, size_t flash_size) +{ + /* Adding NOR Memory Map in XLAT Table */ + mmap_add_region(flash_addr, flash_addr, flash_size, MT_MEMORY | MT_RW); + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/nxp/ifc/nor/ifc_nor.mk 2.7.0+dfsg-2/drivers/nxp/ifc/nor/ifc_nor.mk --- 2.6+dfsg-1/drivers/nxp/ifc/nor/ifc_nor.mk 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/ifc/nor/ifc_nor.mk 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,28 @@ +# +# Copyright 2020-2021 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${NOR_ADDED},) + +NOR_ADDED := 1 + +NOR_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/ifc/nor + +NOR_SOURCES := $(NOR_DRIVERS_PATH)/ifc_nor.c + +PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ifc + +ifeq (${BL_COMM_IFC_NOR_NEEDED},yes) +BL_COMMON_SOURCES += ${NOR_SOURCES} +else +ifeq (${BL2_IFC_NOR_NEEDED},yes) +BL2_SOURCES += ${NOR_SOURCES} +endif +ifeq (${BL31_IFC_NOR_NEEDED},yes) +BL31_SOURCES += ${NOR_SOURCES} +endif +endif + +endif diff -pruN 2.6+dfsg-1/drivers/nxp/qspi/qspi.mk 2.7.0+dfsg-2/drivers/nxp/qspi/qspi.mk --- 2.6+dfsg-1/drivers/nxp/qspi/qspi.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/qspi/qspi.mk 2022-06-01 15:02:46.000000000 +0000 @@ -10,7 +10,7 @@ QSPI_ADDED := 1 QSPI_SOURCES := $(PLAT_DRIVERS_PATH)/qspi/qspi.c -PLAT_INCLUDES += -I$(PLAT_DRIVERS_PATH)/qspi +PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/qspi ifeq (${BL_COMM_QSPI_NEEDED},yes) BL_COMMON_SOURCES += ${QSPI_SOURCES} diff -pruN 2.6+dfsg-1/drivers/nxp/tzc/plat_tzc380.c 2.7.0+dfsg-2/drivers/nxp/tzc/plat_tzc380.c --- 2.6+dfsg-1/drivers/nxp/tzc/plat_tzc380.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/tzc/plat_tzc380.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,152 @@ +/* + * Copyright 2018-2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#pragma weak populate_tzc380_reg_list + +#ifdef DEFAULT_TZASC_CONFIG +/* + * Typical Memory map of DRAM0 + * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------| + * | | + * | | + * | Non-SECURE REGION | + * | | + * | | + * | | + * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------| + * |-----------------NXP_SECURE_DRAM_ADDR--------------------| + * | | + * | | + * | | + * | SECURE REGION (= 64MB) | + * | | + * | | + * | | + * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----| + * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------| + * | | + * | Secure EL1 Payload SHARED REGION (= 2MB) | + * | | + * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------| + * + * + * + * Typical Memory map of DRAM1 + * |---------------------NXP_DRAM1_ADDR----------------------| + * | | + * | | + * | Non-SECURE REGION | + * | | + * | | + * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---| + * + * + * Typical Memory map of DRAM2 + * |---------------------NXP_DRAM2_ADDR----------------------| + * | | + * | | + * | Non-SECURE REGION | + * | | + * | | + * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---| + */ + +/***************************************************************************** + * This function sets up access permissions on memory regions + * + * Input: + * tzc380_reg_list : TZC380 Region List + * dram_idx : DRAM index + * list_idx : TZC380 Region List Index + * dram_start_addr : Start address of DRAM at dram_idx. + * dram_size : Size of DRAM at dram_idx. + * secure_dram_sz : Secure DRAM Size + * shrd_dram_sz : Shared DRAM Size + * + * Out: + * list_idx : last populated index + 1 + * + ****************************************************************************/ +int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, + int dram_idx, int list_idx, + uint64_t dram_start_addr, + uint64_t dram_size, + uint32_t secure_dram_sz, + uint32_t shrd_dram_sz) +{ + /* Region 0: Default region marked as Non-Secure */ + if (list_idx == 0) { + tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW; + tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE; + tzc380_reg_list[list_idx].addr = UL(0x0); + tzc380_reg_list[list_idx].size = 0x0; + tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ + list_idx++; + } + /* Continue with list entries for index > 0 */ + if (dram_idx == 0) { + /* TZC Region 1 on DRAM0 for Secure Memory*/ + tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; + tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; + tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size; + tzc380_reg_list[list_idx].size = secure_dram_sz; + tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ + list_idx++; + + /* TZC Region 2 on DRAM0 for Shared Memory*/ + tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW; + tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; + tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz; + tzc380_reg_list[list_idx].size = shrd_dram_sz; + tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */ + list_idx++; + + } + + return list_idx; +} +#else +int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, + int dram_idx, int list_idx, + uint64_t dram_start_addr, + uint64_t dram_size, + uint32_t secure_dram_sz, + uint32_t shrd_dram_sz) +{ + ERROR("tzc380_reg_list used is not a default list\n"); + ERROR("%s needs to be over-written.\n", __func__); + return 0; +} +#endif /* DEFAULT_TZASC_CONFIG */ + + +void mem_access_setup(uintptr_t base, uint32_t total_regions, + struct tzc380_reg *tzc380_reg_list) +{ + uint32_t indx = 0; + unsigned int attr_value; + + VERBOSE("Configuring TrustZone Controller tzc380\n"); + + tzc380_init(base); + + tzc380_set_action(TZC_ACTION_NONE); + + for (indx = 0; indx < total_regions; indx++) { + attr_value = tzc380_reg_list[indx].secure | + TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) | + TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) | + tzc380_reg_list[indx].enabled; + + tzc380_configure_region(indx, tzc380_reg_list[indx].addr, + attr_value); + } + + tzc380_set_action(TZC_ACTION_ERR); +} diff -pruN 2.6+dfsg-1/drivers/nxp/tzc/tzc.mk 2.7.0+dfsg-2/drivers/nxp/tzc/tzc.mk --- 2.6+dfsg-1/drivers/nxp/tzc/tzc.mk 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/nxp/tzc/tzc.mk 2022-06-01 15:02:46.000000000 +0000 @@ -13,11 +13,18 @@ PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLU ifeq ($(TZC_ID), TZC400) TZASC_SOURCES += drivers/arm/tzc/tzc400.c\ $(PLAT_DRIVERS_PATH)/tzc/plat_tzc400.c -else ifeq ($(TZC_ID), NONE) +else +ifeq ($(TZC_ID), TZC380) +TZASC_SOURCES += drivers/arm/tzc/tzc380.c\ + $(PLAT_DRIVERS_PATH)/tzc/plat_tzc380.c +else +ifeq ($(TZC_ID), NONE) $(info -> No TZC present on platform) else $(error -> TZC type not set!) endif +endif +endif ifeq (${BL_COMM_TZASC_NEEDED},yes) BL_COMMON_SOURCES += ${TZASC_SOURCES} diff -pruN 2.6+dfsg-1/drivers/partition/gpt.c 2.7.0+dfsg-2/drivers/partition/gpt.c --- 2.6+dfsg-1/drivers/partition/gpt.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/partition/gpt.c 2022-06-01 15:02:46.000000000 +0000 @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -57,5 +58,7 @@ int parse_gpt_entry(gpt_entry_t *gpt_ent entry->length = (uint64_t)(gpt_entry->last_lba - gpt_entry->first_lba + 1) * PLAT_PARTITION_BLOCK_SIZE; + guidcpy(&entry->part_guid, &gpt_entry->unique_uuid); + return 0; } diff -pruN 2.6+dfsg-1/drivers/partition/partition.c 2.7.0+dfsg-2/drivers/partition/partition.c --- 2.6+dfsg-1/drivers/partition/partition.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/partition/partition.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,9 @@ #include #include +#include #include +#include #include #include #include @@ -75,7 +77,7 @@ static int load_mbr_header(uintptr_t ima } /* - * Load GPT header and check the GPT signature. + * Load GPT header and check the GPT signature and header CRC. * If partition numbers could be found, check & update it. */ static int load_gpt_header(uintptr_t image_handle) @@ -83,6 +85,7 @@ static int load_gpt_header(uintptr_t ima gpt_header_t header; size_t bytes_read; int result; + uint32_t header_crc, calc_crc; result = io_seek(image_handle, IO_SEEK_SET, GPT_HEADER_OFFSET); if (result != 0) { @@ -98,6 +101,23 @@ static int load_gpt_header(uintptr_t ima return -EINVAL; } + /* + * UEFI Spec 2.8 March 2019 Page 119: HeaderCRC32 value is + * computed by setting this field to 0, and computing the + * 32-bit CRC for HeaderSize bytes. + */ + header_crc = header.header_crc; + header.header_crc = 0U; + + calc_crc = tf_crc32(0U, (uint8_t *)&header, DEFAULT_GPT_HEADER_SIZE); + if (header_crc != calc_crc) { + ERROR("Invalid GPT Header CRC: Expected 0x%x but got 0x%x.\n", + header_crc, calc_crc); + return -EINVAL; + } + + header.header_crc = header_crc; + /* partition numbers can't exceed PLAT_PARTITION_MAX_ENTRIES */ list.entry_count = header.list_num; if (list.entry_count > PLAT_PARTITION_MAX_ENTRIES) { @@ -246,6 +266,19 @@ const partition_entry_t *get_partition_e return NULL; } +const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid) +{ + int i; + + for (i = 0; i < list.entry_count; i++) { + if (guidcmp(part_uuid, &list.list[i].part_guid) == 0) { + return &list.list[i]; + } + } + + return NULL; +} + const partition_entry_list_t *get_partition_entry_list(void) { return &list; diff -pruN 2.6+dfsg-1/drivers/renesas/common/pwrc/pwrc.c 2.7.0+dfsg-2/drivers/renesas/common/pwrc/pwrc.c --- 2.6+dfsg-1/drivers/renesas/common/pwrc/pwrc.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/renesas/common/pwrc/pwrc.c 2022-06-01 15:02:46.000000000 +0000 @@ -156,7 +156,7 @@ IMPORT_SYM(unsigned long, __system_ram_e IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START); #endif -uint32_t rcar_pwrc_status(uint64_t mpidr) +uint32_t rcar_pwrc_status(u_register_t mpidr) { uint32_t ret = 0; uint64_t cm, cpu; @@ -188,7 +188,7 @@ done: return ret; } -static void scu_power_up(uint64_t mpidr) +static void scu_power_up(u_register_t mpidr) { uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer; uint32_t c, sysc_reg_bit; @@ -243,7 +243,7 @@ static void scu_power_up(uint64_t mpidr) ; } -void rcar_pwrc_cpuon(uint64_t mpidr) +void rcar_pwrc_cpuon(u_register_t mpidr) { uint32_t res_data, on_data; uintptr_t res_reg, on_reg; @@ -268,7 +268,7 @@ void rcar_pwrc_cpuon(uint64_t mpidr) rcar_lock_release(); } -void rcar_pwrc_cpuoff(uint64_t mpidr) +void rcar_pwrc_cpuoff(u_register_t mpidr) { uint32_t c; uintptr_t reg; @@ -289,7 +289,7 @@ void rcar_pwrc_cpuoff(uint64_t mpidr) rcar_lock_release(); } -void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) +void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr) { uint32_t c, shift_irq, shift_fiq; uintptr_t reg; @@ -304,12 +304,12 @@ void rcar_pwrc_enable_interrupt_wakeup(u shift_irq = WUP_IRQ_SHIFT + cpu; shift_fiq = WUP_FIQ_SHIFT + cpu; - mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) & - ~((uint32_t) 1 << shift_fiq)); + mmio_clrbits_32(reg, ((uint32_t) 1 << shift_irq) | + ((uint32_t) 1 << shift_fiq)); rcar_lock_release(); } -void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) +void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr) { uint32_t c, shift_irq, shift_fiq; uintptr_t reg; @@ -324,12 +324,35 @@ void rcar_pwrc_disable_interrupt_wakeup( shift_irq = WUP_IRQ_SHIFT + cpu; shift_fiq = WUP_FIQ_SHIFT + cpu; - mmio_write_32(reg, ((uint32_t) 1 << shift_irq) | + mmio_setbits_32(reg, ((uint32_t) 1 << shift_irq) | ((uint32_t) 1 << shift_fiq)); rcar_lock_release(); } -void rcar_pwrc_clusteroff(uint64_t mpidr) +void rcar_pwrc_all_disable_interrupt_wakeup(void) +{ + uint32_t cpu_num; + u_register_t cl, cpu, mpidr; + + const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = { + RCAR_CLUSTER_CA57, + RCAR_CLUSTER_CA53 + }; + + for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) { + cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]); + for (cpu = 0; cpu < cpu_num; cpu++) { + mpidr = ((cl << MPIDR_AFFINITY_BITS) | cpu); + if (mpidr == rcar_boot_mpidr) { + rcar_pwrc_enable_interrupt_wakeup(mpidr); + } else { + rcar_pwrc_disable_interrupt_wakeup(mpidr); + } + } + } +} + +void rcar_pwrc_clusteroff(u_register_t mpidr) { uint32_t c, product, cut, reg; uintptr_t dst; @@ -801,7 +824,7 @@ uint32_t rcar_pwrc_get_cluster(void) return RCAR_CLUSTER_A53A57; } -uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr) +uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr) { uint32_t c = rcar_pwrc_get_cluster(); @@ -854,7 +877,7 @@ done: } #endif -int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr) +int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr) { uint64_t i; uint64_t j; diff -pruN 2.6+dfsg-1/drivers/renesas/common/pwrc/pwrc.h 2.7.0+dfsg-2/drivers/renesas/common/pwrc/pwrc.h --- 2.6+dfsg-1/drivers/renesas/common/pwrc/pwrc.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/renesas/common/pwrc/pwrc.h 2022-06-01 15:02:46.000000000 +0000 @@ -38,19 +38,22 @@ #define RCAR_CLUSTER_CA53 (1U) #define RCAR_CLUSTER_CA57 (2U) +extern u_register_t rcar_boot_mpidr; + #ifndef __ASSEMBLER__ -void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); -void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); -void rcar_pwrc_clusteroff(uint64_t mpidr); -void rcar_pwrc_cpuoff(uint64_t mpidr); -void rcar_pwrc_cpuon(uint64_t mpidr); -int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr); +void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr); +void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr); +void rcar_pwrc_all_disable_interrupt_wakeup(void); +void rcar_pwrc_clusteroff(u_register_t mpidr); +void rcar_pwrc_cpuoff(u_register_t mpidr); +void rcar_pwrc_cpuon(u_register_t mpidr); +int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr); void rcar_pwrc_setup(void); -uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); -uint32_t rcar_pwrc_status(uint64_t mpidr); +uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr); +uint32_t rcar_pwrc_status(u_register_t mpidr); uint32_t rcar_pwrc_get_cluster(void); -uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr); +uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr); uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type); void rcar_pwrc_restore_timer_state(void); void plat_secondary_reset(void); diff -pruN 2.6+dfsg-1/drivers/scmi-msg/clock.c 2.7.0+dfsg-2/drivers/scmi-msg/clock.c --- 2.6+dfsg-1/drivers/scmi-msg/clock.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/scmi-msg/clock.c 2022-06-01 15:02:46.000000000 +0000 @@ -361,7 +361,7 @@ static const scmi_msg_handler_t scmi_clo [SCMI_CLOCK_CONFIG_SET] = scmi_clock_config_set, }; -static bool message_id_is_supported(size_t message_id) +static bool message_id_is_supported(unsigned int message_id) { return (message_id < ARRAY_SIZE(scmi_clock_handler_table)) && (scmi_clock_handler_table[message_id] != NULL); diff -pruN 2.6+dfsg-1/drivers/scmi-msg/entry.c 2.7.0+dfsg-2/drivers/scmi-msg/entry.c --- 2.6+dfsg-1/drivers/scmi-msg/entry.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/scmi-msg/entry.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2019-2020, Linaro Limited */ @@ -84,7 +84,7 @@ void scmi_process_message(struct scmi_ms return; } - ERROR("Agent %u Protocol 0x%x Message 0x%x: not supported", + ERROR("Agent %u Protocol 0x%x Message 0x%x: not supported\n", msg->agent_id, msg->protocol_id, msg->message_id); scmi_status_response(msg, SCMI_NOT_SUPPORTED); diff -pruN 2.6+dfsg-1/drivers/scmi-msg/power_domain.c 2.7.0+dfsg-2/drivers/scmi-msg/power_domain.c --- 2.6+dfsg-1/drivers/scmi-msg/power_domain.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/scmi-msg/power_domain.c 2022-06-01 15:02:46.000000000 +0000 @@ -19,7 +19,7 @@ #pragma weak plat_scmi_pd_statistics #pragma weak plat_scmi_pd_get_attributes -static bool message_id_is_supported(size_t message_id); +static bool message_id_is_supported(unsigned int message_id); size_t plat_scmi_pd_count(unsigned int agent_id __unused) { @@ -219,7 +219,7 @@ static const scmi_msg_handler_t scmi_pd_ [SCMI_PD_STATE_GET] = scmi_pd_state_get, }; -static bool message_id_is_supported(size_t message_id) +static bool message_id_is_supported(unsigned int message_id) { return (message_id < ARRAY_SIZE(scmi_pd_handler_table)) && (scmi_pd_handler_table[message_id] != NULL); diff -pruN 2.6+dfsg-1/drivers/st/bsec/bsec2.c 2.7.0+dfsg-2/drivers/st/bsec/bsec2.c --- 2.6+dfsg-1/drivers/st/bsec/bsec2.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/bsec/bsec2.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,961 @@ +/* + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BSEC_IP_VERSION_1_1 U(0x11) +#define BSEC_IP_VERSION_2_0 U(0x20) +#define BSEC_IP_ID_2 U(0x100032) + +#define OTP_ACCESS_SIZE (round_up(OTP_MAX_SIZE, __WORD_BIT) / __WORD_BIT) + +static uint32_t otp_nsec_access[OTP_ACCESS_SIZE] __unused; + +static uint32_t bsec_power_safmem(bool power); + +/* BSEC access protection */ +static spinlock_t bsec_spinlock; +static uintptr_t bsec_base; + +static void bsec_lock(void) +{ + if (stm32mp_lock_available()) { + spin_lock(&bsec_spinlock); + } +} + +static void bsec_unlock(void) +{ + if (stm32mp_lock_available()) { + spin_unlock(&bsec_spinlock); + } +} + +static bool is_otp_invalid_mode(void) +{ + bool ret = ((bsec_get_status() & BSEC_MODE_INVALID) == BSEC_MODE_INVALID); + + if (ret) { + ERROR("OTP mode is OTP-INVALID\n"); + } + + return ret; +} + +#if defined(IMAGE_BL32) +static int bsec_get_dt_node(struct dt_node_info *info) +{ + int node; + + node = dt_get_node(info, -1, DT_BSEC_COMPAT); + if (node < 0) { + return -FDT_ERR_NOTFOUND; + } + + return node; +} + +static void enable_non_secure_access(uint32_t otp) +{ + otp_nsec_access[otp / __WORD_BIT] |= BIT(otp % __WORD_BIT); + + if (bsec_shadow_register(otp) != BSEC_OK) { + panic(); + } +} + +static bool non_secure_can_access(uint32_t otp) +{ + return (otp_nsec_access[otp / __WORD_BIT] & + BIT(otp % __WORD_BIT)) != 0U; +} + +static void bsec_dt_otp_nsec_access(void *fdt, int bsec_node) +{ + int bsec_subnode; + + fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) { + const fdt32_t *cuint; + uint32_t otp; + uint32_t i; + uint32_t size; + uint32_t offset; + uint32_t length; + + cuint = fdt_getprop(fdt, bsec_subnode, "reg", NULL); + if (cuint == NULL) { + panic(); + } + + offset = fdt32_to_cpu(*cuint); + cuint++; + length = fdt32_to_cpu(*cuint); + + otp = offset / sizeof(uint32_t); + + if (otp < STM32MP1_UPPER_OTP_START) { + unsigned int otp_end = round_up(offset + length, + sizeof(uint32_t)) / + sizeof(uint32_t); + + if (otp_end > STM32MP1_UPPER_OTP_START) { + /* + * OTP crosses Lower/Upper boundary, consider + * only the upper part. + */ + otp = STM32MP1_UPPER_OTP_START; + length -= (STM32MP1_UPPER_OTP_START * + sizeof(uint32_t)) - offset; + offset = STM32MP1_UPPER_OTP_START * + sizeof(uint32_t); + + WARN("OTP crosses Lower/Upper boundary\n"); + } else { + continue; + } + } + + if ((fdt_getprop(fdt, bsec_subnode, + "st,non-secure-otp", NULL)) == NULL) { + continue; + } + + if (((offset % sizeof(uint32_t)) != 0U) || + ((length % sizeof(uint32_t)) != 0U)) { + ERROR("Unaligned non-secure OTP\n"); + panic(); + } + + size = length / sizeof(uint32_t); + + for (i = otp; i < (otp + size); i++) { + enable_non_secure_access(i); + } + } +} + +static void bsec_late_init(void) +{ + void *fdt; + int node; + struct dt_node_info bsec_info; + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + node = bsec_get_dt_node(&bsec_info); + if (node < 0) { + panic(); + } + + assert(bsec_base == bsec_info.base); + + bsec_dt_otp_nsec_access(fdt, node); +} +#endif + +static uint32_t otp_bank_offset(uint32_t otp) +{ + assert(otp <= STM32MP1_OTP_MAX_ID); + + return ((otp & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * + sizeof(uint32_t); +} + +/* + * bsec_check_error: check BSEC error status. + * otp: OTP number. + * check_disturbed: check only error (false), + * or error and disturbed status (true). + * return value: BSEC_OK if no error. + */ +static uint32_t bsec_check_error(uint32_t otp, bool check_disturbed) +{ + uint32_t bit = BIT(otp & BSEC_OTP_MASK); + uint32_t bank = otp_bank_offset(otp); + + if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) { + return BSEC_ERROR; + } + + if (!check_disturbed) { + return BSEC_OK; + } + + if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) { + return BSEC_DISTURBED; + } + + return BSEC_OK; +} + +/* + * bsec_probe: initialize BSEC driver. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_probe(void) +{ + bsec_base = BSEC_BASE; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if ((((bsec_get_version() & BSEC_IPVR_MSK) != BSEC_IP_VERSION_1_1) && + ((bsec_get_version() & BSEC_IPVR_MSK) != BSEC_IP_VERSION_2_0)) || + (bsec_get_id() != BSEC_IP_ID_2)) { + panic(); + } + +#if defined(IMAGE_BL32) + bsec_late_init(); +#endif + return BSEC_OK; +} + +/* + * bsec_get_base: return BSEC base address. + */ +uint32_t bsec_get_base(void) +{ + return bsec_base; +} + +/* + * bsec_set_config: enable and configure BSEC. + * cfg: pointer to param structure used to set register. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_set_config(struct bsec_config *cfg) +{ + uint32_t value; + uint32_t result; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) & + BSEC_CONF_FRQ_MASK) | + (((uint32_t)cfg->pulse_width << BSEC_CONF_PRG_WIDTH_SHIFT) & + BSEC_CONF_PRG_WIDTH_MASK) | + (((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) & + BSEC_CONF_TREAD_MASK)); + + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, value); + + bsec_unlock(); + + result = bsec_power_safmem((bool)cfg->power & + BSEC_CONF_POWER_UP_MASK); + if (result != BSEC_OK) { + return result; + } + + value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) & + UPPER_OTP_LOCK_MASK) | + (((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) & + DENREG_LOCK_MASK) | + (((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) & + GPLOCK_LOCK_MASK)); + + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_LOCK_OFF, value); + + bsec_unlock(); + + return BSEC_OK; +} + +/* + * bsec_get_config: return config parameters set in BSEC registers. + * cfg: config param return. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_get_config(struct bsec_config *cfg) +{ + uint32_t value; + + if (cfg == NULL) { + return BSEC_INVALID_PARAM; + } + + value = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF); + cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >> + BSEC_CONF_POWER_UP_SHIFT); + cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >> + BSEC_CONF_FRQ_SHIFT); + cfg->pulse_width = (uint8_t)((value & BSEC_CONF_PRG_WIDTH_MASK) >> + BSEC_CONF_PRG_WIDTH_SHIFT); + cfg->tread = (uint8_t)((value & BSEC_CONF_TREAD_MASK) >> + BSEC_CONF_TREAD_SHIFT); + + value = mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF); + cfg->upper_otp_lock = (uint8_t)((value & UPPER_OTP_LOCK_MASK) >> + UPPER_OTP_LOCK_SHIFT); + cfg->den_lock = (uint8_t)((value & DENREG_LOCK_MASK) >> + DENREG_LOCK_SHIFT); + cfg->prog_lock = (uint8_t)((value & GPLOCK_LOCK_MASK) >> + GPLOCK_LOCK_SHIFT); + + return BSEC_OK; +} + +/* + * bsec_shadow_register: copy SAFMEM OTP to BSEC data. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_shadow_register(uint32_t otp) +{ + uint32_t result; + bool value; + bool power_up = false; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + result = bsec_read_sr_lock(otp, &value); + if (result != BSEC_OK) { + ERROR("BSEC: %u Sticky-read bit read Error %u\n", otp, result); + return result; + } + + if (value) { + VERBOSE("BSEC: OTP %u is locked and will not be refreshed\n", + otp); + } + + if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { + result = bsec_power_safmem(true); + + if (result != BSEC_OK) { + return result; + } + + power_up = true; + } + + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_READ); + + while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { + ; + } + + result = bsec_check_error(otp, true); + + bsec_unlock(); + + if (power_up) { + if (bsec_power_safmem(false) != BSEC_OK) { + panic(); + } + } + + return result; +} + +/* + * bsec_read_otp: read an OTP data value. + * val: read value. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_read_otp(uint32_t *val, uint32_t otp) +{ + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + *val = mmio_read_32(bsec_base + BSEC_OTP_DATA_OFF + + (otp * sizeof(uint32_t))); + + return BSEC_OK; +} + +/* + * bsec_write_otp: write value in BSEC data register. + * val: value to write. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_write_otp(uint32_t val, uint32_t otp) +{ + uint32_t result; + bool value; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + result = bsec_read_sw_lock(otp, &value); + if (result != BSEC_OK) { + ERROR("BSEC: %u Sticky-write bit read Error %u\n", otp, result); + return result; + } + + if (value) { + VERBOSE("BSEC: OTP %u is locked and write will be ignored\n", + otp); + } + + /* Ensure integrity of each register access sequence */ + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_DATA_OFF + + (otp * sizeof(uint32_t)), val); + + bsec_unlock(); + + return result; +} + +/* + * bsec_program_otp: program a bit in SAFMEM after the prog. + * The OTP data is not refreshed. + * val: value to program. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_program_otp(uint32_t val, uint32_t otp) +{ + uint32_t result; + bool power_up = false; + bool sp_lock; + bool perm_lock; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + result = bsec_read_sp_lock(otp, &sp_lock); + if (result != BSEC_OK) { + ERROR("BSEC: %u Sticky-prog bit read Error %u\n", otp, result); + return result; + } + + result = bsec_read_permanent_lock(otp, &perm_lock); + if (result != BSEC_OK) { + ERROR("BSEC: %u permanent bit read Error %u\n", otp, result); + return result; + } + + if (sp_lock || perm_lock) { + WARN("BSEC: OTP locked, prog will be ignored\n"); + return BSEC_PROG_FAIL; + } + + if ((mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF) & + BIT(BSEC_LOCK_PROGRAM)) != 0U) { + WARN("BSEC: GPLOCK activated, prog will be ignored\n"); + } + + if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { + result = bsec_power_safmem(true); + + if (result != BSEC_OK) { + return result; + } + + power_up = true; + } + + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, val); + + mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_WRITE); + + while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { + ; + } + + if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) { + result = BSEC_PROG_FAIL; + } else { + result = bsec_check_error(otp, true); + } + + bsec_unlock(); + + if (power_up) { + if (bsec_power_safmem(false) != BSEC_OK) { + panic(); + } + } + + return result; +} + +/* + * bsec_permanent_lock_otp: permanent lock of OTP in SAFMEM. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_permanent_lock_otp(uint32_t otp) +{ + uint32_t result; + bool power_up = false; + uint32_t data; + uint32_t addr; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { + result = bsec_power_safmem(true); + + if (result != BSEC_OK) { + return result; + } + + power_up = true; + } + + if (otp < STM32MP1_UPPER_OTP_START) { + addr = otp >> ADDR_LOWER_OTP_PERLOCK_SHIFT; + data = DATA_LOWER_OTP_PERLOCK_BIT << + ((otp & DATA_LOWER_OTP_PERLOCK_MASK) << 1U); + } else { + addr = (otp >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U; + data = DATA_UPPER_OTP_PERLOCK_BIT << + (otp & DATA_UPPER_OTP_PERLOCK_MASK); + } + + bsec_lock(); + + mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, data); + + mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, + addr | BSEC_WRITE | BSEC_LOCK); + + while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { + ; + } + + if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) { + result = BSEC_PROG_FAIL; + } else { + result = bsec_check_error(otp, false); + } + + bsec_unlock(); + + if (power_up) { + if (bsec_power_safmem(false) != BSEC_OK) { + panic(); + } + } + + return result; +} + +/* + * bsec_write_debug_conf: write value in debug feature. + * to enable/disable debug service. + * val: value to write. + * return value: none. + */ +void bsec_write_debug_conf(uint32_t val) +{ + if (is_otp_invalid_mode()) { + return; + } + + bsec_lock(); + mmio_write_32(bsec_base + BSEC_DEN_OFF, val & BSEC_DEN_ALL_MSK); + bsec_unlock(); +} + +/* + * bsec_read_debug_conf: return debug configuration register value. + */ +uint32_t bsec_read_debug_conf(void) +{ + return mmio_read_32(bsec_base + BSEC_DEN_OFF); +} + +/* + * bsec_write_scratch: write value in scratch register. + * val: value to write. + * return value: none. + */ +void bsec_write_scratch(uint32_t val) +{ +#if defined(IMAGE_BL32) + if (is_otp_invalid_mode()) { + return; + } + + bsec_lock(); + mmio_write_32(bsec_base + BSEC_SCRATCH_OFF, val); + bsec_unlock(); +#else + mmio_write_32(BSEC_BASE + BSEC_SCRATCH_OFF, val); +#endif +} + +/* + * bsec_read_scratch: return scratch register value. + */ +uint32_t bsec_read_scratch(void) +{ + return mmio_read_32(bsec_base + BSEC_SCRATCH_OFF); +} + +/* + * bsec_get_status: return status register value. + */ +uint32_t bsec_get_status(void) +{ + return mmio_read_32(bsec_base + BSEC_OTP_STATUS_OFF); +} + +/* + * bsec_get_hw_conf: return hardware configuration register value. + */ +uint32_t bsec_get_hw_conf(void) +{ + return mmio_read_32(bsec_base + BSEC_IPHW_CFG_OFF); +} + +/* + * bsec_get_version: return BSEC version register value. + */ +uint32_t bsec_get_version(void) +{ + return mmio_read_32(bsec_base + BSEC_IPVR_OFF); +} + +/* + * bsec_get_id: return BSEC ID register value. + */ +uint32_t bsec_get_id(void) +{ + return mmio_read_32(bsec_base + BSEC_IP_ID_OFF); +} + +/* + * bsec_get_magic_id: return BSEC magic number register value. + */ +uint32_t bsec_get_magic_id(void) +{ + return mmio_read_32(bsec_base + BSEC_IP_MAGIC_ID_OFF); +} + +/* + * bsec_set_sr_lock: set shadow-read lock. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_set_sr_lock(uint32_t otp) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bsec_lock(); + mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, otp_mask); + bsec_unlock(); + + return BSEC_OK; +} + +/* + * bsec_read_sr_lock: read shadow-read lock. + * otp: OTP number. + * value: read value (true or false). + * return value: BSEC_OK if no error. + */ +uint32_t bsec_read_sr_lock(uint32_t otp, bool *value) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + uint32_t bank_value; + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); + + *value = ((bank_value & otp_mask) != 0U); + + return BSEC_OK; +} + +/* + * bsec_set_sw_lock: set shadow-write lock. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_set_sw_lock(uint32_t otp) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bsec_lock(); + mmio_write_32(bsec_base + BSEC_SWLOCK_OFF + bank, otp_mask); + bsec_unlock(); + + return BSEC_OK; +} + +/* + * bsec_read_sw_lock: read shadow-write lock. + * otp: OTP number. + * value: read value (true or false). + * return value: BSEC_OK if no error. + */ +uint32_t bsec_read_sw_lock(uint32_t otp, bool *value) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + uint32_t bank_value; + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank); + + *value = ((bank_value & otp_mask) != 0U); + + return BSEC_OK; +} + +/* + * bsec_set_sp_lock: set shadow-program lock. + * otp: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_set_sp_lock(uint32_t otp) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bsec_lock(); + mmio_write_32(bsec_base + BSEC_SPLOCK_OFF + bank, otp_mask); + bsec_unlock(); + + return BSEC_OK; +} + +/* + * bsec_read_sp_lock: read shadow-program lock. + * otp: OTP number. + * value: read value (true or false). + * return value: BSEC_OK if no error. + */ +uint32_t bsec_read_sp_lock(uint32_t otp, bool *value) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + uint32_t bank_value; + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank); + + *value = ((bank_value & otp_mask) != 0U); + + return BSEC_OK; +} + +/* + * bsec_read_permanent_lock: Read permanent lock status. + * otp: OTP number. + * value: read value (true or false). + * return value: BSEC_OK if no error. + */ +uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value) +{ + uint32_t bank = otp_bank_offset(otp); + uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); + uint32_t bank_value; + + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + bank_value = mmio_read_32(bsec_base + BSEC_WRLOCK_OFF + bank); + + *value = ((bank_value & otp_mask) != 0U); + + return BSEC_OK; +} + +/* + * bsec_otp_lock: Lock Upper OTP or Global Programming or Debug Enable. + * service: Service to lock, see header file. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_otp_lock(uint32_t service) +{ + uintptr_t reg = bsec_base + BSEC_OTP_LOCK_OFF; + + if (is_otp_invalid_mode()) { + return BSEC_ERROR; + } + + switch (service) { + case BSEC_LOCK_UPPER_OTP: + mmio_write_32(reg, BIT(BSEC_LOCK_UPPER_OTP)); + break; + case BSEC_LOCK_DEBUG: + mmio_write_32(reg, BIT(BSEC_LOCK_DEBUG)); + break; + case BSEC_LOCK_PROGRAM: + mmio_write_32(reg, BIT(BSEC_LOCK_PROGRAM)); + break; + default: + return BSEC_INVALID_PARAM; + } + + return BSEC_OK; +} + +/* + * bsec_power_safmem: Activate or deactivate SAFMEM power. + * power: true to power up, false to power down. + * return value: BSEC_OK if no error. + */ +static uint32_t bsec_power_safmem(bool power) +{ + uint32_t register_val; + uint32_t timeout = BSEC_TIMEOUT_VALUE; + + bsec_lock(); + + register_val = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF); + + if (power) { + register_val |= BSEC_CONF_POWER_UP_MASK; + } else { + register_val &= ~BSEC_CONF_POWER_UP_MASK; + } + + mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, register_val); + + if (power) { + while (((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) && + (timeout != 0U)) { + timeout--; + } + } else { + while (((bsec_get_status() & BSEC_MODE_PWR_MASK) != 0U) && + (timeout != 0U)) { + timeout--; + } + } + + bsec_unlock(); + + if (timeout == 0U) { + return BSEC_TIMEOUT; + } + + return BSEC_OK; +} + +/* + * bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value. + * otp_value: read value. + * word: OTP number. + * return value: BSEC_OK if no error. + */ +uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word) +{ + uint32_t result; + + result = bsec_shadow_register(word); + if (result != BSEC_OK) { + ERROR("BSEC: %u Shadowing Error %u\n", word, result); + return result; + } + + result = bsec_read_otp(otp_value, word); + if (result != BSEC_OK) { + ERROR("BSEC: %u Read Error %u\n", word, result); + } + + return result; +} + +/* + * bsec_check_nsec_access_rights: check non-secure access rights to target OTP. + * otp: OTP number. + * return value: BSEC_OK if authorized access. + */ +uint32_t bsec_check_nsec_access_rights(uint32_t otp) +{ +#if defined(IMAGE_BL32) + if (otp > STM32MP1_OTP_MAX_ID) { + return BSEC_INVALID_PARAM; + } + + if (otp >= STM32MP1_UPPER_OTP_START) { + if (!non_secure_can_access(otp)) { + return BSEC_ERROR; + } + } +#endif + + return BSEC_OK; +} + diff -pruN 2.6+dfsg-1/drivers/st/bsec/bsec.c 2.7.0+dfsg-2/drivers/st/bsec/bsec.c --- 2.6+dfsg-1/drivers/st/bsec/bsec.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/bsec/bsec.c 1970-01-01 00:00:00.000000000 +0000 @@ -1,891 +0,0 @@ -/* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include - -#include -#include -#include -#include -#include - -#define BSEC_IP_VERSION_1_0 0x10 -#define BSEC_COMPAT "st,stm32mp15-bsec" - -#define OTP_ACCESS_SIZE (round_up(OTP_MAX_SIZE, __WORD_BIT) / __WORD_BIT) - -static uint32_t otp_nsec_access[OTP_ACCESS_SIZE] __unused; - -static uint32_t bsec_power_safmem(bool power); - -/* BSEC access protection */ -static spinlock_t bsec_spinlock; -static uintptr_t bsec_base; - -static void bsec_lock(void) -{ - if (stm32mp_lock_available()) { - spin_lock(&bsec_spinlock); - } -} - -static void bsec_unlock(void) -{ - if (stm32mp_lock_available()) { - spin_unlock(&bsec_spinlock); - } -} - -static int bsec_get_dt_node(struct dt_node_info *info) -{ - int node; - - node = dt_get_node(info, -1, BSEC_COMPAT); - if (node < 0) { - return -FDT_ERR_NOTFOUND; - } - - return node; -} - -#if defined(IMAGE_BL32) -static void enable_non_secure_access(uint32_t otp) -{ - otp_nsec_access[otp / __WORD_BIT] |= BIT(otp % __WORD_BIT); - - if (bsec_shadow_register(otp) != BSEC_OK) { - panic(); - } -} - -static bool non_secure_can_access(uint32_t otp) -{ - return (otp_nsec_access[otp / __WORD_BIT] & - BIT(otp % __WORD_BIT)) != 0; -} - -static int bsec_dt_otp_nsec_access(void *fdt, int bsec_node) -{ - int bsec_subnode; - - fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) { - const fdt32_t *cuint; - uint32_t reg; - uint32_t i; - uint32_t size; - uint8_t status; - - cuint = fdt_getprop(fdt, bsec_subnode, "reg", NULL); - if (cuint == NULL) { - panic(); - } - - reg = fdt32_to_cpu(*cuint) / sizeof(uint32_t); - if (reg < STM32MP1_UPPER_OTP_START) { - continue; - } - - status = fdt_get_status(bsec_subnode); - if ((status & DT_NON_SECURE) == 0U) { - continue; - } - - size = fdt32_to_cpu(*(cuint + 1)) / sizeof(uint32_t); - - if ((fdt32_to_cpu(*(cuint + 1)) % sizeof(uint32_t)) != 0) { - size++; - } - - for (i = reg; i < (reg + size); i++) { - enable_non_secure_access(i); - } - } - - return 0; -} -#endif - -static uint32_t otp_bank_offset(uint32_t otp) -{ - assert(otp <= STM32MP1_OTP_MAX_ID); - - return ((otp & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * - sizeof(uint32_t); -} - -static uint32_t bsec_check_error(uint32_t otp) -{ - uint32_t bit = BIT(otp & BSEC_OTP_MASK); - uint32_t bank = otp_bank_offset(otp); - - if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) { - return BSEC_DISTURBED; - } - - if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) { - return BSEC_ERROR; - } - - return BSEC_OK; -} - -/* - * bsec_probe: initialize BSEC driver. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_probe(void) -{ - void *fdt; - int node; - struct dt_node_info bsec_info; - - if (fdt_get_address(&fdt) == 0) { - panic(); - } - - node = bsec_get_dt_node(&bsec_info); - if (node < 0) { - panic(); - } - - bsec_base = bsec_info.base; - -#if defined(IMAGE_BL32) - bsec_dt_otp_nsec_access(fdt, node); -#endif - return BSEC_OK; -} - -/* - * bsec_get_base: return BSEC base address. - */ -uint32_t bsec_get_base(void) -{ - return bsec_base; -} - -/* - * bsec_set_config: enable and configure BSEC. - * cfg: pointer to param structure used to set register. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_set_config(struct bsec_config *cfg) -{ - uint32_t value; - int32_t result; - - value = ((((uint32_t)cfg->freq << BSEC_CONF_FRQ_SHIFT) & - BSEC_CONF_FRQ_MASK) | - (((uint32_t)cfg->pulse_width << BSEC_CONF_PRG_WIDTH_SHIFT) & - BSEC_CONF_PRG_WIDTH_MASK) | - (((uint32_t)cfg->tread << BSEC_CONF_TREAD_SHIFT) & - BSEC_CONF_TREAD_MASK)); - - bsec_lock(); - - mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, value); - - bsec_unlock(); - - result = bsec_power_safmem((bool)cfg->power & - BSEC_CONF_POWER_UP_MASK); - if (result != BSEC_OK) { - return result; - } - - value = ((((uint32_t)cfg->upper_otp_lock << UPPER_OTP_LOCK_SHIFT) & - UPPER_OTP_LOCK_MASK) | - (((uint32_t)cfg->den_lock << DENREG_LOCK_SHIFT) & - DENREG_LOCK_MASK) | - (((uint32_t)cfg->prog_lock << GPLOCK_LOCK_SHIFT) & - GPLOCK_LOCK_MASK)); - - bsec_lock(); - - mmio_write_32(bsec_base + BSEC_OTP_LOCK_OFF, value); - - bsec_unlock(); - - return BSEC_OK; -} - -/* - * bsec_get_config: return config parameters set in BSEC registers. - * cfg: config param return. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_get_config(struct bsec_config *cfg) -{ - uint32_t value; - - if (cfg == NULL) { - return BSEC_INVALID_PARAM; - } - - value = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF); - cfg->power = (uint8_t)((value & BSEC_CONF_POWER_UP_MASK) >> - BSEC_CONF_POWER_UP_SHIFT); - cfg->freq = (uint8_t)((value & BSEC_CONF_FRQ_MASK) >> - BSEC_CONF_FRQ_SHIFT); - cfg->pulse_width = (uint8_t)((value & BSEC_CONF_PRG_WIDTH_MASK) >> - BSEC_CONF_PRG_WIDTH_SHIFT); - cfg->tread = (uint8_t)((value & BSEC_CONF_TREAD_MASK) >> - BSEC_CONF_TREAD_SHIFT); - - value = mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF); - cfg->upper_otp_lock = (uint8_t)((value & UPPER_OTP_LOCK_MASK) >> - UPPER_OTP_LOCK_SHIFT); - cfg->den_lock = (uint8_t)((value & DENREG_LOCK_MASK) >> - DENREG_LOCK_SHIFT); - cfg->prog_lock = (uint8_t)((value & GPLOCK_LOCK_MASK) >> - GPLOCK_LOCK_SHIFT); - - return BSEC_OK; -} - -/* - * bsec_shadow_register: copy SAFMEM OTP to BSEC data. - * otp: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_shadow_register(uint32_t otp) -{ - uint32_t result; - bool power_up = false; - - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - /* Check if shadowing of OTP is locked */ - if (bsec_read_sr_lock(otp)) { - VERBOSE("BSEC: OTP %i is locked and will not be refreshed\n", - otp); - } - - if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { - result = bsec_power_safmem(true); - - if (result != BSEC_OK) { - return result; - } - - power_up = true; - } - - bsec_lock(); - - /* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */ - mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_READ); - - while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { - ; - } - - result = bsec_check_error(otp); - - bsec_unlock(); - - if (power_up) { - if (bsec_power_safmem(false) != BSEC_OK) { - panic(); - } - } - - return result; -} - -/* - * bsec_read_otp: read an OTP data value. - * val: read value. - * otp: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_read_otp(uint32_t *val, uint32_t otp) -{ - uint32_t result; - - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - bsec_lock(); - - *val = mmio_read_32(bsec_base + BSEC_OTP_DATA_OFF + - (otp * sizeof(uint32_t))); - - result = bsec_check_error(otp); - - bsec_unlock(); - - return result; -} - -/* - * bsec_write_otp: write value in BSEC data register. - * val: value to write. - * otp: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_write_otp(uint32_t val, uint32_t otp) -{ - uint32_t result; - - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - /* Check if programming of OTP is locked */ - if (bsec_read_sw_lock(otp)) { - VERBOSE("BSEC: OTP %i is locked and write will be ignored\n", - otp); - } - - bsec_lock(); - - mmio_write_32(bsec_base + BSEC_OTP_DATA_OFF + - (otp * sizeof(uint32_t)), val); - - result = bsec_check_error(otp); - - bsec_unlock(); - - return result; -} - -/* - * bsec_program_otp: program a bit in SAFMEM after the prog. - * The OTP data is not refreshed. - * val: value to program. - * otp: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_program_otp(uint32_t val, uint32_t otp) -{ - uint32_t result; - bool power_up = false; - - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - /* Check if programming of OTP is locked */ - if (bsec_read_sp_lock(otp)) { - WARN("BSEC: OTP locked, prog will be ignored\n"); - } - - if ((mmio_read_32(bsec_base + BSEC_OTP_LOCK_OFF) & - BIT(BSEC_LOCK_PROGRAM)) != 0U) { - WARN("BSEC: GPLOCK activated, prog will be ignored\n"); - } - - if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { - result = bsec_power_safmem(true); - - if (result != BSEC_OK) { - return result; - } - - power_up = true; - } - - bsec_lock(); - - /* Set value in write register */ - mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, val); - - /* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */ - mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, otp | BSEC_WRITE); - - while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { - ; - } - - if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) { - result = BSEC_PROG_FAIL; - } else { - result = bsec_check_error(otp); - } - - bsec_unlock(); - - if (power_up) { - if (bsec_power_safmem(false) != BSEC_OK) { - panic(); - } - } - - return result; -} - -/* - * bsec_permanent_lock_otp: permanent lock of OTP in SAFMEM. - * otp: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_permanent_lock_otp(uint32_t otp) -{ - uint32_t result; - bool power_up = false; - uint32_t data; - uint32_t addr; - - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - if ((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) { - result = bsec_power_safmem(true); - - if (result != BSEC_OK) { - return result; - } - - power_up = true; - } - - if (otp < STM32MP1_UPPER_OTP_START) { - addr = otp >> ADDR_LOWER_OTP_PERLOCK_SHIFT; - data = DATA_LOWER_OTP_PERLOCK_BIT << - ((otp & DATA_LOWER_OTP_PERLOCK_MASK) << 1U); - } else { - addr = (otp >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U; - data = DATA_UPPER_OTP_PERLOCK_BIT << - (otp & DATA_UPPER_OTP_PERLOCK_MASK); - } - - bsec_lock(); - - /* Set value in write register */ - mmio_write_32(bsec_base + BSEC_OTP_WRDATA_OFF, data); - - /* Set BSEC_OTP_CTRL_OFF and set ADDR with the OTP value */ - mmio_write_32(bsec_base + BSEC_OTP_CTRL_OFF, - addr | BSEC_WRITE | BSEC_LOCK); - - while ((bsec_get_status() & BSEC_MODE_BUSY_MASK) != 0U) { - ; - } - - if ((bsec_get_status() & BSEC_MODE_PROGFAIL_MASK) != 0U) { - result = BSEC_PROG_FAIL; - } else { - result = bsec_check_error(otp); - } - - bsec_unlock(); - - if (power_up) { - if (bsec_power_safmem(false) != BSEC_OK) { - panic(); - } - } - - return result; -} - -/* - * bsec_write_debug_conf: write value in debug feature - * to enable/disable debug service. - * val: value to write. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_write_debug_conf(uint32_t val) -{ - uint32_t result = BSEC_ERROR; - uint32_t masked_val = val & BSEC_DEN_ALL_MSK; - - bsec_lock(); - - mmio_write_32(bsec_base + BSEC_DEN_OFF, masked_val); - - if ((mmio_read_32(bsec_base + BSEC_DEN_OFF) ^ masked_val) == 0U) { - result = BSEC_OK; - } - - bsec_unlock(); - - return result; -} - -/* - * bsec_read_debug_conf: read debug configuration. - */ -uint32_t bsec_read_debug_conf(void) -{ - return mmio_read_32(bsec_base + BSEC_DEN_OFF); -} - -/* - * bsec_get_status: return status register value. - */ -uint32_t bsec_get_status(void) -{ - return mmio_read_32(bsec_base + BSEC_OTP_STATUS_OFF); -} - -/* - * bsec_get_hw_conf: return hardware configuration. - */ -uint32_t bsec_get_hw_conf(void) -{ - return mmio_read_32(bsec_base + BSEC_IPHW_CFG_OFF); -} - -/* - * bsec_get_version: return BSEC version. - */ -uint32_t bsec_get_version(void) -{ - return mmio_read_32(bsec_base + BSEC_IPVR_OFF); -} - -/* - * bsec_get_id: return BSEC ID. - */ -uint32_t bsec_get_id(void) -{ - return mmio_read_32(bsec_base + BSEC_IP_ID_OFF); -} - -/* - * bsec_get_magic_id: return BSEC magic number. - */ -uint32_t bsec_get_magic_id(void) -{ - return mmio_read_32(bsec_base + BSEC_IP_MAGIC_ID_OFF); -} - -/* - * bsec_write_sr_lock: write shadow-read lock. - * otp: OTP number. - * value: value to write in the register. - * Must be always 1. - * return: true if OTP is locked, else false. - */ -bool bsec_write_sr_lock(uint32_t otp, uint32_t value) -{ - bool result = false; - uint32_t bank = otp_bank_offset(otp); - uint32_t bank_value; - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - - bsec_lock(); - - bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); - - if ((bank_value & otp_mask) == value) { - /* - * In case of write don't need to write, - * the lock is already set. - */ - if (value != 0U) { - result = true; - } - } else { - if (value != 0U) { - bank_value = bank_value | otp_mask; - } else { - bank_value = bank_value & ~otp_mask; - } - - /* - * We can write 0 in all other OTP - * if the lock is activated in one of other OTP. - * Write 0 has no effect. - */ - mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, bank_value); - result = true; - } - - bsec_unlock(); - - return result; -} - -/* - * bsec_read_sr_lock: read shadow-read lock. - * otp: OTP number. - * return: true if otp is locked, else false. - */ -bool bsec_read_sr_lock(uint32_t otp) -{ - uint32_t bank = otp_bank_offset(otp); - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); - - return (bank_value & otp_mask) != 0U; -} - -/* - * bsec_write_sw_lock: write shadow-write lock. - * otp: OTP number. - * value: Value to write in the register. - * Must be always 1. - * return: true if OTP is locked, else false. - */ -bool bsec_write_sw_lock(uint32_t otp, uint32_t value) -{ - bool result = false; - uint32_t bank = otp_bank_offset(otp); - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - uint32_t bank_value; - - bsec_lock(); - - bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank); - - if ((bank_value & otp_mask) == value) { - /* - * In case of write don't need to write, - * the lock is already set. - */ - if (value != 0U) { - result = true; - } - } else { - if (value != 0U) { - bank_value = bank_value | otp_mask; - } else { - bank_value = bank_value & ~otp_mask; - } - - /* - * We can write 0 in all other OTP - * if the lock is activated in one of other OTP. - * Write 0 has no effect. - */ - mmio_write_32(bsec_base + BSEC_SWLOCK_OFF + bank, bank_value); - result = true; - } - - bsec_unlock(); - - return result; -} - -/* - * bsec_read_sw_lock: read shadow-write lock. - * otp: OTP number. - * return: true if OTP is locked, else false. - */ -bool bsec_read_sw_lock(uint32_t otp) -{ - uint32_t bank = otp_bank_offset(otp); - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank); - - return (bank_value & otp_mask) != 0U; -} - -/* - * bsec_write_sp_lock: write shadow-program lock. - * otp: OTP number. - * value: Value to write in the register. - * Must be always 1. - * return: true if OTP is locked, else false. - */ -bool bsec_write_sp_lock(uint32_t otp, uint32_t value) -{ - bool result = false; - uint32_t bank = otp_bank_offset(otp); - uint32_t bank_value; - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - - bsec_lock(); - - bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank); - - if ((bank_value & otp_mask) == value) { - /* - * In case of write don't need to write, - * the lock is already set. - */ - if (value != 0U) { - result = true; - } - } else { - if (value != 0U) { - bank_value = bank_value | otp_mask; - } else { - bank_value = bank_value & ~otp_mask; - } - - /* - * We can write 0 in all other OTP - * if the lock is activated in one of other OTP. - * Write 0 has no effect. - */ - mmio_write_32(bsec_base + BSEC_SPLOCK_OFF + bank, bank_value); - result = true; - } - - bsec_unlock(); - - return result; -} - -/* - * bsec_read_sp_lock: read shadow-program lock. - * otp: OTP number. - * return: true if OTP is locked, else false. - */ -bool bsec_read_sp_lock(uint32_t otp) -{ - uint32_t bank = otp_bank_offset(otp); - uint32_t otp_mask = BIT(otp & BSEC_OTP_MASK); - uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SPLOCK_OFF + bank); - - return (bank_value & otp_mask) != 0U; -} - -/* - * bsec_wr_lock: Read permanent lock status. - * otp: OTP number. - * return: true if OTP is locked, else false. - */ -bool bsec_wr_lock(uint32_t otp) -{ - uint32_t bank = otp_bank_offset(otp); - uint32_t lock_bit = BIT(otp & BSEC_OTP_MASK); - - if ((mmio_read_32(bsec_base + BSEC_WRLOCK_OFF + bank) & - lock_bit) != 0U) { - /* - * In case of write don't need to write, - * the lock is already set. - */ - return true; - } - - return false; -} - -/* - * bsec_otp_lock: Lock Upper OTP or Global programming or debug enable - * service: Service to lock see header file. - * value: Value to write must always set to 1 (only use for debug purpose). - * return: BSEC_OK if succeed. - */ -uint32_t bsec_otp_lock(uint32_t service, uint32_t value) -{ - uintptr_t reg = bsec_base + BSEC_OTP_LOCK_OFF; - - switch (service) { - case BSEC_LOCK_UPPER_OTP: - mmio_write_32(reg, value << BSEC_LOCK_UPPER_OTP); - break; - case BSEC_LOCK_DEBUG: - mmio_write_32(reg, value << BSEC_LOCK_DEBUG); - break; - case BSEC_LOCK_PROGRAM: - mmio_write_32(reg, value << BSEC_LOCK_PROGRAM); - break; - default: - return BSEC_INVALID_PARAM; - } - - return BSEC_OK; -} - -/* - * bsec_power_safmem: Activate or deactivate SAFMEM power. - * power: true to power up, false to power down. - * return: BSEC_OK if succeed. - */ -static uint32_t bsec_power_safmem(bool power) -{ - uint32_t register_val; - uint32_t timeout = BSEC_TIMEOUT_VALUE; - - bsec_lock(); - - register_val = mmio_read_32(bsec_base + BSEC_OTP_CONF_OFF); - - if (power) { - register_val |= BSEC_CONF_POWER_UP_MASK; - } else { - register_val &= ~BSEC_CONF_POWER_UP_MASK; - } - - mmio_write_32(bsec_base + BSEC_OTP_CONF_OFF, register_val); - - /* Waiting loop */ - if (power) { - while (((bsec_get_status() & BSEC_MODE_PWR_MASK) == 0U) && - (timeout != 0U)) { - timeout--; - } - } else { - while (((bsec_get_status() & BSEC_MODE_PWR_MASK) != 0U) && - (timeout != 0U)) { - timeout--; - } - } - - bsec_unlock(); - - if (timeout == 0U) { - return BSEC_TIMEOUT; - } - - return BSEC_OK; -} - -/* - * bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value - * otp_value: read value. - * word: OTP number. - * return value: BSEC_OK if no error. - */ -uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word) -{ - uint32_t result; - - result = bsec_shadow_register(word); - if (result != BSEC_OK) { - ERROR("BSEC: %u Shadowing Error %i\n", word, result); - return result; - } - - result = bsec_read_otp(otp_value, word); - if (result != BSEC_OK) { - ERROR("BSEC: %u Read Error %i\n", word, result); - } - - return result; -} - -/* - * bsec_check_nsec_access_rights: check non-secure access rights to target OTP. - * otp: OTP number. - * return: BSEC_OK if authorized access. - */ -uint32_t bsec_check_nsec_access_rights(uint32_t otp) -{ -#if defined(IMAGE_BL32) - if (otp > STM32MP1_OTP_MAX_ID) { - return BSEC_INVALID_PARAM; - } - - if (otp >= STM32MP1_UPPER_OTP_START) { - /* Check if BSEC is in OTP-SECURED closed_device state. */ - if (stm32mp_is_closed_device()) { - if (!non_secure_can_access(otp)) { - return BSEC_ERROR; - } - } - } -#endif - - return BSEC_OK; -} - diff -pruN 2.6+dfsg-1/drivers/st/clk/clk-stm32-core.c 2.7.0+dfsg-2/drivers/st/clk/clk-stm32-core.c --- 2.6+dfsg-1/drivers/st/clk/clk-stm32-core.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/clk/clk-stm32-core.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,1113 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include +#include + +#include "clk-stm32-core.h" +#include +#include +#include +#include +#include +#include +#include + +static struct spinlock reg_lock; +static struct spinlock refcount_lock; + +static struct stm32_clk_priv *stm32_clock_data; + +const struct stm32_clk_ops clk_mux_ops; + +struct stm32_clk_priv *clk_stm32_get_priv(void) +{ + return stm32_clock_data; +} + +static void stm32mp1_clk_lock(struct spinlock *lock) +{ + if (stm32mp_lock_available()) { + /* Assume interrupts are masked */ + spin_lock(lock); + } +} + +static void stm32mp1_clk_unlock(struct spinlock *lock) +{ + if (stm32mp_lock_available()) { + spin_unlock(lock); + } +} + +void stm32mp1_clk_rcc_regs_lock(void) +{ + stm32mp1_clk_lock(®_lock); +} + +void stm32mp1_clk_rcc_regs_unlock(void) +{ + stm32mp1_clk_unlock(®_lock); +} + +#define TIMEOUT_US_1S U(1000000) +#define OSCRDY_TIMEOUT TIMEOUT_US_1S + +struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_osc_cfg *osc_cfg = clk->clock_cfg; + int osc_id = osc_cfg->osc_id; + + return &priv->osci_data[osc_id]; +} + +void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_bypass *bypass_data = osc_data->bypass; + uintptr_t address; + + if (bypass_data == NULL) { + return; + } + + address = priv->base + bypass_data->offset; + + if (digbyp) { + mmio_setbits_32(address, BIT(bypass_data->bit_digbyp)); + } + + if (bypass || digbyp) { + mmio_setbits_32(address, BIT(bypass_data->bit_byp)); + } +} + +void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_css *css_data = osc_data->css; + uintptr_t address; + + if (css_data == NULL) { + return; + } + + address = priv->base + css_data->offset; + + if (css) { + mmio_setbits_32(address, BIT(css_data->bit_css)); + } +} + +void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + struct stm32_clk_drive *drive_data = osc_data->drive; + uintptr_t address; + uint32_t mask; + uint32_t value; + + if (drive_data == NULL) { + return; + } + + address = priv->base + drive_data->offset; + + mask = (BIT(drive_data->drv_width) - 1U) << drive_data->drv_shift; + + /* + * Warning: not recommended to switch directly from "high drive" + * to "medium low drive", and vice-versa. + */ + value = (mmio_read_32(address) & mask) >> drive_data->drv_shift; + + while (value != lsedrv) { + if (value > lsedrv) { + value--; + } else { + value++; + } + + mmio_clrsetbits_32(address, mask, value << drive_data->drv_shift); + } +} + +int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return _clk_stm32_gate_wait_ready(priv, osc_data->gate_id, ready_on); +} + +int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id) +{ + return clk_oscillator_wait_ready(priv, id, true); +} + +int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id) +{ + return clk_oscillator_wait_ready(priv, id, false); +} + +static int clk_gate_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); + + return 0; +} + +static void clk_gate_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx)); +} + +static bool clk_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_gate_cfg *cfg = clk->clock_cfg; + + return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U); +} + +const struct stm32_clk_ops clk_gate_ops = { + .enable = clk_gate_enable, + .disable = clk_gate_disable, + .is_enabled = clk_gate_is_enabled, +}; + +void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + } else { + mmio_clrbits_32(addr, BIT(gate->bit_idx)); + } +} + +int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr, BIT(gate->bit_idx)); + + } else { + mmio_setbits_32(addr, BIT(gate->bit_idx)); + } + + return 0; +} + +const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id) +{ + return priv->clks[id].name; +} + +const char *clk_stm32_get_name(struct stm32_clk_priv *priv, + unsigned long binding_id) +{ + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return NULL; + } + + return _clk_stm32_get_name(priv, id); +} + +const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id) +{ + if ((unsigned int)id < priv->num) { + return &priv->clks[id]; + } + + return NULL; +} + +#define clk_div_mask(_width) GENMASK(((_width) - 1U), 0U) + +static unsigned int _get_table_div(const struct clk_div_table *table, + unsigned int val) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) { + if (clkt->val == val) { + return clkt->div; + } + } + + return 0; +} + +static unsigned int _get_div(const struct clk_div_table *table, + unsigned int val, unsigned long flags, + uint8_t width) +{ + if ((flags & CLK_DIVIDER_ONE_BASED) != 0UL) { + return val; + } + + if ((flags & CLK_DIVIDER_POWER_OF_TWO) != 0UL) { + return BIT(val); + } + + if ((flags & CLK_DIVIDER_MAX_AT_ZERO) != 0UL) { + return (val != 0U) ? val : BIT(width); + } + + if (table != NULL) { + return _get_table_div(table, val); + } + + return val + 1U; +} + +#define TIMEOUT_US_200MS U(200000) +#define CLKSRC_TIMEOUT TIMEOUT_US_200MS + +int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) +{ + const struct parent_cfg *parents = &priv->parents[pid & MUX_PARENT_MASK]; + const struct mux_cfg *mux = parents->mux; + uintptr_t address = priv->base + mux->offset; + uint32_t mask; + uint64_t timeout; + + mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); + + mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); + + if (mux->bitrdy == MUX_NO_BIT_RDY) { + return 0; + } + + timeout = timeout_init_us(CLKSRC_TIMEOUT); + + mask = BIT(mux->bitrdy); + + while ((mmio_read_32(address) & mask) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int clk, int clkp) +{ + const struct parent_cfg *parents; + uint16_t pid; + uint8_t sel; + int old_parent; + + pid = priv->clks[clk].parent; + + if ((pid == CLK_IS_ROOT) || (pid < MUX_MAX_PARENTS)) { + return -EINVAL; + } + + old_parent = _clk_stm32_get_parent(priv, clk); + if (old_parent < 0) { + return old_parent; + } + if (old_parent == clkp) { + return 0; + } + + parents = &priv->parents[pid & MUX_PARENT_MASK]; + + for (sel = 0; sel < parents->num_parents; sel++) { + if (parents->id_parents[sel] == (uint16_t)clkp) { + bool clk_was_enabled = _clk_stm32_is_enabled(priv, clk); + int err = 0; + + /* Enable the parents (for glitch free mux) */ + _clk_stm32_enable(priv, clkp); + _clk_stm32_enable(priv, old_parent); + + err = clk_mux_set_parent(priv, pid, sel); + + _clk_stm32_disable(priv, old_parent); + + if (clk_was_enabled) { + _clk_stm32_disable(priv, old_parent); + } else { + _clk_stm32_disable(priv, clkp); + } + + return err; + } + } + + return -EINVAL; +} + +int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id) +{ + const struct parent_cfg *parent; + const struct mux_cfg *mux; + uint32_t mask; + + if (mux_id >= priv->nb_parents) { + panic(); + } + + parent = &priv->parents[mux_id]; + mux = parent->mux; + + mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); + + return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift; +} + +int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel) +{ + uint16_t pid; + + pid = priv->clks[clk].parent; + + if ((pid == CLK_IS_ROOT) || (pid < MUX_MAX_PARENTS)) { + return -EINVAL; + } + + return clk_mux_set_parent(priv, pid, sel); +} + +int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id) +{ + const struct clk_stm32 *clk = _clk_get(priv, clk_id); + const struct parent_cfg *parent; + uint16_t mux_id; + int sel; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + parent = &priv->parents[mux_id]; + + if (clk->ops->get_parent != NULL) { + sel = clk->ops->get_parent(priv, clk_id); + } else { + sel = clk_mux_get_parent(priv, mux_id); + } + + if ((sel >= 0) && (sel < parent->num_parents)) { + return parent->id_parents[sel]; + } + + return -EINVAL; +} + +int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id) +{ + uint16_t mux_id; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + + return clk_mux_get_parent(priv, mux_id); +} + +int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx) +{ + const struct parent_cfg *parent; + uint16_t mux_id; + + mux_id = priv->clks[clk_id].parent; + if (mux_id == CLK_IS_ROOT) { + return CLK_IS_ROOT; + } + + if (mux_id < MUX_MAX_PARENTS) { + return mux_id & MUX_PARENT_MASK; + } + + mux_id &= MUX_PARENT_MASK; + parent = &priv->parents[mux_id]; + + if (idx < parent->num_parents) { + return parent->id_parents[idx]; + } + + return -EINVAL; +} + +int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id) +{ + unsigned int i; + + for (i = 0U; i < priv->num; i++) { + if (binding_id == priv->clks[i].binding) { + return (int)i; + } + } + + return -EINVAL; +} + +unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + int parent; + unsigned long rate = 0UL; + + if ((unsigned int)id >= priv->num) { + return rate; + } + + parent = _clk_stm32_get_parent(priv, id); + if (parent < 0) { + return 0UL; + } + + if (clk->ops->recalc_rate != NULL) { + unsigned long prate = 0UL; + + if (parent != CLK_IS_ROOT) { + prate = _clk_stm32_get_rate(priv, parent); + } + + rate = clk->ops->recalc_rate(priv, id, prate); + + return rate; + } + + switch (parent) { + case CLK_IS_ROOT: + panic(); + + default: + rate = _clk_stm32_get_rate(priv, parent); + break; + } + return rate; + +} + +unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id) +{ + int parent_id = _clk_stm32_get_parent(priv, id); + + if (parent_id < 0) { + return 0UL; + } + + return _clk_stm32_get_rate(priv, parent_id); +} + +static uint8_t _stm32_clk_get_flags(struct stm32_clk_priv *priv, int id) +{ + return priv->clks[id].flags; +} + +bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag) +{ + if (_stm32_clk_get_flags(priv, id) & flag) { + return true; + } + + return false; +} + +int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->enable != NULL) { + clk->ops->enable(priv, id); + } + + return 0; +} + +static int _clk_stm32_enable_core(struct stm32_clk_priv *priv, int id) +{ + int parent; + int ret = 0; + + if (priv->gate_refcounts[id] == 0U) { + parent = _clk_stm32_get_parent(priv, id); + if (parent < 0) { + return parent; + } + if (parent != CLK_IS_ROOT) { + ret = _clk_stm32_enable_core(priv, parent); + if (ret) { + return ret; + } + } + clk_stm32_enable_call_ops(priv, id); + } + + priv->gate_refcounts[id]++; + + if (priv->gate_refcounts[id] == UINT_MAX) { + ERROR("%s: %d max enable count !", __func__, id); + panic(); + } + + return 0; +} + +int _clk_stm32_enable(struct stm32_clk_priv *priv, int id) +{ + int ret; + + stm32mp1_clk_lock(&refcount_lock); + ret = _clk_stm32_enable_core(priv, id); + stm32mp1_clk_unlock(&refcount_lock); + + return ret; +} + +void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->disable != NULL) { + clk->ops->disable(priv, id); + } +} + +static void _clk_stm32_disable_core(struct stm32_clk_priv *priv, int id) +{ + int parent; + + if ((priv->gate_refcounts[id] == 1U) && _stm32_clk_is_flags(priv, id, CLK_IS_CRITICAL)) { + return; + } + + if (priv->gate_refcounts[id] == 0U) { + /* case of clock ignore unused */ + if (_clk_stm32_is_enabled(priv, id)) { + clk_stm32_disable_call_ops(priv, id); + return; + } + VERBOSE("%s: %d already disabled !\n\n", __func__, id); + return; + } + + if (--priv->gate_refcounts[id] > 0U) { + return; + } + + clk_stm32_disable_call_ops(priv, id); + + parent = _clk_stm32_get_parent(priv, id); + if ((parent >= 0) && (parent != CLK_IS_ROOT)) { + _clk_stm32_disable_core(priv, parent); + } +} + +void _clk_stm32_disable(struct stm32_clk_priv *priv, int id) +{ + stm32mp1_clk_lock(&refcount_lock); + + _clk_stm32_disable_core(priv, id); + + stm32mp1_clk_unlock(&refcount_lock); +} + +bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + + if (clk->ops->is_enabled != NULL) { + return clk->ops->is_enabled(priv, id); + } + + return priv->gate_refcounts[id]; +} + +static int clk_stm32_enable(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return id; + } + + return _clk_stm32_enable(priv, id); +} + +static void clk_stm32_disable(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id != -EINVAL) { + _clk_stm32_disable(priv, id); + } +} + +static bool clk_stm32_is_enabled(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return false; + } + + return _clk_stm32_is_enabled(priv, id); +} + +static unsigned long clk_stm32_get_rate(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return 0UL; + } + + return _clk_stm32_get_rate(priv, id); +} + +static int clk_stm32_get_parent(unsigned long binding_id) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int id; + + id = clk_get_index(priv, binding_id); + if (id == -EINVAL) { + return id; + } + + return _clk_stm32_get_parent(priv, id); +} + +static const struct clk_ops stm32mp_clk_ops = { + .enable = clk_stm32_enable, + .disable = clk_stm32_disable, + .is_enabled = clk_stm32_is_enabled, + .get_rate = clk_stm32_get_rate, + .get_parent = clk_stm32_get_parent, +}; + +void clk_stm32_enable_critical_clocks(void) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + unsigned int i; + + for (i = 0U; i < priv->num; i++) { + if (_stm32_clk_is_flags(priv, i, CLK_IS_CRITICAL)) { + _clk_stm32_enable(priv, i); + } + } +} + +static void stm32_clk_register(void) +{ + clk_register(&stm32mp_clk_ops); +} + +uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id) +{ + const struct div_cfg *divider = &priv->div[div_id]; + uint32_t val = 0; + + val = mmio_read_32(priv->base + divider->offset) >> divider->shift; + val &= clk_div_mask(divider->width); + + return val; +} + +unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, + int div_id, + unsigned long prate) +{ + const struct div_cfg *divider = &priv->div[div_id]; + uint32_t val = clk_stm32_div_get_value(priv, div_id); + unsigned int div = 0U; + + div = _get_div(divider->table, val, divider->flags, divider->width); + if (div == 0U) { + return prate; + } + + return div_round_up((uint64_t)prate, div); +} + +unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_div_cfg *div_cfg = clk->clock_cfg; + + return _clk_stm32_divider_recalc(priv, div_cfg->id, prate); +} + +const struct stm32_clk_ops clk_stm32_divider_ops = { + .recalc_rate = clk_stm32_divider_recalc, +}; + +int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) +{ + const struct div_cfg *divider; + uintptr_t address; + uint64_t timeout; + uint32_t mask; + + if (div_id >= priv->nb_div) { + panic(); + } + + divider = &priv->div[div_id]; + address = priv->base + divider->offset; + + mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); + mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); + + if (divider->bitrdy == DIV_NO_BIT_RDY) { + return 0; + } + + timeout = timeout_init_us(CLKSRC_TIMEOUT); + mask = BIT(divider->bitrdy); + + while ((mmio_read_32(address) & mask) == 0U) { + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, + bool ready_on) +{ + const struct gate_cfg *gate = &priv->gates[gate_id]; + uintptr_t address = priv->base + gate->offset; + uint32_t mask_rdy = BIT(gate->bit_idx); + uint64_t timeout; + uint32_t mask_test; + + if (ready_on) { + mask_test = BIT(gate->bit_idx); + } else { + mask_test = 0U; + } + + timeout = timeout_init_us(OSCRDY_TIMEOUT); + + while ((mmio_read_32(address) & mask_rdy) != mask_test) { + if (timeout_elapsed(timeout)) { + break; + } + } + + if ((mmio_read_32(address) & mask_rdy) != mask_test) + return -ETIMEDOUT; + + return 0; +} + +int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + const struct gate_cfg *gate = &priv->gates[cfg->id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr, BIT(gate->bit_idx)); + + } else { + mmio_setbits_32(addr, BIT(gate->bit_idx)); + } + + return 0; +} + +void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + const struct gate_cfg *gate = &priv->gates[cfg->id]; + uintptr_t addr = priv->base + gate->offset; + + if (gate->set_clr != 0U) { + mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); + } else { + mmio_clrbits_32(addr, BIT(gate->bit_idx)); + } +} + +bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id) +{ + const struct gate_cfg *gate; + uint32_t addr; + + gate = &priv->gates[gate_id]; + addr = priv->base + gate->offset; + + return ((mmio_read_32(addr) & BIT(gate->bit_idx)) != 0U); +} + +bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_gate_cfg *cfg = clk->clock_cfg; + + return _clk_stm32_gate_is_enabled(priv, cfg->id); +} + +const struct stm32_clk_ops clk_stm32_gate_ops = { + .enable = clk_stm32_gate_enable, + .disable = clk_stm32_gate_disable, + .is_enabled = clk_stm32_gate_is_enabled, +}; + +const struct stm32_clk_ops clk_fixed_factor_ops = { + .recalc_rate = fixed_factor_recalc_rate, +}; + +unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + const struct fixed_factor_cfg *cfg = clk->clock_cfg; + unsigned long long rate; + + rate = (unsigned long long)prate * cfg->mult; + + if (cfg->div == 0U) { + ERROR("division by zero\n"); + panic(); + } + + return (unsigned long)(rate / cfg->div); +}; + +#define APB_DIV_MASK GENMASK(2, 0) +#define TIM_PRE_MASK BIT(0) + +static unsigned long timer_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + const struct clk_timer_cfg *cfg = clk->clock_cfg; + uint32_t prescaler, timpre; + uintptr_t rcc_base = priv->base; + + prescaler = mmio_read_32(rcc_base + cfg->apbdiv) & + APB_DIV_MASK; + + timpre = mmio_read_32(rcc_base + cfg->timpre) & + TIM_PRE_MASK; + + if (prescaler == 0U) { + return prate; + } + + return prate * (timpre + 1U) * 2U; +}; + +const struct stm32_clk_ops clk_timer_ops = { + .recalc_rate = timer_recalc_rate, +}; + +static unsigned long clk_fixed_rate_recalc(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct clk_stm32_fixed_rate_cfg *cfg = clk->clock_cfg; + + return cfg->rate; +} + +const struct stm32_clk_ops clk_stm32_fixed_rate_ops = { + .recalc_rate = clk_fixed_rate_recalc, +}; + +static unsigned long clk_stm32_osc_recalc_rate(struct stm32_clk_priv *priv, + int id, unsigned long prate) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return osc_data->frequency; +}; + +bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + return _clk_stm32_gate_is_enabled(priv, osc_data->gate_id); + +} + +int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + _clk_stm32_gate_enable(priv, osc_data->gate_id); + + if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, true) != 0U) { + ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__); + panic(); + } + + return 0; +} + +void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + + _clk_stm32_gate_disable(priv, osc_data->gate_id); + + if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, false) != 0U) { + ERROR("%s: %s (%d)\n", __func__, osc_data->name, __LINE__); + panic(); + } +} + +static unsigned long clk_stm32_get_dt_oscillator_frequency(const char *name) +{ + void *fdt = NULL; + int node = 0; + int subnode = 0; + + if (fdt_get_address(&fdt) == 0) { + panic(); + } + + node = fdt_path_offset(fdt, "/clocks"); + if (node < 0) { + return 0UL; + } + + fdt_for_each_subnode(subnode, fdt, node) { + const char *cchar = NULL; + const fdt32_t *cuint = NULL; + int ret = 0; + + cchar = fdt_get_name(fdt, subnode, &ret); + if (cchar == NULL) { + continue; + } + + if (strncmp(cchar, name, (size_t)ret) || + fdt_get_status(subnode) == DT_DISABLED) { + continue; + } + + cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); + if (cuint == NULL) { + return 0UL; + } + + return fdt32_to_cpu(*cuint); + } + + return 0UL; +} + +void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id); + const char *name = osc_data->name; + + osc_data->frequency = clk_stm32_get_dt_oscillator_frequency(name); +} + +const struct stm32_clk_ops clk_stm32_osc_ops = { + .recalc_rate = clk_stm32_osc_recalc_rate, + .is_enabled = clk_stm32_osc_gate_is_enabled, + .enable = clk_stm32_osc_gate_enable, + .disable = clk_stm32_osc_gate_disable, + .init = clk_stm32_osc_init, +}; + +const struct stm32_clk_ops clk_stm32_osc_nogate_ops = { + .recalc_rate = clk_stm32_osc_recalc_rate, + .init = clk_stm32_osc_init, +}; + +int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb) +{ + const fdt32_t *cell; + int len = 0; + uint32_t i; + + cell = fdt_getprop(fdt, node, name, &len); + if (cell == NULL) { + *nb = 0U; + return 0; + } + + for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { + uint32_t val = fdt32_to_cpu(cell[i]); + + tab[i] = val; + } + + *nb = (uint32_t)len / sizeof(uint32_t); + + return 0; +} + +int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base) +{ + unsigned int i; + + stm32_clock_data = priv; + + priv->base = base; + + for (i = 0U; i < priv->num; i++) { + const struct clk_stm32 *clk = _clk_get(priv, i); + + assert(clk->ops != NULL); + + if (clk->ops->init != NULL) { + clk->ops->init(priv, i); + } + } + + stm32_clk_register(); + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/st/clk/clk-stm32-core.h 2.7.0+dfsg-2/drivers/st/clk/clk-stm32-core.h --- 2.6+dfsg-1/drivers/st/clk/clk-stm32-core.h 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/clk/clk-stm32-core.h 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,405 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef CLK_STM32_CORE_H +#define CLK_STM32_CORE_H + +struct mux_cfg { + uint16_t offset; + uint8_t shift; + uint8_t width; + uint8_t bitrdy; +}; + +struct gate_cfg { + uint16_t offset; + uint8_t bit_idx; + uint8_t set_clr; +}; + +struct clk_div_table { + unsigned int val; + unsigned int div; +}; + +struct div_cfg { + uint16_t offset; + uint8_t shift; + uint8_t width; + uint8_t flags; + uint8_t bitrdy; + const struct clk_div_table *table; +}; + +struct parent_cfg { + uint8_t num_parents; + const uint16_t *id_parents; + struct mux_cfg *mux; +}; + +struct stm32_clk_priv; + +struct stm32_clk_ops { + unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate); + int (*get_parent)(struct stm32_clk_priv *priv, int id); + int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate, + unsigned long prate); + int (*enable)(struct stm32_clk_priv *priv, int id); + void (*disable)(struct stm32_clk_priv *priv, int id); + bool (*is_enabled)(struct stm32_clk_priv *priv, int id); + void (*init)(struct stm32_clk_priv *priv, int id); +}; + +struct clk_stm32 { + const char *name; + uint16_t binding; + uint16_t parent; + uint8_t flags; + void *clock_cfg; + const struct stm32_clk_ops *ops; +}; + +struct stm32_clk_priv { + uintptr_t base; + const uint32_t num; + const struct clk_stm32 *clks; + const struct parent_cfg *parents; + const uint32_t nb_parents; + const struct gate_cfg *gates; + const uint32_t nb_gates; + const struct div_cfg *div; + const uint32_t nb_div; + struct clk_oscillator_data *osci_data; + const uint32_t nb_osci_data; + uint32_t *gate_refcounts; + void *pdata; +}; + +struct stm32_clk_bypass { + uint16_t offset; + uint8_t bit_byp; + uint8_t bit_digbyp; +}; + +struct stm32_clk_css { + uint16_t offset; + uint8_t bit_css; +}; + +struct stm32_clk_drive { + uint16_t offset; + uint8_t drv_shift; + uint8_t drv_width; + uint8_t drv_default; +}; + +struct clk_oscillator_data { + const char *name; + uint16_t id_clk; + unsigned long frequency; + uint16_t gate_id; + uint16_t gate_rdy_id; + struct stm32_clk_bypass *bypass; + struct stm32_clk_css *css; + struct stm32_clk_drive *drive; +}; + +struct clk_fixed_rate { + const char *name; + unsigned long fixed_rate; +}; + +struct clk_gate_cfg { + uint32_t offset; + uint8_t bit_idx; +}; + +/* CLOCK FLAGS */ +#define CLK_IS_CRITICAL BIT(0) +#define CLK_IGNORE_UNUSED BIT(1) +#define CLK_SET_RATE_PARENT BIT(2) + +#define CLK_DIVIDER_ONE_BASED BIT(0) +#define CLK_DIVIDER_POWER_OF_TWO BIT(1) +#define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) +#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) +#define CLK_DIVIDER_READ_ONLY BIT(5) +#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_DIVIDER_BIG_ENDIAN BIT(7) + +#define MUX_MAX_PARENTS U(0x8000) +#define MUX_PARENT_MASK GENMASK(14, 0) +#define MUX_FLAG U(0x8000) +#define MUX(mux) ((mux) | MUX_FLAG) + +#define NO_GATE 0 +#define _NO_ID UINT16_MAX +#define CLK_IS_ROOT UINT16_MAX +#define MUX_NO_BIT_RDY UINT8_MAX +#define DIV_NO_BIT_RDY UINT8_MAX + +#define MASK_WIDTH_SHIFT(_width, _shift) \ + GENMASK(((_width) + (_shift) - 1U), (_shift)) + +int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base); +void clk_stm32_enable_critical_clocks(void); + +struct stm32_clk_priv *clk_stm32_get_priv(void); + +int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id); +const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id); + +void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass); +void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv); +void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css); + +int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on); + +int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on); +int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id); +int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id); + +const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id); +const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id); +int clk_stm32_get_counter(unsigned long binding_id); + +void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); +int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id); + +int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id); +int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel); + +int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id); +int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx); +int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id); + +unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id); +unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id); + +bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag); + +int _clk_stm32_enable(struct stm32_clk_priv *priv, int id); +void _clk_stm32_disable(struct stm32_clk_priv *priv, int id); + +int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id); +void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id); + +bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id); + +int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id, + unsigned long rate, unsigned long parent_rate); + +int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, + unsigned long prate); + +unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, + int div_id, + unsigned long prate); + +unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx, + unsigned long prate); + +int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx); +void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx); + +bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id); +bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx); + +uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id); +int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value); +int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel); +int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id); + +int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb); + +#ifdef CFG_STM32_CLK_DEBUG +void clk_stm32_display_clock_info(void); +#endif + +struct clk_stm32_div_cfg { + int id; +}; + +#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_div_cfg){\ + .id = (_div_id),\ + },\ + .ops = &clk_stm32_divider_ops,\ + } + +struct clk_stm32_gate_cfg { + int id; +}; + +#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_gate_cfg){\ + .id = (_gate_id),\ + },\ + .ops = &clk_stm32_gate_ops,\ + } + +struct fixed_factor_cfg { + unsigned int mult; + unsigned int div; +}; + +unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, + int _idx, unsigned long prate); + +#define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .clock_cfg = &(struct fixed_factor_cfg){\ + .mult = (_mult),\ + .div = (_div),\ + },\ + .ops = &clk_fixed_factor_ops,\ + } + +#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_gate_cfg){\ + .offset = (_offset),\ + .bit_idx = (_bit_idx),\ + },\ + .ops = &clk_gate_ops,\ + } + +#define STM32_MUX(idx, _binding, _mux_id, _flags) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (MUX(_mux_id)),\ + .flags = (_flags),\ + .clock_cfg = NULL,\ + .ops = (&clk_mux_ops),\ + } + +struct clk_timer_cfg { + uint32_t apbdiv; + uint32_t timpre; +}; + +#define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = (CLK_SET_RATE_PARENT | (_flags)),\ + .clock_cfg = &(struct clk_timer_cfg){\ + .apbdiv = (_apbdiv),\ + .timpre = (_timpre),\ + },\ + .ops = &clk_timer_ops,\ + } + +struct clk_stm32_fixed_rate_cfg { + unsigned long rate; +}; + +#define CLK_FIXED_RATE(idx, _binding, _rate) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_binding),\ + .parent = (CLK_IS_ROOT),\ + .clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ + .rate = (_rate),\ + },\ + .ops = &clk_stm32_fixed_rate_ops,\ + } + +#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\ + .offset = (_offset),\ + .bit_byp = (_bit_byp),\ + .bit_digbyp = (_bit_digbyp),\ +} + +#define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ + .offset = (_offset),\ + .bit_css = (_bit_css),\ +} + +#define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\ + .offset = (_offset),\ + .drv_shift = (_shift),\ + .drv_width = (_width),\ + .drv_default = (_default),\ +} + +#define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ + [(idx_osc)] = (struct clk_oscillator_data){\ + .name = (_name),\ + .id_clk = (_id),\ + .gate_id = (_gate_id),\ + .gate_rdy_id = (_gate_rdy_id),\ + .bypass = (_bypass),\ + .css = (_css),\ + .drive = (_drive),\ + } + +struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id); + +void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id); +bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id); +int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id); +void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id); + +struct stm32_osc_cfg { + int osc_id; +}; + +#define CLK_OSC(idx, _idx, _parent, _osc_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = CLK_IS_CRITICAL,\ + .clock_cfg = &(struct stm32_osc_cfg){\ + .osc_id = (_osc_id),\ + },\ + .ops = &clk_stm32_osc_ops,\ + } + +#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ + [(idx)] = (struct clk_stm32){ \ + .name = #idx,\ + .binding = (_idx),\ + .parent = (_parent),\ + .flags = CLK_IS_CRITICAL,\ + .clock_cfg = &(struct stm32_osc_cfg){\ + .osc_id = (_osc_id),\ + },\ + .ops = &clk_stm32_osc_nogate_ops,\ + } + +extern const struct stm32_clk_ops clk_mux_ops; +extern const struct stm32_clk_ops clk_stm32_divider_ops; +extern const struct stm32_clk_ops clk_stm32_gate_ops; +extern const struct stm32_clk_ops clk_fixed_factor_ops; +extern const struct stm32_clk_ops clk_gate_ops; +extern const struct stm32_clk_ops clk_timer_ops; +extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops; +extern const struct stm32_clk_ops clk_stm32_osc_ops; +extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops; + +#endif /* CLK_STM32_CORE_H */ diff -pruN 2.6+dfsg-1/drivers/st/clk/clk-stm32mp13.c 2.7.0+dfsg-2/drivers/st/clk/clk-stm32mp13.c --- 2.6+dfsg-1/drivers/st/clk/clk-stm32mp13.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/clk/clk-stm32mp13.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,2334 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include +#include +#include "clk-stm32-core.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct stm32_osci_dt_cfg { + unsigned long freq; + bool bypass; + bool digbyp; + bool css; + uint32_t drive; +}; + +enum pll_mn { + PLL_CFG_M, + PLL_CFG_N, + PLL_DIV_MN_NB +}; + +enum pll_pqr { + PLL_CFG_P, + PLL_CFG_Q, + PLL_CFG_R, + PLL_DIV_PQR_NB +}; + +enum pll_csg { + PLL_CSG_MOD_PER, + PLL_CSG_INC_STEP, + PLL_CSG_SSCG_MODE, + PLL_CSG_NB +}; + +struct stm32_pll_vco { + uint32_t status; + uint32_t src; + uint32_t div_mn[PLL_DIV_MN_NB]; + uint32_t frac; + bool csg_enabled; + uint32_t csg[PLL_CSG_NB]; +}; + +struct stm32_pll_output { + uint32_t output[PLL_DIV_PQR_NB]; +}; + +struct stm32_pll_dt_cfg { + struct stm32_pll_vco vco; + struct stm32_pll_output output; +}; + +struct stm32_clk_platdata { + uint32_t nosci; + struct stm32_osci_dt_cfg *osci; + uint32_t npll; + struct stm32_pll_dt_cfg *pll; + uint32_t nclksrc; + uint32_t *clksrc; + uint32_t nclkdiv; + uint32_t *clkdiv; +}; + +enum stm32_clock { + /* ROOT CLOCKS */ + _CK_OFF, + _CK_HSI, + _CK_HSE, + _CK_CSI, + _CK_LSI, + _CK_LSE, + _I2SCKIN, + _CSI_DIV122, + _HSE_DIV, + _HSE_DIV2, + _CK_PLL1, + _CK_PLL2, + _CK_PLL3, + _CK_PLL4, + _PLL1P, + _PLL1P_DIV, + _PLL2P, + _PLL2Q, + _PLL2R, + _PLL3P, + _PLL3Q, + _PLL3R, + _PLL4P, + _PLL4Q, + _PLL4R, + _PCLK1, + _PCLK2, + _PCLK3, + _PCLK4, + _PCLK5, + _PCLK6, + _CKMPU, + _CKAXI, + _CKMLAHB, + _CKPER, + _CKTIMG1, + _CKTIMG2, + _CKTIMG3, + _USB_PHY_48, + _MCO1_K, + _MCO2_K, + _TRACECK, + /* BUS and KERNEL CLOCKS */ + _DDRC1, + _DDRC1LP, + _DDRPHYC, + _DDRPHYCLP, + _DDRCAPB, + _DDRCAPBLP, + _AXIDCG, + _DDRPHYCAPB, + _DDRPHYCAPBLP, + _SYSCFG, + _DDRPERFM, + _IWDG2APB, + _USBPHY_K, + _USBO_K, + _RTCAPB, + _TZC, + _ETZPC, + _IWDG1APB, + _BSEC, + _STGENC, + _USART1_K, + _USART2_K, + _I2C3_K, + _I2C4_K, + _I2C5_K, + _TIM12, + _TIM15, + _RTCCK, + _GPIOA, + _GPIOB, + _GPIOC, + _GPIOD, + _GPIOE, + _GPIOF, + _GPIOG, + _GPIOH, + _GPIOI, + _PKA, + _SAES_K, + _CRYP1, + _HASH1, + _RNG1_K, + _BKPSRAM, + _SDMMC1_K, + _SDMMC2_K, + _DBGCK, + _USART3_K, + _UART4_K, + _UART5_K, + _UART7_K, + _UART8_K, + _USART6_K, + _MCE, + _FMC_K, + _QSPI_K, +#if defined(IMAGE_BL32) + _LTDC, + _DMA1, + _DMA2, + _MDMA, + _ETH1MAC, + _USBH, + _TIM2, + _TIM3, + _TIM4, + _TIM5, + _TIM6, + _TIM7, + _LPTIM1_K, + _SPI2_K, + _SPI3_K, + _SPDIF_K, + _TIM1, + _TIM8, + _SPI1_K, + _SAI1_K, + _SAI2_K, + _DFSDM, + _FDCAN_K, + _TIM13, + _TIM14, + _TIM16, + _TIM17, + _SPI4_K, + _SPI5_K, + _I2C1_K, + _I2C2_K, + _ADFSDM, + _LPTIM2_K, + _LPTIM3_K, + _LPTIM4_K, + _LPTIM5_K, + _VREF, + _DTS, + _PMBCTRL, + _HDP, + _STGENRO, + _DCMIPP_K, + _DMAMUX1, + _DMAMUX2, + _DMA3, + _ADC1_K, + _ADC2_K, + _TSC, + _AXIMC, + _ETH1CK, + _ETH1TX, + _ETH1RX, + _CRC1, + _ETH2CK, + _ETH2TX, + _ETH2RX, + _ETH2MAC, +#endif + CK_LAST +}; + +/* PARENT CONFIG */ +static const uint16_t RTC_src[] = { + _CK_OFF, _CK_LSE, _CK_LSI, _CK_HSE +}; + +static const uint16_t MCO1_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _CK_LSI, _CK_LSE +}; + +static const uint16_t MCO2_src[] = { + _CKMPU, _CKAXI, _CKMLAHB, _PLL4P, _CK_HSE, _CK_HSI +}; + +static const uint16_t PLL12_src[] = { + _CK_HSI, _CK_HSE +}; + +static const uint16_t PLL3_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI +}; + +static const uint16_t PLL4_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _I2SCKIN +}; + +static const uint16_t MPU_src[] = { + _CK_HSI, _CK_HSE, _PLL1P, _PLL1P_DIV +}; + +static const uint16_t AXI_src[] = { + _CK_HSI, _CK_HSE, _PLL2P +}; + +static const uint16_t MLAHBS_src[] = { + _CK_HSI, _CK_HSE, _CK_CSI, _PLL3P +}; + +static const uint16_t CKPER_src[] = { + _CK_HSI, _CK_CSI, _CK_HSE, _CK_OFF +}; + +static const uint16_t I2C12_src[] = { + _PCLK1, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C3_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C4_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t I2C5_src[] = { + _PCLK6, _PLL4R, _CK_HSI, _CK_CSI +}; + +static const uint16_t SPI1_src[] = { + _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SPI23_src[] = { + _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SPI4_src[] = { + _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE, _I2SCKIN +}; + +static const uint16_t SPI5_src[] = { + _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART1_src[] = { + _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE +}; + +static const uint16_t UART2_src[] = { + _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE +}; + +static const uint16_t UART35_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART4_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART6_src[] = { + _PCLK2, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t UART78_src[] = { + _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE +}; + +static const uint16_t LPTIM1_src[] = { + _PCLK1, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER +}; + +static const uint16_t LPTIM2_src[] = { + _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI +}; + +static const uint16_t LPTIM3_src[] = { + _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI +}; + +static const uint16_t LPTIM45_src[] = { + _PCLK3, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER +}; + +static const uint16_t SAI1_src[] = { + _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R +}; + +static const uint16_t SAI2_src[] = { + _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _NO_ID, _PLL3R +}; + +static const uint16_t FDCAN_src[] = { + _CK_HSE, _PLL3Q, _PLL4Q, _PLL4R +}; + +static const uint16_t SPDIF_src[] = { + _PLL4P, _PLL3Q, _CK_HSI +}; + +static const uint16_t ADC1_src[] = { + _PLL4R, _CKPER, _PLL3Q +}; + +static const uint16_t ADC2_src[] = { + _PLL4R, _CKPER, _PLL3Q +}; + +static const uint16_t SDMMC1_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CK_HSI +}; + +static const uint16_t SDMMC2_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CK_HSI +}; + +static const uint16_t ETH1_src[] = { + _PLL4P, _PLL3Q +}; + +static const uint16_t ETH2_src[] = { + _PLL4P, _PLL3Q +}; + +static const uint16_t USBPHY_src[] = { + _CK_HSE, _PLL4R, _HSE_DIV2 +}; + +static const uint16_t USBO_src[] = { + _PLL4R, _USB_PHY_48 +}; + +static const uint16_t QSPI_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CKPER +}; + +static const uint16_t FMC_src[] = { + _CKAXI, _PLL3R, _PLL4P, _CKPER +}; + +/* Position 2 of RNG1 mux is reserved */ +static const uint16_t RNG1_src[] = { + _CK_CSI, _PLL4R, _CK_OFF, _CK_LSI +}; + +static const uint16_t STGEN_src[] = { + _CK_HSI, _CK_HSE +}; + +static const uint16_t DCMIPP_src[] = { + _CKAXI, _PLL2Q, _PLL4P, _CKPER +}; + +static const uint16_t SAES_src[] = { + _CKAXI, _CKPER, _PLL4R, _CK_LSI +}; + +#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .id_parents = src,\ + .num_parents = ARRAY_SIZE(src),\ + .mux = &(struct mux_cfg) {\ + .offset = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ + .bitrdy = MUX_NO_BIT_RDY,\ + },\ +} + +#define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .id_parents = src,\ + .num_parents = ARRAY_SIZE(src),\ + .mux = &(struct mux_cfg) {\ + .offset = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ + .bitrdy = 31,\ + },\ +} + +static const struct parent_cfg parent_mp13[] = { + MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2), + MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2), + MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3), + MUX_CFG(MUX_CKPER, CKPER_src, RCC_CPERCKSELR, 0, 2), + MUX_CFG(MUX_DCMIPP, DCMIPP_src, RCC_DCMIPPCKSELR, 0, 2), + MUX_CFG(MUX_ETH1, ETH1_src, RCC_ETH12CKSELR, 0, 2), + MUX_CFG(MUX_ETH2, ETH2_src, RCC_ETH12CKSELR, 8, 2), + MUX_CFG(MUX_FDCAN, FDCAN_src, RCC_FDCANCKSELR, 0, 2), + MUX_CFG(MUX_FMC, FMC_src, RCC_FMCCKSELR, 0, 2), + MUX_CFG(MUX_I2C12, I2C12_src, RCC_I2C12CKSELR, 0, 3), + MUX_CFG(MUX_I2C3, I2C3_src, RCC_I2C345CKSELR, 0, 3), + MUX_CFG(MUX_I2C4, I2C4_src, RCC_I2C345CKSELR, 3, 3), + MUX_CFG(MUX_I2C5, I2C5_src, RCC_I2C345CKSELR, 6, 3), + MUX_CFG(MUX_LPTIM1, LPTIM1_src, RCC_LPTIM1CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM2, LPTIM2_src, RCC_LPTIM23CKSELR, 0, 3), + MUX_CFG(MUX_LPTIM3, LPTIM3_src, RCC_LPTIM23CKSELR, 3, 3), + MUX_CFG(MUX_LPTIM45, LPTIM45_src, RCC_LPTIM45CKSELR, 0, 3), + MUX_CFG(MUX_MCO1, MCO1_src, RCC_MCO1CFGR, 0, 3), + MUX_CFG(MUX_MCO2, MCO2_src, RCC_MCO2CFGR, 0, 3), + MUX_RDY_CFG(MUX_MLAHB, MLAHBS_src, RCC_MSSCKSELR, 0, 2), + MUX_RDY_CFG(MUX_MPU, MPU_src, RCC_MPCKSELR, 0, 2), + MUX_RDY_CFG(MUX_PLL12, PLL12_src, RCC_RCK12SELR, 0, 2), + MUX_RDY_CFG(MUX_PLL3, PLL3_src, RCC_RCK3SELR, 0, 2), + MUX_RDY_CFG(MUX_PLL4, PLL4_src, RCC_RCK4SELR, 0, 2), + MUX_CFG(MUX_QSPI, QSPI_src, RCC_QSPICKSELR, 0, 2), + MUX_CFG(MUX_RNG1, RNG1_src, RCC_RNG1CKSELR, 0, 2), + MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2), + MUX_CFG(MUX_SAES, SAES_src, RCC_SAESCKSELR, 0, 2), + MUX_CFG(MUX_SAI1, SAI1_src, RCC_SAI1CKSELR, 0, 3), + MUX_CFG(MUX_SAI2, SAI2_src, RCC_SAI2CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC1, SDMMC1_src, RCC_SDMMC12CKSELR, 0, 3), + MUX_CFG(MUX_SDMMC2, SDMMC2_src, RCC_SDMMC12CKSELR, 3, 3), + MUX_CFG(MUX_SPDIF, SPDIF_src, RCC_SPDIFCKSELR, 0, 2), + MUX_CFG(MUX_SPI1, SPI1_src, RCC_SPI2S1CKSELR, 0, 3), + MUX_CFG(MUX_SPI23, SPI23_src, RCC_SPI2S23CKSELR, 0, 3), + MUX_CFG(MUX_SPI4, SPI4_src, RCC_SPI45CKSELR, 0, 3), + MUX_CFG(MUX_SPI5, SPI5_src, RCC_SPI45CKSELR, 3, 3), + MUX_CFG(MUX_STGEN, STGEN_src, RCC_STGENCKSELR, 0, 2), + MUX_CFG(MUX_UART1, UART1_src, RCC_UART12CKSELR, 0, 3), + MUX_CFG(MUX_UART2, UART2_src, RCC_UART12CKSELR, 3, 3), + MUX_CFG(MUX_UART35, UART35_src, RCC_UART35CKSELR, 0, 3), + MUX_CFG(MUX_UART4, UART4_src, RCC_UART4CKSELR, 0, 3), + MUX_CFG(MUX_UART6, UART6_src, RCC_UART6CKSELR, 0, 3), + MUX_CFG(MUX_UART78, UART78_src, RCC_UART78CKSELR, 0, 3), + MUX_CFG(MUX_USBO, USBO_src, RCC_USBCKSELR, 4, 1), + MUX_CFG(MUX_USBPHY, USBPHY_src, RCC_USBCKSELR, 0, 2), +}; + +/* + * GATE CONFIG + */ + +enum enum_gate_cfg { + GATE_ZERO, /* reserved for no gate */ + GATE_LSE, + GATE_RTCCK, + GATE_LSI, + GATE_HSI, + GATE_CSI, + GATE_HSE, + GATE_LSI_RDY, + GATE_CSI_RDY, + GATE_LSE_RDY, + GATE_HSE_RDY, + GATE_HSI_RDY, + GATE_MCO1, + GATE_MCO2, + GATE_DBGCK, + GATE_TRACECK, + GATE_PLL1, + GATE_PLL1_DIVP, + GATE_PLL1_DIVQ, + GATE_PLL1_DIVR, + GATE_PLL2, + GATE_PLL2_DIVP, + GATE_PLL2_DIVQ, + GATE_PLL2_DIVR, + GATE_PLL3, + GATE_PLL3_DIVP, + GATE_PLL3_DIVQ, + GATE_PLL3_DIVR, + GATE_PLL4, + GATE_PLL4_DIVP, + GATE_PLL4_DIVQ, + GATE_PLL4_DIVR, + GATE_DDRC1, + GATE_DDRC1LP, + GATE_DDRPHYC, + GATE_DDRPHYCLP, + GATE_DDRCAPB, + GATE_DDRCAPBLP, + GATE_AXIDCG, + GATE_DDRPHYCAPB, + GATE_DDRPHYCAPBLP, + GATE_TIM2, + GATE_TIM3, + GATE_TIM4, + GATE_TIM5, + GATE_TIM6, + GATE_TIM7, + GATE_LPTIM1, + GATE_SPI2, + GATE_SPI3, + GATE_USART3, + GATE_UART4, + GATE_UART5, + GATE_UART7, + GATE_UART8, + GATE_I2C1, + GATE_I2C2, + GATE_SPDIF, + GATE_TIM1, + GATE_TIM8, + GATE_SPI1, + GATE_USART6, + GATE_SAI1, + GATE_SAI2, + GATE_DFSDM, + GATE_ADFSDM, + GATE_FDCAN, + GATE_LPTIM2, + GATE_LPTIM3, + GATE_LPTIM4, + GATE_LPTIM5, + GATE_VREF, + GATE_DTS, + GATE_PMBCTRL, + GATE_HDP, + GATE_SYSCFG, + GATE_DCMIPP, + GATE_DDRPERFM, + GATE_IWDG2APB, + GATE_USBPHY, + GATE_STGENRO, + GATE_LTDC, + GATE_RTCAPB, + GATE_TZC, + GATE_ETZPC, + GATE_IWDG1APB, + GATE_BSEC, + GATE_STGENC, + GATE_USART1, + GATE_USART2, + GATE_SPI4, + GATE_SPI5, + GATE_I2C3, + GATE_I2C4, + GATE_I2C5, + GATE_TIM12, + GATE_TIM13, + GATE_TIM14, + GATE_TIM15, + GATE_TIM16, + GATE_TIM17, + GATE_DMA1, + GATE_DMA2, + GATE_DMAMUX1, + GATE_DMA3, + GATE_DMAMUX2, + GATE_ADC1, + GATE_ADC2, + GATE_USBO, + GATE_TSC, + GATE_GPIOA, + GATE_GPIOB, + GATE_GPIOC, + GATE_GPIOD, + GATE_GPIOE, + GATE_GPIOF, + GATE_GPIOG, + GATE_GPIOH, + GATE_GPIOI, + GATE_PKA, + GATE_SAES, + GATE_CRYP1, + GATE_HASH1, + GATE_RNG1, + GATE_BKPSRAM, + GATE_AXIMC, + GATE_MCE, + GATE_ETH1CK, + GATE_ETH1TX, + GATE_ETH1RX, + GATE_ETH1MAC, + GATE_FMC, + GATE_QSPI, + GATE_SDMMC1, + GATE_SDMMC2, + GATE_CRC1, + GATE_USBH, + GATE_ETH2CK, + GATE_ETH2TX, + GATE_ETH2RX, + GATE_ETH2MAC, + GATE_MDMA, + + LAST_GATE +}; + +#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ + .offset = (_offset),\ + .bit_idx = (_bit_idx),\ + .set_clr = (_offset_clr),\ +} + +static const struct gate_cfg gates_mp13[LAST_GATE] = { + GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), + GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), + GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0), + GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), + GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1), + GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), + GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0), + GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0), + GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), + GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), + GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), + GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0), + GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0), + GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0), + GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0), + GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0), + GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0), + GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0), + GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0), + GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0), + GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0), + GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0), + GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0), + GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0), + GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0), + GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0), + GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0), + GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0), + GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0), + GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0), + GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0), + GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0), + GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0), + GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0), + GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0), + GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0), + GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0), + GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0), + GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0), + GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0), + GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1), + GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1), + GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1), + GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1), + GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1), + GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1), + GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1), + GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1), + GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1), + GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1), + GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1), + GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1), + GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1), + GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1), + GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1), + GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1), + GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1), + GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1), + GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1), + GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1), + GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1), + GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1), + GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1), + GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1), + GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1), + GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1), + GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1), + GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1), + GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1), + GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1), + GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1), + GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1), + GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1), + GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1), + GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1), + GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1), + GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1), + GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1), + GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1), + GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1), + GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1), + GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1), + GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1), + GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1), + GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1), + GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1), + GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1), + GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1), + GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1), + GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1), + GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1), + GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1), + GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1), + GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1), + GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1), + GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1), + GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1), + GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1), + GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1), + GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1), + GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1), + GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1), + GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1), + GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1), + GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1), + GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1), + GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1), + GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1), + GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1), + + GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1), + GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1), + GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1), + GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1), + GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1), + GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1), + GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1), + GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1), + GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1), + + GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1), + GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1), + GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1), + GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1), + GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1), + GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1), + GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1), + GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1), + GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1), + GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1), + GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1), + GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1), + GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1), + GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1), + GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1), + GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1), + GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1), + GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1), + GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1), + GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1), + GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1), + GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1), + GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1), +}; + +/* + * DIV CONFIG + */ + +static const struct clk_div_table axi_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 }, + { 0 }, +}; + +static const struct clk_div_table mlahb_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 }, + { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 }, + { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 }, + { 0 }, +}; + +static const struct clk_div_table apb_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, + { 0 }, +}; + +#define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ + .offset = _offset,\ + .shift = _shift,\ + .width = _width,\ + .flags = _flags,\ + .table = _table,\ + .bitrdy = _bitrdy,\ +} + +static const struct div_cfg dividers_mp13[] = { + DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 31), + DIV_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 31), + DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 31), + DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + + DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), + + DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), + DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_BIT_RDY), +}; + +#define MAX_HSI_HZ 64000000 +#define USB_PHY_48_MHZ 48000000 + +#define TIMEOUT_US_200MS U(200000) +#define TIMEOUT_US_1S U(1000000) + +#define PLLRDY_TIMEOUT TIMEOUT_US_200MS +#define CLKSRC_TIMEOUT TIMEOUT_US_200MS +#define CLKDIV_TIMEOUT TIMEOUT_US_200MS +#define HSIDIV_TIMEOUT TIMEOUT_US_200MS +#define OSCRDY_TIMEOUT TIMEOUT_US_1S + +enum stm32_osc { + OSC_HSI, + OSC_HSE, + OSC_CSI, + OSC_LSI, + OSC_LSE, + OSC_I2SCKIN, + NB_OSCILLATOR +}; + +enum stm32mp1_pll_id { + _PLL1, + _PLL2, + _PLL3, + _PLL4, + _PLL_NB +}; + +enum stm32mp1_plltype { + PLL_800, + PLL_1600, + PLL_2000, + PLL_TYPE_NB +}; + +#define RCC_OFFSET_PLLXCR 0 +#define RCC_OFFSET_PLLXCFGR1 4 +#define RCC_OFFSET_PLLXCFGR2 8 +#define RCC_OFFSET_PLLXFRACR 12 +#define RCC_OFFSET_PLLXCSGR 16 + +struct stm32_clk_pll { + enum stm32mp1_plltype plltype; + uint16_t clk_id; + uint16_t reg_pllxcr; +}; + +struct stm32mp1_pll { + uint8_t refclk_min; + uint8_t refclk_max; +}; + +/* Define characteristic of PLL according type */ +static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { + [PLL_800] = { + .refclk_min = 4, + .refclk_max = 16, + }, + [PLL_1600] = { + .refclk_min = 8, + .refclk_max = 16, + }, + [PLL_2000] = { + .refclk_min = 8, + .refclk_max = 16, + }, +}; + +#if STM32MP_USB_PROGRAMMER +static bool pll4_bootrom; +#endif + +/* RCC clock device driver private */ +static unsigned int refcounts_mp13[CK_LAST]; + +static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx); + +#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER +static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx, + bool digbyp, bool bypass) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx); + struct stm32_clk_bypass *bypass_data = osc_data->bypass; + uintptr_t address; + + if (bypass_data == NULL) { + return; + } + + address = priv->base + bypass_data->offset; + if ((mmio_read_32(address) & RCC_OCENR_HSEBYP) && + (!(digbyp || bypass))) { + panic(); + } +} +#endif + +static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; + bool digbyp = osci->digbyp; + bool bypass = osci->bypass; + bool css = osci->css; + + if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { + return; + } + + clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); + + _clk_stm32_enable(priv, _CK_HSE); + +#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER + clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass); +#endif + + clk_oscillator_set_css(priv, _CK_HSE, css); +} + +static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) +{ + struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; + bool digbyp = osci->digbyp; + bool bypass = osci->bypass; + uint8_t drive = osci->drive; + + if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { + return; + } + + clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); + + clk_oscillator_set_drive(priv, _CK_LSE, drive); + + _clk_stm32_gate_enable(priv, osc_data->gate_id); +} + +static int stm32mp1_set_hsidiv(uint8_t hsidiv) +{ + uint64_t timeout; + uintptr_t rcc_base = stm32mp_rcc_base(); + uintptr_t address = rcc_base + RCC_OCRDYR; + + mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, + RCC_HSICFGR_HSIDIV_MASK, + RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); + + timeout = timeout_init_us(HSIDIV_TIMEOUT); + while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", + address, mmio_read_32(address)); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int stm32mp1_hsidiv(unsigned long hsifreq) +{ + uint8_t hsidiv; + uint32_t hsidivfreq = MAX_HSI_HZ; + + for (hsidiv = 0; hsidiv < 4U; hsidiv++) { + if (hsidivfreq == hsifreq) { + break; + } + + hsidivfreq /= 2U; + } + + if (hsidiv == 4U) { + ERROR("Invalid clk-hsi frequency\n"); + return -EINVAL; + } + + if (hsidiv != 0U) { + return stm32mp1_set_hsidiv(hsidiv); + } + + return 0; +} + +static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; + + clk_oscillator_set_css(priv, _CK_LSE, osci->css); + + return 0; +} + +static int stm32mp1_come_back_to_hsi(void) +{ + int ret; + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + + /* Come back to HSI */ + ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI); + if (ret != 0) { + return ret; + } + + ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI); + if (ret != 0) { + return ret; + } + + ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI); + if (ret != 0) { + return ret; + } + + return 0; +} + +static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) +{ + unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; + + return clk_get_index(priv, binding_id); +} + +static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) +{ + int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; + int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; + int clk_id; + int ret; + + clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); + if (clk_id < 0) { + return clk_id; + } + + ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); + if (ret != 0) { + return ret; + } + + if (enable) { + clk_stm32_enable_call_ops(priv, clk_id); + } else { + clk_stm32_disable_call_ops(priv, clk_id); + } + + return 0; +} + +static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) +{ + int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; + int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; + + return clk_mux_set_parent(priv, mux, sel); +} + +static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + uint32_t i; + + for (i = 0; i < pdata->nclkdiv; i++) { + int div_id, div_n; + int val; + int ret; + + val = pdata->clkdiv[i] & CMD_DATA_MASK; + div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; + div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; + + ret = clk_stm32_set_div(priv, div_id, div_n); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +static int stm32_clk_source_configure(struct stm32_clk_priv *priv) +{ + struct stm32_clk_platdata *pdata = priv->pdata; + bool ckper_disabled = false; + int clk_id; + int ret; + uint32_t i; + + for (i = 0; i < pdata->nclksrc; i++) { + uint32_t val = pdata->clksrc[i]; + uint32_t cmd, cmd_data; + + if (val == (uint32_t)CLK_CKPER_DISABLED) { + ckper_disabled = true; + continue; + } + + if (val == (uint32_t)CLK_RTC_DISABLED) { + continue; + } + + cmd = (val & CMD_MASK) >> CMD_SHIFT; + cmd_data = val & ~CMD_MASK; + + switch (cmd) { + case CMD_MUX: + ret = stm32_clk_configure_mux(priv, cmd_data); + break; + + case CMD_CLK: + clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); + + if (clk_id == _RTCCK) { + if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) { + continue; + } + } + + ret = stm32_clk_configure_clk(priv, cmd_data); + break; + default: + ret = -EINVAL; + break; + } + + if (ret != 0) { + return ret; + } + } + + /* + * CKPER is source for some peripheral clocks + * (FMC-NAND / QPSI-NOR) and switching source is allowed + * only if previous clock is still ON + * => deactivate CKPER only after switching clock + */ + if (ckper_disabled) { + ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id) +{ + unsigned long stgen_freq; + + stgen_freq = _clk_stm32_get_rate(priv, id); + + stm32mp_stgen_config(stgen_freq); + + return 0; +} + +#define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ + [(_idx)] = {\ + .clk_id = (_clk_id),\ + .plltype = (_type),\ + .reg_pllxcr = (_reg),\ + } + +static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco, + uint32_t *value) +{ + uint32_t divm = vco->div_mn[PLL_CFG_M]; + uint32_t divn = vco->div_mn[PLL_CFG_N]; + unsigned long prate = 0UL; + unsigned long refclk = 0UL; + + prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); + refclk = prate / (divm + 1U); + + if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || + (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) { + return -EINVAL; + } + + *value = 0; + + if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) { + *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT; + } + + *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; + *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; + + return 0; +} + +static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out) +{ + uint32_t value = 0; + + value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & RCC_PLLNCFGR2_DIVP_MASK; + value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & RCC_PLLNCFGR2_DIVQ_MASK; + value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & RCC_PLLNCFGR2_DIVR_MASK; + + return value; +} + +static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t value = 0; + + if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) { + ERROR("Invalid Vref clock !\n"); + panic(); + } + + /* Write N / M / IFREGE fields */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value); + + /* Fractional configuration */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0); + + /* Frac must be enabled only once its configuration is loaded */ + mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT); + mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE); +} + +static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll, + struct stm32_pll_vco *vco) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t mod_per = 0; + uint32_t inc_step = 0; + uint32_t sscg_mode = 0; + uint32_t value = 0; + + if (!vco->csg_enabled) { + return; + } + + mod_per = vco->csg[PLL_CSG_MOD_PER]; + inc_step = vco->csg[PLL_CSG_INC_STEP]; + sscg_mode = vco->csg[PLL_CSG_SSCG_MODE]; + + value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & RCC_PLLNCSGR_MOD_PER_MASK; + value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & RCC_PLLNCSGR_INC_STEP_MASK; + value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & RCC_PLLNCSGR_SSCG_MODE_MASK; + + mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value); + mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL); +} + +static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll, + struct stm32_pll_output *out) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t value = 0; + + value = clk_stm32_pll_compute_cfgr2(out); + + mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value); +} + +static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + struct stm32_clk_platdata *pdata = priv->pdata; + + return &pdata->pll[pll_idx]; +} + +static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U); +} + +static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + /* Preserve RCC_PLLNCR_SSCG_CTRL value */ + mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); +} + +static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + + /* Stop all output */ + mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + /* Stop PLL */ + mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON); +} + +static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); + + /* Wait PLL lock */ + while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%d clock start failed @ 0x%x: 0x%x\n", + pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base)); + return -EINVAL; + } + } + + return 0; +} + +static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, + const struct stm32_clk_pll *pll) +{ + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); + + /* Wait PLL lock */ + while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) { + if (timeout_elapsed(timeout)) { + ERROR("%d clock stop failed @ 0x%x: 0x%x\n", + pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base)); + return -EINVAL; + } + } + + return 0; +} + +static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + if (_clk_stm32_pll_is_enabled(priv, pll)) { + return 0; + } + + /* Preserve RCC_PLLNCR_SSCG_CTRL value */ + _clk_stm32_pll_set_on(priv, pll); + + /* Wait PLL lock */ + return _clk_stm32_pll_wait_ready_on(priv, pll); +} + +static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) +{ + if (!_clk_stm32_pll_is_enabled(priv, pll)) { + return; + } + + /* Stop all outputs and the PLL */ + _clk_stm32_pll_set_off(priv, pll); + + /* Wait PLL stopped */ + _clk_stm32_pll_wait_ready_off(priv, pll); +} + +static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, + struct stm32_pll_dt_cfg *pll_conf) +{ + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx); + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + int ret = 0; + + /* Configure PLLs source */ + ret = stm32_clk_configure_mux(priv, pll_conf->vco.src); + if (ret) { + return ret; + } + +#if STM32MP_USB_PROGRAMMER + if ((pll_idx == _PLL4) && pll4_bootrom) { + clk_stm32_pll_config_out(priv, pll, &pll_conf->output); + + mmio_setbits_32(pll_base, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + return 0; + } +#endif + /* Stop the PLL before */ + _clk_stm32_pll_disable(priv, pll); + + clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); + clk_stm32_pll_config_out(priv, pll, &pll_conf->output); + clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco); + + ret = _clk_stm32_pll_enable(priv, pll); + if (ret != 0) { + return ret; + } + + mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + return 0; +} + +static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) +{ + struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); + + if (pll_conf->vco.status) { + return _clk_stm32_pll_init(priv, pll_idx, pll_conf); + } + + return 0; +} + +static int stm32_clk_pll_configure(struct stm32_clk_priv *priv) +{ + int err = 0; + + err = clk_stm32_pll_init(priv, _PLL1); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL2); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL3); + if (err) { + return err; + } + + err = clk_stm32_pll_init(priv, _PLL4); + if (err) { + return err; + } + + return 0; +} + +static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) +{ + int ret = 0; + + if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { + ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); + } + + return ret; +} + +static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) +{ + stm32_enable_oscillator_hse(priv); + stm32_enable_oscillator_lse(priv); + _clk_stm32_enable(priv, _CK_LSI); + _clk_stm32_enable(priv, _CK_CSI); +} + +static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv) +{ + return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI)); +} + +#if STM32MP_USB_PROGRAMMER +static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p) +{ + /* Don't initialize PLL4, when used by BOOTROM */ + if ((stm32mp_get_boot_itf_selected() == + BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && + (usbphy_p == _PLL4R)) { + return true; + } + + return false; +} + +static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p) +{ + int _usbo_p; + int _usbphy_p; + + if (!pll4_bootrom) { + return 0; + } + + _usbo_p = _clk_stm32_get_parent(priv, _USBO_K); + _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); + + if ((_usbo_p != usbo_p) || (_usbphy_p != usbphy_p)) { + return -FDT_ERR_BADVALUE; + } + + return 0; +} +#endif + +static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = { + OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_CSI, _CK_CSI, "clk-csi", GATE_CSI, GATE_CSI_RDY, + NULL, NULL, NULL), + + OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, + BYPASS(RCC_BDCR, 1, 3), + CSS(RCC_BDCR, 8), + DRIVE(RCC_BDCR, 4, 2, 2)), + + OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, + BYPASS(RCC_OCENSETR, 10, 7), + CSS(RCC_OCENSETR, 11), + NULL), + + OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, + NULL, NULL, NULL), +}; + +static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) +{ + if (id < NB_OSCILLATOR) { + return stm32mp13_osc_data[id].name; + } + + return NULL; +} + +#define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ + [(_idx)] = {\ + .clk_id = (_clk_id),\ + .plltype = (_type),\ + .reg_pllxcr = (_reg),\ + } + +static const struct stm32_clk_pll stm32_mp13_clk_pll[_PLL_NB] = { + CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR), + CLK_PLL_CFG(_PLL2, _CK_PLL2, PLL_1600, RCC_PLL2CR), + CLK_PLL_CFG(_PLL3, _CK_PLL3, PLL_800, RCC_PLL3CR), + CLK_PLL_CFG(_PLL4, _CK_PLL4, PLL_800, RCC_PLL4CR), +}; + +static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx) +{ + return &stm32_mp13_clk_pll[idx]; +} + +struct stm32_pll_cfg { + int pll_id; +}; + +static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, + unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + uintptr_t pll_base = priv->base + pll->reg_pllxcr; + uint32_t cfgr1, fracr, divm, divn; + unsigned long fvco; + + cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1); + fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR); + + divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; + divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; + + /* + * With FRACV : + * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) + * Without FRACV + * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) + */ + if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { + uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> + RCC_PLLNFRACR_FRACV_SHIFT; + unsigned long long numerator, denominator; + + numerator = (((unsigned long long)divn + 1U) << 13) + fracv; + numerator = prate * numerator; + denominator = ((unsigned long long)divm + 1U) << 13; + fvco = (unsigned long)(numerator / denominator); + } else { + fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U)); + } + + return fvco; +}; + +static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + return _clk_stm32_pll_is_enabled(priv, pll); +} + +static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + return _clk_stm32_pll_enable(priv, pll); +} + +static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) +{ + const struct clk_stm32 *clk = _clk_get(priv, id); + struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; + const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); + + _clk_stm32_pll_disable(priv, pll); +} + +static const struct stm32_clk_ops clk_stm32_pll_ops = { + .recalc_rate = clk_stm32_pll_recalc_rate, + .enable = clk_stm32_pll_enable, + .disable = clk_stm32_pll_disable, + .is_enabled = clk_stm32_pll_is_enabled, +}; + +#define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ + .name = #idx,\ + .binding = _idx,\ + .parent = _parent,\ + .flags = (_flags),\ + .clock_cfg = &(struct stm32_pll_cfg) {\ + .pll_id = _pll_id,\ + },\ + .ops = &clk_stm32_pll_ops,\ +} + +struct clk_stm32_composite_cfg { + int gate_id; + int div_id; +}; + +static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv, + int idx, unsigned long prate) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate); +}; + +static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id); +} + +static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + return _clk_stm32_gate_enable(priv, composite_cfg->gate_id); +} + +static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx) +{ + const struct clk_stm32 *clk = _clk_get(priv, idx); + struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; + + _clk_stm32_gate_disable(priv, composite_cfg->gate_id); +} + +static const struct stm32_clk_ops clk_stm32_composite_ops = { + .recalc_rate = clk_stm32_composite_recalc_rate, + .is_enabled = clk_stm32_composite_gate_is_enabled, + .enable = clk_stm32_composite_gate_enable, + .disable = clk_stm32_composite_gate_disable, +}; + +#define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ + _div_id)[idx] = {\ + .name = #idx,\ + .binding = (_binding),\ + .parent = (_parent),\ + .flags = (_flags),\ + .clock_cfg = &(struct clk_stm32_composite_cfg) {\ + .gate_id = (_gate_id),\ + .div_id = (_div_id),\ + },\ + .ops = &clk_stm32_composite_ops,\ +} + +static const struct clk_stm32 stm32mp13_clk[CK_LAST] = { + /* ROOT CLOCKS */ + CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0), + CLK_OSC(_CK_HSE, CK_HSE, CLK_IS_ROOT, OSC_HSE), + CLK_OSC(_CK_HSI, CK_HSI, CLK_IS_ROOT, OSC_HSI), + CLK_OSC(_CK_CSI, CK_CSI, CLK_IS_ROOT, OSC_CSI), + CLK_OSC(_CK_LSI, CK_LSI, CLK_IS_ROOT, OSC_LSI), + CLK_OSC(_CK_LSE, CK_LSE, CLK_IS_ROOT, OSC_LSE), + + CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), + + CLK_FIXED_RATE(_USB_PHY_48, _NO_ID, USB_PHY_48_MHZ), + + STM32_DIV(_HSE_DIV, _NO_ID, _CK_HSE, 0, DIV_RTC), + + FIXED_FACTOR(_HSE_DIV2, CK_HSE_DIV2, _CK_HSE, 1, 2), + FIXED_FACTOR(_CSI_DIV122, _NO_ID, _CK_CSI, 1, 122), + + CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0), + CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0), + CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0), + CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0), + + STM32_COMPOSITE(_PLL1P, PLL1_P, _CK_PLL1, CLK_IS_CRITICAL, GATE_PLL1_DIVP, DIV_PLL1DIVP), + STM32_DIV(_PLL1P_DIV, _NO_ID, _CK_PLL1, 0, DIV_MPU), + + STM32_COMPOSITE(_PLL2P, PLL2_P, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVP, DIV_PLL2DIVP), + STM32_COMPOSITE(_PLL2Q, PLL2_Q, _CK_PLL2, 0, GATE_PLL2_DIVQ, DIV_PLL2DIVQ), + STM32_COMPOSITE(_PLL2R, PLL2_R, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVR, DIV_PLL2DIVR), + + STM32_COMPOSITE(_PLL3P, PLL3_P, _CK_PLL3, 0, GATE_PLL3_DIVP, DIV_PLL3DIVP), + STM32_COMPOSITE(_PLL3Q, PLL3_Q, _CK_PLL3, 0, GATE_PLL3_DIVQ, DIV_PLL3DIVQ), + STM32_COMPOSITE(_PLL3R, PLL3_R, _CK_PLL3, 0, GATE_PLL3_DIVR, DIV_PLL3DIVR), + + STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP), + STM32_COMPOSITE(_PLL4Q, PLL4_Q, _CK_PLL4, 0, GATE_PLL4_DIVQ, DIV_PLL4DIVQ), + STM32_COMPOSITE(_PLL4R, PLL4_R, _CK_PLL4, 0, GATE_PLL4_DIVR, DIV_PLL4DIVR), + + STM32_MUX(_CKMPU, CK_MPU, MUX_MPU, 0), + STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI), + STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB), + STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0), + + STM32_DIV(_PCLK1, PCLK1, _CKMLAHB, 0, DIV_APB1), + STM32_DIV(_PCLK2, PCLK2, _CKMLAHB, 0, DIV_APB2), + STM32_DIV(_PCLK3, PCLK3, _CKMLAHB, 0, DIV_APB3), + STM32_DIV(_PCLK4, PCLK4, _CKAXI, 0, DIV_APB4), + STM32_DIV(_PCLK5, PCLK5, _CKAXI, 0, DIV_APB5), + STM32_DIV(_PCLK6, PCLK6, _CKMLAHB, 0, DIV_APB6), + + CK_TIMER(_CKTIMG1, CK_TIMG1, _PCLK1, 0, RCC_APB1DIVR, RCC_TIMG1PRER), + CK_TIMER(_CKTIMG2, CK_TIMG2, _PCLK2, 0, RCC_APB2DIVR, RCC_TIMG2PRER), + CK_TIMER(_CKTIMG3, CK_TIMG3, _PCLK6, 0, RCC_APB6DIVR, RCC_TIMG3PRER), + + /* END ROOT CLOCKS */ + + STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1), + STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP), + STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC), + STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP), + STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB), + STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP), + STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG), + STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB), + STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP), + + STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG), + STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM), + STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB), + STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY), + STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO), + + STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB), + STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC), + STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC), + STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB), + STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC), + STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC), + + STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1), + STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2), + STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3), + STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4), + STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5), + STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12), + STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15), + + STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK), + + STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA), + STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB), + STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC), + STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD), + STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE), + STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF), + STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG), + STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH), + STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI), + + STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA), + STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES), + STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1), + STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1), + + STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1), + STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM), + + STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1), + STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2), + STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK), + +/* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */ + STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3), + STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4), + STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5), + STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7), + STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8), + STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6), + STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE), + STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC), + STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI), + + STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1), + STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2), + STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE), + +#if defined(IMAGE_BL32) + STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2), + STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3), + STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4), + STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5), + STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6), + STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7), + STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13), + STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14), + STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1), + STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2), + STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3), + STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF), + STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1), + STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8), + STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16), + STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17), + STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1), + STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4), + STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5), + STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1), + STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2), + STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM), + STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN), + STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH), + STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1), + STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2), + STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM), + STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2), + STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3), + STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4), + STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5), + STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF), + STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS), + STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP), + STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL), + STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP), + STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP), + STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1), + STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2), + STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2), + STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1), + STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2), + STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC), + STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC), + STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX), + STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK), + STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX), + STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX), + STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK), + STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX), + STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX), + STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC), +#endif +}; + +static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB]; + +static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR]; + +static uint32_t mp13_clksrc[MUX_MAX]; + +static uint32_t mp13_clkdiv[DIV_MAX]; + +static struct stm32_clk_platdata stm32mp13_clock_pdata = { + .osci = mp13_osci, + .nosci = NB_OSCILLATOR, + .pll = mp13_pll, + .npll = _PLL_NB, + .clksrc = mp13_clksrc, + .nclksrc = MUX_MAX, + .clkdiv = mp13_clkdiv, + .nclkdiv = DIV_MAX, +}; + +static struct stm32_clk_priv stm32mp13_clock_data = { + .base = RCC_BASE, + .num = ARRAY_SIZE(stm32mp13_clk), + .clks = stm32mp13_clk, + .parents = parent_mp13, + .nb_parents = ARRAY_SIZE(parent_mp13), + .gates = gates_mp13, + .nb_gates = ARRAY_SIZE(gates_mp13), + .div = dividers_mp13, + .nb_div = ARRAY_SIZE(dividers_mp13), + .osci_data = stm32mp13_osc_data, + .nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data), + .gate_refcounts = refcounts_mp13, + .pdata = &stm32mp13_clock_pdata, +}; + +static int stm32mp1_init_clock_tree(void) +{ + struct stm32_clk_priv *priv = clk_stm32_get_priv(); + int ret; + +#if STM32MP_USB_PROGRAMMER + int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); + int usbo_p = _clk_stm32_get_parent(priv, _USBO_K); + + /* Don't initialize PLL4, when used by BOOTROM */ + pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p); +#endif + + /* + * Switch ON oscillators found in device-tree. + * Note: HSI already ON after BootROM stage. + */ + stm32_clk_oscillators_enable(priv); + + /* Come back to HSI */ + ret = stm32mp1_come_back_to_hsi(); + if (ret != 0) { + return ret; + } + + ret = stm32_clk_hsidiv_configure(priv); + if (ret != 0) { + return ret; + } + + ret = stm32_clk_stgen_configure(priv, _STGENC); + if (ret != 0) { + panic(); + } + + ret = stm32_clk_dividers_configure(priv); + if (ret != 0) { + panic(); + } + + ret = stm32_clk_pll_configure(priv); + if (ret != 0) { + panic(); + } + + /* Wait LSE ready before to use it */ + ret = stm32_clk_oscillators_wait_lse_ready(priv); + if (ret != 0) { + panic(); + } + + /* Configure with expected clock source */ + ret = stm32_clk_source_configure(priv); + if (ret != 0) { + panic(); + } + + /* Configure LSE css after RTC source configuration */ + ret = stm32_clk_oscillators_lse_set_css(priv); + if (ret != 0) { + panic(); + } + +#if STM32MP_USB_PROGRAMMER + ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p); + if (ret != 0) { + return ret; + } +#endif + /* reconfigure STGEN with DT config */ + ret = stm32_clk_stgen_configure(priv, _STGENC); + if (ret != 0) { + panic(); + } + + /* Software Self-Refresh mode (SSR) during DDR initilialization */ + mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, + RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_SSR << + RCC_DDRITFCR_DDRCKMOD_SHIFT); + + return 0; +} + +#define LSEDRV_MEDIUM_HIGH 2 + +static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, + struct stm32_osci_dt_cfg *osci) +{ + int subnode = 0; + + /* default value oscillator not found, freq=0 */ + osci->freq = 0; + + fdt_for_each_subnode(subnode, fdt, node) { + const char *cchar = NULL; + const fdt32_t *cuint = NULL; + int ret = 0; + + cchar = fdt_get_name(fdt, subnode, &ret); + if (cchar == NULL) { + return ret; + } + + if (strncmp(cchar, name, (size_t)ret) || + fdt_get_status(subnode) == DT_DISABLED) { + continue; + } + + cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); + if (cuint == NULL) { + return ret; + } + + osci->freq = fdt32_to_cpu(*cuint); + + if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { + osci->bypass = true; + } + + if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { + osci->digbyp = true; + } + + if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { + osci->css = true; + } + + osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); + + return 0; + } + + return 0; +} + +static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) +{ + int fdt_err = 0; + uint32_t i = 0; + int node = 0; + + node = fdt_path_offset(fdt, "/clocks"); + if (node < 0) { + return -FDT_ERR_NOTFOUND; + } + + for (i = 0; i < pdata->nosci; i++) { + const char *name = NULL; + + name = clk_stm32_get_oscillator_name((enum stm32_osc)i); + if (name == NULL) { + continue; + } + + fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); + if (fdt_err < 0) { + panic(); + } + } + + return 0; +} + +#define RCC_PLL_NAME_SIZE 12 + +static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco) +{ + int err = 0; + + err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn); + if (err != 0) { + return err; + } + + err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg); + + vco->csg_enabled = (err == 0); + + if (err == -FDT_ERR_NOTFOUND) { + err = 0; + } + + if (err != 0) { + return err; + } + + vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON; + + vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); + + vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); + + return 0; +} + +static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output) +{ + int err = 0; + + err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB, + output->output); + if (err != 0) { + return err; + } + + return 0; +} + +static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) +{ + const fdt32_t *cuint = NULL; + int subnode_pll = 0; + int subnode_vco = 0; + int err = 0; + + cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); + if (!cuint) { + return -FDT_ERR_NOTFOUND; + } + + subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); + if (subnode_pll < 0) { + return -FDT_ERR_NOTFOUND; + } + + cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); + if (!cuint) { + return -FDT_ERR_NOTFOUND; + } + + subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); + if (subnode_vco < 0) { + return -FDT_ERR_NOTFOUND; + } + + err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco); + if (err != 0) { + return err; + } + + err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output); + if (err != 0) { + return err; + } + + return 0; +} + +static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) +{ + size_t i = 0U; + + for (i = _PLL1; i < pdata->npll; i++) { + struct stm32_pll_dt_cfg *pll = pdata->pll + i; + char name[RCC_PLL_NAME_SIZE]; + int subnode = 0; + int err = 0; + + snprintf(name, sizeof(name), "st,pll@%u", i); + + subnode = fdt_subnode_offset(fdt, node, name); + if (!fdt_check_node(subnode)) { + continue; + } + + err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); + if (err != 0) { + panic(); + } + } + + return 0; +} + +static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) +{ + void *fdt = NULL; + int node; + uint32_t err; + + if (fdt_get_address(&fdt) == 0) { + return -ENOENT; + } + + node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); + if (node < 0) { + panic(); + } + + err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv); + if (err != 0) { + return err; + } + + err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc); + if (err != 0) { + return err; + } + + return 0; +} + +int stm32mp1_clk_init(void) +{ + return 0; +} + +int stm32mp1_clk_probe(void) +{ + uintptr_t base = RCC_BASE; + int ret; + + ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata); + if (ret != 0) { + return ret; + } + + ret = clk_stm32_init(&stm32mp13_clock_data, base); + if (ret != 0) { + return ret; + } + + ret = stm32mp1_init_clock_tree(); + if (ret != 0) { + return ret; + } + + clk_stm32_enable_critical_clocks(); + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/st/clk/stm32mp1_clk.c 2.7.0+dfsg-2/drivers/st/clk/stm32mp1_clk.c --- 2.6+dfsg-1/drivers/st/clk/stm32mp1_clk.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/clk/stm32mp1_clk.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -9,16 +9,12 @@ #include #include -#include - -#include - #include #include #include #include +#include #include -#include #include #include #include @@ -26,8 +22,11 @@ #include #include #include +#include #include +#include + #define MAX_HSI_HZ 64000000 #define USB_PHY_48_MHZ 48000000 @@ -241,6 +240,7 @@ struct stm32mp1_clk_gate { uint8_t bit; uint8_t index; uint8_t set_clr; + uint8_t secure; uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ }; @@ -266,45 +266,49 @@ struct stm32mp1_clk_pll { }; /* Clocks with selectable source and non set/clr register access */ -#define _CLK_SELEC(off, b, idx, s) \ +#define _CLK_SELEC(sec, off, b, idx, s) \ { \ .offset = (off), \ .bit = (b), \ .index = (idx), \ .set_clr = 0, \ + .secure = (sec), \ .sel = (s), \ .fixed = _UNKNOWN_ID, \ } /* Clocks with fixed source and non set/clr register access */ -#define _CLK_FIXED(off, b, idx, f) \ +#define _CLK_FIXED(sec, off, b, idx, f) \ { \ .offset = (off), \ .bit = (b), \ .index = (idx), \ .set_clr = 0, \ + .secure = (sec), \ .sel = _UNKNOWN_SEL, \ .fixed = (f), \ } /* Clocks with selectable source and set/clr register access */ -#define _CLK_SC_SELEC(off, b, idx, s) \ +#define _CLK_SC_SELEC(sec, off, b, idx, s) \ { \ .offset = (off), \ .bit = (b), \ .index = (idx), \ .set_clr = 1, \ + .secure = (sec), \ .sel = (s), \ .fixed = _UNKNOWN_ID, \ } /* Clocks with fixed source and set/clr register access */ -#define _CLK_SC_FIXED(off, b, idx, f) \ +#define _CLK_SC_FIXED(sec, off, b, idx, f) \ { \ .offset = (off), \ .bit = (b), \ .index = (idx), \ .set_clr = 1, \ + .secure = (sec), \ .sel = _UNKNOWN_SEL, \ .fixed = (f), \ } @@ -338,81 +342,94 @@ struct stm32mp1_clk_pll { #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) +#define SEC 1 +#define N_S 0 + static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { - _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), - _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), - _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), - _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), - _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), - _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), - _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), - _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), - _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), - _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), - _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), - - _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), - _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), - - _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), - _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), - - _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), - - _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), - - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), - _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), - - _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), - _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), - - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), - _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), - - _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), - _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), - _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), - _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), - _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), - - _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), - _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), - _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), - _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), - _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), + _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), + _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), + _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), + _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), + _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), + _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), + _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), + _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), + _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), + _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), + _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), + +#if defined(IMAGE_BL32) + _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), +#endif + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), + +#if defined(IMAGE_BL32) + _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), +#endif + _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), + + _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), + + _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), + + _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), + _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), + _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), + _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), + _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), + +#if defined(IMAGE_BL32) + _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), +#endif + + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), + + _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), + _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), + _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), + _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), + +#if defined(IMAGE_BL2) + _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), +#endif + _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), + _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), +#if defined(IMAGE_BL32) + _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), +#endif - _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), - _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), + _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), + _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), }; static const uint8_t i2c12_parents[] = { @@ -628,6 +645,13 @@ static const struct stm32mp1_clk_gate *g return &stm32mp1_clk_gate[idx]; } +#if defined(IMAGE_BL32) +static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) +{ + return gate->secure == N_S; +} +#endif + static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) { return &stm32mp1_clk_sel[idx]; @@ -698,7 +722,7 @@ static int stm32mp1_clk_get_gated_id(uns } } - ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); + ERROR("%s: clk id %lu not found\n", __func__, id); return -EINVAL; } @@ -1062,17 +1086,6 @@ static bool __clk_is_enabled(struct stm3 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); } -unsigned int stm32mp1_clk_get_refcount(unsigned long id) -{ - int i = stm32mp1_clk_get_gated_id(id); - - if (i < 0) { - panic(); - } - - return gate_refcounts[i]; -} - /* Oscillators and PLLs are not gated at runtime */ static bool clock_is_always_on(unsigned long id) { @@ -1101,11 +1114,10 @@ static bool clock_is_always_on(unsigned } } -void __stm32mp1_clk_enable(unsigned long id, bool secure) +static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) { const struct stm32mp1_clk_gate *gate; int i; - unsigned int *refcnt; if (clock_is_always_on(id)) { return; @@ -1113,27 +1125,44 @@ void __stm32mp1_clk_enable(unsigned long i = stm32mp1_clk_get_gated_id(id); if (i < 0) { - ERROR("Clock %d can't be enabled\n", (uint32_t)id); + ERROR("Clock %lu can't be enabled\n", id); panic(); } gate = gate_ref(i); - refcnt = &gate_refcounts[i]; + + if (!with_refcnt) { + __clk_enable(gate); + return; + } + +#if defined(IMAGE_BL32) + if (gate_is_non_secure(gate)) { + /* Enable non-secure clock w/o any refcounting */ + __clk_enable(gate); + return; + } +#endif stm32mp1_clk_lock(&refcount_lock); - if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { + if (gate_refcounts[i] == 0U) { __clk_enable(gate); } + gate_refcounts[i]++; + if (gate_refcounts[i] == UINT_MAX) { + ERROR("Clock %lu refcount reached max value\n", id); + panic(); + } + stm32mp1_clk_unlock(&refcount_lock); } -void __stm32mp1_clk_disable(unsigned long id, bool secure) +static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) { const struct stm32mp1_clk_gate *gate; int i; - unsigned int *refcnt; if (clock_is_always_on(id)) { return; @@ -1141,33 +1170,52 @@ void __stm32mp1_clk_disable(unsigned lon i = stm32mp1_clk_get_gated_id(id); if (i < 0) { - ERROR("Clock %d can't be disabled\n", (uint32_t)id); + ERROR("Clock %lu can't be disabled\n", id); panic(); } gate = gate_ref(i); - refcnt = &gate_refcounts[i]; + + if (!with_refcnt) { + __clk_disable(gate); + return; + } + +#if defined(IMAGE_BL32) + if (gate_is_non_secure(gate)) { + /* Don't disable non-secure clocks */ + return; + } +#endif stm32mp1_clk_lock(&refcount_lock); - if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { + if (gate_refcounts[i] == 0U) { + ERROR("Clock %lu refcount reached 0\n", id); + panic(); + } + gate_refcounts[i]--; + + if (gate_refcounts[i] == 0U) { __clk_disable(gate); } stm32mp1_clk_unlock(&refcount_lock); } -void stm32mp_clk_enable(unsigned long id) +static int stm32mp_clk_enable(unsigned long id) { __stm32mp1_clk_enable(id, true); + + return 0; } -void stm32mp_clk_disable(unsigned long id) +static void stm32mp_clk_disable(unsigned long id) { __stm32mp1_clk_disable(id, true); } -bool stm32mp_clk_is_enabled(unsigned long id) +static bool stm32mp_clk_is_enabled(unsigned long id) { int i; @@ -1183,15 +1231,55 @@ bool stm32mp_clk_is_enabled(unsigned lon return __clk_is_enabled(gate_ref(i)); } -unsigned long stm32mp_clk_get_rate(unsigned long id) +static unsigned long stm32mp_clk_get_rate(unsigned long id) { + uintptr_t rcc_base = stm32mp_rcc_base(); int p = stm32mp1_clk_get_parent(id); + uint32_t prescaler, timpre; + unsigned long parent_rate; if (p < 0) { return 0; } - return get_clock_rate(p); + parent_rate = get_clock_rate(p); + + switch (id) { + case TIM2_K: + case TIM3_K: + case TIM4_K: + case TIM5_K: + case TIM6_K: + case TIM7_K: + case TIM12_K: + case TIM13_K: + case TIM14_K: + prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & + RCC_APBXDIV_MASK; + timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & + RCC_TIMGXPRER_TIMGXPRE; + break; + + case TIM1_K: + case TIM8_K: + case TIM15_K: + case TIM16_K: + case TIM17_K: + prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & + RCC_APBXDIV_MASK; + timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & + RCC_TIMGXPRER_TIMGXPRE; + break; + + default: + return parent_rate; + } + + if (prescaler == 0U) { + return parent_rate; + } + + return parent_rate * (timpre + 1U) * 2U; } static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) @@ -1308,6 +1396,13 @@ static void stm32mp1_hse_enable(bool byp if (css) { mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); } + +#if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER + if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && + (!(digbyp || bypass))) { + panic(); + } +#endif } static void stm32mp1_csi_set(bool enable) @@ -1469,7 +1564,7 @@ static int stm32mp1_pll_output(enum stm3 /* Wait PLL lock */ while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { if (timeout_elapsed(timeout)) { - ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", + ERROR("PLL%u start failed @ 0x%lx: 0x%x\n", pll_id, pllxcr, mmio_read_32(pllxcr)); return -ETIMEDOUT; } @@ -1498,7 +1593,7 @@ static int stm32mp1_pll_stop(enum stm32m /* Wait PLL stopped */ while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { if (timeout_elapsed(timeout)) { - ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", + ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n", pll_id, pllxcr, mmio_read_32(pllxcr)); return -ETIMEDOUT; } @@ -1671,89 +1766,77 @@ static void stm32mp1_set_rtcsrc(unsigned } } -static void stm32mp1_stgen_config(void) +static void stm32mp1_pkcs_config(uint32_t pkcs) { - uint32_t cntfid0; - unsigned long rate; - unsigned long long counter; - - cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); - rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); + uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); + uint32_t value = pkcs & 0xFU; + uint32_t mask = 0xFU; - if (cntfid0 == rate) { - return; + if ((pkcs & BIT(31)) != 0U) { + mask <<= 4; + value <<= 4; } - mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); - counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); - counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; - counter = (counter * rate / cntfid0); - - mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); - mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); - mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); - mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); - - write_cntfrq((u_register_t)rate); - - /* Need to update timer with new frequency */ - generic_delay_timer_init(); + mmio_clrsetbits_32(address, mask, value); } -void stm32mp1_stgen_increment(unsigned long long offset_in_ms) +static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, + uint32_t *fracv, uint32_t *csg, + bool *csg_set) { - unsigned long long cnt; + void *fdt; + int ret; - cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | - mmio_read_32(STGEN_BASE + CNTCVL_OFF); + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } - cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; + ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, + pllcfg); + if (ret < 0) { + return -FDT_ERR_NOTFOUND; + } - mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); - mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); - mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); - mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); -} + *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); -static void stm32mp1_pkcs_config(uint32_t pkcs) -{ - uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); - uint32_t value = pkcs & 0xFU; - uint32_t mask = 0xFU; + ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, + csg); - if ((pkcs & BIT(31)) != 0U) { - mask <<= 4; - value <<= 4; + *csg_set = (ret == 0); + + if (ret == -FDT_ERR_NOTFOUND) { + ret = 0; } - mmio_clrsetbits_32(address, mask, value); + return ret; } int stm32mp1_clk_init(void) { uintptr_t rcc_base = stm32mp_rcc_base(); + uint32_t pllfracv[_PLL_NB]; + uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; unsigned int clksrc[CLKSRC_NB]; unsigned int clkdiv[CLKDIV_NB]; unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; int plloff[_PLL_NB]; int ret, len; enum stm32mp1_pll_id i; + bool pllcsg_set[_PLL_NB]; + bool pllcfg_valid[_PLL_NB]; bool lse_css = false; bool pll3_preserve = false; bool pll4_preserve = false; bool pll4_bootrom = false; const fdt32_t *pkcs_cell; void *fdt; + int stgen_p = stm32mp1_clk_get_parent(STGEN_K); + int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); if (fdt_get_address(&fdt) == 0) { return -FDT_ERR_NOTFOUND; } - /* Check status field to disable security */ - if (!fdt_get_rcc_secure_status()) { - mmio_write_32(rcc_base + RCC_TZCR, 0); - } - ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, clksrc); if (ret < 0) { @@ -1769,17 +1852,19 @@ int stm32mp1_clk_init(void) for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { char name[12]; - snprintf(name, sizeof(name), "st,pll@%d", i); + snprintf(name, sizeof(name), "st,pll@%u", i); plloff[i] = fdt_rcc_subnode_offset(name); - if (!fdt_check_node(plloff[i])) { + pllcfg_valid[i] = fdt_check_node(plloff[i]); + if (!pllcfg_valid[i]) { continue; } - ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", - (int)PLLCFG_NB, pllcfg[i]); - if (ret < 0) { - return -FDT_ERR_NOTFOUND; + ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], + &pllfracv[i], pllcsg[i], + &pllcsg_set[i]); + if (ret != 0) { + return ret; } } @@ -1794,22 +1879,24 @@ int stm32mp1_clk_init(void) stm32mp1_lsi_set(true); } if (stm32mp1_osc[_LSE] != 0U) { + const char *name = stm32mp_osc_node_label[_LSE]; bool bypass, digbyp; uint32_t lsedrv; - bypass = fdt_osc_read_bool(_LSE, "st,bypass"); - digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); - lse_css = fdt_osc_read_bool(_LSE, "st,css"); - lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", + bypass = fdt_clk_read_bool(name, "st,bypass"); + digbyp = fdt_clk_read_bool(name, "st,digbypass"); + lse_css = fdt_clk_read_bool(name, "st,css"); + lsedrv = fdt_clk_read_uint32_default(name, "st,drive", LSEDRV_MEDIUM_HIGH); stm32mp1_lse_enable(bypass, digbyp, lsedrv); } if (stm32mp1_osc[_HSE] != 0U) { + const char *name = stm32mp_osc_node_label[_HSE]; bool bypass, digbyp, css; - bypass = fdt_osc_read_bool(_HSE, "st,bypass"); - digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); - css = fdt_osc_read_bool(_HSE, "st,css"); + bypass = fdt_clk_read_bool(name, "st,bypass"); + digbyp = fdt_clk_read_bool(name, "st,digbypass"); + css = fdt_clk_read_bool(name, "st,css"); stm32mp1_hse_enable(bypass, digbyp, css); } /* @@ -1834,14 +1921,28 @@ int stm32mp1_clk_init(void) if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { - pll3_preserve = stm32mp1_check_pll_conf(_PLL3, + if (pllcfg_valid[_PLL3]) { + pll3_preserve = + stm32mp1_check_pll_conf(_PLL3, clksrc[CLKSRC_PLL3], pllcfg[_PLL3], plloff[_PLL3]); - pll4_preserve = stm32mp1_check_pll_conf(_PLL4, + } + + if (pllcfg_valid[_PLL4]) { + pll4_preserve = + stm32mp1_check_pll_conf(_PLL4, clksrc[CLKSRC_PLL4], pllcfg[_PLL4], plloff[_PLL4]); + } + } + /* Don't initialize PLL4, when used by BOOTROM */ + if ((stm32mp_get_boot_itf_selected() == + BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && + ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { + pll4_bootrom = true; + pll4_preserve = true; } for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { @@ -1862,7 +1963,8 @@ int stm32mp1_clk_init(void) if (ret != 0) { return ret; } - stm32mp1_stgen_config(); + + stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); } /* Select DIV */ @@ -1924,15 +2026,12 @@ int stm32mp1_clk_init(void) /* Configure and start PLLs */ for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { - uint32_t fracv; - uint32_t csg[PLLCSG_NB]; - if (((i == _PLL3) && pll3_preserve) || ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { continue; } - if (!fdt_check_node(plloff[i])) { + if (!pllcfg_valid[i]) { continue; } @@ -1942,25 +2041,20 @@ int stm32mp1_clk_init(void) continue; } - fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); - - ret = stm32mp1_pll_config(i, pllcfg[i], fracv); + ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); if (ret != 0) { return ret; } - ret = fdt_read_uint32_array(fdt, plloff[i], "csg", - (uint32_t)PLLCSG_NB, csg); - if (ret == 0) { - stm32mp1_pll_csg(i, csg); - } else if (ret != -FDT_ERR_NOTFOUND) { - return ret; + + if (pllcsg_set[i]) { + stm32mp1_pll_csg(i, pllcsg[i]); } stm32mp1_pll_start(i); } /* Wait and start PLLs ouptut when ready */ for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { - if (!fdt_check_node(plloff[i])) { + if (!pllcfg_valid[i]) { continue; } @@ -1994,6 +2088,11 @@ int stm32mp1_clk_init(void) if (pkcs_cell != NULL) { bool ckper_disabled = false; uint32_t j; + uint32_t usbreg_bootrom = 0U; + + if (pll4_bootrom) { + usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); + } for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); @@ -2014,13 +2113,33 @@ int stm32mp1_clk_init(void) if (ckper_disabled) { stm32mp1_pkcs_config(CLK_CKPER_DISABLED); } + + if (pll4_bootrom) { + uint32_t usbreg_value, usbreg_mask; + const struct stm32mp1_clk_sel *sel; + + sel = clk_sel_ref(_USBPHY_SEL); + usbreg_mask = (uint32_t)sel->msk << sel->src; + sel = clk_sel_ref(_USBO_SEL); + usbreg_mask |= (uint32_t)sel->msk << sel->src; + + usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & + usbreg_mask; + usbreg_bootrom &= usbreg_mask; + if (usbreg_bootrom != usbreg_value) { + VERBOSE("forbidden new USB clk path\n"); + VERBOSE("vs bootrom on USB boot\n"); + return -FDT_ERR_BADVALUE; + } + } } /* Switch OFF HSI if not found in device-tree */ if (stm32mp1_osc[_HSI] == 0U) { stm32mp1_hsi_set(false); } - stm32mp1_stgen_config(); + + stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); /* Software Self-Refresh mode (SSR) during DDR initilialization */ mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, @@ -2231,11 +2350,27 @@ static void sync_earlyboot_clocks_state( } } +static const struct clk_ops stm32mp_clk_ops = { + .enable = stm32mp_clk_enable, + .disable = stm32mp_clk_disable, + .is_enabled = stm32mp_clk_is_enabled, + .get_rate = stm32mp_clk_get_rate, + .get_parent = stm32mp1_clk_get_parent, +}; + int stm32mp1_clk_probe(void) { +#if defined(IMAGE_BL32) + if (!fdt_get_rcc_secure_state()) { + mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); + } +#endif + stm32mp1_osc_init(); sync_earlyboot_clocks_state(); + clk_register(&stm32mp_clk_ops); + return 0; } diff -pruN 2.6+dfsg-1/drivers/st/clk/stm32mp_clkfunc.c 2.7.0+dfsg-2/drivers/st/clk/stm32mp_clkfunc.c --- 2.6+dfsg-1/drivers/st/clk/stm32mp_clkfunc.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/clk/stm32mp_clkfunc.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,19 +1,23 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ #include -#include - -#include - +#include #include +#include +#include #include #include +#include +#include + +#include +#define DT_UART_COMPAT "st,stm32h7-uart" /* * Get the frequency of an oscillator from its name in device tree. * @param name: oscillator name @@ -43,7 +47,8 @@ int fdt_osc_read_freq(const char *name, return ret; } - if (strncmp(cchar, name, (size_t)ret) == 0) { + if ((strncmp(cchar, name, (size_t)ret) == 0) && + (fdt_get_status(subnode) != DT_DISABLED)) { const fdt32_t *cuint; cuint = fdt_getprop(fdt, subnode, "clock-frequency", @@ -65,11 +70,11 @@ int fdt_osc_read_freq(const char *name, /* * Check the presence of an oscillator property from its id. - * @param osc_id: oscillator ID + * @param node_label: clock node name * @param prop_name: property name * @return: true/false regarding search result. */ -bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name) +bool fdt_clk_read_bool(const char *node_label, const char *prop_name) { int node, subnode; void *fdt; @@ -78,10 +83,6 @@ bool fdt_osc_read_bool(enum stm32mp_osc_ return false; } - if (osc_id >= NB_OSC) { - return false; - } - node = fdt_path_offset(fdt, "/clocks"); if (node < 0) { return false; @@ -96,8 +97,7 @@ bool fdt_osc_read_bool(enum stm32mp_osc_ return false; } - if (strncmp(cchar, stm32mp_osc_node_label[osc_id], - (size_t)ret) != 0) { + if (strncmp(cchar, node_label, (size_t)ret) != 0) { continue; } @@ -110,13 +110,13 @@ bool fdt_osc_read_bool(enum stm32mp_osc_ } /* - * Get the value of a oscillator property from its ID. - * @param osc_id: oscillator ID + * Get the value of a oscillator property from its name. + * @param node_label: oscillator name * @param prop_name: property name * @param dflt_value: default value * @return oscillator value on success, default value if property not found. */ -uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, +uint32_t fdt_clk_read_uint32_default(const char *node_label, const char *prop_name, uint32_t dflt_value) { int node, subnode; @@ -126,10 +126,6 @@ uint32_t fdt_osc_read_uint32_default(enu return dflt_value; } - if (osc_id >= NB_OSC) { - return dflt_value; - } - node = fdt_path_offset(fdt, "/clocks"); if (node < 0) { return dflt_value; @@ -144,8 +140,7 @@ uint32_t fdt_osc_read_uint32_default(enu return dflt_value; } - if (strncmp(cchar, stm32mp_osc_node_label[osc_id], - (size_t)ret) != 0) { + if (strncmp(cchar, node_label, (size_t)ret) != 0) { continue; } @@ -255,24 +250,22 @@ const fdt32_t *fdt_rcc_read_prop(const c } /* - * Get the secure status for rcc node in device tree. - * @return: true if rcc is available from secure world, false if not. + * Get the secure state for rcc node in device tree. + * @return: true if rcc is configured for secure world access, false if not. */ -bool fdt_get_rcc_secure_status(void) +bool fdt_get_rcc_secure_state(void) { - int node; void *fdt; if (fdt_get_address(&fdt) == 0) { return false; } - node = fdt_get_rcc_node(fdt); - if (node < 0) { + if (fdt_node_offset_by_compatible(fdt, -1, DT_RCC_SEC_CLK_COMPAT) < 0) { return false; } - return !!(fdt_get_status(node) & DT_SECURE); + return true; } /* @@ -297,3 +290,89 @@ int fdt_get_clock_id(int node) cuint++; return (int)fdt32_to_cpu(*cuint); } + +/* + * Get the frequency of the specified UART instance. + * @param instance: UART interface registers base address. + * @return: clock frequency on success, 0 value on failure. + */ +unsigned long fdt_get_uart_clock_freq(uintptr_t instance) +{ + void *fdt; + int node; + int clk_id; + + if (fdt_get_address(&fdt) == 0) { + return 0UL; + } + + /* Check for UART nodes */ + node = dt_match_instance_by_compatible(DT_UART_COMPAT, instance); + if (node < 0) { + return 0UL; + } + + clk_id = fdt_get_clock_id(node); + if (clk_id < 0) { + return 0UL; + } + + return clk_get_rate((unsigned long)clk_id); +} + +/******************************************************************************* + * This function configures and restores the STGEN counter depending on the + * connected clock. + ******************************************************************************/ +void stm32mp_stgen_config(unsigned long rate) +{ + uint32_t cntfid0; + unsigned long long counter; + + cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); + + if (cntfid0 == rate) { + return; + } + + mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); + counter = stm32mp_stgen_get_counter() * rate / cntfid0; + + mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); + mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); + mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); + mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); + + write_cntfrq_el0(rate); + + /* Need to update timer with new frequency */ + generic_delay_timer_init(); +} + +/******************************************************************************* + * This function returns the STGEN counter value. + ******************************************************************************/ +unsigned long long stm32mp_stgen_get_counter(void) +{ + return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | + mmio_read_32(STGEN_BASE + CNTCVL_OFF)); +} + +/******************************************************************************* + * This function restores the STGEN counter value. + * It takes a first input value as a counter backup value to be restored and a + * offset in ms to be added. + ******************************************************************************/ +void stm32mp_stgen_restore_counter(unsigned long long value, + unsigned long long offset_in_ms) +{ + unsigned long long cnt; + + cnt = value + ((offset_in_ms * + mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U); + + mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); + mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); + mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); + mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); +} diff -pruN 2.6+dfsg-1/drivers/st/crypto/stm32_hash.c 2.7.0+dfsg-2/drivers/st/crypto/stm32_hash.c --- 2.6+dfsg-1/drivers/st/crypto/stm32_hash.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/crypto/stm32_hash.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -189,7 +190,7 @@ int stm32_hash_update(const uint8_t *buf return 0; } - stm32mp_clk_enable(stm32_hash.clock); + clk_enable(stm32_hash.clock); if (stm32_remain.length != 0U) { uint32_t copysize; @@ -231,7 +232,7 @@ int stm32_hash_update(const uint8_t *buf } exit: - stm32mp_clk_disable(stm32_hash.clock); + clk_disable(stm32_hash.clock); return ret; } @@ -240,12 +241,12 @@ int stm32_hash_final(uint8_t *digest) { int ret; - stm32mp_clk_enable(stm32_hash.clock); + clk_enable(stm32_hash.clock); if (stm32_remain.length != 0U) { ret = hash_write_data(stm32_remain.buffer); if (ret != 0) { - stm32mp_clk_disable(stm32_hash.clock); + clk_disable(stm32_hash.clock); return ret; } @@ -260,7 +261,7 @@ int stm32_hash_final(uint8_t *digest) ret = hash_get_digest(digest); - stm32mp_clk_disable(stm32_hash.clock); + clk_disable(stm32_hash.clock); return ret; } @@ -280,11 +281,11 @@ int stm32_hash_final_update(const uint8_ void stm32_hash_init(enum stm32_hash_algo_mode mode) { - stm32mp_clk_enable(stm32_hash.clock); + clk_enable(stm32_hash.clock); hash_hw_init(mode); - stm32mp_clk_disable(stm32_hash.clock); + clk_disable(stm32_hash.clock); zeromem(&stm32_remain, sizeof(stm32_remain)); } @@ -321,7 +322,7 @@ int stm32_hash_register(void) stm32_hash.base = hash_info.base; stm32_hash.clock = hash_info.clock; - stm32mp_clk_enable(stm32_hash.clock); + clk_enable(stm32_hash.clock); if (hash_info.reset >= 0) { uint32_t id = (uint32_t)hash_info.reset; @@ -335,7 +336,7 @@ int stm32_hash_register(void) } } - stm32mp_clk_disable(stm32_hash.clock); + clk_disable(stm32_hash.clock); return 0; } diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ddr.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ddr.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ddr.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ddr.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -7,46 +7,58 @@ #include #include -#include - #include #include #include +#include #include -#include #include #include #include #include +#include #include #include -struct reg_desc { - const char *name; - uint16_t offset; /* Offset for base address */ - uint8_t par_offset; /* Offset for parameter array */ -}; - -#define INVALID_OFFSET 0xFFU - -#define TIMEOUT_US_1S 1000000U +#include #define DDRCTL_REG(x, y) \ { \ .name = #x, \ - .offset = offsetof(struct stm32mp1_ddrctl, x), \ + .offset = offsetof(struct stm32mp_ddrctl, x), \ .par_offset = offsetof(struct y, x) \ } #define DDRPHY_REG(x, y) \ { \ .name = #x, \ - .offset = offsetof(struct stm32mp1_ddrphy, x), \ + .offset = offsetof(struct stm32mp_ddrphy, x), \ .par_offset = offsetof(struct y, x) \ } +/* + * PARAMETERS: value get from device tree : + * size / order need to be aligned with binding + * modification NOT ALLOWED !!! + */ +#define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */ +#define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */ +#define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */ +#if STM32MP_DDR_DUAL_AXI_PORT +#define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */ +#else +#define DDRCTL_REG_PERF_SIZE 11 /* st,ctl-perf */ +#endif + +#if STM32MP_DDR_32BIT_INTERFACE +#define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */ +#else +#define DDRPHY_REG_REG_SIZE 9 /* st,phy-reg */ +#endif +#define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */ + #define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg) -static const struct reg_desc ddr_reg[] = { +static const struct stm32mp_ddr_reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = { DDRCTL_REG_REG(mstr), DDRCTL_REG_REG(mrctrl0), DDRCTL_REG_REG(mrctrl1), @@ -75,7 +87,7 @@ static const struct reg_desc ddr_reg[] = }; #define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing) -static const struct reg_desc ddr_timing[] = { +static const struct stm32mp_ddr_reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = { DDRCTL_REG_TIMING(rfshtmg), DDRCTL_REG_TIMING(dramtmg0), DDRCTL_REG_TIMING(dramtmg1), @@ -91,7 +103,7 @@ static const struct reg_desc ddr_timing[ }; #define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map) -static const struct reg_desc ddr_map[] = { +static const struct stm32mp_ddr_reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = { DDRCTL_REG_MAP(addrmap1), DDRCTL_REG_MAP(addrmap2), DDRCTL_REG_MAP(addrmap3), @@ -104,7 +116,7 @@ static const struct reg_desc ddr_map[] = }; #define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf) -static const struct reg_desc ddr_perf[] = { +static const struct stm32mp_ddr_reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = { DDRCTL_REG_PERF(sched), DDRCTL_REG_PERF(sched1), DDRCTL_REG_PERF(perfhpr1), @@ -116,16 +128,18 @@ static const struct reg_desc ddr_perf[] DDRCTL_REG_PERF(pcfgqos1_0), DDRCTL_REG_PERF(pcfgwqos0_0), DDRCTL_REG_PERF(pcfgwqos1_0), +#if STM32MP_DDR_DUAL_AXI_PORT DDRCTL_REG_PERF(pcfgr_1), DDRCTL_REG_PERF(pcfgw_1), DDRCTL_REG_PERF(pcfgqos0_1), DDRCTL_REG_PERF(pcfgqos1_1), DDRCTL_REG_PERF(pcfgwqos0_1), DDRCTL_REG_PERF(pcfgwqos1_1), +#endif }; #define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg) -static const struct reg_desc ddrphy_reg[] = { +static const struct stm32mp_ddr_reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = { DDRPHY_REG_REG(pgcr), DDRPHY_REG_REG(aciocr), DDRPHY_REG_REG(dxccr), @@ -135,12 +149,14 @@ static const struct reg_desc ddrphy_reg[ DDRPHY_REG_REG(zq0cr1), DDRPHY_REG_REG(dx0gcr), DDRPHY_REG_REG(dx1gcr), +#if STM32MP_DDR_32BIT_INTERFACE DDRPHY_REG_REG(dx2gcr), DDRPHY_REG_REG(dx3gcr), +#endif }; #define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing) -static const struct reg_desc ddrphy_timing[] = { +static const struct stm32mp_ddr_reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = { DDRPHY_REG_TIMING(ptr0), DDRPHY_REG_TIMING(ptr1), DDRPHY_REG_TIMING(ptr2), @@ -153,174 +169,49 @@ static const struct reg_desc ddrphy_timi DDRPHY_REG_TIMING(mr3), }; -#define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal) -static const struct reg_desc ddrphy_cal[] = { - DDRPHY_REG_CAL(dx0dllcr), - DDRPHY_REG_CAL(dx0dqtr), - DDRPHY_REG_CAL(dx0dqstr), - DDRPHY_REG_CAL(dx1dllcr), - DDRPHY_REG_CAL(dx1dqtr), - DDRPHY_REG_CAL(dx1dqstr), - DDRPHY_REG_CAL(dx2dllcr), - DDRPHY_REG_CAL(dx2dqtr), - DDRPHY_REG_CAL(dx2dqstr), - DDRPHY_REG_CAL(dx3dllcr), - DDRPHY_REG_CAL(dx3dqtr), - DDRPHY_REG_CAL(dx3dqstr), -}; - -#define DDR_REG_DYN(x) \ - { \ - .name = #x, \ - .offset = offsetof(struct stm32mp1_ddrctl, x), \ - .par_offset = INVALID_OFFSET \ - } - -static const struct reg_desc ddr_dyn[] = { - DDR_REG_DYN(stat), - DDR_REG_DYN(init0), - DDR_REG_DYN(dfimisc), - DDR_REG_DYN(dfistat), - DDR_REG_DYN(swctl), - DDR_REG_DYN(swstat), - DDR_REG_DYN(pctrl_0), - DDR_REG_DYN(pctrl_1), -}; - -#define DDRPHY_REG_DYN(x) \ - { \ - .name = #x, \ - .offset = offsetof(struct stm32mp1_ddrphy, x), \ - .par_offset = INVALID_OFFSET \ - } - -static const struct reg_desc ddrphy_dyn[] = { - DDRPHY_REG_DYN(pir), - DDRPHY_REG_DYN(pgsr), -}; - -enum reg_type { - REG_REG, - REG_TIMING, - REG_PERF, - REG_MAP, - REGPHY_REG, - REGPHY_TIMING, - REGPHY_CAL, /* - * Dynamic registers => managed in driver or not changed, - * can be dumped in interactive mode. + * REGISTERS ARRAY: used to parse device tree and interactive mode */ - REG_DYN, - REGPHY_DYN, - REG_TYPE_NB -}; - -enum base_type { - DDR_BASE, - DDRPHY_BASE, - NONE_BASE -}; - -struct ddr_reg_info { - const char *name; - const struct reg_desc *desc; - uint8_t size; - enum base_type base; -}; - -static const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = { +static const struct stm32mp_ddr_reg_info ddr_registers[REG_TYPE_NB] = { [REG_REG] = { .name = "static", .desc = ddr_reg, - .size = ARRAY_SIZE(ddr_reg), + .size = DDRCTL_REG_REG_SIZE, .base = DDR_BASE }, [REG_TIMING] = { .name = "timing", .desc = ddr_timing, - .size = ARRAY_SIZE(ddr_timing), + .size = DDRCTL_REG_TIMING_SIZE, .base = DDR_BASE }, [REG_PERF] = { .name = "perf", .desc = ddr_perf, - .size = ARRAY_SIZE(ddr_perf), + .size = DDRCTL_REG_PERF_SIZE, .base = DDR_BASE }, [REG_MAP] = { .name = "map", .desc = ddr_map, - .size = ARRAY_SIZE(ddr_map), + .size = DDRCTL_REG_MAP_SIZE, .base = DDR_BASE }, [REGPHY_REG] = { .name = "static", .desc = ddrphy_reg, - .size = ARRAY_SIZE(ddrphy_reg), + .size = DDRPHY_REG_REG_SIZE, .base = DDRPHY_BASE }, [REGPHY_TIMING] = { .name = "timing", .desc = ddrphy_timing, - .size = ARRAY_SIZE(ddrphy_timing), - .base = DDRPHY_BASE - }, - [REGPHY_CAL] = { - .name = "cal", - .desc = ddrphy_cal, - .size = ARRAY_SIZE(ddrphy_cal), - .base = DDRPHY_BASE - }, - [REG_DYN] = { - .name = "dyn", - .desc = ddr_dyn, - .size = ARRAY_SIZE(ddr_dyn), - .base = DDR_BASE - }, - [REGPHY_DYN] = { - .name = "dyn", - .desc = ddrphy_dyn, - .size = ARRAY_SIZE(ddrphy_dyn), + .size = DDRPHY_REG_TIMING_SIZE, .base = DDRPHY_BASE }, }; -static uintptr_t get_base_addr(const struct ddr_info *priv, enum base_type base) -{ - if (base == DDRPHY_BASE) { - return (uintptr_t)priv->phy; - } else { - return (uintptr_t)priv->ctl; - } -} - -static void set_reg(const struct ddr_info *priv, - enum reg_type type, - const void *param) -{ - unsigned int i; - unsigned int value; - enum base_type base = ddr_registers[type].base; - uintptr_t base_addr = get_base_addr(priv, base); - const struct reg_desc *desc = ddr_registers[type].desc; - - VERBOSE("init %s\n", ddr_registers[type].name); - for (i = 0; i < ddr_registers[type].size; i++) { - uintptr_t ptr = base_addr + desc[i].offset; - - if (desc[i].par_offset == INVALID_OFFSET) { - ERROR("invalid parameter offset for %s", desc[i].name); - panic(); - } else { - value = *((uint32_t *)((uintptr_t)param + - desc[i].par_offset)); - mmio_write_32(ptr, value); - } - } -} - -static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy) +static void stm32mp1_ddrphy_idone_wait(struct stm32mp_ddrphy *phy) { uint32_t pgsr; int error = 0; @@ -365,7 +256,7 @@ static void stm32mp1_ddrphy_idone_wait(s (uintptr_t)&phy->pgsr, pgsr); } -static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, uint32_t pir) +static void stm32mp1_ddrphy_init(struct stm32mp_ddrphy *phy, uint32_t pir) { uint32_t pir_init = pir | DDRPHYC_PIR_INIT; @@ -381,40 +272,8 @@ static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy_idone_wait(phy); } -/* Start quasi dynamic register update */ -static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl) -{ - mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); - VERBOSE("[0x%lx] swctl = 0x%x\n", - (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); -} - /* Wait quasi dynamic register update */ -static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl) -{ - uint64_t timeout; - uint32_t swstat; - - mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); - VERBOSE("[0x%lx] swctl = 0x%x\n", - (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); - - timeout = timeout_init_us(TIMEOUT_US_1S); - do { - swstat = mmio_read_32((uintptr_t)&ctl->swstat); - VERBOSE("[0x%lx] swstat = 0x%x ", - (uintptr_t)&ctl->swstat, swstat); - if (timeout_elapsed(timeout)) { - panic(); - } - } while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U); - - VERBOSE("[0x%lx] swstat = 0x%x\n", - (uintptr_t)&ctl->swstat, swstat); -} - -/* Wait quasi dynamic register update */ -static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode) +static void stm32mp1_wait_operating_mode(struct stm32mp_ddr_priv *priv, uint32_t mode) { uint64_t timeout; uint32_t stat; @@ -463,7 +322,7 @@ static void stm32mp1_wait_operating_mode } /* Mode Register Writes (MRW or MRS) */ -static void stm32mp1_mode_register_write(struct ddr_info *priv, uint8_t addr, +static void stm32mp1_mode_register_write(struct stm32mp_ddr_priv *priv, uint8_t addr, uint32_t data) { uint32_t mrctrl0; @@ -518,7 +377,7 @@ static void stm32mp1_mode_register_write } /* Switch DDR3 from DLL-on to DLL-off */ -static void stm32mp1_ddr3_dll_off(struct ddr_info *priv) +static void stm32mp1_ddr3_dll_off(struct stm32mp_ddr_priv *priv) { uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1); uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2); @@ -609,14 +468,14 @@ static void stm32mp1_ddr3_dll_off(struct * 9. Set the MSTR.dll_off_mode = 1. * warning: MSTR.dll_off_mode is a quasi-dynamic type 2 field */ - stm32mp1_start_sw_done(priv->ctl); + stm32mp_ddr_start_sw_done(priv->ctl); mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); VERBOSE("[0x%lx] mstr = 0x%x\n", (uintptr_t)&priv->ctl->mstr, mmio_read_32((uintptr_t)&priv->ctl->mstr)); - stm32mp1_wait_sw_done_ack(priv->ctl); + stm32mp_ddr_wait_sw_done_ack(priv->ctl); /* 10. Change the clock frequency to the desired value. */ @@ -627,7 +486,7 @@ static void stm32mp1_ddr3_dll_off(struct */ /* Change Bypass Mode Frequency Range */ - if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) { + if (clk_get_rate(DDRPHYC) < 100000000U) { mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, DDRPHYC_DLLGCR_BPS200); } else { @@ -641,10 +500,12 @@ static void stm32mp1_ddr3_dll_off(struct DDRPHYC_DXNDLLCR_DLLDIS); mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, DDRPHYC_DXNDLLCR_DLLDIS); +#if STM32MP_DDR_32BIT_INTERFACE mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, DDRPHYC_DXNDLLCR_DLLDIS); mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, DDRPHYC_DXNDLLCR_DLLDIS); +#endif /* 12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0. */ mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, @@ -669,22 +530,22 @@ static void stm32mp1_ddr3_dll_off(struct mmio_read_32((uintptr_t)&priv->ctl->dbg1)); } -static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl) +static void stm32mp1_refresh_disable(struct stm32mp_ddrctl *ctl) { - stm32mp1_start_sw_done(ctl); + stm32mp_ddr_start_sw_done(ctl); /* Quasi-dynamic register update*/ mmio_setbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - stm32mp1_wait_sw_done_ack(ctl); + stm32mp_ddr_wait_sw_done_ack(ctl); } -static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, +static void stm32mp1_refresh_restore(struct stm32mp_ddrctl *ctl, uint32_t rfshctl3, uint32_t pwrctl) { - stm32mp1_start_sw_done(ctl); + stm32mp_ddr_start_sw_done(ctl); if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) { mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); @@ -695,30 +556,21 @@ static void stm32mp1_refresh_restore(str } mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - stm32mp1_wait_sw_done_ack(ctl); + stm32mp_ddr_wait_sw_done_ack(ctl); } -static int board_ddr_power_init(enum ddr_type ddr_type) -{ - if (dt_pmic_status() > 0) { - return pmic_ddr_power_init(ddr_type); - } - - return 0; -} - -void stm32mp1_ddr_init(struct ddr_info *priv, - struct stm32mp1_ddr_config *config) +void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, + struct stm32mp_ddr_config *config) { uint32_t pir; int ret = -EINVAL; if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) { - ret = board_ddr_power_init(STM32MP_DDR3); + ret = stm32mp_board_ddr_power_init(STM32MP_DDR3); } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) { - ret = board_ddr_power_init(STM32MP_LPDDR2); + ret = stm32mp_board_ddr_power_init(STM32MP_LPDDR2); } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) != 0U) { - ret = board_ddr_power_init(STM32MP_LPDDR3); + ret = stm32mp_board_ddr_power_init(STM32MP_LPDDR3); } else { ERROR("DDR type not supported\n"); } @@ -728,7 +580,7 @@ void stm32mp1_ddr_init(struct ddr_info * } VERBOSE("name = %s\n", config->info.name); - VERBOSE("speed = %d kHz\n", config->info.speed); + VERBOSE("speed = %u kHz\n", config->info.speed); VERBOSE("size = 0x%x\n", config->info.size); /* DDR INIT SEQUENCE */ @@ -773,7 +625,7 @@ void stm32mp1_ddr_init(struct ddr_info * (uintptr_t)&priv->ctl->dfimisc, mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); - set_reg(priv, REG_REG, &config->c_reg); + stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers); /* DDR3 = don't set DLLOFF for init mode */ if ((config->c_reg.mstr & @@ -787,8 +639,8 @@ void stm32mp1_ddr_init(struct ddr_info * mmio_read_32((uintptr_t)&priv->ctl->mstr)); } - set_reg(priv, REG_TIMING, &config->c_timing); - set_reg(priv, REG_MAP, &config->c_map); + stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers); + stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers); /* Skip CTRL init, SDRAM init is done by PHY PUBL */ mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0, @@ -798,7 +650,7 @@ void stm32mp1_ddr_init(struct ddr_info * (uintptr_t)&priv->ctl->init0, mmio_read_32((uintptr_t)&priv->ctl->init0)); - set_reg(priv, REG_PERF, &config->c_perf); + stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers); /* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */ mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); @@ -809,9 +661,8 @@ void stm32mp1_ddr_init(struct ddr_info * * 3. start PHY init by accessing relevant PUBL registers * (DXGCR, DCR, PTR*, MR*, DTPR*) */ - set_reg(priv, REGPHY_REG, &config->p_reg); - set_reg(priv, REGPHY_TIMING, &config->p_timing); - set_reg(priv, REGPHY_CAL, &config->p_cal); + stm32mp_ddr_set_reg(priv, REGPHY_REG, &config->p_reg, ddr_registers); + stm32mp_ddr_set_reg(priv, REGPHY_TIMING, &config->p_timing, ddr_registers); /* DDR3 = don't set DLLOFF for init mode */ if ((config->c_reg.mstr & @@ -849,7 +700,7 @@ void stm32mp1_ddr_init(struct ddr_info * * 6. SET DFIMISC.dfi_init_complete_en to 1 * Enable quasi-dynamic register programming. */ - stm32mp1_start_sw_done(priv->ctl); + stm32mp_ddr_start_sw_done(priv->ctl); mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); @@ -857,7 +708,7 @@ void stm32mp1_ddr_init(struct ddr_info * (uintptr_t)&priv->ctl->dfimisc, mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); - stm32mp1_wait_sw_done_ack(priv->ctl); + stm32mp_ddr_wait_sw_done_ack(priv->ctl); /* * 7. Wait for DWC_ddr_umctl2 to move to normal operation mode @@ -891,9 +742,14 @@ void stm32mp1_ddr_init(struct ddr_info * /* * 10. configure PUBL PIR register to specify which training step * to run - * Warning : RVTRN is not supported by this PUBL + * RVTRN is executed only on LPDDR2/LPDDR3 */ - stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN); + pir = DDRPHYC_PIR_QSTRN; + if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) == 0U) { + pir |= DDRPHYC_PIR_RVTRN; + } + + stm32mp1_ddrphy_init(priv->phy, pir); /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ stm32mp1_ddrphy_idone_wait(priv->phy); @@ -904,17 +760,5 @@ void stm32mp1_ddr_init(struct ddr_info * stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); - /* Enable uMCTL2 AXI port 0 */ - mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_0, - DDRCTRL_PCTRL_N_PORT_EN); - VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", - (uintptr_t)&priv->ctl->pctrl_0, - mmio_read_32((uintptr_t)&priv->ctl->pctrl_0)); - - /* Enable uMCTL2 AXI port 1 */ - mmio_setbits_32((uintptr_t)&priv->ctl->pctrl_1, - DDRCTRL_PCTRL_N_PORT_EN); - VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", - (uintptr_t)&priv->ctl->pctrl_1, - mmio_read_32((uintptr_t)&priv->ctl->pctrl_1)); + stm32mp_ddr_enable_axi_port(priv->ctl); } diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ddr_helpers.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ddr_helpers.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ddr_helpers.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ddr_helpers.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,21 +1,23 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ -#include - #include #include +#include + void ddr_enable_clock(void) { stm32mp1_clk_rcc_regs_lock(); mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, RCC_DDRITFCR_DDRC1EN | +#if STM32MP_DDR_DUAL_AXI_PORT RCC_DDRITFCR_DDRC2EN | +#endif RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN | RCC_DDRITFCR_DDRCAPBEN); diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ram.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ram.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp1_ram.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp1_ram.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,37 +1,37 @@ /* - * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ #include -#include - -#include - #include #include #include +#include #include #include #include +#include +#include +#include #include +#include -#define DDR_PATTERN 0xAAAAAAAAU -#define DDR_ANTIPATTERN 0x55555555U +#include -static struct ddr_info ddr_priv_data; +static struct stm32mp_ddr_priv ddr_priv_data; -int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) +int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed) { unsigned long ddrphy_clk, ddr_clk, mem_speed_hz; ddr_enable_clock(); - ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC); + ddrphy_clk = clk_get_rate(DDRPHYC); - VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n", + VERBOSE("DDR: mem_speed (%u kHz), RCC %lu kHz\n", mem_speed, ddrphy_clk / 1000U); mem_speed_hz = mem_speed * 1000U; @@ -43,157 +43,29 @@ int stm32mp1_ddr_clk_enable(struct ddr_i ddr_clk = mem_speed_hz - ddrphy_clk; } if (ddr_clk > (mem_speed_hz / 10)) { - ERROR("DDR expected freq %d kHz, current is %ld kHz\n", + ERROR("DDR expected freq %u kHz, current is %lu kHz\n", mem_speed, ddrphy_clk / 1000U); return -1; } return 0; } -/******************************************************************************* - * This function tests the DDR data bus wiring. - * This is inspired from the Data Bus Test algorithm written by Michael Barr - * in "Programming Embedded Systems in C and C++" book. - * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ - * File: memtest.c - This source code belongs to Public Domain. - * Returns 0 if success, and address value else. - ******************************************************************************/ -static uint32_t ddr_test_data_bus(void) -{ - uint32_t pattern; - - for (pattern = 1U; pattern != 0U; pattern <<= 1) { - mmio_write_32(STM32MP_DDR_BASE, pattern); - - if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { - return (uint32_t)STM32MP_DDR_BASE; - } - } - - return 0; -} - -/******************************************************************************* - * This function tests the DDR address bus wiring. - * This is inspired from the Data Bus Test algorithm written by Michael Barr - * in "Programming Embedded Systems in C and C++" book. - * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ - * File: memtest.c - This source code belongs to Public Domain. - * Returns 0 if success, and address value else. - ******************************************************************************/ -static uint32_t ddr_test_addr_bus(void) -{ - uint64_t addressmask = (ddr_priv_data.info.size - 1U); - uint64_t offset; - uint64_t testoffset = 0; - - /* Write the default pattern at each of the power-of-two offsets. */ - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; - offset <<= 1) { - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset, - DDR_PATTERN); - } - - /* Check for address bits stuck high. */ - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_ANTIPATTERN); - - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; - offset <<= 1) { - if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != - DDR_PATTERN) { - return (uint32_t)(STM32MP_DDR_BASE + offset); - } - } - - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); - - /* Check for address bits stuck low or shorted. */ - for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; - testoffset <<= 1) { - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_ANTIPATTERN); - - if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { - return STM32MP_DDR_BASE; - } - - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; - offset <<= 1) { - if ((mmio_read_32(STM32MP_DDR_BASE + - (uint32_t)offset) != DDR_PATTERN) && - (offset != testoffset)) { - return (uint32_t)(STM32MP_DDR_BASE + offset); - } - } - - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_PATTERN); - } - - return 0; -} - -/******************************************************************************* - * This function checks the DDR size. It has to be run with Data Cache off. - * This test is run before data have been put in DDR, and is only done for - * cold boot. The DDR data can then be overwritten, and it is not useful to - * restore its content. - * Returns DDR computed size. - ******************************************************************************/ -static uint32_t ddr_check_size(void) -{ - uint32_t offset = sizeof(uint32_t); - - mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); - - while (offset < STM32MP_DDR_MAX_SIZE) { - mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN); - dsb(); - - if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { - break; - } - - offset <<= 1; - } - - INFO("Memory size = 0x%x (%d MB)\n", offset, offset / (1024U * 1024U)); - - return offset; -} - static int stm32mp1_ddr_setup(void) { - struct ddr_info *priv = &ddr_priv_data; + struct stm32mp_ddr_priv *priv = &ddr_priv_data; int ret; - struct stm32mp1_ddr_config config; - int node, len; - uint32_t uret, idx; + struct stm32mp_ddr_config config; + int node; + uint32_t uret; void *fdt; -#define PARAM(x, y) \ - { \ - .name = x, \ - .offset = offsetof(struct stm32mp1_ddr_config, y), \ - .size = sizeof(config.y) / sizeof(uint32_t) \ - } - -#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) -#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) - - const struct { - const char *name; /* Name in DT */ - const uint32_t offset; /* Offset in config struct */ - const uint32_t size; /* Size of parameters */ - } param[] = { + const struct stm32mp_ddr_param param[] = { CTL_PARAM(reg), CTL_PARAM(timing), CTL_PARAM(map), CTL_PARAM(perf), PHY_PARAM(reg), PHY_PARAM(timing), - PHY_PARAM(cal) }; if (fdt_get_address(&fdt) == 0) { @@ -206,36 +78,14 @@ static int stm32mp1_ddr_setup(void) return -EINVAL; } - ret = fdt_read_uint32(fdt, node, "st,mem-speed", &config.info.speed); - if (ret < 0) { - VERBOSE("%s: no st,mem-speed\n", __func__); - return -EINVAL; - } - ret = fdt_read_uint32(fdt, node, "st,mem-size", &config.info.size); + ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); if (ret < 0) { - VERBOSE("%s: no st,mem-size\n", __func__); - return -EINVAL; + return ret; } - config.info.name = fdt_getprop(fdt, node, "st,mem-name", &len); - if (config.info.name == NULL) { - VERBOSE("%s: no st,mem-name\n", __func__); - return -EINVAL; - } - INFO("RAM: %s\n", config.info.name); - for (idx = 0; idx < ARRAY_SIZE(param); idx++) { - ret = fdt_read_uint32_array(fdt, node, param[idx].name, - param[idx].size, - (void *)((uintptr_t)&config + - param[idx].offset)); - - VERBOSE("%s: %s[0x%x] = %d\n", __func__, - param[idx].name, param[idx].size, ret); - if (ret != 0) { - ERROR("%s: Cannot read %s\n", - __func__, param[idx].name); - return -EINVAL; - } + ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config); + if (ret < 0) { + return ret; } /* Disable axidcg clock gating during init */ @@ -255,21 +105,21 @@ static int stm32mp1_ddr_setup(void) panic(); } - uret = ddr_test_data_bus(); + uret = stm32mp_ddr_test_data_bus(); if (uret != 0U) { ERROR("DDR data bus test: can't access memory @ 0x%x\n", uret); panic(); } - uret = ddr_test_addr_bus(); + uret = stm32mp_ddr_test_addr_bus(config.info.size); if (uret != 0U) { ERROR("DDR addr bus test: can't access memory @ 0x%x\n", uret); panic(); } - uret = ddr_check_size(); + uret = stm32mp_ddr_check_size(); if (uret < config.info.size) { ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", uret, config.info.size); @@ -285,12 +135,12 @@ static int stm32mp1_ddr_setup(void) int stm32mp1_ddr_probe(void) { - struct ddr_info *priv = &ddr_priv_data; + struct stm32mp_ddr_priv *priv = &ddr_priv_data; VERBOSE("STM32MP DDR probe\n"); - priv->ctl = (struct stm32mp1_ddrctl *)stm32mp_ddrctrl_base(); - priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base(); + priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base(); + priv->phy = (struct stm32mp_ddrphy *)stm32mp_ddrphyc_base(); priv->pwr = stm32mp_pwr_base(); priv->rcc = stm32mp_rcc_base(); diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp_ddr.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ddr.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp_ddr.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ddr.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define INVALID_OFFSET 0xFFU + +static uintptr_t get_base_addr(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_base_type base) +{ + if (base == DDRPHY_BASE) { + return (uintptr_t)priv->phy; + } else { + return (uintptr_t)priv->ctl; + } +} + +void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, + const void *param, const struct stm32mp_ddr_reg_info *ddr_registers) +{ + unsigned int i; + unsigned int value; + enum stm32mp_ddr_base_type base = ddr_registers[type].base; + uintptr_t base_addr = get_base_addr(priv, base); + const struct stm32mp_ddr_reg_desc *desc = ddr_registers[type].desc; + + VERBOSE("init %s\n", ddr_registers[type].name); + for (i = 0; i < ddr_registers[type].size; i++) { + uintptr_t ptr = base_addr + desc[i].offset; + + if (desc[i].par_offset == INVALID_OFFSET) { + ERROR("invalid parameter offset for %s", desc[i].name); + panic(); + } else { + value = *((uint32_t *)((uintptr_t)param + + desc[i].par_offset)); + mmio_write_32(ptr, value); + } + } +} + +/* Start quasi dynamic register update */ +void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl) +{ + mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); + VERBOSE("[0x%lx] swctl = 0x%x\n", + (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); +} + +/* Wait quasi dynamic register update */ +void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl) +{ + uint64_t timeout; + uint32_t swstat; + + mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); + VERBOSE("[0x%lx] swctl = 0x%x\n", + (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); + + timeout = timeout_init_us(TIMEOUT_US_1S); + do { + swstat = mmio_read_32((uintptr_t)&ctl->swstat); + VERBOSE("[0x%lx] swstat = 0x%x ", + (uintptr_t)&ctl->swstat, swstat); + if (timeout_elapsed(timeout)) { + panic(); + } + } while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U); + + VERBOSE("[0x%lx] swstat = 0x%x\n", + (uintptr_t)&ctl->swstat, swstat); +} + +void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl) +{ + /* Enable uMCTL2 AXI port 0 */ + mmio_setbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); + VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0, + mmio_read_32((uintptr_t)&ctl->pctrl_0)); + +#if STM32MP_DDR_DUAL_AXI_PORT + /* Enable uMCTL2 AXI port 1 */ + mmio_setbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); + VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1, + mmio_read_32((uintptr_t)&ctl->pctrl_1)); +#endif + +} + +int stm32mp_board_ddr_power_init(enum ddr_type ddr_type) +{ + if (dt_pmic_status() > 0) { + return pmic_ddr_power_init(ddr_type); + } + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp_ddr_test.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ddr_test.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp_ddr_test.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ddr_test.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#define DDR_PATTERN 0xAAAAAAAAU +#define DDR_ANTIPATTERN 0x55555555U + +/******************************************************************************* + * This function tests a simple read/write access to the DDR. + * Note that the previous content is restored after test. + * Returns 0 if success, and address value else. + ******************************************************************************/ +uint32_t stm32mp_ddr_test_rw_access(void) +{ + uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE); + + mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); + + if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + return (uint32_t)STM32MP_DDR_BASE; + } + + mmio_write_32(STM32MP_DDR_BASE, saved_value); + + return 0U; +} + +/******************************************************************************* + * This function tests the DDR data bus wiring. + * This is inspired from the Data Bus Test algorithm written by Michael Barr + * in "Programming Embedded Systems in C and C++" book. + * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ + * File: memtest.c - This source code belongs to Public Domain. + * Returns 0 if success, and address value else. + ******************************************************************************/ +uint32_t stm32mp_ddr_test_data_bus(void) +{ + uint32_t pattern; + + for (pattern = 1U; pattern != 0U; pattern <<= 1U) { + mmio_write_32(STM32MP_DDR_BASE, pattern); + + if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { + return (uint32_t)STM32MP_DDR_BASE; + } + } + + return 0; +} + +/******************************************************************************* + * This function tests the DDR address bus wiring. + * This is inspired from the Data Bus Test algorithm written by Michael Barr + * in "Programming Embedded Systems in C and C++" book. + * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ + * File: memtest.c - This source code belongs to Public Domain. + * size: size in bytes of the DDR memory device. + * Returns 0 if success, and address value else. + ******************************************************************************/ +uint32_t stm32mp_ddr_test_addr_bus(uint64_t size) +{ + uint64_t addressmask = size - 1U; + uint64_t offset; + uint64_t testoffset = 0U; + + /* Write the default pattern at each of the power-of-two offsets. */ + for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; + offset <<= 1U) { + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset, + DDR_PATTERN); + } + + /* Check for address bits stuck high. */ + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, + DDR_ANTIPATTERN); + + for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; + offset <<= 1U) { + if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != + DDR_PATTERN) { + return (uint32_t)(STM32MP_DDR_BASE + offset); + } + } + + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); + + /* Check for address bits stuck low or shorted. */ + for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; + testoffset <<= 1U) { + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, + DDR_ANTIPATTERN); + + if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + return STM32MP_DDR_BASE; + } + + for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; + offset <<= 1) { + if ((mmio_read_32(STM32MP_DDR_BASE + + (uint32_t)offset) != DDR_PATTERN) && + (offset != testoffset)) { + return (uint32_t)(STM32MP_DDR_BASE + offset); + } + } + + mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, + DDR_PATTERN); + } + + return 0U; +} + +/******************************************************************************* + * This function checks the DDR size. It has to be run with Data Cache off. + * This test is run before data have been put in DDR, and is only done for + * cold boot. The DDR data can then be overwritten, and it is not useful to + * restore its content. + * Returns DDR computed size. + ******************************************************************************/ +uint32_t stm32mp_ddr_check_size(void) +{ + uint32_t offset = sizeof(uint32_t); + + mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); + + while (offset < STM32MP_DDR_MAX_SIZE) { + mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN); + dsb(); + + if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + break; + } + + offset <<= 1U; + } + + INFO("Memory size = 0x%x (%u MB)\n", offset, offset / (1024U * 1024U)); + + return offset; +} diff -pruN 2.6+dfsg-1/drivers/st/ddr/stm32mp_ram.c 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ram.c --- 2.6+dfsg-1/drivers/st/ddr/stm32mp_ram.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/ddr/stm32mp_ram.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include + +#include + +int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info) +{ + int ret; + + ret = fdt_read_uint32(fdt, node, "st,mem-speed", &info->speed); + if (ret < 0) { + VERBOSE("%s: no st,mem-speed\n", __func__); + return -EINVAL; + } + ret = fdt_read_uint32(fdt, node, "st,mem-size", &info->size); + if (ret < 0) { + VERBOSE("%s: no st,mem-size\n", __func__); + return -EINVAL; + } + info->name = fdt_getprop(fdt, node, "st,mem-name", NULL); + if (info->name == NULL) { + VERBOSE("%s: no st,mem-name\n", __func__); + return -EINVAL; + } + + INFO("RAM: %s\n", info->name); + + return 0; +} + +int stm32mp_ddr_dt_get_param(void *fdt, int node, const struct stm32mp_ddr_param *param, + uint32_t param_size, uintptr_t config) +{ + int ret; + uint32_t idx; + + for (idx = 0U; idx < param_size; idx++) { + ret = fdt_read_uint32_array(fdt, node, param[idx].name, param[idx].size, + (void *)(config + param[idx].offset)); + + VERBOSE("%s: %s[0x%x] = %d\n", __func__, param[idx].name, param[idx].size, ret); + if (ret != 0) { + ERROR("%s: Cannot read %s, error=%d\n", __func__, param[idx].name, ret); + return -EINVAL; + } + } + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/st/fmc/stm32_fmc2_nand.c 2.7.0+dfsg-2/drivers/st/fmc/stm32_fmc2_nand.c --- 2.6+dfsg-1/drivers/st/fmc/stm32_fmc2_nand.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/fmc/stm32_fmc2_nand.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -9,11 +9,8 @@ #include #include -#include - -#include - #include +#include #include #include #include @@ -21,6 +18,9 @@ #include #include #include +#include + +#include /* Timeout for device interface reset */ #define TIMEOUT_US_1_MS 1000U @@ -162,7 +162,7 @@ static uintptr_t fmc2_base(void) static void stm32_fmc2_nand_setup_timing(void) { struct stm32_fmc2_nand_timings tims; - unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id); + unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id); unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); unsigned long timing, tar, tclr, thiz, twait; unsigned long tset_mem, tset_att, thold_mem, thold_att; @@ -515,7 +515,7 @@ static int stm32_fmc2_read_page(struct n unsigned int s; int ret; - VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); + VERBOSE(">%s page %u buffer %lx\n", __func__, page, buffer); ret = nand_read_page_cmd(page, 0U, 0U, 0U); if (ret != 0) { @@ -909,7 +909,7 @@ int stm32_fmc2_init(void) } /* Enable Clock */ - stm32mp_clk_enable(stm32_fmc2.clock_id); + clk_enable(stm32_fmc2.clock_id); /* Reset IP */ ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); diff -pruN 2.6+dfsg-1/drivers/st/gpio/stm32_gpio.c 2.7.0+dfsg-2/drivers/st/gpio/stm32_gpio.c --- 2.6+dfsg-1/drivers/st/gpio/stm32_gpio.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/gpio/stm32_gpio.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,16 +8,16 @@ #include #include -#include - -#include - #include #include +#include #include #include #include #include +#include + +#include #define DT_GPIO_BANK_SHIFT 12 #define DT_GPIO_BANK_MASK GENMASK(16, 12) @@ -25,6 +25,10 @@ #define DT_GPIO_PIN_MASK GENMASK(11, 8) #define DT_GPIO_MODE_MASK GENMASK(7, 0) +static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, + uint32_t speed, uint32_t pull, uint32_t od, + uint32_t alternate, uint8_t status); + /******************************************************************************* * This function gets GPIO bank node in DT. * Returns node offset if status is okay in DT, else return 0 @@ -99,6 +103,8 @@ static int dt_set_gpio_config(void *fdt, uint32_t pin; uint32_t mode; uint32_t alternate = GPIO_ALTERNATE_(0); + uint32_t type; + uint32_t od = GPIO_OD_OUTPUT_LOW; int bank_node; int clk; @@ -128,7 +134,23 @@ static int dt_set_gpio_config(void *fdt, } if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) { - mode |= GPIO_OPEN_DRAIN; + type = GPIO_TYPE_OPEN_DRAIN; + } else { + type = GPIO_TYPE_PUSH_PULL; + } + + if (fdt_getprop(fdt, node, "output-high", NULL) != NULL) { + if (mode == GPIO_MODE_INPUT) { + mode = GPIO_MODE_OUTPUT; + od = GPIO_OD_OUTPUT_HIGH; + } + } + + if (fdt_getprop(fdt, node, "output-low", NULL) != NULL) { + if (mode == GPIO_MODE_INPUT) { + mode = GPIO_MODE_OUTPUT; + od = GPIO_OD_OUTPUT_LOW; + } } bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); @@ -145,7 +167,7 @@ static int dt_set_gpio_config(void *fdt, /* Platform knows the clock: assert it is okay */ assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); - set_gpio(bank, pin, mode, speed, pull, alternate, status); + set_gpio(bank, pin, mode, type, speed, pull, od, alternate, status); } return 0; @@ -159,7 +181,7 @@ static int dt_set_gpio_config(void *fdt, int dt_set_pinctrl_config(int node) { const fdt32_t *cuint; - int lenp = 0; + int lenp; uint32_t i; uint8_t status; void *fdt; @@ -200,51 +222,53 @@ int dt_set_pinctrl_config(int node) return 0; } -void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, - uint32_t pull, uint32_t alternate, uint8_t status) +static void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t type, + uint32_t speed, uint32_t pull, uint32_t od, + uint32_t alternate, uint8_t status) { uintptr_t base = stm32_get_gpio_bank_base(bank); unsigned long clock = stm32_get_gpio_bank_clock(bank); assert(pin <= GPIO_PIN_MAX); - stm32mp_clk_enable(clock); - - mmio_clrbits_32(base + GPIO_MODE_OFFSET, - ((uint32_t)GPIO_MODE_MASK << (pin << 1))); - mmio_setbits_32(base + GPIO_MODE_OFFSET, - (mode & ~GPIO_OPEN_DRAIN) << (pin << 1)); - - if ((mode & GPIO_OPEN_DRAIN) != 0U) { - mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); - } else { - mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); - } - - mmio_clrbits_32(base + GPIO_SPEED_OFFSET, - ((uint32_t)GPIO_SPEED_MASK << (pin << 1))); - mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); + clk_enable(clock); - mmio_clrbits_32(base + GPIO_PUPD_OFFSET, - ((uint32_t)GPIO_PULL_MASK << (pin << 1))); - mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); + mmio_clrsetbits_32(base + GPIO_MODE_OFFSET, + (uint32_t)GPIO_MODE_MASK << (pin << 1), + mode << (pin << 1)); + + mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET, + (uint32_t)GPIO_TYPE_MASK << pin, + type << pin); + + mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET, + (uint32_t)GPIO_SPEED_MASK << (pin << 1), + speed << (pin << 1)); + + mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET, + (uint32_t)GPIO_PULL_MASK << (pin << 1), + pull << (pin << 1)); if (pin < GPIO_ALT_LOWER_LIMIT) { - mmio_clrbits_32(base + GPIO_AFRL_OFFSET, - ((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2))); - mmio_setbits_32(base + GPIO_AFRL_OFFSET, - alternate << (pin << 2)); + mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET, + (uint32_t)GPIO_ALTERNATE_MASK << (pin << 2), + alternate << (pin << 2)); } else { - mmio_clrbits_32(base + GPIO_AFRH_OFFSET, - ((uint32_t)GPIO_ALTERNATE_MASK << - ((pin - GPIO_ALT_LOWER_LIMIT) << 2))); - mmio_setbits_32(base + GPIO_AFRH_OFFSET, - alternate << ((pin - GPIO_ALT_LOWER_LIMIT) << - 2)); + size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; + + mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET, + (uint32_t)GPIO_ALTERNATE_MASK << shift, + alternate << shift); } + mmio_clrsetbits_32(base + GPIO_OD_OFFSET, + (uint32_t)GPIO_OD_MASK << pin, + od << pin); + VERBOSE("GPIO %u mode set to 0x%x\n", bank, mmio_read_32(base + GPIO_MODE_OFFSET)); + VERBOSE("GPIO %u type set to 0x%x\n", bank, + mmio_read_32(base + GPIO_TYPE_OFFSET)); VERBOSE("GPIO %u speed set to 0x%x\n", bank, mmio_read_32(base + GPIO_SPEED_OFFSET)); VERBOSE("GPIO %u mode pull to 0x%x\n", bank, @@ -253,16 +277,22 @@ void set_gpio(uint32_t bank, uint32_t pi mmio_read_32(base + GPIO_AFRL_OFFSET)); VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, mmio_read_32(base + GPIO_AFRH_OFFSET)); + VERBOSE("GPIO %u output data set to 0x%x\n", bank, + mmio_read_32(base + GPIO_OD_OFFSET)); - stm32mp_clk_disable(clock); + clk_disable(clock); if (status == DT_SECURE) { stm32mp_register_secure_gpio(bank, pin); +#if !IMAGE_BL2 set_gpio_secure_cfg(bank, pin, true); +#endif } else { stm32mp_register_non_secure_gpio(bank, pin); +#if !IMAGE_BL2 set_gpio_secure_cfg(bank, pin, false); +#endif } } @@ -273,7 +303,7 @@ void set_gpio_secure_cfg(uint32_t bank, assert(pin <= GPIO_PIN_MAX); - stm32mp_clk_enable(clock); + clk_enable(clock); if (secure) { mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); @@ -281,5 +311,13 @@ void set_gpio_secure_cfg(uint32_t bank, mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); } - stm32mp_clk_disable(clock); + clk_disable(clock); +} + +void set_gpio_reset_cfg(uint32_t bank, uint32_t pin) +{ + set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_TYPE_PUSH_PULL, + GPIO_SPEED_LOW, GPIO_NO_PULL, GPIO_OD_OUTPUT_LOW, + GPIO_ALTERNATE_(0), DT_DISABLED); + set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank)); } diff -pruN 2.6+dfsg-1/drivers/st/i2c/stm32_i2c.c 2.7.0+dfsg-2/drivers/st/i2c/stm32_i2c.c --- 2.6+dfsg-1/drivers/st/i2c/stm32_i2c.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/i2c/stm32_i2c.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -158,7 +159,7 @@ int stm32_i2c_init(struct i2c_handle_s * hi2c->i2c_state = I2C_STATE_BUSY; - stm32mp_clk_enable(hi2c->clock); + clk_enable(hi2c->clock); /* Disable the selected I2C peripheral */ mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE); @@ -220,11 +221,11 @@ int stm32_i2c_init(struct i2c_handle_s * I2C_ANALOGFILTER_DISABLE); if (rc != 0) { ERROR("Cannot initialize I2C analog filter (%d)\n", rc); - stm32mp_clk_disable(hi2c->clock); + clk_disable(hi2c->clock); return rc; } - stm32mp_clk_disable(hi2c->clock); + clk_disable(hi2c->clock); return rc; } @@ -548,7 +549,7 @@ static int i2c_write(struct i2c_handle_s return -EINVAL; } - stm32mp_clk_enable(hi2c->clock); + clk_enable(hi2c->clock); hi2c->lock = 1; @@ -648,7 +649,7 @@ static int i2c_write(struct i2c_handle_s bail: hi2c->lock = 0; - stm32mp_clk_disable(hi2c->clock); + clk_disable(hi2c->clock); return rc; } @@ -729,7 +730,7 @@ static int i2c_read(struct i2c_handle_s return -EINVAL; } - stm32mp_clk_enable(hi2c->clock); + clk_enable(hi2c->clock); hi2c->lock = 1; @@ -817,7 +818,7 @@ static int i2c_read(struct i2c_handle_s bail: hi2c->lock = 0; - stm32mp_clk_disable(hi2c->clock); + clk_disable(hi2c->clock); return rc; } @@ -882,7 +883,7 @@ bool stm32_i2c_is_device_ready(struct i2 return rc; } - stm32mp_clk_enable(hi2c->clock); + clk_enable(hi2c->clock); hi2c->lock = 1; hi2c->i2c_mode = I2C_MODE_NONE; @@ -974,7 +975,7 @@ bool stm32_i2c_is_device_ready(struct i2 bail: hi2c->lock = 0; - stm32mp_clk_disable(hi2c->clock); + clk_disable(hi2c->clock); return rc; } diff -pruN 2.6+dfsg-1/drivers/st/iwdg/stm32_iwdg.c 2.7.0+dfsg-2/drivers/st/iwdg/stm32_iwdg.c --- 2.6+dfsg-1/drivers/st/iwdg/stm32_iwdg.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/iwdg/stm32_iwdg.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -61,12 +62,12 @@ void stm32_iwdg_refresh(void) /* 0x00000000 is not a valid address for IWDG peripherals */ if (iwdg->base != 0U) { - stm32mp_clk_enable(iwdg->clock); + clk_enable(iwdg->clock); mmio_write_32(iwdg->base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY); - stm32mp_clk_disable(iwdg->clock); + clk_disable(iwdg->clock); } } } diff -pruN 2.6+dfsg-1/drivers/st/mmc/stm32_sdmmc2.c 2.7.0+dfsg-2/drivers/st/mmc/stm32_sdmmc2.c --- 2.6+dfsg-1/drivers/st/mmc/stm32_sdmmc2.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/mmc/stm32_sdmmc2.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,13 +8,10 @@ #include #include -#include - -#include - #include #include #include +#include #include #include #include @@ -22,8 +19,11 @@ #include #include #include +#include #include +#include + /* Registers offsets */ #define SDMMC_POWER 0x00U #define SDMMC_CLKCR 0x04U @@ -50,6 +50,7 @@ /* SDMMC power control register */ #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) +#define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) #define SDMMC_POWER_DIRPOL BIT(4) /* SDMMC clock control register */ @@ -117,7 +118,16 @@ #define TIMEOUT_US_10_MS 10000U #define TIMEOUT_US_1_S 1000000U +/* Power cycle delays in ms */ +#define VCC_POWER_OFF_DELAY 2 +#define VCC_POWER_ON_DELAY 2 +#define POWER_CYCLE_DELAY 2 +#define POWER_OFF_DELAY 2 +#define POWER_ON_DELAY 1 + +#ifndef DT_SDMMC2_COMPAT #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" +#endif static void stm32_sdmmc2_init(void); static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); @@ -149,11 +159,37 @@ static void stm32_sdmmc2_init(void) uint32_t clock_div; uint32_t freq = STM32MP_MMC_INIT_FREQ; uintptr_t base = sdmmc2_params.reg_base; + int ret; if (sdmmc2_params.max_freq != 0U) { freq = MIN(sdmmc2_params.max_freq, freq); } + if (sdmmc2_params.vmmc_regu != NULL) { + ret = regulator_disable(sdmmc2_params.vmmc_regu); + if (ret < 0) { + panic(); + } + } + + mdelay(VCC_POWER_OFF_DELAY); + + mmio_write_32(base + SDMMC_POWER, + SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); + mdelay(POWER_CYCLE_DELAY); + + if (sdmmc2_params.vmmc_regu != NULL) { + ret = regulator_enable(sdmmc2_params.vmmc_regu); + if (ret < 0) { + panic(); + } + } + + mdelay(VCC_POWER_ON_DELAY); + + mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); + mdelay(POWER_OFF_DELAY); + clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | @@ -163,7 +199,7 @@ static void stm32_sdmmc2_init(void) mmio_write_32(base + SDMMC_POWER, SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); - mdelay(1); + mdelay(POWER_ON_DELAY); } static int stm32_sdmmc2_stop_transfer(void) @@ -285,7 +321,7 @@ static int stm32_sdmmc2_send_cmd_req(str while ((status & flags_cmd) == 0U) { if (timeout_elapsed(timeout)) { err = -ETIMEDOUT; - ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", + ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", __func__, cmd->cmd_idx, status); goto err_exit; } @@ -305,12 +341,12 @@ static int stm32_sdmmc2_send_cmd_req(str (cmd->cmd_idx == MMC_CMD(13)) || ((cmd->cmd_idx == MMC_CMD(8)) && (cmd->resp_type == MMC_RESPONSE_R7)))) { - ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", + ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n", __func__, cmd->cmd_idx, status); } } else { err = -EIO; - ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", + ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n", __func__, cmd->cmd_idx, status); } @@ -351,7 +387,7 @@ static int stm32_sdmmc2_send_cmd_req(str while ((status & flags_data) == 0U) { if (timeout_elapsed(timeout)) { - ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", + ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", __func__, cmd->cmd_idx, status); err = -ETIMEDOUT; goto err_exit; @@ -363,7 +399,7 @@ static int stm32_sdmmc2_send_cmd_req(str if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | SDMMC_STAR_IDMATE)) != 0U) { - ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, + ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__, cmd->cmd_idx, status); err = -EIO; } @@ -689,6 +725,8 @@ static int stm32_sdmmc2_dt_get_config(vo sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); } + sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); + return 0; } @@ -709,12 +747,14 @@ int stm32_sdmmc2_mmc_init(struct stm32_s memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); + sdmmc2_params.vmmc_regu = NULL; + if (stm32_sdmmc2_dt_get_config() != 0) { ERROR("%s: DT error\n", __func__); return -ENOMEM; } - stm32mp_clk_enable(sdmmc2_params.clock_id); + clk_enable(sdmmc2_params.clock_id); rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); if (rc != 0) { @@ -727,7 +767,7 @@ int stm32_sdmmc2_mmc_init(struct stm32_s } mdelay(1); - sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id); + sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, diff -pruN 2.6+dfsg-1/drivers/st/pmic/stm32mp_pmic.c 2.7.0+dfsg-2/drivers/st/pmic/stm32mp_pmic.c --- 2.6+dfsg-1/drivers/st/pmic/stm32mp_pmic.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/pmic/stm32mp_pmic.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,57 +1,66 @@ /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ +#include #include -#include - -#include - #include #include +#include #include #include #include #include #include +#include -#define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2)) -#define STPMIC1_LDO12356_OUTPUT_SHIFT 2 -#define STPMIC1_LDO3_MODE (uint8_t)(BIT(7)) -#define STPMIC1_LDO3_DDR_SEL 31U -#define STPMIC1_LDO3_1800000 (9U << STPMIC1_LDO12356_OUTPUT_SHIFT) - -#define STPMIC1_BUCK_OUTPUT_SHIFT 2 -#define STPMIC1_BUCK3_1V8 (39U << STPMIC1_BUCK_OUTPUT_SHIFT) +#include -#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 +#define PMIC_NODE_NOT_FOUND 1 static struct i2c_handle_s i2c_handle; static uint32_t pmic_i2c_addr; +static int register_pmic(void); + static int dt_get_pmic_node(void *fdt) { - return fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1"); + static int node = -FDT_ERR_BADOFFSET; + + if (node == -FDT_ERR_BADOFFSET) { + node = fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1"); + } + + return node; } int dt_pmic_status(void) { + static int status = -FDT_ERR_BADVALUE; int node; void *fdt; + if (status != -FDT_ERR_BADVALUE) { + return status; + } + if (fdt_get_address(&fdt) == 0) { return -ENOENT; } node = dt_get_pmic_node(fdt); if (node <= 0) { - return -FDT_ERR_NOTFOUND; + status = -FDT_ERR_NOTFOUND; + + return status; } - return fdt_get_status(node); + status = (int)fdt_get_status(node); + + return status; } static bool dt_pmic_is_secure(void) @@ -65,125 +74,49 @@ static bool dt_pmic_is_secure(void) /* * Get PMIC and its I2C bus configuration from the device tree. - * Return 0 on success, negative on error, 1 if no PMIC node is found. + * Return 0 on success, negative on error, 1 if no PMIC node is defined. */ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info, struct stm32_i2c_init_s *init) { - int pmic_node, i2c_node; + static int i2c_node = -FDT_ERR_NOTFOUND; void *fdt; - const fdt32_t *cuint; if (fdt_get_address(&fdt) == 0) { - return -ENOENT; - } - - pmic_node = dt_get_pmic_node(fdt); - if (pmic_node < 0) { - return 1; - } - - cuint = fdt_getprop(fdt, pmic_node, "reg", NULL); - if (cuint == NULL) { return -FDT_ERR_NOTFOUND; } - pmic_i2c_addr = fdt32_to_cpu(*cuint) << 1; - if (pmic_i2c_addr > UINT16_MAX) { - return -EINVAL; - } - - i2c_node = fdt_parent_offset(fdt, pmic_node); - if (i2c_node < 0) { - return -FDT_ERR_NOTFOUND; - } - - dt_fill_device_info(i2c_info, i2c_node); - if (i2c_info->base == 0U) { - return -FDT_ERR_NOTFOUND; - } - - return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init); -} - -int dt_pmic_configure_boot_on_regulators(void) -{ - int pmic_node, regulators_node, regulator_node; - void *fdt; - - if (fdt_get_address(&fdt) == 0) { - return -ENOENT; - } - - pmic_node = dt_get_pmic_node(fdt); - if (pmic_node < 0) { - return -FDT_ERR_NOTFOUND; - } - - regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators"); - if (regulators_node < 0) { - return -ENOENT; - } - - fdt_for_each_subnode(regulator_node, fdt, regulators_node) { + if (i2c_node == -FDT_ERR_NOTFOUND) { + int pmic_node; const fdt32_t *cuint; - const char *node_name = fdt_get_name(fdt, regulator_node, NULL); - uint16_t voltage; - int status; - -#if defined(IMAGE_BL2) - if ((fdt_getprop(fdt, regulator_node, "regulator-boot-on", - NULL) == NULL) && - (fdt_getprop(fdt, regulator_node, "regulator-always-on", - NULL) == NULL)) { -#else - if (fdt_getprop(fdt, regulator_node, "regulator-boot-on", - NULL) == NULL) { -#endif - continue; - } - - if (fdt_getprop(fdt, regulator_node, "regulator-pull-down", - NULL) != NULL) { - - status = stpmic1_regulator_pull_down_set(node_name); - if (status != 0) { - return status; - } - } - if (fdt_getprop(fdt, regulator_node, "st,mask-reset", - NULL) != NULL) { - - status = stpmic1_regulator_mask_reset_set(node_name); - if (status != 0) { - return status; - } + pmic_node = dt_get_pmic_node(fdt); + if (pmic_node < 0) { + return PMIC_NODE_NOT_FOUND; } - cuint = fdt_getprop(fdt, regulator_node, - "regulator-min-microvolt", NULL); + cuint = fdt_getprop(fdt, pmic_node, "reg", NULL); if (cuint == NULL) { - continue; + return -FDT_ERR_NOTFOUND; } - /* DT uses microvolts, whereas driver awaits millivolts */ - voltage = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U); - - status = stpmic1_regulator_voltage_set(node_name, voltage); - if (status != 0) { - return status; + pmic_i2c_addr = fdt32_to_cpu(*cuint) << 1; + if (pmic_i2c_addr > UINT16_MAX) { + return -FDT_ERR_BADVALUE; } - if (stpmic1_is_regulator_enabled(node_name) == 0U) { - status = stpmic1_regulator_enable(node_name); - if (status != 0) { - return status; - } + i2c_node = fdt_parent_offset(fdt, pmic_node); + if (i2c_node < 0) { + return -FDT_ERR_NOTFOUND; } } - return 0; + dt_fill_device_info(i2c_info, i2c_node); + if (i2c_info->base == 0U) { + return -FDT_ERR_NOTFOUND; + } + + return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init); } bool initialize_pmic_i2c(void) @@ -251,8 +184,6 @@ static void register_pmic_shared_periphe void initialize_pmic(void) { - unsigned long pmic_version; - if (!initialize_pmic_i2c()) { VERBOSE("No PMIC\n"); return; @@ -260,70 +191,84 @@ void initialize_pmic(void) register_pmic_shared_peripherals(); + if (register_pmic() < 0) { + panic(); + } + + if (stpmic1_powerctrl_on() < 0) { + panic(); + } + +} + +#if DEBUG +void print_pmic_info_and_debug(void) +{ + unsigned long pmic_version; + if (stpmic1_get_version(&pmic_version) != 0) { ERROR("Failed to access PMIC\n"); panic(); } INFO("PMIC version = 0x%02lx\n", pmic_version); - stpmic1_dump_regulators(); - -#if defined(IMAGE_BL2) - if (dt_pmic_configure_boot_on_regulators() != 0) { - panic(); - }; -#endif } +#endif int pmic_ddr_power_init(enum ddr_type ddr_type) { - bool buck3_at_1v8 = false; - uint8_t read_val; int status; + uint16_t buck3_min_mv; + struct rdev *buck2, *buck3, *vref; + struct rdev *ldo3 __unused; - switch (ddr_type) { - case STM32MP_DDR3: - /* Set LDO3 to sync mode */ - status = stpmic1_register_read(LDO3_CONTROL_REG, &read_val); - if (status != 0) { - return status; - } + buck2 = regulator_get_by_name("buck2"); + if (buck2 == NULL) { + return -ENOENT; + } - read_val &= ~STPMIC1_LDO3_MODE; - read_val &= ~STPMIC1_LDO12356_OUTPUT_MASK; - read_val |= STPMIC1_LDO3_DDR_SEL << - STPMIC1_LDO12356_OUTPUT_SHIFT; +#if STM32MP15 + ldo3 = regulator_get_by_name("ldo3"); + if (ldo3 == NULL) { + return -ENOENT; + } +#endif + + vref = regulator_get_by_name("vref_ddr"); + if (vref == NULL) { + return -ENOENT; + } - status = stpmic1_register_write(LDO3_CONTROL_REG, read_val); + switch (ddr_type) { + case STM32MP_DDR3: +#if STM32MP15 + status = regulator_set_flag(ldo3, REGUL_SINK_SOURCE); if (status != 0) { return status; } +#endif - status = stpmic1_regulator_voltage_set("buck2", 1350); + status = regulator_set_min_voltage(buck2); if (status != 0) { return status; } - status = stpmic1_regulator_enable("buck2"); + status = regulator_enable(buck2); if (status != 0) { return status; } - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - - status = stpmic1_regulator_enable("vref_ddr"); + status = regulator_enable(vref); if (status != 0) { return status; } - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - - status = stpmic1_regulator_enable("ldo3"); +#if STM32MP15 + status = regulator_enable(ldo3); if (status != 0) { return status; } - - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); +#endif break; case STM32MP_LPDDR2: @@ -333,62 +278,249 @@ int pmic_ddr_power_init(enum ddr_type dd * Set LDO3 to bypass mode if BUCK3 = 1.8V * Set LDO3 to normal mode if BUCK3 != 1.8V */ - status = stpmic1_register_read(BUCK3_CONTROL_REG, &read_val); - if (status != 0) { - return status; + buck3 = regulator_get_by_name("buck3"); + if (buck3 == NULL) { + return -ENOENT; } - if ((read_val & STPMIC1_BUCK3_1V8) == STPMIC1_BUCK3_1V8) { - buck3_at_1v8 = true; + regulator_get_range(buck3, &buck3_min_mv, NULL); + +#if STM32MP15 + if (buck3_min_mv != 1800) { + status = regulator_set_min_voltage(ldo3); + if (status != 0) { + return status; + } + } else { + status = regulator_set_flag(ldo3, REGUL_ENABLE_BYPASS); + if (status != 0) { + return status; + } } +#endif - status = stpmic1_register_read(LDO3_CONTROL_REG, &read_val); + status = regulator_set_min_voltage(buck2); if (status != 0) { return status; } - read_val &= ~STPMIC1_LDO3_MODE; - read_val &= ~STPMIC1_LDO12356_OUTPUT_MASK; - read_val |= STPMIC1_LDO3_1800000; - if (buck3_at_1v8) { - read_val |= STPMIC1_LDO3_MODE; - } - - status = stpmic1_register_write(LDO3_CONTROL_REG, read_val); +#if STM32MP15 + status = regulator_enable(ldo3); if (status != 0) { return status; } +#endif - status = stpmic1_regulator_voltage_set("buck2", 1200); + status = regulator_enable(buck2); if (status != 0) { return status; } - status = stpmic1_regulator_enable("ldo3"); + status = regulator_enable(vref); if (status != 0) { return status; } + break; - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); + default: + break; + }; - status = stpmic1_regulator_enable("buck2"); - if (status != 0) { - return status; - } + return 0; +} - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); +int pmic_voltages_init(void) +{ +#if STM32MP13 + struct rdev *buck1, *buck4; + int status; - status = stpmic1_regulator_enable("vref_ddr"); - if (status != 0) { - return status; - } + buck1 = regulator_get_by_name("buck1"); + if (buck1 == NULL) { + return -ENOENT; + } - mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - break; + buck4 = regulator_get_by_name("buck4"); + if (buck4 == NULL) { + return -ENOENT; + } + + status = regulator_set_min_voltage(buck1); + if (status != 0) { + return status; + } + + status = regulator_set_min_voltage(buck4); + if (status != 0) { + return status; + } +#endif + + return 0; +} + +enum { + STPMIC1_BUCK1 = 0, + STPMIC1_BUCK2, + STPMIC1_BUCK3, + STPMIC1_BUCK4, + STPMIC1_LDO1, + STPMIC1_LDO2, + STPMIC1_LDO3, + STPMIC1_LDO4, + STPMIC1_LDO5, + STPMIC1_LDO6, + STPMIC1_VREF_DDR, + STPMIC1_BOOST, + STPMIC1_VBUS_OTG, + STPMIC1_SW_OUT, +}; + +static int pmic_set_state(const struct regul_description *desc, bool enable) +{ + VERBOSE("%s: set state to %d\n", desc->node_name, enable); + + if (enable == STATE_ENABLE) { + return stpmic1_regulator_enable(desc->node_name); + } else { + return stpmic1_regulator_disable(desc->node_name); + } +} + +static int pmic_get_state(const struct regul_description *desc) +{ + VERBOSE("%s: get state\n", desc->node_name); + + return stpmic1_is_regulator_enabled(desc->node_name); +} + +static int pmic_get_voltage(const struct regul_description *desc) +{ + VERBOSE("%s: get volt\n", desc->node_name); + + return stpmic1_regulator_voltage_get(desc->node_name); +} + +static int pmic_set_voltage(const struct regul_description *desc, uint16_t mv) +{ + VERBOSE("%s: get volt\n", desc->node_name); + + return stpmic1_regulator_voltage_set(desc->node_name, mv); +} + +static int pmic_list_voltages(const struct regul_description *desc, + const uint16_t **levels, size_t *count) +{ + VERBOSE("%s: list volt\n", desc->node_name); + + return stpmic1_regulator_levels_mv(desc->node_name, levels, count); +} + +static int pmic_set_flag(const struct regul_description *desc, uint16_t flag) +{ + VERBOSE("%s: set_flag 0x%x\n", desc->node_name, flag); + + switch (flag) { + case REGUL_OCP: + return stpmic1_regulator_icc_set(desc->node_name); + + case REGUL_ACTIVE_DISCHARGE: + return stpmic1_active_discharge_mode_set(desc->node_name); + + case REGUL_PULL_DOWN: + return stpmic1_regulator_pull_down_set(desc->node_name); + + case REGUL_MASK_RESET: + return stpmic1_regulator_mask_reset_set(desc->node_name); + + case REGUL_SINK_SOURCE: + return stpmic1_regulator_sink_mode_set(desc->node_name); + + case REGUL_ENABLE_BYPASS: + return stpmic1_regulator_bypass_mode_set(desc->node_name); default: - break; - }; + return -EINVAL; + } +} + +static const struct regul_ops pmic_ops = { + .set_state = pmic_set_state, + .get_state = pmic_get_state, + .set_voltage = pmic_set_voltage, + .get_voltage = pmic_get_voltage, + .list_voltages = pmic_list_voltages, + .set_flag = pmic_set_flag, +}; + +#define DEFINE_REGU(name) { \ + .node_name = name, \ + .ops = &pmic_ops, \ + .driver_data = NULL, \ + .enable_ramp_delay = 1000, \ +} + +static const struct regul_description pmic_regs[] = { + [STPMIC1_BUCK1] = DEFINE_REGU("buck1"), + [STPMIC1_BUCK2] = DEFINE_REGU("buck2"), + [STPMIC1_BUCK3] = DEFINE_REGU("buck3"), + [STPMIC1_BUCK4] = DEFINE_REGU("buck4"), + [STPMIC1_LDO1] = DEFINE_REGU("ldo1"), + [STPMIC1_LDO2] = DEFINE_REGU("ldo2"), + [STPMIC1_LDO3] = DEFINE_REGU("ldo3"), + [STPMIC1_LDO4] = DEFINE_REGU("ldo4"), + [STPMIC1_LDO5] = DEFINE_REGU("ldo5"), + [STPMIC1_LDO6] = DEFINE_REGU("ldo6"), + [STPMIC1_VREF_DDR] = DEFINE_REGU("vref_ddr"), + [STPMIC1_BOOST] = DEFINE_REGU("boost"), + [STPMIC1_VBUS_OTG] = DEFINE_REGU("pwr_sw1"), + [STPMIC1_SW_OUT] = DEFINE_REGU("pwr_sw2"), +}; + +#define NB_REG ARRAY_SIZE(pmic_regs) + +static int register_pmic(void) +{ + void *fdt; + int pmic_node, regulators_node, subnode; + + VERBOSE("Register pmic\n"); + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + pmic_node = dt_get_pmic_node(fdt); + if (pmic_node < 0) { + return pmic_node; + } + + regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators"); + if (regulators_node < 0) { + return -ENOENT; + } + + fdt_for_each_subnode(subnode, fdt, regulators_node) { + const char *reg_name = fdt_get_name(fdt, subnode, NULL); + const struct regul_description *desc; + unsigned int i; + int ret; + + for (i = 0; i < NB_REG; i++) { + desc = &pmic_regs[i]; + if (strcmp(desc->node_name, reg_name) == 0) { + break; + } + } + assert(i < NB_REG); + + ret = regulator_register(desc, subnode); + if (ret != 0) { + WARN("%s:%d failed to register %s\n", __func__, + __LINE__, reg_name); + return ret; + } + } return 0; } diff -pruN 2.6+dfsg-1/drivers/st/pmic/stpmic1.c 2.7.0+dfsg-2/drivers/st/pmic/stpmic1.c --- 2.6+dfsg-1/drivers/st/pmic/stpmic1.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/pmic/stpmic1.c 2022-06-01 15:02:46.000000000 +0000 @@ -23,10 +23,17 @@ struct regul_struct { uint8_t pull_down; uint8_t mask_reset_reg; uint8_t mask_reset; + uint8_t icc_reg; + uint8_t icc_mask; }; static struct i2c_handle_s *pmic_i2c_handle; static uint16_t pmic_i2c_addr; +/* + * Special mode corresponds to LDO3 in sink source mode or in bypass mode. + * LDO3 doesn't switch back from special to normal mode. + */ +static bool ldo3_special_mode; /* Voltage tables in mV */ static const uint16_t buck1_voltage_table[] = { @@ -347,8 +354,11 @@ static const uint16_t ldo3_voltage_table 3300, 3300, 3300, - 500, - 0xFFFF, /* VREFDDR */ +}; + +/* Special mode table is used for sink source OR bypass mode */ +static const uint16_t ldo3_special_mode_table[] = { + 0, }; static const uint16_t ldo5_voltage_table[] = { @@ -421,6 +431,10 @@ static const uint16_t vref_ddr_voltage_t 3300, }; +static const uint16_t fixed_5v_voltage_table[] = { + 5000, +}; + /* Table of Regulators in PMIC SoC */ static const struct regul_struct regulators_table[] = { { @@ -434,6 +448,8 @@ static const struct regul_struct regulat .pull_down = BUCK1_PULL_DOWN_SHIFT, .mask_reset_reg = MASK_RESET_BUCK_REG, .mask_reset = BUCK1_MASK_RESET, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = BUCK1_ICC_SHIFT, }, { .dt_node_name = "buck2", @@ -446,6 +462,8 @@ static const struct regul_struct regulat .pull_down = BUCK2_PULL_DOWN_SHIFT, .mask_reset_reg = MASK_RESET_BUCK_REG, .mask_reset = BUCK2_MASK_RESET, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = BUCK2_ICC_SHIFT, }, { .dt_node_name = "buck3", @@ -458,6 +476,8 @@ static const struct regul_struct regulat .pull_down = BUCK3_PULL_DOWN_SHIFT, .mask_reset_reg = MASK_RESET_BUCK_REG, .mask_reset = BUCK3_MASK_RESET, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = BUCK3_ICC_SHIFT, }, { .dt_node_name = "buck4", @@ -470,6 +490,8 @@ static const struct regul_struct regulat .pull_down = BUCK4_PULL_DOWN_SHIFT, .mask_reset_reg = MASK_RESET_BUCK_REG, .mask_reset = BUCK4_MASK_RESET, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = BUCK4_ICC_SHIFT, }, { .dt_node_name = "ldo1", @@ -480,6 +502,8 @@ static const struct regul_struct regulat .low_power_reg = LDO1_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO1_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO1_ICC_SHIFT, }, { .dt_node_name = "ldo2", @@ -490,6 +514,8 @@ static const struct regul_struct regulat .low_power_reg = LDO2_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO2_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO2_ICC_SHIFT, }, { .dt_node_name = "ldo3", @@ -500,6 +526,8 @@ static const struct regul_struct regulat .low_power_reg = LDO3_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO3_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO3_ICC_SHIFT, }, { .dt_node_name = "ldo4", @@ -510,6 +538,8 @@ static const struct regul_struct regulat .low_power_reg = LDO4_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO4_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO4_ICC_SHIFT, }, { .dt_node_name = "ldo5", @@ -520,6 +550,8 @@ static const struct regul_struct regulat .low_power_reg = LDO5_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO5_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO5_ICC_SHIFT, }, { .dt_node_name = "ldo6", @@ -530,6 +562,8 @@ static const struct regul_struct regulat .low_power_reg = LDO6_PWRCTRL_REG, .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = LDO6_MASK_RESET, + .icc_reg = LDO_ICC_TURNOFF_REG, + .icc_mask = LDO6_ICC_SHIFT, }, { .dt_node_name = "vref_ddr", @@ -541,6 +575,33 @@ static const struct regul_struct regulat .mask_reset_reg = MASK_RESET_LDO_REG, .mask_reset = VREF_DDR_MASK_RESET, }, + { + .dt_node_name = "boost", + .voltage_table = fixed_5v_voltage_table, + .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), + .control_reg = USB_CONTROL_REG, + .enable_mask = BOOST_ENABLED, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = BOOST_ICC_SHIFT, + }, + { + .dt_node_name = "pwr_sw1", + .voltage_table = fixed_5v_voltage_table, + .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), + .control_reg = USB_CONTROL_REG, + .enable_mask = USBSW_OTG_SWITCH_ENABLED, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = PWR_SW1_ICC_SHIFT, + }, + { + .dt_node_name = "pwr_sw2", + .voltage_table = fixed_5v_voltage_table, + .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), + .control_reg = USB_CONTROL_REG, + .enable_mask = SWIN_SWOUT_ENABLED, + .icc_reg = BUCK_ICC_TURNOFF_REG, + .icc_mask = PWR_SW2_ICC_SHIFT, + }, }; #define MAX_REGUL ARRAY_SIZE(regulators_table) @@ -606,7 +667,7 @@ int stpmic1_regulator_disable(const char regul->enable_mask); } -uint8_t stpmic1_is_regulator_enabled(const char *name) +bool stpmic1_is_regulator_enabled(const char *name) { uint8_t val; const struct regul_struct *regul = get_regulator_data(name); @@ -615,7 +676,7 @@ uint8_t stpmic1_is_regulator_enabled(con panic(); } - return (val & regul->enable_mask); + return (val & regul->enable_mask) == regul->enable_mask; } int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts) @@ -624,11 +685,21 @@ int stpmic1_regulator_voltage_set(const const struct regul_struct *regul = get_regulator_data(name); uint8_t mask; + if ((strncmp(name, "ldo3", 5) == 0) && ldo3_special_mode) { + /* + * when the LDO3 is in special mode, we do not change voltage, + * because by setting voltage, the LDO would leaves sink-source + * mode. There is obviously no reason to leave sink-source mode + * at runtime. + */ + return 0; + } + /* Voltage can be set for buck or ldo (except ldo4) regulators */ if (strncmp(name, "buck", 4) == 0) { mask = BUCK_VOLTAGE_MASK; } else if ((strncmp(name, "ldo", 3) == 0) && - (strncmp(name, "ldo4", 4) != 0)) { + (strncmp(name, "ldo4", 5) != 0)) { mask = LDO_VOLTAGE_MASK; } else { return 0; @@ -657,12 +728,90 @@ int stpmic1_regulator_mask_reset_set(con { const struct regul_struct *regul = get_regulator_data(name); + if (regul->mask_reset_reg == 0U) { + return -EPERM; + } + return stpmic1_register_update(regul->mask_reset_reg, BIT(regul->mask_reset), LDO_BUCK_RESET_MASK << regul->mask_reset); } +int stpmic1_regulator_icc_set(const char *name) +{ + const struct regul_struct *regul = get_regulator_data(name); + + if (regul->mask_reset_reg == 0U) { + return -EPERM; + } + + return stpmic1_register_update(regul->icc_reg, + BIT(regul->icc_mask), + BIT(regul->icc_mask)); +} + +int stpmic1_regulator_sink_mode_set(const char *name) +{ + if (strncmp(name, "ldo3", 5) != 0) { + return -EPERM; + } + + ldo3_special_mode = true; + + /* disable bypass mode, enable sink mode */ + return stpmic1_register_update(LDO3_CONTROL_REG, + LDO3_DDR_SEL << LDO_BUCK_VOLTAGE_SHIFT, + LDO3_BYPASS | LDO_VOLTAGE_MASK); +} + +int stpmic1_regulator_bypass_mode_set(const char *name) +{ + if (strncmp(name, "ldo3", 5) != 0) { + return -EPERM; + } + + ldo3_special_mode = true; + + /* enable bypass mode, disable sink mode */ + return stpmic1_register_update(LDO3_CONTROL_REG, + LDO3_BYPASS, + LDO3_BYPASS | LDO_VOLTAGE_MASK); +} + +int stpmic1_active_discharge_mode_set(const char *name) +{ + if (strncmp(name, "pwr_sw1", 8) == 0) { + return stpmic1_register_update(USB_CONTROL_REG, + VBUS_OTG_DISCHARGE, + VBUS_OTG_DISCHARGE); + } + + if (strncmp(name, "pwr_sw2", 8) == 0) { + return stpmic1_register_update(USB_CONTROL_REG, + SW_OUT_DISCHARGE, + SW_OUT_DISCHARGE); + } + + return -EPERM; +} + +int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels, + size_t *levels_count) +{ + const struct regul_struct *regul = get_regulator_data(name); + + if ((strncmp(name, "ldo3", 5) == 0) && ldo3_special_mode) { + *levels_count = ARRAY_SIZE(ldo3_special_mode_table); + *levels = ldo3_special_mode_table; + } else { + *levels_count = regul->voltage_table_size; + *levels = regul->voltage_table; + } + + return 0; +} + int stpmic1_regulator_voltage_get(const char *name) { const struct regul_struct *regul = get_regulator_data(name); @@ -670,11 +819,15 @@ int stpmic1_regulator_voltage_get(const uint8_t mask; int status; + if ((strncmp(name, "ldo3", 5) == 0) && ldo3_special_mode) { + return 0; + } + /* Voltage can be set for buck or ldo (except ldo4) regulators */ if (strncmp(name, "buck", 4) == 0) { mask = BUCK_VOLTAGE_MASK; } else if ((strncmp(name, "ldo", 3) == 0) && - (strncmp(name, "ldo4", 4) != 0)) { + (strncmp(name, "ldo4", 5) != 0)) { mask = LDO_VOLTAGE_MASK; } else { return 0; diff -pruN 2.6+dfsg-1/drivers/st/regulator/regulator_core.c 2.7.0+dfsg-2/drivers/st/regulator/regulator_core.c --- 2.6+dfsg-1/drivers/st/regulator/regulator_core.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/regulator/regulator_core.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define MAX_PROPERTY_LEN 64 + +static struct rdev rdev_array[PLAT_NB_RDEVS]; + +#define for_each_rdev(rdev) \ + for (rdev = rdev_array; rdev < (rdev_array + PLAT_NB_RDEVS); rdev++) + +#define for_each_registered_rdev(rdev) \ + for (rdev = rdev_array; \ + (rdev < (rdev_array + PLAT_NB_RDEVS)) && (rdev->desc != NULL); rdev++) + +static void lock_driver(const struct rdev *rdev) +{ + if (rdev->desc->ops->lock != NULL) { + rdev->desc->ops->lock(rdev->desc); + } +} + +static void unlock_driver(const struct rdev *rdev) +{ + if (rdev->desc->ops->unlock != NULL) { + rdev->desc->ops->unlock(rdev->desc); + } +} + +static struct rdev *regulator_get_by_phandle(int32_t phandle) +{ + struct rdev *rdev; + + for_each_registered_rdev(rdev) { + if (rdev->phandle == phandle) { + return rdev; + } + } + + WARN("%s: phandle %d not found\n", __func__, phandle); + return NULL; +} + +/* + * Get a regulator from its node name + * + * @fdt - pointer to device tree memory + * @node_name - name of the node "ldo1" + * Return pointer to rdev if succeed, NULL else. + */ +struct rdev *regulator_get_by_name(const char *node_name) +{ + struct rdev *rdev; + + assert(node_name != NULL); + VERBOSE("get %s\n", node_name); + + for_each_registered_rdev(rdev) { + if (strcmp(rdev->desc->node_name, node_name) == 0) { + return rdev; + } + } + + WARN("%s: %s not found\n", __func__, node_name); + return NULL; +} + +static int32_t get_supply_phandle(const void *fdt, int node, const char *name) +{ + const fdt32_t *cuint; + int len __unused; + int supply_phandle = -FDT_ERR_NOTFOUND; + char prop_name[MAX_PROPERTY_LEN]; + + len = snprintf(prop_name, MAX_PROPERTY_LEN - 1, "%s-supply", name); + assert((len >= 0) && (len < MAX_PROPERTY_LEN - 1)); + + cuint = fdt_getprop(fdt, node, prop_name, NULL); + if (cuint != NULL) { + supply_phandle = fdt32_to_cpu(*cuint); + VERBOSE("%s: supplied by %d\n", name, supply_phandle); + } + + return supply_phandle; +} + +/* + * Get a regulator from a supply name + * + * @fdt - pointer to device tree memory + * @node - offset of the node that contains the supply description + * @name - name of the supply "vdd" for "vdd-supply' + * Return pointer to rdev if succeed, NULL else. + */ +struct rdev *regulator_get_by_supply_name(const void *fdt, int node, const char *name) +{ + const int p = get_supply_phandle(fdt, node, name); + + if (p < 0) { + return NULL; + } + + return regulator_get_by_phandle(p); +} + +static int __regulator_set_state(struct rdev *rdev, bool state) +{ + if (rdev->desc->ops->set_state == NULL) { + return -ENODEV; + } + + return rdev->desc->ops->set_state(rdev->desc, state); +} + +/* + * Enable regulator + * + * @rdev - pointer to rdev struct + * Return 0 if succeed, non 0 else. + */ +int regulator_enable(struct rdev *rdev) +{ + int ret; + + assert(rdev != NULL); + + ret = __regulator_set_state(rdev, STATE_ENABLE); + + udelay(rdev->enable_ramp_delay); + + return ret; +} + +/* + * Disable regulator + * + * @rdev - pointer to rdev struct + * Return 0 if succeed, non 0 else. + */ +int regulator_disable(struct rdev *rdev) +{ + int ret; + + assert(rdev != NULL); + + if (rdev->flags & REGUL_ALWAYS_ON) { + return 0; + } + + ret = __regulator_set_state(rdev, STATE_DISABLE); + + udelay(rdev->enable_ramp_delay); + + return ret; +} + +/* + * Regulator enabled query + * + * @rdev - pointer to rdev struct + * Return 0 if disabled, 1 if enabled, <0 else. + */ +int regulator_is_enabled(const struct rdev *rdev) +{ + int ret; + + assert(rdev != NULL); + + VERBOSE("%s: is en\n", rdev->desc->node_name); + + if (rdev->desc->ops->get_state == NULL) { + return -ENODEV; + } + + lock_driver(rdev); + + ret = rdev->desc->ops->get_state(rdev->desc); + if (ret < 0) { + ERROR("regul %s get state failed: err:%d\n", + rdev->desc->node_name, ret); + } + + unlock_driver(rdev); + + return ret; +} + +/* + * Set regulator voltage + * + * @rdev - pointer to rdev struct + * @mvolt - Target voltage level in millivolt + * Return 0 if succeed, non 0 else. + */ +int regulator_set_voltage(struct rdev *rdev, uint16_t mvolt) +{ + int ret; + + assert(rdev != NULL); + + VERBOSE("%s: set mvolt\n", rdev->desc->node_name); + + if (rdev->desc->ops->set_voltage == NULL) { + return -ENODEV; + } + + if ((mvolt < rdev->min_mv) || (mvolt > rdev->max_mv)) { + return -EPERM; + } + + lock_driver(rdev); + + ret = rdev->desc->ops->set_voltage(rdev->desc, mvolt); + if (ret < 0) { + ERROR("regul %s set volt failed: err:%d\n", + rdev->desc->node_name, ret); + } + + unlock_driver(rdev); + + return ret; +} + +/* + * Set regulator min voltage + * + * @rdev - pointer to rdev struct + * Return 0 if succeed, non 0 else. + */ +int regulator_set_min_voltage(struct rdev *rdev) +{ + return regulator_set_voltage(rdev, rdev->min_mv); +} + +/* + * Get regulator voltage + * + * @rdev - pointer to rdev struct + * Return milli volts if succeed, <0 else. + */ +int regulator_get_voltage(const struct rdev *rdev) +{ + int ret; + + assert(rdev != NULL); + + VERBOSE("%s: get volt\n", rdev->desc->node_name); + + if (rdev->desc->ops->get_voltage == NULL) { + return rdev->min_mv; + } + + lock_driver(rdev); + + ret = rdev->desc->ops->get_voltage(rdev->desc); + if (ret < 0) { + ERROR("regul %s get voltage failed: err:%d\n", + rdev->desc->node_name, ret); + } + + unlock_driver(rdev); + + return ret; +} + +/* + * List regulator voltages + * + * @rdev - pointer to rdev struct + * @levels - out: array of supported millitvolt levels from min to max value + * @count - out: number of possible millivolt values + * Return 0 if succeed, non 0 else. + */ +int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count) +{ + int ret; + size_t n; + + assert(rdev != NULL); + assert(levels != NULL); + assert(count != NULL); + + VERBOSE("%s: list volt\n", rdev->desc->node_name); + + if (rdev->desc->ops->list_voltages == NULL) { + return -ENODEV; + } + + lock_driver(rdev); + + ret = rdev->desc->ops->list_voltages(rdev->desc, levels, count); + + unlock_driver(rdev); + + if (ret < 0) { + ERROR("regul %s list_voltages failed: err: %d\n", + rdev->desc->node_name, ret); + return ret; + } + + /* + * Reduce the possible values depending on min and max from device-tree + */ + n = *count; + while ((n > 1U) && ((*levels)[n - 1U] > rdev->max_mv)) { + n--; + } + + /* Verify that max val is a valid value */ + if (rdev->max_mv != (*levels)[n - 1]) { + ERROR("regul %s: max value %u is invalid\n", + rdev->desc->node_name, rdev->max_mv); + return -EINVAL; + } + + while ((n > 1U) && ((*levels[0U]) < rdev->min_mv)) { + (*levels)++; + n--; + } + + /* Verify that min is not too high */ + if (n == 0U) { + ERROR("regul %s set min voltage is too high\n", + rdev->desc->node_name); + return -EINVAL; + } + + /* Verify that min val is a valid vlue */ + if (rdev->min_mv != (*levels)[0U]) { + ERROR("regul %s: min value %u is invalid\n", + rdev->desc->node_name, rdev->min_mv); + return -EINVAL; + } + + *count = n; + + VERBOSE("rdev->min_mv=%u rdev->max_mv=%u\n", rdev->min_mv, rdev->max_mv); + + return 0; +} + +/* + * Get regulator voltages range + * + * @rdev - pointer to rdev struct + * @min_mv - out: min possible millivolt value + * @max_mv - out: max possible millivolt value + * Return 0 if succeed, non 0 else. + */ +void regulator_get_range(const struct rdev *rdev, uint16_t *min_mv, uint16_t *max_mv) +{ + assert(rdev != NULL); + + if (min_mv != NULL) { + *min_mv = rdev->min_mv; + } + if (max_mv != NULL) { + *max_mv = rdev->max_mv; + } +} + +/* + * Set regulator flag + * + * @rdev - pointer to rdev struct + * @flag - flag value to set (eg: REGUL_OCP) + * Return 0 if succeed, non 0 else. + */ +int regulator_set_flag(struct rdev *rdev, uint16_t flag) +{ + int ret; + + /* check that only one bit is set on flag */ + if (__builtin_popcount(flag) != 1) { + return -EINVAL; + } + + /* REGUL_ALWAYS_ON and REGUL_BOOT_ON are internal properties of the core */ + if ((flag == REGUL_ALWAYS_ON) || (flag == REGUL_BOOT_ON)) { + rdev->flags |= flag; + return 0; + } + + if (rdev->desc->ops->set_flag == NULL) { + ERROR("%s can not set any flag\n", rdev->desc->node_name); + return -ENODEV; + } + + lock_driver(rdev); + + ret = rdev->desc->ops->set_flag(rdev->desc, flag); + + unlock_driver(rdev); + + if (ret != 0) { + ERROR("%s: could not set flag %d ret=%d\n", + rdev->desc->node_name, flag, ret); + return ret; + } + + rdev->flags |= flag; + + return 0; +} + +static int parse_properties(const void *fdt, struct rdev *rdev, int node) +{ + int ret; + + if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) { + VERBOSE("%s: set regulator-always-on\n", rdev->desc->node_name); + ret = regulator_set_flag(rdev, REGUL_ALWAYS_ON); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +/* + * Parse the device-tree for a regulator + * + * Read min/max voltage from dt and check its validity + * Read the properties, and call the driver to set flags + * Read power supply phandle + * Read and store low power mode states + * + * @rdev - pointer to rdev struct + * @node - device-tree node offset of the regulator + * Return 0 if disabled, 1 if enabled, <0 else. + */ +static int parse_dt(struct rdev *rdev, int node) +{ + void *fdt; + const fdt32_t *cuint; + const uint16_t *levels; + size_t size; + int ret; + + VERBOSE("%s: parse dt\n", rdev->desc->node_name); + + if (fdt_get_address(&fdt) == 0) { + return -ENOENT; + } + + rdev->phandle = fdt_get_phandle(fdt, node); + + cuint = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); + if (cuint != NULL) { + uint16_t min_mv; + + min_mv = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U); + VERBOSE("%s: min_mv=%d\n", rdev->desc->node_name, (int)min_mv); + if (min_mv <= rdev->max_mv) { + rdev->min_mv = min_mv; + } else { + ERROR("%s: min_mv=%d is too high\n", + rdev->desc->node_name, (int)min_mv); + return -EINVAL; + } + } + + cuint = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); + if (cuint != NULL) { + uint16_t max_mv; + + max_mv = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U); + VERBOSE("%s: max_mv=%d\n", rdev->desc->node_name, (int)max_mv); + if (max_mv >= rdev->min_mv) { + rdev->max_mv = max_mv; + } else { + ERROR("%s: max_mv=%d is too low\n", + rdev->desc->node_name, (int)max_mv); + return -EINVAL; + } + } + + /* validate that min and max values can be used */ + ret = regulator_list_voltages(rdev, &levels, &size); + if ((ret != 0) && (ret != -ENODEV)) { + return ret; + } + + ret = parse_properties(fdt, rdev, node); + if (ret != 0) { + return ret; + } + + return 0; +} + +/* + * Register a regulator driver in regulator framework. + * Initialize voltage range from driver description + * + * @desc - pointer to the regulator description + * @node - device-tree node offset of the regulator + * Return 0 if succeed, non 0 else. + */ +int regulator_register(const struct regul_description *desc, int node) +{ + struct rdev *rdev; + + assert(desc != NULL); + + VERBOSE("register %s\n", desc->node_name); + + for_each_rdev(rdev) { + if (rdev->desc == NULL) { + break; + } + } + + if (rdev == rdev_array + PLAT_NB_RDEVS) { + WARN("Not enough place for regulators, PLAT_NB_RDEVS should be increased.\n"); + return -ENOMEM; + } + + rdev->desc = desc; + rdev->enable_ramp_delay = rdev->desc->enable_ramp_delay; + + if (rdev->desc->ops->list_voltages != NULL) { + int ret; + const uint16_t *levels; + size_t count; + + lock_driver(rdev); + + ret = rdev->desc->ops->list_voltages(rdev->desc, &levels, &count); + + unlock_driver(rdev); + + if (ret < 0) { + ERROR("regul %s set state failed: err:%d\n", + rdev->desc->node_name, ret); + return ret; + } + + rdev->min_mv = levels[0]; + rdev->max_mv = levels[count - 1U]; + } else { + rdev->max_mv = UINT16_MAX; + } + + return parse_dt(rdev, node); +} diff -pruN 2.6+dfsg-1/drivers/st/regulator/regulator_fixed.c 2.7.0+dfsg-2/drivers/st/regulator/regulator_fixed.c --- 2.6+dfsg-1/drivers/st/regulator/regulator_fixed.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/regulator/regulator_fixed.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include +#include +#include + +#ifndef PLAT_NB_FIXED_REGS +#error "Missing PLAT_NB_FIXED_REGS" +#endif + +#define FIXED_NAME_LEN 32 + +struct fixed_data { + char name[FIXED_NAME_LEN]; + uint16_t volt; + struct regul_description desc; +}; + +static struct fixed_data data[PLAT_NB_FIXED_REGS]; + +static int fixed_set_state(const struct regul_description *desc, bool state) +{ + return 0; +} + +static int fixed_get_state(const struct regul_description *desc) +{ + return 1; +} + +static struct regul_ops fixed_ops = { + .set_state = fixed_set_state, + .get_state = fixed_get_state, +}; + +int fixed_regulator_register(void) +{ + uint32_t count = 0; + void *fdt; + int node; + + VERBOSE("fixed reg init!\n"); + + if (fdt_get_address(&fdt) == 0) { + return -FDT_ERR_NOTFOUND; + } + + fdt_for_each_compatible_node(fdt, node, "regulator-fixed") { + int len __unused; + int ret; + struct fixed_data *d = &data[count]; + const char *reg_name; + + reg_name = fdt_get_name(fdt, node, NULL); + + VERBOSE("register fixed reg %s!\n", reg_name); + + len = snprintf(d->name, FIXED_NAME_LEN - 1, "%s", reg_name); + assert((len > 0) && (len < (FIXED_NAME_LEN - 1))); + + d->desc.node_name = d->name; + d->desc.driver_data = d; + d->desc.ops = &fixed_ops; + + ret = regulator_register(&d->desc, node); + if (ret != 0) { + WARN("%s:%d failed to register %s\n", __func__, + __LINE__, reg_name); + return ret; + } + + count++; + assert(count <= PLAT_NB_FIXED_REGS); + + } + + return 0; +} diff -pruN 2.6+dfsg-1/drivers/st/spi/stm32_qspi.c 2.7.0+dfsg-2/drivers/st/spi/stm32_qspi.c --- 2.6+dfsg-1/drivers/st/spi/stm32_qspi.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/spi/stm32_qspi.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,16 +1,14 @@ /* - * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ #include -#include - -#include #include #include +#include #include #include #include @@ -18,6 +16,9 @@ #include #include #include +#include + +#include /* Timeout for device interface reset */ #define TIMEOUT_US_1_MS 1000U @@ -138,10 +139,6 @@ static int stm32_qspi_wait_cmd(const str int ret = 0; uint64_t timeout; - if (op->data.nbytes == 0U) { - return stm32_qspi_wait_for_not_busy(); - } - timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { if (timeout_elapsed(timeout)) { @@ -162,6 +159,10 @@ static int stm32_qspi_wait_cmd(const str /* Clear flags */ mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); + if (ret == 0) { + ret = stm32_qspi_wait_for_not_busy(); + } + return ret; } @@ -250,11 +251,6 @@ static int stm32_qspi_exec_op(const stru op->dummy.buswidth, op->data.buswidth, op->addr.val, op->data.nbytes); - ret = stm32_qspi_wait_for_not_busy(); - if (ret != 0) { - return ret; - } - addr_max = op->addr.val + op->data.nbytes + 1U; if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { @@ -364,7 +360,7 @@ static void stm32_qspi_release_bus(void) static int stm32_qspi_set_speed(unsigned int hz) { - unsigned long qspi_clk = stm32mp_clk_get_rate(stm32_qspi.clock_id); + unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id); uint32_t prescaler = UINT8_MAX; uint32_t csht; int ret; @@ -494,7 +490,7 @@ int stm32_qspi_init(void) stm32_qspi.clock_id = (unsigned long)info.clock; stm32_qspi.reset_id = (unsigned int)info.reset; - stm32mp_clk_enable(stm32_qspi.clock_id); + clk_enable(stm32_qspi.clock_id); ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS); if (ret != 0) { diff -pruN 2.6+dfsg-1/drivers/st/uart/aarch32/stm32_console.S 2.7.0+dfsg-2/drivers/st/uart/aarch32/stm32_console.S --- 2.6+dfsg-1/drivers/st/uart/aarch32/stm32_console.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/uart/aarch32/stm32_console.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,9 +67,24 @@ func console_stm32_core_init bic r3, r3, #USART_CR2_STOP str r3, [r0, #USART_CR2] /* Divisor = (Uart clock + (baudrate / 2)) / baudrate */ - lsl r3, r2, #1 + lsr r3, r2, #1 add r3, r1, r3 udiv r3, r3, r2 + cmp r3, #16 + bhi 2f + /* Oversampling 8 */ + /* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */ + lsr r3, r2, #1 + add r3, r3, r1, lsl #1 + udiv r3, r3, r2 + and r1, r3, #USART_BRR_DIV_FRACTION + lsr r1, r1, #1 + bic r3, r3, #USART_BRR_DIV_FRACTION + orr r3, r3, r1 + ldr r1, [r0, #USART_CR1] + orr r1, r1, #USART_CR1_OVER8 + str r1, [r0, #USART_CR1] +2: str r3, [r0, #USART_BRR] /* Enable UART */ ldr r3, [r0, #USART_CR1] diff -pruN 2.6+dfsg-1/drivers/st/uart/stm32_uart.c 2.7.0+dfsg-2/drivers/st/uart/stm32_uart.c --- 2.6+dfsg-1/drivers/st/uart/stm32_uart.c 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/st/uart/stm32_uart.c 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/* UART time-out value */ +#define STM32_UART_TIMEOUT_US 20000U + +/* Mask to clear ALL the configuration registers */ + +#define STM32_UART_CR1_FIELDS \ + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8 | USART_CR1_FIFOEN) + +#define STM32_UART_CR2_FIELDS \ + (USART_CR2_SLVEN | USART_CR2_DIS_NSS | USART_CR2_ADDM7 | \ + USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \ + USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_STOP | USART_CR2_LINEN | USART_CR2_SWAP | \ + USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \ + USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMODE | \ + USART_CR2_RTOEN | USART_CR2_ADD) + +#define STM32_UART_CR3_FIELDS \ + (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | \ + USART_CR3_HDSEL | USART_CR3_NACK | USART_CR3_SCEN | \ + USART_CR3_DMAR | USART_CR3_DMAT | USART_CR3_RTSE | \ + USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \ + USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | \ + USART_CR3_DEP | USART_CR3_SCARCNT | USART_CR3_WUS | \ + USART_CR3_WUFIE | USART_CR3_TXFTIE | USART_CR3_TCBGTIE | \ + USART_CR3_RXFTCFG | USART_CR3_RXFTIE | USART_CR3_TXFTCFG) + +#define STM32_UART_ISR_ERRORS \ + (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE) + +static const uint16_t presc_table[STM32_UART_PRESCALER_NB] = { + 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U +}; + +/* @brief BRR division operation to set BRR register in 8-bit oversampling + * mode. + * @param clockfreq: UART clock. + * @param baud_rate: Baud rate set by the user. + * @param prescaler: UART prescaler value. + * @retval Division result. + */ +static uint32_t uart_div_sampling8(unsigned long clockfreq, + uint32_t baud_rate, + uint32_t prescaler) +{ + uint32_t scaled_freq = clockfreq / presc_table[prescaler]; + + return ((scaled_freq * 2) + (baud_rate / 2)) / baud_rate; + +} + +/* @brief BRR division operation to set BRR register in 16-bit oversampling + * mode. + * @param clockfreq: UART clock. + * @param baud_rate: Baud rate set by the user. + * @param prescaler: UART prescaler value. + * @retval Division result. + */ +static uint32_t uart_div_sampling16(unsigned long clockfreq, + uint32_t baud_rate, + uint32_t prescaler) +{ + uint32_t scaled_freq = clockfreq / presc_table[prescaler]; + + return (scaled_freq + (baud_rate / 2)) / baud_rate; + +} + +/* + * @brief Return the UART clock frequency. + * @param huart: UART handle. + * @retval Frequency value in Hz. + */ +static unsigned long uart_get_clock_freq(struct stm32_uart_handle_s *huart) +{ + return fdt_get_uart_clock_freq((uintptr_t)huart->base); +} + +/* + * @brief Configure the UART peripheral. + * @param huart: UART handle. + * @retval UART status. + */ +static int uart_set_config(struct stm32_uart_handle_s *huart, + const struct stm32_uart_init_s *init) +{ + uint32_t tmpreg; + unsigned long clockfreq; + uint32_t brrtemp; + + /* + * ---------------------- USART CR1 Configuration -------------------- + * Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART word length, parity, mode and oversampling: + * - set the M bits according to init->word_length value, + * - set PCE and PS bits according to init->parity value, + * - set TE and RE bits according to init->mode value, + * - set OVER8 bit according to init->over_sampling value. + */ + tmpreg = init->word_length | + init->parity | + init->mode | + init->over_sampling | + init->fifo_mode; + mmio_clrsetbits_32(huart->base + USART_CR1, STM32_UART_CR1_FIELDS, tmpreg); + + /* + * --------------------- USART CR2 Configuration --------------------- + * Configure the UART Stop Bits: Set STOP[13:12] bits according + * to init->stop_bits value. + */ + mmio_clrsetbits_32(huart->base + USART_CR2, STM32_UART_CR2_FIELDS, + init->stop_bits); + + /* + * --------------------- USART CR3 Configuration --------------------- + * Configure: + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to init->hw_flow_control value, + * - one-bit sampling method versus three samples' majority rule + * according to init->one_bit_sampling (not applicable to + * LPUART), + * - set TXFTCFG bit according to init->tx_fifo_threshold value, + * - set RXFTCFG bit according to init->rx_fifo_threshold value. + */ + tmpreg = init->hw_flow_control | init->one_bit_sampling; + + if (init->fifo_mode == USART_CR1_FIFOEN) { + tmpreg |= init->tx_fifo_threshold | + init->rx_fifo_threshold; + } + + mmio_clrsetbits_32(huart->base + USART_CR3, STM32_UART_CR3_FIELDS, tmpreg); + + /* + * --------------------- USART PRESC Configuration ------------------- + * Configure UART Clock Prescaler : set PRESCALER according to + * init->prescaler value. + */ + assert(init->prescaler < STM32_UART_PRESCALER_NB); + mmio_clrsetbits_32(huart->base + USART_PRESC, USART_PRESC_PRESCALER, + init->prescaler); + + /*---------------------- USART BRR configuration --------------------*/ + clockfreq = uart_get_clock_freq(huart); + if (clockfreq == 0UL) { + return -ENODEV; + } + + if (init->over_sampling == STM32_UART_OVERSAMPLING_8) { + uint32_t usartdiv = uart_div_sampling8(clockfreq, + init->baud_rate, + init->prescaler); + + brrtemp = (usartdiv & USART_BRR_DIV_MANTISSA) | + ((usartdiv & USART_BRR_DIV_FRACTION) >> 1); + } else { + brrtemp = uart_div_sampling16(clockfreq, + init->baud_rate, + init->prescaler) & + (USART_BRR_DIV_FRACTION | USART_BRR_DIV_MANTISSA); + } + mmio_write_32(huart->base + USART_BRR, brrtemp); + + return 0; +} + +/* + * @brief Handle UART communication timeout. + * @param huart: UART handle. + * @param flag: Specifies the UART flag to check. + * @retval UART status. + */ +static int stm32_uart_wait_flag(struct stm32_uart_handle_s *huart, uint32_t flag) +{ + uint64_t timeout_ref = timeout_init_us(STM32_UART_TIMEOUT_US); + + while ((mmio_read_32(huart->base + USART_ISR) & flag) == 0U) { + if (timeout_elapsed(timeout_ref)) { + return -ETIMEDOUT; + } + } + + return 0; +} + +/* + * @brief Check the UART idle State. + * @param huart: UART handle. + * @retval UART status. + */ +static int stm32_uart_check_idle(struct stm32_uart_handle_s *huart) +{ + int ret; + + /* Check if the transmitter is enabled */ + if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_TE) == USART_CR1_TE) { + ret = stm32_uart_wait_flag(huart, USART_ISR_TEACK); + if (ret != 0) { + return ret; + } + } + + /* Check if the receiver is enabled */ + if ((mmio_read_32(huart->base + USART_CR1) & USART_CR1_RE) == USART_CR1_RE) { + ret = stm32_uart_wait_flag(huart, USART_ISR_REACK); + if (ret != 0) { + return ret; + } + } + + return 0; +} + +/* + * @brief Compute RDR register mask depending on word length. + * @param huart: UART handle. + * @retval Mask value. + */ +static unsigned int stm32_uart_rdr_mask(const struct stm32_uart_init_s *init) +{ + unsigned int mask = 0U; + + switch (init->word_length) { + case STM32_UART_WORDLENGTH_9B: + mask = GENMASK(8, 0); + break; + case STM32_UART_WORDLENGTH_8B: + mask = GENMASK(7, 0); + break; + case STM32_UART_WORDLENGTH_7B: + mask = GENMASK(6, 0); + break; + default: + break; /* not reached */ + } + + if (init->parity != STM32_UART_PARITY_NONE) { + mask >>= 1; + } + + return mask; +} + +/* + * @brief Check interrupt and status errors. + * @retval True if error detected, false otherwise. + */ +static bool stm32_uart_error_detected(struct stm32_uart_handle_s *huart) +{ + return (mmio_read_32(huart->base + USART_ISR) & STM32_UART_ISR_ERRORS) != 0U; +} + +/* + * @brief Clear status errors. + */ +static void stm32_uart_error_clear(struct stm32_uart_handle_s *huart) +{ + mmio_write_32(huart->base + USART_ICR, STM32_UART_ISR_ERRORS); +} + +/* + * @brief Stop the UART. + * @param base: UART base address. + */ +void stm32_uart_stop(uintptr_t base) +{ + mmio_clrbits_32(base + USART_CR1, USART_CR1_UE); +} + +/* + * @brief Initialize UART. + * @param huart: UART handle. + * @param base_addr: base address of UART. + * @param init: UART initialization parameter. + * @retval UART status. + */ + +int stm32_uart_init(struct stm32_uart_handle_s *huart, + uintptr_t base_addr, + const struct stm32_uart_init_s *init) +{ + int ret; + + if (huart == NULL || init == NULL || base_addr == 0U) { + return -EINVAL; + } + + huart->base = base_addr; + + /* Disable the peripheral */ + stm32_uart_stop(huart->base); + + /* Computation of UART mask to apply to RDR register */ + huart->rdr_mask = stm32_uart_rdr_mask(init); + + /* Init the peripheral */ + ret = uart_set_config(huart, init); + if (ret != 0) { + return ret; + } + + /* Enable the peripheral */ + mmio_setbits_32(huart->base + USART_CR1, USART_CR1_UE); + + /* TEACK and/or REACK to check */ + return stm32_uart_check_idle(huart); +} + +/* + * @brief Transmit one data in no blocking mode. + * @param huart: UART handle. + * @param c: data to sent. + * @retval UART status. + */ +int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c) +{ + int ret; + + if (huart == NULL) { + return -EINVAL; + } + + ret = stm32_uart_wait_flag(huart, USART_ISR_TXE); + if (ret != 0) { + return ret; + } + + mmio_write_32(huart->base + USART_TDR, c); + if (stm32_uart_error_detected(huart)) { + stm32_uart_error_clear(huart); + return -EFAULT; + } + + return 0; +} + +/* + * @brief Flush TX Transmit fifo + * @param huart: UART handle. + * @retval UART status. + */ +int stm32_uart_flush(struct stm32_uart_handle_s *huart) +{ + int ret; + + if (huart == NULL) { + return -EINVAL; + } + + ret = stm32_uart_wait_flag(huart, USART_ISR_TXE); + if (ret != 0) { + return ret; + } + + return stm32_uart_wait_flag(huart, USART_ISR_TC); +} + +/* + * @brief Receive a data in no blocking mode. + * @retval value if >0 or UART status. + */ +int stm32_uart_getc(struct stm32_uart_handle_s *huart) +{ + uint32_t data; + + if (huart == NULL) { + return -EINVAL; + } + + /* Check if data is available */ + if ((mmio_read_32(huart->base + USART_ISR) & USART_ISR_RXNE) == 0U) { + return -EAGAIN; + } + + data = mmio_read_32(huart->base + USART_RDR) & huart->rdr_mask; + + if (stm32_uart_error_detected(huart)) { + stm32_uart_error_clear(huart); + return -EFAULT; + } + + return (int)data; +} diff -pruN 2.6+dfsg-1/drivers/ufs/ufs.c 2.7.0+dfsg-2/drivers/ufs/ufs.c --- 2.6+dfsg-1/drivers/ufs/ufs.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/ufs/ufs.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -146,11 +146,43 @@ static int ufshc_hce_enable(uintptr_t ba return 0; } +static int ufshc_hce_disable(uintptr_t base) +{ + unsigned int data; + int timeout; + + /* Disable Host Controller */ + mmio_write_32(base + HCE, HCE_DISABLE); + timeout = HCE_DISABLE_TIMEOUT_US; + do { + data = mmio_read_32(base + HCE); + if ((data & HCE_ENABLE) == HCE_DISABLE) { + break; + } + udelay(1); + } while (--timeout > 0); + + if (timeout <= 0) { + return -ETIMEDOUT; + } + + return 0; +} + + static int ufshc_reset(uintptr_t base) { unsigned int data; int retries, result; + /* disable controller if enabled */ + if (mmio_read_32(base + HCE) & HCE_ENABLE) { + result = ufshc_hce_disable(base); + if (result != 0) { + return -EIO; + } + } + for (retries = 0; retries < HCE_ENABLE_OUTER_RETRIES; ++retries) { result = ufshc_hce_enable(base); if (result == 0) { @@ -356,7 +388,6 @@ static int ufs_prepare_cmd(utp_utrd_t *u hd->prdto = (utrd->size_upiu + utrd->size_resp_upiu) >> 2; } - flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); return 0; } @@ -409,13 +440,12 @@ static int ufs_prepare_query(utp_utrd_t break; case QUERY_WRITE_ATTR: query_upiu->query_func = QUERY_FUNC_STD_WRITE; - memcpy((void *)&query_upiu->ts.attr.value, (void *)buf, length); + query_upiu->ts.attr.value = htobe32(*((uint32_t *)buf)); break; default: assert(0); break; } - flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); return 0; } @@ -439,7 +469,6 @@ static void ufs_prepare_nop_out(utp_utrd nop_out->trans_type = 0; nop_out->task_tag = utrd->task_tag; - flush_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); flush_dcache_range((uintptr_t)utrd->header, UFS_DESC_SIZE); } @@ -473,8 +502,6 @@ static int ufs_check_resp(utp_utrd_t *ut hd = (utrd_header_t *)utrd->header; resp = (resp_upiu_t *)utrd->resp_upiu; - inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); - inv_dcache_range((uintptr_t)utrd, sizeof(utp_utrd_t)); do { data = mmio_read_32(ufs_params.reg_base + IS); if ((data & ~(UFS_INT_UCCS | UFS_INT_UTRCS)) != 0) @@ -484,6 +511,12 @@ static int ufs_check_resp(utp_utrd_t *ut data = mmio_read_32(ufs_params.reg_base + UTRLDBR); assert((data & (1 << slot)) == 0); + /* + * Invalidate the header after DMA read operation has + * completed to avoid cpu referring to the prefetched + * data brought in before DMA completion. + */ + inv_dcache_range((uintptr_t)hd, UFS_DESC_SIZE); assert(hd->ocs == OCS_SUCCESS); assert((resp->trans_type & TRANS_TYPE_CODE_MASK) == trans_type); (void)resp; @@ -491,6 +524,21 @@ static int ufs_check_resp(utp_utrd_t *ut return 0; } +static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf, + size_t length) +{ + int result; + + get_utrd(utrd); + + result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length); + assert(result == 0); + ufs_send_request(utrd->task_tag); + result = ufs_check_resp(utrd, RESPONSE_UPIU); + assert(result == 0); + (void)result; +} + #ifdef UFS_RESP_DEBUG static void dump_upiu(utp_utrd_t *utrd) { @@ -541,14 +589,7 @@ static void ufs_verify_init(void) static void ufs_verify_ready(void) { utp_utrd_t utrd; - int result; - - get_utrd(&utrd); - ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); - ufs_send_request(utrd.task_tag); - result = ufs_check_resp(&utrd, RESPONSE_UPIU); - assert(result == 0); - (void)result; + ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0); } static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, @@ -585,12 +626,14 @@ static void ufs_query(uint8_t op, uint8_ case QUERY_READ_FLAG: *(uint32_t *)buf = (uint32_t)resp->ts.flag.value; break; - case QUERY_READ_ATTR: case QUERY_READ_DESC: memcpy((void *)buf, (void *)(utrd.resp_upiu + sizeof(query_resp_upiu_t)), size); break; + case QUERY_READ_ATTR: + *(uint32_t *)buf = htobe32(resp->ts.attr.value); + break; default: /* Do nothing in default case */ break; @@ -649,7 +692,6 @@ static void ufs_read_capacity(int lun, u sense_data_t *sense; unsigned char data[CACHE_WRITEBACK_GRANULE << 1]; uintptr_t buf; - int result; int retry; assert((ufs_params.reg_base != 0) && @@ -661,15 +703,9 @@ static void ufs_read_capacity(int lun, u buf = (uintptr_t)data; buf = (buf + CACHE_WRITEBACK_GRANULE - 1) & ~(CACHE_WRITEBACK_GRANULE - 1); - memset((void *)buf, 0, CACHE_WRITEBACK_GRANULE); - flush_dcache_range(buf, CACHE_WRITEBACK_GRANULE); do { - get_utrd(&utrd); - ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, - buf, READ_CAPACITY_LENGTH); - ufs_send_request(utrd.task_tag); - result = ufs_check_resp(&utrd, RESPONSE_UPIU); - assert(result == 0); + ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0, + buf, READ_CAPACITY_LENGTH); #ifdef UFS_RESP_DEBUG dump_upiu(&utrd); #endif @@ -690,30 +726,27 @@ static void ufs_read_capacity(int lun, u /* logical block length in bytes */ *size = be32toh(*(unsigned int *)(buf + 4)); } while (retry); - (void)result; } size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size) { utp_utrd_t utrd; resp_upiu_t *resp; - int result; assert((ufs_params.reg_base != 0) && (ufs_params.desc_base != 0) && (ufs_params.desc_size >= UFS_DESC_SIZE)); - memset((void *)buf, 0, size); - get_utrd(&utrd); - ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); - ufs_send_request(utrd.task_tag); - result = ufs_check_resp(&utrd, RESPONSE_UPIU); - assert(result == 0); + ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size); #ifdef UFS_RESP_DEBUG dump_upiu(&utrd); #endif + /* + * Invalidate prefetched cache contents before cpu + * accesses the buf. + */ + inv_dcache_range(buf, size); resp = (resp_upiu_t *)utrd.resp_upiu; - (void)result; return size - resp->res_trans_cnt; } @@ -721,41 +754,54 @@ size_t ufs_write_blocks(int lun, int lba { utp_utrd_t utrd; resp_upiu_t *resp; - int result; assert((ufs_params.reg_base != 0) && (ufs_params.desc_base != 0) && (ufs_params.desc_size >= UFS_DESC_SIZE)); - memset((void *)buf, 0, size); - get_utrd(&utrd); - ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); - ufs_send_request(utrd.task_tag); - result = ufs_check_resp(&utrd, RESPONSE_UPIU); - assert(result == 0); + ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size); #ifdef UFS_RESP_DEBUG dump_upiu(&utrd); #endif resp = (resp_upiu_t *)utrd.resp_upiu; - (void)result; return size - resp->res_trans_cnt; } +static int ufs_set_fdevice_init(void) +{ + unsigned int result; + int timeout; + + ufs_set_flag(FLAG_DEVICE_INIT); + + timeout = FDEVICEINIT_TIMEOUT_MS; + do { + result = ufs_read_flag(FLAG_DEVICE_INIT); + if (!result) { + break; + } + mdelay(5); + timeout -= 5; + } while (timeout > 0); + + if (result != 0U) { + return -ETIMEDOUT; + } + + return 0; +} + static void ufs_enum(void) { unsigned int blk_num, blk_size; - int i; - - /* 0 means 1 slot */ - nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; - if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) - nutrs = ufs_params.desc_size / UFS_DESC_SIZE; + int i, result; ufs_verify_init(); ufs_verify_ready(); - ufs_set_flag(FLAG_DEVICE_INIT); - mdelay(200); + result = ufs_set_fdevice_init(); + assert(result == 0); + /* dump available LUNs */ for (i = 0; i < UFS_MAX_LUNS; i++) { ufs_read_capacity(i, &blk_num, &blk_size); @@ -764,6 +810,8 @@ static void ufs_enum(void) i, blk_num, blk_size); } } + + (void)result; } static void ufs_get_device_info(struct ufs_dev_desc *card_data) @@ -795,6 +843,13 @@ int ufs_init(const ufs_ops_t *ops, ufs_p memcpy(&ufs_params, params, sizeof(ufs_params_t)); + /* 0 means 1 slot */ + nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1; + if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) { + nutrs = ufs_params.desc_size / UFS_DESC_SIZE; + } + + if (ufs_params.flags & UFS_FLAGS_SKIPINIT) { result = ufshc_dme_get(0x1571, 0, &data); assert(result == 0); diff -pruN 2.6+dfsg-1/drivers/usb/usb_device.c 2.7.0+dfsg-2/drivers/usb/usb_device.c --- 2.6+dfsg-1/drivers/usb/usb_device.c 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/drivers/usb/usb_device.c 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -362,7 +362,7 @@ static enum usb_status usb_core_setup_st case USB_REQ_RECIPIENT_ENDPOINT: default: - ERROR("receive unsupported request %i", + ERROR("receive unsupported request %u", pdev->request.bm_request & USB_REQ_RECIPIENT_MASK); usb_core_set_stall(pdev, pdev->request.bm_request & USB_REQ_DIRECTION); return USBD_FAIL; diff -pruN 2.6+dfsg-1/fdts/morello.dtsi 2.7.0+dfsg-2/fdts/morello.dtsi --- 2.6+dfsg-1/fdts/morello.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/morello.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,17 +58,17 @@ "mhu_hpri_rx"; #mbox-cells = <2>; mbox-name = "ARM-MHU"; - clocks = <&soc_refclk100mhz>; + clocks = <&soc_refclk50mhz>; clock-names = "apb_pclk"; }; sram: sram@45200000 { compatible = "mmio-sram"; - reg = <0x0 0x45200000 0x0 0x8000>; + reg = <0x0 0x06000000 0x0 0x8000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0x45200000 0x8000>; + ranges = <0 0x0 0x06000000 0x8000>; cpu_scp_hpri0: scp-shmem@0 { compatible = "arm,scmi-shmem"; @@ -81,10 +81,10 @@ }; }; - soc_refclk100mhz: refclk100mhz { + soc_refclk50mhz: refclk50mhz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <50000000>; clock-output-names = "apb_pclk"; }; @@ -99,7 +99,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x2a400000 0x0 0x1000>; interrupts = ; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clocks = <&soc_uartclk>, <&soc_refclk50mhz>; clock-names = "uartclk", "apb_pclk"; status = "okay"; }; diff -pruN 2.6+dfsg-1/fdts/morello-soc.dts 2.7.0+dfsg-2/fdts/morello-soc.dts --- 2.6+dfsg-1/fdts/morello-soc.dts 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/morello-soc.dts 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + + chosen { + stdout-path = "soc_uart0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0 0xff000000 0 0x01000000>; + no-map; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu0@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + cpu1@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 0>; + }; + cpu2@10000 { + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + cpu3@10100 { + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + clocks = <&scmi_dvfs 1>; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7F000000>; + }; + + memory@8080000000 { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x4f400000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x28 0xC0000000 0 0x10000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + status = "okay"; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0 0x4f000000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + reg = <0x4F 0xC0000000 0 0x10000000>; + bus-range = <0 255>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + status = "okay"; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0 0x2ce00000 0 0x40000>; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + #iommu-cells = <1>; + }; + + dp0: display@2cc00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,mali-d32"; + reg = <0 0x2cc00000 0 0x20000>; + interrupts = <0 69 4>; + interrupt-names = "DPU"; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&scmi_clk 1>; + clock-names = "pxclk"; + pl_id = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + }; + + i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <500>; + interrupts = ; + clocks = <&dpu_aclk>; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dpu_aclk: dpu_aclk { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; +}; + +&gic { + reg = <0x0 0x30000000 0 0x10000>, /* GICD */ + <0x0 0x300c0000 0 0x80000>; /* GICR */ + interrupts = ; + + its1: its@30040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30040000 0x0 0x20000>; + }; + + its2: its@30060000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30060000 0x0 0x20000>; + }; + + its_ccix: its@30080000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x30080000 0x0 0x20000>; + }; + + its_pcie: its@300a0000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0x300a0000 0x0 0x20000>; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp131.dtsi 2.7.0+dfsg-2/fdts/stm32mp131.dtsi --- 2.6+dfsg-1/fdts/stm32mp131.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp131.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&rcc CK_MPU>; + clock-names = "cpu"; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + }; + }; + + clocks { + clk_csi: clk-csi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts = ; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts = ; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts = ; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + status = "disabled"; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts = ; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts = ; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + status = "disabled"; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts = ; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts = ; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts = ; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = ; + secure-interrupts = ; + secure-interrupt-names = "wakeup"; + }; + + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + + hash: hash@54003000 { + compatible = "st,stm32mp13-hash"; + reg = <0x54003000 0x400>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + status = "disabled"; + }; + + rng: rng@54004000 { + compatible = "st,stm32mp13-rng"; + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + }; + + usbh_ohci: usbh-ohci@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usbh-ehci@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + ddr: ddr@5a003000{ + compatible = "st,stm32mp13-ddr"; + reg = <0x5a003000 0x550>, <0x5a004000 0x234>; + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + clock-names = "axidcg", + "ddrc1", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = ; + clocks = <&rcc IWDG1>, <&rcc CK_LSI>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp15-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + cfg0_otp: cfg0_otp@0 { + reg = <0x0 0x2>; + }; + part_number_otp: part_number_otp@4 { + reg = <0x4 0x2>; + }; + monotonic_otp: monotonic_otp@10 { + reg = <0x10 0x4>; + }; + nand_otp: cfg9_otp@24 { + reg = <0x24 0x4>; + }; + nand2_otp: cfg10_otp@28 { + reg = <0x28 0x4>; + }; + uid_otp: uid_otp@34 { + reg = <0x34 0xc>; + }; + hw2_otp: hw2_otp@48 { + reg = <0x48 0x4>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + pkh_otp: pkh_otp@60 { + reg = <0x60 0x20>; + }; + mac_addr: mac_addr@e4 { + reg = <0xe4 0xc>; + st,non-secure-otp; + }; + }; + + tamp: tamp@5c00a000 { + reg = <0x5c00a000 0x400>; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pin-controller@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; + ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc GPIOA>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc GPIOB>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc GPIOC>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&rcc GPIOD>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&rcc GPIOE>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&rcc GPIOF>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&rcc GPIOG>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&rcc GPIOH>; + st,bank-name = "GPIOH"; + ngpios = <15>; + gpio-ranges = <&pinctrl 0 112 15>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&rcc GPIOI>; + st,bank-name = "GPIOI"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 128 8>; + }; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp133.dtsi 2.7.0+dfsg-2/fdts/stm32mp133.dtsi --- 2.6+dfsg-1/fdts/stm32mp133.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp133.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp131.dtsi" + +/ { + soc { + m_can1: can@4400e000 { + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + status = "disabled"; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp135.dtsi 2.7.0+dfsg-2/fdts/stm32mp135.dtsi --- 2.6+dfsg-1/fdts/stm32mp135.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp135.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp133.dtsi" + +/ { + soc { + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp135f-dk.dts 2.7.0+dfsg-2/fdts/stm32mp135f-dk.dts --- 2.6+dfsg-1/fdts/stm32mp135f-dk.dts 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp135f-dk.dts 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + v3v3_ao: v3v3_ao { + compatible = "regulator-fixed"; + regulator-name = "v3v3_ao"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&bsec { + board_id: board_id@f0 { + reg = <0xf0 0x4>; + st,non-secure-otp; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&hash { + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + status = "disabled"; + secure-status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + + status = "disabled"; + secure-status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; + ldo1-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + vref_ddr-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&v3v3_ao>; + + vddcpu: buck1 { + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-over-current-protection; + }; + + vddcore: buck4 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + v1v8_periph: ldo6 { + regulator-name = "v1v8_periph"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + }; + + v3v3_sw: pwr_sw2 { + regulator-name = "v3v3_sw"; + regulator-active-discharge = <1>; + regulator-always-on; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pka { + secure-status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_SDMMC1_PLL4P + CLK_SDMMC2_PLL4P + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_I2C4_HSI + CLK_USBO_USBPHY + CLK_I2C12_HSI + CLK_UART2_HSI + CLK_UART4_HSI + CLK_SAES_AXI + >; + + st,clkdiv = < + DIV(DIV_AXI, 0) + DIV(DIV_MLAHB, 0) + DIV(DIV_APB1, 1) + DIV(DIV_APB2, 1) + DIV(DIV_APB3, 1) + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) + DIV(DIV_APB6, 1) + DIV(DIV_RTC, 0) + >; + + st,pll_vco { + pll1_vco_1300Mhz: pll1-vco-1300Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 2 80 >; + frac = < 0x800 >; + }; + + pll2_vco_1066Mhz: pll2-vco-1066Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 2 65 >; + frac = < 0x1400 >; + }; + + pll3_vco_417_8Mhz: pll2-vco-417_8Mhz { + src = < CLK_PLL3_HSE >; + divmn = < 1 33 >; + frac = < 0x1a04 >; + }; + + pll4_vco_600Mhz: pll2-vco-600Mhz { + src = < CLK_PLL4_HSE >; + divmn = < 1 49 >; + }; + }; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1:st,pll@0 { + compatible = "st,stm32mp1-pll"; + reg = <0>; + + st,pll = < &pll1_cfg1 >; + + pll1_cfg1: pll1_cfg1 { + st,pll_vco = < &pll1_vco_1300Mhz >; + st,pll_div_pqr = < 0 1 1 >; + }; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2:st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + + st,pll = < &pll2_cfg1 >; + + pll2_cfg1: pll2_cfg1 { + st,pll_vco = < &pll2_vco_1066Mhz >; + st,pll_div_pqr = < 1 1 0 >; + }; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */ + pll3:st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + + st,pll = < &pll3_cfg1 >; + + pll3_cfg1: pll3_cfg1 { + st,pll_vco = < &pll3_vco_417_8Mhz >; + st,pll_div_pqr = < 1 16 1 >; + }; + }; + + /* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */ + pll4:st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + + st,pll = < &pll4_cfg1 >; + + pll4_cfg1: pll4_cfg1 { + st,pll_vco = < &pll4_vco_600Mhz >; + st,pll_div_pqr = < 11 59 5 >; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&saes { + secure-status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default"; + pinctrl-0 = <&usart1_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp135f-dk-fw-config.dts 2.7.0+dfsg-2/fdts/stm32mp135f-dk-fw-config.dts --- 2.6+dfsg-1/fdts/stm32mp135f-dk-fw-config.dts 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp135f-dk-fw-config.dts 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + */ + +#define DDR_SIZE 0x20000000 /* 512MB */ +#include "stm32mp13-fw-config.dtsi" diff -pruN 2.6+dfsg-1/fdts/stm32mp13-bl2.dtsi 2.7.0+dfsg-2/fdts/stm32mp13-bl2.dtsi --- 2.6+dfsg-1/fdts/stm32mp13-bl2.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13-bl2.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ + +/ { + aliases { +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-property/ mmc0; + /delete-property/ mmc1; +#endif + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + cpus { + cpu@0 { + /delete-property/ operating-points-v2; + }; + }; + + /delete-node/ cpu0-opp-table; + /delete-node/ psci; + + soc { + /delete-node/ sram@30000000; + /delete-node/ timer@40000000; + /delete-node/ timer@40001000; + /delete-node/ timer@40002000; + /delete-node/ timer@40003000; + /delete-node/ timer@40004000; + /delete-node/ timer@40005000; + /delete-node/ timer@40009000; + /delete-node/ spi@4000b000; + /delete-node/ audio-controller@4000b000; + /delete-node/ spi@4000c000; + /delete-node/ audio-controller@4000c000; + /delete-node/ audio-controller@4000d000; + /delete-node/ i2c@40012000; + /delete-node/ i2c@40013000; + /delete-node/ timer@44000000; + /delete-node/ timer@44001000; + /delete-node/ spi@44004000; + /delete-node/ audio-controller@44004000; + /delete-node/ sai@4400a000; + /delete-node/ sai@4400b000; + /delete-node/ dfsdm@4400d000; + /delete-node/ can@4400e000; + /delete-node/ can@4400f000; + /delete-node/ dma-controller@48000000; + /delete-node/ dma-controller@48001000; + /delete-node/ dma-router@48002000; + /delete-node/ adc@48003000; + /delete-node/ adc@48004000; + /delete-node/ dma@48005000; + /delete-node/ dma-router@48006000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usb-otg@49000000; +#endif + /delete-node/ spi@4c002000; + /delete-node/ spi@4c003000; + /delete-node/ timer@4c007000; + /delete-node/ timer@4c008000; + /delete-node/ timer@4c009000; + /delete-node/ timer@4c00a000; + /delete-node/ timer@4c00b000; + /delete-node/ timer@4c00c000; + /delete-node/ timer@50021000; + /delete-node/ timer@50022000; + /delete-node/ timer@50023000; + /delete-node/ timer@50024000; + /delete-node/ vrefbuf@50025000; + /delete-node/ thermal@50028000; + /delete-node/ hdp@5002a000; + /delete-node/ dma-controller@58000000; +#if !STM32MP_RAW_NAND + /delete-node/ memory-controller@58002000; +#endif +#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR + /delete-node/ spi@58003000; +#endif +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ mmc@58005000; + /delete-node/ mmc@58007000; +#endif + /delete-node/ crc@58009000; + /delete-node/ stmmac-axi-config; + /delete-node/ eth1@5800a000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbh-ohci@5800c000; + /delete-node/ usbh-ehci@5800d000; +#endif + /delete-node/ eth2@5800e000; + /delete-node/ dcmipp@5a000000; + /delete-node/ display-controller@5a001000; +#if !STM32MP_USB_PROGRAMMER + /delete-node/ usbphyc@5a006000; +#endif + /delete-node/ perf@5a007000; + /delete-node/ rtc@5c004000; + /delete-node/ tamp@5c00a000; + /delete-node/ stgen@5c008000; + + pin-controller@50002000 { +#if !STM32MP_EMMC && !STM32MP_SDMMC + /delete-node/ sdmmc1-b4-0; + /delete-node/ sdmmc2-b4-0; +#endif + }; + }; + + /* + * UUID's here are UUID RFC 4122 compliant meaning fieds are stored in + * network order (big endian) + */ + + st-io_policies { + fip-handles { + compatible = "st,io-fip-handle"; + fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e"; + bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38"; + bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288"; + bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9"; + bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; + hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; + tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; + nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi 2.7.0+dfsg-2/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi --- 2.6+dfsg-1/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * STM32MP135C DISCO BOARD configuration + * 1x DDR3L 4Gb, 16-bit, 533MHz. + * Reference used MT41K256M16TW-107 P from Micron + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 1 + * DDR density 4 + * timing mode optimized + * Scheduling/QoS options : type = 6 + * address mapping : RBC + * Tc > + 85C : N + */ +#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff -pruN 2.6+dfsg-1/fdts/stm32mp13-ddr.dtsi 2.7.0+dfsg-2/fdts/stm32mp13-ddr.dtsi --- 2.6+dfsg-1/fdts/stm32mp13-ddr.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13-ddr.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +&ddr { + st,mem-name = DDR_MEM_NAME; + st,mem-speed = ; + st,mem-size = ; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + >; + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; +}; + +#undef DDR_MEM_NAME +#undef DDR_MEM_SPEED +#undef DDR_MEM_SIZE +#undef DDR_MSTR +#undef DDR_MRCTRL0 +#undef DDR_MRCTRL1 +#undef DDR_DERATEEN +#undef DDR_DERATEINT +#undef DDR_PWRCTL +#undef DDR_PWRTMG +#undef DDR_HWLPCTL +#undef DDR_RFSHCTL0 +#undef DDR_RFSHCTL3 +#undef DDR_RFSHTMG +#undef DDR_CRCPARCTL0 +#undef DDR_DRAMTMG0 +#undef DDR_DRAMTMG1 +#undef DDR_DRAMTMG2 +#undef DDR_DRAMTMG3 +#undef DDR_DRAMTMG4 +#undef DDR_DRAMTMG5 +#undef DDR_DRAMTMG6 +#undef DDR_DRAMTMG7 +#undef DDR_DRAMTMG8 +#undef DDR_DRAMTMG14 +#undef DDR_ZQCTL0 +#undef DDR_DFITMG0 +#undef DDR_DFITMG1 +#undef DDR_DFILPCFG0 +#undef DDR_DFIUPD0 +#undef DDR_DFIUPD1 +#undef DDR_DFIUPD2 +#undef DDR_DFIPHYMSTR +#undef DDR_ADDRMAP1 +#undef DDR_ADDRMAP2 +#undef DDR_ADDRMAP3 +#undef DDR_ADDRMAP4 +#undef DDR_ADDRMAP5 +#undef DDR_ADDRMAP6 +#undef DDR_ADDRMAP9 +#undef DDR_ADDRMAP10 +#undef DDR_ADDRMAP11 +#undef DDR_ODTCFG +#undef DDR_ODTMAP +#undef DDR_SCHED +#undef DDR_SCHED1 +#undef DDR_PERFHPR1 +#undef DDR_PERFLPR1 +#undef DDR_PERFWR1 +#undef DDR_DBG0 +#undef DDR_DBG1 +#undef DDR_DBGCMD +#undef DDR_POISONCFG +#undef DDR_PCCFG +#undef DDR_PCFGR_0 +#undef DDR_PCFGW_0 +#undef DDR_PCFGQOS0_0 +#undef DDR_PCFGQOS1_0 +#undef DDR_PCFGWQOS0_0 +#undef DDR_PCFGWQOS1_0 +#undef DDR_PGCR +#undef DDR_PTR0 +#undef DDR_PTR1 +#undef DDR_PTR2 +#undef DDR_ACIOCR +#undef DDR_DXCCR +#undef DDR_DSGCR +#undef DDR_DCR +#undef DDR_DTPR0 +#undef DDR_DTPR1 +#undef DDR_DTPR2 +#undef DDR_MR0 +#undef DDR_MR1 +#undef DDR_MR2 +#undef DDR_MR3 +#undef DDR_ODTCR +#undef DDR_ZQ0CR1 +#undef DDR_DX0GCR +#undef DDR_DX1GCR diff -pruN 2.6+dfsg-1/fdts/stm32mp13-fw-config.dtsi 2.7.0+dfsg-2/fdts/stm32mp13-fw-config.dtsi --- 2.6+dfsg-1/fdts/stm32mp13-fw-config.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13-fw-config.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + */ + +#include +#include + +#include + +#ifndef DDR_SIZE +#error "DDR_SIZE is not defined" +#endif + +#define DDR_NS_BASE STM32MP_DDR_BASE +#define DDR_SEC_SIZE 0x02000000 +#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) +#define DDR_NS_SIZE (DDR_SEC_BASE - DDR_NS_BASE) + +/dts-v1/; + +/ { + dtb-registry { + compatible = "fconf,dyn_cfg-dtb_registry"; + + hw-config { + load-address = <0x0 STM32MP_HW_CONFIG_BASE>; + max-size = ; + id = ; + }; + + nt_fw { + load-address = <0x0 STM32MP_BL33_BASE>; + max-size = ; + id = ; + }; + + tos_fw { + load-address = <0x0 DDR_SEC_BASE>; + max-size = ; + id = ; + }; + }; + + st-mem-firewall { + compatible = "st,mem-firewall"; + memory-ranges = < + DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR + DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp13-pinctrl.dtsi 2.7.0+dfsg-2/fdts/stm32mp13-pinctrl.dtsi --- 2.6+dfsg-1/fdts/stm32mp13-pinctrl.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13-pinctrl.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue + */ +#include + +&pinctrl { + i2c4_pins_a: i2c4-0 { + pins { + pinmux = , /* I2C4_SCL */ + ; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp13xa.dtsi 2.7.0+dfsg-2/fdts/stm32mp13xa.dtsi --- 2.6+dfsg-1/fdts/stm32mp13xa.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13xa.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ diff -pruN 2.6+dfsg-1/fdts/stm32mp13xc.dtsi 2.7.0+dfsg-2/fdts/stm32mp13xc.dtsi --- 2.6+dfsg-1/fdts/stm32mp13xc.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13xc.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32mp13xa.dtsi" + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + saes: saes@54005000 { + compatible = "st,stm32-saes"; + reg = <0x54005000 0x400>; + clocks = <&rcc SAES_K>; + resets = <&rcc SAES_R>; + status = "disabled"; + }; + + pka: pka@54006000 { + compatible = "st,stm32-pka64"; + reg = <0x54006000 0x2000>; + clocks = <&rcc PKA>; + resets = <&rcc PKA_R>; + status = "disabled"; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp13xd.dtsi 2.7.0+dfsg-2/fdts/stm32mp13xd.dtsi --- 2.6+dfsg-1/fdts/stm32mp13xd.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13xd.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ diff -pruN 2.6+dfsg-1/fdts/stm32mp13xf.dtsi 2.7.0+dfsg-2/fdts/stm32mp13xf.dtsi --- 2.6+dfsg-1/fdts/stm32mp13xf.dtsi 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp13xf.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp13xd.dtsi" + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + saes: saes@54005000 { + compatible = "st,stm32-saes"; + reg = <0x54005000 0x400>; + clocks = <&rcc SAES_K>; + resets = <&rcc SAES_R>; + status = "disabled"; + }; + + pka: pka@54006000 { + compatible = "st,stm32-pka64"; + reg = <0x54006000 0x2000>; + clocks = <&rcc PKA>; + resets = <&rcc PKA_R>; + status = "disabled"; + }; + }; +}; diff -pruN 2.6+dfsg-1/fdts/stm32mp151.dtsi 2.7.0+dfsg-2/fdts/stm32mp151.dtsi --- 2.6+dfsg-1/fdts/stm32mp151.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp151.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ #include @@ -19,6 +19,8 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; }; }; @@ -457,12 +459,38 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + + cfg0_otp: cfg0_otp@0 { + reg = <0x0 0x1>; + }; + part_number_otp: part_number_otp@4 { + reg = <0x4 0x1>; + }; + monotonic_otp: monotonic_otp@10 { + reg = <0x10 0x4>; + }; + nand_otp: nand_otp@24 { + reg = <0x24 0x4>; + }; + uid_otp: uid_otp@34 { + reg = <0x34 0xc>; + }; + package_otp: package_otp@40 { + reg = <0x40 0x4>; + }; + hw2_otp: hw2_otp@48 { + reg = <0x48 0x4>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + mac_addr: mac_addr@e4 { + reg = <0xe4 0x8>; + st,non-secure-otp; + }; }; etzpc: etzpc@5c007000 { diff -pruN 2.6+dfsg-1/fdts/stm32mp157c-ed1.dts 2.7.0+dfsg-2/fdts/stm32mp157c-ed1.dts --- 2.6+dfsg-1/fdts/stm32mp157c-ed1.dts 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp157c-ed1.dts 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ /dts-v1/; @@ -33,8 +33,7 @@ &bsec { board_id: board_id@ec { reg = <0xec 0x4>; - status = "okay"; - secure-status = "okay"; + st,non-secure-otp; }; }; @@ -135,14 +134,15 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; + st,regulator-sink-source; }; vdd_usb: ldo4 { regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vdd_sd: ldo5 { diff -pruN 2.6+dfsg-1/fdts/stm32mp15-bl2.dtsi 2.7.0+dfsg-2/fdts/stm32mp15-bl2.dtsi --- 2.6+dfsg-1/fdts/stm32mp15-bl2.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp15-bl2.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,12 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2020-2021 - All Rights Reserved + * Copyright (C) STMicroelectronics 2020-2022 - All Rights Reserved */ / { #if !STM32MP_EMMC && !STM32MP_SDMMC aliases { /delete-property/ mmc0; + /delete-property/ mmc1; }; #endif diff -pruN 2.6+dfsg-1/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi 2.7.0+dfsg-2/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi --- 2.6+dfsg-1/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved */ /* @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE80 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE80 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff -pruN 2.6+dfsg-1/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi 2.7.0+dfsg-2/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi --- 2.6+dfsg-1/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (c) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved */ /* @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff -pruN 2.6+dfsg-1/fdts/stm32mp15-ddr.dtsi 2.7.0+dfsg-2/fdts/stm32mp15-ddr.dtsi --- 2.6+dfsg-1/fdts/stm32mp15-ddr.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp15-ddr.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved */ &ddr { @@ -109,19 +109,4 @@ DDR_MR2 DDR_MR3 >; - - st,phy-cal = < - DDR_DX0DLLCR - DDR_DX0DQTR - DDR_DX0DQSTR - DDR_DX1DLLCR - DDR_DX1DQTR - DDR_DX1DQSTR - DDR_DX2DLLCR - DDR_DX2DQTR - DDR_DX2DQSTR - DDR_DX3DLLCR - DDR_DX3DQTR - DDR_DX3DQSTR - >; }; diff -pruN 2.6+dfsg-1/fdts/stm32mp15xx-dkx.dtsi 2.7.0+dfsg-2/fdts/stm32mp15xx-dkx.dtsi --- 2.6+dfsg-1/fdts/stm32mp15xx-dkx.dtsi 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/stm32mp15xx-dkx.dtsi 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ @@ -131,10 +131,9 @@ vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; + st,regulator-sink-source; }; vdd_usb: ldo4 { @@ -160,7 +159,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { diff -pruN 2.6+dfsg-1/fdts/tc.dts 2.7.0+dfsg-2/fdts/tc.dts --- 2.6+dfsg-1/fdts/tc.dts 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/fdts/tc.dts 2022-06-01 15:02:46.000000000 +0000 @@ -17,7 +17,6 @@ }; chosen { - bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0"; stdout-path = "serial0:115200n8"; }; @@ -207,6 +206,13 @@ #size-cells = <2>; ranges; + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + linux,cma-default; + }; + optee@0xfce00000 { reg = <0x00000000 0xfce00000 0 0x00200000>; no-map; @@ -255,6 +261,12 @@ arm,mhuv2-protocols = <0 1>; }; + cmn-pmu { + compatible = "arm,ci-700"; + reg = <0x0 0x50000000 0x0 0x10000000>; + interrupts = <0x0 460 0x4>; + }; + scmi { compatible = "arm,scmi"; mbox-names = "tx", "rx"; @@ -435,6 +447,26 @@ clock-names = "mclk", "apb_pclk"; }; + gpu: gpu@2d000000 { + compatible = "arm,mali-midgard"; + reg = <0x0 0x2d000000 0x0 0x200000>; + interrupts = <0 66 4>, <0 67 4>, <0 65 4>; + interrupt-names = "JOB", "MMU", "GPU"; + clocks = <&soc_refclk100mhz>; + clock-names = "clk_mali"; + operating-points = < + /* KHz uV */ + 50000 820000 + >; + }; + + smmu: smmu@2ce00000 { + #iommu-cells = <1>; + compatible = "arm,smmu-v3"; + reg = <0x0 0x2ce00000 0x0 0x20000>; + status = "okay"; + }; + dp0: display@2cc00000 { #address-cells = <1>; #size-cells = <0>; @@ -444,6 +476,9 @@ interrupt-names = "DPU"; clocks = <&scmi_clk 0>; clock-names = "aclk"; + iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, + <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, + <&smmu 8>, <&smmu 9>; pl0: pipeline@0 { reg = <0>; clocks = <&scmi_clk 1>; @@ -476,4 +511,48 @@ }; }; + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU0>; + }; + + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU1>; + }; + + ete2 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU2>; + }; + + ete3 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU3>; + }; + + ete4 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU4>; + }; + + ete5 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU5>; + }; + + ete6 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU6>; + }; + + ete7 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU7>; + }; + + trbe0 { + compatible = "arm,trace-buffer-extension"; + interrupts = <1 2 4>; + }; }; diff -pruN 2.6+dfsg-1/.gitignore 2.7.0+dfsg-2/.gitignore --- 2.6+dfsg-1/.gitignore 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/.gitignore 2022-06-01 15:02:46.000000000 +0000 @@ -30,8 +30,7 @@ tools/amlogic/doimage tools/stm32image/*.o tools/stm32image/stm32image tools/stm32image/stm32image.exe -tools/sptool/sptool -tools/sptool/sptool.exe +tools/sptool/__pycache__/ # GNU GLOBAL files GPATH diff -pruN 2.6+dfsg-1/include/arch/aarch32/arch.h 2.7.0+dfsg-2/include/arch/aarch32/arch.h --- 2.6+dfsg-1/include/arch/aarch32/arch.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch32/arch.h 2022-06-01 15:02:46.000000000 +0000 @@ -122,6 +122,10 @@ #define ID_MMFR4_CNP_LENGTH U(4) #define ID_MMFR4_CNP_MASK U(0xf) +#define ID_MMFR4_CCIDX_SHIFT U(24) +#define ID_MMFR4_CCIDX_LENGTH U(4) +#define ID_MMFR4_CCIDX_MASK U(0xf) + /* ID_PFR0 definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) @@ -174,7 +178,7 @@ #define SCTLR_AFE_BIT (U(1) << 29) #define SCTLR_TE_BIT (U(1) << 30) #define SCTLR_DSSBS_BIT (U(1) << 31) -#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ +#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) /* SDCR definitions */ @@ -295,7 +299,7 @@ #define CPACR_CP10_SHIFT U(20) #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ (U(0x3) << CPACR_CP10_SHIFT)) -#define CPACR_RESET_VAL U(0x0) +#define CPACR_RESET_VAL U(0x0) /* FPEXC definitions */ #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) @@ -495,13 +499,13 @@ #define CNTP_CTL U(0x2c) /* Physical timer control register bit fields shifts and masks */ -#define CNTP_CTL_ENABLE_SHIFT 0 -#define CNTP_CTL_IMASK_SHIFT 1 -#define CNTP_CTL_ISTATUS_SHIFT 2 - -#define CNTP_CTL_ENABLE_MASK U(1) -#define CNTP_CTL_IMASK_MASK U(1) -#define CNTP_CTL_ISTATUS_MASK U(1) +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 + +#define CNTP_CTL_ENABLE_MASK U(1) +#define CNTP_CTL_IMASK_MASK U(1) +#define CNTP_CTL_ISTATUS_MASK U(1) /* MAIR macros */ #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) @@ -559,6 +563,7 @@ #define CLIDR p15, 1, c0, c0, 1 #define CSSELR p15, 2, c0, c0, 0 #define CCSIDR p15, 1, c0, c0, 0 +#define CCSIDR2 p15, 1, c0, c0, 2 #define HTCR p15, 4, c2, c0, 2 #define HMAIR0 p15, 4, c10, c2, 0 #define ATS1CPR p15, 0, c7, c8, 0 diff -pruN 2.6+dfsg-1/include/arch/aarch32/el3_common_macros.S 2.7.0+dfsg-2/include/arch/aarch32/el3_common_macros.S --- 2.6+dfsg-1/include/arch/aarch32/el3_common_macros.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch32/el3_common_macros.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -398,6 +398,12 @@ ldr r1, =__RW_END__ sub r1, r1, r0 bl inv_dcache_range +#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION + ldr r0, =__BL2_NOLOAD_START__ + ldr r1, =__BL2_NOLOAD_END__ + sub r1, r1, r0 + bl inv_dcache_range +#endif #endif /* diff -pruN 2.6+dfsg-1/include/arch/aarch64/arch_features.h 2.7.0+dfsg-2/include/arch/aarch64/arch_features.h --- 2.6+dfsg-1/include/arch/aarch64/arch_features.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch64/arch_features.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,6 +46,12 @@ static inline bool is_armv8_3_pauth_pres return (read_id_aa64isar1_el1() & mask) != 0U; } +static inline bool is_armv8_4_dit_present(void) +{ + return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & + ID_AA64PFR0_DIT_MASK) == 1U; +} + static inline bool is_armv8_4_ttst_present(void) { return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) & @@ -134,4 +140,88 @@ static inline unsigned int get_armv9_2_f ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK; } +/********************************************************************************* + * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction) + ********************************************************************************/ +static inline bool is_armv8_0_feat_sb_present(void) +{ + return (((read_id_aa64isar1_el1() >> ID_AA64ISAR1_SB_SHIFT) & + ID_AA64ISAR1_SB_MASK) == ID_AA64ISAR1_SB_SUPPORTED); +} + +/********************************************************************************* + * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) + ********************************************************************************/ +static inline bool is_armv8_0_feat_csv2_2_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_CSV2_SHIFT) & + ID_AA64PFR0_CSV2_MASK) == ID_AA64PFR0_CSV2_2_SUPPORTED); +} + +/********************************************************************************** + * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) + *********************************************************************************/ +static inline bool is_armv8_2_feat_spe_present(void) +{ + return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT) & + ID_AA64DFR0_PMS_MASK) != ID_AA64DFR0_SPE_NOT_SUPPORTED); +} + +/******************************************************************************* + * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) + ******************************************************************************/ +static inline bool is_armv8_2_feat_sve_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT) & + ID_AA64PFR0_SVE_MASK) == ID_AA64PFR0_SVE_SUPPORTED); +} + +/******************************************************************************* + * Function to identify the presence of FEAT_RAS (Reliability,Availability, + * and Serviceability Extension) + ******************************************************************************/ +static inline bool is_armv8_2_feat_ras_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) & + ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED); +} + +/************************************************************************** + * Function to identify the presence of FEAT_DIT (Data Independent Timing) + *************************************************************************/ +static inline bool is_armv8_4_feat_dit_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) & + ID_AA64PFR0_DIT_MASK) == ID_AA64PFR0_DIT_SUPPORTED); +} + +/************************************************************************* + * Function to identify the presence of FEAT_TRF (TraceLift) + ************************************************************************/ +static inline bool is_arm8_4_feat_trf_present(void) +{ + return (((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) & + ID_AA64DFR0_TRACEFILT_MASK) == ID_AA64DFR0_TRACEFILT_SUPPORTED); +} + +/******************************************************************************* + * Function to identify the presence of FEAT_AMUv1 (Activity Monitors- + * Extension v1) + ******************************************************************************/ +static inline bool is_armv8_4_feat_amuv1_present(void) +{ + return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & + ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1); +} + +/******************************************************************************** + * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization + * Support) + *******************************************************************************/ +static inline unsigned int get_armv8_4_feat_nv_support(void) +{ + return (((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) & + ID_AA64MMFR2_EL1_NV_MASK)); +} + #endif /* ARCH_FEATURES_H */ diff -pruN 2.6+dfsg-1/include/arch/aarch64/arch.h 2.7.0+dfsg-2/include/arch/aarch64/arch.h --- 2.6+dfsg-1/include/arch/aarch64/arch.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch64/arch.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,6 +1,6 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -99,7 +99,6 @@ /******************************************************************************* * Definitions for EL2 system registers for save/restore routine ******************************************************************************/ - #define CNTPOFF_EL2 S3_4_C14_C0_6 #define HAFGRTR_EL2 S3_4_C3_C1_6 #define HDFGRTR_EL2 S3_4_C3_C1_4 @@ -109,14 +108,14 @@ #define HFGWTR_EL2 S3_4_C1_C1_5 #define ICH_HCR_EL2 S3_4_C12_C11_0 #define ICH_VMCR_EL2 S3_4_C12_C11_7 -#define MPAMVPM0_EL2 S3_4_C10_C5_0 -#define MPAMVPM1_EL2 S3_4_C10_C5_1 -#define MPAMVPM2_EL2 S3_4_C10_C5_2 -#define MPAMVPM3_EL2 S3_4_C10_C5_3 -#define MPAMVPM4_EL2 S3_4_C10_C5_4 -#define MPAMVPM5_EL2 S3_4_C10_C5_5 -#define MPAMVPM6_EL2 S3_4_C10_C5_6 -#define MPAMVPM7_EL2 S3_4_C10_C5_7 +#define MPAMVPM0_EL2 S3_4_C10_C6_0 +#define MPAMVPM1_EL2 S3_4_C10_C6_1 +#define MPAMVPM2_EL2 S3_4_C10_C6_2 +#define MPAMVPM3_EL2 S3_4_C10_C6_3 +#define MPAMVPM4_EL2 S3_4_C10_C6_4 +#define MPAMVPM5_EL2 S3_4_C10_C6_5 +#define MPAMVPM6_EL2 S3_4_C10_C6_6 +#define MPAMVPM7_EL2 S3_4_C10_C6_7 #define MPAMVPMV_EL2 S3_4_C10_C4_1 #define TRFCR_EL2 S3_4_C1_C2_1 #define PMSCR_EL2 S3_4_C9_C9_0 @@ -155,39 +154,55 @@ #endif /* ID_AA64PFR0_EL1 definitions */ -#define ID_AA64PFR0_EL0_SHIFT U(0) -#define ID_AA64PFR0_EL1_SHIFT U(4) -#define ID_AA64PFR0_EL2_SHIFT U(8) -#define ID_AA64PFR0_EL3_SHIFT U(12) -#define ID_AA64PFR0_AMU_SHIFT U(44) -#define ID_AA64PFR0_AMU_MASK ULL(0xf) -#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) -#define ID_AA64PFR0_AMU_V1 U(0x1) -#define ID_AA64PFR0_AMU_V1P1 U(0x2) -#define ID_AA64PFR0_ELX_MASK ULL(0xf) -#define ID_AA64PFR0_GIC_SHIFT U(24) -#define ID_AA64PFR0_GIC_WIDTH U(4) -#define ID_AA64PFR0_GIC_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_SHIFT U(32) -#define ID_AA64PFR0_SVE_MASK ULL(0xf) -#define ID_AA64PFR0_SVE_LENGTH U(4) -#define ID_AA64PFR0_SEL2_SHIFT U(36) -#define ID_AA64PFR0_SEL2_MASK ULL(0xf) -#define ID_AA64PFR0_MPAM_SHIFT U(40) -#define ID_AA64PFR0_MPAM_MASK ULL(0xf) -#define ID_AA64PFR0_DIT_SHIFT U(48) -#define ID_AA64PFR0_DIT_MASK ULL(0xf) -#define ID_AA64PFR0_DIT_LENGTH U(4) -#define ID_AA64PFR0_DIT_SUPPORTED U(1) -#define ID_AA64PFR0_CSV2_SHIFT U(56) -#define ID_AA64PFR0_CSV2_MASK ULL(0xf) -#define ID_AA64PFR0_CSV2_LENGTH U(4) +#define ID_AA64PFR0_EL0_SHIFT U(0) +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_EL2_SHIFT U(8) +#define ID_AA64PFR0_EL3_SHIFT U(12) + +#define ID_AA64PFR0_AMU_SHIFT U(44) +#define ID_AA64PFR0_AMU_MASK ULL(0xf) +#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) +#define ID_AA64PFR0_AMU_V1 ULL(0x1) +#define ID_AA64PFR0_AMU_V1P1 U(0x2) + +#define ID_AA64PFR0_ELX_MASK ULL(0xf) + +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ULL(0xf) + +#define ID_AA64PFR0_SVE_SHIFT U(32) +#define ID_AA64PFR0_SVE_MASK ULL(0xf) +#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) +#define ID_AA64PFR0_SVE_LENGTH U(4) + +#define ID_AA64PFR0_SEL2_SHIFT U(36) +#define ID_AA64PFR0_SEL2_MASK ULL(0xf) + +#define ID_AA64PFR0_MPAM_SHIFT U(40) +#define ID_AA64PFR0_MPAM_MASK ULL(0xf) + +#define ID_AA64PFR0_DIT_SHIFT U(48) +#define ID_AA64PFR0_DIT_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_LENGTH U(4) +#define ID_AA64PFR0_DIT_SUPPORTED U(1) + +#define ID_AA64PFR0_CSV2_SHIFT U(56) +#define ID_AA64PFR0_CSV2_MASK ULL(0xf) +#define ID_AA64PFR0_CSV2_LENGTH U(4) +#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) + #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) #define ID_AA64PFR0_FEAT_RME_V1 U(1) +#define ID_AA64PFR0_RAS_SHIFT U(28) +#define ID_AA64PFR0_RAS_MASK ULL(0xf) +#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) +#define ID_AA64PFR0_RAS_LENGTH U(4) + /* Exception level handling */ #define EL_IMPL_NONE ULL(0) #define EL_IMPL_A64ONLY ULL(1) @@ -204,8 +219,10 @@ #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ -#define ID_AA64DFR0_PMS_SHIFT U(32) -#define ID_AA64DFR0_PMS_MASK ULL(0xf) +#define ID_AA64DFR0_PMS_SHIFT U(32) +#define ID_AA64DFR0_PMS_MASK ULL(0xf) +#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) +#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) /* ID_AA64DFR0_EL1.TraceBuffer definitions */ #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) @@ -217,20 +234,32 @@ #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) +/* ID_AA64DFR0_EL1.BRBE definitions */ +#define ID_AA64DFR0_BRBE_SHIFT U(52) +#define ID_AA64DFR0_BRBE_MASK ULL(0xf) +#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) + /* ID_AA64ISAR0_EL1 definitions */ #define ID_AA64ISAR0_RNDR_SHIFT U(60) #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) /* ID_AA64ISAR1_EL1 definitions */ -#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 -#define ID_AA64ISAR1_GPI_SHIFT U(28) -#define ID_AA64ISAR1_GPI_MASK ULL(0xf) -#define ID_AA64ISAR1_GPA_SHIFT U(24) -#define ID_AA64ISAR1_GPA_MASK ULL(0xf) -#define ID_AA64ISAR1_API_SHIFT U(8) -#define ID_AA64ISAR1_API_MASK ULL(0xf) -#define ID_AA64ISAR1_APA_SHIFT U(4) -#define ID_AA64ISAR1_APA_MASK ULL(0xf) +#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 + +#define ID_AA64ISAR1_GPI_SHIFT U(28) +#define ID_AA64ISAR1_GPI_MASK ULL(0xf) +#define ID_AA64ISAR1_GPA_SHIFT U(24) +#define ID_AA64ISAR1_GPA_MASK ULL(0xf) + +#define ID_AA64ISAR1_API_SHIFT U(8) +#define ID_AA64ISAR1_API_MASK ULL(0xf) +#define ID_AA64ISAR1_APA_SHIFT U(4) +#define ID_AA64ISAR1_APA_MASK ULL(0xf) + +#define ID_AA64ISAR1_SB_SHIFT U(36) +#define ID_AA64ISAR1_SB_MASK ULL(0xf) +#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) +#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) /* ID_AA64MMFR0_EL1 definitions */ #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) @@ -292,13 +321,23 @@ #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) /* ID_AA64MMFR2_EL1 definitions */ -#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 -#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) -#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_ST_SHIFT U(28) +#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) -#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) -#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) +#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) + +#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) +#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) + +#define ID_AA64MMFR2_EL1_NV_SHIFT U(24) +#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) +#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) +#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) /* ID_AA64PFR1_EL1 definitions */ #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) @@ -449,7 +488,8 @@ #define SCR_HXEn_BIT (UL(1) << 38) #define SCR_ENTP2_SHIFT U(41) #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) -#define SCR_AMVOFFEN_BIT (UL(1) << 35) +#define SCR_AMVOFFEN_SHIFT U(35) +#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) #define SCR_TWEDEn_BIT (UL(1) << 29) #define SCR_ECVEN_BIT (UL(1) << 28) #define SCR_FGTEN_BIT (UL(1) << 27) @@ -478,6 +518,8 @@ #define MDCR_EnPMSN_BIT (ULL(1) << 36) #define MDCR_MPMX_BIT (ULL(1) << 35) #define MDCR_MCCD_BIT (ULL(1) << 34) +#define MDCR_SBRBE_SHIFT U(32) +#define MDCR_SBRBE_MASK ULL(0x3) #define MDCR_NSTB(x) ((x) << 24) #define MDCR_NSTB_EL1 ULL(0x3) #define MDCR_NSTBE (ULL(1) << 26) @@ -1181,7 +1223,8 @@ #define ERXMISC0_EL1 S3_0_C5_C5_0 #define ERXMISC1_EL1 S3_0_C5_C5_1 -#define ERXCTLR_ED_BIT (U(1) << 0) +#define ERXCTLR_ED_SHIFT U(0) +#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) #define ERXCTLR_UE_BIT (U(1) << 4) #define ERXPFGCTL_UC_BIT (U(1) << 1) diff -pruN 2.6+dfsg-1/include/arch/aarch64/arch_helpers.h 2.7.0+dfsg-2/include/arch/aarch64/arch_helpers.h --- 2.6+dfsg-1/include/arch/aarch64/arch_helpers.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch64/arch_helpers.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,6 +224,7 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) DEFINE_SYSOP_PARAM_FUNC(xpaci) void flush_dcache_range(uintptr_t addr, size_t size); +void flush_dcache_to_popa_range(uintptr_t addr, size_t size); void clean_dcache_range(uintptr_t addr, size_t size); void inv_dcache_range(uintptr_t addr, size_t size); bool is_dcache_enabled(void); @@ -274,8 +275,10 @@ DEFINE_SYSOP_TYPE_FUNC(dmb, sy) DEFINE_SYSOP_TYPE_FUNC(dmb, st) DEFINE_SYSOP_TYPE_FUNC(dmb, ld) DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dsb, osh) DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) +DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) DEFINE_SYSOP_TYPE_FUNC(dmb, osh) @@ -529,6 +532,9 @@ DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mm DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) +/* Armv8.4 Data Independent Timing Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) + /* Armv8.5 MTE Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) @@ -607,14 +613,13 @@ static inline void tlbipaallos(void) } /* - * Invalidate cached copies of GPT entries - * from TLBs by physical address + * Invalidate TLBs of GPT entries by Physical address, last level. * * @pa: the starting address for the range * of invalidation * @size: size of the range of invalidation */ -void gpt_tlbi_by_pa(uint64_t pa, size_t size); +void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size); /* Previously defined accessor functions with incomplete register names */ diff -pruN 2.6+dfsg-1/include/arch/aarch64/el3_common_macros.S 2.7.0+dfsg-2/include/arch/aarch64/el3_common_macros.S --- 2.6+dfsg-1/include/arch/aarch64/el3_common_macros.S 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/arch/aarch64/el3_common_macros.S 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -237,15 +238,20 @@ /* * If Data Independent Timing (DIT) functionality is implemented, - * always enable DIT in EL3 + * always enable DIT in EL3. + * First assert that the FEAT_DIT build flag matches the feature id + * register value for DIT. */ +#if ENABLE_FEAT_DIT +#if ENABLE_ASSERTIONS mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH cmp x0, #ID_AA64PFR0_DIT_SUPPORTED - bne 1f + ASM_ASSERT(eq) +#endif /* ENABLE_ASSERTIONS */ mov x0, #DIT_BIT msr DIT, x0 -1: +#endif .endm /* ----------------------------------------------------------------------------- @@ -463,6 +469,14 @@ sub x1, x1, x0 bl inv_dcache_range #endif +#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION + adrp x0, __BL2_NOLOAD_START__ + add x0, x0, :lo12:__BL2_NOLOAD_START__ + adrp x1, __BL2_NOLOAD_END__ + add x1, x1, :lo12:__BL2_NOLOAD_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif #endif adrp x0, __BSS_START__ add x0, x0, :lo12:__BSS_START__ diff -pruN 2.6+dfsg-1/include/bl32/tsp/tsp.h 2.7.0+dfsg-2/include/bl32/tsp/tsp.h --- 2.6+dfsg-1/include/bl32/tsp/tsp.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/bl32/tsp/tsp.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,6 +41,7 @@ #define TSP_MUL 0x2002 #define TSP_DIV 0x2003 #define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004 +#define TSP_CHECK_DIT 0x2005 /* * Identify a TSP service from function ID filtering the last 16 bits from the diff -pruN 2.6+dfsg-1/include/common/bl_common.h 2.7.0+dfsg-2/include/common/bl_common.h --- 2.6+dfsg-1/include/common/bl_common.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/bl_common.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -81,6 +81,10 @@ #define __RODATA_END__ Load$$__RODATA_EPILOGUE__$$Base #define __RT_SVC_DESCS_START__ Load$$__RT_SVC_DESCS__$$Base #define __RT_SVC_DESCS_END__ Load$$__RT_SVC_DESCS__$$Limit +#if SPMC_AT_EL3 +#define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base +#define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit +#endif #define __RW_START__ Load$$LR$$LR_RW_DATA$$Base #define __RW_END__ Load$$LR$$LR_END$$Base #define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base diff -pruN 2.6+dfsg-1/include/common/bl_common.ld.h 2.7.0+dfsg-2/include/common/bl_common.ld.h --- 2.6+dfsg-1/include/common/bl_common.ld.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/bl_common.ld.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,6 +39,16 @@ KEEP(*(rt_svc_descs)) \ __RT_SVC_DESCS_END__ = .; +#if SPMC_AT_EL3 +#define EL3_LP_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __EL3_LP_DESCS_START__ = .; \ + KEEP(*(el3_lp_descs)) \ + __EL3_LP_DESCS_END__ = .; +#else +#define EL3_LP_DESCS +#endif + #define PMF_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __PMF_SVC_DESCS_START__ = .; \ @@ -70,7 +80,9 @@ */ #define BASE_XLAT_TABLE \ . = ALIGN(16); \ - *(base_xlat_table) + __BASE_XLAT_TABLE_START__ = .; \ + *(base_xlat_table) \ + __BASE_XLAT_TABLE_END__ = .; #if PLAT_RO_XLAT_TABLES #define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE @@ -87,7 +99,8 @@ PARSER_LIB_DESCS \ CPU_OPS \ GOT \ - BASE_XLAT_TABLE_RO + BASE_XLAT_TABLE_RO \ + EL3_LP_DESCS /* * .data must be placed at a lower address than the stacks if the stack @@ -210,7 +223,9 @@ */ #define XLAT_TABLE_SECTION \ xlat_table (NOLOAD) : { \ + __XLAT_TABLE_START__ = .; \ *(xlat_table) \ + __XLAT_TABLE_END__ = .; \ } #endif /* BL_COMMON_LD_H */ diff -pruN 2.6+dfsg-1/include/common/fdt_fixup.h 2.7.0+dfsg-2/include/common/fdt_fixup.h --- 2.6+dfsg-1/include/common/fdt_fixup.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/fdt_fixup.h 2022-06-01 15:02:46.000000000 +0000 @@ -7,14 +7,29 @@ #ifndef FDT_FIXUP_H #define FDT_FIXUP_H +#include +#include +#include + #define INVALID_BASE_ADDR ((uintptr_t)~0UL) +struct psci_cpu_idle_state { + const char *name; + uint32_t power_state; + bool local_timer_stop; + uint32_t entry_latency_us; + uint32_t exit_latency_us; + uint32_t min_residency_us; + uint32_t wakeup_latency_us; +}; + int dt_add_psci_node(void *fdt); int dt_add_psci_cpu_enable_methods(void *fdt); int fdt_add_reserved_memory(void *dtb, const char *node_name, uintptr_t base, size_t size); int fdt_add_cpus_node(void *dtb, unsigned int afflv0, unsigned int afflv1, unsigned int afflv2); +int fdt_add_cpu_idle_states(void *dtb, const struct psci_cpu_idle_state *state); int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, uintptr_t gicr_base, unsigned int gicr_frame_size); diff -pruN 2.6+dfsg-1/include/common/fdt_wrappers.h 2.7.0+dfsg-2/include/common/fdt_wrappers.h --- 2.6+dfsg-1/include/common/fdt_wrappers.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/fdt_wrappers.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,6 +44,8 @@ uint64_t fdtw_translate_address(const vo int fdtw_for_each_cpu(const void *fdt, int (*callback)(const void *dtb, int node, uintptr_t mpidr)); +int fdtw_find_or_add_subnode(void *fdt, int parentoffset, const char *name); + static inline uint32_t fdt_blob_size(const void *dtb) { const uint32_t *dtb_header = dtb; diff -pruN 2.6+dfsg-1/include/common/feat_detect.h 2.7.0+dfsg-2/include/common/feat_detect.h --- 2.6+dfsg-1/include/common/feat_detect.h 1970-01-01 00:00:00.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/feat_detect.h 2022-06-01 15:02:46.000000000 +0000 @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FEAT_DETECT_H +#define FEAT_DETECT_H + +#include +#include + +/* Function Prototypes */ +void detect_arch_features(void); + +/* Macro Definitions */ +#define FEAT_STATE_1 1 +#define FEAT_STATE_2 2 +#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b)) + +/******************************************************************************* + * Function : feature_panic + * Customised panic module with error logging mechanism to list the feature + * not supported by the PE. + ******************************************************************************/ +static inline void feature_panic(char *feat_name) +{ + ERROR("FEAT_%s not supported by the PE\n", feat_name); + panic(); +} + +#endif /* FEAT_DETECT_H */ diff -pruN 2.6+dfsg-1/include/common/uuid.h 2.7.0+dfsg-2/include/common/uuid.h --- 2.6+dfsg-1/include/common/uuid.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/common/uuid.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,15 +1,18 @@ /* - * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef UUID_H -#define UUID_H +#ifndef UUID_COMMON_H +#define UUID_COMMON_H #define UUID_BYTES_LENGTH 16 #define UUID_STRING_LENGTH 36 int read_uuid(uint8_t *dest, char *uuid); +bool uuid_match(uint32_t *uuid1, uint32_t *uuid2); +void copy_uuid(uint32_t *to_uuid, uint32_t *from_uuid); +bool is_null_uuid(uint32_t *uuid); -#endif /* UUID_H */ +#endif /* UUID_COMMON_H */ diff -pruN 2.6+dfsg-1/include/drivers/allwinner/axp.h 2.7.0+dfsg-2/include/drivers/allwinner/axp.h --- 2.6+dfsg-1/include/drivers/allwinner/axp.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/drivers/allwinner/axp.h 2022-06-01 15:02:46.000000000 +0000 @@ -47,6 +47,13 @@ int axp_clrsetbits(uint8_t reg, uint8_t int axp_check_id(void); void axp_power_off(void); + +#if SUNXI_SETUP_REGULATORS == 1 void axp_setup_regulators(const void *fdt); +#else +static inline void axp_setup_regulators(const void *fdt) +{ +} +#endif #endif /* AXP_H */ diff -pruN 2.6+dfsg-1/include/drivers/arm/gic600ae_fmu.h 2.7.0+dfsg-2/include/drivers/arm/gic600ae_fmu.h --- 2.6+dfsg-1/include/drivers/arm/gic600ae_fmu.h 2021-11-23 13:14:26.000000000 +0000 +++ 2.7.0+dfsg-2/include/drivers/arm/gic600ae_fmu.h 2022-06-01 15:02:46.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,7 @@ /* SMEN constants */ #define FMU_SMEN_BLK_SHIFT U(8) #define FMU_SMEN_SMID_SHIFT U(24) +#define FMU_SMEN_EN_BIT BIT(0) /* Error record IDs */ #define FMU_BLK_GICD U(0) @@ -86,10 +87,10 @@ /* Safety Mechamism limit */ #define FMU_SMID_GICD_MAX U(33) +#define FMU_SMID_PPI_MAX U(12) +#define FMU_SMID_ITS_MAX U(14) #define FMU_SMID_SPICOL_MAX U(5) #define FMU_SMID_WAKERQ_MAX U(2) -#define FMU_SMID_ITS_MAX U(14) -#define FMU_SMID_PPI_MAX U(12) /* MBIST Safety Mechanism ID */ #define GICD_MBIST_REQ_ERROR U(23) @@ -100,12 +101,17 @@ #define ITS_FMU_CLKGATE_ERROR U(14) /* ERRSTATUS bits */ -#define FMU_ERRSTATUS_V_BIT BIT(30) -#define FMU_ERRSTATUS_UE_BIT BIT(29) -#define FMU_ERRSTATUS_OV_BIT BIT(27) -#define FMU_ERRSTATUS_CE_BITS (BIT(25) | BIT(24)) -#define FMU_ERRSTATUS_CLEAR (FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \ - FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS) +#define FMU_ERRSTATUS_BLKID_SHIFT U(32) +#define FMU_ERRSTATUS_BLKID_MASK U(0xFF) +#define FMU_ERRSTATUS_V_BIT BIT(30) +#define FMU_ERRSTATUS_UE_BIT BIT(29) +#define FMU_ERRSTATUS_OV_BIT BIT(27) +#define FMU_ERRSTATUS_CE_BITS (BIT(25) | BIT(24)) +#define FMU_ERRSTATUS_CLEAR (FMU_ERRSTATUS_V_BIT | FMU_ERRSTATUS_UE_BIT | \ + FMU_ERRSTATUS_OV_BIT | FMU_ERRSTATUS_CE_BITS) +#define FMU_ERRSTATUS_IERR_MASK U(0xFF) +#define FMU_ERRSTATUS_IERR_SHIFT U(8) +#define FMU_ERRSTATUS_SERR_MASK U(0xFF) /* PINGCTLR constants */ #define FMU_PINGCTLR_INTDIFF_SHIFT U(16) @@ -137,11 +143,14 @@ void gic_fmu_write_pingnow(uintptr_t bas void gic_fmu_write_smen(uintptr_t base, uint32_t val); void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val); void gic_fmu_write_pingmask(uintptr_t base, uint64_t val); +void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid); void gic600_fmu_init(uint64_t ba